Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cm7.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**************************************************************************//**
lypinator 0:bb348c97df44 2 * @file core_cm7.h
lypinator 0:bb348c97df44 3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
lypinator 0:bb348c97df44 4 * @version V5.0.5
lypinator 0:bb348c97df44 5 * @date 08. January 2018
lypinator 0:bb348c97df44 6 ******************************************************************************/
lypinator 0:bb348c97df44 7 /*
lypinator 0:bb348c97df44 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * SPDX-License-Identifier: Apache-2.0
lypinator 0:bb348c97df44 11 *
lypinator 0:bb348c97df44 12 * Licensed under the Apache License, Version 2.0 (the License); you may
lypinator 0:bb348c97df44 13 * not use this file except in compliance with the License.
lypinator 0:bb348c97df44 14 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 15 *
lypinator 0:bb348c97df44 16 * www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 17 *
lypinator 0:bb348c97df44 18 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
lypinator 0:bb348c97df44 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 21 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 22 * limitations under the License.
lypinator 0:bb348c97df44 23 */
lypinator 0:bb348c97df44 24
lypinator 0:bb348c97df44 25 #if defined ( __ICCARM__ )
lypinator 0:bb348c97df44 26 #pragma system_include /* treat file as system include file for MISRA check */
lypinator 0:bb348c97df44 27 #elif defined (__clang__)
lypinator 0:bb348c97df44 28 #pragma clang system_header /* treat file as system include file */
lypinator 0:bb348c97df44 29 #endif
lypinator 0:bb348c97df44 30
lypinator 0:bb348c97df44 31 #ifndef __CORE_CM7_H_GENERIC
lypinator 0:bb348c97df44 32 #define __CORE_CM7_H_GENERIC
lypinator 0:bb348c97df44 33
lypinator 0:bb348c97df44 34 #include <stdint.h>
lypinator 0:bb348c97df44 35
lypinator 0:bb348c97df44 36 #ifdef __cplusplus
lypinator 0:bb348c97df44 37 extern "C" {
lypinator 0:bb348c97df44 38 #endif
lypinator 0:bb348c97df44 39
lypinator 0:bb348c97df44 40 /**
lypinator 0:bb348c97df44 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
lypinator 0:bb348c97df44 42 CMSIS violates the following MISRA-C:2004 rules:
lypinator 0:bb348c97df44 43
lypinator 0:bb348c97df44 44 \li Required Rule 8.5, object/function definition in header file.<br>
lypinator 0:bb348c97df44 45 Function definitions in header files are used to allow 'inlining'.
lypinator 0:bb348c97df44 46
lypinator 0:bb348c97df44 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
lypinator 0:bb348c97df44 48 Unions are used for effective representation of core registers.
lypinator 0:bb348c97df44 49
lypinator 0:bb348c97df44 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
lypinator 0:bb348c97df44 51 Function-like macros are used to allow more efficient code.
lypinator 0:bb348c97df44 52 */
lypinator 0:bb348c97df44 53
lypinator 0:bb348c97df44 54
lypinator 0:bb348c97df44 55 /*******************************************************************************
lypinator 0:bb348c97df44 56 * CMSIS definitions
lypinator 0:bb348c97df44 57 ******************************************************************************/
lypinator 0:bb348c97df44 58 /**
lypinator 0:bb348c97df44 59 \ingroup Cortex_M7
lypinator 0:bb348c97df44 60 @{
lypinator 0:bb348c97df44 61 */
lypinator 0:bb348c97df44 62
lypinator 0:bb348c97df44 63 #include "cmsis_version.h"
lypinator 0:bb348c97df44 64
lypinator 0:bb348c97df44 65 /* CMSIS CM7 definitions */
lypinator 0:bb348c97df44 66 #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
lypinator 0:bb348c97df44 67 #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
lypinator 0:bb348c97df44 68 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
lypinator 0:bb348c97df44 69 __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
lypinator 0:bb348c97df44 70
lypinator 0:bb348c97df44 71 #define __CORTEX_M (7U) /*!< Cortex-M Core */
lypinator 0:bb348c97df44 72
lypinator 0:bb348c97df44 73 /** __FPU_USED indicates whether an FPU is used or not.
lypinator 0:bb348c97df44 74 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
lypinator 0:bb348c97df44 75 */
lypinator 0:bb348c97df44 76 #if defined ( __CC_ARM )
lypinator 0:bb348c97df44 77 #if defined __TARGET_FPU_VFP
lypinator 0:bb348c97df44 78 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
lypinator 0:bb348c97df44 79 #define __FPU_USED 1U
lypinator 0:bb348c97df44 80 #else
lypinator 0:bb348c97df44 81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 82 #define __FPU_USED 0U
lypinator 0:bb348c97df44 83 #endif
lypinator 0:bb348c97df44 84 #else
lypinator 0:bb348c97df44 85 #define __FPU_USED 0U
lypinator 0:bb348c97df44 86 #endif
lypinator 0:bb348c97df44 87
lypinator 0:bb348c97df44 88 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
lypinator 0:bb348c97df44 89 #if defined __ARM_PCS_VFP
lypinator 0:bb348c97df44 90 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
lypinator 0:bb348c97df44 91 #define __FPU_USED 1U
lypinator 0:bb348c97df44 92 #else
lypinator 0:bb348c97df44 93 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 94 #define __FPU_USED 0U
lypinator 0:bb348c97df44 95 #endif
lypinator 0:bb348c97df44 96 #else
lypinator 0:bb348c97df44 97 #define __FPU_USED 0U
lypinator 0:bb348c97df44 98 #endif
lypinator 0:bb348c97df44 99
lypinator 0:bb348c97df44 100 #elif defined ( __GNUC__ )
lypinator 0:bb348c97df44 101 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
lypinator 0:bb348c97df44 102 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
lypinator 0:bb348c97df44 103 #define __FPU_USED 1U
lypinator 0:bb348c97df44 104 #else
lypinator 0:bb348c97df44 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 106 #define __FPU_USED 0U
lypinator 0:bb348c97df44 107 #endif
lypinator 0:bb348c97df44 108 #else
lypinator 0:bb348c97df44 109 #define __FPU_USED 0U
lypinator 0:bb348c97df44 110 #endif
lypinator 0:bb348c97df44 111
lypinator 0:bb348c97df44 112 #elif defined ( __ICCARM__ )
lypinator 0:bb348c97df44 113 #if defined __ARMVFP__
lypinator 0:bb348c97df44 114 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
lypinator 0:bb348c97df44 115 #define __FPU_USED 1U
lypinator 0:bb348c97df44 116 #else
lypinator 0:bb348c97df44 117 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 118 #define __FPU_USED 0U
lypinator 0:bb348c97df44 119 #endif
lypinator 0:bb348c97df44 120 #else
lypinator 0:bb348c97df44 121 #define __FPU_USED 0U
lypinator 0:bb348c97df44 122 #endif
lypinator 0:bb348c97df44 123
lypinator 0:bb348c97df44 124 #elif defined ( __TI_ARM__ )
lypinator 0:bb348c97df44 125 #if defined __TI_VFP_SUPPORT__
lypinator 0:bb348c97df44 126 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
lypinator 0:bb348c97df44 127 #define __FPU_USED 1U
lypinator 0:bb348c97df44 128 #else
lypinator 0:bb348c97df44 129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 130 #define __FPU_USED 0U
lypinator 0:bb348c97df44 131 #endif
lypinator 0:bb348c97df44 132 #else
lypinator 0:bb348c97df44 133 #define __FPU_USED 0U
lypinator 0:bb348c97df44 134 #endif
lypinator 0:bb348c97df44 135
lypinator 0:bb348c97df44 136 #elif defined ( __TASKING__ )
lypinator 0:bb348c97df44 137 #if defined __FPU_VFP__
lypinator 0:bb348c97df44 138 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
lypinator 0:bb348c97df44 139 #define __FPU_USED 1U
lypinator 0:bb348c97df44 140 #else
lypinator 0:bb348c97df44 141 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 142 #define __FPU_USED 0U
lypinator 0:bb348c97df44 143 #endif
lypinator 0:bb348c97df44 144 #else
lypinator 0:bb348c97df44 145 #define __FPU_USED 0U
lypinator 0:bb348c97df44 146 #endif
lypinator 0:bb348c97df44 147
lypinator 0:bb348c97df44 148 #elif defined ( __CSMC__ )
lypinator 0:bb348c97df44 149 #if ( __CSMC__ & 0x400U)
lypinator 0:bb348c97df44 150 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
lypinator 0:bb348c97df44 151 #define __FPU_USED 1U
lypinator 0:bb348c97df44 152 #else
lypinator 0:bb348c97df44 153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 154 #define __FPU_USED 0U
lypinator 0:bb348c97df44 155 #endif
lypinator 0:bb348c97df44 156 #else
lypinator 0:bb348c97df44 157 #define __FPU_USED 0U
lypinator 0:bb348c97df44 158 #endif
lypinator 0:bb348c97df44 159
lypinator 0:bb348c97df44 160 #endif
lypinator 0:bb348c97df44 161
lypinator 0:bb348c97df44 162 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
lypinator 0:bb348c97df44 163
lypinator 0:bb348c97df44 164
lypinator 0:bb348c97df44 165 #ifdef __cplusplus
lypinator 0:bb348c97df44 166 }
lypinator 0:bb348c97df44 167 #endif
lypinator 0:bb348c97df44 168
lypinator 0:bb348c97df44 169 #endif /* __CORE_CM7_H_GENERIC */
lypinator 0:bb348c97df44 170
lypinator 0:bb348c97df44 171 #ifndef __CMSIS_GENERIC
lypinator 0:bb348c97df44 172
lypinator 0:bb348c97df44 173 #ifndef __CORE_CM7_H_DEPENDANT
lypinator 0:bb348c97df44 174 #define __CORE_CM7_H_DEPENDANT
lypinator 0:bb348c97df44 175
lypinator 0:bb348c97df44 176 #ifdef __cplusplus
lypinator 0:bb348c97df44 177 extern "C" {
lypinator 0:bb348c97df44 178 #endif
lypinator 0:bb348c97df44 179
lypinator 0:bb348c97df44 180 /* check device defines and use defaults */
lypinator 0:bb348c97df44 181 #if defined __CHECK_DEVICE_DEFINES
lypinator 0:bb348c97df44 182 #ifndef __CM7_REV
lypinator 0:bb348c97df44 183 #define __CM7_REV 0x0000U
lypinator 0:bb348c97df44 184 #warning "__CM7_REV not defined in device header file; using default!"
lypinator 0:bb348c97df44 185 #endif
lypinator 0:bb348c97df44 186
lypinator 0:bb348c97df44 187 #ifndef __FPU_PRESENT
lypinator 0:bb348c97df44 188 #define __FPU_PRESENT 0U
lypinator 0:bb348c97df44 189 #warning "__FPU_PRESENT not defined in device header file; using default!"
lypinator 0:bb348c97df44 190 #endif
lypinator 0:bb348c97df44 191
lypinator 0:bb348c97df44 192 #ifndef __MPU_PRESENT
lypinator 0:bb348c97df44 193 #define __MPU_PRESENT 0U
lypinator 0:bb348c97df44 194 #warning "__MPU_PRESENT not defined in device header file; using default!"
lypinator 0:bb348c97df44 195 #endif
lypinator 0:bb348c97df44 196
lypinator 0:bb348c97df44 197 #ifndef __ICACHE_PRESENT
lypinator 0:bb348c97df44 198 #define __ICACHE_PRESENT 0U
lypinator 0:bb348c97df44 199 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
lypinator 0:bb348c97df44 200 #endif
lypinator 0:bb348c97df44 201
lypinator 0:bb348c97df44 202 #ifndef __DCACHE_PRESENT
lypinator 0:bb348c97df44 203 #define __DCACHE_PRESENT 0U
lypinator 0:bb348c97df44 204 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
lypinator 0:bb348c97df44 205 #endif
lypinator 0:bb348c97df44 206
lypinator 0:bb348c97df44 207 #ifndef __DTCM_PRESENT
lypinator 0:bb348c97df44 208 #define __DTCM_PRESENT 0U
lypinator 0:bb348c97df44 209 #warning "__DTCM_PRESENT not defined in device header file; using default!"
lypinator 0:bb348c97df44 210 #endif
lypinator 0:bb348c97df44 211
lypinator 0:bb348c97df44 212 #ifndef __NVIC_PRIO_BITS
lypinator 0:bb348c97df44 213 #define __NVIC_PRIO_BITS 3U
lypinator 0:bb348c97df44 214 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
lypinator 0:bb348c97df44 215 #endif
lypinator 0:bb348c97df44 216
lypinator 0:bb348c97df44 217 #ifndef __Vendor_SysTickConfig
lypinator 0:bb348c97df44 218 #define __Vendor_SysTickConfig 0U
lypinator 0:bb348c97df44 219 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
lypinator 0:bb348c97df44 220 #endif
lypinator 0:bb348c97df44 221 #endif
lypinator 0:bb348c97df44 222
lypinator 0:bb348c97df44 223 /* IO definitions (access restrictions to peripheral registers) */
lypinator 0:bb348c97df44 224 /**
lypinator 0:bb348c97df44 225 \defgroup CMSIS_glob_defs CMSIS Global Defines
lypinator 0:bb348c97df44 226
lypinator 0:bb348c97df44 227 <strong>IO Type Qualifiers</strong> are used
lypinator 0:bb348c97df44 228 \li to specify the access to peripheral variables.
lypinator 0:bb348c97df44 229 \li for automatic generation of peripheral register debug information.
lypinator 0:bb348c97df44 230 */
lypinator 0:bb348c97df44 231 #ifdef __cplusplus
lypinator 0:bb348c97df44 232 #define __I volatile /*!< Defines 'read only' permissions */
lypinator 0:bb348c97df44 233 #else
lypinator 0:bb348c97df44 234 #define __I volatile const /*!< Defines 'read only' permissions */
lypinator 0:bb348c97df44 235 #endif
lypinator 0:bb348c97df44 236 #define __O volatile /*!< Defines 'write only' permissions */
lypinator 0:bb348c97df44 237 #define __IO volatile /*!< Defines 'read / write' permissions */
lypinator 0:bb348c97df44 238
lypinator 0:bb348c97df44 239 /* following defines should be used for structure members */
lypinator 0:bb348c97df44 240 #define __IM volatile const /*! Defines 'read only' structure member permissions */
lypinator 0:bb348c97df44 241 #define __OM volatile /*! Defines 'write only' structure member permissions */
lypinator 0:bb348c97df44 242 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
lypinator 0:bb348c97df44 243
lypinator 0:bb348c97df44 244 /*@} end of group Cortex_M7 */
lypinator 0:bb348c97df44 245
lypinator 0:bb348c97df44 246
lypinator 0:bb348c97df44 247
lypinator 0:bb348c97df44 248 /*******************************************************************************
lypinator 0:bb348c97df44 249 * Register Abstraction
lypinator 0:bb348c97df44 250 Core Register contain:
lypinator 0:bb348c97df44 251 - Core Register
lypinator 0:bb348c97df44 252 - Core NVIC Register
lypinator 0:bb348c97df44 253 - Core SCB Register
lypinator 0:bb348c97df44 254 - Core SysTick Register
lypinator 0:bb348c97df44 255 - Core Debug Register
lypinator 0:bb348c97df44 256 - Core MPU Register
lypinator 0:bb348c97df44 257 - Core FPU Register
lypinator 0:bb348c97df44 258 ******************************************************************************/
lypinator 0:bb348c97df44 259 /**
lypinator 0:bb348c97df44 260 \defgroup CMSIS_core_register Defines and Type Definitions
lypinator 0:bb348c97df44 261 \brief Type definitions and defines for Cortex-M processor based devices.
lypinator 0:bb348c97df44 262 */
lypinator 0:bb348c97df44 263
lypinator 0:bb348c97df44 264 /**
lypinator 0:bb348c97df44 265 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 266 \defgroup CMSIS_CORE Status and Control Registers
lypinator 0:bb348c97df44 267 \brief Core Register type definitions.
lypinator 0:bb348c97df44 268 @{
lypinator 0:bb348c97df44 269 */
lypinator 0:bb348c97df44 270
lypinator 0:bb348c97df44 271 /**
lypinator 0:bb348c97df44 272 \brief Union type to access the Application Program Status Register (APSR).
lypinator 0:bb348c97df44 273 */
lypinator 0:bb348c97df44 274 typedef union
lypinator 0:bb348c97df44 275 {
lypinator 0:bb348c97df44 276 struct
lypinator 0:bb348c97df44 277 {
lypinator 0:bb348c97df44 278 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
lypinator 0:bb348c97df44 279 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
lypinator 0:bb348c97df44 280 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
lypinator 0:bb348c97df44 281 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
lypinator 0:bb348c97df44 282 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
lypinator 0:bb348c97df44 283 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
lypinator 0:bb348c97df44 284 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
lypinator 0:bb348c97df44 285 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
lypinator 0:bb348c97df44 286 } b; /*!< Structure used for bit access */
lypinator 0:bb348c97df44 287 uint32_t w; /*!< Type used for word access */
lypinator 0:bb348c97df44 288 } APSR_Type;
lypinator 0:bb348c97df44 289
lypinator 0:bb348c97df44 290 /* APSR Register Definitions */
lypinator 0:bb348c97df44 291 #define APSR_N_Pos 31U /*!< APSR: N Position */
lypinator 0:bb348c97df44 292 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
lypinator 0:bb348c97df44 293
lypinator 0:bb348c97df44 294 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
lypinator 0:bb348c97df44 295 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
lypinator 0:bb348c97df44 296
lypinator 0:bb348c97df44 297 #define APSR_C_Pos 29U /*!< APSR: C Position */
lypinator 0:bb348c97df44 298 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
lypinator 0:bb348c97df44 299
lypinator 0:bb348c97df44 300 #define APSR_V_Pos 28U /*!< APSR: V Position */
lypinator 0:bb348c97df44 301 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
lypinator 0:bb348c97df44 302
lypinator 0:bb348c97df44 303 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
lypinator 0:bb348c97df44 304 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
lypinator 0:bb348c97df44 305
lypinator 0:bb348c97df44 306 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
lypinator 0:bb348c97df44 307 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
lypinator 0:bb348c97df44 308
lypinator 0:bb348c97df44 309
lypinator 0:bb348c97df44 310 /**
lypinator 0:bb348c97df44 311 \brief Union type to access the Interrupt Program Status Register (IPSR).
lypinator 0:bb348c97df44 312 */
lypinator 0:bb348c97df44 313 typedef union
lypinator 0:bb348c97df44 314 {
lypinator 0:bb348c97df44 315 struct
lypinator 0:bb348c97df44 316 {
lypinator 0:bb348c97df44 317 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
lypinator 0:bb348c97df44 318 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
lypinator 0:bb348c97df44 319 } b; /*!< Structure used for bit access */
lypinator 0:bb348c97df44 320 uint32_t w; /*!< Type used for word access */
lypinator 0:bb348c97df44 321 } IPSR_Type;
lypinator 0:bb348c97df44 322
lypinator 0:bb348c97df44 323 /* IPSR Register Definitions */
lypinator 0:bb348c97df44 324 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
lypinator 0:bb348c97df44 325 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
lypinator 0:bb348c97df44 326
lypinator 0:bb348c97df44 327
lypinator 0:bb348c97df44 328 /**
lypinator 0:bb348c97df44 329 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
lypinator 0:bb348c97df44 330 */
lypinator 0:bb348c97df44 331 typedef union
lypinator 0:bb348c97df44 332 {
lypinator 0:bb348c97df44 333 struct
lypinator 0:bb348c97df44 334 {
lypinator 0:bb348c97df44 335 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
lypinator 0:bb348c97df44 336 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
lypinator 0:bb348c97df44 337 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
lypinator 0:bb348c97df44 338 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
lypinator 0:bb348c97df44 339 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
lypinator 0:bb348c97df44 340 uint32_t T:1; /*!< bit: 24 Thumb bit */
lypinator 0:bb348c97df44 341 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
lypinator 0:bb348c97df44 342 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
lypinator 0:bb348c97df44 343 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
lypinator 0:bb348c97df44 344 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
lypinator 0:bb348c97df44 345 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
lypinator 0:bb348c97df44 346 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
lypinator 0:bb348c97df44 347 } b; /*!< Structure used for bit access */
lypinator 0:bb348c97df44 348 uint32_t w; /*!< Type used for word access */
lypinator 0:bb348c97df44 349 } xPSR_Type;
lypinator 0:bb348c97df44 350
lypinator 0:bb348c97df44 351 /* xPSR Register Definitions */
lypinator 0:bb348c97df44 352 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
lypinator 0:bb348c97df44 353 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
lypinator 0:bb348c97df44 354
lypinator 0:bb348c97df44 355 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
lypinator 0:bb348c97df44 356 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
lypinator 0:bb348c97df44 357
lypinator 0:bb348c97df44 358 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
lypinator 0:bb348c97df44 359 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
lypinator 0:bb348c97df44 360
lypinator 0:bb348c97df44 361 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
lypinator 0:bb348c97df44 362 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
lypinator 0:bb348c97df44 363
lypinator 0:bb348c97df44 364 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
lypinator 0:bb348c97df44 365 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
lypinator 0:bb348c97df44 366
lypinator 0:bb348c97df44 367 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
lypinator 0:bb348c97df44 368 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
lypinator 0:bb348c97df44 369
lypinator 0:bb348c97df44 370 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
lypinator 0:bb348c97df44 371 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
lypinator 0:bb348c97df44 372
lypinator 0:bb348c97df44 373 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
lypinator 0:bb348c97df44 374 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
lypinator 0:bb348c97df44 375
lypinator 0:bb348c97df44 376 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
lypinator 0:bb348c97df44 377 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
lypinator 0:bb348c97df44 378
lypinator 0:bb348c97df44 379 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
lypinator 0:bb348c97df44 380 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
lypinator 0:bb348c97df44 381
lypinator 0:bb348c97df44 382
lypinator 0:bb348c97df44 383 /**
lypinator 0:bb348c97df44 384 \brief Union type to access the Control Registers (CONTROL).
lypinator 0:bb348c97df44 385 */
lypinator 0:bb348c97df44 386 typedef union
lypinator 0:bb348c97df44 387 {
lypinator 0:bb348c97df44 388 struct
lypinator 0:bb348c97df44 389 {
lypinator 0:bb348c97df44 390 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
lypinator 0:bb348c97df44 391 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
lypinator 0:bb348c97df44 392 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
lypinator 0:bb348c97df44 393 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
lypinator 0:bb348c97df44 394 } b; /*!< Structure used for bit access */
lypinator 0:bb348c97df44 395 uint32_t w; /*!< Type used for word access */
lypinator 0:bb348c97df44 396 } CONTROL_Type;
lypinator 0:bb348c97df44 397
lypinator 0:bb348c97df44 398 /* CONTROL Register Definitions */
lypinator 0:bb348c97df44 399 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
lypinator 0:bb348c97df44 400 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
lypinator 0:bb348c97df44 401
lypinator 0:bb348c97df44 402 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
lypinator 0:bb348c97df44 403 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
lypinator 0:bb348c97df44 404
lypinator 0:bb348c97df44 405 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
lypinator 0:bb348c97df44 406 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
lypinator 0:bb348c97df44 407
lypinator 0:bb348c97df44 408 /*@} end of group CMSIS_CORE */
lypinator 0:bb348c97df44 409
lypinator 0:bb348c97df44 410
lypinator 0:bb348c97df44 411 /**
lypinator 0:bb348c97df44 412 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 413 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
lypinator 0:bb348c97df44 414 \brief Type definitions for the NVIC Registers
lypinator 0:bb348c97df44 415 @{
lypinator 0:bb348c97df44 416 */
lypinator 0:bb348c97df44 417
lypinator 0:bb348c97df44 418 /**
lypinator 0:bb348c97df44 419 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
lypinator 0:bb348c97df44 420 */
lypinator 0:bb348c97df44 421 typedef struct
lypinator 0:bb348c97df44 422 {
lypinator 0:bb348c97df44 423 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
lypinator 0:bb348c97df44 424 uint32_t RESERVED0[24U];
lypinator 0:bb348c97df44 425 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
lypinator 0:bb348c97df44 426 uint32_t RSERVED1[24U];
lypinator 0:bb348c97df44 427 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
lypinator 0:bb348c97df44 428 uint32_t RESERVED2[24U];
lypinator 0:bb348c97df44 429 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
lypinator 0:bb348c97df44 430 uint32_t RESERVED3[24U];
lypinator 0:bb348c97df44 431 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
lypinator 0:bb348c97df44 432 uint32_t RESERVED4[56U];
lypinator 0:bb348c97df44 433 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
lypinator 0:bb348c97df44 434 uint32_t RESERVED5[644U];
lypinator 0:bb348c97df44 435 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
lypinator 0:bb348c97df44 436 } NVIC_Type;
lypinator 0:bb348c97df44 437
lypinator 0:bb348c97df44 438 /* Software Triggered Interrupt Register Definitions */
lypinator 0:bb348c97df44 439 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
lypinator 0:bb348c97df44 440 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
lypinator 0:bb348c97df44 441
lypinator 0:bb348c97df44 442 /*@} end of group CMSIS_NVIC */
lypinator 0:bb348c97df44 443
lypinator 0:bb348c97df44 444
lypinator 0:bb348c97df44 445 /**
lypinator 0:bb348c97df44 446 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 447 \defgroup CMSIS_SCB System Control Block (SCB)
lypinator 0:bb348c97df44 448 \brief Type definitions for the System Control Block Registers
lypinator 0:bb348c97df44 449 @{
lypinator 0:bb348c97df44 450 */
lypinator 0:bb348c97df44 451
lypinator 0:bb348c97df44 452 /**
lypinator 0:bb348c97df44 453 \brief Structure type to access the System Control Block (SCB).
lypinator 0:bb348c97df44 454 */
lypinator 0:bb348c97df44 455 typedef struct
lypinator 0:bb348c97df44 456 {
lypinator 0:bb348c97df44 457 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
lypinator 0:bb348c97df44 458 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
lypinator 0:bb348c97df44 459 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
lypinator 0:bb348c97df44 460 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
lypinator 0:bb348c97df44 461 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
lypinator 0:bb348c97df44 462 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
lypinator 0:bb348c97df44 463 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
lypinator 0:bb348c97df44 464 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
lypinator 0:bb348c97df44 465 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
lypinator 0:bb348c97df44 466 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
lypinator 0:bb348c97df44 467 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
lypinator 0:bb348c97df44 468 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
lypinator 0:bb348c97df44 469 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
lypinator 0:bb348c97df44 470 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
lypinator 0:bb348c97df44 471 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
lypinator 0:bb348c97df44 472 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
lypinator 0:bb348c97df44 473 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
lypinator 0:bb348c97df44 474 __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
lypinator 0:bb348c97df44 475 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
lypinator 0:bb348c97df44 476 uint32_t RESERVED0[1U];
lypinator 0:bb348c97df44 477 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
lypinator 0:bb348c97df44 478 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
lypinator 0:bb348c97df44 479 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
lypinator 0:bb348c97df44 480 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
lypinator 0:bb348c97df44 481 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
lypinator 0:bb348c97df44 482 uint32_t RESERVED3[93U];
lypinator 0:bb348c97df44 483 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
lypinator 0:bb348c97df44 484 uint32_t RESERVED4[15U];
lypinator 0:bb348c97df44 485 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
lypinator 0:bb348c97df44 486 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
lypinator 0:bb348c97df44 487 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
lypinator 0:bb348c97df44 488 uint32_t RESERVED5[1U];
lypinator 0:bb348c97df44 489 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
lypinator 0:bb348c97df44 490 uint32_t RESERVED6[1U];
lypinator 0:bb348c97df44 491 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
lypinator 0:bb348c97df44 492 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
lypinator 0:bb348c97df44 493 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
lypinator 0:bb348c97df44 494 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
lypinator 0:bb348c97df44 495 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
lypinator 0:bb348c97df44 496 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
lypinator 0:bb348c97df44 497 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
lypinator 0:bb348c97df44 498 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
lypinator 0:bb348c97df44 499 uint32_t RESERVED7[6U];
lypinator 0:bb348c97df44 500 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
lypinator 0:bb348c97df44 501 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
lypinator 0:bb348c97df44 502 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
lypinator 0:bb348c97df44 503 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
lypinator 0:bb348c97df44 504 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
lypinator 0:bb348c97df44 505 uint32_t RESERVED8[1U];
lypinator 0:bb348c97df44 506 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
lypinator 0:bb348c97df44 507 } SCB_Type;
lypinator 0:bb348c97df44 508
lypinator 0:bb348c97df44 509 /* SCB CPUID Register Definitions */
lypinator 0:bb348c97df44 510 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
lypinator 0:bb348c97df44 511 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
lypinator 0:bb348c97df44 512
lypinator 0:bb348c97df44 513 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
lypinator 0:bb348c97df44 514 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
lypinator 0:bb348c97df44 515
lypinator 0:bb348c97df44 516 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
lypinator 0:bb348c97df44 517 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
lypinator 0:bb348c97df44 518
lypinator 0:bb348c97df44 519 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
lypinator 0:bb348c97df44 520 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
lypinator 0:bb348c97df44 521
lypinator 0:bb348c97df44 522 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
lypinator 0:bb348c97df44 523 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
lypinator 0:bb348c97df44 524
lypinator 0:bb348c97df44 525 /* SCB Interrupt Control State Register Definitions */
lypinator 0:bb348c97df44 526 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
lypinator 0:bb348c97df44 527 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
lypinator 0:bb348c97df44 528
lypinator 0:bb348c97df44 529 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
lypinator 0:bb348c97df44 530 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
lypinator 0:bb348c97df44 531
lypinator 0:bb348c97df44 532 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
lypinator 0:bb348c97df44 533 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
lypinator 0:bb348c97df44 534
lypinator 0:bb348c97df44 535 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
lypinator 0:bb348c97df44 536 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
lypinator 0:bb348c97df44 537
lypinator 0:bb348c97df44 538 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
lypinator 0:bb348c97df44 539 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
lypinator 0:bb348c97df44 540
lypinator 0:bb348c97df44 541 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
lypinator 0:bb348c97df44 542 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
lypinator 0:bb348c97df44 543
lypinator 0:bb348c97df44 544 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
lypinator 0:bb348c97df44 545 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
lypinator 0:bb348c97df44 546
lypinator 0:bb348c97df44 547 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
lypinator 0:bb348c97df44 548 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
lypinator 0:bb348c97df44 549
lypinator 0:bb348c97df44 550 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
lypinator 0:bb348c97df44 551 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
lypinator 0:bb348c97df44 552
lypinator 0:bb348c97df44 553 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
lypinator 0:bb348c97df44 554 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
lypinator 0:bb348c97df44 555
lypinator 0:bb348c97df44 556 /* SCB Vector Table Offset Register Definitions */
lypinator 0:bb348c97df44 557 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
lypinator 0:bb348c97df44 558 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
lypinator 0:bb348c97df44 559
lypinator 0:bb348c97df44 560 /* SCB Application Interrupt and Reset Control Register Definitions */
lypinator 0:bb348c97df44 561 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
lypinator 0:bb348c97df44 562 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
lypinator 0:bb348c97df44 563
lypinator 0:bb348c97df44 564 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
lypinator 0:bb348c97df44 565 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
lypinator 0:bb348c97df44 566
lypinator 0:bb348c97df44 567 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
lypinator 0:bb348c97df44 568 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
lypinator 0:bb348c97df44 569
lypinator 0:bb348c97df44 570 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
lypinator 0:bb348c97df44 571 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
lypinator 0:bb348c97df44 572
lypinator 0:bb348c97df44 573 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
lypinator 0:bb348c97df44 574 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
lypinator 0:bb348c97df44 575
lypinator 0:bb348c97df44 576 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
lypinator 0:bb348c97df44 577 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
lypinator 0:bb348c97df44 578
lypinator 0:bb348c97df44 579 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
lypinator 0:bb348c97df44 580 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
lypinator 0:bb348c97df44 581
lypinator 0:bb348c97df44 582 /* SCB System Control Register Definitions */
lypinator 0:bb348c97df44 583 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
lypinator 0:bb348c97df44 584 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
lypinator 0:bb348c97df44 585
lypinator 0:bb348c97df44 586 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
lypinator 0:bb348c97df44 587 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
lypinator 0:bb348c97df44 588
lypinator 0:bb348c97df44 589 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
lypinator 0:bb348c97df44 590 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
lypinator 0:bb348c97df44 591
lypinator 0:bb348c97df44 592 /* SCB Configuration Control Register Definitions */
lypinator 0:bb348c97df44 593 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
lypinator 0:bb348c97df44 594 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
lypinator 0:bb348c97df44 595
lypinator 0:bb348c97df44 596 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
lypinator 0:bb348c97df44 597 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
lypinator 0:bb348c97df44 598
lypinator 0:bb348c97df44 599 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
lypinator 0:bb348c97df44 600 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
lypinator 0:bb348c97df44 601
lypinator 0:bb348c97df44 602 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
lypinator 0:bb348c97df44 603 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
lypinator 0:bb348c97df44 604
lypinator 0:bb348c97df44 605 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
lypinator 0:bb348c97df44 606 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
lypinator 0:bb348c97df44 607
lypinator 0:bb348c97df44 608 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
lypinator 0:bb348c97df44 609 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
lypinator 0:bb348c97df44 610
lypinator 0:bb348c97df44 611 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
lypinator 0:bb348c97df44 612 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
lypinator 0:bb348c97df44 613
lypinator 0:bb348c97df44 614 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
lypinator 0:bb348c97df44 615 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
lypinator 0:bb348c97df44 616
lypinator 0:bb348c97df44 617 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
lypinator 0:bb348c97df44 618 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
lypinator 0:bb348c97df44 619
lypinator 0:bb348c97df44 620 /* SCB System Handler Control and State Register Definitions */
lypinator 0:bb348c97df44 621 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
lypinator 0:bb348c97df44 622 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
lypinator 0:bb348c97df44 623
lypinator 0:bb348c97df44 624 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
lypinator 0:bb348c97df44 625 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
lypinator 0:bb348c97df44 626
lypinator 0:bb348c97df44 627 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
lypinator 0:bb348c97df44 628 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
lypinator 0:bb348c97df44 629
lypinator 0:bb348c97df44 630 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
lypinator 0:bb348c97df44 631 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
lypinator 0:bb348c97df44 632
lypinator 0:bb348c97df44 633 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
lypinator 0:bb348c97df44 634 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
lypinator 0:bb348c97df44 635
lypinator 0:bb348c97df44 636 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
lypinator 0:bb348c97df44 637 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
lypinator 0:bb348c97df44 638
lypinator 0:bb348c97df44 639 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
lypinator 0:bb348c97df44 640 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
lypinator 0:bb348c97df44 641
lypinator 0:bb348c97df44 642 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
lypinator 0:bb348c97df44 643 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
lypinator 0:bb348c97df44 644
lypinator 0:bb348c97df44 645 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
lypinator 0:bb348c97df44 646 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
lypinator 0:bb348c97df44 647
lypinator 0:bb348c97df44 648 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
lypinator 0:bb348c97df44 649 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
lypinator 0:bb348c97df44 650
lypinator 0:bb348c97df44 651 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
lypinator 0:bb348c97df44 652 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
lypinator 0:bb348c97df44 653
lypinator 0:bb348c97df44 654 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
lypinator 0:bb348c97df44 655 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
lypinator 0:bb348c97df44 656
lypinator 0:bb348c97df44 657 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
lypinator 0:bb348c97df44 658 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
lypinator 0:bb348c97df44 659
lypinator 0:bb348c97df44 660 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
lypinator 0:bb348c97df44 661 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
lypinator 0:bb348c97df44 662
lypinator 0:bb348c97df44 663 /* SCB Configurable Fault Status Register Definitions */
lypinator 0:bb348c97df44 664 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
lypinator 0:bb348c97df44 665 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
lypinator 0:bb348c97df44 666
lypinator 0:bb348c97df44 667 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
lypinator 0:bb348c97df44 668 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
lypinator 0:bb348c97df44 669
lypinator 0:bb348c97df44 670 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
lypinator 0:bb348c97df44 671 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
lypinator 0:bb348c97df44 672
lypinator 0:bb348c97df44 673 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
lypinator 0:bb348c97df44 674 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
lypinator 0:bb348c97df44 675 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
lypinator 0:bb348c97df44 676
lypinator 0:bb348c97df44 677 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
lypinator 0:bb348c97df44 678 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
lypinator 0:bb348c97df44 679
lypinator 0:bb348c97df44 680 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
lypinator 0:bb348c97df44 681 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
lypinator 0:bb348c97df44 682
lypinator 0:bb348c97df44 683 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
lypinator 0:bb348c97df44 684 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
lypinator 0:bb348c97df44 685
lypinator 0:bb348c97df44 686 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
lypinator 0:bb348c97df44 687 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
lypinator 0:bb348c97df44 688
lypinator 0:bb348c97df44 689 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
lypinator 0:bb348c97df44 690 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
lypinator 0:bb348c97df44 691
lypinator 0:bb348c97df44 692 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
lypinator 0:bb348c97df44 693 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
lypinator 0:bb348c97df44 694 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
lypinator 0:bb348c97df44 695
lypinator 0:bb348c97df44 696 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
lypinator 0:bb348c97df44 697 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
lypinator 0:bb348c97df44 698
lypinator 0:bb348c97df44 699 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
lypinator 0:bb348c97df44 700 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
lypinator 0:bb348c97df44 701
lypinator 0:bb348c97df44 702 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
lypinator 0:bb348c97df44 703 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
lypinator 0:bb348c97df44 704
lypinator 0:bb348c97df44 705 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
lypinator 0:bb348c97df44 706 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
lypinator 0:bb348c97df44 707
lypinator 0:bb348c97df44 708 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
lypinator 0:bb348c97df44 709 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
lypinator 0:bb348c97df44 710
lypinator 0:bb348c97df44 711 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
lypinator 0:bb348c97df44 712 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
lypinator 0:bb348c97df44 713
lypinator 0:bb348c97df44 714 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
lypinator 0:bb348c97df44 715 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
lypinator 0:bb348c97df44 716 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
lypinator 0:bb348c97df44 717
lypinator 0:bb348c97df44 718 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
lypinator 0:bb348c97df44 719 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
lypinator 0:bb348c97df44 720
lypinator 0:bb348c97df44 721 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
lypinator 0:bb348c97df44 722 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
lypinator 0:bb348c97df44 723
lypinator 0:bb348c97df44 724 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
lypinator 0:bb348c97df44 725 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
lypinator 0:bb348c97df44 726
lypinator 0:bb348c97df44 727 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
lypinator 0:bb348c97df44 728 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
lypinator 0:bb348c97df44 729
lypinator 0:bb348c97df44 730 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
lypinator 0:bb348c97df44 731 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
lypinator 0:bb348c97df44 732
lypinator 0:bb348c97df44 733 /* SCB Hard Fault Status Register Definitions */
lypinator 0:bb348c97df44 734 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
lypinator 0:bb348c97df44 735 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
lypinator 0:bb348c97df44 736
lypinator 0:bb348c97df44 737 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
lypinator 0:bb348c97df44 738 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
lypinator 0:bb348c97df44 739
lypinator 0:bb348c97df44 740 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
lypinator 0:bb348c97df44 741 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
lypinator 0:bb348c97df44 742
lypinator 0:bb348c97df44 743 /* SCB Debug Fault Status Register Definitions */
lypinator 0:bb348c97df44 744 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
lypinator 0:bb348c97df44 745 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
lypinator 0:bb348c97df44 746
lypinator 0:bb348c97df44 747 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
lypinator 0:bb348c97df44 748 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
lypinator 0:bb348c97df44 749
lypinator 0:bb348c97df44 750 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
lypinator 0:bb348c97df44 751 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
lypinator 0:bb348c97df44 752
lypinator 0:bb348c97df44 753 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
lypinator 0:bb348c97df44 754 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
lypinator 0:bb348c97df44 755
lypinator 0:bb348c97df44 756 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
lypinator 0:bb348c97df44 757 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
lypinator 0:bb348c97df44 758
lypinator 0:bb348c97df44 759 /* SCB Cache Level ID Register Definitions */
lypinator 0:bb348c97df44 760 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
lypinator 0:bb348c97df44 761 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
lypinator 0:bb348c97df44 762
lypinator 0:bb348c97df44 763 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
lypinator 0:bb348c97df44 764 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
lypinator 0:bb348c97df44 765
lypinator 0:bb348c97df44 766 /* SCB Cache Type Register Definitions */
lypinator 0:bb348c97df44 767 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
lypinator 0:bb348c97df44 768 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
lypinator 0:bb348c97df44 769
lypinator 0:bb348c97df44 770 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
lypinator 0:bb348c97df44 771 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
lypinator 0:bb348c97df44 772
lypinator 0:bb348c97df44 773 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
lypinator 0:bb348c97df44 774 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
lypinator 0:bb348c97df44 775
lypinator 0:bb348c97df44 776 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
lypinator 0:bb348c97df44 777 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
lypinator 0:bb348c97df44 778
lypinator 0:bb348c97df44 779 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
lypinator 0:bb348c97df44 780 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
lypinator 0:bb348c97df44 781
lypinator 0:bb348c97df44 782 /* SCB Cache Size ID Register Definitions */
lypinator 0:bb348c97df44 783 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
lypinator 0:bb348c97df44 784 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
lypinator 0:bb348c97df44 785
lypinator 0:bb348c97df44 786 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
lypinator 0:bb348c97df44 787 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
lypinator 0:bb348c97df44 788
lypinator 0:bb348c97df44 789 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
lypinator 0:bb348c97df44 790 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
lypinator 0:bb348c97df44 791
lypinator 0:bb348c97df44 792 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
lypinator 0:bb348c97df44 793 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
lypinator 0:bb348c97df44 794
lypinator 0:bb348c97df44 795 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
lypinator 0:bb348c97df44 796 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
lypinator 0:bb348c97df44 797
lypinator 0:bb348c97df44 798 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
lypinator 0:bb348c97df44 799 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
lypinator 0:bb348c97df44 800
lypinator 0:bb348c97df44 801 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
lypinator 0:bb348c97df44 802 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
lypinator 0:bb348c97df44 803
lypinator 0:bb348c97df44 804 /* SCB Cache Size Selection Register Definitions */
lypinator 0:bb348c97df44 805 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
lypinator 0:bb348c97df44 806 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
lypinator 0:bb348c97df44 807
lypinator 0:bb348c97df44 808 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
lypinator 0:bb348c97df44 809 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
lypinator 0:bb348c97df44 810
lypinator 0:bb348c97df44 811 /* SCB Software Triggered Interrupt Register Definitions */
lypinator 0:bb348c97df44 812 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
lypinator 0:bb348c97df44 813 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
lypinator 0:bb348c97df44 814
lypinator 0:bb348c97df44 815 /* SCB D-Cache Invalidate by Set-way Register Definitions */
lypinator 0:bb348c97df44 816 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
lypinator 0:bb348c97df44 817 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
lypinator 0:bb348c97df44 818
lypinator 0:bb348c97df44 819 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
lypinator 0:bb348c97df44 820 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
lypinator 0:bb348c97df44 821
lypinator 0:bb348c97df44 822 /* SCB D-Cache Clean by Set-way Register Definitions */
lypinator 0:bb348c97df44 823 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
lypinator 0:bb348c97df44 824 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
lypinator 0:bb348c97df44 825
lypinator 0:bb348c97df44 826 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
lypinator 0:bb348c97df44 827 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
lypinator 0:bb348c97df44 828
lypinator 0:bb348c97df44 829 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
lypinator 0:bb348c97df44 830 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
lypinator 0:bb348c97df44 831 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
lypinator 0:bb348c97df44 832
lypinator 0:bb348c97df44 833 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
lypinator 0:bb348c97df44 834 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
lypinator 0:bb348c97df44 835
lypinator 0:bb348c97df44 836 /* Instruction Tightly-Coupled Memory Control Register Definitions */
lypinator 0:bb348c97df44 837 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
lypinator 0:bb348c97df44 838 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
lypinator 0:bb348c97df44 839
lypinator 0:bb348c97df44 840 #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
lypinator 0:bb348c97df44 841 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
lypinator 0:bb348c97df44 842
lypinator 0:bb348c97df44 843 #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
lypinator 0:bb348c97df44 844 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
lypinator 0:bb348c97df44 845
lypinator 0:bb348c97df44 846 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
lypinator 0:bb348c97df44 847 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
lypinator 0:bb348c97df44 848
lypinator 0:bb348c97df44 849 /* Data Tightly-Coupled Memory Control Register Definitions */
lypinator 0:bb348c97df44 850 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
lypinator 0:bb348c97df44 851 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
lypinator 0:bb348c97df44 852
lypinator 0:bb348c97df44 853 #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
lypinator 0:bb348c97df44 854 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
lypinator 0:bb348c97df44 855
lypinator 0:bb348c97df44 856 #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
lypinator 0:bb348c97df44 857 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
lypinator 0:bb348c97df44 858
lypinator 0:bb348c97df44 859 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
lypinator 0:bb348c97df44 860 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
lypinator 0:bb348c97df44 861
lypinator 0:bb348c97df44 862 /* AHBP Control Register Definitions */
lypinator 0:bb348c97df44 863 #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
lypinator 0:bb348c97df44 864 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
lypinator 0:bb348c97df44 865
lypinator 0:bb348c97df44 866 #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
lypinator 0:bb348c97df44 867 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
lypinator 0:bb348c97df44 868
lypinator 0:bb348c97df44 869 /* L1 Cache Control Register Definitions */
lypinator 0:bb348c97df44 870 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
lypinator 0:bb348c97df44 871 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
lypinator 0:bb348c97df44 872
lypinator 0:bb348c97df44 873 #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
lypinator 0:bb348c97df44 874 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
lypinator 0:bb348c97df44 875
lypinator 0:bb348c97df44 876 #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
lypinator 0:bb348c97df44 877 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
lypinator 0:bb348c97df44 878
lypinator 0:bb348c97df44 879 /* AHBS Control Register Definitions */
lypinator 0:bb348c97df44 880 #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
lypinator 0:bb348c97df44 881 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
lypinator 0:bb348c97df44 882
lypinator 0:bb348c97df44 883 #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
lypinator 0:bb348c97df44 884 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
lypinator 0:bb348c97df44 885
lypinator 0:bb348c97df44 886 #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
lypinator 0:bb348c97df44 887 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
lypinator 0:bb348c97df44 888
lypinator 0:bb348c97df44 889 /* Auxiliary Bus Fault Status Register Definitions */
lypinator 0:bb348c97df44 890 #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
lypinator 0:bb348c97df44 891 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
lypinator 0:bb348c97df44 892
lypinator 0:bb348c97df44 893 #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
lypinator 0:bb348c97df44 894 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
lypinator 0:bb348c97df44 895
lypinator 0:bb348c97df44 896 #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
lypinator 0:bb348c97df44 897 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
lypinator 0:bb348c97df44 898
lypinator 0:bb348c97df44 899 #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
lypinator 0:bb348c97df44 900 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
lypinator 0:bb348c97df44 901
lypinator 0:bb348c97df44 902 #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
lypinator 0:bb348c97df44 903 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
lypinator 0:bb348c97df44 904
lypinator 0:bb348c97df44 905 #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
lypinator 0:bb348c97df44 906 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
lypinator 0:bb348c97df44 907
lypinator 0:bb348c97df44 908 /*@} end of group CMSIS_SCB */
lypinator 0:bb348c97df44 909
lypinator 0:bb348c97df44 910
lypinator 0:bb348c97df44 911 /**
lypinator 0:bb348c97df44 912 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 913 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
lypinator 0:bb348c97df44 914 \brief Type definitions for the System Control and ID Register not in the SCB
lypinator 0:bb348c97df44 915 @{
lypinator 0:bb348c97df44 916 */
lypinator 0:bb348c97df44 917
lypinator 0:bb348c97df44 918 /**
lypinator 0:bb348c97df44 919 \brief Structure type to access the System Control and ID Register not in the SCB.
lypinator 0:bb348c97df44 920 */
lypinator 0:bb348c97df44 921 typedef struct
lypinator 0:bb348c97df44 922 {
lypinator 0:bb348c97df44 923 uint32_t RESERVED0[1U];
lypinator 0:bb348c97df44 924 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
lypinator 0:bb348c97df44 925 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
lypinator 0:bb348c97df44 926 } SCnSCB_Type;
lypinator 0:bb348c97df44 927
lypinator 0:bb348c97df44 928 /* Interrupt Controller Type Register Definitions */
lypinator 0:bb348c97df44 929 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
lypinator 0:bb348c97df44 930 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
lypinator 0:bb348c97df44 931
lypinator 0:bb348c97df44 932 /* Auxiliary Control Register Definitions */
lypinator 0:bb348c97df44 933 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
lypinator 0:bb348c97df44 934 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
lypinator 0:bb348c97df44 935
lypinator 0:bb348c97df44 936 #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
lypinator 0:bb348c97df44 937 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
lypinator 0:bb348c97df44 938
lypinator 0:bb348c97df44 939 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
lypinator 0:bb348c97df44 940 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
lypinator 0:bb348c97df44 941
lypinator 0:bb348c97df44 942 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
lypinator 0:bb348c97df44 943 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
lypinator 0:bb348c97df44 944
lypinator 0:bb348c97df44 945 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
lypinator 0:bb348c97df44 946 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
lypinator 0:bb348c97df44 947
lypinator 0:bb348c97df44 948 /*@} end of group CMSIS_SCnotSCB */
lypinator 0:bb348c97df44 949
lypinator 0:bb348c97df44 950
lypinator 0:bb348c97df44 951 /**
lypinator 0:bb348c97df44 952 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 953 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
lypinator 0:bb348c97df44 954 \brief Type definitions for the System Timer Registers.
lypinator 0:bb348c97df44 955 @{
lypinator 0:bb348c97df44 956 */
lypinator 0:bb348c97df44 957
lypinator 0:bb348c97df44 958 /**
lypinator 0:bb348c97df44 959 \brief Structure type to access the System Timer (SysTick).
lypinator 0:bb348c97df44 960 */
lypinator 0:bb348c97df44 961 typedef struct
lypinator 0:bb348c97df44 962 {
lypinator 0:bb348c97df44 963 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
lypinator 0:bb348c97df44 964 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
lypinator 0:bb348c97df44 965 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
lypinator 0:bb348c97df44 966 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
lypinator 0:bb348c97df44 967 } SysTick_Type;
lypinator 0:bb348c97df44 968
lypinator 0:bb348c97df44 969 /* SysTick Control / Status Register Definitions */
lypinator 0:bb348c97df44 970 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
lypinator 0:bb348c97df44 971 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
lypinator 0:bb348c97df44 972
lypinator 0:bb348c97df44 973 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
lypinator 0:bb348c97df44 974 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
lypinator 0:bb348c97df44 975
lypinator 0:bb348c97df44 976 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
lypinator 0:bb348c97df44 977 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
lypinator 0:bb348c97df44 978
lypinator 0:bb348c97df44 979 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
lypinator 0:bb348c97df44 980 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
lypinator 0:bb348c97df44 981
lypinator 0:bb348c97df44 982 /* SysTick Reload Register Definitions */
lypinator 0:bb348c97df44 983 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
lypinator 0:bb348c97df44 984 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
lypinator 0:bb348c97df44 985
lypinator 0:bb348c97df44 986 /* SysTick Current Register Definitions */
lypinator 0:bb348c97df44 987 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
lypinator 0:bb348c97df44 988 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
lypinator 0:bb348c97df44 989
lypinator 0:bb348c97df44 990 /* SysTick Calibration Register Definitions */
lypinator 0:bb348c97df44 991 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
lypinator 0:bb348c97df44 992 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
lypinator 0:bb348c97df44 993
lypinator 0:bb348c97df44 994 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
lypinator 0:bb348c97df44 995 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
lypinator 0:bb348c97df44 996
lypinator 0:bb348c97df44 997 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
lypinator 0:bb348c97df44 998 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
lypinator 0:bb348c97df44 999
lypinator 0:bb348c97df44 1000 /*@} end of group CMSIS_SysTick */
lypinator 0:bb348c97df44 1001
lypinator 0:bb348c97df44 1002
lypinator 0:bb348c97df44 1003 /**
lypinator 0:bb348c97df44 1004 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 1005 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
lypinator 0:bb348c97df44 1006 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
lypinator 0:bb348c97df44 1007 @{
lypinator 0:bb348c97df44 1008 */
lypinator 0:bb348c97df44 1009
lypinator 0:bb348c97df44 1010 /**
lypinator 0:bb348c97df44 1011 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
lypinator 0:bb348c97df44 1012 */
lypinator 0:bb348c97df44 1013 typedef struct
lypinator 0:bb348c97df44 1014 {
lypinator 0:bb348c97df44 1015 __OM union
lypinator 0:bb348c97df44 1016 {
lypinator 0:bb348c97df44 1017 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
lypinator 0:bb348c97df44 1018 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
lypinator 0:bb348c97df44 1019 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
lypinator 0:bb348c97df44 1020 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
lypinator 0:bb348c97df44 1021 uint32_t RESERVED0[864U];
lypinator 0:bb348c97df44 1022 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
lypinator 0:bb348c97df44 1023 uint32_t RESERVED1[15U];
lypinator 0:bb348c97df44 1024 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
lypinator 0:bb348c97df44 1025 uint32_t RESERVED2[15U];
lypinator 0:bb348c97df44 1026 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
lypinator 0:bb348c97df44 1027 uint32_t RESERVED3[29U];
lypinator 0:bb348c97df44 1028 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
lypinator 0:bb348c97df44 1029 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
lypinator 0:bb348c97df44 1030 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
lypinator 0:bb348c97df44 1031 uint32_t RESERVED4[43U];
lypinator 0:bb348c97df44 1032 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
lypinator 0:bb348c97df44 1033 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
lypinator 0:bb348c97df44 1034 uint32_t RESERVED5[6U];
lypinator 0:bb348c97df44 1035 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
lypinator 0:bb348c97df44 1036 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
lypinator 0:bb348c97df44 1037 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
lypinator 0:bb348c97df44 1038 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
lypinator 0:bb348c97df44 1039 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
lypinator 0:bb348c97df44 1040 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
lypinator 0:bb348c97df44 1041 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
lypinator 0:bb348c97df44 1042 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
lypinator 0:bb348c97df44 1043 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
lypinator 0:bb348c97df44 1044 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
lypinator 0:bb348c97df44 1045 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
lypinator 0:bb348c97df44 1046 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
lypinator 0:bb348c97df44 1047 } ITM_Type;
lypinator 0:bb348c97df44 1048
lypinator 0:bb348c97df44 1049 /* ITM Trace Privilege Register Definitions */
lypinator 0:bb348c97df44 1050 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
lypinator 0:bb348c97df44 1051 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
lypinator 0:bb348c97df44 1052
lypinator 0:bb348c97df44 1053 /* ITM Trace Control Register Definitions */
lypinator 0:bb348c97df44 1054 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
lypinator 0:bb348c97df44 1055 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
lypinator 0:bb348c97df44 1056
lypinator 0:bb348c97df44 1057 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
lypinator 0:bb348c97df44 1058 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
lypinator 0:bb348c97df44 1059
lypinator 0:bb348c97df44 1060 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
lypinator 0:bb348c97df44 1061 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
lypinator 0:bb348c97df44 1062
lypinator 0:bb348c97df44 1063 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
lypinator 0:bb348c97df44 1064 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
lypinator 0:bb348c97df44 1065
lypinator 0:bb348c97df44 1066 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
lypinator 0:bb348c97df44 1067 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
lypinator 0:bb348c97df44 1068
lypinator 0:bb348c97df44 1069 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
lypinator 0:bb348c97df44 1070 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
lypinator 0:bb348c97df44 1071
lypinator 0:bb348c97df44 1072 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
lypinator 0:bb348c97df44 1073 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
lypinator 0:bb348c97df44 1074
lypinator 0:bb348c97df44 1075 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
lypinator 0:bb348c97df44 1076 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
lypinator 0:bb348c97df44 1077
lypinator 0:bb348c97df44 1078 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
lypinator 0:bb348c97df44 1079 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
lypinator 0:bb348c97df44 1080
lypinator 0:bb348c97df44 1081 /* ITM Integration Write Register Definitions */
lypinator 0:bb348c97df44 1082 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
lypinator 0:bb348c97df44 1083 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
lypinator 0:bb348c97df44 1084
lypinator 0:bb348c97df44 1085 /* ITM Integration Read Register Definitions */
lypinator 0:bb348c97df44 1086 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
lypinator 0:bb348c97df44 1087 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
lypinator 0:bb348c97df44 1088
lypinator 0:bb348c97df44 1089 /* ITM Integration Mode Control Register Definitions */
lypinator 0:bb348c97df44 1090 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
lypinator 0:bb348c97df44 1091 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
lypinator 0:bb348c97df44 1092
lypinator 0:bb348c97df44 1093 /* ITM Lock Status Register Definitions */
lypinator 0:bb348c97df44 1094 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
lypinator 0:bb348c97df44 1095 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
lypinator 0:bb348c97df44 1096
lypinator 0:bb348c97df44 1097 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
lypinator 0:bb348c97df44 1098 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
lypinator 0:bb348c97df44 1099
lypinator 0:bb348c97df44 1100 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
lypinator 0:bb348c97df44 1101 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
lypinator 0:bb348c97df44 1102
lypinator 0:bb348c97df44 1103 /*@}*/ /* end of group CMSIS_ITM */
lypinator 0:bb348c97df44 1104
lypinator 0:bb348c97df44 1105
lypinator 0:bb348c97df44 1106 /**
lypinator 0:bb348c97df44 1107 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 1108 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
lypinator 0:bb348c97df44 1109 \brief Type definitions for the Data Watchpoint and Trace (DWT)
lypinator 0:bb348c97df44 1110 @{
lypinator 0:bb348c97df44 1111 */
lypinator 0:bb348c97df44 1112
lypinator 0:bb348c97df44 1113 /**
lypinator 0:bb348c97df44 1114 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
lypinator 0:bb348c97df44 1115 */
lypinator 0:bb348c97df44 1116 typedef struct
lypinator 0:bb348c97df44 1117 {
lypinator 0:bb348c97df44 1118 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
lypinator 0:bb348c97df44 1119 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
lypinator 0:bb348c97df44 1120 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
lypinator 0:bb348c97df44 1121 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
lypinator 0:bb348c97df44 1122 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
lypinator 0:bb348c97df44 1123 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
lypinator 0:bb348c97df44 1124 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
lypinator 0:bb348c97df44 1125 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
lypinator 0:bb348c97df44 1126 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
lypinator 0:bb348c97df44 1127 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
lypinator 0:bb348c97df44 1128 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
lypinator 0:bb348c97df44 1129 uint32_t RESERVED0[1U];
lypinator 0:bb348c97df44 1130 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
lypinator 0:bb348c97df44 1131 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
lypinator 0:bb348c97df44 1132 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
lypinator 0:bb348c97df44 1133 uint32_t RESERVED1[1U];
lypinator 0:bb348c97df44 1134 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
lypinator 0:bb348c97df44 1135 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
lypinator 0:bb348c97df44 1136 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
lypinator 0:bb348c97df44 1137 uint32_t RESERVED2[1U];
lypinator 0:bb348c97df44 1138 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
lypinator 0:bb348c97df44 1139 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
lypinator 0:bb348c97df44 1140 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
lypinator 0:bb348c97df44 1141 uint32_t RESERVED3[981U];
lypinator 0:bb348c97df44 1142 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
lypinator 0:bb348c97df44 1143 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
lypinator 0:bb348c97df44 1144 } DWT_Type;
lypinator 0:bb348c97df44 1145
lypinator 0:bb348c97df44 1146 /* DWT Control Register Definitions */
lypinator 0:bb348c97df44 1147 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
lypinator 0:bb348c97df44 1148 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
lypinator 0:bb348c97df44 1149
lypinator 0:bb348c97df44 1150 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
lypinator 0:bb348c97df44 1151 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
lypinator 0:bb348c97df44 1152
lypinator 0:bb348c97df44 1153 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
lypinator 0:bb348c97df44 1154 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
lypinator 0:bb348c97df44 1155
lypinator 0:bb348c97df44 1156 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
lypinator 0:bb348c97df44 1157 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
lypinator 0:bb348c97df44 1158
lypinator 0:bb348c97df44 1159 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
lypinator 0:bb348c97df44 1160 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
lypinator 0:bb348c97df44 1161
lypinator 0:bb348c97df44 1162 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
lypinator 0:bb348c97df44 1163 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
lypinator 0:bb348c97df44 1164
lypinator 0:bb348c97df44 1165 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
lypinator 0:bb348c97df44 1166 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
lypinator 0:bb348c97df44 1167
lypinator 0:bb348c97df44 1168 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
lypinator 0:bb348c97df44 1169 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
lypinator 0:bb348c97df44 1170
lypinator 0:bb348c97df44 1171 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
lypinator 0:bb348c97df44 1172 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
lypinator 0:bb348c97df44 1173
lypinator 0:bb348c97df44 1174 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
lypinator 0:bb348c97df44 1175 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
lypinator 0:bb348c97df44 1176
lypinator 0:bb348c97df44 1177 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
lypinator 0:bb348c97df44 1178 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
lypinator 0:bb348c97df44 1179
lypinator 0:bb348c97df44 1180 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
lypinator 0:bb348c97df44 1181 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
lypinator 0:bb348c97df44 1182
lypinator 0:bb348c97df44 1183 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
lypinator 0:bb348c97df44 1184 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
lypinator 0:bb348c97df44 1185
lypinator 0:bb348c97df44 1186 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
lypinator 0:bb348c97df44 1187 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
lypinator 0:bb348c97df44 1188
lypinator 0:bb348c97df44 1189 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
lypinator 0:bb348c97df44 1190 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
lypinator 0:bb348c97df44 1191
lypinator 0:bb348c97df44 1192 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
lypinator 0:bb348c97df44 1193 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
lypinator 0:bb348c97df44 1194
lypinator 0:bb348c97df44 1195 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
lypinator 0:bb348c97df44 1196 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
lypinator 0:bb348c97df44 1197
lypinator 0:bb348c97df44 1198 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
lypinator 0:bb348c97df44 1199 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
lypinator 0:bb348c97df44 1200
lypinator 0:bb348c97df44 1201 /* DWT CPI Count Register Definitions */
lypinator 0:bb348c97df44 1202 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
lypinator 0:bb348c97df44 1203 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
lypinator 0:bb348c97df44 1204
lypinator 0:bb348c97df44 1205 /* DWT Exception Overhead Count Register Definitions */
lypinator 0:bb348c97df44 1206 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
lypinator 0:bb348c97df44 1207 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
lypinator 0:bb348c97df44 1208
lypinator 0:bb348c97df44 1209 /* DWT Sleep Count Register Definitions */
lypinator 0:bb348c97df44 1210 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
lypinator 0:bb348c97df44 1211 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
lypinator 0:bb348c97df44 1212
lypinator 0:bb348c97df44 1213 /* DWT LSU Count Register Definitions */
lypinator 0:bb348c97df44 1214 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
lypinator 0:bb348c97df44 1215 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
lypinator 0:bb348c97df44 1216
lypinator 0:bb348c97df44 1217 /* DWT Folded-instruction Count Register Definitions */
lypinator 0:bb348c97df44 1218 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
lypinator 0:bb348c97df44 1219 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
lypinator 0:bb348c97df44 1220
lypinator 0:bb348c97df44 1221 /* DWT Comparator Mask Register Definitions */
lypinator 0:bb348c97df44 1222 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
lypinator 0:bb348c97df44 1223 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
lypinator 0:bb348c97df44 1224
lypinator 0:bb348c97df44 1225 /* DWT Comparator Function Register Definitions */
lypinator 0:bb348c97df44 1226 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
lypinator 0:bb348c97df44 1227 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
lypinator 0:bb348c97df44 1228
lypinator 0:bb348c97df44 1229 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
lypinator 0:bb348c97df44 1230 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
lypinator 0:bb348c97df44 1231
lypinator 0:bb348c97df44 1232 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
lypinator 0:bb348c97df44 1233 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
lypinator 0:bb348c97df44 1234
lypinator 0:bb348c97df44 1235 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
lypinator 0:bb348c97df44 1236 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
lypinator 0:bb348c97df44 1237
lypinator 0:bb348c97df44 1238 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
lypinator 0:bb348c97df44 1239 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
lypinator 0:bb348c97df44 1240
lypinator 0:bb348c97df44 1241 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
lypinator 0:bb348c97df44 1242 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
lypinator 0:bb348c97df44 1243
lypinator 0:bb348c97df44 1244 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
lypinator 0:bb348c97df44 1245 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
lypinator 0:bb348c97df44 1246
lypinator 0:bb348c97df44 1247 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
lypinator 0:bb348c97df44 1248 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
lypinator 0:bb348c97df44 1249
lypinator 0:bb348c97df44 1250 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
lypinator 0:bb348c97df44 1251 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
lypinator 0:bb348c97df44 1252
lypinator 0:bb348c97df44 1253 /*@}*/ /* end of group CMSIS_DWT */
lypinator 0:bb348c97df44 1254
lypinator 0:bb348c97df44 1255
lypinator 0:bb348c97df44 1256 /**
lypinator 0:bb348c97df44 1257 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 1258 \defgroup CMSIS_TPI Trace Port Interface (TPI)
lypinator 0:bb348c97df44 1259 \brief Type definitions for the Trace Port Interface (TPI)
lypinator 0:bb348c97df44 1260 @{
lypinator 0:bb348c97df44 1261 */
lypinator 0:bb348c97df44 1262
lypinator 0:bb348c97df44 1263 /**
lypinator 0:bb348c97df44 1264 \brief Structure type to access the Trace Port Interface Register (TPI).
lypinator 0:bb348c97df44 1265 */
lypinator 0:bb348c97df44 1266 typedef struct
lypinator 0:bb348c97df44 1267 {
lypinator 0:bb348c97df44 1268 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
lypinator 0:bb348c97df44 1269 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
lypinator 0:bb348c97df44 1270 uint32_t RESERVED0[2U];
lypinator 0:bb348c97df44 1271 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
lypinator 0:bb348c97df44 1272 uint32_t RESERVED1[55U];
lypinator 0:bb348c97df44 1273 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
lypinator 0:bb348c97df44 1274 uint32_t RESERVED2[131U];
lypinator 0:bb348c97df44 1275 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
lypinator 0:bb348c97df44 1276 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
lypinator 0:bb348c97df44 1277 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
lypinator 0:bb348c97df44 1278 uint32_t RESERVED3[759U];
lypinator 0:bb348c97df44 1279 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
lypinator 0:bb348c97df44 1280 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
lypinator 0:bb348c97df44 1281 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
lypinator 0:bb348c97df44 1282 uint32_t RESERVED4[1U];
lypinator 0:bb348c97df44 1283 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
lypinator 0:bb348c97df44 1284 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
lypinator 0:bb348c97df44 1285 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
lypinator 0:bb348c97df44 1286 uint32_t RESERVED5[39U];
lypinator 0:bb348c97df44 1287 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
lypinator 0:bb348c97df44 1288 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
lypinator 0:bb348c97df44 1289 uint32_t RESERVED7[8U];
lypinator 0:bb348c97df44 1290 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
lypinator 0:bb348c97df44 1291 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
lypinator 0:bb348c97df44 1292 } TPI_Type;
lypinator 0:bb348c97df44 1293
lypinator 0:bb348c97df44 1294 /* TPI Asynchronous Clock Prescaler Register Definitions */
lypinator 0:bb348c97df44 1295 #define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */
lypinator 0:bb348c97df44 1296 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */
lypinator 0:bb348c97df44 1297
lypinator 0:bb348c97df44 1298 #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
lypinator 0:bb348c97df44 1299 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
lypinator 0:bb348c97df44 1300
lypinator 0:bb348c97df44 1301 /* TPI Selected Pin Protocol Register Definitions */
lypinator 0:bb348c97df44 1302 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
lypinator 0:bb348c97df44 1303 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
lypinator 0:bb348c97df44 1304
lypinator 0:bb348c97df44 1305 /* TPI Formatter and Flush Status Register Definitions */
lypinator 0:bb348c97df44 1306 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
lypinator 0:bb348c97df44 1307 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
lypinator 0:bb348c97df44 1308
lypinator 0:bb348c97df44 1309 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
lypinator 0:bb348c97df44 1310 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
lypinator 0:bb348c97df44 1311
lypinator 0:bb348c97df44 1312 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
lypinator 0:bb348c97df44 1313 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
lypinator 0:bb348c97df44 1314
lypinator 0:bb348c97df44 1315 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
lypinator 0:bb348c97df44 1316 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
lypinator 0:bb348c97df44 1317
lypinator 0:bb348c97df44 1318 /* TPI Formatter and Flush Control Register Definitions */
lypinator 0:bb348c97df44 1319 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
lypinator 0:bb348c97df44 1320 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
lypinator 0:bb348c97df44 1321
lypinator 0:bb348c97df44 1322 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
lypinator 0:bb348c97df44 1323 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
lypinator 0:bb348c97df44 1324
lypinator 0:bb348c97df44 1325 /* TPI TRIGGER Register Definitions */
lypinator 0:bb348c97df44 1326 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
lypinator 0:bb348c97df44 1327 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
lypinator 0:bb348c97df44 1328
lypinator 0:bb348c97df44 1329 /* TPI Integration ETM Data Register Definitions (FIFO0) */
lypinator 0:bb348c97df44 1330 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
lypinator 0:bb348c97df44 1331 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
lypinator 0:bb348c97df44 1332
lypinator 0:bb348c97df44 1333 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
lypinator 0:bb348c97df44 1334 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
lypinator 0:bb348c97df44 1335
lypinator 0:bb348c97df44 1336 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
lypinator 0:bb348c97df44 1337 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
lypinator 0:bb348c97df44 1338
lypinator 0:bb348c97df44 1339 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
lypinator 0:bb348c97df44 1340 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
lypinator 0:bb348c97df44 1341
lypinator 0:bb348c97df44 1342 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
lypinator 0:bb348c97df44 1343 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
lypinator 0:bb348c97df44 1344
lypinator 0:bb348c97df44 1345 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
lypinator 0:bb348c97df44 1346 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
lypinator 0:bb348c97df44 1347
lypinator 0:bb348c97df44 1348 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
lypinator 0:bb348c97df44 1349 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
lypinator 0:bb348c97df44 1350
lypinator 0:bb348c97df44 1351 /* TPI ITATBCTR2 Register Definitions */
lypinator 0:bb348c97df44 1352 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
lypinator 0:bb348c97df44 1353 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
lypinator 0:bb348c97df44 1354
lypinator 0:bb348c97df44 1355 /* TPI Integration ITM Data Register Definitions (FIFO1) */
lypinator 0:bb348c97df44 1356 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
lypinator 0:bb348c97df44 1357 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
lypinator 0:bb348c97df44 1358
lypinator 0:bb348c97df44 1359 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
lypinator 0:bb348c97df44 1360 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
lypinator 0:bb348c97df44 1361
lypinator 0:bb348c97df44 1362 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
lypinator 0:bb348c97df44 1363 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
lypinator 0:bb348c97df44 1364
lypinator 0:bb348c97df44 1365 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
lypinator 0:bb348c97df44 1366 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
lypinator 0:bb348c97df44 1367
lypinator 0:bb348c97df44 1368 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
lypinator 0:bb348c97df44 1369 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
lypinator 0:bb348c97df44 1370
lypinator 0:bb348c97df44 1371 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
lypinator 0:bb348c97df44 1372 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
lypinator 0:bb348c97df44 1373
lypinator 0:bb348c97df44 1374 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
lypinator 0:bb348c97df44 1375 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
lypinator 0:bb348c97df44 1376
lypinator 0:bb348c97df44 1377 /* TPI ITATBCTR0 Register Definitions */
lypinator 0:bb348c97df44 1378 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
lypinator 0:bb348c97df44 1379 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
lypinator 0:bb348c97df44 1380
lypinator 0:bb348c97df44 1381 /* TPI Integration Mode Control Register Definitions */
lypinator 0:bb348c97df44 1382 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
lypinator 0:bb348c97df44 1383 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
lypinator 0:bb348c97df44 1384
lypinator 0:bb348c97df44 1385 /* TPI DEVID Register Definitions */
lypinator 0:bb348c97df44 1386 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
lypinator 0:bb348c97df44 1387 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
lypinator 0:bb348c97df44 1388
lypinator 0:bb348c97df44 1389 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
lypinator 0:bb348c97df44 1390 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
lypinator 0:bb348c97df44 1391
lypinator 0:bb348c97df44 1392 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
lypinator 0:bb348c97df44 1393 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
lypinator 0:bb348c97df44 1394
lypinator 0:bb348c97df44 1395 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
lypinator 0:bb348c97df44 1396 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
lypinator 0:bb348c97df44 1397
lypinator 0:bb348c97df44 1398 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
lypinator 0:bb348c97df44 1399 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
lypinator 0:bb348c97df44 1400
lypinator 0:bb348c97df44 1401 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
lypinator 0:bb348c97df44 1402 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
lypinator 0:bb348c97df44 1403
lypinator 0:bb348c97df44 1404 /* TPI DEVTYPE Register Definitions */
lypinator 0:bb348c97df44 1405 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
lypinator 0:bb348c97df44 1406 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
lypinator 0:bb348c97df44 1407
lypinator 0:bb348c97df44 1408 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
lypinator 0:bb348c97df44 1409 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
lypinator 0:bb348c97df44 1410
lypinator 0:bb348c97df44 1411 /*@}*/ /* end of group CMSIS_TPI */
lypinator 0:bb348c97df44 1412
lypinator 0:bb348c97df44 1413
lypinator 0:bb348c97df44 1414 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
lypinator 0:bb348c97df44 1415 /**
lypinator 0:bb348c97df44 1416 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 1417 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
lypinator 0:bb348c97df44 1418 \brief Type definitions for the Memory Protection Unit (MPU)
lypinator 0:bb348c97df44 1419 @{
lypinator 0:bb348c97df44 1420 */
lypinator 0:bb348c97df44 1421
lypinator 0:bb348c97df44 1422 /**
lypinator 0:bb348c97df44 1423 \brief Structure type to access the Memory Protection Unit (MPU).
lypinator 0:bb348c97df44 1424 */
lypinator 0:bb348c97df44 1425 typedef struct
lypinator 0:bb348c97df44 1426 {
lypinator 0:bb348c97df44 1427 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
lypinator 0:bb348c97df44 1428 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
lypinator 0:bb348c97df44 1429 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
lypinator 0:bb348c97df44 1430 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
lypinator 0:bb348c97df44 1431 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
lypinator 0:bb348c97df44 1432 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
lypinator 0:bb348c97df44 1433 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
lypinator 0:bb348c97df44 1434 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
lypinator 0:bb348c97df44 1435 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
lypinator 0:bb348c97df44 1436 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
lypinator 0:bb348c97df44 1437 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
lypinator 0:bb348c97df44 1438 } MPU_Type;
lypinator 0:bb348c97df44 1439
lypinator 0:bb348c97df44 1440 #define MPU_TYPE_RALIASES 4U
lypinator 0:bb348c97df44 1441
lypinator 0:bb348c97df44 1442 /* MPU Type Register Definitions */
lypinator 0:bb348c97df44 1443 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
lypinator 0:bb348c97df44 1444 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
lypinator 0:bb348c97df44 1445
lypinator 0:bb348c97df44 1446 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
lypinator 0:bb348c97df44 1447 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
lypinator 0:bb348c97df44 1448
lypinator 0:bb348c97df44 1449 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
lypinator 0:bb348c97df44 1450 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
lypinator 0:bb348c97df44 1451
lypinator 0:bb348c97df44 1452 /* MPU Control Register Definitions */
lypinator 0:bb348c97df44 1453 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
lypinator 0:bb348c97df44 1454 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
lypinator 0:bb348c97df44 1455
lypinator 0:bb348c97df44 1456 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
lypinator 0:bb348c97df44 1457 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
lypinator 0:bb348c97df44 1458
lypinator 0:bb348c97df44 1459 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
lypinator 0:bb348c97df44 1460 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
lypinator 0:bb348c97df44 1461
lypinator 0:bb348c97df44 1462 /* MPU Region Number Register Definitions */
lypinator 0:bb348c97df44 1463 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
lypinator 0:bb348c97df44 1464 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
lypinator 0:bb348c97df44 1465
lypinator 0:bb348c97df44 1466 /* MPU Region Base Address Register Definitions */
lypinator 0:bb348c97df44 1467 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
lypinator 0:bb348c97df44 1468 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
lypinator 0:bb348c97df44 1469
lypinator 0:bb348c97df44 1470 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
lypinator 0:bb348c97df44 1471 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
lypinator 0:bb348c97df44 1472
lypinator 0:bb348c97df44 1473 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
lypinator 0:bb348c97df44 1474 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
lypinator 0:bb348c97df44 1475
lypinator 0:bb348c97df44 1476 /* MPU Region Attribute and Size Register Definitions */
lypinator 0:bb348c97df44 1477 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
lypinator 0:bb348c97df44 1478 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
lypinator 0:bb348c97df44 1479
lypinator 0:bb348c97df44 1480 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
lypinator 0:bb348c97df44 1481 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
lypinator 0:bb348c97df44 1482
lypinator 0:bb348c97df44 1483 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
lypinator 0:bb348c97df44 1484 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
lypinator 0:bb348c97df44 1485
lypinator 0:bb348c97df44 1486 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
lypinator 0:bb348c97df44 1487 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
lypinator 0:bb348c97df44 1488
lypinator 0:bb348c97df44 1489 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
lypinator 0:bb348c97df44 1490 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
lypinator 0:bb348c97df44 1491
lypinator 0:bb348c97df44 1492 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
lypinator 0:bb348c97df44 1493 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
lypinator 0:bb348c97df44 1494
lypinator 0:bb348c97df44 1495 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
lypinator 0:bb348c97df44 1496 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
lypinator 0:bb348c97df44 1497
lypinator 0:bb348c97df44 1498 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
lypinator 0:bb348c97df44 1499 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
lypinator 0:bb348c97df44 1500
lypinator 0:bb348c97df44 1501 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
lypinator 0:bb348c97df44 1502 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
lypinator 0:bb348c97df44 1503
lypinator 0:bb348c97df44 1504 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
lypinator 0:bb348c97df44 1505 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
lypinator 0:bb348c97df44 1506
lypinator 0:bb348c97df44 1507 /*@} end of group CMSIS_MPU */
lypinator 0:bb348c97df44 1508 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
lypinator 0:bb348c97df44 1509
lypinator 0:bb348c97df44 1510
lypinator 0:bb348c97df44 1511 /**
lypinator 0:bb348c97df44 1512 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 1513 \defgroup CMSIS_FPU Floating Point Unit (FPU)
lypinator 0:bb348c97df44 1514 \brief Type definitions for the Floating Point Unit (FPU)
lypinator 0:bb348c97df44 1515 @{
lypinator 0:bb348c97df44 1516 */
lypinator 0:bb348c97df44 1517
lypinator 0:bb348c97df44 1518 /**
lypinator 0:bb348c97df44 1519 \brief Structure type to access the Floating Point Unit (FPU).
lypinator 0:bb348c97df44 1520 */
lypinator 0:bb348c97df44 1521 typedef struct
lypinator 0:bb348c97df44 1522 {
lypinator 0:bb348c97df44 1523 uint32_t RESERVED0[1U];
lypinator 0:bb348c97df44 1524 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
lypinator 0:bb348c97df44 1525 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
lypinator 0:bb348c97df44 1526 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
lypinator 0:bb348c97df44 1527 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
lypinator 0:bb348c97df44 1528 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
lypinator 0:bb348c97df44 1529 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
lypinator 0:bb348c97df44 1530 } FPU_Type;
lypinator 0:bb348c97df44 1531
lypinator 0:bb348c97df44 1532 /* Floating-Point Context Control Register Definitions */
lypinator 0:bb348c97df44 1533 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
lypinator 0:bb348c97df44 1534 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
lypinator 0:bb348c97df44 1535
lypinator 0:bb348c97df44 1536 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
lypinator 0:bb348c97df44 1537 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
lypinator 0:bb348c97df44 1538
lypinator 0:bb348c97df44 1539 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
lypinator 0:bb348c97df44 1540 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
lypinator 0:bb348c97df44 1541
lypinator 0:bb348c97df44 1542 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
lypinator 0:bb348c97df44 1543 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
lypinator 0:bb348c97df44 1544
lypinator 0:bb348c97df44 1545 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
lypinator 0:bb348c97df44 1546 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
lypinator 0:bb348c97df44 1547
lypinator 0:bb348c97df44 1548 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
lypinator 0:bb348c97df44 1549 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
lypinator 0:bb348c97df44 1550
lypinator 0:bb348c97df44 1551 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
lypinator 0:bb348c97df44 1552 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
lypinator 0:bb348c97df44 1553
lypinator 0:bb348c97df44 1554 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
lypinator 0:bb348c97df44 1555 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
lypinator 0:bb348c97df44 1556
lypinator 0:bb348c97df44 1557 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
lypinator 0:bb348c97df44 1558 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
lypinator 0:bb348c97df44 1559
lypinator 0:bb348c97df44 1560 /* Floating-Point Context Address Register Definitions */
lypinator 0:bb348c97df44 1561 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
lypinator 0:bb348c97df44 1562 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
lypinator 0:bb348c97df44 1563
lypinator 0:bb348c97df44 1564 /* Floating-Point Default Status Control Register Definitions */
lypinator 0:bb348c97df44 1565 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
lypinator 0:bb348c97df44 1566 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
lypinator 0:bb348c97df44 1567
lypinator 0:bb348c97df44 1568 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
lypinator 0:bb348c97df44 1569 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
lypinator 0:bb348c97df44 1570
lypinator 0:bb348c97df44 1571 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
lypinator 0:bb348c97df44 1572 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
lypinator 0:bb348c97df44 1573
lypinator 0:bb348c97df44 1574 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
lypinator 0:bb348c97df44 1575 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
lypinator 0:bb348c97df44 1576
lypinator 0:bb348c97df44 1577 /* Media and FP Feature Register 0 Definitions */
lypinator 0:bb348c97df44 1578 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
lypinator 0:bb348c97df44 1579 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
lypinator 0:bb348c97df44 1580
lypinator 0:bb348c97df44 1581 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
lypinator 0:bb348c97df44 1582 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
lypinator 0:bb348c97df44 1583
lypinator 0:bb348c97df44 1584 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
lypinator 0:bb348c97df44 1585 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
lypinator 0:bb348c97df44 1586
lypinator 0:bb348c97df44 1587 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
lypinator 0:bb348c97df44 1588 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
lypinator 0:bb348c97df44 1589
lypinator 0:bb348c97df44 1590 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
lypinator 0:bb348c97df44 1591 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
lypinator 0:bb348c97df44 1592
lypinator 0:bb348c97df44 1593 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
lypinator 0:bb348c97df44 1594 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
lypinator 0:bb348c97df44 1595
lypinator 0:bb348c97df44 1596 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
lypinator 0:bb348c97df44 1597 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
lypinator 0:bb348c97df44 1598
lypinator 0:bb348c97df44 1599 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
lypinator 0:bb348c97df44 1600 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
lypinator 0:bb348c97df44 1601
lypinator 0:bb348c97df44 1602 /* Media and FP Feature Register 1 Definitions */
lypinator 0:bb348c97df44 1603 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
lypinator 0:bb348c97df44 1604 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
lypinator 0:bb348c97df44 1605
lypinator 0:bb348c97df44 1606 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
lypinator 0:bb348c97df44 1607 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
lypinator 0:bb348c97df44 1608
lypinator 0:bb348c97df44 1609 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
lypinator 0:bb348c97df44 1610 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
lypinator 0:bb348c97df44 1611
lypinator 0:bb348c97df44 1612 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
lypinator 0:bb348c97df44 1613 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
lypinator 0:bb348c97df44 1614
lypinator 0:bb348c97df44 1615 /* Media and FP Feature Register 2 Definitions */
lypinator 0:bb348c97df44 1616
lypinator 0:bb348c97df44 1617 /*@} end of group CMSIS_FPU */
lypinator 0:bb348c97df44 1618
lypinator 0:bb348c97df44 1619
lypinator 0:bb348c97df44 1620 /**
lypinator 0:bb348c97df44 1621 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 1622 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
lypinator 0:bb348c97df44 1623 \brief Type definitions for the Core Debug Registers
lypinator 0:bb348c97df44 1624 @{
lypinator 0:bb348c97df44 1625 */
lypinator 0:bb348c97df44 1626
lypinator 0:bb348c97df44 1627 /**
lypinator 0:bb348c97df44 1628 \brief Structure type to access the Core Debug Register (CoreDebug).
lypinator 0:bb348c97df44 1629 */
lypinator 0:bb348c97df44 1630 typedef struct
lypinator 0:bb348c97df44 1631 {
lypinator 0:bb348c97df44 1632 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
lypinator 0:bb348c97df44 1633 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
lypinator 0:bb348c97df44 1634 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
lypinator 0:bb348c97df44 1635 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
lypinator 0:bb348c97df44 1636 } CoreDebug_Type;
lypinator 0:bb348c97df44 1637
lypinator 0:bb348c97df44 1638 /* Debug Halting Control and Status Register Definitions */
lypinator 0:bb348c97df44 1639 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
lypinator 0:bb348c97df44 1640 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
lypinator 0:bb348c97df44 1641
lypinator 0:bb348c97df44 1642 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
lypinator 0:bb348c97df44 1643 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
lypinator 0:bb348c97df44 1644
lypinator 0:bb348c97df44 1645 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
lypinator 0:bb348c97df44 1646 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
lypinator 0:bb348c97df44 1647
lypinator 0:bb348c97df44 1648 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
lypinator 0:bb348c97df44 1649 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
lypinator 0:bb348c97df44 1650
lypinator 0:bb348c97df44 1651 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
lypinator 0:bb348c97df44 1652 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
lypinator 0:bb348c97df44 1653
lypinator 0:bb348c97df44 1654 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
lypinator 0:bb348c97df44 1655 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
lypinator 0:bb348c97df44 1656
lypinator 0:bb348c97df44 1657 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
lypinator 0:bb348c97df44 1658 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
lypinator 0:bb348c97df44 1659
lypinator 0:bb348c97df44 1660 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
lypinator 0:bb348c97df44 1661 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
lypinator 0:bb348c97df44 1662
lypinator 0:bb348c97df44 1663 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
lypinator 0:bb348c97df44 1664 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
lypinator 0:bb348c97df44 1665
lypinator 0:bb348c97df44 1666 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
lypinator 0:bb348c97df44 1667 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
lypinator 0:bb348c97df44 1668
lypinator 0:bb348c97df44 1669 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
lypinator 0:bb348c97df44 1670 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
lypinator 0:bb348c97df44 1671
lypinator 0:bb348c97df44 1672 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
lypinator 0:bb348c97df44 1673 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
lypinator 0:bb348c97df44 1674
lypinator 0:bb348c97df44 1675 /* Debug Core Register Selector Register Definitions */
lypinator 0:bb348c97df44 1676 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
lypinator 0:bb348c97df44 1677 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
lypinator 0:bb348c97df44 1678
lypinator 0:bb348c97df44 1679 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
lypinator 0:bb348c97df44 1680 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
lypinator 0:bb348c97df44 1681
lypinator 0:bb348c97df44 1682 /* Debug Exception and Monitor Control Register Definitions */
lypinator 0:bb348c97df44 1683 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
lypinator 0:bb348c97df44 1684 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
lypinator 0:bb348c97df44 1685
lypinator 0:bb348c97df44 1686 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
lypinator 0:bb348c97df44 1687 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
lypinator 0:bb348c97df44 1688
lypinator 0:bb348c97df44 1689 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
lypinator 0:bb348c97df44 1690 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
lypinator 0:bb348c97df44 1691
lypinator 0:bb348c97df44 1692 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
lypinator 0:bb348c97df44 1693 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
lypinator 0:bb348c97df44 1694
lypinator 0:bb348c97df44 1695 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
lypinator 0:bb348c97df44 1696 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
lypinator 0:bb348c97df44 1697
lypinator 0:bb348c97df44 1698 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
lypinator 0:bb348c97df44 1699 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
lypinator 0:bb348c97df44 1700
lypinator 0:bb348c97df44 1701 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
lypinator 0:bb348c97df44 1702 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
lypinator 0:bb348c97df44 1703
lypinator 0:bb348c97df44 1704 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
lypinator 0:bb348c97df44 1705 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
lypinator 0:bb348c97df44 1706
lypinator 0:bb348c97df44 1707 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
lypinator 0:bb348c97df44 1708 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
lypinator 0:bb348c97df44 1709
lypinator 0:bb348c97df44 1710 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
lypinator 0:bb348c97df44 1711 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
lypinator 0:bb348c97df44 1712
lypinator 0:bb348c97df44 1713 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
lypinator 0:bb348c97df44 1714 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
lypinator 0:bb348c97df44 1715
lypinator 0:bb348c97df44 1716 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
lypinator 0:bb348c97df44 1717 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
lypinator 0:bb348c97df44 1718
lypinator 0:bb348c97df44 1719 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
lypinator 0:bb348c97df44 1720 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
lypinator 0:bb348c97df44 1721
lypinator 0:bb348c97df44 1722 /*@} end of group CMSIS_CoreDebug */
lypinator 0:bb348c97df44 1723
lypinator 0:bb348c97df44 1724
lypinator 0:bb348c97df44 1725 /**
lypinator 0:bb348c97df44 1726 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 1727 \defgroup CMSIS_core_bitfield Core register bit field macros
lypinator 0:bb348c97df44 1728 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
lypinator 0:bb348c97df44 1729 @{
lypinator 0:bb348c97df44 1730 */
lypinator 0:bb348c97df44 1731
lypinator 0:bb348c97df44 1732 /**
lypinator 0:bb348c97df44 1733 \brief Mask and shift a bit field value for use in a register bit range.
lypinator 0:bb348c97df44 1734 \param[in] field Name of the register bit field.
lypinator 0:bb348c97df44 1735 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
lypinator 0:bb348c97df44 1736 \return Masked and shifted value.
lypinator 0:bb348c97df44 1737 */
lypinator 0:bb348c97df44 1738 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
lypinator 0:bb348c97df44 1739
lypinator 0:bb348c97df44 1740 /**
lypinator 0:bb348c97df44 1741 \brief Mask and shift a register value to extract a bit filed value.
lypinator 0:bb348c97df44 1742 \param[in] field Name of the register bit field.
lypinator 0:bb348c97df44 1743 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
lypinator 0:bb348c97df44 1744 \return Masked and shifted bit field value.
lypinator 0:bb348c97df44 1745 */
lypinator 0:bb348c97df44 1746 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
lypinator 0:bb348c97df44 1747
lypinator 0:bb348c97df44 1748 /*@} end of group CMSIS_core_bitfield */
lypinator 0:bb348c97df44 1749
lypinator 0:bb348c97df44 1750
lypinator 0:bb348c97df44 1751 /**
lypinator 0:bb348c97df44 1752 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 1753 \defgroup CMSIS_core_base Core Definitions
lypinator 0:bb348c97df44 1754 \brief Definitions for base addresses, unions, and structures.
lypinator 0:bb348c97df44 1755 @{
lypinator 0:bb348c97df44 1756 */
lypinator 0:bb348c97df44 1757
lypinator 0:bb348c97df44 1758 /* Memory mapping of Core Hardware */
lypinator 0:bb348c97df44 1759 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
lypinator 0:bb348c97df44 1760 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
lypinator 0:bb348c97df44 1761 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
lypinator 0:bb348c97df44 1762 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
lypinator 0:bb348c97df44 1763 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
lypinator 0:bb348c97df44 1764 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
lypinator 0:bb348c97df44 1765 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
lypinator 0:bb348c97df44 1766 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
lypinator 0:bb348c97df44 1767
lypinator 0:bb348c97df44 1768 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
lypinator 0:bb348c97df44 1769 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
lypinator 0:bb348c97df44 1770 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
lypinator 0:bb348c97df44 1771 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
lypinator 0:bb348c97df44 1772 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
lypinator 0:bb348c97df44 1773 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
lypinator 0:bb348c97df44 1774 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
lypinator 0:bb348c97df44 1775 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
lypinator 0:bb348c97df44 1776
lypinator 0:bb348c97df44 1777 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
lypinator 0:bb348c97df44 1778 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
lypinator 0:bb348c97df44 1779 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
lypinator 0:bb348c97df44 1780 #endif
lypinator 0:bb348c97df44 1781
lypinator 0:bb348c97df44 1782 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
lypinator 0:bb348c97df44 1783 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
lypinator 0:bb348c97df44 1784
lypinator 0:bb348c97df44 1785 /*@} */
lypinator 0:bb348c97df44 1786
lypinator 0:bb348c97df44 1787
lypinator 0:bb348c97df44 1788
lypinator 0:bb348c97df44 1789 /*******************************************************************************
lypinator 0:bb348c97df44 1790 * Hardware Abstraction Layer
lypinator 0:bb348c97df44 1791 Core Function Interface contains:
lypinator 0:bb348c97df44 1792 - Core NVIC Functions
lypinator 0:bb348c97df44 1793 - Core SysTick Functions
lypinator 0:bb348c97df44 1794 - Core Debug Functions
lypinator 0:bb348c97df44 1795 - Core Register Access Functions
lypinator 0:bb348c97df44 1796 ******************************************************************************/
lypinator 0:bb348c97df44 1797 /**
lypinator 0:bb348c97df44 1798 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
lypinator 0:bb348c97df44 1799 */
lypinator 0:bb348c97df44 1800
lypinator 0:bb348c97df44 1801
lypinator 0:bb348c97df44 1802
lypinator 0:bb348c97df44 1803 /* ########################## NVIC functions #################################### */
lypinator 0:bb348c97df44 1804 /**
lypinator 0:bb348c97df44 1805 \ingroup CMSIS_Core_FunctionInterface
lypinator 0:bb348c97df44 1806 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
lypinator 0:bb348c97df44 1807 \brief Functions that manage interrupts and exceptions via the NVIC.
lypinator 0:bb348c97df44 1808 @{
lypinator 0:bb348c97df44 1809 */
lypinator 0:bb348c97df44 1810
lypinator 0:bb348c97df44 1811 #ifdef CMSIS_NVIC_VIRTUAL
lypinator 0:bb348c97df44 1812 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
lypinator 0:bb348c97df44 1813 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
lypinator 0:bb348c97df44 1814 #endif
lypinator 0:bb348c97df44 1815 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
lypinator 0:bb348c97df44 1816 #else
lypinator 0:bb348c97df44 1817 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
lypinator 0:bb348c97df44 1818 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
lypinator 0:bb348c97df44 1819 #define NVIC_EnableIRQ __NVIC_EnableIRQ
lypinator 0:bb348c97df44 1820 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
lypinator 0:bb348c97df44 1821 #define NVIC_DisableIRQ __NVIC_DisableIRQ
lypinator 0:bb348c97df44 1822 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
lypinator 0:bb348c97df44 1823 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
lypinator 0:bb348c97df44 1824 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
lypinator 0:bb348c97df44 1825 #define NVIC_GetActive __NVIC_GetActive
lypinator 0:bb348c97df44 1826 #define NVIC_SetPriority __NVIC_SetPriority
lypinator 0:bb348c97df44 1827 #define NVIC_GetPriority __NVIC_GetPriority
lypinator 0:bb348c97df44 1828 #define NVIC_SystemReset __NVIC_SystemReset
lypinator 0:bb348c97df44 1829 #endif /* CMSIS_NVIC_VIRTUAL */
lypinator 0:bb348c97df44 1830
lypinator 0:bb348c97df44 1831 #ifdef CMSIS_VECTAB_VIRTUAL
lypinator 0:bb348c97df44 1832 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
lypinator 0:bb348c97df44 1833 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
lypinator 0:bb348c97df44 1834 #endif
lypinator 0:bb348c97df44 1835 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
lypinator 0:bb348c97df44 1836 #else
lypinator 0:bb348c97df44 1837 #define NVIC_SetVector __NVIC_SetVector
lypinator 0:bb348c97df44 1838 #define NVIC_GetVector __NVIC_GetVector
lypinator 0:bb348c97df44 1839 #endif /* (CMSIS_VECTAB_VIRTUAL) */
lypinator 0:bb348c97df44 1840
lypinator 0:bb348c97df44 1841 #define NVIC_USER_IRQ_OFFSET 16
lypinator 0:bb348c97df44 1842
lypinator 0:bb348c97df44 1843
lypinator 0:bb348c97df44 1844
lypinator 0:bb348c97df44 1845 /**
lypinator 0:bb348c97df44 1846 \brief Set Priority Grouping
lypinator 0:bb348c97df44 1847 \details Sets the priority grouping field using the required unlock sequence.
lypinator 0:bb348c97df44 1848 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
lypinator 0:bb348c97df44 1849 Only values from 0..7 are used.
lypinator 0:bb348c97df44 1850 In case of a conflict between priority grouping and available
lypinator 0:bb348c97df44 1851 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
lypinator 0:bb348c97df44 1852 \param [in] PriorityGroup Priority grouping field.
lypinator 0:bb348c97df44 1853 */
lypinator 0:bb348c97df44 1854 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
lypinator 0:bb348c97df44 1855 {
lypinator 0:bb348c97df44 1856 uint32_t reg_value;
lypinator 0:bb348c97df44 1857 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
lypinator 0:bb348c97df44 1858
lypinator 0:bb348c97df44 1859 reg_value = SCB->AIRCR; /* read old register configuration */
lypinator 0:bb348c97df44 1860 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
lypinator 0:bb348c97df44 1861 reg_value = (reg_value |
lypinator 0:bb348c97df44 1862 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
lypinator 0:bb348c97df44 1863 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
lypinator 0:bb348c97df44 1864 SCB->AIRCR = reg_value;
lypinator 0:bb348c97df44 1865 }
lypinator 0:bb348c97df44 1866
lypinator 0:bb348c97df44 1867
lypinator 0:bb348c97df44 1868 /**
lypinator 0:bb348c97df44 1869 \brief Get Priority Grouping
lypinator 0:bb348c97df44 1870 \details Reads the priority grouping field from the NVIC Interrupt Controller.
lypinator 0:bb348c97df44 1871 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
lypinator 0:bb348c97df44 1872 */
lypinator 0:bb348c97df44 1873 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
lypinator 0:bb348c97df44 1874 {
lypinator 0:bb348c97df44 1875 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
lypinator 0:bb348c97df44 1876 }
lypinator 0:bb348c97df44 1877
lypinator 0:bb348c97df44 1878
lypinator 0:bb348c97df44 1879 /**
lypinator 0:bb348c97df44 1880 \brief Enable Interrupt
lypinator 0:bb348c97df44 1881 \details Enables a device specific interrupt in the NVIC interrupt controller.
lypinator 0:bb348c97df44 1882 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1883 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1884 */
lypinator 0:bb348c97df44 1885 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1886 {
lypinator 0:bb348c97df44 1887 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1888 {
lypinator 0:bb348c97df44 1889 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 1890 }
lypinator 0:bb348c97df44 1891 }
lypinator 0:bb348c97df44 1892
lypinator 0:bb348c97df44 1893
lypinator 0:bb348c97df44 1894 /**
lypinator 0:bb348c97df44 1895 \brief Get Interrupt Enable status
lypinator 0:bb348c97df44 1896 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
lypinator 0:bb348c97df44 1897 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1898 \return 0 Interrupt is not enabled.
lypinator 0:bb348c97df44 1899 \return 1 Interrupt is enabled.
lypinator 0:bb348c97df44 1900 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1901 */
lypinator 0:bb348c97df44 1902 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1903 {
lypinator 0:bb348c97df44 1904 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1905 {
lypinator 0:bb348c97df44 1906 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
lypinator 0:bb348c97df44 1907 }
lypinator 0:bb348c97df44 1908 else
lypinator 0:bb348c97df44 1909 {
lypinator 0:bb348c97df44 1910 return(0U);
lypinator 0:bb348c97df44 1911 }
lypinator 0:bb348c97df44 1912 }
lypinator 0:bb348c97df44 1913
lypinator 0:bb348c97df44 1914
lypinator 0:bb348c97df44 1915 /**
lypinator 0:bb348c97df44 1916 \brief Disable Interrupt
lypinator 0:bb348c97df44 1917 \details Disables a device specific interrupt in the NVIC interrupt controller.
lypinator 0:bb348c97df44 1918 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1919 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1920 */
lypinator 0:bb348c97df44 1921 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1922 {
lypinator 0:bb348c97df44 1923 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1924 {
lypinator 0:bb348c97df44 1925 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 1926 __DSB();
lypinator 0:bb348c97df44 1927 __ISB();
lypinator 0:bb348c97df44 1928 }
lypinator 0:bb348c97df44 1929 }
lypinator 0:bb348c97df44 1930
lypinator 0:bb348c97df44 1931
lypinator 0:bb348c97df44 1932 /**
lypinator 0:bb348c97df44 1933 \brief Get Pending Interrupt
lypinator 0:bb348c97df44 1934 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
lypinator 0:bb348c97df44 1935 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1936 \return 0 Interrupt status is not pending.
lypinator 0:bb348c97df44 1937 \return 1 Interrupt status is pending.
lypinator 0:bb348c97df44 1938 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1939 */
lypinator 0:bb348c97df44 1940 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1941 {
lypinator 0:bb348c97df44 1942 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1943 {
lypinator 0:bb348c97df44 1944 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
lypinator 0:bb348c97df44 1945 }
lypinator 0:bb348c97df44 1946 else
lypinator 0:bb348c97df44 1947 {
lypinator 0:bb348c97df44 1948 return(0U);
lypinator 0:bb348c97df44 1949 }
lypinator 0:bb348c97df44 1950 }
lypinator 0:bb348c97df44 1951
lypinator 0:bb348c97df44 1952
lypinator 0:bb348c97df44 1953 /**
lypinator 0:bb348c97df44 1954 \brief Set Pending Interrupt
lypinator 0:bb348c97df44 1955 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
lypinator 0:bb348c97df44 1956 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1957 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1958 */
lypinator 0:bb348c97df44 1959 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1960 {
lypinator 0:bb348c97df44 1961 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1962 {
lypinator 0:bb348c97df44 1963 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 1964 }
lypinator 0:bb348c97df44 1965 }
lypinator 0:bb348c97df44 1966
lypinator 0:bb348c97df44 1967
lypinator 0:bb348c97df44 1968 /**
lypinator 0:bb348c97df44 1969 \brief Clear Pending Interrupt
lypinator 0:bb348c97df44 1970 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
lypinator 0:bb348c97df44 1971 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1972 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1973 */
lypinator 0:bb348c97df44 1974 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1975 {
lypinator 0:bb348c97df44 1976 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1977 {
lypinator 0:bb348c97df44 1978 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 1979 }
lypinator 0:bb348c97df44 1980 }
lypinator 0:bb348c97df44 1981
lypinator 0:bb348c97df44 1982
lypinator 0:bb348c97df44 1983 /**
lypinator 0:bb348c97df44 1984 \brief Get Active Interrupt
lypinator 0:bb348c97df44 1985 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
lypinator 0:bb348c97df44 1986 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1987 \return 0 Interrupt status is not active.
lypinator 0:bb348c97df44 1988 \return 1 Interrupt status is active.
lypinator 0:bb348c97df44 1989 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1990 */
lypinator 0:bb348c97df44 1991 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1992 {
lypinator 0:bb348c97df44 1993 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1994 {
lypinator 0:bb348c97df44 1995 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
lypinator 0:bb348c97df44 1996 }
lypinator 0:bb348c97df44 1997 else
lypinator 0:bb348c97df44 1998 {
lypinator 0:bb348c97df44 1999 return(0U);
lypinator 0:bb348c97df44 2000 }
lypinator 0:bb348c97df44 2001 }
lypinator 0:bb348c97df44 2002
lypinator 0:bb348c97df44 2003
lypinator 0:bb348c97df44 2004 /**
lypinator 0:bb348c97df44 2005 \brief Set Interrupt Priority
lypinator 0:bb348c97df44 2006 \details Sets the priority of a device specific interrupt or a processor exception.
lypinator 0:bb348c97df44 2007 The interrupt number can be positive to specify a device specific interrupt,
lypinator 0:bb348c97df44 2008 or negative to specify a processor exception.
lypinator 0:bb348c97df44 2009 \param [in] IRQn Interrupt number.
lypinator 0:bb348c97df44 2010 \param [in] priority Priority to set.
lypinator 0:bb348c97df44 2011 \note The priority cannot be set for every processor exception.
lypinator 0:bb348c97df44 2012 */
lypinator 0:bb348c97df44 2013 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
lypinator 0:bb348c97df44 2014 {
lypinator 0:bb348c97df44 2015 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 2016 {
lypinator 0:bb348c97df44 2017 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
lypinator 0:bb348c97df44 2018 }
lypinator 0:bb348c97df44 2019 else
lypinator 0:bb348c97df44 2020 {
lypinator 0:bb348c97df44 2021 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
lypinator 0:bb348c97df44 2022 }
lypinator 0:bb348c97df44 2023 }
lypinator 0:bb348c97df44 2024
lypinator 0:bb348c97df44 2025
lypinator 0:bb348c97df44 2026 /**
lypinator 0:bb348c97df44 2027 \brief Get Interrupt Priority
lypinator 0:bb348c97df44 2028 \details Reads the priority of a device specific interrupt or a processor exception.
lypinator 0:bb348c97df44 2029 The interrupt number can be positive to specify a device specific interrupt,
lypinator 0:bb348c97df44 2030 or negative to specify a processor exception.
lypinator 0:bb348c97df44 2031 \param [in] IRQn Interrupt number.
lypinator 0:bb348c97df44 2032 \return Interrupt Priority.
lypinator 0:bb348c97df44 2033 Value is aligned automatically to the implemented priority bits of the microcontroller.
lypinator 0:bb348c97df44 2034 */
lypinator 0:bb348c97df44 2035 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
lypinator 0:bb348c97df44 2036 {
lypinator 0:bb348c97df44 2037
lypinator 0:bb348c97df44 2038 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 2039 {
lypinator 0:bb348c97df44 2040 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
lypinator 0:bb348c97df44 2041 }
lypinator 0:bb348c97df44 2042 else
lypinator 0:bb348c97df44 2043 {
lypinator 0:bb348c97df44 2044 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
lypinator 0:bb348c97df44 2045 }
lypinator 0:bb348c97df44 2046 }
lypinator 0:bb348c97df44 2047
lypinator 0:bb348c97df44 2048
lypinator 0:bb348c97df44 2049 /**
lypinator 0:bb348c97df44 2050 \brief Encode Priority
lypinator 0:bb348c97df44 2051 \details Encodes the priority for an interrupt with the given priority group,
lypinator 0:bb348c97df44 2052 preemptive priority value, and subpriority value.
lypinator 0:bb348c97df44 2053 In case of a conflict between priority grouping and available
lypinator 0:bb348c97df44 2054 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
lypinator 0:bb348c97df44 2055 \param [in] PriorityGroup Used priority group.
lypinator 0:bb348c97df44 2056 \param [in] PreemptPriority Preemptive priority value (starting from 0).
lypinator 0:bb348c97df44 2057 \param [in] SubPriority Subpriority value (starting from 0).
lypinator 0:bb348c97df44 2058 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
lypinator 0:bb348c97df44 2059 */
lypinator 0:bb348c97df44 2060 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
lypinator 0:bb348c97df44 2061 {
lypinator 0:bb348c97df44 2062 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
lypinator 0:bb348c97df44 2063 uint32_t PreemptPriorityBits;
lypinator 0:bb348c97df44 2064 uint32_t SubPriorityBits;
lypinator 0:bb348c97df44 2065
lypinator 0:bb348c97df44 2066 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
lypinator 0:bb348c97df44 2067 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
lypinator 0:bb348c97df44 2068
lypinator 0:bb348c97df44 2069 return (
lypinator 0:bb348c97df44 2070 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
lypinator 0:bb348c97df44 2071 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
lypinator 0:bb348c97df44 2072 );
lypinator 0:bb348c97df44 2073 }
lypinator 0:bb348c97df44 2074
lypinator 0:bb348c97df44 2075
lypinator 0:bb348c97df44 2076 /**
lypinator 0:bb348c97df44 2077 \brief Decode Priority
lypinator 0:bb348c97df44 2078 \details Decodes an interrupt priority value with a given priority group to
lypinator 0:bb348c97df44 2079 preemptive priority value and subpriority value.
lypinator 0:bb348c97df44 2080 In case of a conflict between priority grouping and available
lypinator 0:bb348c97df44 2081 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
lypinator 0:bb348c97df44 2082 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
lypinator 0:bb348c97df44 2083 \param [in] PriorityGroup Used priority group.
lypinator 0:bb348c97df44 2084 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
lypinator 0:bb348c97df44 2085 \param [out] pSubPriority Subpriority value (starting from 0).
lypinator 0:bb348c97df44 2086 */
lypinator 0:bb348c97df44 2087 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
lypinator 0:bb348c97df44 2088 {
lypinator 0:bb348c97df44 2089 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
lypinator 0:bb348c97df44 2090 uint32_t PreemptPriorityBits;
lypinator 0:bb348c97df44 2091 uint32_t SubPriorityBits;
lypinator 0:bb348c97df44 2092
lypinator 0:bb348c97df44 2093 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
lypinator 0:bb348c97df44 2094 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
lypinator 0:bb348c97df44 2095
lypinator 0:bb348c97df44 2096 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
lypinator 0:bb348c97df44 2097 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
lypinator 0:bb348c97df44 2098 }
lypinator 0:bb348c97df44 2099
lypinator 0:bb348c97df44 2100
lypinator 0:bb348c97df44 2101 /**
lypinator 0:bb348c97df44 2102 \brief Set Interrupt Vector
lypinator 0:bb348c97df44 2103 \details Sets an interrupt vector in SRAM based interrupt vector table.
lypinator 0:bb348c97df44 2104 The interrupt number can be positive to specify a device specific interrupt,
lypinator 0:bb348c97df44 2105 or negative to specify a processor exception.
lypinator 0:bb348c97df44 2106 VTOR must been relocated to SRAM before.
lypinator 0:bb348c97df44 2107 \param [in] IRQn Interrupt number
lypinator 0:bb348c97df44 2108 \param [in] vector Address of interrupt handler function
lypinator 0:bb348c97df44 2109 */
lypinator 0:bb348c97df44 2110 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
lypinator 0:bb348c97df44 2111 {
lypinator 0:bb348c97df44 2112 uint32_t *vectors = (uint32_t *)SCB->VTOR;
lypinator 0:bb348c97df44 2113 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
lypinator 0:bb348c97df44 2114 }
lypinator 0:bb348c97df44 2115
lypinator 0:bb348c97df44 2116
lypinator 0:bb348c97df44 2117 /**
lypinator 0:bb348c97df44 2118 \brief Get Interrupt Vector
lypinator 0:bb348c97df44 2119 \details Reads an interrupt vector from interrupt vector table.
lypinator 0:bb348c97df44 2120 The interrupt number can be positive to specify a device specific interrupt,
lypinator 0:bb348c97df44 2121 or negative to specify a processor exception.
lypinator 0:bb348c97df44 2122 \param [in] IRQn Interrupt number.
lypinator 0:bb348c97df44 2123 \return Address of interrupt handler function
lypinator 0:bb348c97df44 2124 */
lypinator 0:bb348c97df44 2125 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
lypinator 0:bb348c97df44 2126 {
lypinator 0:bb348c97df44 2127 uint32_t *vectors = (uint32_t *)SCB->VTOR;
lypinator 0:bb348c97df44 2128 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
lypinator 0:bb348c97df44 2129 }
lypinator 0:bb348c97df44 2130
lypinator 0:bb348c97df44 2131
lypinator 0:bb348c97df44 2132 /**
lypinator 0:bb348c97df44 2133 \brief System Reset
lypinator 0:bb348c97df44 2134 \details Initiates a system reset request to reset the MCU.
lypinator 0:bb348c97df44 2135 */
lypinator 0:bb348c97df44 2136 __STATIC_INLINE void __NVIC_SystemReset(void)
lypinator 0:bb348c97df44 2137 {
lypinator 0:bb348c97df44 2138 __DSB(); /* Ensure all outstanding memory accesses included
lypinator 0:bb348c97df44 2139 buffered write are completed before reset */
lypinator 0:bb348c97df44 2140 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
lypinator 0:bb348c97df44 2141 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
lypinator 0:bb348c97df44 2142 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
lypinator 0:bb348c97df44 2143 __DSB(); /* Ensure completion of memory access */
lypinator 0:bb348c97df44 2144
lypinator 0:bb348c97df44 2145 for(;;) /* wait until reset */
lypinator 0:bb348c97df44 2146 {
lypinator 0:bb348c97df44 2147 __NOP();
lypinator 0:bb348c97df44 2148 }
lypinator 0:bb348c97df44 2149 }
lypinator 0:bb348c97df44 2150
lypinator 0:bb348c97df44 2151 /*@} end of CMSIS_Core_NVICFunctions */
lypinator 0:bb348c97df44 2152
lypinator 0:bb348c97df44 2153 /* ########################## MPU functions #################################### */
lypinator 0:bb348c97df44 2154
lypinator 0:bb348c97df44 2155 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
lypinator 0:bb348c97df44 2156
lypinator 0:bb348c97df44 2157 #include "mpu_armv7.h"
lypinator 0:bb348c97df44 2158
lypinator 0:bb348c97df44 2159 #endif
lypinator 0:bb348c97df44 2160
lypinator 0:bb348c97df44 2161 /* ########################## FPU functions #################################### */
lypinator 0:bb348c97df44 2162 /**
lypinator 0:bb348c97df44 2163 \ingroup CMSIS_Core_FunctionInterface
lypinator 0:bb348c97df44 2164 \defgroup CMSIS_Core_FpuFunctions FPU Functions
lypinator 0:bb348c97df44 2165 \brief Function that provides FPU type.
lypinator 0:bb348c97df44 2166 @{
lypinator 0:bb348c97df44 2167 */
lypinator 0:bb348c97df44 2168
lypinator 0:bb348c97df44 2169 /**
lypinator 0:bb348c97df44 2170 \brief get FPU type
lypinator 0:bb348c97df44 2171 \details returns the FPU type
lypinator 0:bb348c97df44 2172 \returns
lypinator 0:bb348c97df44 2173 - \b 0: No FPU
lypinator 0:bb348c97df44 2174 - \b 1: Single precision FPU
lypinator 0:bb348c97df44 2175 - \b 2: Double + Single precision FPU
lypinator 0:bb348c97df44 2176 */
lypinator 0:bb348c97df44 2177 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
lypinator 0:bb348c97df44 2178 {
lypinator 0:bb348c97df44 2179 uint32_t mvfr0;
lypinator 0:bb348c97df44 2180
lypinator 0:bb348c97df44 2181 mvfr0 = SCB->MVFR0;
lypinator 0:bb348c97df44 2182 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
lypinator 0:bb348c97df44 2183 {
lypinator 0:bb348c97df44 2184 return 2U; /* Double + Single precision FPU */
lypinator 0:bb348c97df44 2185 }
lypinator 0:bb348c97df44 2186 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
lypinator 0:bb348c97df44 2187 {
lypinator 0:bb348c97df44 2188 return 1U; /* Single precision FPU */
lypinator 0:bb348c97df44 2189 }
lypinator 0:bb348c97df44 2190 else
lypinator 0:bb348c97df44 2191 {
lypinator 0:bb348c97df44 2192 return 0U; /* No FPU */
lypinator 0:bb348c97df44 2193 }
lypinator 0:bb348c97df44 2194 }
lypinator 0:bb348c97df44 2195
lypinator 0:bb348c97df44 2196
lypinator 0:bb348c97df44 2197 /*@} end of CMSIS_Core_FpuFunctions */
lypinator 0:bb348c97df44 2198
lypinator 0:bb348c97df44 2199
lypinator 0:bb348c97df44 2200
lypinator 0:bb348c97df44 2201 /* ########################## Cache functions #################################### */
lypinator 0:bb348c97df44 2202 /**
lypinator 0:bb348c97df44 2203 \ingroup CMSIS_Core_FunctionInterface
lypinator 0:bb348c97df44 2204 \defgroup CMSIS_Core_CacheFunctions Cache Functions
lypinator 0:bb348c97df44 2205 \brief Functions that configure Instruction and Data cache.
lypinator 0:bb348c97df44 2206 @{
lypinator 0:bb348c97df44 2207 */
lypinator 0:bb348c97df44 2208
lypinator 0:bb348c97df44 2209 /* Cache Size ID Register Macros */
lypinator 0:bb348c97df44 2210 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
lypinator 0:bb348c97df44 2211 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
lypinator 0:bb348c97df44 2212
lypinator 0:bb348c97df44 2213
lypinator 0:bb348c97df44 2214 /**
lypinator 0:bb348c97df44 2215 \brief Enable I-Cache
lypinator 0:bb348c97df44 2216 \details Turns on I-Cache
lypinator 0:bb348c97df44 2217 */
lypinator 0:bb348c97df44 2218 __STATIC_INLINE void SCB_EnableICache (void)
lypinator 0:bb348c97df44 2219 {
lypinator 0:bb348c97df44 2220 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
lypinator 0:bb348c97df44 2221 __DSB();
lypinator 0:bb348c97df44 2222 __ISB();
lypinator 0:bb348c97df44 2223 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
lypinator 0:bb348c97df44 2224 __DSB();
lypinator 0:bb348c97df44 2225 __ISB();
lypinator 0:bb348c97df44 2226 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
lypinator 0:bb348c97df44 2227 __DSB();
lypinator 0:bb348c97df44 2228 __ISB();
lypinator 0:bb348c97df44 2229 #endif
lypinator 0:bb348c97df44 2230 }
lypinator 0:bb348c97df44 2231
lypinator 0:bb348c97df44 2232
lypinator 0:bb348c97df44 2233 /**
lypinator 0:bb348c97df44 2234 \brief Disable I-Cache
lypinator 0:bb348c97df44 2235 \details Turns off I-Cache
lypinator 0:bb348c97df44 2236 */
lypinator 0:bb348c97df44 2237 __STATIC_INLINE void SCB_DisableICache (void)
lypinator 0:bb348c97df44 2238 {
lypinator 0:bb348c97df44 2239 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
lypinator 0:bb348c97df44 2240 __DSB();
lypinator 0:bb348c97df44 2241 __ISB();
lypinator 0:bb348c97df44 2242 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
lypinator 0:bb348c97df44 2243 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
lypinator 0:bb348c97df44 2244 __DSB();
lypinator 0:bb348c97df44 2245 __ISB();
lypinator 0:bb348c97df44 2246 #endif
lypinator 0:bb348c97df44 2247 }
lypinator 0:bb348c97df44 2248
lypinator 0:bb348c97df44 2249
lypinator 0:bb348c97df44 2250 /**
lypinator 0:bb348c97df44 2251 \brief Invalidate I-Cache
lypinator 0:bb348c97df44 2252 \details Invalidates I-Cache
lypinator 0:bb348c97df44 2253 */
lypinator 0:bb348c97df44 2254 __STATIC_INLINE void SCB_InvalidateICache (void)
lypinator 0:bb348c97df44 2255 {
lypinator 0:bb348c97df44 2256 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
lypinator 0:bb348c97df44 2257 __DSB();
lypinator 0:bb348c97df44 2258 __ISB();
lypinator 0:bb348c97df44 2259 SCB->ICIALLU = 0UL;
lypinator 0:bb348c97df44 2260 __DSB();
lypinator 0:bb348c97df44 2261 __ISB();
lypinator 0:bb348c97df44 2262 #endif
lypinator 0:bb348c97df44 2263 }
lypinator 0:bb348c97df44 2264
lypinator 0:bb348c97df44 2265
lypinator 0:bb348c97df44 2266 /**
lypinator 0:bb348c97df44 2267 \brief Enable D-Cache
lypinator 0:bb348c97df44 2268 \details Turns on D-Cache
lypinator 0:bb348c97df44 2269 */
lypinator 0:bb348c97df44 2270 __STATIC_INLINE void SCB_EnableDCache (void)
lypinator 0:bb348c97df44 2271 {
lypinator 0:bb348c97df44 2272 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
lypinator 0:bb348c97df44 2273 uint32_t ccsidr;
lypinator 0:bb348c97df44 2274 uint32_t sets;
lypinator 0:bb348c97df44 2275 uint32_t ways;
lypinator 0:bb348c97df44 2276
lypinator 0:bb348c97df44 2277 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
lypinator 0:bb348c97df44 2278 __DSB();
lypinator 0:bb348c97df44 2279
lypinator 0:bb348c97df44 2280 ccsidr = SCB->CCSIDR;
lypinator 0:bb348c97df44 2281
lypinator 0:bb348c97df44 2282 /* invalidate D-Cache */
lypinator 0:bb348c97df44 2283 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
lypinator 0:bb348c97df44 2284 do {
lypinator 0:bb348c97df44 2285 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
lypinator 0:bb348c97df44 2286 do {
lypinator 0:bb348c97df44 2287 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
lypinator 0:bb348c97df44 2288 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
lypinator 0:bb348c97df44 2289 #if defined ( __CC_ARM )
lypinator 0:bb348c97df44 2290 __schedule_barrier();
lypinator 0:bb348c97df44 2291 #endif
lypinator 0:bb348c97df44 2292 } while (ways-- != 0U);
lypinator 0:bb348c97df44 2293 } while(sets-- != 0U);
lypinator 0:bb348c97df44 2294 __DSB();
lypinator 0:bb348c97df44 2295
lypinator 0:bb348c97df44 2296 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
lypinator 0:bb348c97df44 2297
lypinator 0:bb348c97df44 2298 __DSB();
lypinator 0:bb348c97df44 2299 __ISB();
lypinator 0:bb348c97df44 2300 #endif
lypinator 0:bb348c97df44 2301 }
lypinator 0:bb348c97df44 2302
lypinator 0:bb348c97df44 2303
lypinator 0:bb348c97df44 2304 /**
lypinator 0:bb348c97df44 2305 \brief Disable D-Cache
lypinator 0:bb348c97df44 2306 \details Turns off D-Cache
lypinator 0:bb348c97df44 2307 */
lypinator 0:bb348c97df44 2308 __STATIC_INLINE void SCB_DisableDCache (void)
lypinator 0:bb348c97df44 2309 {
lypinator 0:bb348c97df44 2310 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
lypinator 0:bb348c97df44 2311 register uint32_t ccsidr;
lypinator 0:bb348c97df44 2312 register uint32_t sets;
lypinator 0:bb348c97df44 2313 register uint32_t ways;
lypinator 0:bb348c97df44 2314
lypinator 0:bb348c97df44 2315 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
lypinator 0:bb348c97df44 2316 __DSB();
lypinator 0:bb348c97df44 2317
lypinator 0:bb348c97df44 2318 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
lypinator 0:bb348c97df44 2319 __DSB();
lypinator 0:bb348c97df44 2320
lypinator 0:bb348c97df44 2321 ccsidr = SCB->CCSIDR;
lypinator 0:bb348c97df44 2322
lypinator 0:bb348c97df44 2323 /* clean & invalidate D-Cache */
lypinator 0:bb348c97df44 2324 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
lypinator 0:bb348c97df44 2325 do {
lypinator 0:bb348c97df44 2326 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
lypinator 0:bb348c97df44 2327 do {
lypinator 0:bb348c97df44 2328 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
lypinator 0:bb348c97df44 2329 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
lypinator 0:bb348c97df44 2330 #if defined ( __CC_ARM )
lypinator 0:bb348c97df44 2331 __schedule_barrier();
lypinator 0:bb348c97df44 2332 #endif
lypinator 0:bb348c97df44 2333 } while (ways-- != 0U);
lypinator 0:bb348c97df44 2334 } while(sets-- != 0U);
lypinator 0:bb348c97df44 2335
lypinator 0:bb348c97df44 2336 __DSB();
lypinator 0:bb348c97df44 2337 __ISB();
lypinator 0:bb348c97df44 2338 #endif
lypinator 0:bb348c97df44 2339 }
lypinator 0:bb348c97df44 2340
lypinator 0:bb348c97df44 2341
lypinator 0:bb348c97df44 2342 /**
lypinator 0:bb348c97df44 2343 \brief Invalidate D-Cache
lypinator 0:bb348c97df44 2344 \details Invalidates D-Cache
lypinator 0:bb348c97df44 2345 */
lypinator 0:bb348c97df44 2346 __STATIC_INLINE void SCB_InvalidateDCache (void)
lypinator 0:bb348c97df44 2347 {
lypinator 0:bb348c97df44 2348 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
lypinator 0:bb348c97df44 2349 uint32_t ccsidr;
lypinator 0:bb348c97df44 2350 uint32_t sets;
lypinator 0:bb348c97df44 2351 uint32_t ways;
lypinator 0:bb348c97df44 2352
lypinator 0:bb348c97df44 2353 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
lypinator 0:bb348c97df44 2354 __DSB();
lypinator 0:bb348c97df44 2355
lypinator 0:bb348c97df44 2356 ccsidr = SCB->CCSIDR;
lypinator 0:bb348c97df44 2357
lypinator 0:bb348c97df44 2358 /* invalidate D-Cache */
lypinator 0:bb348c97df44 2359 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
lypinator 0:bb348c97df44 2360 do {
lypinator 0:bb348c97df44 2361 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
lypinator 0:bb348c97df44 2362 do {
lypinator 0:bb348c97df44 2363 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
lypinator 0:bb348c97df44 2364 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
lypinator 0:bb348c97df44 2365 #if defined ( __CC_ARM )
lypinator 0:bb348c97df44 2366 __schedule_barrier();
lypinator 0:bb348c97df44 2367 #endif
lypinator 0:bb348c97df44 2368 } while (ways-- != 0U);
lypinator 0:bb348c97df44 2369 } while(sets-- != 0U);
lypinator 0:bb348c97df44 2370
lypinator 0:bb348c97df44 2371 __DSB();
lypinator 0:bb348c97df44 2372 __ISB();
lypinator 0:bb348c97df44 2373 #endif
lypinator 0:bb348c97df44 2374 }
lypinator 0:bb348c97df44 2375
lypinator 0:bb348c97df44 2376
lypinator 0:bb348c97df44 2377 /**
lypinator 0:bb348c97df44 2378 \brief Clean D-Cache
lypinator 0:bb348c97df44 2379 \details Cleans D-Cache
lypinator 0:bb348c97df44 2380 */
lypinator 0:bb348c97df44 2381 __STATIC_INLINE void SCB_CleanDCache (void)
lypinator 0:bb348c97df44 2382 {
lypinator 0:bb348c97df44 2383 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
lypinator 0:bb348c97df44 2384 uint32_t ccsidr;
lypinator 0:bb348c97df44 2385 uint32_t sets;
lypinator 0:bb348c97df44 2386 uint32_t ways;
lypinator 0:bb348c97df44 2387
lypinator 0:bb348c97df44 2388 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
lypinator 0:bb348c97df44 2389 __DSB();
lypinator 0:bb348c97df44 2390
lypinator 0:bb348c97df44 2391 ccsidr = SCB->CCSIDR;
lypinator 0:bb348c97df44 2392
lypinator 0:bb348c97df44 2393 /* clean D-Cache */
lypinator 0:bb348c97df44 2394 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
lypinator 0:bb348c97df44 2395 do {
lypinator 0:bb348c97df44 2396 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
lypinator 0:bb348c97df44 2397 do {
lypinator 0:bb348c97df44 2398 SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
lypinator 0:bb348c97df44 2399 ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
lypinator 0:bb348c97df44 2400 #if defined ( __CC_ARM )
lypinator 0:bb348c97df44 2401 __schedule_barrier();
lypinator 0:bb348c97df44 2402 #endif
lypinator 0:bb348c97df44 2403 } while (ways-- != 0U);
lypinator 0:bb348c97df44 2404 } while(sets-- != 0U);
lypinator 0:bb348c97df44 2405
lypinator 0:bb348c97df44 2406 __DSB();
lypinator 0:bb348c97df44 2407 __ISB();
lypinator 0:bb348c97df44 2408 #endif
lypinator 0:bb348c97df44 2409 }
lypinator 0:bb348c97df44 2410
lypinator 0:bb348c97df44 2411
lypinator 0:bb348c97df44 2412 /**
lypinator 0:bb348c97df44 2413 \brief Clean & Invalidate D-Cache
lypinator 0:bb348c97df44 2414 \details Cleans and Invalidates D-Cache
lypinator 0:bb348c97df44 2415 */
lypinator 0:bb348c97df44 2416 __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
lypinator 0:bb348c97df44 2417 {
lypinator 0:bb348c97df44 2418 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
lypinator 0:bb348c97df44 2419 uint32_t ccsidr;
lypinator 0:bb348c97df44 2420 uint32_t sets;
lypinator 0:bb348c97df44 2421 uint32_t ways;
lypinator 0:bb348c97df44 2422
lypinator 0:bb348c97df44 2423 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
lypinator 0:bb348c97df44 2424 __DSB();
lypinator 0:bb348c97df44 2425
lypinator 0:bb348c97df44 2426 ccsidr = SCB->CCSIDR;
lypinator 0:bb348c97df44 2427
lypinator 0:bb348c97df44 2428 /* clean & invalidate D-Cache */
lypinator 0:bb348c97df44 2429 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
lypinator 0:bb348c97df44 2430 do {
lypinator 0:bb348c97df44 2431 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
lypinator 0:bb348c97df44 2432 do {
lypinator 0:bb348c97df44 2433 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
lypinator 0:bb348c97df44 2434 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
lypinator 0:bb348c97df44 2435 #if defined ( __CC_ARM )
lypinator 0:bb348c97df44 2436 __schedule_barrier();
lypinator 0:bb348c97df44 2437 #endif
lypinator 0:bb348c97df44 2438 } while (ways-- != 0U);
lypinator 0:bb348c97df44 2439 } while(sets-- != 0U);
lypinator 0:bb348c97df44 2440
lypinator 0:bb348c97df44 2441 __DSB();
lypinator 0:bb348c97df44 2442 __ISB();
lypinator 0:bb348c97df44 2443 #endif
lypinator 0:bb348c97df44 2444 }
lypinator 0:bb348c97df44 2445
lypinator 0:bb348c97df44 2446
lypinator 0:bb348c97df44 2447 /**
lypinator 0:bb348c97df44 2448 \brief D-Cache Invalidate by address
lypinator 0:bb348c97df44 2449 \details Invalidates D-Cache for the given address
lypinator 0:bb348c97df44 2450 \param[in] addr address (aligned to 32-byte boundary)
lypinator 0:bb348c97df44 2451 \param[in] dsize size of memory block (in number of bytes)
lypinator 0:bb348c97df44 2452 */
lypinator 0:bb348c97df44 2453 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
lypinator 0:bb348c97df44 2454 {
lypinator 0:bb348c97df44 2455 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
lypinator 0:bb348c97df44 2456 int32_t op_size = dsize;
lypinator 0:bb348c97df44 2457 uint32_t op_addr = (uint32_t)addr;
lypinator 0:bb348c97df44 2458 int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
lypinator 0:bb348c97df44 2459
lypinator 0:bb348c97df44 2460 __DSB();
lypinator 0:bb348c97df44 2461
lypinator 0:bb348c97df44 2462 while (op_size > 0) {
lypinator 0:bb348c97df44 2463 SCB->DCIMVAC = op_addr;
lypinator 0:bb348c97df44 2464 op_addr += (uint32_t)linesize;
lypinator 0:bb348c97df44 2465 op_size -= linesize;
lypinator 0:bb348c97df44 2466 }
lypinator 0:bb348c97df44 2467
lypinator 0:bb348c97df44 2468 __DSB();
lypinator 0:bb348c97df44 2469 __ISB();
lypinator 0:bb348c97df44 2470 #endif
lypinator 0:bb348c97df44 2471 }
lypinator 0:bb348c97df44 2472
lypinator 0:bb348c97df44 2473
lypinator 0:bb348c97df44 2474 /**
lypinator 0:bb348c97df44 2475 \brief D-Cache Clean by address
lypinator 0:bb348c97df44 2476 \details Cleans D-Cache for the given address
lypinator 0:bb348c97df44 2477 \param[in] addr address (aligned to 32-byte boundary)
lypinator 0:bb348c97df44 2478 \param[in] dsize size of memory block (in number of bytes)
lypinator 0:bb348c97df44 2479 */
lypinator 0:bb348c97df44 2480 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
lypinator 0:bb348c97df44 2481 {
lypinator 0:bb348c97df44 2482 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
lypinator 0:bb348c97df44 2483 int32_t op_size = dsize;
lypinator 0:bb348c97df44 2484 uint32_t op_addr = (uint32_t) addr;
lypinator 0:bb348c97df44 2485 int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
lypinator 0:bb348c97df44 2486
lypinator 0:bb348c97df44 2487 __DSB();
lypinator 0:bb348c97df44 2488
lypinator 0:bb348c97df44 2489 while (op_size > 0) {
lypinator 0:bb348c97df44 2490 SCB->DCCMVAC = op_addr;
lypinator 0:bb348c97df44 2491 op_addr += (uint32_t)linesize;
lypinator 0:bb348c97df44 2492 op_size -= linesize;
lypinator 0:bb348c97df44 2493 }
lypinator 0:bb348c97df44 2494
lypinator 0:bb348c97df44 2495 __DSB();
lypinator 0:bb348c97df44 2496 __ISB();
lypinator 0:bb348c97df44 2497 #endif
lypinator 0:bb348c97df44 2498 }
lypinator 0:bb348c97df44 2499
lypinator 0:bb348c97df44 2500
lypinator 0:bb348c97df44 2501 /**
lypinator 0:bb348c97df44 2502 \brief D-Cache Clean and Invalidate by address
lypinator 0:bb348c97df44 2503 \details Cleans and invalidates D_Cache for the given address
lypinator 0:bb348c97df44 2504 \param[in] addr address (aligned to 32-byte boundary)
lypinator 0:bb348c97df44 2505 \param[in] dsize size of memory block (in number of bytes)
lypinator 0:bb348c97df44 2506 */
lypinator 0:bb348c97df44 2507 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
lypinator 0:bb348c97df44 2508 {
lypinator 0:bb348c97df44 2509 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
lypinator 0:bb348c97df44 2510 int32_t op_size = dsize;
lypinator 0:bb348c97df44 2511 uint32_t op_addr = (uint32_t) addr;
lypinator 0:bb348c97df44 2512 int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
lypinator 0:bb348c97df44 2513
lypinator 0:bb348c97df44 2514 __DSB();
lypinator 0:bb348c97df44 2515
lypinator 0:bb348c97df44 2516 while (op_size > 0) {
lypinator 0:bb348c97df44 2517 SCB->DCCIMVAC = op_addr;
lypinator 0:bb348c97df44 2518 op_addr += (uint32_t)linesize;
lypinator 0:bb348c97df44 2519 op_size -= linesize;
lypinator 0:bb348c97df44 2520 }
lypinator 0:bb348c97df44 2521
lypinator 0:bb348c97df44 2522 __DSB();
lypinator 0:bb348c97df44 2523 __ISB();
lypinator 0:bb348c97df44 2524 #endif
lypinator 0:bb348c97df44 2525 }
lypinator 0:bb348c97df44 2526
lypinator 0:bb348c97df44 2527
lypinator 0:bb348c97df44 2528 /*@} end of CMSIS_Core_CacheFunctions */
lypinator 0:bb348c97df44 2529
lypinator 0:bb348c97df44 2530
lypinator 0:bb348c97df44 2531
lypinator 0:bb348c97df44 2532 /* ################################## SysTick function ############################################ */
lypinator 0:bb348c97df44 2533 /**
lypinator 0:bb348c97df44 2534 \ingroup CMSIS_Core_FunctionInterface
lypinator 0:bb348c97df44 2535 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
lypinator 0:bb348c97df44 2536 \brief Functions that configure the System.
lypinator 0:bb348c97df44 2537 @{
lypinator 0:bb348c97df44 2538 */
lypinator 0:bb348c97df44 2539
lypinator 0:bb348c97df44 2540 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
lypinator 0:bb348c97df44 2541
lypinator 0:bb348c97df44 2542 /**
lypinator 0:bb348c97df44 2543 \brief System Tick Configuration
lypinator 0:bb348c97df44 2544 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
lypinator 0:bb348c97df44 2545 Counter is in free running mode to generate periodic interrupts.
lypinator 0:bb348c97df44 2546 \param [in] ticks Number of ticks between two interrupts.
lypinator 0:bb348c97df44 2547 \return 0 Function succeeded.
lypinator 0:bb348c97df44 2548 \return 1 Function failed.
lypinator 0:bb348c97df44 2549 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
lypinator 0:bb348c97df44 2550 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
lypinator 0:bb348c97df44 2551 must contain a vendor-specific implementation of this function.
lypinator 0:bb348c97df44 2552 */
lypinator 0:bb348c97df44 2553 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
lypinator 0:bb348c97df44 2554 {
lypinator 0:bb348c97df44 2555 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
lypinator 0:bb348c97df44 2556 {
lypinator 0:bb348c97df44 2557 return (1UL); /* Reload value impossible */
lypinator 0:bb348c97df44 2558 }
lypinator 0:bb348c97df44 2559
lypinator 0:bb348c97df44 2560 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
lypinator 0:bb348c97df44 2561 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
lypinator 0:bb348c97df44 2562 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
lypinator 0:bb348c97df44 2563 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
lypinator 0:bb348c97df44 2564 SysTick_CTRL_TICKINT_Msk |
lypinator 0:bb348c97df44 2565 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
lypinator 0:bb348c97df44 2566 return (0UL); /* Function successful */
lypinator 0:bb348c97df44 2567 }
lypinator 0:bb348c97df44 2568
lypinator 0:bb348c97df44 2569 #endif
lypinator 0:bb348c97df44 2570
lypinator 0:bb348c97df44 2571 /*@} end of CMSIS_Core_SysTickFunctions */
lypinator 0:bb348c97df44 2572
lypinator 0:bb348c97df44 2573
lypinator 0:bb348c97df44 2574
lypinator 0:bb348c97df44 2575 /* ##################################### Debug In/Output function ########################################### */
lypinator 0:bb348c97df44 2576 /**
lypinator 0:bb348c97df44 2577 \ingroup CMSIS_Core_FunctionInterface
lypinator 0:bb348c97df44 2578 \defgroup CMSIS_core_DebugFunctions ITM Functions
lypinator 0:bb348c97df44 2579 \brief Functions that access the ITM debug interface.
lypinator 0:bb348c97df44 2580 @{
lypinator 0:bb348c97df44 2581 */
lypinator 0:bb348c97df44 2582
lypinator 0:bb348c97df44 2583 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
lypinator 0:bb348c97df44 2584 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
lypinator 0:bb348c97df44 2585
lypinator 0:bb348c97df44 2586
lypinator 0:bb348c97df44 2587 /**
lypinator 0:bb348c97df44 2588 \brief ITM Send Character
lypinator 0:bb348c97df44 2589 \details Transmits a character via the ITM channel 0, and
lypinator 0:bb348c97df44 2590 \li Just returns when no debugger is connected that has booked the output.
lypinator 0:bb348c97df44 2591 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
lypinator 0:bb348c97df44 2592 \param [in] ch Character to transmit.
lypinator 0:bb348c97df44 2593 \returns Character to transmit.
lypinator 0:bb348c97df44 2594 */
lypinator 0:bb348c97df44 2595 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
lypinator 0:bb348c97df44 2596 {
lypinator 0:bb348c97df44 2597 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
lypinator 0:bb348c97df44 2598 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
lypinator 0:bb348c97df44 2599 {
lypinator 0:bb348c97df44 2600 while (ITM->PORT[0U].u32 == 0UL)
lypinator 0:bb348c97df44 2601 {
lypinator 0:bb348c97df44 2602 __NOP();
lypinator 0:bb348c97df44 2603 }
lypinator 0:bb348c97df44 2604 ITM->PORT[0U].u8 = (uint8_t)ch;
lypinator 0:bb348c97df44 2605 }
lypinator 0:bb348c97df44 2606 return (ch);
lypinator 0:bb348c97df44 2607 }
lypinator 0:bb348c97df44 2608
lypinator 0:bb348c97df44 2609
lypinator 0:bb348c97df44 2610 /**
lypinator 0:bb348c97df44 2611 \brief ITM Receive Character
lypinator 0:bb348c97df44 2612 \details Inputs a character via the external variable \ref ITM_RxBuffer.
lypinator 0:bb348c97df44 2613 \return Received character.
lypinator 0:bb348c97df44 2614 \return -1 No character pending.
lypinator 0:bb348c97df44 2615 */
lypinator 0:bb348c97df44 2616 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
lypinator 0:bb348c97df44 2617 {
lypinator 0:bb348c97df44 2618 int32_t ch = -1; /* no character available */
lypinator 0:bb348c97df44 2619
lypinator 0:bb348c97df44 2620 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
lypinator 0:bb348c97df44 2621 {
lypinator 0:bb348c97df44 2622 ch = ITM_RxBuffer;
lypinator 0:bb348c97df44 2623 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
lypinator 0:bb348c97df44 2624 }
lypinator 0:bb348c97df44 2625
lypinator 0:bb348c97df44 2626 return (ch);
lypinator 0:bb348c97df44 2627 }
lypinator 0:bb348c97df44 2628
lypinator 0:bb348c97df44 2629
lypinator 0:bb348c97df44 2630 /**
lypinator 0:bb348c97df44 2631 \brief ITM Check Character
lypinator 0:bb348c97df44 2632 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
lypinator 0:bb348c97df44 2633 \return 0 No character available.
lypinator 0:bb348c97df44 2634 \return 1 Character available.
lypinator 0:bb348c97df44 2635 */
lypinator 0:bb348c97df44 2636 __STATIC_INLINE int32_t ITM_CheckChar (void)
lypinator 0:bb348c97df44 2637 {
lypinator 0:bb348c97df44 2638
lypinator 0:bb348c97df44 2639 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
lypinator 0:bb348c97df44 2640 {
lypinator 0:bb348c97df44 2641 return (0); /* no character available */
lypinator 0:bb348c97df44 2642 }
lypinator 0:bb348c97df44 2643 else
lypinator 0:bb348c97df44 2644 {
lypinator 0:bb348c97df44 2645 return (1); /* character available */
lypinator 0:bb348c97df44 2646 }
lypinator 0:bb348c97df44 2647 }
lypinator 0:bb348c97df44 2648
lypinator 0:bb348c97df44 2649 /*@} end of CMSIS_core_DebugFunctions */
lypinator 0:bb348c97df44 2650
lypinator 0:bb348c97df44 2651
lypinator 0:bb348c97df44 2652
lypinator 0:bb348c97df44 2653
lypinator 0:bb348c97df44 2654 #ifdef __cplusplus
lypinator 0:bb348c97df44 2655 }
lypinator 0:bb348c97df44 2656 #endif
lypinator 0:bb348c97df44 2657
lypinator 0:bb348c97df44 2658 #endif /* __CORE_CM7_H_DEPENDANT */
lypinator 0:bb348c97df44 2659
lypinator 0:bb348c97df44 2660 #endif /* __CMSIS_GENERIC */