DevLibMemoryController - Initial commit

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Initial commit

mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cm3.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:: lypinator
Date:: Wed Sep 16 01:11:49 2020 +0000
Revision:: 0:bb348c97df44

Added PWM

Who changed what in which revision?

User	Revision	Line number	New contents of line
lypinator	0:bb348c97df44	1	/************************************************************************//
lypinator	0:bb348c97df44	2	* @file core_cm3.h
lypinator	0:bb348c97df44	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
lypinator	0:bb348c97df44	4	* @version V5.0.5
lypinator	0:bb348c97df44	5	* @date 08. January 2018
lypinator	0:bb348c97df44	6	******************************************************************************/
lypinator	0:bb348c97df44	7	/*
lypinator	0:bb348c97df44	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
lypinator	0:bb348c97df44	9	*
lypinator	0:bb348c97df44	10	* SPDX-License-Identifier: Apache-2.0
lypinator	0:bb348c97df44	11	*
lypinator	0:bb348c97df44	12	* Licensed under the Apache License, Version 2.0 (the License); you may
lypinator	0:bb348c97df44	13	* not use this file except in compliance with the License.
lypinator	0:bb348c97df44	14	* You may obtain a copy of the License at
lypinator	0:bb348c97df44	15	*
lypinator	0:bb348c97df44	16	* www.apache.org/licenses/LICENSE-2.0
lypinator	0:bb348c97df44	17	*
lypinator	0:bb348c97df44	18	* Unless required by applicable law or agreed to in writing, software
lypinator	0:bb348c97df44	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
lypinator	0:bb348c97df44	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator	0:bb348c97df44	21	* See the License for the specific language governing permissions and
lypinator	0:bb348c97df44	22	* limitations under the License.
lypinator	0:bb348c97df44	23	*/
lypinator	0:bb348c97df44	24
lypinator	0:bb348c97df44	25	#if defined ( __ICCARM__ )
lypinator	0:bb348c97df44	26	#pragma system_include /* treat file as system include file for MISRA check */
lypinator	0:bb348c97df44	27	#elif defined (__clang__)
lypinator	0:bb348c97df44	28	#pragma clang system_header /* treat file as system include file */
lypinator	0:bb348c97df44	29	#endif
lypinator	0:bb348c97df44	30
lypinator	0:bb348c97df44	31	#ifndef __CORE_CM3_H_GENERIC
lypinator	0:bb348c97df44	32	#define __CORE_CM3_H_GENERIC
lypinator	0:bb348c97df44	33
lypinator	0:bb348c97df44	34	#include <stdint.h>
lypinator	0:bb348c97df44	35
lypinator	0:bb348c97df44	36	#ifdef __cplusplus
lypinator	0:bb348c97df44	37	extern "C" {
lypinator	0:bb348c97df44	38	#endif
lypinator	0:bb348c97df44	39
lypinator	0:bb348c97df44	40	/**
lypinator	0:bb348c97df44	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
lypinator	0:bb348c97df44	42	CMSIS violates the following MISRA-C:2004 rules:
lypinator	0:bb348c97df44	43
lypinator	0:bb348c97df44	44	\li Required Rule 8.5, object/function definition in header file.<br>
lypinator	0:bb348c97df44	45	Function definitions in header files are used to allow 'inlining'.
lypinator	0:bb348c97df44	46
lypinator	0:bb348c97df44	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
lypinator	0:bb348c97df44	48	Unions are used for effective representation of core registers.
lypinator	0:bb348c97df44	49
lypinator	0:bb348c97df44	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
lypinator	0:bb348c97df44	51	Function-like macros are used to allow more efficient code.
lypinator	0:bb348c97df44	52	*/
lypinator	0:bb348c97df44	53
lypinator	0:bb348c97df44	54
lypinator	0:bb348c97df44	55	/*******************************************************************************
lypinator	0:bb348c97df44	56	* CMSIS definitions
lypinator	0:bb348c97df44	57	******************************************************************************/
lypinator	0:bb348c97df44	58	/**
lypinator	0:bb348c97df44	59	\ingroup Cortex_M3
lypinator	0:bb348c97df44	60	@{
lypinator	0:bb348c97df44	61	*/
lypinator	0:bb348c97df44	62
lypinator	0:bb348c97df44	63	#include "cmsis_version.h"
lypinator	0:bb348c97df44	64
lypinator	0:bb348c97df44	65	/* CMSIS CM3 definitions */
lypinator	0:bb348c97df44	66	#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
lypinator	0:bb348c97df44	67	#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
lypinator	0:bb348c97df44	68	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) \| \
lypinator	0:bb348c97df44	69	__CM3_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
lypinator	0:bb348c97df44	70
lypinator	0:bb348c97df44	71	#define __CORTEX_M (3U) /!< Cortex-M Core /
lypinator	0:bb348c97df44	72
lypinator	0:bb348c97df44	73	/** __FPU_USED indicates whether an FPU is used or not.
lypinator	0:bb348c97df44	74	This core does not support an FPU at all
lypinator	0:bb348c97df44	75	*/
lypinator	0:bb348c97df44	76	#define __FPU_USED 0U
lypinator	0:bb348c97df44	77
lypinator	0:bb348c97df44	78	#if defined ( __CC_ARM )
lypinator	0:bb348c97df44	79	#if defined __TARGET_FPU_VFP
lypinator	0:bb348c97df44	80	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator	0:bb348c97df44	81	#endif
lypinator	0:bb348c97df44	82
lypinator	0:bb348c97df44	83	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
lypinator	0:bb348c97df44	84	#if defined __ARM_PCS_VFP
lypinator	0:bb348c97df44	85	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator	0:bb348c97df44	86	#endif
lypinator	0:bb348c97df44	87
lypinator	0:bb348c97df44	88	#elif defined ( __GNUC__ )
lypinator	0:bb348c97df44	89	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
lypinator	0:bb348c97df44	90	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator	0:bb348c97df44	91	#endif
lypinator	0:bb348c97df44	92
lypinator	0:bb348c97df44	93	#elif defined ( __ICCARM__ )
lypinator	0:bb348c97df44	94	#if defined __ARMVFP__
lypinator	0:bb348c97df44	95	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator	0:bb348c97df44	96	#endif
lypinator	0:bb348c97df44	97
lypinator	0:bb348c97df44	98	#elif defined ( __TI_ARM__ )
lypinator	0:bb348c97df44	99	#if defined __TI_VFP_SUPPORT__
lypinator	0:bb348c97df44	100	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator	0:bb348c97df44	101	#endif
lypinator	0:bb348c97df44	102
lypinator	0:bb348c97df44	103	#elif defined ( __TASKING__ )
lypinator	0:bb348c97df44	104	#if defined __FPU_VFP__
lypinator	0:bb348c97df44	105	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator	0:bb348c97df44	106	#endif
lypinator	0:bb348c97df44	107
lypinator	0:bb348c97df44	108	#elif defined ( __CSMC__ )
lypinator	0:bb348c97df44	109	#if ( __CSMC__ & 0x400U)
lypinator	0:bb348c97df44	110	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator	0:bb348c97df44	111	#endif
lypinator	0:bb348c97df44	112
lypinator	0:bb348c97df44	113	#endif
lypinator	0:bb348c97df44	114
lypinator	0:bb348c97df44	115	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
lypinator	0:bb348c97df44	116
lypinator	0:bb348c97df44	117
lypinator	0:bb348c97df44	118	#ifdef __cplusplus
lypinator	0:bb348c97df44	119	}
lypinator	0:bb348c97df44	120	#endif
lypinator	0:bb348c97df44	121
lypinator	0:bb348c97df44	122	#endif /* __CORE_CM3_H_GENERIC */
lypinator	0:bb348c97df44	123
lypinator	0:bb348c97df44	124	#ifndef __CMSIS_GENERIC
lypinator	0:bb348c97df44	125
lypinator	0:bb348c97df44	126	#ifndef __CORE_CM3_H_DEPENDANT
lypinator	0:bb348c97df44	127	#define __CORE_CM3_H_DEPENDANT
lypinator	0:bb348c97df44	128
lypinator	0:bb348c97df44	129	#ifdef __cplusplus
lypinator	0:bb348c97df44	130	extern "C" {
lypinator	0:bb348c97df44	131	#endif
lypinator	0:bb348c97df44	132
lypinator	0:bb348c97df44	133	/* check device defines and use defaults */
lypinator	0:bb348c97df44	134	#if defined __CHECK_DEVICE_DEFINES
lypinator	0:bb348c97df44	135	#ifndef __CM3_REV
lypinator	0:bb348c97df44	136	#define __CM3_REV 0x0200U
lypinator	0:bb348c97df44	137	#warning "__CM3_REV not defined in device header file; using default!"
lypinator	0:bb348c97df44	138	#endif
lypinator	0:bb348c97df44	139
lypinator	0:bb348c97df44	140	#ifndef __MPU_PRESENT
lypinator	0:bb348c97df44	141	#define __MPU_PRESENT 0U
lypinator	0:bb348c97df44	142	#warning "__MPU_PRESENT not defined in device header file; using default!"
lypinator	0:bb348c97df44	143	#endif
lypinator	0:bb348c97df44	144
lypinator	0:bb348c97df44	145	#ifndef __NVIC_PRIO_BITS
lypinator	0:bb348c97df44	146	#define __NVIC_PRIO_BITS 3U
lypinator	0:bb348c97df44	147	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
lypinator	0:bb348c97df44	148	#endif
lypinator	0:bb348c97df44	149
lypinator	0:bb348c97df44	150	#ifndef __Vendor_SysTickConfig
lypinator	0:bb348c97df44	151	#define __Vendor_SysTickConfig 0U
lypinator	0:bb348c97df44	152	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
lypinator	0:bb348c97df44	153	#endif
lypinator	0:bb348c97df44	154	#endif
lypinator	0:bb348c97df44	155
lypinator	0:bb348c97df44	156	/* IO definitions (access restrictions to peripheral registers) */
lypinator	0:bb348c97df44	157	/**
lypinator	0:bb348c97df44	158	\defgroup CMSIS_glob_defs CMSIS Global Defines
lypinator	0:bb348c97df44	159
lypinator	0:bb348c97df44	160	<strong>IO Type Qualifiers</strong> are used
lypinator	0:bb348c97df44	161	\li to specify the access to peripheral variables.
lypinator	0:bb348c97df44	162	\li for automatic generation of peripheral register debug information.
lypinator	0:bb348c97df44	163	*/
lypinator	0:bb348c97df44	164	#ifdef __cplusplus
lypinator	0:bb348c97df44	165	#define __I volatile /!< Defines 'read only' permissions /
lypinator	0:bb348c97df44	166	#else
lypinator	0:bb348c97df44	167	#define __I volatile const /!< Defines 'read only' permissions /
lypinator	0:bb348c97df44	168	#endif
lypinator	0:bb348c97df44	169	#define __O volatile /!< Defines 'write only' permissions /
lypinator	0:bb348c97df44	170	#define __IO volatile /!< Defines 'read / write' permissions /
lypinator	0:bb348c97df44	171
lypinator	0:bb348c97df44	172	/* following defines should be used for structure members */
lypinator	0:bb348c97df44	173	#define __IM volatile const /! Defines 'read only' structure member permissions /
lypinator	0:bb348c97df44	174	#define __OM volatile /! Defines 'write only' structure member permissions /
lypinator	0:bb348c97df44	175	#define __IOM volatile /! Defines 'read / write' structure member permissions /
lypinator	0:bb348c97df44	176
lypinator	0:bb348c97df44	177	/@} end of group Cortex_M3 /
lypinator	0:bb348c97df44	178
lypinator	0:bb348c97df44	179
lypinator	0:bb348c97df44	180
lypinator	0:bb348c97df44	181	/*******************************************************************************
lypinator	0:bb348c97df44	182	* Register Abstraction
lypinator	0:bb348c97df44	183	Core Register contain:
lypinator	0:bb348c97df44	184	- Core Register
lypinator	0:bb348c97df44	185	- Core NVIC Register
lypinator	0:bb348c97df44	186	- Core SCB Register
lypinator	0:bb348c97df44	187	- Core SysTick Register
lypinator	0:bb348c97df44	188	- Core Debug Register
lypinator	0:bb348c97df44	189	- Core MPU Register
lypinator	0:bb348c97df44	190	******************************************************************************/
lypinator	0:bb348c97df44	191	/**
lypinator	0:bb348c97df44	192	\defgroup CMSIS_core_register Defines and Type Definitions
lypinator	0:bb348c97df44	193	\brief Type definitions and defines for Cortex-M processor based devices.
lypinator	0:bb348c97df44	194	*/
lypinator	0:bb348c97df44	195
lypinator	0:bb348c97df44	196	/**
lypinator	0:bb348c97df44	197	\ingroup CMSIS_core_register
lypinator	0:bb348c97df44	198	\defgroup CMSIS_CORE Status and Control Registers
lypinator	0:bb348c97df44	199	\brief Core Register type definitions.
lypinator	0:bb348c97df44	200	@{
lypinator	0:bb348c97df44	201	*/
lypinator	0:bb348c97df44	202
lypinator	0:bb348c97df44	203	/**
lypinator	0:bb348c97df44	204	\brief Union type to access the Application Program Status Register (APSR).
lypinator	0:bb348c97df44	205	*/
lypinator	0:bb348c97df44	206	typedef union
lypinator	0:bb348c97df44	207	{
lypinator	0:bb348c97df44	208	struct
lypinator	0:bb348c97df44	209	{
lypinator	0:bb348c97df44	210	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
lypinator	0:bb348c97df44	211	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
lypinator	0:bb348c97df44	212	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
lypinator	0:bb348c97df44	213	uint32_t C:1; /!< bit: 29 Carry condition code flag /
lypinator	0:bb348c97df44	214	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
lypinator	0:bb348c97df44	215	uint32_t N:1; /!< bit: 31 Negative condition code flag /
lypinator	0:bb348c97df44	216	} b; /!< Structure used for bit access /
lypinator	0:bb348c97df44	217	uint32_t w; /!< Type used for word access /
lypinator	0:bb348c97df44	218	} APSR_Type;
lypinator	0:bb348c97df44	219
lypinator	0:bb348c97df44	220	/* APSR Register Definitions */
lypinator	0:bb348c97df44	221	#define APSR_N_Pos 31U /!< APSR: N Position /
lypinator	0:bb348c97df44	222	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
lypinator	0:bb348c97df44	223
lypinator	0:bb348c97df44	224	#define APSR_Z_Pos 30U /!< APSR: Z Position /
lypinator	0:bb348c97df44	225	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
lypinator	0:bb348c97df44	226
lypinator	0:bb348c97df44	227	#define APSR_C_Pos 29U /!< APSR: C Position /
lypinator	0:bb348c97df44	228	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
lypinator	0:bb348c97df44	229
lypinator	0:bb348c97df44	230	#define APSR_V_Pos 28U /!< APSR: V Position /
lypinator	0:bb348c97df44	231	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
lypinator	0:bb348c97df44	232
lypinator	0:bb348c97df44	233	#define APSR_Q_Pos 27U /!< APSR: Q Position /
lypinator	0:bb348c97df44	234	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
lypinator	0:bb348c97df44	235
lypinator	0:bb348c97df44	236
lypinator	0:bb348c97df44	237	/**
lypinator	0:bb348c97df44	238	\brief Union type to access the Interrupt Program Status Register (IPSR).
lypinator	0:bb348c97df44	239	*/
lypinator	0:bb348c97df44	240	typedef union
lypinator	0:bb348c97df44	241	{
lypinator	0:bb348c97df44	242	struct
lypinator	0:bb348c97df44	243	{
lypinator	0:bb348c97df44	244	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
lypinator	0:bb348c97df44	245	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
lypinator	0:bb348c97df44	246	} b; /!< Structure used for bit access /
lypinator	0:bb348c97df44	247	uint32_t w; /!< Type used for word access /
lypinator	0:bb348c97df44	248	} IPSR_Type;
lypinator	0:bb348c97df44	249
lypinator	0:bb348c97df44	250	/* IPSR Register Definitions */
lypinator	0:bb348c97df44	251	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
lypinator	0:bb348c97df44	252	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
lypinator	0:bb348c97df44	253
lypinator	0:bb348c97df44	254
lypinator	0:bb348c97df44	255	/**
lypinator	0:bb348c97df44	256	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
lypinator	0:bb348c97df44	257	*/
lypinator	0:bb348c97df44	258	typedef union
lypinator	0:bb348c97df44	259	{
lypinator	0:bb348c97df44	260	struct
lypinator	0:bb348c97df44	261	{
lypinator	0:bb348c97df44	262	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
lypinator	0:bb348c97df44	263	uint32_t _reserved0:1; /!< bit: 9 Reserved /
lypinator	0:bb348c97df44	264	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
lypinator	0:bb348c97df44	265	uint32_t _reserved1:8; /!< bit: 16..23 Reserved /
lypinator	0:bb348c97df44	266	uint32_t T:1; /!< bit: 24 Thumb bit /
lypinator	0:bb348c97df44	267	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
lypinator	0:bb348c97df44	268	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
lypinator	0:bb348c97df44	269	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
lypinator	0:bb348c97df44	270	uint32_t C:1; /!< bit: 29 Carry condition code flag /
lypinator	0:bb348c97df44	271	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
lypinator	0:bb348c97df44	272	uint32_t N:1; /!< bit: 31 Negative condition code flag /
lypinator	0:bb348c97df44	273	} b; /!< Structure used for bit access /
lypinator	0:bb348c97df44	274	uint32_t w; /!< Type used for word access /
lypinator	0:bb348c97df44	275	} xPSR_Type;
lypinator	0:bb348c97df44	276
lypinator	0:bb348c97df44	277	/* xPSR Register Definitions */
lypinator	0:bb348c97df44	278	#define xPSR_N_Pos 31U /!< xPSR: N Position /
lypinator	0:bb348c97df44	279	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
lypinator	0:bb348c97df44	280
lypinator	0:bb348c97df44	281	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
lypinator	0:bb348c97df44	282	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
lypinator	0:bb348c97df44	283
lypinator	0:bb348c97df44	284	#define xPSR_C_Pos 29U /!< xPSR: C Position /
lypinator	0:bb348c97df44	285	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
lypinator	0:bb348c97df44	286
lypinator	0:bb348c97df44	287	#define xPSR_V_Pos 28U /!< xPSR: V Position /
lypinator	0:bb348c97df44	288	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
lypinator	0:bb348c97df44	289
lypinator	0:bb348c97df44	290	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
lypinator	0:bb348c97df44	291	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
lypinator	0:bb348c97df44	292
lypinator	0:bb348c97df44	293	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
lypinator	0:bb348c97df44	294	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
lypinator	0:bb348c97df44	295
lypinator	0:bb348c97df44	296	#define xPSR_T_Pos 24U /!< xPSR: T Position /
lypinator	0:bb348c97df44	297	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
lypinator	0:bb348c97df44	298
lypinator	0:bb348c97df44	299	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
lypinator	0:bb348c97df44	300	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
lypinator	0:bb348c97df44	301
lypinator	0:bb348c97df44	302	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
lypinator	0:bb348c97df44	303	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
lypinator	0:bb348c97df44	304
lypinator	0:bb348c97df44	305
lypinator	0:bb348c97df44	306	/**
lypinator	0:bb348c97df44	307	\brief Union type to access the Control Registers (CONTROL).
lypinator	0:bb348c97df44	308	*/
lypinator	0:bb348c97df44	309	typedef union
lypinator	0:bb348c97df44	310	{
lypinator	0:bb348c97df44	311	struct
lypinator	0:bb348c97df44	312	{
lypinator	0:bb348c97df44	313	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
lypinator	0:bb348c97df44	314	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
lypinator	0:bb348c97df44	315	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
lypinator	0:bb348c97df44	316	} b; /!< Structure used for bit access /
lypinator	0:bb348c97df44	317	uint32_t w; /!< Type used for word access /
lypinator	0:bb348c97df44	318	} CONTROL_Type;
lypinator	0:bb348c97df44	319
lypinator	0:bb348c97df44	320	/* CONTROL Register Definitions */
lypinator	0:bb348c97df44	321	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
lypinator	0:bb348c97df44	322	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
lypinator	0:bb348c97df44	323
lypinator	0:bb348c97df44	324	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
lypinator	0:bb348c97df44	325	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
lypinator	0:bb348c97df44	326
lypinator	0:bb348c97df44	327	/@} end of group CMSIS_CORE /
lypinator	0:bb348c97df44	328
lypinator	0:bb348c97df44	329
lypinator	0:bb348c97df44	330	/**
lypinator	0:bb348c97df44	331	\ingroup CMSIS_core_register
lypinator	0:bb348c97df44	332	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
lypinator	0:bb348c97df44	333	\brief Type definitions for the NVIC Registers
lypinator	0:bb348c97df44	334	@{
lypinator	0:bb348c97df44	335	*/
lypinator	0:bb348c97df44	336
lypinator	0:bb348c97df44	337	/**
lypinator	0:bb348c97df44	338	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
lypinator	0:bb348c97df44	339	*/
lypinator	0:bb348c97df44	340	typedef struct
lypinator	0:bb348c97df44	341	{
lypinator	0:bb348c97df44	342	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
lypinator	0:bb348c97df44	343	uint32_t RESERVED0[24U];
lypinator	0:bb348c97df44	344	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
lypinator	0:bb348c97df44	345	uint32_t RSERVED1[24U];
lypinator	0:bb348c97df44	346	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
lypinator	0:bb348c97df44	347	uint32_t RESERVED2[24U];
lypinator	0:bb348c97df44	348	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
lypinator	0:bb348c97df44	349	uint32_t RESERVED3[24U];
lypinator	0:bb348c97df44	350	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
lypinator	0:bb348c97df44	351	uint32_t RESERVED4[56U];
lypinator	0:bb348c97df44	352	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
lypinator	0:bb348c97df44	353	uint32_t RESERVED5[644U];
lypinator	0:bb348c97df44	354	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
lypinator	0:bb348c97df44	355	} NVIC_Type;
lypinator	0:bb348c97df44	356
lypinator	0:bb348c97df44	357	/* Software Triggered Interrupt Register Definitions */
lypinator	0:bb348c97df44	358	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
lypinator	0:bb348c97df44	359	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
lypinator	0:bb348c97df44	360
lypinator	0:bb348c97df44	361	/@} end of group CMSIS_NVIC /
lypinator	0:bb348c97df44	362
lypinator	0:bb348c97df44	363
lypinator	0:bb348c97df44	364	/**
lypinator	0:bb348c97df44	365	\ingroup CMSIS_core_register
lypinator	0:bb348c97df44	366	\defgroup CMSIS_SCB System Control Block (SCB)
lypinator	0:bb348c97df44	367	\brief Type definitions for the System Control Block Registers
lypinator	0:bb348c97df44	368	@{
lypinator	0:bb348c97df44	369	*/
lypinator	0:bb348c97df44	370
lypinator	0:bb348c97df44	371	/**
lypinator	0:bb348c97df44	372	\brief Structure type to access the System Control Block (SCB).
lypinator	0:bb348c97df44	373	*/
lypinator	0:bb348c97df44	374	typedef struct
lypinator	0:bb348c97df44	375	{
lypinator	0:bb348c97df44	376	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
lypinator	0:bb348c97df44	377	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
lypinator	0:bb348c97df44	378	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
lypinator	0:bb348c97df44	379	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
lypinator	0:bb348c97df44	380	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
lypinator	0:bb348c97df44	381	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
lypinator	0:bb348c97df44	382	__IOM uint8_t SHP[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
lypinator	0:bb348c97df44	383	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
lypinator	0:bb348c97df44	384	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
lypinator	0:bb348c97df44	385	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
lypinator	0:bb348c97df44	386	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
lypinator	0:bb348c97df44	387	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
lypinator	0:bb348c97df44	388	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
lypinator	0:bb348c97df44	389	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
lypinator	0:bb348c97df44	390	__IM uint32_t PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
lypinator	0:bb348c97df44	391	__IM uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
lypinator	0:bb348c97df44	392	__IM uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
lypinator	0:bb348c97df44	393	__IM uint32_t MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
lypinator	0:bb348c97df44	394	__IM uint32_t ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
lypinator	0:bb348c97df44	395	uint32_t RESERVED0[5U];
lypinator	0:bb348c97df44	396	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
lypinator	0:bb348c97df44	397	} SCB_Type;
lypinator	0:bb348c97df44	398
lypinator	0:bb348c97df44	399	/* SCB CPUID Register Definitions */
lypinator	0:bb348c97df44	400	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
lypinator	0:bb348c97df44	401	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
lypinator	0:bb348c97df44	402
lypinator	0:bb348c97df44	403	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
lypinator	0:bb348c97df44	404	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
lypinator	0:bb348c97df44	405
lypinator	0:bb348c97df44	406	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
lypinator	0:bb348c97df44	407	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
lypinator	0:bb348c97df44	408
lypinator	0:bb348c97df44	409	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
lypinator	0:bb348c97df44	410	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
lypinator	0:bb348c97df44	411
lypinator	0:bb348c97df44	412	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
lypinator	0:bb348c97df44	413	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
lypinator	0:bb348c97df44	414
lypinator	0:bb348c97df44	415	/* SCB Interrupt Control State Register Definitions */
lypinator	0:bb348c97df44	416	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
lypinator	0:bb348c97df44	417	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
lypinator	0:bb348c97df44	418
lypinator	0:bb348c97df44	419	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
lypinator	0:bb348c97df44	420	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
lypinator	0:bb348c97df44	421
lypinator	0:bb348c97df44	422	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
lypinator	0:bb348c97df44	423	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
lypinator	0:bb348c97df44	424
lypinator	0:bb348c97df44	425	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
lypinator	0:bb348c97df44	426	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
lypinator	0:bb348c97df44	427
lypinator	0:bb348c97df44	428	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
lypinator	0:bb348c97df44	429	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
lypinator	0:bb348c97df44	430
lypinator	0:bb348c97df44	431	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
lypinator	0:bb348c97df44	432	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
lypinator	0:bb348c97df44	433
lypinator	0:bb348c97df44	434	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
lypinator	0:bb348c97df44	435	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
lypinator	0:bb348c97df44	436
lypinator	0:bb348c97df44	437	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
lypinator	0:bb348c97df44	438	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
lypinator	0:bb348c97df44	439
lypinator	0:bb348c97df44	440	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
lypinator	0:bb348c97df44	441	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
lypinator	0:bb348c97df44	442
lypinator	0:bb348c97df44	443	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
lypinator	0:bb348c97df44	444	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
lypinator	0:bb348c97df44	445
lypinator	0:bb348c97df44	446	/* SCB Vector Table Offset Register Definitions */
lypinator	0:bb348c97df44	447	#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
lypinator	0:bb348c97df44	448	#define SCB_VTOR_TBLBASE_Pos 29U /!< SCB VTOR: TBLBASE Position /
lypinator	0:bb348c97df44	449	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
lypinator	0:bb348c97df44	450
lypinator	0:bb348c97df44	451	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
lypinator	0:bb348c97df44	452	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
lypinator	0:bb348c97df44	453	#else
lypinator	0:bb348c97df44	454	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
lypinator	0:bb348c97df44	455	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
lypinator	0:bb348c97df44	456	#endif
lypinator	0:bb348c97df44	457
lypinator	0:bb348c97df44	458	/* SCB Application Interrupt and Reset Control Register Definitions */
lypinator	0:bb348c97df44	459	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
lypinator	0:bb348c97df44	460	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
lypinator	0:bb348c97df44	461
lypinator	0:bb348c97df44	462	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
lypinator	0:bb348c97df44	463	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
lypinator	0:bb348c97df44	464
lypinator	0:bb348c97df44	465	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
lypinator	0:bb348c97df44	466	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
lypinator	0:bb348c97df44	467
lypinator	0:bb348c97df44	468	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
lypinator	0:bb348c97df44	469	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
lypinator	0:bb348c97df44	470
lypinator	0:bb348c97df44	471	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
lypinator	0:bb348c97df44	472	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
lypinator	0:bb348c97df44	473
lypinator	0:bb348c97df44	474	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
lypinator	0:bb348c97df44	475	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
lypinator	0:bb348c97df44	476
lypinator	0:bb348c97df44	477	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
lypinator	0:bb348c97df44	478	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
lypinator	0:bb348c97df44	479
lypinator	0:bb348c97df44	480	/* SCB System Control Register Definitions */
lypinator	0:bb348c97df44	481	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
lypinator	0:bb348c97df44	482	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
lypinator	0:bb348c97df44	483
lypinator	0:bb348c97df44	484	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
lypinator	0:bb348c97df44	485	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
lypinator	0:bb348c97df44	486
lypinator	0:bb348c97df44	487	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
lypinator	0:bb348c97df44	488	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
lypinator	0:bb348c97df44	489
lypinator	0:bb348c97df44	490	/* SCB Configuration Control Register Definitions */
lypinator	0:bb348c97df44	491	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
lypinator	0:bb348c97df44	492	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
lypinator	0:bb348c97df44	493
lypinator	0:bb348c97df44	494	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
lypinator	0:bb348c97df44	495	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
lypinator	0:bb348c97df44	496
lypinator	0:bb348c97df44	497	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
lypinator	0:bb348c97df44	498	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
lypinator	0:bb348c97df44	499
lypinator	0:bb348c97df44	500	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
lypinator	0:bb348c97df44	501	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
lypinator	0:bb348c97df44	502
lypinator	0:bb348c97df44	503	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
lypinator	0:bb348c97df44	504	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
lypinator	0:bb348c97df44	505
lypinator	0:bb348c97df44	506	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
lypinator	0:bb348c97df44	507	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
lypinator	0:bb348c97df44	508
lypinator	0:bb348c97df44	509	/* SCB System Handler Control and State Register Definitions */
lypinator	0:bb348c97df44	510	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
lypinator	0:bb348c97df44	511	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
lypinator	0:bb348c97df44	512
lypinator	0:bb348c97df44	513	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
lypinator	0:bb348c97df44	514	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
lypinator	0:bb348c97df44	515
lypinator	0:bb348c97df44	516	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
lypinator	0:bb348c97df44	517	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
lypinator	0:bb348c97df44	518
lypinator	0:bb348c97df44	519	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
lypinator	0:bb348c97df44	520	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
lypinator	0:bb348c97df44	521
lypinator	0:bb348c97df44	522	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
lypinator	0:bb348c97df44	523	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
lypinator	0:bb348c97df44	524
lypinator	0:bb348c97df44	525	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
lypinator	0:bb348c97df44	526	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
lypinator	0:bb348c97df44	527
lypinator	0:bb348c97df44	528	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
lypinator	0:bb348c97df44	529	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
lypinator	0:bb348c97df44	530
lypinator	0:bb348c97df44	531	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
lypinator	0:bb348c97df44	532	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
lypinator	0:bb348c97df44	533
lypinator	0:bb348c97df44	534	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
lypinator	0:bb348c97df44	535	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
lypinator	0:bb348c97df44	536
lypinator	0:bb348c97df44	537	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
lypinator	0:bb348c97df44	538	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
lypinator	0:bb348c97df44	539
lypinator	0:bb348c97df44	540	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
lypinator	0:bb348c97df44	541	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
lypinator	0:bb348c97df44	542
lypinator	0:bb348c97df44	543	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
lypinator	0:bb348c97df44	544	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
lypinator	0:bb348c97df44	545
lypinator	0:bb348c97df44	546	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
lypinator	0:bb348c97df44	547	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
lypinator	0:bb348c97df44	548
lypinator	0:bb348c97df44	549	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
lypinator	0:bb348c97df44	550	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
lypinator	0:bb348c97df44	551
lypinator	0:bb348c97df44	552	/* SCB Configurable Fault Status Register Definitions */
lypinator	0:bb348c97df44	553	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
lypinator	0:bb348c97df44	554	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
lypinator	0:bb348c97df44	555
lypinator	0:bb348c97df44	556	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
lypinator	0:bb348c97df44	557	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
lypinator	0:bb348c97df44	558
lypinator	0:bb348c97df44	559	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
lypinator	0:bb348c97df44	560	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
lypinator	0:bb348c97df44	561
lypinator	0:bb348c97df44	562	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
lypinator	0:bb348c97df44	563	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
lypinator	0:bb348c97df44	564	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
lypinator	0:bb348c97df44	565
lypinator	0:bb348c97df44	566	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
lypinator	0:bb348c97df44	567	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
lypinator	0:bb348c97df44	568
lypinator	0:bb348c97df44	569	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
lypinator	0:bb348c97df44	570	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
lypinator	0:bb348c97df44	571
lypinator	0:bb348c97df44	572	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
lypinator	0:bb348c97df44	573	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
lypinator	0:bb348c97df44	574
lypinator	0:bb348c97df44	575	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
lypinator	0:bb348c97df44	576	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
lypinator	0:bb348c97df44	577
lypinator	0:bb348c97df44	578	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
lypinator	0:bb348c97df44	579	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
lypinator	0:bb348c97df44	580	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
lypinator	0:bb348c97df44	581
lypinator	0:bb348c97df44	582	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
lypinator	0:bb348c97df44	583	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
lypinator	0:bb348c97df44	584
lypinator	0:bb348c97df44	585	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
lypinator	0:bb348c97df44	586	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
lypinator	0:bb348c97df44	587
lypinator	0:bb348c97df44	588	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
lypinator	0:bb348c97df44	589	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
lypinator	0:bb348c97df44	590
lypinator	0:bb348c97df44	591	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
lypinator	0:bb348c97df44	592	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
lypinator	0:bb348c97df44	593
lypinator	0:bb348c97df44	594	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
lypinator	0:bb348c97df44	595	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
lypinator	0:bb348c97df44	596
lypinator	0:bb348c97df44	597	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
lypinator	0:bb348c97df44	598	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
lypinator	0:bb348c97df44	599	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
lypinator	0:bb348c97df44	600
lypinator	0:bb348c97df44	601	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
lypinator	0:bb348c97df44	602	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
lypinator	0:bb348c97df44	603
lypinator	0:bb348c97df44	604	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
lypinator	0:bb348c97df44	605	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
lypinator	0:bb348c97df44	606
lypinator	0:bb348c97df44	607	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
lypinator	0:bb348c97df44	608	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
lypinator	0:bb348c97df44	609
lypinator	0:bb348c97df44	610	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
lypinator	0:bb348c97df44	611	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
lypinator	0:bb348c97df44	612
lypinator	0:bb348c97df44	613	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
lypinator	0:bb348c97df44	614	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
lypinator	0:bb348c97df44	615
lypinator	0:bb348c97df44	616	/* SCB Hard Fault Status Register Definitions */
lypinator	0:bb348c97df44	617	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
lypinator	0:bb348c97df44	618	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
lypinator	0:bb348c97df44	619
lypinator	0:bb348c97df44	620	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
lypinator	0:bb348c97df44	621	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
lypinator	0:bb348c97df44	622
lypinator	0:bb348c97df44	623	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
lypinator	0:bb348c97df44	624	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
lypinator	0:bb348c97df44	625
lypinator	0:bb348c97df44	626	/* SCB Debug Fault Status Register Definitions */
lypinator	0:bb348c97df44	627	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
lypinator	0:bb348c97df44	628	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
lypinator	0:bb348c97df44	629
lypinator	0:bb348c97df44	630	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
lypinator	0:bb348c97df44	631	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
lypinator	0:bb348c97df44	632
lypinator	0:bb348c97df44	633	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
lypinator	0:bb348c97df44	634	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
lypinator	0:bb348c97df44	635
lypinator	0:bb348c97df44	636	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
lypinator	0:bb348c97df44	637	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
lypinator	0:bb348c97df44	638
lypinator	0:bb348c97df44	639	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
lypinator	0:bb348c97df44	640	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
lypinator	0:bb348c97df44	641
lypinator	0:bb348c97df44	642	/@} end of group CMSIS_SCB /
lypinator	0:bb348c97df44	643
lypinator	0:bb348c97df44	644
lypinator	0:bb348c97df44	645	/**
lypinator	0:bb348c97df44	646	\ingroup CMSIS_core_register
lypinator	0:bb348c97df44	647	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
lypinator	0:bb348c97df44	648	\brief Type definitions for the System Control and ID Register not in the SCB
lypinator	0:bb348c97df44	649	@{
lypinator	0:bb348c97df44	650	*/
lypinator	0:bb348c97df44	651
lypinator	0:bb348c97df44	652	/**
lypinator	0:bb348c97df44	653	\brief Structure type to access the System Control and ID Register not in the SCB.
lypinator	0:bb348c97df44	654	*/
lypinator	0:bb348c97df44	655	typedef struct
lypinator	0:bb348c97df44	656	{
lypinator	0:bb348c97df44	657	uint32_t RESERVED0[1U];
lypinator	0:bb348c97df44	658	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
lypinator	0:bb348c97df44	659	#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
lypinator	0:bb348c97df44	660	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
lypinator	0:bb348c97df44	661	#else
lypinator	0:bb348c97df44	662	uint32_t RESERVED1[1U];
lypinator	0:bb348c97df44	663	#endif
lypinator	0:bb348c97df44	664	} SCnSCB_Type;
lypinator	0:bb348c97df44	665
lypinator	0:bb348c97df44	666	/* Interrupt Controller Type Register Definitions */
lypinator	0:bb348c97df44	667	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
lypinator	0:bb348c97df44	668	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
lypinator	0:bb348c97df44	669
lypinator	0:bb348c97df44	670	/* Auxiliary Control Register Definitions */
lypinator	0:bb348c97df44	671
lypinator	0:bb348c97df44	672	#define SCnSCB_ACTLR_DISFOLD_Pos 2U /!< ACTLR: DISFOLD Position /
lypinator	0:bb348c97df44	673	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
lypinator	0:bb348c97df44	674
lypinator	0:bb348c97df44	675	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /!< ACTLR: DISDEFWBUF Position /
lypinator	0:bb348c97df44	676	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
lypinator	0:bb348c97df44	677
lypinator	0:bb348c97df44	678	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /!< ACTLR: DISMCYCINT Position /
lypinator	0:bb348c97df44	679	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
lypinator	0:bb348c97df44	680
lypinator	0:bb348c97df44	681	/@} end of group CMSIS_SCnotSCB /
lypinator	0:bb348c97df44	682
lypinator	0:bb348c97df44	683
lypinator	0:bb348c97df44	684	/**
lypinator	0:bb348c97df44	685	\ingroup CMSIS_core_register
lypinator	0:bb348c97df44	686	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
lypinator	0:bb348c97df44	687	\brief Type definitions for the System Timer Registers.
lypinator	0:bb348c97df44	688	@{
lypinator	0:bb348c97df44	689	*/
lypinator	0:bb348c97df44	690
lypinator	0:bb348c97df44	691	/**
lypinator	0:bb348c97df44	692	\brief Structure type to access the System Timer (SysTick).
lypinator	0:bb348c97df44	693	*/
lypinator	0:bb348c97df44	694	typedef struct
lypinator	0:bb348c97df44	695	{
lypinator	0:bb348c97df44	696	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
lypinator	0:bb348c97df44	697	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
lypinator	0:bb348c97df44	698	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
lypinator	0:bb348c97df44	699	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
lypinator	0:bb348c97df44	700	} SysTick_Type;
lypinator	0:bb348c97df44	701
lypinator	0:bb348c97df44	702	/* SysTick Control / Status Register Definitions */
lypinator	0:bb348c97df44	703	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
lypinator	0:bb348c97df44	704	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
lypinator	0:bb348c97df44	705
lypinator	0:bb348c97df44	706	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
lypinator	0:bb348c97df44	707	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
lypinator	0:bb348c97df44	708
lypinator	0:bb348c97df44	709	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
lypinator	0:bb348c97df44	710	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
lypinator	0:bb348c97df44	711
lypinator	0:bb348c97df44	712	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
lypinator	0:bb348c97df44	713	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
lypinator	0:bb348c97df44	714
lypinator	0:bb348c97df44	715	/* SysTick Reload Register Definitions */
lypinator	0:bb348c97df44	716	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
lypinator	0:bb348c97df44	717	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
lypinator	0:bb348c97df44	718
lypinator	0:bb348c97df44	719	/* SysTick Current Register Definitions */
lypinator	0:bb348c97df44	720	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
lypinator	0:bb348c97df44	721	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
lypinator	0:bb348c97df44	722
lypinator	0:bb348c97df44	723	/* SysTick Calibration Register Definitions */
lypinator	0:bb348c97df44	724	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
lypinator	0:bb348c97df44	725	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
lypinator	0:bb348c97df44	726
lypinator	0:bb348c97df44	727	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
lypinator	0:bb348c97df44	728	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
lypinator	0:bb348c97df44	729
lypinator	0:bb348c97df44	730	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
lypinator	0:bb348c97df44	731	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
lypinator	0:bb348c97df44	732
lypinator	0:bb348c97df44	733	/@} end of group CMSIS_SysTick /
lypinator	0:bb348c97df44	734
lypinator	0:bb348c97df44	735
lypinator	0:bb348c97df44	736	/**
lypinator	0:bb348c97df44	737	\ingroup CMSIS_core_register
lypinator	0:bb348c97df44	738	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
lypinator	0:bb348c97df44	739	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
lypinator	0:bb348c97df44	740	@{
lypinator	0:bb348c97df44	741	*/
lypinator	0:bb348c97df44	742
lypinator	0:bb348c97df44	743	/**
lypinator	0:bb348c97df44	744	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
lypinator	0:bb348c97df44	745	*/
lypinator	0:bb348c97df44	746	typedef struct
lypinator	0:bb348c97df44	747	{
lypinator	0:bb348c97df44	748	__OM union
lypinator	0:bb348c97df44	749	{
lypinator	0:bb348c97df44	750	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
lypinator	0:bb348c97df44	751	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
lypinator	0:bb348c97df44	752	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
lypinator	0:bb348c97df44	753	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
lypinator	0:bb348c97df44	754	uint32_t RESERVED0[864U];
lypinator	0:bb348c97df44	755	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
lypinator	0:bb348c97df44	756	uint32_t RESERVED1[15U];
lypinator	0:bb348c97df44	757	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
lypinator	0:bb348c97df44	758	uint32_t RESERVED2[15U];
lypinator	0:bb348c97df44	759	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
lypinator	0:bb348c97df44	760	uint32_t RESERVED3[29U];
lypinator	0:bb348c97df44	761	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
lypinator	0:bb348c97df44	762	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
lypinator	0:bb348c97df44	763	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
lypinator	0:bb348c97df44	764	uint32_t RESERVED4[43U];
lypinator	0:bb348c97df44	765	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
lypinator	0:bb348c97df44	766	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
lypinator	0:bb348c97df44	767	uint32_t RESERVED5[6U];
lypinator	0:bb348c97df44	768	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
lypinator	0:bb348c97df44	769	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
lypinator	0:bb348c97df44	770	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
lypinator	0:bb348c97df44	771	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
lypinator	0:bb348c97df44	772	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
lypinator	0:bb348c97df44	773	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
lypinator	0:bb348c97df44	774	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
lypinator	0:bb348c97df44	775	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
lypinator	0:bb348c97df44	776	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
lypinator	0:bb348c97df44	777	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
lypinator	0:bb348c97df44	778	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
lypinator	0:bb348c97df44	779	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
lypinator	0:bb348c97df44	780	} ITM_Type;
lypinator	0:bb348c97df44	781
lypinator	0:bb348c97df44	782	/* ITM Trace Privilege Register Definitions */
lypinator	0:bb348c97df44	783	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
lypinator	0:bb348c97df44	784	#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
lypinator	0:bb348c97df44	785
lypinator	0:bb348c97df44	786	/* ITM Trace Control Register Definitions */
lypinator	0:bb348c97df44	787	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
lypinator	0:bb348c97df44	788	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
lypinator	0:bb348c97df44	789
lypinator	0:bb348c97df44	790	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
lypinator	0:bb348c97df44	791	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
lypinator	0:bb348c97df44	792
lypinator	0:bb348c97df44	793	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
lypinator	0:bb348c97df44	794	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
lypinator	0:bb348c97df44	795
lypinator	0:bb348c97df44	796	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
lypinator	0:bb348c97df44	797	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
lypinator	0:bb348c97df44	798
lypinator	0:bb348c97df44	799	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
lypinator	0:bb348c97df44	800	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
lypinator	0:bb348c97df44	801
lypinator	0:bb348c97df44	802	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
lypinator	0:bb348c97df44	803	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
lypinator	0:bb348c97df44	804
lypinator	0:bb348c97df44	805	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
lypinator	0:bb348c97df44	806	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
lypinator	0:bb348c97df44	807
lypinator	0:bb348c97df44	808	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
lypinator	0:bb348c97df44	809	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
lypinator	0:bb348c97df44	810
lypinator	0:bb348c97df44	811	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
lypinator	0:bb348c97df44	812	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
lypinator	0:bb348c97df44	813
lypinator	0:bb348c97df44	814	/* ITM Integration Write Register Definitions */
lypinator	0:bb348c97df44	815	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
lypinator	0:bb348c97df44	816	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
lypinator	0:bb348c97df44	817
lypinator	0:bb348c97df44	818	/* ITM Integration Read Register Definitions */
lypinator	0:bb348c97df44	819	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
lypinator	0:bb348c97df44	820	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
lypinator	0:bb348c97df44	821
lypinator	0:bb348c97df44	822	/* ITM Integration Mode Control Register Definitions */
lypinator	0:bb348c97df44	823	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
lypinator	0:bb348c97df44	824	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
lypinator	0:bb348c97df44	825
lypinator	0:bb348c97df44	826	/* ITM Lock Status Register Definitions */
lypinator	0:bb348c97df44	827	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
lypinator	0:bb348c97df44	828	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
lypinator	0:bb348c97df44	829
lypinator	0:bb348c97df44	830	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
lypinator	0:bb348c97df44	831	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
lypinator	0:bb348c97df44	832
lypinator	0:bb348c97df44	833	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
lypinator	0:bb348c97df44	834	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
lypinator	0:bb348c97df44	835
lypinator	0:bb348c97df44	836	/@}/ /* end of group CMSIS_ITM */
lypinator	0:bb348c97df44	837
lypinator	0:bb348c97df44	838
lypinator	0:bb348c97df44	839	/**
lypinator	0:bb348c97df44	840	\ingroup CMSIS_core_register
lypinator	0:bb348c97df44	841	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
lypinator	0:bb348c97df44	842	\brief Type definitions for the Data Watchpoint and Trace (DWT)
lypinator	0:bb348c97df44	843	@{
lypinator	0:bb348c97df44	844	*/
lypinator	0:bb348c97df44	845
lypinator	0:bb348c97df44	846	/**
lypinator	0:bb348c97df44	847	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
lypinator	0:bb348c97df44	848	*/
lypinator	0:bb348c97df44	849	typedef struct
lypinator	0:bb348c97df44	850	{
lypinator	0:bb348c97df44	851	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
lypinator	0:bb348c97df44	852	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
lypinator	0:bb348c97df44	853	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
lypinator	0:bb348c97df44	854	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
lypinator	0:bb348c97df44	855	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
lypinator	0:bb348c97df44	856	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
lypinator	0:bb348c97df44	857	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
lypinator	0:bb348c97df44	858	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
lypinator	0:bb348c97df44	859	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
lypinator	0:bb348c97df44	860	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
lypinator	0:bb348c97df44	861	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
lypinator	0:bb348c97df44	862	uint32_t RESERVED0[1U];
lypinator	0:bb348c97df44	863	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
lypinator	0:bb348c97df44	864	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
lypinator	0:bb348c97df44	865	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
lypinator	0:bb348c97df44	866	uint32_t RESERVED1[1U];
lypinator	0:bb348c97df44	867	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
lypinator	0:bb348c97df44	868	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
lypinator	0:bb348c97df44	869	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
lypinator	0:bb348c97df44	870	uint32_t RESERVED2[1U];
lypinator	0:bb348c97df44	871	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
lypinator	0:bb348c97df44	872	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
lypinator	0:bb348c97df44	873	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
lypinator	0:bb348c97df44	874	} DWT_Type;
lypinator	0:bb348c97df44	875
lypinator	0:bb348c97df44	876	/* DWT Control Register Definitions */
lypinator	0:bb348c97df44	877	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
lypinator	0:bb348c97df44	878	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
lypinator	0:bb348c97df44	879
lypinator	0:bb348c97df44	880	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
lypinator	0:bb348c97df44	881	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
lypinator	0:bb348c97df44	882
lypinator	0:bb348c97df44	883	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
lypinator	0:bb348c97df44	884	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
lypinator	0:bb348c97df44	885
lypinator	0:bb348c97df44	886	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
lypinator	0:bb348c97df44	887	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
lypinator	0:bb348c97df44	888
lypinator	0:bb348c97df44	889	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
lypinator	0:bb348c97df44	890	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
lypinator	0:bb348c97df44	891
lypinator	0:bb348c97df44	892	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
lypinator	0:bb348c97df44	893	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
lypinator	0:bb348c97df44	894
lypinator	0:bb348c97df44	895	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
lypinator	0:bb348c97df44	896	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
lypinator	0:bb348c97df44	897
lypinator	0:bb348c97df44	898	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
lypinator	0:bb348c97df44	899	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
lypinator	0:bb348c97df44	900
lypinator	0:bb348c97df44	901	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
lypinator	0:bb348c97df44	902	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
lypinator	0:bb348c97df44	903
lypinator	0:bb348c97df44	904	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
lypinator	0:bb348c97df44	905	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
lypinator	0:bb348c97df44	906
lypinator	0:bb348c97df44	907	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
lypinator	0:bb348c97df44	908	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
lypinator	0:bb348c97df44	909
lypinator	0:bb348c97df44	910	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
lypinator	0:bb348c97df44	911	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
lypinator	0:bb348c97df44	912
lypinator	0:bb348c97df44	913	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
lypinator	0:bb348c97df44	914	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
lypinator	0:bb348c97df44	915
lypinator	0:bb348c97df44	916	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
lypinator	0:bb348c97df44	917	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
lypinator	0:bb348c97df44	918
lypinator	0:bb348c97df44	919	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
lypinator	0:bb348c97df44	920	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
lypinator	0:bb348c97df44	921
lypinator	0:bb348c97df44	922	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
lypinator	0:bb348c97df44	923	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
lypinator	0:bb348c97df44	924
lypinator	0:bb348c97df44	925	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
lypinator	0:bb348c97df44	926	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
lypinator	0:bb348c97df44	927
lypinator	0:bb348c97df44	928	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
lypinator	0:bb348c97df44	929	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
lypinator	0:bb348c97df44	930
lypinator	0:bb348c97df44	931	/* DWT CPI Count Register Definitions */
lypinator	0:bb348c97df44	932	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
lypinator	0:bb348c97df44	933	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
lypinator	0:bb348c97df44	934
lypinator	0:bb348c97df44	935	/* DWT Exception Overhead Count Register Definitions */
lypinator	0:bb348c97df44	936	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
lypinator	0:bb348c97df44	937	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
lypinator	0:bb348c97df44	938
lypinator	0:bb348c97df44	939	/* DWT Sleep Count Register Definitions */
lypinator	0:bb348c97df44	940	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
lypinator	0:bb348c97df44	941	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
lypinator	0:bb348c97df44	942
lypinator	0:bb348c97df44	943	/* DWT LSU Count Register Definitions */
lypinator	0:bb348c97df44	944	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
lypinator	0:bb348c97df44	945	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
lypinator	0:bb348c97df44	946
lypinator	0:bb348c97df44	947	/* DWT Folded-instruction Count Register Definitions */
lypinator	0:bb348c97df44	948	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
lypinator	0:bb348c97df44	949	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
lypinator	0:bb348c97df44	950
lypinator	0:bb348c97df44	951	/* DWT Comparator Mask Register Definitions */
lypinator	0:bb348c97df44	952	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
lypinator	0:bb348c97df44	953	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
lypinator	0:bb348c97df44	954
lypinator	0:bb348c97df44	955	/* DWT Comparator Function Register Definitions */
lypinator	0:bb348c97df44	956	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
lypinator	0:bb348c97df44	957	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
lypinator	0:bb348c97df44	958
lypinator	0:bb348c97df44	959	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
lypinator	0:bb348c97df44	960	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
lypinator	0:bb348c97df44	961
lypinator	0:bb348c97df44	962	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
lypinator	0:bb348c97df44	963	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
lypinator	0:bb348c97df44	964
lypinator	0:bb348c97df44	965	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
lypinator	0:bb348c97df44	966	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
lypinator	0:bb348c97df44	967
lypinator	0:bb348c97df44	968	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
lypinator	0:bb348c97df44	969	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
lypinator	0:bb348c97df44	970
lypinator	0:bb348c97df44	971	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
lypinator	0:bb348c97df44	972	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
lypinator	0:bb348c97df44	973
lypinator	0:bb348c97df44	974	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
lypinator	0:bb348c97df44	975	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
lypinator	0:bb348c97df44	976
lypinator	0:bb348c97df44	977	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
lypinator	0:bb348c97df44	978	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
lypinator	0:bb348c97df44	979
lypinator	0:bb348c97df44	980	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
lypinator	0:bb348c97df44	981	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
lypinator	0:bb348c97df44	982
lypinator	0:bb348c97df44	983	/@}/ /* end of group CMSIS_DWT */
lypinator	0:bb348c97df44	984
lypinator	0:bb348c97df44	985
lypinator	0:bb348c97df44	986	/**
lypinator	0:bb348c97df44	987	\ingroup CMSIS_core_register
lypinator	0:bb348c97df44	988	\defgroup CMSIS_TPI Trace Port Interface (TPI)
lypinator	0:bb348c97df44	989	\brief Type definitions for the Trace Port Interface (TPI)
lypinator	0:bb348c97df44	990	@{
lypinator	0:bb348c97df44	991	*/
lypinator	0:bb348c97df44	992
lypinator	0:bb348c97df44	993	/**
lypinator	0:bb348c97df44	994	\brief Structure type to access the Trace Port Interface Register (TPI).
lypinator	0:bb348c97df44	995	*/
lypinator	0:bb348c97df44	996	typedef struct
lypinator	0:bb348c97df44	997	{
lypinator	0:bb348c97df44	998	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
lypinator	0:bb348c97df44	999	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
lypinator	0:bb348c97df44	1000	uint32_t RESERVED0[2U];
lypinator	0:bb348c97df44	1001	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
lypinator	0:bb348c97df44	1002	uint32_t RESERVED1[55U];
lypinator	0:bb348c97df44	1003	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
lypinator	0:bb348c97df44	1004	uint32_t RESERVED2[131U];
lypinator	0:bb348c97df44	1005	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
lypinator	0:bb348c97df44	1006	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
lypinator	0:bb348c97df44	1007	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
lypinator	0:bb348c97df44	1008	uint32_t RESERVED3[759U];
lypinator	0:bb348c97df44	1009	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
lypinator	0:bb348c97df44	1010	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
lypinator	0:bb348c97df44	1011	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
lypinator	0:bb348c97df44	1012	uint32_t RESERVED4[1U];
lypinator	0:bb348c97df44	1013	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
lypinator	0:bb348c97df44	1014	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
lypinator	0:bb348c97df44	1015	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
lypinator	0:bb348c97df44	1016	uint32_t RESERVED5[39U];
lypinator	0:bb348c97df44	1017	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
lypinator	0:bb348c97df44	1018	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
lypinator	0:bb348c97df44	1019	uint32_t RESERVED7[8U];
lypinator	0:bb348c97df44	1020	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
lypinator	0:bb348c97df44	1021	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
lypinator	0:bb348c97df44	1022	} TPI_Type;
lypinator	0:bb348c97df44	1023
lypinator	0:bb348c97df44	1024	/* TPI Asynchronous Clock Prescaler Register Definitions */
lypinator	0:bb348c97df44	1025	#define TPI_ACPR_PRESCALER_Pos 0U /!< @Deprecated TPI ACPR: PRESCALER Position /
lypinator	0:bb348c97df44	1026	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< @Deprecated TPI ACPR: PRESCALER Mask /
lypinator	0:bb348c97df44	1027
lypinator	0:bb348c97df44	1028	#define TPI_ACPR_SWOSCALER_Pos 0U /!< TPI ACPR: SWOSCALER Position /
lypinator	0:bb348c97df44	1029	#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/) /!< TPI ACPR: SWOSCALER Mask /
lypinator	0:bb348c97df44	1030
lypinator	0:bb348c97df44	1031	/* TPI Selected Pin Protocol Register Definitions */
lypinator	0:bb348c97df44	1032	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
lypinator	0:bb348c97df44	1033	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
lypinator	0:bb348c97df44	1034
lypinator	0:bb348c97df44	1035	/* TPI Formatter and Flush Status Register Definitions */
lypinator	0:bb348c97df44	1036	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
lypinator	0:bb348c97df44	1037	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
lypinator	0:bb348c97df44	1038
lypinator	0:bb348c97df44	1039	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
lypinator	0:bb348c97df44	1040	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
lypinator	0:bb348c97df44	1041
lypinator	0:bb348c97df44	1042	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
lypinator	0:bb348c97df44	1043	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
lypinator	0:bb348c97df44	1044
lypinator	0:bb348c97df44	1045	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
lypinator	0:bb348c97df44	1046	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
lypinator	0:bb348c97df44	1047
lypinator	0:bb348c97df44	1048	/* TPI Formatter and Flush Control Register Definitions */
lypinator	0:bb348c97df44	1049	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
lypinator	0:bb348c97df44	1050	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
lypinator	0:bb348c97df44	1051
lypinator	0:bb348c97df44	1052	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
lypinator	0:bb348c97df44	1053	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
lypinator	0:bb348c97df44	1054
lypinator	0:bb348c97df44	1055	/* TPI TRIGGER Register Definitions */
lypinator	0:bb348c97df44	1056	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
lypinator	0:bb348c97df44	1057	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
lypinator	0:bb348c97df44	1058
lypinator	0:bb348c97df44	1059	/* TPI Integration ETM Data Register Definitions (FIFO0) */
lypinator	0:bb348c97df44	1060	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
lypinator	0:bb348c97df44	1061	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
lypinator	0:bb348c97df44	1062
lypinator	0:bb348c97df44	1063	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
lypinator	0:bb348c97df44	1064	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
lypinator	0:bb348c97df44	1065
lypinator	0:bb348c97df44	1066	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
lypinator	0:bb348c97df44	1067	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
lypinator	0:bb348c97df44	1068
lypinator	0:bb348c97df44	1069	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
lypinator	0:bb348c97df44	1070	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
lypinator	0:bb348c97df44	1071
lypinator	0:bb348c97df44	1072	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
lypinator	0:bb348c97df44	1073	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
lypinator	0:bb348c97df44	1074
lypinator	0:bb348c97df44	1075	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
lypinator	0:bb348c97df44	1076	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
lypinator	0:bb348c97df44	1077
lypinator	0:bb348c97df44	1078	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
lypinator	0:bb348c97df44	1079	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
lypinator	0:bb348c97df44	1080
lypinator	0:bb348c97df44	1081	/* TPI ITATBCTR2 Register Definitions */
lypinator	0:bb348c97df44	1082	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
lypinator	0:bb348c97df44	1083	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
lypinator	0:bb348c97df44	1084
lypinator	0:bb348c97df44	1085	/* TPI Integration ITM Data Register Definitions (FIFO1) */
lypinator	0:bb348c97df44	1086	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
lypinator	0:bb348c97df44	1087	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
lypinator	0:bb348c97df44	1088
lypinator	0:bb348c97df44	1089	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
lypinator	0:bb348c97df44	1090	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
lypinator	0:bb348c97df44	1091
lypinator	0:bb348c97df44	1092	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
lypinator	0:bb348c97df44	1093	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
lypinator	0:bb348c97df44	1094
lypinator	0:bb348c97df44	1095	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
lypinator	0:bb348c97df44	1096	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
lypinator	0:bb348c97df44	1097
lypinator	0:bb348c97df44	1098	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
lypinator	0:bb348c97df44	1099	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
lypinator	0:bb348c97df44	1100
lypinator	0:bb348c97df44	1101	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
lypinator	0:bb348c97df44	1102	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
lypinator	0:bb348c97df44	1103
lypinator	0:bb348c97df44	1104	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
lypinator	0:bb348c97df44	1105	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
lypinator	0:bb348c97df44	1106
lypinator	0:bb348c97df44	1107	/* TPI ITATBCTR0 Register Definitions */
lypinator	0:bb348c97df44	1108	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
lypinator	0:bb348c97df44	1109	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
lypinator	0:bb348c97df44	1110
lypinator	0:bb348c97df44	1111	/* TPI Integration Mode Control Register Definitions */
lypinator	0:bb348c97df44	1112	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
lypinator	0:bb348c97df44	1113	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
lypinator	0:bb348c97df44	1114
lypinator	0:bb348c97df44	1115	/* TPI DEVID Register Definitions */
lypinator	0:bb348c97df44	1116	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
lypinator	0:bb348c97df44	1117	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
lypinator	0:bb348c97df44	1118
lypinator	0:bb348c97df44	1119	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
lypinator	0:bb348c97df44	1120	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
lypinator	0:bb348c97df44	1121
lypinator	0:bb348c97df44	1122	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
lypinator	0:bb348c97df44	1123	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
lypinator	0:bb348c97df44	1124
lypinator	0:bb348c97df44	1125	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
lypinator	0:bb348c97df44	1126	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
lypinator	0:bb348c97df44	1127
lypinator	0:bb348c97df44	1128	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
lypinator	0:bb348c97df44	1129	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
lypinator	0:bb348c97df44	1130
lypinator	0:bb348c97df44	1131	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
lypinator	0:bb348c97df44	1132	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
lypinator	0:bb348c97df44	1133
lypinator	0:bb348c97df44	1134	/* TPI DEVTYPE Register Definitions */
lypinator	0:bb348c97df44	1135	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
lypinator	0:bb348c97df44	1136	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
lypinator	0:bb348c97df44	1137
lypinator	0:bb348c97df44	1138	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
lypinator	0:bb348c97df44	1139	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
lypinator	0:bb348c97df44	1140
lypinator	0:bb348c97df44	1141	/@}/ /* end of group CMSIS_TPI */
lypinator	0:bb348c97df44	1142
lypinator	0:bb348c97df44	1143
lypinator	0:bb348c97df44	1144	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
lypinator	0:bb348c97df44	1145	/**
lypinator	0:bb348c97df44	1146	\ingroup CMSIS_core_register
lypinator	0:bb348c97df44	1147	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
lypinator	0:bb348c97df44	1148	\brief Type definitions for the Memory Protection Unit (MPU)
lypinator	0:bb348c97df44	1149	@{
lypinator	0:bb348c97df44	1150	*/
lypinator	0:bb348c97df44	1151
lypinator	0:bb348c97df44	1152	/**
lypinator	0:bb348c97df44	1153	\brief Structure type to access the Memory Protection Unit (MPU).
lypinator	0:bb348c97df44	1154	*/
lypinator	0:bb348c97df44	1155	typedef struct
lypinator	0:bb348c97df44	1156	{
lypinator	0:bb348c97df44	1157	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
lypinator	0:bb348c97df44	1158	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
lypinator	0:bb348c97df44	1159	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
lypinator	0:bb348c97df44	1160	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
lypinator	0:bb348c97df44	1161	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
lypinator	0:bb348c97df44	1162	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
lypinator	0:bb348c97df44	1163	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
lypinator	0:bb348c97df44	1164	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
lypinator	0:bb348c97df44	1165	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
lypinator	0:bb348c97df44	1166	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
lypinator	0:bb348c97df44	1167	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
lypinator	0:bb348c97df44	1168	} MPU_Type;
lypinator	0:bb348c97df44	1169
lypinator	0:bb348c97df44	1170	#define MPU_TYPE_RALIASES 4U
lypinator	0:bb348c97df44	1171
lypinator	0:bb348c97df44	1172	/* MPU Type Register Definitions */
lypinator	0:bb348c97df44	1173	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
lypinator	0:bb348c97df44	1174	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
lypinator	0:bb348c97df44	1175
lypinator	0:bb348c97df44	1176	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
lypinator	0:bb348c97df44	1177	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
lypinator	0:bb348c97df44	1178
lypinator	0:bb348c97df44	1179	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
lypinator	0:bb348c97df44	1180	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
lypinator	0:bb348c97df44	1181
lypinator	0:bb348c97df44	1182	/* MPU Control Register Definitions */
lypinator	0:bb348c97df44	1183	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
lypinator	0:bb348c97df44	1184	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
lypinator	0:bb348c97df44	1185
lypinator	0:bb348c97df44	1186	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
lypinator	0:bb348c97df44	1187	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
lypinator	0:bb348c97df44	1188
lypinator	0:bb348c97df44	1189	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
lypinator	0:bb348c97df44	1190	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
lypinator	0:bb348c97df44	1191
lypinator	0:bb348c97df44	1192	/* MPU Region Number Register Definitions */
lypinator	0:bb348c97df44	1193	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
lypinator	0:bb348c97df44	1194	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
lypinator	0:bb348c97df44	1195
lypinator	0:bb348c97df44	1196	/* MPU Region Base Address Register Definitions */
lypinator	0:bb348c97df44	1197	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
lypinator	0:bb348c97df44	1198	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
lypinator	0:bb348c97df44	1199
lypinator	0:bb348c97df44	1200	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
lypinator	0:bb348c97df44	1201	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
lypinator	0:bb348c97df44	1202
lypinator	0:bb348c97df44	1203	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
lypinator	0:bb348c97df44	1204	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
lypinator	0:bb348c97df44	1205
lypinator	0:bb348c97df44	1206	/* MPU Region Attribute and Size Register Definitions */
lypinator	0:bb348c97df44	1207	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
lypinator	0:bb348c97df44	1208	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
lypinator	0:bb348c97df44	1209
lypinator	0:bb348c97df44	1210	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
lypinator	0:bb348c97df44	1211	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
lypinator	0:bb348c97df44	1212
lypinator	0:bb348c97df44	1213	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
lypinator	0:bb348c97df44	1214	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
lypinator	0:bb348c97df44	1215
lypinator	0:bb348c97df44	1216	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
lypinator	0:bb348c97df44	1217	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
lypinator	0:bb348c97df44	1218
lypinator	0:bb348c97df44	1219	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
lypinator	0:bb348c97df44	1220	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
lypinator	0:bb348c97df44	1221
lypinator	0:bb348c97df44	1222	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
lypinator	0:bb348c97df44	1223	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
lypinator	0:bb348c97df44	1224
lypinator	0:bb348c97df44	1225	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
lypinator	0:bb348c97df44	1226	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
lypinator	0:bb348c97df44	1227
lypinator	0:bb348c97df44	1228	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
lypinator	0:bb348c97df44	1229	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
lypinator	0:bb348c97df44	1230
lypinator	0:bb348c97df44	1231	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
lypinator	0:bb348c97df44	1232	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
lypinator	0:bb348c97df44	1233
lypinator	0:bb348c97df44	1234	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
lypinator	0:bb348c97df44	1235	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
lypinator	0:bb348c97df44	1236
lypinator	0:bb348c97df44	1237	/@} end of group CMSIS_MPU /
lypinator	0:bb348c97df44	1238	#endif
lypinator	0:bb348c97df44	1239
lypinator	0:bb348c97df44	1240
lypinator	0:bb348c97df44	1241	/**
lypinator	0:bb348c97df44	1242	\ingroup CMSIS_core_register
lypinator	0:bb348c97df44	1243	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
lypinator	0:bb348c97df44	1244	\brief Type definitions for the Core Debug Registers
lypinator	0:bb348c97df44	1245	@{
lypinator	0:bb348c97df44	1246	*/
lypinator	0:bb348c97df44	1247
lypinator	0:bb348c97df44	1248	/**
lypinator	0:bb348c97df44	1249	\brief Structure type to access the Core Debug Register (CoreDebug).
lypinator	0:bb348c97df44	1250	*/
lypinator	0:bb348c97df44	1251	typedef struct
lypinator	0:bb348c97df44	1252	{
lypinator	0:bb348c97df44	1253	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
lypinator	0:bb348c97df44	1254	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
lypinator	0:bb348c97df44	1255	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
lypinator	0:bb348c97df44	1256	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
lypinator	0:bb348c97df44	1257	} CoreDebug_Type;
lypinator	0:bb348c97df44	1258
lypinator	0:bb348c97df44	1259	/* Debug Halting Control and Status Register Definitions */
lypinator	0:bb348c97df44	1260	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
lypinator	0:bb348c97df44	1261	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
lypinator	0:bb348c97df44	1262
lypinator	0:bb348c97df44	1263	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
lypinator	0:bb348c97df44	1264	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
lypinator	0:bb348c97df44	1265
lypinator	0:bb348c97df44	1266	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
lypinator	0:bb348c97df44	1267	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
lypinator	0:bb348c97df44	1268
lypinator	0:bb348c97df44	1269	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
lypinator	0:bb348c97df44	1270	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
lypinator	0:bb348c97df44	1271
lypinator	0:bb348c97df44	1272	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
lypinator	0:bb348c97df44	1273	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
lypinator	0:bb348c97df44	1274
lypinator	0:bb348c97df44	1275	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
lypinator	0:bb348c97df44	1276	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
lypinator	0:bb348c97df44	1277
lypinator	0:bb348c97df44	1278	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
lypinator	0:bb348c97df44	1279	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
lypinator	0:bb348c97df44	1280
lypinator	0:bb348c97df44	1281	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
lypinator	0:bb348c97df44	1282	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
lypinator	0:bb348c97df44	1283
lypinator	0:bb348c97df44	1284	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
lypinator	0:bb348c97df44	1285	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
lypinator	0:bb348c97df44	1286
lypinator	0:bb348c97df44	1287	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
lypinator	0:bb348c97df44	1288	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
lypinator	0:bb348c97df44	1289
lypinator	0:bb348c97df44	1290	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
lypinator	0:bb348c97df44	1291	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
lypinator	0:bb348c97df44	1292
lypinator	0:bb348c97df44	1293	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
lypinator	0:bb348c97df44	1294	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
lypinator	0:bb348c97df44	1295
lypinator	0:bb348c97df44	1296	/* Debug Core Register Selector Register Definitions */
lypinator	0:bb348c97df44	1297	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
lypinator	0:bb348c97df44	1298	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
lypinator	0:bb348c97df44	1299
lypinator	0:bb348c97df44	1300	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
lypinator	0:bb348c97df44	1301	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
lypinator	0:bb348c97df44	1302
lypinator	0:bb348c97df44	1303	/* Debug Exception and Monitor Control Register Definitions */
lypinator	0:bb348c97df44	1304	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
lypinator	0:bb348c97df44	1305	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
lypinator	0:bb348c97df44	1306
lypinator	0:bb348c97df44	1307	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
lypinator	0:bb348c97df44	1308	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
lypinator	0:bb348c97df44	1309
lypinator	0:bb348c97df44	1310	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
lypinator	0:bb348c97df44	1311	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
lypinator	0:bb348c97df44	1312
lypinator	0:bb348c97df44	1313	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
lypinator	0:bb348c97df44	1314	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
lypinator	0:bb348c97df44	1315
lypinator	0:bb348c97df44	1316	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
lypinator	0:bb348c97df44	1317	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
lypinator	0:bb348c97df44	1318
lypinator	0:bb348c97df44	1319	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
lypinator	0:bb348c97df44	1320	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
lypinator	0:bb348c97df44	1321
lypinator	0:bb348c97df44	1322	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
lypinator	0:bb348c97df44	1323	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
lypinator	0:bb348c97df44	1324
lypinator	0:bb348c97df44	1325	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
lypinator	0:bb348c97df44	1326	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
lypinator	0:bb348c97df44	1327
lypinator	0:bb348c97df44	1328	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
lypinator	0:bb348c97df44	1329	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
lypinator	0:bb348c97df44	1330
lypinator	0:bb348c97df44	1331	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
lypinator	0:bb348c97df44	1332	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
lypinator	0:bb348c97df44	1333
lypinator	0:bb348c97df44	1334	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
lypinator	0:bb348c97df44	1335	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
lypinator	0:bb348c97df44	1336
lypinator	0:bb348c97df44	1337	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
lypinator	0:bb348c97df44	1338	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
lypinator	0:bb348c97df44	1339
lypinator	0:bb348c97df44	1340	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
lypinator	0:bb348c97df44	1341	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
lypinator	0:bb348c97df44	1342
lypinator	0:bb348c97df44	1343	/@} end of group CMSIS_CoreDebug /
lypinator	0:bb348c97df44	1344
lypinator	0:bb348c97df44	1345
lypinator	0:bb348c97df44	1346	/**
lypinator	0:bb348c97df44	1347	\ingroup CMSIS_core_register
lypinator	0:bb348c97df44	1348	\defgroup CMSIS_core_bitfield Core register bit field macros
lypinator	0:bb348c97df44	1349	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
lypinator	0:bb348c97df44	1350	@{
lypinator	0:bb348c97df44	1351	*/
lypinator	0:bb348c97df44	1352
lypinator	0:bb348c97df44	1353	/**
lypinator	0:bb348c97df44	1354	\brief Mask and shift a bit field value for use in a register bit range.
lypinator	0:bb348c97df44	1355	\param[in] field Name of the register bit field.
lypinator	0:bb348c97df44	1356	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
lypinator	0:bb348c97df44	1357	\return Masked and shifted value.
lypinator	0:bb348c97df44	1358	*/
lypinator	0:bb348c97df44	1359	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
lypinator	0:bb348c97df44	1360
lypinator	0:bb348c97df44	1361	/**
lypinator	0:bb348c97df44	1362	\brief Mask and shift a register value to extract a bit filed value.
lypinator	0:bb348c97df44	1363	\param[in] field Name of the register bit field.
lypinator	0:bb348c97df44	1364	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
lypinator	0:bb348c97df44	1365	\return Masked and shifted bit field value.
lypinator	0:bb348c97df44	1366	*/
lypinator	0:bb348c97df44	1367	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
lypinator	0:bb348c97df44	1368
lypinator	0:bb348c97df44	1369	/@} end of group CMSIS_core_bitfield /
lypinator	0:bb348c97df44	1370
lypinator	0:bb348c97df44	1371
lypinator	0:bb348c97df44	1372	/**
lypinator	0:bb348c97df44	1373	\ingroup CMSIS_core_register
lypinator	0:bb348c97df44	1374	\defgroup CMSIS_core_base Core Definitions
lypinator	0:bb348c97df44	1375	\brief Definitions for base addresses, unions, and structures.
lypinator	0:bb348c97df44	1376	@{
lypinator	0:bb348c97df44	1377	*/
lypinator	0:bb348c97df44	1378
lypinator	0:bb348c97df44	1379	/* Memory mapping of Core Hardware */
lypinator	0:bb348c97df44	1380	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
lypinator	0:bb348c97df44	1381	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
lypinator	0:bb348c97df44	1382	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
lypinator	0:bb348c97df44	1383	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
lypinator	0:bb348c97df44	1384	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
lypinator	0:bb348c97df44	1385	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
lypinator	0:bb348c97df44	1386	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
lypinator	0:bb348c97df44	1387	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
lypinator	0:bb348c97df44	1388
lypinator	0:bb348c97df44	1389	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
lypinator	0:bb348c97df44	1390	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
lypinator	0:bb348c97df44	1391	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
lypinator	0:bb348c97df44	1392	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
lypinator	0:bb348c97df44	1393	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
lypinator	0:bb348c97df44	1394	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
lypinator	0:bb348c97df44	1395	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
lypinator	0:bb348c97df44	1396	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
lypinator	0:bb348c97df44	1397
lypinator	0:bb348c97df44	1398	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
lypinator	0:bb348c97df44	1399	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
lypinator	0:bb348c97df44	1400	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
lypinator	0:bb348c97df44	1401	#endif
lypinator	0:bb348c97df44	1402
lypinator	0:bb348c97df44	1403	/@} /
lypinator	0:bb348c97df44	1404
lypinator	0:bb348c97df44	1405
lypinator	0:bb348c97df44	1406
lypinator	0:bb348c97df44	1407	/*******************************************************************************
lypinator	0:bb348c97df44	1408	* Hardware Abstraction Layer
lypinator	0:bb348c97df44	1409	Core Function Interface contains:
lypinator	0:bb348c97df44	1410	- Core NVIC Functions
lypinator	0:bb348c97df44	1411	- Core SysTick Functions
lypinator	0:bb348c97df44	1412	- Core Debug Functions
lypinator	0:bb348c97df44	1413	- Core Register Access Functions
lypinator	0:bb348c97df44	1414	******************************************************************************/
lypinator	0:bb348c97df44	1415	/**
lypinator	0:bb348c97df44	1416	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
lypinator	0:bb348c97df44	1417	*/
lypinator	0:bb348c97df44	1418
lypinator	0:bb348c97df44	1419
lypinator	0:bb348c97df44	1420
lypinator	0:bb348c97df44	1421	/* ########################## NVIC functions #################################### */
lypinator	0:bb348c97df44	1422	/**
lypinator	0:bb348c97df44	1423	\ingroup CMSIS_Core_FunctionInterface
lypinator	0:bb348c97df44	1424	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
lypinator	0:bb348c97df44	1425	\brief Functions that manage interrupts and exceptions via the NVIC.
lypinator	0:bb348c97df44	1426	@{
lypinator	0:bb348c97df44	1427	*/
lypinator	0:bb348c97df44	1428
lypinator	0:bb348c97df44	1429	#ifdef CMSIS_NVIC_VIRTUAL
lypinator	0:bb348c97df44	1430	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
lypinator	0:bb348c97df44	1431	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
lypinator	0:bb348c97df44	1432	#endif
lypinator	0:bb348c97df44	1433	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
lypinator	0:bb348c97df44	1434	#else
lypinator	0:bb348c97df44	1435	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
lypinator	0:bb348c97df44	1436	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
lypinator	0:bb348c97df44	1437	#define NVIC_EnableIRQ __NVIC_EnableIRQ
lypinator	0:bb348c97df44	1438	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
lypinator	0:bb348c97df44	1439	#define NVIC_DisableIRQ __NVIC_DisableIRQ
lypinator	0:bb348c97df44	1440	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
lypinator	0:bb348c97df44	1441	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
lypinator	0:bb348c97df44	1442	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
lypinator	0:bb348c97df44	1443	#define NVIC_GetActive __NVIC_GetActive
lypinator	0:bb348c97df44	1444	#define NVIC_SetPriority __NVIC_SetPriority
lypinator	0:bb348c97df44	1445	#define NVIC_GetPriority __NVIC_GetPriority
lypinator	0:bb348c97df44	1446	#define NVIC_SystemReset __NVIC_SystemReset
lypinator	0:bb348c97df44	1447	#endif /* CMSIS_NVIC_VIRTUAL */
lypinator	0:bb348c97df44	1448
lypinator	0:bb348c97df44	1449	#ifdef CMSIS_VECTAB_VIRTUAL
lypinator	0:bb348c97df44	1450	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
lypinator	0:bb348c97df44	1451	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
lypinator	0:bb348c97df44	1452	#endif
lypinator	0:bb348c97df44	1453	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
lypinator	0:bb348c97df44	1454	#else
lypinator	0:bb348c97df44	1455	#define NVIC_SetVector __NVIC_SetVector
lypinator	0:bb348c97df44	1456	#define NVIC_GetVector __NVIC_GetVector
lypinator	0:bb348c97df44	1457	#endif /* (CMSIS_VECTAB_VIRTUAL) */
lypinator	0:bb348c97df44	1458
lypinator	0:bb348c97df44	1459	#define NVIC_USER_IRQ_OFFSET 16
lypinator	0:bb348c97df44	1460
lypinator	0:bb348c97df44	1461
lypinator	0:bb348c97df44	1462
lypinator	0:bb348c97df44	1463	/**
lypinator	0:bb348c97df44	1464	\brief Set Priority Grouping
lypinator	0:bb348c97df44	1465	\details Sets the priority grouping field using the required unlock sequence.
lypinator	0:bb348c97df44	1466	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
lypinator	0:bb348c97df44	1467	Only values from 0..7 are used.
lypinator	0:bb348c97df44	1468	In case of a conflict between priority grouping and available
lypinator	0:bb348c97df44	1469	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
lypinator	0:bb348c97df44	1470	\param [in] PriorityGroup Priority grouping field.
lypinator	0:bb348c97df44	1471	*/
lypinator	0:bb348c97df44	1472	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
lypinator	0:bb348c97df44	1473	{
lypinator	0:bb348c97df44	1474	uint32_t reg_value;
lypinator	0:bb348c97df44	1475	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
lypinator	0:bb348c97df44	1476
lypinator	0:bb348c97df44	1477	reg_value = SCB->AIRCR; /* read old register configuration */
lypinator	0:bb348c97df44	1478	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
lypinator	0:bb348c97df44	1479	reg_value = (reg_value \|
lypinator	0:bb348c97df44	1480	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
lypinator	0:bb348c97df44	1481	(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
lypinator	0:bb348c97df44	1482	SCB->AIRCR = reg_value;
lypinator	0:bb348c97df44	1483	}
lypinator	0:bb348c97df44	1484
lypinator	0:bb348c97df44	1485
lypinator	0:bb348c97df44	1486	/**
lypinator	0:bb348c97df44	1487	\brief Get Priority Grouping
lypinator	0:bb348c97df44	1488	\details Reads the priority grouping field from the NVIC Interrupt Controller.
lypinator	0:bb348c97df44	1489	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
lypinator	0:bb348c97df44	1490	*/
lypinator	0:bb348c97df44	1491	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
lypinator	0:bb348c97df44	1492	{
lypinator	0:bb348c97df44	1493	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
lypinator	0:bb348c97df44	1494	}
lypinator	0:bb348c97df44	1495
lypinator	0:bb348c97df44	1496
lypinator	0:bb348c97df44	1497	/**
lypinator	0:bb348c97df44	1498	\brief Enable Interrupt
lypinator	0:bb348c97df44	1499	\details Enables a device specific interrupt in the NVIC interrupt controller.
lypinator	0:bb348c97df44	1500	\param [in] IRQn Device specific interrupt number.
lypinator	0:bb348c97df44	1501	\note IRQn must not be negative.
lypinator	0:bb348c97df44	1502	*/
lypinator	0:bb348c97df44	1503	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1504	{
lypinator	0:bb348c97df44	1505	if ((int32_t)(IRQn) >= 0)
lypinator	0:bb348c97df44	1506	{
lypinator	0:bb348c97df44	1507	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator	0:bb348c97df44	1508	}
lypinator	0:bb348c97df44	1509	}
lypinator	0:bb348c97df44	1510
lypinator	0:bb348c97df44	1511
lypinator	0:bb348c97df44	1512	/**
lypinator	0:bb348c97df44	1513	\brief Get Interrupt Enable status
lypinator	0:bb348c97df44	1514	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
lypinator	0:bb348c97df44	1515	\param [in] IRQn Device specific interrupt number.
lypinator	0:bb348c97df44	1516	\return 0 Interrupt is not enabled.
lypinator	0:bb348c97df44	1517	\return 1 Interrupt is enabled.
lypinator	0:bb348c97df44	1518	\note IRQn must not be negative.
lypinator	0:bb348c97df44	1519	*/
lypinator	0:bb348c97df44	1520	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1521	{
lypinator	0:bb348c97df44	1522	if ((int32_t)(IRQn) >= 0)
lypinator	0:bb348c97df44	1523	{
lypinator	0:bb348c97df44	1524	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
lypinator	0:bb348c97df44	1525	}
lypinator	0:bb348c97df44	1526	else
lypinator	0:bb348c97df44	1527	{
lypinator	0:bb348c97df44	1528	return(0U);
lypinator	0:bb348c97df44	1529	}
lypinator	0:bb348c97df44	1530	}
lypinator	0:bb348c97df44	1531
lypinator	0:bb348c97df44	1532
lypinator	0:bb348c97df44	1533	/**
lypinator	0:bb348c97df44	1534	\brief Disable Interrupt
lypinator	0:bb348c97df44	1535	\details Disables a device specific interrupt in the NVIC interrupt controller.
lypinator	0:bb348c97df44	1536	\param [in] IRQn Device specific interrupt number.
lypinator	0:bb348c97df44	1537	\note IRQn must not be negative.
lypinator	0:bb348c97df44	1538	*/
lypinator	0:bb348c97df44	1539	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1540	{
lypinator	0:bb348c97df44	1541	if ((int32_t)(IRQn) >= 0)
lypinator	0:bb348c97df44	1542	{
lypinator	0:bb348c97df44	1543	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator	0:bb348c97df44	1544	__DSB();
lypinator	0:bb348c97df44	1545	__ISB();
lypinator	0:bb348c97df44	1546	}
lypinator	0:bb348c97df44	1547	}
lypinator	0:bb348c97df44	1548
lypinator	0:bb348c97df44	1549
lypinator	0:bb348c97df44	1550	/**
lypinator	0:bb348c97df44	1551	\brief Get Pending Interrupt
lypinator	0:bb348c97df44	1552	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
lypinator	0:bb348c97df44	1553	\param [in] IRQn Device specific interrupt number.
lypinator	0:bb348c97df44	1554	\return 0 Interrupt status is not pending.
lypinator	0:bb348c97df44	1555	\return 1 Interrupt status is pending.
lypinator	0:bb348c97df44	1556	\note IRQn must not be negative.
lypinator	0:bb348c97df44	1557	*/
lypinator	0:bb348c97df44	1558	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1559	{
lypinator	0:bb348c97df44	1560	if ((int32_t)(IRQn) >= 0)
lypinator	0:bb348c97df44	1561	{
lypinator	0:bb348c97df44	1562	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
lypinator	0:bb348c97df44	1563	}
lypinator	0:bb348c97df44	1564	else
lypinator	0:bb348c97df44	1565	{
lypinator	0:bb348c97df44	1566	return(0U);
lypinator	0:bb348c97df44	1567	}
lypinator	0:bb348c97df44	1568	}
lypinator	0:bb348c97df44	1569
lypinator	0:bb348c97df44	1570
lypinator	0:bb348c97df44	1571	/**
lypinator	0:bb348c97df44	1572	\brief Set Pending Interrupt
lypinator	0:bb348c97df44	1573	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
lypinator	0:bb348c97df44	1574	\param [in] IRQn Device specific interrupt number.
lypinator	0:bb348c97df44	1575	\note IRQn must not be negative.
lypinator	0:bb348c97df44	1576	*/
lypinator	0:bb348c97df44	1577	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1578	{
lypinator	0:bb348c97df44	1579	if ((int32_t)(IRQn) >= 0)
lypinator	0:bb348c97df44	1580	{
lypinator	0:bb348c97df44	1581	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator	0:bb348c97df44	1582	}
lypinator	0:bb348c97df44	1583	}
lypinator	0:bb348c97df44	1584
lypinator	0:bb348c97df44	1585
lypinator	0:bb348c97df44	1586	/**
lypinator	0:bb348c97df44	1587	\brief Clear Pending Interrupt
lypinator	0:bb348c97df44	1588	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
lypinator	0:bb348c97df44	1589	\param [in] IRQn Device specific interrupt number.
lypinator	0:bb348c97df44	1590	\note IRQn must not be negative.
lypinator	0:bb348c97df44	1591	*/
lypinator	0:bb348c97df44	1592	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1593	{
lypinator	0:bb348c97df44	1594	if ((int32_t)(IRQn) >= 0)
lypinator	0:bb348c97df44	1595	{
lypinator	0:bb348c97df44	1596	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator	0:bb348c97df44	1597	}
lypinator	0:bb348c97df44	1598	}
lypinator	0:bb348c97df44	1599
lypinator	0:bb348c97df44	1600
lypinator	0:bb348c97df44	1601	/**
lypinator	0:bb348c97df44	1602	\brief Get Active Interrupt
lypinator	0:bb348c97df44	1603	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
lypinator	0:bb348c97df44	1604	\param [in] IRQn Device specific interrupt number.
lypinator	0:bb348c97df44	1605	\return 0 Interrupt status is not active.
lypinator	0:bb348c97df44	1606	\return 1 Interrupt status is active.
lypinator	0:bb348c97df44	1607	\note IRQn must not be negative.
lypinator	0:bb348c97df44	1608	*/
lypinator	0:bb348c97df44	1609	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1610	{
lypinator	0:bb348c97df44	1611	if ((int32_t)(IRQn) >= 0)
lypinator	0:bb348c97df44	1612	{
lypinator	0:bb348c97df44	1613	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
lypinator	0:bb348c97df44	1614	}
lypinator	0:bb348c97df44	1615	else
lypinator	0:bb348c97df44	1616	{
lypinator	0:bb348c97df44	1617	return(0U);
lypinator	0:bb348c97df44	1618	}
lypinator	0:bb348c97df44	1619	}
lypinator	0:bb348c97df44	1620
lypinator	0:bb348c97df44	1621
lypinator	0:bb348c97df44	1622	/**
lypinator	0:bb348c97df44	1623	\brief Set Interrupt Priority
lypinator	0:bb348c97df44	1624	\details Sets the priority of a device specific interrupt or a processor exception.
lypinator	0:bb348c97df44	1625	The interrupt number can be positive to specify a device specific interrupt,
lypinator	0:bb348c97df44	1626	or negative to specify a processor exception.
lypinator	0:bb348c97df44	1627	\param [in] IRQn Interrupt number.
lypinator	0:bb348c97df44	1628	\param [in] priority Priority to set.
lypinator	0:bb348c97df44	1629	\note The priority cannot be set for every processor exception.
lypinator	0:bb348c97df44	1630	*/
lypinator	0:bb348c97df44	1631	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
lypinator	0:bb348c97df44	1632	{
lypinator	0:bb348c97df44	1633	if ((int32_t)(IRQn) >= 0)
lypinator	0:bb348c97df44	1634	{
lypinator	0:bb348c97df44	1635	NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
lypinator	0:bb348c97df44	1636	}
lypinator	0:bb348c97df44	1637	else
lypinator	0:bb348c97df44	1638	{
lypinator	0:bb348c97df44	1639	SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
lypinator	0:bb348c97df44	1640	}
lypinator	0:bb348c97df44	1641	}
lypinator	0:bb348c97df44	1642
lypinator	0:bb348c97df44	1643
lypinator	0:bb348c97df44	1644	/**
lypinator	0:bb348c97df44	1645	\brief Get Interrupt Priority
lypinator	0:bb348c97df44	1646	\details Reads the priority of a device specific interrupt or a processor exception.
lypinator	0:bb348c97df44	1647	The interrupt number can be positive to specify a device specific interrupt,
lypinator	0:bb348c97df44	1648	or negative to specify a processor exception.
lypinator	0:bb348c97df44	1649	\param [in] IRQn Interrupt number.
lypinator	0:bb348c97df44	1650	\return Interrupt Priority.
lypinator	0:bb348c97df44	1651	Value is aligned automatically to the implemented priority bits of the microcontroller.
lypinator	0:bb348c97df44	1652	*/
lypinator	0:bb348c97df44	1653	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1654	{
lypinator	0:bb348c97df44	1655
lypinator	0:bb348c97df44	1656	if ((int32_t)(IRQn) >= 0)
lypinator	0:bb348c97df44	1657	{
lypinator	0:bb348c97df44	1658	return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
lypinator	0:bb348c97df44	1659	}
lypinator	0:bb348c97df44	1660	else
lypinator	0:bb348c97df44	1661	{
lypinator	0:bb348c97df44	1662	return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
lypinator	0:bb348c97df44	1663	}
lypinator	0:bb348c97df44	1664	}
lypinator	0:bb348c97df44	1665
lypinator	0:bb348c97df44	1666
lypinator	0:bb348c97df44	1667	/**
lypinator	0:bb348c97df44	1668	\brief Encode Priority
lypinator	0:bb348c97df44	1669	\details Encodes the priority for an interrupt with the given priority group,
lypinator	0:bb348c97df44	1670	preemptive priority value, and subpriority value.
lypinator	0:bb348c97df44	1671	In case of a conflict between priority grouping and available
lypinator	0:bb348c97df44	1672	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
lypinator	0:bb348c97df44	1673	\param [in] PriorityGroup Used priority group.
lypinator	0:bb348c97df44	1674	\param [in] PreemptPriority Preemptive priority value (starting from 0).
lypinator	0:bb348c97df44	1675	\param [in] SubPriority Subpriority value (starting from 0).
lypinator	0:bb348c97df44	1676	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
lypinator	0:bb348c97df44	1677	*/
lypinator	0:bb348c97df44	1678	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
lypinator	0:bb348c97df44	1679	{
lypinator	0:bb348c97df44	1680	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
lypinator	0:bb348c97df44	1681	uint32_t PreemptPriorityBits;
lypinator	0:bb348c97df44	1682	uint32_t SubPriorityBits;
lypinator	0:bb348c97df44	1683
lypinator	0:bb348c97df44	1684	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
lypinator	0:bb348c97df44	1685	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
lypinator	0:bb348c97df44	1686
lypinator	0:bb348c97df44	1687	return (
lypinator	0:bb348c97df44	1688	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
lypinator	0:bb348c97df44	1689	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
lypinator	0:bb348c97df44	1690	);
lypinator	0:bb348c97df44	1691	}
lypinator	0:bb348c97df44	1692
lypinator	0:bb348c97df44	1693
lypinator	0:bb348c97df44	1694	/**
lypinator	0:bb348c97df44	1695	\brief Decode Priority
lypinator	0:bb348c97df44	1696	\details Decodes an interrupt priority value with a given priority group to
lypinator	0:bb348c97df44	1697	preemptive priority value and subpriority value.
lypinator	0:bb348c97df44	1698	In case of a conflict between priority grouping and available
lypinator	0:bb348c97df44	1699	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
lypinator	0:bb348c97df44	1700	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
lypinator	0:bb348c97df44	1701	\param [in] PriorityGroup Used priority group.
lypinator	0:bb348c97df44	1702	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
lypinator	0:bb348c97df44	1703	\param [out] pSubPriority Subpriority value (starting from 0).
lypinator	0:bb348c97df44	1704	*/
lypinator	0:bb348c97df44	1705	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
lypinator	0:bb348c97df44	1706	{
lypinator	0:bb348c97df44	1707	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
lypinator	0:bb348c97df44	1708	uint32_t PreemptPriorityBits;
lypinator	0:bb348c97df44	1709	uint32_t SubPriorityBits;
lypinator	0:bb348c97df44	1710
lypinator	0:bb348c97df44	1711	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
lypinator	0:bb348c97df44	1712	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
lypinator	0:bb348c97df44	1713
lypinator	0:bb348c97df44	1714	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
lypinator	0:bb348c97df44	1715	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
lypinator	0:bb348c97df44	1716	}
lypinator	0:bb348c97df44	1717
lypinator	0:bb348c97df44	1718
lypinator	0:bb348c97df44	1719	/**
lypinator	0:bb348c97df44	1720	\brief Set Interrupt Vector
lypinator	0:bb348c97df44	1721	\details Sets an interrupt vector in SRAM based interrupt vector table.
lypinator	0:bb348c97df44	1722	The interrupt number can be positive to specify a device specific interrupt,
lypinator	0:bb348c97df44	1723	or negative to specify a processor exception.
lypinator	0:bb348c97df44	1724	VTOR must been relocated to SRAM before.
lypinator	0:bb348c97df44	1725	\param [in] IRQn Interrupt number
lypinator	0:bb348c97df44	1726	\param [in] vector Address of interrupt handler function
lypinator	0:bb348c97df44	1727	*/
lypinator	0:bb348c97df44	1728	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
lypinator	0:bb348c97df44	1729	{
lypinator	0:bb348c97df44	1730	uint32_t vectors = (uint32_t )SCB->VTOR;
lypinator	0:bb348c97df44	1731	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
lypinator	0:bb348c97df44	1732	}
lypinator	0:bb348c97df44	1733
lypinator	0:bb348c97df44	1734
lypinator	0:bb348c97df44	1735	/**
lypinator	0:bb348c97df44	1736	\brief Get Interrupt Vector
lypinator	0:bb348c97df44	1737	\details Reads an interrupt vector from interrupt vector table.
lypinator	0:bb348c97df44	1738	The interrupt number can be positive to specify a device specific interrupt,
lypinator	0:bb348c97df44	1739	or negative to specify a processor exception.
lypinator	0:bb348c97df44	1740	\param [in] IRQn Interrupt number.
lypinator	0:bb348c97df44	1741	\return Address of interrupt handler function
lypinator	0:bb348c97df44	1742	*/
lypinator	0:bb348c97df44	1743	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1744	{
lypinator	0:bb348c97df44	1745	uint32_t vectors = (uint32_t )SCB->VTOR;
lypinator	0:bb348c97df44	1746	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
lypinator	0:bb348c97df44	1747	}
lypinator	0:bb348c97df44	1748
lypinator	0:bb348c97df44	1749
lypinator	0:bb348c97df44	1750	/**
lypinator	0:bb348c97df44	1751	\brief System Reset
lypinator	0:bb348c97df44	1752	\details Initiates a system reset request to reset the MCU.
lypinator	0:bb348c97df44	1753	*/
lypinator	0:bb348c97df44	1754	__STATIC_INLINE void __NVIC_SystemReset(void)
lypinator	0:bb348c97df44	1755	{
lypinator	0:bb348c97df44	1756	__DSB(); /* Ensure all outstanding memory accesses included
lypinator	0:bb348c97df44	1757	buffered write are completed before reset */
lypinator	0:bb348c97df44	1758	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
lypinator	0:bb348c97df44	1759	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
lypinator	0:bb348c97df44	1760	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
lypinator	0:bb348c97df44	1761	__DSB(); /* Ensure completion of memory access */
lypinator	0:bb348c97df44	1762
lypinator	0:bb348c97df44	1763	for(;;) /* wait until reset */
lypinator	0:bb348c97df44	1764	{
lypinator	0:bb348c97df44	1765	__NOP();
lypinator	0:bb348c97df44	1766	}
lypinator	0:bb348c97df44	1767	}
lypinator	0:bb348c97df44	1768
lypinator	0:bb348c97df44	1769	/@} end of CMSIS_Core_NVICFunctions /
lypinator	0:bb348c97df44	1770
lypinator	0:bb348c97df44	1771	/* ########################## MPU functions #################################### */
lypinator	0:bb348c97df44	1772
lypinator	0:bb348c97df44	1773	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
lypinator	0:bb348c97df44	1774
lypinator	0:bb348c97df44	1775	#include "mpu_armv7.h"
lypinator	0:bb348c97df44	1776
lypinator	0:bb348c97df44	1777	#endif
lypinator	0:bb348c97df44	1778
lypinator	0:bb348c97df44	1779	/* ########################## FPU functions #################################### */
lypinator	0:bb348c97df44	1780	/**
lypinator	0:bb348c97df44	1781	\ingroup CMSIS_Core_FunctionInterface
lypinator	0:bb348c97df44	1782	\defgroup CMSIS_Core_FpuFunctions FPU Functions
lypinator	0:bb348c97df44	1783	\brief Function that provides FPU type.
lypinator	0:bb348c97df44	1784	@{
lypinator	0:bb348c97df44	1785	*/
lypinator	0:bb348c97df44	1786
lypinator	0:bb348c97df44	1787	/**
lypinator	0:bb348c97df44	1788	\brief get FPU type
lypinator	0:bb348c97df44	1789	\details returns the FPU type
lypinator	0:bb348c97df44	1790	\returns
lypinator	0:bb348c97df44	1791	- \b 0: No FPU
lypinator	0:bb348c97df44	1792	- \b 1: Single precision FPU
lypinator	0:bb348c97df44	1793	- \b 2: Double + Single precision FPU
lypinator	0:bb348c97df44	1794	*/
lypinator	0:bb348c97df44	1795	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
lypinator	0:bb348c97df44	1796	{
lypinator	0:bb348c97df44	1797	return 0U; /* No FPU */
lypinator	0:bb348c97df44	1798	}
lypinator	0:bb348c97df44	1799
lypinator	0:bb348c97df44	1800
lypinator	0:bb348c97df44	1801	/@} end of CMSIS_Core_FpuFunctions /
lypinator	0:bb348c97df44	1802
lypinator	0:bb348c97df44	1803
lypinator	0:bb348c97df44	1804
lypinator	0:bb348c97df44	1805	/* ################################## SysTick function ############################################ */
lypinator	0:bb348c97df44	1806	/**
lypinator	0:bb348c97df44	1807	\ingroup CMSIS_Core_FunctionInterface
lypinator	0:bb348c97df44	1808	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
lypinator	0:bb348c97df44	1809	\brief Functions that configure the System.
lypinator	0:bb348c97df44	1810	@{
lypinator	0:bb348c97df44	1811	*/
lypinator	0:bb348c97df44	1812
lypinator	0:bb348c97df44	1813	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
lypinator	0:bb348c97df44	1814
lypinator	0:bb348c97df44	1815	/**
lypinator	0:bb348c97df44	1816	\brief System Tick Configuration
lypinator	0:bb348c97df44	1817	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
lypinator	0:bb348c97df44	1818	Counter is in free running mode to generate periodic interrupts.
lypinator	0:bb348c97df44	1819	\param [in] ticks Number of ticks between two interrupts.
lypinator	0:bb348c97df44	1820	\return 0 Function succeeded.
lypinator	0:bb348c97df44	1821	\return 1 Function failed.
lypinator	0:bb348c97df44	1822	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
lypinator	0:bb348c97df44	1823	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
lypinator	0:bb348c97df44	1824	must contain a vendor-specific implementation of this function.
lypinator	0:bb348c97df44	1825	*/
lypinator	0:bb348c97df44	1826	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
lypinator	0:bb348c97df44	1827	{
lypinator	0:bb348c97df44	1828	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
lypinator	0:bb348c97df44	1829	{
lypinator	0:bb348c97df44	1830	return (1UL); /* Reload value impossible */
lypinator	0:bb348c97df44	1831	}
lypinator	0:bb348c97df44	1832
lypinator	0:bb348c97df44	1833	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
lypinator	0:bb348c97df44	1834	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
lypinator	0:bb348c97df44	1835	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
lypinator	0:bb348c97df44	1836	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
lypinator	0:bb348c97df44	1837	SysTick_CTRL_TICKINT_Msk \|
lypinator	0:bb348c97df44	1838	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
lypinator	0:bb348c97df44	1839	return (0UL); /* Function successful */
lypinator	0:bb348c97df44	1840	}
lypinator	0:bb348c97df44	1841
lypinator	0:bb348c97df44	1842	#endif
lypinator	0:bb348c97df44	1843
lypinator	0:bb348c97df44	1844	/@} end of CMSIS_Core_SysTickFunctions /
lypinator	0:bb348c97df44	1845
lypinator	0:bb348c97df44	1846
lypinator	0:bb348c97df44	1847
lypinator	0:bb348c97df44	1848	/* ##################################### Debug In/Output function ########################################### */
lypinator	0:bb348c97df44	1849	/**
lypinator	0:bb348c97df44	1850	\ingroup CMSIS_Core_FunctionInterface
lypinator	0:bb348c97df44	1851	\defgroup CMSIS_core_DebugFunctions ITM Functions
lypinator	0:bb348c97df44	1852	\brief Functions that access the ITM debug interface.
lypinator	0:bb348c97df44	1853	@{
lypinator	0:bb348c97df44	1854	*/
lypinator	0:bb348c97df44	1855
lypinator	0:bb348c97df44	1856	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
lypinator	0:bb348c97df44	1857	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
lypinator	0:bb348c97df44	1858
lypinator	0:bb348c97df44	1859
lypinator	0:bb348c97df44	1860	/**
lypinator	0:bb348c97df44	1861	\brief ITM Send Character
lypinator	0:bb348c97df44	1862	\details Transmits a character via the ITM channel 0, and
lypinator	0:bb348c97df44	1863	\li Just returns when no debugger is connected that has booked the output.
lypinator	0:bb348c97df44	1864	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
lypinator	0:bb348c97df44	1865	\param [in] ch Character to transmit.
lypinator	0:bb348c97df44	1866	\returns Character to transmit.
lypinator	0:bb348c97df44	1867	*/
lypinator	0:bb348c97df44	1868	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
lypinator	0:bb348c97df44	1869	{
lypinator	0:bb348c97df44	1870	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
lypinator	0:bb348c97df44	1871	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
lypinator	0:bb348c97df44	1872	{
lypinator	0:bb348c97df44	1873	while (ITM->PORT[0U].u32 == 0UL)
lypinator	0:bb348c97df44	1874	{
lypinator	0:bb348c97df44	1875	__NOP();
lypinator	0:bb348c97df44	1876	}
lypinator	0:bb348c97df44	1877	ITM->PORT[0U].u8 = (uint8_t)ch;
lypinator	0:bb348c97df44	1878	}
lypinator	0:bb348c97df44	1879	return (ch);
lypinator	0:bb348c97df44	1880	}
lypinator	0:bb348c97df44	1881
lypinator	0:bb348c97df44	1882
lypinator	0:bb348c97df44	1883	/**
lypinator	0:bb348c97df44	1884	\brief ITM Receive Character
lypinator	0:bb348c97df44	1885	\details Inputs a character via the external variable \ref ITM_RxBuffer.
lypinator	0:bb348c97df44	1886	\return Received character.
lypinator	0:bb348c97df44	1887	\return -1 No character pending.
lypinator	0:bb348c97df44	1888	*/
lypinator	0:bb348c97df44	1889	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
lypinator	0:bb348c97df44	1890	{
lypinator	0:bb348c97df44	1891	int32_t ch = -1; /* no character available */
lypinator	0:bb348c97df44	1892
lypinator	0:bb348c97df44	1893	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
lypinator	0:bb348c97df44	1894	{
lypinator	0:bb348c97df44	1895	ch = ITM_RxBuffer;
lypinator	0:bb348c97df44	1896	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
lypinator	0:bb348c97df44	1897	}
lypinator	0:bb348c97df44	1898
lypinator	0:bb348c97df44	1899	return (ch);
lypinator	0:bb348c97df44	1900	}
lypinator	0:bb348c97df44	1901
lypinator	0:bb348c97df44	1902
lypinator	0:bb348c97df44	1903	/**
lypinator	0:bb348c97df44	1904	\brief ITM Check Character
lypinator	0:bb348c97df44	1905	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
lypinator	0:bb348c97df44	1906	\return 0 No character available.
lypinator	0:bb348c97df44	1907	\return 1 Character available.
lypinator	0:bb348c97df44	1908	*/
lypinator	0:bb348c97df44	1909	__STATIC_INLINE int32_t ITM_CheckChar (void)
lypinator	0:bb348c97df44	1910	{
lypinator	0:bb348c97df44	1911
lypinator	0:bb348c97df44	1912	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
lypinator	0:bb348c97df44	1913	{
lypinator	0:bb348c97df44	1914	return (0); /* no character available */
lypinator	0:bb348c97df44	1915	}
lypinator	0:bb348c97df44	1916	else
lypinator	0:bb348c97df44	1917	{
lypinator	0:bb348c97df44	1918	return (1); /* character available */
lypinator	0:bb348c97df44	1919	}
lypinator	0:bb348c97df44	1920	}
lypinator	0:bb348c97df44	1921
lypinator	0:bb348c97df44	1922	/@} end of CMSIS_core_DebugFunctions /
lypinator	0:bb348c97df44	1923
lypinator	0:bb348c97df44	1924
lypinator	0:bb348c97df44	1925
lypinator	0:bb348c97df44	1926
lypinator	0:bb348c97df44	1927	#ifdef __cplusplus
lypinator	0:bb348c97df44	1928	}
lypinator	0:bb348c97df44	1929	#endif
lypinator	0:bb348c97df44	1930
lypinator	0:bb348c97df44	1931	#endif /* __CORE_CM3_H_DEPENDANT */
lypinator	0:bb348c97df44	1932
lypinator	0:bb348c97df44	1933	#endif /* __CMSIS_GENERIC */

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Type:	Program
Created:	16 Sep 2020
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cm3.h@0:bb348c97df44, 2020-09-16 (annotated)

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