Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cm23.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**************************************************************************//**
lypinator 0:bb348c97df44 2 * @file core_cm23.h
lypinator 0:bb348c97df44 3 * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
lypinator 0:bb348c97df44 4 * @version V5.0.4
lypinator 0:bb348c97df44 5 * @date 10. January 2018
lypinator 0:bb348c97df44 6 ******************************************************************************/
lypinator 0:bb348c97df44 7 /*
lypinator 0:bb348c97df44 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * SPDX-License-Identifier: Apache-2.0
lypinator 0:bb348c97df44 11 *
lypinator 0:bb348c97df44 12 * Licensed under the Apache License, Version 2.0 (the License); you may
lypinator 0:bb348c97df44 13 * not use this file except in compliance with the License.
lypinator 0:bb348c97df44 14 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 15 *
lypinator 0:bb348c97df44 16 * www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 17 *
lypinator 0:bb348c97df44 18 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
lypinator 0:bb348c97df44 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 21 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 22 * limitations under the License.
lypinator 0:bb348c97df44 23 */
lypinator 0:bb348c97df44 24
lypinator 0:bb348c97df44 25 #if defined ( __ICCARM__ )
lypinator 0:bb348c97df44 26 #pragma system_include /* treat file as system include file for MISRA check */
lypinator 0:bb348c97df44 27 #elif defined (__clang__)
lypinator 0:bb348c97df44 28 #pragma clang system_header /* treat file as system include file */
lypinator 0:bb348c97df44 29 #endif
lypinator 0:bb348c97df44 30
lypinator 0:bb348c97df44 31 #ifndef __CORE_CM23_H_GENERIC
lypinator 0:bb348c97df44 32 #define __CORE_CM23_H_GENERIC
lypinator 0:bb348c97df44 33
lypinator 0:bb348c97df44 34 #include <stdint.h>
lypinator 0:bb348c97df44 35
lypinator 0:bb348c97df44 36 #ifdef __cplusplus
lypinator 0:bb348c97df44 37 extern "C" {
lypinator 0:bb348c97df44 38 #endif
lypinator 0:bb348c97df44 39
lypinator 0:bb348c97df44 40 /**
lypinator 0:bb348c97df44 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
lypinator 0:bb348c97df44 42 CMSIS violates the following MISRA-C:2004 rules:
lypinator 0:bb348c97df44 43
lypinator 0:bb348c97df44 44 \li Required Rule 8.5, object/function definition in header file.<br>
lypinator 0:bb348c97df44 45 Function definitions in header files are used to allow 'inlining'.
lypinator 0:bb348c97df44 46
lypinator 0:bb348c97df44 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
lypinator 0:bb348c97df44 48 Unions are used for effective representation of core registers.
lypinator 0:bb348c97df44 49
lypinator 0:bb348c97df44 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
lypinator 0:bb348c97df44 51 Function-like macros are used to allow more efficient code.
lypinator 0:bb348c97df44 52 */
lypinator 0:bb348c97df44 53
lypinator 0:bb348c97df44 54
lypinator 0:bb348c97df44 55 /*******************************************************************************
lypinator 0:bb348c97df44 56 * CMSIS definitions
lypinator 0:bb348c97df44 57 ******************************************************************************/
lypinator 0:bb348c97df44 58 /**
lypinator 0:bb348c97df44 59 \ingroup Cortex_M23
lypinator 0:bb348c97df44 60 @{
lypinator 0:bb348c97df44 61 */
lypinator 0:bb348c97df44 62
lypinator 0:bb348c97df44 63 #include "cmsis_version.h"
lypinator 0:bb348c97df44 64
lypinator 0:bb348c97df44 65 /* CMSIS definitions */
lypinator 0:bb348c97df44 66 #define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
lypinator 0:bb348c97df44 67 #define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
lypinator 0:bb348c97df44 68 #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
lypinator 0:bb348c97df44 69 __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
lypinator 0:bb348c97df44 70
lypinator 0:bb348c97df44 71 #define __CORTEX_M (23U) /*!< Cortex-M Core */
lypinator 0:bb348c97df44 72
lypinator 0:bb348c97df44 73 /** __FPU_USED indicates whether an FPU is used or not.
lypinator 0:bb348c97df44 74 This core does not support an FPU at all
lypinator 0:bb348c97df44 75 */
lypinator 0:bb348c97df44 76 #define __FPU_USED 0U
lypinator 0:bb348c97df44 77
lypinator 0:bb348c97df44 78 #if defined ( __CC_ARM )
lypinator 0:bb348c97df44 79 #if defined __TARGET_FPU_VFP
lypinator 0:bb348c97df44 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 81 #endif
lypinator 0:bb348c97df44 82
lypinator 0:bb348c97df44 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
lypinator 0:bb348c97df44 84 #if defined __ARM_PCS_VFP
lypinator 0:bb348c97df44 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 86 #endif
lypinator 0:bb348c97df44 87
lypinator 0:bb348c97df44 88 #elif defined ( __GNUC__ )
lypinator 0:bb348c97df44 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
lypinator 0:bb348c97df44 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 91 #endif
lypinator 0:bb348c97df44 92
lypinator 0:bb348c97df44 93 #elif defined ( __ICCARM__ )
lypinator 0:bb348c97df44 94 #if defined __ARMVFP__
lypinator 0:bb348c97df44 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 96 #endif
lypinator 0:bb348c97df44 97
lypinator 0:bb348c97df44 98 #elif defined ( __TI_ARM__ )
lypinator 0:bb348c97df44 99 #if defined __TI_VFP_SUPPORT__
lypinator 0:bb348c97df44 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 101 #endif
lypinator 0:bb348c97df44 102
lypinator 0:bb348c97df44 103 #elif defined ( __TASKING__ )
lypinator 0:bb348c97df44 104 #if defined __FPU_VFP__
lypinator 0:bb348c97df44 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 106 #endif
lypinator 0:bb348c97df44 107
lypinator 0:bb348c97df44 108 #elif defined ( __CSMC__ )
lypinator 0:bb348c97df44 109 #if ( __CSMC__ & 0x400U)
lypinator 0:bb348c97df44 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 111 #endif
lypinator 0:bb348c97df44 112
lypinator 0:bb348c97df44 113 #endif
lypinator 0:bb348c97df44 114
lypinator 0:bb348c97df44 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
lypinator 0:bb348c97df44 116
lypinator 0:bb348c97df44 117
lypinator 0:bb348c97df44 118 #ifdef __cplusplus
lypinator 0:bb348c97df44 119 }
lypinator 0:bb348c97df44 120 #endif
lypinator 0:bb348c97df44 121
lypinator 0:bb348c97df44 122 #endif /* __CORE_CM23_H_GENERIC */
lypinator 0:bb348c97df44 123
lypinator 0:bb348c97df44 124 #ifndef __CMSIS_GENERIC
lypinator 0:bb348c97df44 125
lypinator 0:bb348c97df44 126 #ifndef __CORE_CM23_H_DEPENDANT
lypinator 0:bb348c97df44 127 #define __CORE_CM23_H_DEPENDANT
lypinator 0:bb348c97df44 128
lypinator 0:bb348c97df44 129 #ifdef __cplusplus
lypinator 0:bb348c97df44 130 extern "C" {
lypinator 0:bb348c97df44 131 #endif
lypinator 0:bb348c97df44 132
lypinator 0:bb348c97df44 133 /* check device defines and use defaults */
lypinator 0:bb348c97df44 134 #if defined __CHECK_DEVICE_DEFINES
lypinator 0:bb348c97df44 135 #ifndef __CM23_REV
lypinator 0:bb348c97df44 136 #define __CM23_REV 0x0000U
lypinator 0:bb348c97df44 137 #warning "__CM23_REV not defined in device header file; using default!"
lypinator 0:bb348c97df44 138 #endif
lypinator 0:bb348c97df44 139
lypinator 0:bb348c97df44 140 #ifndef __FPU_PRESENT
lypinator 0:bb348c97df44 141 #define __FPU_PRESENT 0U
lypinator 0:bb348c97df44 142 #warning "__FPU_PRESENT not defined in device header file; using default!"
lypinator 0:bb348c97df44 143 #endif
lypinator 0:bb348c97df44 144
lypinator 0:bb348c97df44 145 #ifndef __MPU_PRESENT
lypinator 0:bb348c97df44 146 #define __MPU_PRESENT 0U
lypinator 0:bb348c97df44 147 #warning "__MPU_PRESENT not defined in device header file; using default!"
lypinator 0:bb348c97df44 148 #endif
lypinator 0:bb348c97df44 149
lypinator 0:bb348c97df44 150 #ifndef __SAUREGION_PRESENT
lypinator 0:bb348c97df44 151 #define __SAUREGION_PRESENT 0U
lypinator 0:bb348c97df44 152 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
lypinator 0:bb348c97df44 153 #endif
lypinator 0:bb348c97df44 154
lypinator 0:bb348c97df44 155 #ifndef __VTOR_PRESENT
lypinator 0:bb348c97df44 156 #define __VTOR_PRESENT 0U
lypinator 0:bb348c97df44 157 #warning "__VTOR_PRESENT not defined in device header file; using default!"
lypinator 0:bb348c97df44 158 #endif
lypinator 0:bb348c97df44 159
lypinator 0:bb348c97df44 160 #ifndef __NVIC_PRIO_BITS
lypinator 0:bb348c97df44 161 #define __NVIC_PRIO_BITS 2U
lypinator 0:bb348c97df44 162 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
lypinator 0:bb348c97df44 163 #endif
lypinator 0:bb348c97df44 164
lypinator 0:bb348c97df44 165 #ifndef __Vendor_SysTickConfig
lypinator 0:bb348c97df44 166 #define __Vendor_SysTickConfig 0U
lypinator 0:bb348c97df44 167 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
lypinator 0:bb348c97df44 168 #endif
lypinator 0:bb348c97df44 169
lypinator 0:bb348c97df44 170 #ifndef __ETM_PRESENT
lypinator 0:bb348c97df44 171 #define __ETM_PRESENT 0U
lypinator 0:bb348c97df44 172 #warning "__ETM_PRESENT not defined in device header file; using default!"
lypinator 0:bb348c97df44 173 #endif
lypinator 0:bb348c97df44 174
lypinator 0:bb348c97df44 175 #ifndef __MTB_PRESENT
lypinator 0:bb348c97df44 176 #define __MTB_PRESENT 0U
lypinator 0:bb348c97df44 177 #warning "__MTB_PRESENT not defined in device header file; using default!"
lypinator 0:bb348c97df44 178 #endif
lypinator 0:bb348c97df44 179
lypinator 0:bb348c97df44 180 #endif
lypinator 0:bb348c97df44 181
lypinator 0:bb348c97df44 182 /* IO definitions (access restrictions to peripheral registers) */
lypinator 0:bb348c97df44 183 /**
lypinator 0:bb348c97df44 184 \defgroup CMSIS_glob_defs CMSIS Global Defines
lypinator 0:bb348c97df44 185
lypinator 0:bb348c97df44 186 <strong>IO Type Qualifiers</strong> are used
lypinator 0:bb348c97df44 187 \li to specify the access to peripheral variables.
lypinator 0:bb348c97df44 188 \li for automatic generation of peripheral register debug information.
lypinator 0:bb348c97df44 189 */
lypinator 0:bb348c97df44 190 #ifdef __cplusplus
lypinator 0:bb348c97df44 191 #define __I volatile /*!< Defines 'read only' permissions */
lypinator 0:bb348c97df44 192 #else
lypinator 0:bb348c97df44 193 #define __I volatile const /*!< Defines 'read only' permissions */
lypinator 0:bb348c97df44 194 #endif
lypinator 0:bb348c97df44 195 #define __O volatile /*!< Defines 'write only' permissions */
lypinator 0:bb348c97df44 196 #define __IO volatile /*!< Defines 'read / write' permissions */
lypinator 0:bb348c97df44 197
lypinator 0:bb348c97df44 198 /* following defines should be used for structure members */
lypinator 0:bb348c97df44 199 #define __IM volatile const /*! Defines 'read only' structure member permissions */
lypinator 0:bb348c97df44 200 #define __OM volatile /*! Defines 'write only' structure member permissions */
lypinator 0:bb348c97df44 201 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
lypinator 0:bb348c97df44 202
lypinator 0:bb348c97df44 203 /*@} end of group Cortex_M23 */
lypinator 0:bb348c97df44 204
lypinator 0:bb348c97df44 205
lypinator 0:bb348c97df44 206
lypinator 0:bb348c97df44 207 /*******************************************************************************
lypinator 0:bb348c97df44 208 * Register Abstraction
lypinator 0:bb348c97df44 209 Core Register contain:
lypinator 0:bb348c97df44 210 - Core Register
lypinator 0:bb348c97df44 211 - Core NVIC Register
lypinator 0:bb348c97df44 212 - Core SCB Register
lypinator 0:bb348c97df44 213 - Core SysTick Register
lypinator 0:bb348c97df44 214 - Core Debug Register
lypinator 0:bb348c97df44 215 - Core MPU Register
lypinator 0:bb348c97df44 216 - Core SAU Register
lypinator 0:bb348c97df44 217 ******************************************************************************/
lypinator 0:bb348c97df44 218 /**
lypinator 0:bb348c97df44 219 \defgroup CMSIS_core_register Defines and Type Definitions
lypinator 0:bb348c97df44 220 \brief Type definitions and defines for Cortex-M processor based devices.
lypinator 0:bb348c97df44 221 */
lypinator 0:bb348c97df44 222
lypinator 0:bb348c97df44 223 /**
lypinator 0:bb348c97df44 224 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 225 \defgroup CMSIS_CORE Status and Control Registers
lypinator 0:bb348c97df44 226 \brief Core Register type definitions.
lypinator 0:bb348c97df44 227 @{
lypinator 0:bb348c97df44 228 */
lypinator 0:bb348c97df44 229
lypinator 0:bb348c97df44 230 /**
lypinator 0:bb348c97df44 231 \brief Union type to access the Application Program Status Register (APSR).
lypinator 0:bb348c97df44 232 */
lypinator 0:bb348c97df44 233 typedef union
lypinator 0:bb348c97df44 234 {
lypinator 0:bb348c97df44 235 struct
lypinator 0:bb348c97df44 236 {
lypinator 0:bb348c97df44 237 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
lypinator 0:bb348c97df44 238 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
lypinator 0:bb348c97df44 239 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
lypinator 0:bb348c97df44 240 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
lypinator 0:bb348c97df44 241 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
lypinator 0:bb348c97df44 242 } b; /*!< Structure used for bit access */
lypinator 0:bb348c97df44 243 uint32_t w; /*!< Type used for word access */
lypinator 0:bb348c97df44 244 } APSR_Type;
lypinator 0:bb348c97df44 245
lypinator 0:bb348c97df44 246 /* APSR Register Definitions */
lypinator 0:bb348c97df44 247 #define APSR_N_Pos 31U /*!< APSR: N Position */
lypinator 0:bb348c97df44 248 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
lypinator 0:bb348c97df44 249
lypinator 0:bb348c97df44 250 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
lypinator 0:bb348c97df44 251 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
lypinator 0:bb348c97df44 252
lypinator 0:bb348c97df44 253 #define APSR_C_Pos 29U /*!< APSR: C Position */
lypinator 0:bb348c97df44 254 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
lypinator 0:bb348c97df44 255
lypinator 0:bb348c97df44 256 #define APSR_V_Pos 28U /*!< APSR: V Position */
lypinator 0:bb348c97df44 257 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
lypinator 0:bb348c97df44 258
lypinator 0:bb348c97df44 259
lypinator 0:bb348c97df44 260 /**
lypinator 0:bb348c97df44 261 \brief Union type to access the Interrupt Program Status Register (IPSR).
lypinator 0:bb348c97df44 262 */
lypinator 0:bb348c97df44 263 typedef union
lypinator 0:bb348c97df44 264 {
lypinator 0:bb348c97df44 265 struct
lypinator 0:bb348c97df44 266 {
lypinator 0:bb348c97df44 267 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
lypinator 0:bb348c97df44 268 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
lypinator 0:bb348c97df44 269 } b; /*!< Structure used for bit access */
lypinator 0:bb348c97df44 270 uint32_t w; /*!< Type used for word access */
lypinator 0:bb348c97df44 271 } IPSR_Type;
lypinator 0:bb348c97df44 272
lypinator 0:bb348c97df44 273 /* IPSR Register Definitions */
lypinator 0:bb348c97df44 274 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
lypinator 0:bb348c97df44 275 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
lypinator 0:bb348c97df44 276
lypinator 0:bb348c97df44 277
lypinator 0:bb348c97df44 278 /**
lypinator 0:bb348c97df44 279 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
lypinator 0:bb348c97df44 280 */
lypinator 0:bb348c97df44 281 typedef union
lypinator 0:bb348c97df44 282 {
lypinator 0:bb348c97df44 283 struct
lypinator 0:bb348c97df44 284 {
lypinator 0:bb348c97df44 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
lypinator 0:bb348c97df44 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
lypinator 0:bb348c97df44 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
lypinator 0:bb348c97df44 288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
lypinator 0:bb348c97df44 289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
lypinator 0:bb348c97df44 290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
lypinator 0:bb348c97df44 291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
lypinator 0:bb348c97df44 292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
lypinator 0:bb348c97df44 293 } b; /*!< Structure used for bit access */
lypinator 0:bb348c97df44 294 uint32_t w; /*!< Type used for word access */
lypinator 0:bb348c97df44 295 } xPSR_Type;
lypinator 0:bb348c97df44 296
lypinator 0:bb348c97df44 297 /* xPSR Register Definitions */
lypinator 0:bb348c97df44 298 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
lypinator 0:bb348c97df44 299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
lypinator 0:bb348c97df44 300
lypinator 0:bb348c97df44 301 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
lypinator 0:bb348c97df44 302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
lypinator 0:bb348c97df44 303
lypinator 0:bb348c97df44 304 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
lypinator 0:bb348c97df44 305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
lypinator 0:bb348c97df44 306
lypinator 0:bb348c97df44 307 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
lypinator 0:bb348c97df44 308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
lypinator 0:bb348c97df44 309
lypinator 0:bb348c97df44 310 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
lypinator 0:bb348c97df44 311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
lypinator 0:bb348c97df44 312
lypinator 0:bb348c97df44 313 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
lypinator 0:bb348c97df44 314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
lypinator 0:bb348c97df44 315
lypinator 0:bb348c97df44 316
lypinator 0:bb348c97df44 317 /**
lypinator 0:bb348c97df44 318 \brief Union type to access the Control Registers (CONTROL).
lypinator 0:bb348c97df44 319 */
lypinator 0:bb348c97df44 320 typedef union
lypinator 0:bb348c97df44 321 {
lypinator 0:bb348c97df44 322 struct
lypinator 0:bb348c97df44 323 {
lypinator 0:bb348c97df44 324 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
lypinator 0:bb348c97df44 325 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
lypinator 0:bb348c97df44 326 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
lypinator 0:bb348c97df44 327 } b; /*!< Structure used for bit access */
lypinator 0:bb348c97df44 328 uint32_t w; /*!< Type used for word access */
lypinator 0:bb348c97df44 329 } CONTROL_Type;
lypinator 0:bb348c97df44 330
lypinator 0:bb348c97df44 331 /* CONTROL Register Definitions */
lypinator 0:bb348c97df44 332 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
lypinator 0:bb348c97df44 333 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
lypinator 0:bb348c97df44 334
lypinator 0:bb348c97df44 335 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
lypinator 0:bb348c97df44 336 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
lypinator 0:bb348c97df44 337
lypinator 0:bb348c97df44 338 /*@} end of group CMSIS_CORE */
lypinator 0:bb348c97df44 339
lypinator 0:bb348c97df44 340
lypinator 0:bb348c97df44 341 /**
lypinator 0:bb348c97df44 342 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 343 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
lypinator 0:bb348c97df44 344 \brief Type definitions for the NVIC Registers
lypinator 0:bb348c97df44 345 @{
lypinator 0:bb348c97df44 346 */
lypinator 0:bb348c97df44 347
lypinator 0:bb348c97df44 348 /**
lypinator 0:bb348c97df44 349 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
lypinator 0:bb348c97df44 350 */
lypinator 0:bb348c97df44 351 typedef struct
lypinator 0:bb348c97df44 352 {
lypinator 0:bb348c97df44 353 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
lypinator 0:bb348c97df44 354 uint32_t RESERVED0[16U];
lypinator 0:bb348c97df44 355 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
lypinator 0:bb348c97df44 356 uint32_t RSERVED1[16U];
lypinator 0:bb348c97df44 357 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
lypinator 0:bb348c97df44 358 uint32_t RESERVED2[16U];
lypinator 0:bb348c97df44 359 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
lypinator 0:bb348c97df44 360 uint32_t RESERVED3[16U];
lypinator 0:bb348c97df44 361 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
lypinator 0:bb348c97df44 362 uint32_t RESERVED4[16U];
lypinator 0:bb348c97df44 363 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
lypinator 0:bb348c97df44 364 uint32_t RESERVED5[16U];
lypinator 0:bb348c97df44 365 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
lypinator 0:bb348c97df44 366 } NVIC_Type;
lypinator 0:bb348c97df44 367
lypinator 0:bb348c97df44 368 /*@} end of group CMSIS_NVIC */
lypinator 0:bb348c97df44 369
lypinator 0:bb348c97df44 370
lypinator 0:bb348c97df44 371 /**
lypinator 0:bb348c97df44 372 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 373 \defgroup CMSIS_SCB System Control Block (SCB)
lypinator 0:bb348c97df44 374 \brief Type definitions for the System Control Block Registers
lypinator 0:bb348c97df44 375 @{
lypinator 0:bb348c97df44 376 */
lypinator 0:bb348c97df44 377
lypinator 0:bb348c97df44 378 /**
lypinator 0:bb348c97df44 379 \brief Structure type to access the System Control Block (SCB).
lypinator 0:bb348c97df44 380 */
lypinator 0:bb348c97df44 381 typedef struct
lypinator 0:bb348c97df44 382 {
lypinator 0:bb348c97df44 383 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
lypinator 0:bb348c97df44 384 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
lypinator 0:bb348c97df44 385 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
lypinator 0:bb348c97df44 386 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
lypinator 0:bb348c97df44 387 #else
lypinator 0:bb348c97df44 388 uint32_t RESERVED0;
lypinator 0:bb348c97df44 389 #endif
lypinator 0:bb348c97df44 390 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
lypinator 0:bb348c97df44 391 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
lypinator 0:bb348c97df44 392 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
lypinator 0:bb348c97df44 393 uint32_t RESERVED1;
lypinator 0:bb348c97df44 394 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
lypinator 0:bb348c97df44 395 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
lypinator 0:bb348c97df44 396 } SCB_Type;
lypinator 0:bb348c97df44 397
lypinator 0:bb348c97df44 398 /* SCB CPUID Register Definitions */
lypinator 0:bb348c97df44 399 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
lypinator 0:bb348c97df44 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
lypinator 0:bb348c97df44 401
lypinator 0:bb348c97df44 402 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
lypinator 0:bb348c97df44 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
lypinator 0:bb348c97df44 404
lypinator 0:bb348c97df44 405 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
lypinator 0:bb348c97df44 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
lypinator 0:bb348c97df44 407
lypinator 0:bb348c97df44 408 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
lypinator 0:bb348c97df44 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
lypinator 0:bb348c97df44 410
lypinator 0:bb348c97df44 411 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
lypinator 0:bb348c97df44 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
lypinator 0:bb348c97df44 413
lypinator 0:bb348c97df44 414 /* SCB Interrupt Control State Register Definitions */
lypinator 0:bb348c97df44 415 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
lypinator 0:bb348c97df44 416 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
lypinator 0:bb348c97df44 417
lypinator 0:bb348c97df44 418 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
lypinator 0:bb348c97df44 419 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
lypinator 0:bb348c97df44 420
lypinator 0:bb348c97df44 421 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
lypinator 0:bb348c97df44 422 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
lypinator 0:bb348c97df44 423
lypinator 0:bb348c97df44 424 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
lypinator 0:bb348c97df44 425 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
lypinator 0:bb348c97df44 426
lypinator 0:bb348c97df44 427 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
lypinator 0:bb348c97df44 428 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
lypinator 0:bb348c97df44 429
lypinator 0:bb348c97df44 430 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
lypinator 0:bb348c97df44 431 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
lypinator 0:bb348c97df44 432
lypinator 0:bb348c97df44 433 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
lypinator 0:bb348c97df44 434 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
lypinator 0:bb348c97df44 435
lypinator 0:bb348c97df44 436 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
lypinator 0:bb348c97df44 437 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
lypinator 0:bb348c97df44 438
lypinator 0:bb348c97df44 439 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
lypinator 0:bb348c97df44 440 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
lypinator 0:bb348c97df44 441
lypinator 0:bb348c97df44 442 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
lypinator 0:bb348c97df44 443 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
lypinator 0:bb348c97df44 444
lypinator 0:bb348c97df44 445 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
lypinator 0:bb348c97df44 446 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
lypinator 0:bb348c97df44 447
lypinator 0:bb348c97df44 448 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
lypinator 0:bb348c97df44 449 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
lypinator 0:bb348c97df44 450
lypinator 0:bb348c97df44 451 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
lypinator 0:bb348c97df44 452 /* SCB Vector Table Offset Register Definitions */
lypinator 0:bb348c97df44 453 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
lypinator 0:bb348c97df44 454 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
lypinator 0:bb348c97df44 455 #endif
lypinator 0:bb348c97df44 456
lypinator 0:bb348c97df44 457 /* SCB Application Interrupt and Reset Control Register Definitions */
lypinator 0:bb348c97df44 458 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
lypinator 0:bb348c97df44 459 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
lypinator 0:bb348c97df44 460
lypinator 0:bb348c97df44 461 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
lypinator 0:bb348c97df44 462 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
lypinator 0:bb348c97df44 463
lypinator 0:bb348c97df44 464 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
lypinator 0:bb348c97df44 465 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
lypinator 0:bb348c97df44 466
lypinator 0:bb348c97df44 467 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
lypinator 0:bb348c97df44 468 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
lypinator 0:bb348c97df44 469
lypinator 0:bb348c97df44 470 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
lypinator 0:bb348c97df44 471 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
lypinator 0:bb348c97df44 472
lypinator 0:bb348c97df44 473 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
lypinator 0:bb348c97df44 474 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
lypinator 0:bb348c97df44 475
lypinator 0:bb348c97df44 476 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
lypinator 0:bb348c97df44 477 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
lypinator 0:bb348c97df44 478
lypinator 0:bb348c97df44 479 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
lypinator 0:bb348c97df44 480 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
lypinator 0:bb348c97df44 481
lypinator 0:bb348c97df44 482 /* SCB System Control Register Definitions */
lypinator 0:bb348c97df44 483 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
lypinator 0:bb348c97df44 484 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
lypinator 0:bb348c97df44 485
lypinator 0:bb348c97df44 486 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
lypinator 0:bb348c97df44 487 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
lypinator 0:bb348c97df44 488
lypinator 0:bb348c97df44 489 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
lypinator 0:bb348c97df44 490 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
lypinator 0:bb348c97df44 491
lypinator 0:bb348c97df44 492 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
lypinator 0:bb348c97df44 493 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
lypinator 0:bb348c97df44 494
lypinator 0:bb348c97df44 495 /* SCB Configuration Control Register Definitions */
lypinator 0:bb348c97df44 496 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
lypinator 0:bb348c97df44 497 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
lypinator 0:bb348c97df44 498
lypinator 0:bb348c97df44 499 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
lypinator 0:bb348c97df44 500 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
lypinator 0:bb348c97df44 501
lypinator 0:bb348c97df44 502 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
lypinator 0:bb348c97df44 503 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
lypinator 0:bb348c97df44 504
lypinator 0:bb348c97df44 505 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
lypinator 0:bb348c97df44 506 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
lypinator 0:bb348c97df44 507
lypinator 0:bb348c97df44 508 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
lypinator 0:bb348c97df44 509 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
lypinator 0:bb348c97df44 510
lypinator 0:bb348c97df44 511 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
lypinator 0:bb348c97df44 512 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
lypinator 0:bb348c97df44 513
lypinator 0:bb348c97df44 514 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
lypinator 0:bb348c97df44 515 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
lypinator 0:bb348c97df44 516
lypinator 0:bb348c97df44 517 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
lypinator 0:bb348c97df44 518 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
lypinator 0:bb348c97df44 519
lypinator 0:bb348c97df44 520 /* SCB System Handler Control and State Register Definitions */
lypinator 0:bb348c97df44 521 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
lypinator 0:bb348c97df44 522 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
lypinator 0:bb348c97df44 523
lypinator 0:bb348c97df44 524 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
lypinator 0:bb348c97df44 525 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
lypinator 0:bb348c97df44 526
lypinator 0:bb348c97df44 527 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
lypinator 0:bb348c97df44 528 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
lypinator 0:bb348c97df44 529
lypinator 0:bb348c97df44 530 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
lypinator 0:bb348c97df44 531 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
lypinator 0:bb348c97df44 532
lypinator 0:bb348c97df44 533 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
lypinator 0:bb348c97df44 534 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
lypinator 0:bb348c97df44 535
lypinator 0:bb348c97df44 536 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
lypinator 0:bb348c97df44 537 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
lypinator 0:bb348c97df44 538
lypinator 0:bb348c97df44 539 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
lypinator 0:bb348c97df44 540 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
lypinator 0:bb348c97df44 541
lypinator 0:bb348c97df44 542 /*@} end of group CMSIS_SCB */
lypinator 0:bb348c97df44 543
lypinator 0:bb348c97df44 544
lypinator 0:bb348c97df44 545 /**
lypinator 0:bb348c97df44 546 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 547 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
lypinator 0:bb348c97df44 548 \brief Type definitions for the System Timer Registers.
lypinator 0:bb348c97df44 549 @{
lypinator 0:bb348c97df44 550 */
lypinator 0:bb348c97df44 551
lypinator 0:bb348c97df44 552 /**
lypinator 0:bb348c97df44 553 \brief Structure type to access the System Timer (SysTick).
lypinator 0:bb348c97df44 554 */
lypinator 0:bb348c97df44 555 typedef struct
lypinator 0:bb348c97df44 556 {
lypinator 0:bb348c97df44 557 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
lypinator 0:bb348c97df44 558 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
lypinator 0:bb348c97df44 559 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
lypinator 0:bb348c97df44 560 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
lypinator 0:bb348c97df44 561 } SysTick_Type;
lypinator 0:bb348c97df44 562
lypinator 0:bb348c97df44 563 /* SysTick Control / Status Register Definitions */
lypinator 0:bb348c97df44 564 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
lypinator 0:bb348c97df44 565 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
lypinator 0:bb348c97df44 566
lypinator 0:bb348c97df44 567 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
lypinator 0:bb348c97df44 568 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
lypinator 0:bb348c97df44 569
lypinator 0:bb348c97df44 570 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
lypinator 0:bb348c97df44 571 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
lypinator 0:bb348c97df44 572
lypinator 0:bb348c97df44 573 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
lypinator 0:bb348c97df44 574 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
lypinator 0:bb348c97df44 575
lypinator 0:bb348c97df44 576 /* SysTick Reload Register Definitions */
lypinator 0:bb348c97df44 577 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
lypinator 0:bb348c97df44 578 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
lypinator 0:bb348c97df44 579
lypinator 0:bb348c97df44 580 /* SysTick Current Register Definitions */
lypinator 0:bb348c97df44 581 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
lypinator 0:bb348c97df44 582 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
lypinator 0:bb348c97df44 583
lypinator 0:bb348c97df44 584 /* SysTick Calibration Register Definitions */
lypinator 0:bb348c97df44 585 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
lypinator 0:bb348c97df44 586 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
lypinator 0:bb348c97df44 587
lypinator 0:bb348c97df44 588 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
lypinator 0:bb348c97df44 589 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
lypinator 0:bb348c97df44 590
lypinator 0:bb348c97df44 591 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
lypinator 0:bb348c97df44 592 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
lypinator 0:bb348c97df44 593
lypinator 0:bb348c97df44 594 /*@} end of group CMSIS_SysTick */
lypinator 0:bb348c97df44 595
lypinator 0:bb348c97df44 596
lypinator 0:bb348c97df44 597 /**
lypinator 0:bb348c97df44 598 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 599 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
lypinator 0:bb348c97df44 600 \brief Type definitions for the Data Watchpoint and Trace (DWT)
lypinator 0:bb348c97df44 601 @{
lypinator 0:bb348c97df44 602 */
lypinator 0:bb348c97df44 603
lypinator 0:bb348c97df44 604 /**
lypinator 0:bb348c97df44 605 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
lypinator 0:bb348c97df44 606 */
lypinator 0:bb348c97df44 607 typedef struct
lypinator 0:bb348c97df44 608 {
lypinator 0:bb348c97df44 609 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
lypinator 0:bb348c97df44 610 uint32_t RESERVED0[6U];
lypinator 0:bb348c97df44 611 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
lypinator 0:bb348c97df44 612 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
lypinator 0:bb348c97df44 613 uint32_t RESERVED1[1U];
lypinator 0:bb348c97df44 614 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
lypinator 0:bb348c97df44 615 uint32_t RESERVED2[1U];
lypinator 0:bb348c97df44 616 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
lypinator 0:bb348c97df44 617 uint32_t RESERVED3[1U];
lypinator 0:bb348c97df44 618 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
lypinator 0:bb348c97df44 619 uint32_t RESERVED4[1U];
lypinator 0:bb348c97df44 620 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
lypinator 0:bb348c97df44 621 uint32_t RESERVED5[1U];
lypinator 0:bb348c97df44 622 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
lypinator 0:bb348c97df44 623 uint32_t RESERVED6[1U];
lypinator 0:bb348c97df44 624 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
lypinator 0:bb348c97df44 625 uint32_t RESERVED7[1U];
lypinator 0:bb348c97df44 626 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
lypinator 0:bb348c97df44 627 uint32_t RESERVED8[1U];
lypinator 0:bb348c97df44 628 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
lypinator 0:bb348c97df44 629 uint32_t RESERVED9[1U];
lypinator 0:bb348c97df44 630 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
lypinator 0:bb348c97df44 631 uint32_t RESERVED10[1U];
lypinator 0:bb348c97df44 632 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
lypinator 0:bb348c97df44 633 uint32_t RESERVED11[1U];
lypinator 0:bb348c97df44 634 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
lypinator 0:bb348c97df44 635 uint32_t RESERVED12[1U];
lypinator 0:bb348c97df44 636 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
lypinator 0:bb348c97df44 637 uint32_t RESERVED13[1U];
lypinator 0:bb348c97df44 638 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
lypinator 0:bb348c97df44 639 uint32_t RESERVED14[1U];
lypinator 0:bb348c97df44 640 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
lypinator 0:bb348c97df44 641 uint32_t RESERVED15[1U];
lypinator 0:bb348c97df44 642 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
lypinator 0:bb348c97df44 643 uint32_t RESERVED16[1U];
lypinator 0:bb348c97df44 644 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
lypinator 0:bb348c97df44 645 uint32_t RESERVED17[1U];
lypinator 0:bb348c97df44 646 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
lypinator 0:bb348c97df44 647 uint32_t RESERVED18[1U];
lypinator 0:bb348c97df44 648 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
lypinator 0:bb348c97df44 649 uint32_t RESERVED19[1U];
lypinator 0:bb348c97df44 650 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
lypinator 0:bb348c97df44 651 uint32_t RESERVED20[1U];
lypinator 0:bb348c97df44 652 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
lypinator 0:bb348c97df44 653 uint32_t RESERVED21[1U];
lypinator 0:bb348c97df44 654 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
lypinator 0:bb348c97df44 655 uint32_t RESERVED22[1U];
lypinator 0:bb348c97df44 656 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
lypinator 0:bb348c97df44 657 uint32_t RESERVED23[1U];
lypinator 0:bb348c97df44 658 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
lypinator 0:bb348c97df44 659 uint32_t RESERVED24[1U];
lypinator 0:bb348c97df44 660 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
lypinator 0:bb348c97df44 661 uint32_t RESERVED25[1U];
lypinator 0:bb348c97df44 662 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
lypinator 0:bb348c97df44 663 uint32_t RESERVED26[1U];
lypinator 0:bb348c97df44 664 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
lypinator 0:bb348c97df44 665 uint32_t RESERVED27[1U];
lypinator 0:bb348c97df44 666 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
lypinator 0:bb348c97df44 667 uint32_t RESERVED28[1U];
lypinator 0:bb348c97df44 668 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
lypinator 0:bb348c97df44 669 uint32_t RESERVED29[1U];
lypinator 0:bb348c97df44 670 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
lypinator 0:bb348c97df44 671 uint32_t RESERVED30[1U];
lypinator 0:bb348c97df44 672 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
lypinator 0:bb348c97df44 673 uint32_t RESERVED31[1U];
lypinator 0:bb348c97df44 674 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
lypinator 0:bb348c97df44 675 } DWT_Type;
lypinator 0:bb348c97df44 676
lypinator 0:bb348c97df44 677 /* DWT Control Register Definitions */
lypinator 0:bb348c97df44 678 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
lypinator 0:bb348c97df44 679 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
lypinator 0:bb348c97df44 680
lypinator 0:bb348c97df44 681 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
lypinator 0:bb348c97df44 682 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
lypinator 0:bb348c97df44 683
lypinator 0:bb348c97df44 684 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
lypinator 0:bb348c97df44 685 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
lypinator 0:bb348c97df44 686
lypinator 0:bb348c97df44 687 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
lypinator 0:bb348c97df44 688 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
lypinator 0:bb348c97df44 689
lypinator 0:bb348c97df44 690 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
lypinator 0:bb348c97df44 691 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
lypinator 0:bb348c97df44 692
lypinator 0:bb348c97df44 693 /* DWT Comparator Function Register Definitions */
lypinator 0:bb348c97df44 694 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
lypinator 0:bb348c97df44 695 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
lypinator 0:bb348c97df44 696
lypinator 0:bb348c97df44 697 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
lypinator 0:bb348c97df44 698 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
lypinator 0:bb348c97df44 699
lypinator 0:bb348c97df44 700 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
lypinator 0:bb348c97df44 701 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
lypinator 0:bb348c97df44 702
lypinator 0:bb348c97df44 703 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
lypinator 0:bb348c97df44 704 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
lypinator 0:bb348c97df44 705
lypinator 0:bb348c97df44 706 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
lypinator 0:bb348c97df44 707 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
lypinator 0:bb348c97df44 708
lypinator 0:bb348c97df44 709 /*@}*/ /* end of group CMSIS_DWT */
lypinator 0:bb348c97df44 710
lypinator 0:bb348c97df44 711
lypinator 0:bb348c97df44 712 /**
lypinator 0:bb348c97df44 713 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 714 \defgroup CMSIS_TPI Trace Port Interface (TPI)
lypinator 0:bb348c97df44 715 \brief Type definitions for the Trace Port Interface (TPI)
lypinator 0:bb348c97df44 716 @{
lypinator 0:bb348c97df44 717 */
lypinator 0:bb348c97df44 718
lypinator 0:bb348c97df44 719 /**
lypinator 0:bb348c97df44 720 \brief Structure type to access the Trace Port Interface Register (TPI).
lypinator 0:bb348c97df44 721 */
lypinator 0:bb348c97df44 722 typedef struct
lypinator 0:bb348c97df44 723 {
lypinator 0:bb348c97df44 724 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
lypinator 0:bb348c97df44 725 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
lypinator 0:bb348c97df44 726 uint32_t RESERVED0[2U];
lypinator 0:bb348c97df44 727 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
lypinator 0:bb348c97df44 728 uint32_t RESERVED1[55U];
lypinator 0:bb348c97df44 729 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
lypinator 0:bb348c97df44 730 uint32_t RESERVED2[131U];
lypinator 0:bb348c97df44 731 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
lypinator 0:bb348c97df44 732 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
lypinator 0:bb348c97df44 733 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
lypinator 0:bb348c97df44 734 uint32_t RESERVED3[759U];
lypinator 0:bb348c97df44 735 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
lypinator 0:bb348c97df44 736 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
lypinator 0:bb348c97df44 737 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
lypinator 0:bb348c97df44 738 uint32_t RESERVED4[1U];
lypinator 0:bb348c97df44 739 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
lypinator 0:bb348c97df44 740 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
lypinator 0:bb348c97df44 741 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
lypinator 0:bb348c97df44 742 uint32_t RESERVED5[39U];
lypinator 0:bb348c97df44 743 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
lypinator 0:bb348c97df44 744 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
lypinator 0:bb348c97df44 745 uint32_t RESERVED7[8U];
lypinator 0:bb348c97df44 746 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
lypinator 0:bb348c97df44 747 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
lypinator 0:bb348c97df44 748 } TPI_Type;
lypinator 0:bb348c97df44 749
lypinator 0:bb348c97df44 750 /* TPI Asynchronous Clock Prescaler Register Definitions */
lypinator 0:bb348c97df44 751 #define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */
lypinator 0:bb348c97df44 752 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */
lypinator 0:bb348c97df44 753
lypinator 0:bb348c97df44 754 #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
lypinator 0:bb348c97df44 755 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
lypinator 0:bb348c97df44 756
lypinator 0:bb348c97df44 757 /* TPI Selected Pin Protocol Register Definitions */
lypinator 0:bb348c97df44 758 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
lypinator 0:bb348c97df44 759 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
lypinator 0:bb348c97df44 760
lypinator 0:bb348c97df44 761 /* TPI Formatter and Flush Status Register Definitions */
lypinator 0:bb348c97df44 762 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
lypinator 0:bb348c97df44 763 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
lypinator 0:bb348c97df44 764
lypinator 0:bb348c97df44 765 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
lypinator 0:bb348c97df44 766 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
lypinator 0:bb348c97df44 767
lypinator 0:bb348c97df44 768 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
lypinator 0:bb348c97df44 769 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
lypinator 0:bb348c97df44 770
lypinator 0:bb348c97df44 771 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
lypinator 0:bb348c97df44 772 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
lypinator 0:bb348c97df44 773
lypinator 0:bb348c97df44 774 /* TPI Formatter and Flush Control Register Definitions */
lypinator 0:bb348c97df44 775 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
lypinator 0:bb348c97df44 776 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
lypinator 0:bb348c97df44 777
lypinator 0:bb348c97df44 778 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
lypinator 0:bb348c97df44 779 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
lypinator 0:bb348c97df44 780
lypinator 0:bb348c97df44 781 /* TPI TRIGGER Register Definitions */
lypinator 0:bb348c97df44 782 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
lypinator 0:bb348c97df44 783 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
lypinator 0:bb348c97df44 784
lypinator 0:bb348c97df44 785 /* TPI Integration ETM Data Register Definitions (FIFO0) */
lypinator 0:bb348c97df44 786 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
lypinator 0:bb348c97df44 787 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
lypinator 0:bb348c97df44 788
lypinator 0:bb348c97df44 789 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
lypinator 0:bb348c97df44 790 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
lypinator 0:bb348c97df44 791
lypinator 0:bb348c97df44 792 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
lypinator 0:bb348c97df44 793 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
lypinator 0:bb348c97df44 794
lypinator 0:bb348c97df44 795 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
lypinator 0:bb348c97df44 796 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
lypinator 0:bb348c97df44 797
lypinator 0:bb348c97df44 798 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
lypinator 0:bb348c97df44 799 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
lypinator 0:bb348c97df44 800
lypinator 0:bb348c97df44 801 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
lypinator 0:bb348c97df44 802 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
lypinator 0:bb348c97df44 803
lypinator 0:bb348c97df44 804 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
lypinator 0:bb348c97df44 805 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
lypinator 0:bb348c97df44 806
lypinator 0:bb348c97df44 807 /* TPI ITATBCTR2 Register Definitions */
lypinator 0:bb348c97df44 808 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
lypinator 0:bb348c97df44 809 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
lypinator 0:bb348c97df44 810
lypinator 0:bb348c97df44 811 /* TPI Integration ITM Data Register Definitions (FIFO1) */
lypinator 0:bb348c97df44 812 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
lypinator 0:bb348c97df44 813 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
lypinator 0:bb348c97df44 814
lypinator 0:bb348c97df44 815 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
lypinator 0:bb348c97df44 816 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
lypinator 0:bb348c97df44 817
lypinator 0:bb348c97df44 818 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
lypinator 0:bb348c97df44 819 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
lypinator 0:bb348c97df44 820
lypinator 0:bb348c97df44 821 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
lypinator 0:bb348c97df44 822 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
lypinator 0:bb348c97df44 823
lypinator 0:bb348c97df44 824 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
lypinator 0:bb348c97df44 825 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
lypinator 0:bb348c97df44 826
lypinator 0:bb348c97df44 827 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
lypinator 0:bb348c97df44 828 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
lypinator 0:bb348c97df44 829
lypinator 0:bb348c97df44 830 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
lypinator 0:bb348c97df44 831 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
lypinator 0:bb348c97df44 832
lypinator 0:bb348c97df44 833 /* TPI ITATBCTR0 Register Definitions */
lypinator 0:bb348c97df44 834 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
lypinator 0:bb348c97df44 835 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
lypinator 0:bb348c97df44 836
lypinator 0:bb348c97df44 837 /* TPI Integration Mode Control Register Definitions */
lypinator 0:bb348c97df44 838 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
lypinator 0:bb348c97df44 839 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
lypinator 0:bb348c97df44 840
lypinator 0:bb348c97df44 841 /* TPI DEVID Register Definitions */
lypinator 0:bb348c97df44 842 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
lypinator 0:bb348c97df44 843 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
lypinator 0:bb348c97df44 844
lypinator 0:bb348c97df44 845 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
lypinator 0:bb348c97df44 846 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
lypinator 0:bb348c97df44 847
lypinator 0:bb348c97df44 848 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
lypinator 0:bb348c97df44 849 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
lypinator 0:bb348c97df44 850
lypinator 0:bb348c97df44 851 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
lypinator 0:bb348c97df44 852 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
lypinator 0:bb348c97df44 853
lypinator 0:bb348c97df44 854 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
lypinator 0:bb348c97df44 855 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
lypinator 0:bb348c97df44 856
lypinator 0:bb348c97df44 857 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
lypinator 0:bb348c97df44 858 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
lypinator 0:bb348c97df44 859
lypinator 0:bb348c97df44 860 /* TPI DEVTYPE Register Definitions */
lypinator 0:bb348c97df44 861 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
lypinator 0:bb348c97df44 862 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
lypinator 0:bb348c97df44 863
lypinator 0:bb348c97df44 864 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
lypinator 0:bb348c97df44 865 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
lypinator 0:bb348c97df44 866
lypinator 0:bb348c97df44 867 /*@}*/ /* end of group CMSIS_TPI */
lypinator 0:bb348c97df44 868
lypinator 0:bb348c97df44 869
lypinator 0:bb348c97df44 870 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
lypinator 0:bb348c97df44 871 /**
lypinator 0:bb348c97df44 872 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 873 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
lypinator 0:bb348c97df44 874 \brief Type definitions for the Memory Protection Unit (MPU)
lypinator 0:bb348c97df44 875 @{
lypinator 0:bb348c97df44 876 */
lypinator 0:bb348c97df44 877
lypinator 0:bb348c97df44 878 /**
lypinator 0:bb348c97df44 879 \brief Structure type to access the Memory Protection Unit (MPU).
lypinator 0:bb348c97df44 880 */
lypinator 0:bb348c97df44 881 typedef struct
lypinator 0:bb348c97df44 882 {
lypinator 0:bb348c97df44 883 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
lypinator 0:bb348c97df44 884 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
lypinator 0:bb348c97df44 885 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
lypinator 0:bb348c97df44 886 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
lypinator 0:bb348c97df44 887 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
lypinator 0:bb348c97df44 888 uint32_t RESERVED0[7U];
lypinator 0:bb348c97df44 889 union {
lypinator 0:bb348c97df44 890 __IOM uint32_t MAIR[2];
lypinator 0:bb348c97df44 891 struct {
lypinator 0:bb348c97df44 892 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
lypinator 0:bb348c97df44 893 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
lypinator 0:bb348c97df44 894 };
lypinator 0:bb348c97df44 895 };
lypinator 0:bb348c97df44 896 } MPU_Type;
lypinator 0:bb348c97df44 897
lypinator 0:bb348c97df44 898 #define MPU_TYPE_RALIASES 1U
lypinator 0:bb348c97df44 899
lypinator 0:bb348c97df44 900 /* MPU Type Register Definitions */
lypinator 0:bb348c97df44 901 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
lypinator 0:bb348c97df44 902 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
lypinator 0:bb348c97df44 903
lypinator 0:bb348c97df44 904 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
lypinator 0:bb348c97df44 905 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
lypinator 0:bb348c97df44 906
lypinator 0:bb348c97df44 907 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
lypinator 0:bb348c97df44 908 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
lypinator 0:bb348c97df44 909
lypinator 0:bb348c97df44 910 /* MPU Control Register Definitions */
lypinator 0:bb348c97df44 911 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
lypinator 0:bb348c97df44 912 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
lypinator 0:bb348c97df44 913
lypinator 0:bb348c97df44 914 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
lypinator 0:bb348c97df44 915 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
lypinator 0:bb348c97df44 916
lypinator 0:bb348c97df44 917 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
lypinator 0:bb348c97df44 918 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
lypinator 0:bb348c97df44 919
lypinator 0:bb348c97df44 920 /* MPU Region Number Register Definitions */
lypinator 0:bb348c97df44 921 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
lypinator 0:bb348c97df44 922 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
lypinator 0:bb348c97df44 923
lypinator 0:bb348c97df44 924 /* MPU Region Base Address Register Definitions */
lypinator 0:bb348c97df44 925 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
lypinator 0:bb348c97df44 926 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
lypinator 0:bb348c97df44 927
lypinator 0:bb348c97df44 928 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
lypinator 0:bb348c97df44 929 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
lypinator 0:bb348c97df44 930
lypinator 0:bb348c97df44 931 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
lypinator 0:bb348c97df44 932 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
lypinator 0:bb348c97df44 933
lypinator 0:bb348c97df44 934 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
lypinator 0:bb348c97df44 935 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
lypinator 0:bb348c97df44 936
lypinator 0:bb348c97df44 937 /* MPU Region Limit Address Register Definitions */
lypinator 0:bb348c97df44 938 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
lypinator 0:bb348c97df44 939 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
lypinator 0:bb348c97df44 940
lypinator 0:bb348c97df44 941 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
lypinator 0:bb348c97df44 942 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
lypinator 0:bb348c97df44 943
lypinator 0:bb348c97df44 944 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
lypinator 0:bb348c97df44 945 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
lypinator 0:bb348c97df44 946
lypinator 0:bb348c97df44 947 /* MPU Memory Attribute Indirection Register 0 Definitions */
lypinator 0:bb348c97df44 948 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
lypinator 0:bb348c97df44 949 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
lypinator 0:bb348c97df44 950
lypinator 0:bb348c97df44 951 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
lypinator 0:bb348c97df44 952 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
lypinator 0:bb348c97df44 953
lypinator 0:bb348c97df44 954 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
lypinator 0:bb348c97df44 955 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
lypinator 0:bb348c97df44 956
lypinator 0:bb348c97df44 957 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
lypinator 0:bb348c97df44 958 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
lypinator 0:bb348c97df44 959
lypinator 0:bb348c97df44 960 /* MPU Memory Attribute Indirection Register 1 Definitions */
lypinator 0:bb348c97df44 961 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
lypinator 0:bb348c97df44 962 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
lypinator 0:bb348c97df44 963
lypinator 0:bb348c97df44 964 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
lypinator 0:bb348c97df44 965 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
lypinator 0:bb348c97df44 966
lypinator 0:bb348c97df44 967 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
lypinator 0:bb348c97df44 968 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
lypinator 0:bb348c97df44 969
lypinator 0:bb348c97df44 970 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
lypinator 0:bb348c97df44 971 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
lypinator 0:bb348c97df44 972
lypinator 0:bb348c97df44 973 /*@} end of group CMSIS_MPU */
lypinator 0:bb348c97df44 974 #endif
lypinator 0:bb348c97df44 975
lypinator 0:bb348c97df44 976
lypinator 0:bb348c97df44 977 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
lypinator 0:bb348c97df44 978 /**
lypinator 0:bb348c97df44 979 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 980 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
lypinator 0:bb348c97df44 981 \brief Type definitions for the Security Attribution Unit (SAU)
lypinator 0:bb348c97df44 982 @{
lypinator 0:bb348c97df44 983 */
lypinator 0:bb348c97df44 984
lypinator 0:bb348c97df44 985 /**
lypinator 0:bb348c97df44 986 \brief Structure type to access the Security Attribution Unit (SAU).
lypinator 0:bb348c97df44 987 */
lypinator 0:bb348c97df44 988 typedef struct
lypinator 0:bb348c97df44 989 {
lypinator 0:bb348c97df44 990 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
lypinator 0:bb348c97df44 991 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
lypinator 0:bb348c97df44 992 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
lypinator 0:bb348c97df44 993 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
lypinator 0:bb348c97df44 994 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
lypinator 0:bb348c97df44 995 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
lypinator 0:bb348c97df44 996 #endif
lypinator 0:bb348c97df44 997 } SAU_Type;
lypinator 0:bb348c97df44 998
lypinator 0:bb348c97df44 999 /* SAU Control Register Definitions */
lypinator 0:bb348c97df44 1000 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
lypinator 0:bb348c97df44 1001 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
lypinator 0:bb348c97df44 1002
lypinator 0:bb348c97df44 1003 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
lypinator 0:bb348c97df44 1004 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
lypinator 0:bb348c97df44 1005
lypinator 0:bb348c97df44 1006 /* SAU Type Register Definitions */
lypinator 0:bb348c97df44 1007 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
lypinator 0:bb348c97df44 1008 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
lypinator 0:bb348c97df44 1009
lypinator 0:bb348c97df44 1010 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
lypinator 0:bb348c97df44 1011 /* SAU Region Number Register Definitions */
lypinator 0:bb348c97df44 1012 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
lypinator 0:bb348c97df44 1013 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
lypinator 0:bb348c97df44 1014
lypinator 0:bb348c97df44 1015 /* SAU Region Base Address Register Definitions */
lypinator 0:bb348c97df44 1016 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
lypinator 0:bb348c97df44 1017 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
lypinator 0:bb348c97df44 1018
lypinator 0:bb348c97df44 1019 /* SAU Region Limit Address Register Definitions */
lypinator 0:bb348c97df44 1020 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
lypinator 0:bb348c97df44 1021 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
lypinator 0:bb348c97df44 1022
lypinator 0:bb348c97df44 1023 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
lypinator 0:bb348c97df44 1024 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
lypinator 0:bb348c97df44 1025
lypinator 0:bb348c97df44 1026 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
lypinator 0:bb348c97df44 1027 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
lypinator 0:bb348c97df44 1028
lypinator 0:bb348c97df44 1029 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
lypinator 0:bb348c97df44 1030
lypinator 0:bb348c97df44 1031 /*@} end of group CMSIS_SAU */
lypinator 0:bb348c97df44 1032 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
lypinator 0:bb348c97df44 1033
lypinator 0:bb348c97df44 1034
lypinator 0:bb348c97df44 1035 /**
lypinator 0:bb348c97df44 1036 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 1037 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
lypinator 0:bb348c97df44 1038 \brief Type definitions for the Core Debug Registers
lypinator 0:bb348c97df44 1039 @{
lypinator 0:bb348c97df44 1040 */
lypinator 0:bb348c97df44 1041
lypinator 0:bb348c97df44 1042 /**
lypinator 0:bb348c97df44 1043 \brief Structure type to access the Core Debug Register (CoreDebug).
lypinator 0:bb348c97df44 1044 */
lypinator 0:bb348c97df44 1045 typedef struct
lypinator 0:bb348c97df44 1046 {
lypinator 0:bb348c97df44 1047 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
lypinator 0:bb348c97df44 1048 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
lypinator 0:bb348c97df44 1049 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
lypinator 0:bb348c97df44 1050 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
lypinator 0:bb348c97df44 1051 uint32_t RESERVED4[1U];
lypinator 0:bb348c97df44 1052 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
lypinator 0:bb348c97df44 1053 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
lypinator 0:bb348c97df44 1054 } CoreDebug_Type;
lypinator 0:bb348c97df44 1055
lypinator 0:bb348c97df44 1056 /* Debug Halting Control and Status Register Definitions */
lypinator 0:bb348c97df44 1057 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
lypinator 0:bb348c97df44 1058 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
lypinator 0:bb348c97df44 1059
lypinator 0:bb348c97df44 1060 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
lypinator 0:bb348c97df44 1061 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
lypinator 0:bb348c97df44 1062
lypinator 0:bb348c97df44 1063 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
lypinator 0:bb348c97df44 1064 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
lypinator 0:bb348c97df44 1065
lypinator 0:bb348c97df44 1066 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
lypinator 0:bb348c97df44 1067 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
lypinator 0:bb348c97df44 1068
lypinator 0:bb348c97df44 1069 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
lypinator 0:bb348c97df44 1070 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
lypinator 0:bb348c97df44 1071
lypinator 0:bb348c97df44 1072 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
lypinator 0:bb348c97df44 1073 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
lypinator 0:bb348c97df44 1074
lypinator 0:bb348c97df44 1075 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
lypinator 0:bb348c97df44 1076 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
lypinator 0:bb348c97df44 1077
lypinator 0:bb348c97df44 1078 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
lypinator 0:bb348c97df44 1079 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
lypinator 0:bb348c97df44 1080
lypinator 0:bb348c97df44 1081 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
lypinator 0:bb348c97df44 1082 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
lypinator 0:bb348c97df44 1083
lypinator 0:bb348c97df44 1084 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
lypinator 0:bb348c97df44 1085 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
lypinator 0:bb348c97df44 1086
lypinator 0:bb348c97df44 1087 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
lypinator 0:bb348c97df44 1088 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
lypinator 0:bb348c97df44 1089
lypinator 0:bb348c97df44 1090 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
lypinator 0:bb348c97df44 1091 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
lypinator 0:bb348c97df44 1092
lypinator 0:bb348c97df44 1093 /* Debug Core Register Selector Register Definitions */
lypinator 0:bb348c97df44 1094 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
lypinator 0:bb348c97df44 1095 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
lypinator 0:bb348c97df44 1096
lypinator 0:bb348c97df44 1097 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
lypinator 0:bb348c97df44 1098 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
lypinator 0:bb348c97df44 1099
lypinator 0:bb348c97df44 1100 /* Debug Exception and Monitor Control Register */
lypinator 0:bb348c97df44 1101 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
lypinator 0:bb348c97df44 1102 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
lypinator 0:bb348c97df44 1103
lypinator 0:bb348c97df44 1104 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
lypinator 0:bb348c97df44 1105 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
lypinator 0:bb348c97df44 1106
lypinator 0:bb348c97df44 1107 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
lypinator 0:bb348c97df44 1108 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
lypinator 0:bb348c97df44 1109
lypinator 0:bb348c97df44 1110 /* Debug Authentication Control Register Definitions */
lypinator 0:bb348c97df44 1111 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
lypinator 0:bb348c97df44 1112 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
lypinator 0:bb348c97df44 1113
lypinator 0:bb348c97df44 1114 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
lypinator 0:bb348c97df44 1115 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
lypinator 0:bb348c97df44 1116
lypinator 0:bb348c97df44 1117 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
lypinator 0:bb348c97df44 1118 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
lypinator 0:bb348c97df44 1119
lypinator 0:bb348c97df44 1120 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
lypinator 0:bb348c97df44 1121 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
lypinator 0:bb348c97df44 1122
lypinator 0:bb348c97df44 1123 /* Debug Security Control and Status Register Definitions */
lypinator 0:bb348c97df44 1124 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
lypinator 0:bb348c97df44 1125 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
lypinator 0:bb348c97df44 1126
lypinator 0:bb348c97df44 1127 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
lypinator 0:bb348c97df44 1128 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
lypinator 0:bb348c97df44 1129
lypinator 0:bb348c97df44 1130 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
lypinator 0:bb348c97df44 1131 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
lypinator 0:bb348c97df44 1132
lypinator 0:bb348c97df44 1133 /*@} end of group CMSIS_CoreDebug */
lypinator 0:bb348c97df44 1134
lypinator 0:bb348c97df44 1135
lypinator 0:bb348c97df44 1136 /**
lypinator 0:bb348c97df44 1137 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 1138 \defgroup CMSIS_core_bitfield Core register bit field macros
lypinator 0:bb348c97df44 1139 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
lypinator 0:bb348c97df44 1140 @{
lypinator 0:bb348c97df44 1141 */
lypinator 0:bb348c97df44 1142
lypinator 0:bb348c97df44 1143 /**
lypinator 0:bb348c97df44 1144 \brief Mask and shift a bit field value for use in a register bit range.
lypinator 0:bb348c97df44 1145 \param[in] field Name of the register bit field.
lypinator 0:bb348c97df44 1146 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
lypinator 0:bb348c97df44 1147 \return Masked and shifted value.
lypinator 0:bb348c97df44 1148 */
lypinator 0:bb348c97df44 1149 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
lypinator 0:bb348c97df44 1150
lypinator 0:bb348c97df44 1151 /**
lypinator 0:bb348c97df44 1152 \brief Mask and shift a register value to extract a bit filed value.
lypinator 0:bb348c97df44 1153 \param[in] field Name of the register bit field.
lypinator 0:bb348c97df44 1154 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
lypinator 0:bb348c97df44 1155 \return Masked and shifted bit field value.
lypinator 0:bb348c97df44 1156 */
lypinator 0:bb348c97df44 1157 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
lypinator 0:bb348c97df44 1158
lypinator 0:bb348c97df44 1159 /*@} end of group CMSIS_core_bitfield */
lypinator 0:bb348c97df44 1160
lypinator 0:bb348c97df44 1161
lypinator 0:bb348c97df44 1162 /**
lypinator 0:bb348c97df44 1163 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 1164 \defgroup CMSIS_core_base Core Definitions
lypinator 0:bb348c97df44 1165 \brief Definitions for base addresses, unions, and structures.
lypinator 0:bb348c97df44 1166 @{
lypinator 0:bb348c97df44 1167 */
lypinator 0:bb348c97df44 1168
lypinator 0:bb348c97df44 1169 /* Memory mapping of Core Hardware */
lypinator 0:bb348c97df44 1170 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
lypinator 0:bb348c97df44 1171 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
lypinator 0:bb348c97df44 1172 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
lypinator 0:bb348c97df44 1173 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
lypinator 0:bb348c97df44 1174 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
lypinator 0:bb348c97df44 1175 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
lypinator 0:bb348c97df44 1176 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
lypinator 0:bb348c97df44 1177
lypinator 0:bb348c97df44 1178
lypinator 0:bb348c97df44 1179 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
lypinator 0:bb348c97df44 1180 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
lypinator 0:bb348c97df44 1181 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
lypinator 0:bb348c97df44 1182 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
lypinator 0:bb348c97df44 1183 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
lypinator 0:bb348c97df44 1184 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
lypinator 0:bb348c97df44 1185
lypinator 0:bb348c97df44 1186 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
lypinator 0:bb348c97df44 1187 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
lypinator 0:bb348c97df44 1188 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
lypinator 0:bb348c97df44 1189 #endif
lypinator 0:bb348c97df44 1190
lypinator 0:bb348c97df44 1191 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
lypinator 0:bb348c97df44 1192 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
lypinator 0:bb348c97df44 1193 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
lypinator 0:bb348c97df44 1194 #endif
lypinator 0:bb348c97df44 1195
lypinator 0:bb348c97df44 1196 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
lypinator 0:bb348c97df44 1197 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
lypinator 0:bb348c97df44 1198 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
lypinator 0:bb348c97df44 1199 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
lypinator 0:bb348c97df44 1200 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
lypinator 0:bb348c97df44 1201 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
lypinator 0:bb348c97df44 1202
lypinator 0:bb348c97df44 1203 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
lypinator 0:bb348c97df44 1204 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
lypinator 0:bb348c97df44 1205 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
lypinator 0:bb348c97df44 1206 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
lypinator 0:bb348c97df44 1207
lypinator 0:bb348c97df44 1208 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
lypinator 0:bb348c97df44 1209 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
lypinator 0:bb348c97df44 1210 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
lypinator 0:bb348c97df44 1211 #endif
lypinator 0:bb348c97df44 1212
lypinator 0:bb348c97df44 1213 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
lypinator 0:bb348c97df44 1214 /*@} */
lypinator 0:bb348c97df44 1215
lypinator 0:bb348c97df44 1216
lypinator 0:bb348c97df44 1217
lypinator 0:bb348c97df44 1218 /*******************************************************************************
lypinator 0:bb348c97df44 1219 * Hardware Abstraction Layer
lypinator 0:bb348c97df44 1220 Core Function Interface contains:
lypinator 0:bb348c97df44 1221 - Core NVIC Functions
lypinator 0:bb348c97df44 1222 - Core SysTick Functions
lypinator 0:bb348c97df44 1223 - Core Register Access Functions
lypinator 0:bb348c97df44 1224 ******************************************************************************/
lypinator 0:bb348c97df44 1225 /**
lypinator 0:bb348c97df44 1226 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
lypinator 0:bb348c97df44 1227 */
lypinator 0:bb348c97df44 1228
lypinator 0:bb348c97df44 1229
lypinator 0:bb348c97df44 1230
lypinator 0:bb348c97df44 1231 /* ########################## NVIC functions #################################### */
lypinator 0:bb348c97df44 1232 /**
lypinator 0:bb348c97df44 1233 \ingroup CMSIS_Core_FunctionInterface
lypinator 0:bb348c97df44 1234 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
lypinator 0:bb348c97df44 1235 \brief Functions that manage interrupts and exceptions via the NVIC.
lypinator 0:bb348c97df44 1236 @{
lypinator 0:bb348c97df44 1237 */
lypinator 0:bb348c97df44 1238
lypinator 0:bb348c97df44 1239 #ifdef CMSIS_NVIC_VIRTUAL
lypinator 0:bb348c97df44 1240 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
lypinator 0:bb348c97df44 1241 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
lypinator 0:bb348c97df44 1242 #endif
lypinator 0:bb348c97df44 1243 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
lypinator 0:bb348c97df44 1244 #else
lypinator 0:bb348c97df44 1245 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
lypinator 0:bb348c97df44 1246 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
lypinator 0:bb348c97df44 1247 #define NVIC_EnableIRQ __NVIC_EnableIRQ
lypinator 0:bb348c97df44 1248 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
lypinator 0:bb348c97df44 1249 #define NVIC_DisableIRQ __NVIC_DisableIRQ
lypinator 0:bb348c97df44 1250 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
lypinator 0:bb348c97df44 1251 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
lypinator 0:bb348c97df44 1252 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
lypinator 0:bb348c97df44 1253 #define NVIC_GetActive __NVIC_GetActive
lypinator 0:bb348c97df44 1254 #define NVIC_SetPriority __NVIC_SetPriority
lypinator 0:bb348c97df44 1255 #define NVIC_GetPriority __NVIC_GetPriority
lypinator 0:bb348c97df44 1256 #define NVIC_SystemReset __NVIC_SystemReset
lypinator 0:bb348c97df44 1257 #endif /* CMSIS_NVIC_VIRTUAL */
lypinator 0:bb348c97df44 1258
lypinator 0:bb348c97df44 1259 #ifdef CMSIS_VECTAB_VIRTUAL
lypinator 0:bb348c97df44 1260 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
lypinator 0:bb348c97df44 1261 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
lypinator 0:bb348c97df44 1262 #endif
lypinator 0:bb348c97df44 1263 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
lypinator 0:bb348c97df44 1264 #else
lypinator 0:bb348c97df44 1265 #define NVIC_SetVector __NVIC_SetVector
lypinator 0:bb348c97df44 1266 #define NVIC_GetVector __NVIC_GetVector
lypinator 0:bb348c97df44 1267 #endif /* (CMSIS_VECTAB_VIRTUAL) */
lypinator 0:bb348c97df44 1268
lypinator 0:bb348c97df44 1269 #define NVIC_USER_IRQ_OFFSET 16
lypinator 0:bb348c97df44 1270
lypinator 0:bb348c97df44 1271
lypinator 0:bb348c97df44 1272 /* Interrupt Priorities are WORD accessible only under Armv6-M */
lypinator 0:bb348c97df44 1273 /* The following MACROS handle generation of the register offset and byte masks */
lypinator 0:bb348c97df44 1274 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
lypinator 0:bb348c97df44 1275 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
lypinator 0:bb348c97df44 1276 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
lypinator 0:bb348c97df44 1277
lypinator 0:bb348c97df44 1278
lypinator 0:bb348c97df44 1279 /**
lypinator 0:bb348c97df44 1280 \brief Enable Interrupt
lypinator 0:bb348c97df44 1281 \details Enables a device specific interrupt in the NVIC interrupt controller.
lypinator 0:bb348c97df44 1282 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1283 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1284 */
lypinator 0:bb348c97df44 1285 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1286 {
lypinator 0:bb348c97df44 1287 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1288 {
lypinator 0:bb348c97df44 1289 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 1290 }
lypinator 0:bb348c97df44 1291 }
lypinator 0:bb348c97df44 1292
lypinator 0:bb348c97df44 1293
lypinator 0:bb348c97df44 1294 /**
lypinator 0:bb348c97df44 1295 \brief Get Interrupt Enable status
lypinator 0:bb348c97df44 1296 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
lypinator 0:bb348c97df44 1297 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1298 \return 0 Interrupt is not enabled.
lypinator 0:bb348c97df44 1299 \return 1 Interrupt is enabled.
lypinator 0:bb348c97df44 1300 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1301 */
lypinator 0:bb348c97df44 1302 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1303 {
lypinator 0:bb348c97df44 1304 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1305 {
lypinator 0:bb348c97df44 1306 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
lypinator 0:bb348c97df44 1307 }
lypinator 0:bb348c97df44 1308 else
lypinator 0:bb348c97df44 1309 {
lypinator 0:bb348c97df44 1310 return(0U);
lypinator 0:bb348c97df44 1311 }
lypinator 0:bb348c97df44 1312 }
lypinator 0:bb348c97df44 1313
lypinator 0:bb348c97df44 1314
lypinator 0:bb348c97df44 1315 /**
lypinator 0:bb348c97df44 1316 \brief Disable Interrupt
lypinator 0:bb348c97df44 1317 \details Disables a device specific interrupt in the NVIC interrupt controller.
lypinator 0:bb348c97df44 1318 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1319 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1320 */
lypinator 0:bb348c97df44 1321 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1322 {
lypinator 0:bb348c97df44 1323 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1324 {
lypinator 0:bb348c97df44 1325 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 1326 __DSB();
lypinator 0:bb348c97df44 1327 __ISB();
lypinator 0:bb348c97df44 1328 }
lypinator 0:bb348c97df44 1329 }
lypinator 0:bb348c97df44 1330
lypinator 0:bb348c97df44 1331
lypinator 0:bb348c97df44 1332 /**
lypinator 0:bb348c97df44 1333 \brief Get Pending Interrupt
lypinator 0:bb348c97df44 1334 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
lypinator 0:bb348c97df44 1335 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1336 \return 0 Interrupt status is not pending.
lypinator 0:bb348c97df44 1337 \return 1 Interrupt status is pending.
lypinator 0:bb348c97df44 1338 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1339 */
lypinator 0:bb348c97df44 1340 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1341 {
lypinator 0:bb348c97df44 1342 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1343 {
lypinator 0:bb348c97df44 1344 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
lypinator 0:bb348c97df44 1345 }
lypinator 0:bb348c97df44 1346 else
lypinator 0:bb348c97df44 1347 {
lypinator 0:bb348c97df44 1348 return(0U);
lypinator 0:bb348c97df44 1349 }
lypinator 0:bb348c97df44 1350 }
lypinator 0:bb348c97df44 1351
lypinator 0:bb348c97df44 1352
lypinator 0:bb348c97df44 1353 /**
lypinator 0:bb348c97df44 1354 \brief Set Pending Interrupt
lypinator 0:bb348c97df44 1355 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
lypinator 0:bb348c97df44 1356 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1357 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1358 */
lypinator 0:bb348c97df44 1359 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1360 {
lypinator 0:bb348c97df44 1361 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1362 {
lypinator 0:bb348c97df44 1363 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 1364 }
lypinator 0:bb348c97df44 1365 }
lypinator 0:bb348c97df44 1366
lypinator 0:bb348c97df44 1367
lypinator 0:bb348c97df44 1368 /**
lypinator 0:bb348c97df44 1369 \brief Clear Pending Interrupt
lypinator 0:bb348c97df44 1370 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
lypinator 0:bb348c97df44 1371 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1372 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1373 */
lypinator 0:bb348c97df44 1374 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1375 {
lypinator 0:bb348c97df44 1376 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1377 {
lypinator 0:bb348c97df44 1378 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 1379 }
lypinator 0:bb348c97df44 1380 }
lypinator 0:bb348c97df44 1381
lypinator 0:bb348c97df44 1382
lypinator 0:bb348c97df44 1383 /**
lypinator 0:bb348c97df44 1384 \brief Get Active Interrupt
lypinator 0:bb348c97df44 1385 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
lypinator 0:bb348c97df44 1386 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1387 \return 0 Interrupt status is not active.
lypinator 0:bb348c97df44 1388 \return 1 Interrupt status is active.
lypinator 0:bb348c97df44 1389 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1390 */
lypinator 0:bb348c97df44 1391 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1392 {
lypinator 0:bb348c97df44 1393 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1394 {
lypinator 0:bb348c97df44 1395 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
lypinator 0:bb348c97df44 1396 }
lypinator 0:bb348c97df44 1397 else
lypinator 0:bb348c97df44 1398 {
lypinator 0:bb348c97df44 1399 return(0U);
lypinator 0:bb348c97df44 1400 }
lypinator 0:bb348c97df44 1401 }
lypinator 0:bb348c97df44 1402
lypinator 0:bb348c97df44 1403
lypinator 0:bb348c97df44 1404 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
lypinator 0:bb348c97df44 1405 /**
lypinator 0:bb348c97df44 1406 \brief Get Interrupt Target State
lypinator 0:bb348c97df44 1407 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
lypinator 0:bb348c97df44 1408 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1409 \return 0 if interrupt is assigned to Secure
lypinator 0:bb348c97df44 1410 \return 1 if interrupt is assigned to Non Secure
lypinator 0:bb348c97df44 1411 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1412 */
lypinator 0:bb348c97df44 1413 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1414 {
lypinator 0:bb348c97df44 1415 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1416 {
lypinator 0:bb348c97df44 1417 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
lypinator 0:bb348c97df44 1418 }
lypinator 0:bb348c97df44 1419 else
lypinator 0:bb348c97df44 1420 {
lypinator 0:bb348c97df44 1421 return(0U);
lypinator 0:bb348c97df44 1422 }
lypinator 0:bb348c97df44 1423 }
lypinator 0:bb348c97df44 1424
lypinator 0:bb348c97df44 1425
lypinator 0:bb348c97df44 1426 /**
lypinator 0:bb348c97df44 1427 \brief Set Interrupt Target State
lypinator 0:bb348c97df44 1428 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
lypinator 0:bb348c97df44 1429 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1430 \return 0 if interrupt is assigned to Secure
lypinator 0:bb348c97df44 1431 1 if interrupt is assigned to Non Secure
lypinator 0:bb348c97df44 1432 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1433 */
lypinator 0:bb348c97df44 1434 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1435 {
lypinator 0:bb348c97df44 1436 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1437 {
lypinator 0:bb348c97df44 1438 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
lypinator 0:bb348c97df44 1439 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
lypinator 0:bb348c97df44 1440 }
lypinator 0:bb348c97df44 1441 else
lypinator 0:bb348c97df44 1442 {
lypinator 0:bb348c97df44 1443 return(0U);
lypinator 0:bb348c97df44 1444 }
lypinator 0:bb348c97df44 1445 }
lypinator 0:bb348c97df44 1446
lypinator 0:bb348c97df44 1447
lypinator 0:bb348c97df44 1448 /**
lypinator 0:bb348c97df44 1449 \brief Clear Interrupt Target State
lypinator 0:bb348c97df44 1450 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
lypinator 0:bb348c97df44 1451 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1452 \return 0 if interrupt is assigned to Secure
lypinator 0:bb348c97df44 1453 1 if interrupt is assigned to Non Secure
lypinator 0:bb348c97df44 1454 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1455 */
lypinator 0:bb348c97df44 1456 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1457 {
lypinator 0:bb348c97df44 1458 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1459 {
lypinator 0:bb348c97df44 1460 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
lypinator 0:bb348c97df44 1461 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
lypinator 0:bb348c97df44 1462 }
lypinator 0:bb348c97df44 1463 else
lypinator 0:bb348c97df44 1464 {
lypinator 0:bb348c97df44 1465 return(0U);
lypinator 0:bb348c97df44 1466 }
lypinator 0:bb348c97df44 1467 }
lypinator 0:bb348c97df44 1468 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
lypinator 0:bb348c97df44 1469
lypinator 0:bb348c97df44 1470
lypinator 0:bb348c97df44 1471 /**
lypinator 0:bb348c97df44 1472 \brief Set Interrupt Priority
lypinator 0:bb348c97df44 1473 \details Sets the priority of a device specific interrupt or a processor exception.
lypinator 0:bb348c97df44 1474 The interrupt number can be positive to specify a device specific interrupt,
lypinator 0:bb348c97df44 1475 or negative to specify a processor exception.
lypinator 0:bb348c97df44 1476 \param [in] IRQn Interrupt number.
lypinator 0:bb348c97df44 1477 \param [in] priority Priority to set.
lypinator 0:bb348c97df44 1478 \note The priority cannot be set for every processor exception.
lypinator 0:bb348c97df44 1479 */
lypinator 0:bb348c97df44 1480 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
lypinator 0:bb348c97df44 1481 {
lypinator 0:bb348c97df44 1482 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1483 {
lypinator 0:bb348c97df44 1484 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
lypinator 0:bb348c97df44 1485 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
lypinator 0:bb348c97df44 1486 }
lypinator 0:bb348c97df44 1487 else
lypinator 0:bb348c97df44 1488 {
lypinator 0:bb348c97df44 1489 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
lypinator 0:bb348c97df44 1490 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
lypinator 0:bb348c97df44 1491 }
lypinator 0:bb348c97df44 1492 }
lypinator 0:bb348c97df44 1493
lypinator 0:bb348c97df44 1494
lypinator 0:bb348c97df44 1495 /**
lypinator 0:bb348c97df44 1496 \brief Get Interrupt Priority
lypinator 0:bb348c97df44 1497 \details Reads the priority of a device specific interrupt or a processor exception.
lypinator 0:bb348c97df44 1498 The interrupt number can be positive to specify a device specific interrupt,
lypinator 0:bb348c97df44 1499 or negative to specify a processor exception.
lypinator 0:bb348c97df44 1500 \param [in] IRQn Interrupt number.
lypinator 0:bb348c97df44 1501 \return Interrupt Priority.
lypinator 0:bb348c97df44 1502 Value is aligned automatically to the implemented priority bits of the microcontroller.
lypinator 0:bb348c97df44 1503 */
lypinator 0:bb348c97df44 1504 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1505 {
lypinator 0:bb348c97df44 1506
lypinator 0:bb348c97df44 1507 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1508 {
lypinator 0:bb348c97df44 1509 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
lypinator 0:bb348c97df44 1510 }
lypinator 0:bb348c97df44 1511 else
lypinator 0:bb348c97df44 1512 {
lypinator 0:bb348c97df44 1513 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
lypinator 0:bb348c97df44 1514 }
lypinator 0:bb348c97df44 1515 }
lypinator 0:bb348c97df44 1516
lypinator 0:bb348c97df44 1517
lypinator 0:bb348c97df44 1518 /**
lypinator 0:bb348c97df44 1519 \brief Set Interrupt Vector
lypinator 0:bb348c97df44 1520 \details Sets an interrupt vector in SRAM based interrupt vector table.
lypinator 0:bb348c97df44 1521 The interrupt number can be positive to specify a device specific interrupt,
lypinator 0:bb348c97df44 1522 or negative to specify a processor exception.
lypinator 0:bb348c97df44 1523 VTOR must been relocated to SRAM before.
lypinator 0:bb348c97df44 1524 If VTOR is not present address 0 must be mapped to SRAM.
lypinator 0:bb348c97df44 1525 \param [in] IRQn Interrupt number
lypinator 0:bb348c97df44 1526 \param [in] vector Address of interrupt handler function
lypinator 0:bb348c97df44 1527 */
lypinator 0:bb348c97df44 1528 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
lypinator 0:bb348c97df44 1529 {
lypinator 0:bb348c97df44 1530 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
lypinator 0:bb348c97df44 1531 uint32_t *vectors = (uint32_t *)SCB->VTOR;
lypinator 0:bb348c97df44 1532 #else
lypinator 0:bb348c97df44 1533 uint32_t *vectors = (uint32_t *)0x0U;
lypinator 0:bb348c97df44 1534 #endif
lypinator 0:bb348c97df44 1535 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
lypinator 0:bb348c97df44 1536 }
lypinator 0:bb348c97df44 1537
lypinator 0:bb348c97df44 1538
lypinator 0:bb348c97df44 1539 /**
lypinator 0:bb348c97df44 1540 \brief Get Interrupt Vector
lypinator 0:bb348c97df44 1541 \details Reads an interrupt vector from interrupt vector table.
lypinator 0:bb348c97df44 1542 The interrupt number can be positive to specify a device specific interrupt,
lypinator 0:bb348c97df44 1543 or negative to specify a processor exception.
lypinator 0:bb348c97df44 1544 \param [in] IRQn Interrupt number.
lypinator 0:bb348c97df44 1545 \return Address of interrupt handler function
lypinator 0:bb348c97df44 1546 */
lypinator 0:bb348c97df44 1547 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1548 {
lypinator 0:bb348c97df44 1549 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
lypinator 0:bb348c97df44 1550 uint32_t *vectors = (uint32_t *)SCB->VTOR;
lypinator 0:bb348c97df44 1551 #else
lypinator 0:bb348c97df44 1552 uint32_t *vectors = (uint32_t *)0x0U;
lypinator 0:bb348c97df44 1553 #endif
lypinator 0:bb348c97df44 1554 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
lypinator 0:bb348c97df44 1555 }
lypinator 0:bb348c97df44 1556
lypinator 0:bb348c97df44 1557
lypinator 0:bb348c97df44 1558 /**
lypinator 0:bb348c97df44 1559 \brief System Reset
lypinator 0:bb348c97df44 1560 \details Initiates a system reset request to reset the MCU.
lypinator 0:bb348c97df44 1561 */
lypinator 0:bb348c97df44 1562 __STATIC_INLINE void __NVIC_SystemReset(void)
lypinator 0:bb348c97df44 1563 {
lypinator 0:bb348c97df44 1564 __DSB(); /* Ensure all outstanding memory accesses included
lypinator 0:bb348c97df44 1565 buffered write are completed before reset */
lypinator 0:bb348c97df44 1566 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
lypinator 0:bb348c97df44 1567 SCB_AIRCR_SYSRESETREQ_Msk);
lypinator 0:bb348c97df44 1568 __DSB(); /* Ensure completion of memory access */
lypinator 0:bb348c97df44 1569
lypinator 0:bb348c97df44 1570 for(;;) /* wait until reset */
lypinator 0:bb348c97df44 1571 {
lypinator 0:bb348c97df44 1572 __NOP();
lypinator 0:bb348c97df44 1573 }
lypinator 0:bb348c97df44 1574 }
lypinator 0:bb348c97df44 1575
lypinator 0:bb348c97df44 1576 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
lypinator 0:bb348c97df44 1577 /**
lypinator 0:bb348c97df44 1578 \brief Enable Interrupt (non-secure)
lypinator 0:bb348c97df44 1579 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
lypinator 0:bb348c97df44 1580 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1581 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1582 */
lypinator 0:bb348c97df44 1583 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1584 {
lypinator 0:bb348c97df44 1585 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1586 {
lypinator 0:bb348c97df44 1587 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 1588 }
lypinator 0:bb348c97df44 1589 }
lypinator 0:bb348c97df44 1590
lypinator 0:bb348c97df44 1591
lypinator 0:bb348c97df44 1592 /**
lypinator 0:bb348c97df44 1593 \brief Get Interrupt Enable status (non-secure)
lypinator 0:bb348c97df44 1594 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
lypinator 0:bb348c97df44 1595 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1596 \return 0 Interrupt is not enabled.
lypinator 0:bb348c97df44 1597 \return 1 Interrupt is enabled.
lypinator 0:bb348c97df44 1598 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1599 */
lypinator 0:bb348c97df44 1600 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1601 {
lypinator 0:bb348c97df44 1602 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1603 {
lypinator 0:bb348c97df44 1604 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
lypinator 0:bb348c97df44 1605 }
lypinator 0:bb348c97df44 1606 else
lypinator 0:bb348c97df44 1607 {
lypinator 0:bb348c97df44 1608 return(0U);
lypinator 0:bb348c97df44 1609 }
lypinator 0:bb348c97df44 1610 }
lypinator 0:bb348c97df44 1611
lypinator 0:bb348c97df44 1612
lypinator 0:bb348c97df44 1613 /**
lypinator 0:bb348c97df44 1614 \brief Disable Interrupt (non-secure)
lypinator 0:bb348c97df44 1615 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
lypinator 0:bb348c97df44 1616 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1617 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1618 */
lypinator 0:bb348c97df44 1619 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1620 {
lypinator 0:bb348c97df44 1621 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1622 {
lypinator 0:bb348c97df44 1623 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 1624 }
lypinator 0:bb348c97df44 1625 }
lypinator 0:bb348c97df44 1626
lypinator 0:bb348c97df44 1627
lypinator 0:bb348c97df44 1628 /**
lypinator 0:bb348c97df44 1629 \brief Get Pending Interrupt (non-secure)
lypinator 0:bb348c97df44 1630 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
lypinator 0:bb348c97df44 1631 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1632 \return 0 Interrupt status is not pending.
lypinator 0:bb348c97df44 1633 \return 1 Interrupt status is pending.
lypinator 0:bb348c97df44 1634 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1635 */
lypinator 0:bb348c97df44 1636 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1637 {
lypinator 0:bb348c97df44 1638 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1639 {
lypinator 0:bb348c97df44 1640 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
lypinator 0:bb348c97df44 1641 }
lypinator 0:bb348c97df44 1642 else
lypinator 0:bb348c97df44 1643 {
lypinator 0:bb348c97df44 1644 return(0U);
lypinator 0:bb348c97df44 1645 }
lypinator 0:bb348c97df44 1646 }
lypinator 0:bb348c97df44 1647
lypinator 0:bb348c97df44 1648
lypinator 0:bb348c97df44 1649 /**
lypinator 0:bb348c97df44 1650 \brief Set Pending Interrupt (non-secure)
lypinator 0:bb348c97df44 1651 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
lypinator 0:bb348c97df44 1652 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1653 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1654 */
lypinator 0:bb348c97df44 1655 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1656 {
lypinator 0:bb348c97df44 1657 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1658 {
lypinator 0:bb348c97df44 1659 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 1660 }
lypinator 0:bb348c97df44 1661 }
lypinator 0:bb348c97df44 1662
lypinator 0:bb348c97df44 1663
lypinator 0:bb348c97df44 1664 /**
lypinator 0:bb348c97df44 1665 \brief Clear Pending Interrupt (non-secure)
lypinator 0:bb348c97df44 1666 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
lypinator 0:bb348c97df44 1667 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1668 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1669 */
lypinator 0:bb348c97df44 1670 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1671 {
lypinator 0:bb348c97df44 1672 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1673 {
lypinator 0:bb348c97df44 1674 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 1675 }
lypinator 0:bb348c97df44 1676 }
lypinator 0:bb348c97df44 1677
lypinator 0:bb348c97df44 1678
lypinator 0:bb348c97df44 1679 /**
lypinator 0:bb348c97df44 1680 \brief Get Active Interrupt (non-secure)
lypinator 0:bb348c97df44 1681 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
lypinator 0:bb348c97df44 1682 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 1683 \return 0 Interrupt status is not active.
lypinator 0:bb348c97df44 1684 \return 1 Interrupt status is active.
lypinator 0:bb348c97df44 1685 \note IRQn must not be negative.
lypinator 0:bb348c97df44 1686 */
lypinator 0:bb348c97df44 1687 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1688 {
lypinator 0:bb348c97df44 1689 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1690 {
lypinator 0:bb348c97df44 1691 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
lypinator 0:bb348c97df44 1692 }
lypinator 0:bb348c97df44 1693 else
lypinator 0:bb348c97df44 1694 {
lypinator 0:bb348c97df44 1695 return(0U);
lypinator 0:bb348c97df44 1696 }
lypinator 0:bb348c97df44 1697 }
lypinator 0:bb348c97df44 1698
lypinator 0:bb348c97df44 1699
lypinator 0:bb348c97df44 1700 /**
lypinator 0:bb348c97df44 1701 \brief Set Interrupt Priority (non-secure)
lypinator 0:bb348c97df44 1702 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
lypinator 0:bb348c97df44 1703 The interrupt number can be positive to specify a device specific interrupt,
lypinator 0:bb348c97df44 1704 or negative to specify a processor exception.
lypinator 0:bb348c97df44 1705 \param [in] IRQn Interrupt number.
lypinator 0:bb348c97df44 1706 \param [in] priority Priority to set.
lypinator 0:bb348c97df44 1707 \note The priority cannot be set for every non-secure processor exception.
lypinator 0:bb348c97df44 1708 */
lypinator 0:bb348c97df44 1709 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
lypinator 0:bb348c97df44 1710 {
lypinator 0:bb348c97df44 1711 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1712 {
lypinator 0:bb348c97df44 1713 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
lypinator 0:bb348c97df44 1714 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
lypinator 0:bb348c97df44 1715 }
lypinator 0:bb348c97df44 1716 else
lypinator 0:bb348c97df44 1717 {
lypinator 0:bb348c97df44 1718 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
lypinator 0:bb348c97df44 1719 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
lypinator 0:bb348c97df44 1720 }
lypinator 0:bb348c97df44 1721 }
lypinator 0:bb348c97df44 1722
lypinator 0:bb348c97df44 1723
lypinator 0:bb348c97df44 1724 /**
lypinator 0:bb348c97df44 1725 \brief Get Interrupt Priority (non-secure)
lypinator 0:bb348c97df44 1726 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
lypinator 0:bb348c97df44 1727 The interrupt number can be positive to specify a device specific interrupt,
lypinator 0:bb348c97df44 1728 or negative to specify a processor exception.
lypinator 0:bb348c97df44 1729 \param [in] IRQn Interrupt number.
lypinator 0:bb348c97df44 1730 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
lypinator 0:bb348c97df44 1731 */
lypinator 0:bb348c97df44 1732 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
lypinator 0:bb348c97df44 1733 {
lypinator 0:bb348c97df44 1734
lypinator 0:bb348c97df44 1735 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 1736 {
lypinator 0:bb348c97df44 1737 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
lypinator 0:bb348c97df44 1738 }
lypinator 0:bb348c97df44 1739 else
lypinator 0:bb348c97df44 1740 {
lypinator 0:bb348c97df44 1741 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
lypinator 0:bb348c97df44 1742 }
lypinator 0:bb348c97df44 1743 }
lypinator 0:bb348c97df44 1744 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
lypinator 0:bb348c97df44 1745
lypinator 0:bb348c97df44 1746 /*@} end of CMSIS_Core_NVICFunctions */
lypinator 0:bb348c97df44 1747
lypinator 0:bb348c97df44 1748 /* ########################## MPU functions #################################### */
lypinator 0:bb348c97df44 1749
lypinator 0:bb348c97df44 1750 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
lypinator 0:bb348c97df44 1751
lypinator 0:bb348c97df44 1752 #include "mpu_armv8.h"
lypinator 0:bb348c97df44 1753
lypinator 0:bb348c97df44 1754 #endif
lypinator 0:bb348c97df44 1755
lypinator 0:bb348c97df44 1756 /* ########################## FPU functions #################################### */
lypinator 0:bb348c97df44 1757 /**
lypinator 0:bb348c97df44 1758 \ingroup CMSIS_Core_FunctionInterface
lypinator 0:bb348c97df44 1759 \defgroup CMSIS_Core_FpuFunctions FPU Functions
lypinator 0:bb348c97df44 1760 \brief Function that provides FPU type.
lypinator 0:bb348c97df44 1761 @{
lypinator 0:bb348c97df44 1762 */
lypinator 0:bb348c97df44 1763
lypinator 0:bb348c97df44 1764 /**
lypinator 0:bb348c97df44 1765 \brief get FPU type
lypinator 0:bb348c97df44 1766 \details returns the FPU type
lypinator 0:bb348c97df44 1767 \returns
lypinator 0:bb348c97df44 1768 - \b 0: No FPU
lypinator 0:bb348c97df44 1769 - \b 1: Single precision FPU
lypinator 0:bb348c97df44 1770 - \b 2: Double + Single precision FPU
lypinator 0:bb348c97df44 1771 */
lypinator 0:bb348c97df44 1772 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
lypinator 0:bb348c97df44 1773 {
lypinator 0:bb348c97df44 1774 return 0U; /* No FPU */
lypinator 0:bb348c97df44 1775 }
lypinator 0:bb348c97df44 1776
lypinator 0:bb348c97df44 1777
lypinator 0:bb348c97df44 1778 /*@} end of CMSIS_Core_FpuFunctions */
lypinator 0:bb348c97df44 1779
lypinator 0:bb348c97df44 1780
lypinator 0:bb348c97df44 1781
lypinator 0:bb348c97df44 1782 /* ########################## SAU functions #################################### */
lypinator 0:bb348c97df44 1783 /**
lypinator 0:bb348c97df44 1784 \ingroup CMSIS_Core_FunctionInterface
lypinator 0:bb348c97df44 1785 \defgroup CMSIS_Core_SAUFunctions SAU Functions
lypinator 0:bb348c97df44 1786 \brief Functions that configure the SAU.
lypinator 0:bb348c97df44 1787 @{
lypinator 0:bb348c97df44 1788 */
lypinator 0:bb348c97df44 1789
lypinator 0:bb348c97df44 1790 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
lypinator 0:bb348c97df44 1791
lypinator 0:bb348c97df44 1792 /**
lypinator 0:bb348c97df44 1793 \brief Enable SAU
lypinator 0:bb348c97df44 1794 \details Enables the Security Attribution Unit (SAU).
lypinator 0:bb348c97df44 1795 */
lypinator 0:bb348c97df44 1796 __STATIC_INLINE void TZ_SAU_Enable(void)
lypinator 0:bb348c97df44 1797 {
lypinator 0:bb348c97df44 1798 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
lypinator 0:bb348c97df44 1799 }
lypinator 0:bb348c97df44 1800
lypinator 0:bb348c97df44 1801
lypinator 0:bb348c97df44 1802
lypinator 0:bb348c97df44 1803 /**
lypinator 0:bb348c97df44 1804 \brief Disable SAU
lypinator 0:bb348c97df44 1805 \details Disables the Security Attribution Unit (SAU).
lypinator 0:bb348c97df44 1806 */
lypinator 0:bb348c97df44 1807 __STATIC_INLINE void TZ_SAU_Disable(void)
lypinator 0:bb348c97df44 1808 {
lypinator 0:bb348c97df44 1809 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
lypinator 0:bb348c97df44 1810 }
lypinator 0:bb348c97df44 1811
lypinator 0:bb348c97df44 1812 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
lypinator 0:bb348c97df44 1813
lypinator 0:bb348c97df44 1814 /*@} end of CMSIS_Core_SAUFunctions */
lypinator 0:bb348c97df44 1815
lypinator 0:bb348c97df44 1816
lypinator 0:bb348c97df44 1817
lypinator 0:bb348c97df44 1818
lypinator 0:bb348c97df44 1819 /* ################################## SysTick function ############################################ */
lypinator 0:bb348c97df44 1820 /**
lypinator 0:bb348c97df44 1821 \ingroup CMSIS_Core_FunctionInterface
lypinator 0:bb348c97df44 1822 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
lypinator 0:bb348c97df44 1823 \brief Functions that configure the System.
lypinator 0:bb348c97df44 1824 @{
lypinator 0:bb348c97df44 1825 */
lypinator 0:bb348c97df44 1826
lypinator 0:bb348c97df44 1827 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
lypinator 0:bb348c97df44 1828
lypinator 0:bb348c97df44 1829 /**
lypinator 0:bb348c97df44 1830 \brief System Tick Configuration
lypinator 0:bb348c97df44 1831 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
lypinator 0:bb348c97df44 1832 Counter is in free running mode to generate periodic interrupts.
lypinator 0:bb348c97df44 1833 \param [in] ticks Number of ticks between two interrupts.
lypinator 0:bb348c97df44 1834 \return 0 Function succeeded.
lypinator 0:bb348c97df44 1835 \return 1 Function failed.
lypinator 0:bb348c97df44 1836 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
lypinator 0:bb348c97df44 1837 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
lypinator 0:bb348c97df44 1838 must contain a vendor-specific implementation of this function.
lypinator 0:bb348c97df44 1839 */
lypinator 0:bb348c97df44 1840 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
lypinator 0:bb348c97df44 1841 {
lypinator 0:bb348c97df44 1842 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
lypinator 0:bb348c97df44 1843 {
lypinator 0:bb348c97df44 1844 return (1UL); /* Reload value impossible */
lypinator 0:bb348c97df44 1845 }
lypinator 0:bb348c97df44 1846
lypinator 0:bb348c97df44 1847 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
lypinator 0:bb348c97df44 1848 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
lypinator 0:bb348c97df44 1849 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
lypinator 0:bb348c97df44 1850 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
lypinator 0:bb348c97df44 1851 SysTick_CTRL_TICKINT_Msk |
lypinator 0:bb348c97df44 1852 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
lypinator 0:bb348c97df44 1853 return (0UL); /* Function successful */
lypinator 0:bb348c97df44 1854 }
lypinator 0:bb348c97df44 1855
lypinator 0:bb348c97df44 1856 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
lypinator 0:bb348c97df44 1857 /**
lypinator 0:bb348c97df44 1858 \brief System Tick Configuration (non-secure)
lypinator 0:bb348c97df44 1859 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
lypinator 0:bb348c97df44 1860 Counter is in free running mode to generate periodic interrupts.
lypinator 0:bb348c97df44 1861 \param [in] ticks Number of ticks between two interrupts.
lypinator 0:bb348c97df44 1862 \return 0 Function succeeded.
lypinator 0:bb348c97df44 1863 \return 1 Function failed.
lypinator 0:bb348c97df44 1864 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
lypinator 0:bb348c97df44 1865 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
lypinator 0:bb348c97df44 1866 must contain a vendor-specific implementation of this function.
lypinator 0:bb348c97df44 1867
lypinator 0:bb348c97df44 1868 */
lypinator 0:bb348c97df44 1869 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
lypinator 0:bb348c97df44 1870 {
lypinator 0:bb348c97df44 1871 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
lypinator 0:bb348c97df44 1872 {
lypinator 0:bb348c97df44 1873 return (1UL); /* Reload value impossible */
lypinator 0:bb348c97df44 1874 }
lypinator 0:bb348c97df44 1875
lypinator 0:bb348c97df44 1876 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
lypinator 0:bb348c97df44 1877 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
lypinator 0:bb348c97df44 1878 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
lypinator 0:bb348c97df44 1879 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
lypinator 0:bb348c97df44 1880 SysTick_CTRL_TICKINT_Msk |
lypinator 0:bb348c97df44 1881 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
lypinator 0:bb348c97df44 1882 return (0UL); /* Function successful */
lypinator 0:bb348c97df44 1883 }
lypinator 0:bb348c97df44 1884 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
lypinator 0:bb348c97df44 1885
lypinator 0:bb348c97df44 1886 #endif
lypinator 0:bb348c97df44 1887
lypinator 0:bb348c97df44 1888 /*@} end of CMSIS_Core_SysTickFunctions */
lypinator 0:bb348c97df44 1889
lypinator 0:bb348c97df44 1890
lypinator 0:bb348c97df44 1891
lypinator 0:bb348c97df44 1892
lypinator 0:bb348c97df44 1893 #ifdef __cplusplus
lypinator 0:bb348c97df44 1894 }
lypinator 0:bb348c97df44 1895 #endif
lypinator 0:bb348c97df44 1896
lypinator 0:bb348c97df44 1897 #endif /* __CORE_CM23_H_DEPENDANT */
lypinator 0:bb348c97df44 1898
lypinator 0:bb348c97df44 1899 #endif /* __CMSIS_GENERIC */