Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cm0.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

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lypinator 0:bb348c97df44 1 /**************************************************************************//**
lypinator 0:bb348c97df44 2 * @file core_cm0.h
lypinator 0:bb348c97df44 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
lypinator 0:bb348c97df44 4 * @version V5.0.3
lypinator 0:bb348c97df44 5 * @date 10. January 2018
lypinator 0:bb348c97df44 6 ******************************************************************************/
lypinator 0:bb348c97df44 7 /*
lypinator 0:bb348c97df44 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * SPDX-License-Identifier: Apache-2.0
lypinator 0:bb348c97df44 11 *
lypinator 0:bb348c97df44 12 * Licensed under the Apache License, Version 2.0 (the License); you may
lypinator 0:bb348c97df44 13 * not use this file except in compliance with the License.
lypinator 0:bb348c97df44 14 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 15 *
lypinator 0:bb348c97df44 16 * www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 17 *
lypinator 0:bb348c97df44 18 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
lypinator 0:bb348c97df44 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 21 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 22 * limitations under the License.
lypinator 0:bb348c97df44 23 */
lypinator 0:bb348c97df44 24
lypinator 0:bb348c97df44 25 #if defined ( __ICCARM__ )
lypinator 0:bb348c97df44 26 #pragma system_include /* treat file as system include file for MISRA check */
lypinator 0:bb348c97df44 27 #elif defined (__clang__)
lypinator 0:bb348c97df44 28 #pragma clang system_header /* treat file as system include file */
lypinator 0:bb348c97df44 29 #endif
lypinator 0:bb348c97df44 30
lypinator 0:bb348c97df44 31 #ifndef __CORE_CM0_H_GENERIC
lypinator 0:bb348c97df44 32 #define __CORE_CM0_H_GENERIC
lypinator 0:bb348c97df44 33
lypinator 0:bb348c97df44 34 #include <stdint.h>
lypinator 0:bb348c97df44 35
lypinator 0:bb348c97df44 36 #ifdef __cplusplus
lypinator 0:bb348c97df44 37 extern "C" {
lypinator 0:bb348c97df44 38 #endif
lypinator 0:bb348c97df44 39
lypinator 0:bb348c97df44 40 /**
lypinator 0:bb348c97df44 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
lypinator 0:bb348c97df44 42 CMSIS violates the following MISRA-C:2004 rules:
lypinator 0:bb348c97df44 43
lypinator 0:bb348c97df44 44 \li Required Rule 8.5, object/function definition in header file.<br>
lypinator 0:bb348c97df44 45 Function definitions in header files are used to allow 'inlining'.
lypinator 0:bb348c97df44 46
lypinator 0:bb348c97df44 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
lypinator 0:bb348c97df44 48 Unions are used for effective representation of core registers.
lypinator 0:bb348c97df44 49
lypinator 0:bb348c97df44 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
lypinator 0:bb348c97df44 51 Function-like macros are used to allow more efficient code.
lypinator 0:bb348c97df44 52 */
lypinator 0:bb348c97df44 53
lypinator 0:bb348c97df44 54
lypinator 0:bb348c97df44 55 /*******************************************************************************
lypinator 0:bb348c97df44 56 * CMSIS definitions
lypinator 0:bb348c97df44 57 ******************************************************************************/
lypinator 0:bb348c97df44 58 /**
lypinator 0:bb348c97df44 59 \ingroup Cortex_M0
lypinator 0:bb348c97df44 60 @{
lypinator 0:bb348c97df44 61 */
lypinator 0:bb348c97df44 62
lypinator 0:bb348c97df44 63 #include "cmsis_version.h"
lypinator 0:bb348c97df44 64
lypinator 0:bb348c97df44 65 /* CMSIS CM0 definitions */
lypinator 0:bb348c97df44 66 #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
lypinator 0:bb348c97df44 67 #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
lypinator 0:bb348c97df44 68 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
lypinator 0:bb348c97df44 69 __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
lypinator 0:bb348c97df44 70
lypinator 0:bb348c97df44 71 #define __CORTEX_M (0U) /*!< Cortex-M Core */
lypinator 0:bb348c97df44 72
lypinator 0:bb348c97df44 73 /** __FPU_USED indicates whether an FPU is used or not.
lypinator 0:bb348c97df44 74 This core does not support an FPU at all
lypinator 0:bb348c97df44 75 */
lypinator 0:bb348c97df44 76 #define __FPU_USED 0U
lypinator 0:bb348c97df44 77
lypinator 0:bb348c97df44 78 #if defined ( __CC_ARM )
lypinator 0:bb348c97df44 79 #if defined __TARGET_FPU_VFP
lypinator 0:bb348c97df44 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 81 #endif
lypinator 0:bb348c97df44 82
lypinator 0:bb348c97df44 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
lypinator 0:bb348c97df44 84 #if defined __ARM_PCS_VFP
lypinator 0:bb348c97df44 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 86 #endif
lypinator 0:bb348c97df44 87
lypinator 0:bb348c97df44 88 #elif defined ( __GNUC__ )
lypinator 0:bb348c97df44 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
lypinator 0:bb348c97df44 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 91 #endif
lypinator 0:bb348c97df44 92
lypinator 0:bb348c97df44 93 #elif defined ( __ICCARM__ )
lypinator 0:bb348c97df44 94 #if defined __ARMVFP__
lypinator 0:bb348c97df44 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 96 #endif
lypinator 0:bb348c97df44 97
lypinator 0:bb348c97df44 98 #elif defined ( __TI_ARM__ )
lypinator 0:bb348c97df44 99 #if defined __TI_VFP_SUPPORT__
lypinator 0:bb348c97df44 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 101 #endif
lypinator 0:bb348c97df44 102
lypinator 0:bb348c97df44 103 #elif defined ( __TASKING__ )
lypinator 0:bb348c97df44 104 #if defined __FPU_VFP__
lypinator 0:bb348c97df44 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 106 #endif
lypinator 0:bb348c97df44 107
lypinator 0:bb348c97df44 108 #elif defined ( __CSMC__ )
lypinator 0:bb348c97df44 109 #if ( __CSMC__ & 0x400U)
lypinator 0:bb348c97df44 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 111 #endif
lypinator 0:bb348c97df44 112
lypinator 0:bb348c97df44 113 #endif
lypinator 0:bb348c97df44 114
lypinator 0:bb348c97df44 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
lypinator 0:bb348c97df44 116
lypinator 0:bb348c97df44 117
lypinator 0:bb348c97df44 118 #ifdef __cplusplus
lypinator 0:bb348c97df44 119 }
lypinator 0:bb348c97df44 120 #endif
lypinator 0:bb348c97df44 121
lypinator 0:bb348c97df44 122 #endif /* __CORE_CM0_H_GENERIC */
lypinator 0:bb348c97df44 123
lypinator 0:bb348c97df44 124 #ifndef __CMSIS_GENERIC
lypinator 0:bb348c97df44 125
lypinator 0:bb348c97df44 126 #ifndef __CORE_CM0_H_DEPENDANT
lypinator 0:bb348c97df44 127 #define __CORE_CM0_H_DEPENDANT
lypinator 0:bb348c97df44 128
lypinator 0:bb348c97df44 129 #ifdef __cplusplus
lypinator 0:bb348c97df44 130 extern "C" {
lypinator 0:bb348c97df44 131 #endif
lypinator 0:bb348c97df44 132
lypinator 0:bb348c97df44 133 /* check device defines and use defaults */
lypinator 0:bb348c97df44 134 #if defined __CHECK_DEVICE_DEFINES
lypinator 0:bb348c97df44 135 #ifndef __CM0_REV
lypinator 0:bb348c97df44 136 #define __CM0_REV 0x0000U
lypinator 0:bb348c97df44 137 #warning "__CM0_REV not defined in device header file; using default!"
lypinator 0:bb348c97df44 138 #endif
lypinator 0:bb348c97df44 139
lypinator 0:bb348c97df44 140 #ifndef __NVIC_PRIO_BITS
lypinator 0:bb348c97df44 141 #define __NVIC_PRIO_BITS 2U
lypinator 0:bb348c97df44 142 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
lypinator 0:bb348c97df44 143 #endif
lypinator 0:bb348c97df44 144
lypinator 0:bb348c97df44 145 #ifndef __Vendor_SysTickConfig
lypinator 0:bb348c97df44 146 #define __Vendor_SysTickConfig 0U
lypinator 0:bb348c97df44 147 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
lypinator 0:bb348c97df44 148 #endif
lypinator 0:bb348c97df44 149 #endif
lypinator 0:bb348c97df44 150
lypinator 0:bb348c97df44 151 /* IO definitions (access restrictions to peripheral registers) */
lypinator 0:bb348c97df44 152 /**
lypinator 0:bb348c97df44 153 \defgroup CMSIS_glob_defs CMSIS Global Defines
lypinator 0:bb348c97df44 154
lypinator 0:bb348c97df44 155 <strong>IO Type Qualifiers</strong> are used
lypinator 0:bb348c97df44 156 \li to specify the access to peripheral variables.
lypinator 0:bb348c97df44 157 \li for automatic generation of peripheral register debug information.
lypinator 0:bb348c97df44 158 */
lypinator 0:bb348c97df44 159 #ifdef __cplusplus
lypinator 0:bb348c97df44 160 #define __I volatile /*!< Defines 'read only' permissions */
lypinator 0:bb348c97df44 161 #else
lypinator 0:bb348c97df44 162 #define __I volatile const /*!< Defines 'read only' permissions */
lypinator 0:bb348c97df44 163 #endif
lypinator 0:bb348c97df44 164 #define __O volatile /*!< Defines 'write only' permissions */
lypinator 0:bb348c97df44 165 #define __IO volatile /*!< Defines 'read / write' permissions */
lypinator 0:bb348c97df44 166
lypinator 0:bb348c97df44 167 /* following defines should be used for structure members */
lypinator 0:bb348c97df44 168 #define __IM volatile const /*! Defines 'read only' structure member permissions */
lypinator 0:bb348c97df44 169 #define __OM volatile /*! Defines 'write only' structure member permissions */
lypinator 0:bb348c97df44 170 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
lypinator 0:bb348c97df44 171
lypinator 0:bb348c97df44 172 /*@} end of group Cortex_M0 */
lypinator 0:bb348c97df44 173
lypinator 0:bb348c97df44 174
lypinator 0:bb348c97df44 175
lypinator 0:bb348c97df44 176 /*******************************************************************************
lypinator 0:bb348c97df44 177 * Register Abstraction
lypinator 0:bb348c97df44 178 Core Register contain:
lypinator 0:bb348c97df44 179 - Core Register
lypinator 0:bb348c97df44 180 - Core NVIC Register
lypinator 0:bb348c97df44 181 - Core SCB Register
lypinator 0:bb348c97df44 182 - Core SysTick Register
lypinator 0:bb348c97df44 183 ******************************************************************************/
lypinator 0:bb348c97df44 184 /**
lypinator 0:bb348c97df44 185 \defgroup CMSIS_core_register Defines and Type Definitions
lypinator 0:bb348c97df44 186 \brief Type definitions and defines for Cortex-M processor based devices.
lypinator 0:bb348c97df44 187 */
lypinator 0:bb348c97df44 188
lypinator 0:bb348c97df44 189 /**
lypinator 0:bb348c97df44 190 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 191 \defgroup CMSIS_CORE Status and Control Registers
lypinator 0:bb348c97df44 192 \brief Core Register type definitions.
lypinator 0:bb348c97df44 193 @{
lypinator 0:bb348c97df44 194 */
lypinator 0:bb348c97df44 195
lypinator 0:bb348c97df44 196 /**
lypinator 0:bb348c97df44 197 \brief Union type to access the Application Program Status Register (APSR).
lypinator 0:bb348c97df44 198 */
lypinator 0:bb348c97df44 199 typedef union
lypinator 0:bb348c97df44 200 {
lypinator 0:bb348c97df44 201 struct
lypinator 0:bb348c97df44 202 {
lypinator 0:bb348c97df44 203 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
lypinator 0:bb348c97df44 204 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
lypinator 0:bb348c97df44 205 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
lypinator 0:bb348c97df44 206 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
lypinator 0:bb348c97df44 207 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
lypinator 0:bb348c97df44 208 } b; /*!< Structure used for bit access */
lypinator 0:bb348c97df44 209 uint32_t w; /*!< Type used for word access */
lypinator 0:bb348c97df44 210 } APSR_Type;
lypinator 0:bb348c97df44 211
lypinator 0:bb348c97df44 212 /* APSR Register Definitions */
lypinator 0:bb348c97df44 213 #define APSR_N_Pos 31U /*!< APSR: N Position */
lypinator 0:bb348c97df44 214 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
lypinator 0:bb348c97df44 215
lypinator 0:bb348c97df44 216 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
lypinator 0:bb348c97df44 217 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
lypinator 0:bb348c97df44 218
lypinator 0:bb348c97df44 219 #define APSR_C_Pos 29U /*!< APSR: C Position */
lypinator 0:bb348c97df44 220 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
lypinator 0:bb348c97df44 221
lypinator 0:bb348c97df44 222 #define APSR_V_Pos 28U /*!< APSR: V Position */
lypinator 0:bb348c97df44 223 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
lypinator 0:bb348c97df44 224
lypinator 0:bb348c97df44 225
lypinator 0:bb348c97df44 226 /**
lypinator 0:bb348c97df44 227 \brief Union type to access the Interrupt Program Status Register (IPSR).
lypinator 0:bb348c97df44 228 */
lypinator 0:bb348c97df44 229 typedef union
lypinator 0:bb348c97df44 230 {
lypinator 0:bb348c97df44 231 struct
lypinator 0:bb348c97df44 232 {
lypinator 0:bb348c97df44 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
lypinator 0:bb348c97df44 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
lypinator 0:bb348c97df44 235 } b; /*!< Structure used for bit access */
lypinator 0:bb348c97df44 236 uint32_t w; /*!< Type used for word access */
lypinator 0:bb348c97df44 237 } IPSR_Type;
lypinator 0:bb348c97df44 238
lypinator 0:bb348c97df44 239 /* IPSR Register Definitions */
lypinator 0:bb348c97df44 240 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
lypinator 0:bb348c97df44 241 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
lypinator 0:bb348c97df44 242
lypinator 0:bb348c97df44 243
lypinator 0:bb348c97df44 244 /**
lypinator 0:bb348c97df44 245 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
lypinator 0:bb348c97df44 246 */
lypinator 0:bb348c97df44 247 typedef union
lypinator 0:bb348c97df44 248 {
lypinator 0:bb348c97df44 249 struct
lypinator 0:bb348c97df44 250 {
lypinator 0:bb348c97df44 251 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
lypinator 0:bb348c97df44 252 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
lypinator 0:bb348c97df44 253 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
lypinator 0:bb348c97df44 254 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
lypinator 0:bb348c97df44 255 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
lypinator 0:bb348c97df44 256 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
lypinator 0:bb348c97df44 257 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
lypinator 0:bb348c97df44 258 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
lypinator 0:bb348c97df44 259 } b; /*!< Structure used for bit access */
lypinator 0:bb348c97df44 260 uint32_t w; /*!< Type used for word access */
lypinator 0:bb348c97df44 261 } xPSR_Type;
lypinator 0:bb348c97df44 262
lypinator 0:bb348c97df44 263 /* xPSR Register Definitions */
lypinator 0:bb348c97df44 264 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
lypinator 0:bb348c97df44 265 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
lypinator 0:bb348c97df44 266
lypinator 0:bb348c97df44 267 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
lypinator 0:bb348c97df44 268 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
lypinator 0:bb348c97df44 269
lypinator 0:bb348c97df44 270 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
lypinator 0:bb348c97df44 271 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
lypinator 0:bb348c97df44 272
lypinator 0:bb348c97df44 273 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
lypinator 0:bb348c97df44 274 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
lypinator 0:bb348c97df44 275
lypinator 0:bb348c97df44 276 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
lypinator 0:bb348c97df44 277 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
lypinator 0:bb348c97df44 278
lypinator 0:bb348c97df44 279 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
lypinator 0:bb348c97df44 280 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
lypinator 0:bb348c97df44 281
lypinator 0:bb348c97df44 282
lypinator 0:bb348c97df44 283 /**
lypinator 0:bb348c97df44 284 \brief Union type to access the Control Registers (CONTROL).
lypinator 0:bb348c97df44 285 */
lypinator 0:bb348c97df44 286 typedef union
lypinator 0:bb348c97df44 287 {
lypinator 0:bb348c97df44 288 struct
lypinator 0:bb348c97df44 289 {
lypinator 0:bb348c97df44 290 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
lypinator 0:bb348c97df44 291 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
lypinator 0:bb348c97df44 292 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
lypinator 0:bb348c97df44 293 } b; /*!< Structure used for bit access */
lypinator 0:bb348c97df44 294 uint32_t w; /*!< Type used for word access */
lypinator 0:bb348c97df44 295 } CONTROL_Type;
lypinator 0:bb348c97df44 296
lypinator 0:bb348c97df44 297 /* CONTROL Register Definitions */
lypinator 0:bb348c97df44 298 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
lypinator 0:bb348c97df44 299 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
lypinator 0:bb348c97df44 300
lypinator 0:bb348c97df44 301 /*@} end of group CMSIS_CORE */
lypinator 0:bb348c97df44 302
lypinator 0:bb348c97df44 303
lypinator 0:bb348c97df44 304 /**
lypinator 0:bb348c97df44 305 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 306 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
lypinator 0:bb348c97df44 307 \brief Type definitions for the NVIC Registers
lypinator 0:bb348c97df44 308 @{
lypinator 0:bb348c97df44 309 */
lypinator 0:bb348c97df44 310
lypinator 0:bb348c97df44 311 /**
lypinator 0:bb348c97df44 312 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
lypinator 0:bb348c97df44 313 */
lypinator 0:bb348c97df44 314 typedef struct
lypinator 0:bb348c97df44 315 {
lypinator 0:bb348c97df44 316 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
lypinator 0:bb348c97df44 317 uint32_t RESERVED0[31U];
lypinator 0:bb348c97df44 318 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
lypinator 0:bb348c97df44 319 uint32_t RSERVED1[31U];
lypinator 0:bb348c97df44 320 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
lypinator 0:bb348c97df44 321 uint32_t RESERVED2[31U];
lypinator 0:bb348c97df44 322 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
lypinator 0:bb348c97df44 323 uint32_t RESERVED3[31U];
lypinator 0:bb348c97df44 324 uint32_t RESERVED4[64U];
lypinator 0:bb348c97df44 325 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
lypinator 0:bb348c97df44 326 } NVIC_Type;
lypinator 0:bb348c97df44 327
lypinator 0:bb348c97df44 328 /*@} end of group CMSIS_NVIC */
lypinator 0:bb348c97df44 329
lypinator 0:bb348c97df44 330
lypinator 0:bb348c97df44 331 /**
lypinator 0:bb348c97df44 332 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 333 \defgroup CMSIS_SCB System Control Block (SCB)
lypinator 0:bb348c97df44 334 \brief Type definitions for the System Control Block Registers
lypinator 0:bb348c97df44 335 @{
lypinator 0:bb348c97df44 336 */
lypinator 0:bb348c97df44 337
lypinator 0:bb348c97df44 338 /**
lypinator 0:bb348c97df44 339 \brief Structure type to access the System Control Block (SCB).
lypinator 0:bb348c97df44 340 */
lypinator 0:bb348c97df44 341 typedef struct
lypinator 0:bb348c97df44 342 {
lypinator 0:bb348c97df44 343 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
lypinator 0:bb348c97df44 344 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
lypinator 0:bb348c97df44 345 uint32_t RESERVED0;
lypinator 0:bb348c97df44 346 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
lypinator 0:bb348c97df44 347 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
lypinator 0:bb348c97df44 348 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
lypinator 0:bb348c97df44 349 uint32_t RESERVED1;
lypinator 0:bb348c97df44 350 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
lypinator 0:bb348c97df44 351 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
lypinator 0:bb348c97df44 352 } SCB_Type;
lypinator 0:bb348c97df44 353
lypinator 0:bb348c97df44 354 /* SCB CPUID Register Definitions */
lypinator 0:bb348c97df44 355 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
lypinator 0:bb348c97df44 356 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
lypinator 0:bb348c97df44 357
lypinator 0:bb348c97df44 358 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
lypinator 0:bb348c97df44 359 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
lypinator 0:bb348c97df44 360
lypinator 0:bb348c97df44 361 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
lypinator 0:bb348c97df44 362 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
lypinator 0:bb348c97df44 363
lypinator 0:bb348c97df44 364 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
lypinator 0:bb348c97df44 365 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
lypinator 0:bb348c97df44 366
lypinator 0:bb348c97df44 367 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
lypinator 0:bb348c97df44 368 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
lypinator 0:bb348c97df44 369
lypinator 0:bb348c97df44 370 /* SCB Interrupt Control State Register Definitions */
lypinator 0:bb348c97df44 371 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
lypinator 0:bb348c97df44 372 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
lypinator 0:bb348c97df44 373
lypinator 0:bb348c97df44 374 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
lypinator 0:bb348c97df44 375 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
lypinator 0:bb348c97df44 376
lypinator 0:bb348c97df44 377 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
lypinator 0:bb348c97df44 378 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
lypinator 0:bb348c97df44 379
lypinator 0:bb348c97df44 380 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
lypinator 0:bb348c97df44 381 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
lypinator 0:bb348c97df44 382
lypinator 0:bb348c97df44 383 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
lypinator 0:bb348c97df44 384 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
lypinator 0:bb348c97df44 385
lypinator 0:bb348c97df44 386 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
lypinator 0:bb348c97df44 387 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
lypinator 0:bb348c97df44 388
lypinator 0:bb348c97df44 389 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
lypinator 0:bb348c97df44 390 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
lypinator 0:bb348c97df44 391
lypinator 0:bb348c97df44 392 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
lypinator 0:bb348c97df44 393 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
lypinator 0:bb348c97df44 394
lypinator 0:bb348c97df44 395 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
lypinator 0:bb348c97df44 396 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
lypinator 0:bb348c97df44 397
lypinator 0:bb348c97df44 398 /* SCB Application Interrupt and Reset Control Register Definitions */
lypinator 0:bb348c97df44 399 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
lypinator 0:bb348c97df44 400 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
lypinator 0:bb348c97df44 401
lypinator 0:bb348c97df44 402 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
lypinator 0:bb348c97df44 403 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
lypinator 0:bb348c97df44 404
lypinator 0:bb348c97df44 405 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
lypinator 0:bb348c97df44 406 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
lypinator 0:bb348c97df44 407
lypinator 0:bb348c97df44 408 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
lypinator 0:bb348c97df44 409 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
lypinator 0:bb348c97df44 410
lypinator 0:bb348c97df44 411 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
lypinator 0:bb348c97df44 412 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
lypinator 0:bb348c97df44 413
lypinator 0:bb348c97df44 414 /* SCB System Control Register Definitions */
lypinator 0:bb348c97df44 415 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
lypinator 0:bb348c97df44 416 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
lypinator 0:bb348c97df44 417
lypinator 0:bb348c97df44 418 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
lypinator 0:bb348c97df44 419 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
lypinator 0:bb348c97df44 420
lypinator 0:bb348c97df44 421 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
lypinator 0:bb348c97df44 422 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
lypinator 0:bb348c97df44 423
lypinator 0:bb348c97df44 424 /* SCB Configuration Control Register Definitions */
lypinator 0:bb348c97df44 425 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
lypinator 0:bb348c97df44 426 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
lypinator 0:bb348c97df44 427
lypinator 0:bb348c97df44 428 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
lypinator 0:bb348c97df44 429 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
lypinator 0:bb348c97df44 430
lypinator 0:bb348c97df44 431 /* SCB System Handler Control and State Register Definitions */
lypinator 0:bb348c97df44 432 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
lypinator 0:bb348c97df44 433 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
lypinator 0:bb348c97df44 434
lypinator 0:bb348c97df44 435 /*@} end of group CMSIS_SCB */
lypinator 0:bb348c97df44 436
lypinator 0:bb348c97df44 437
lypinator 0:bb348c97df44 438 /**
lypinator 0:bb348c97df44 439 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 440 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
lypinator 0:bb348c97df44 441 \brief Type definitions for the System Timer Registers.
lypinator 0:bb348c97df44 442 @{
lypinator 0:bb348c97df44 443 */
lypinator 0:bb348c97df44 444
lypinator 0:bb348c97df44 445 /**
lypinator 0:bb348c97df44 446 \brief Structure type to access the System Timer (SysTick).
lypinator 0:bb348c97df44 447 */
lypinator 0:bb348c97df44 448 typedef struct
lypinator 0:bb348c97df44 449 {
lypinator 0:bb348c97df44 450 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
lypinator 0:bb348c97df44 451 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
lypinator 0:bb348c97df44 452 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
lypinator 0:bb348c97df44 453 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
lypinator 0:bb348c97df44 454 } SysTick_Type;
lypinator 0:bb348c97df44 455
lypinator 0:bb348c97df44 456 /* SysTick Control / Status Register Definitions */
lypinator 0:bb348c97df44 457 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
lypinator 0:bb348c97df44 458 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
lypinator 0:bb348c97df44 459
lypinator 0:bb348c97df44 460 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
lypinator 0:bb348c97df44 461 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
lypinator 0:bb348c97df44 462
lypinator 0:bb348c97df44 463 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
lypinator 0:bb348c97df44 464 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
lypinator 0:bb348c97df44 465
lypinator 0:bb348c97df44 466 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
lypinator 0:bb348c97df44 467 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
lypinator 0:bb348c97df44 468
lypinator 0:bb348c97df44 469 /* SysTick Reload Register Definitions */
lypinator 0:bb348c97df44 470 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
lypinator 0:bb348c97df44 471 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
lypinator 0:bb348c97df44 472
lypinator 0:bb348c97df44 473 /* SysTick Current Register Definitions */
lypinator 0:bb348c97df44 474 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
lypinator 0:bb348c97df44 475 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
lypinator 0:bb348c97df44 476
lypinator 0:bb348c97df44 477 /* SysTick Calibration Register Definitions */
lypinator 0:bb348c97df44 478 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
lypinator 0:bb348c97df44 479 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
lypinator 0:bb348c97df44 480
lypinator 0:bb348c97df44 481 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
lypinator 0:bb348c97df44 482 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
lypinator 0:bb348c97df44 483
lypinator 0:bb348c97df44 484 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
lypinator 0:bb348c97df44 485 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
lypinator 0:bb348c97df44 486
lypinator 0:bb348c97df44 487 /*@} end of group CMSIS_SysTick */
lypinator 0:bb348c97df44 488
lypinator 0:bb348c97df44 489
lypinator 0:bb348c97df44 490 /**
lypinator 0:bb348c97df44 491 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 492 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
lypinator 0:bb348c97df44 493 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
lypinator 0:bb348c97df44 494 Therefore they are not covered by the Cortex-M0 header file.
lypinator 0:bb348c97df44 495 @{
lypinator 0:bb348c97df44 496 */
lypinator 0:bb348c97df44 497 /*@} end of group CMSIS_CoreDebug */
lypinator 0:bb348c97df44 498
lypinator 0:bb348c97df44 499
lypinator 0:bb348c97df44 500 /**
lypinator 0:bb348c97df44 501 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 502 \defgroup CMSIS_core_bitfield Core register bit field macros
lypinator 0:bb348c97df44 503 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
lypinator 0:bb348c97df44 504 @{
lypinator 0:bb348c97df44 505 */
lypinator 0:bb348c97df44 506
lypinator 0:bb348c97df44 507 /**
lypinator 0:bb348c97df44 508 \brief Mask and shift a bit field value for use in a register bit range.
lypinator 0:bb348c97df44 509 \param[in] field Name of the register bit field.
lypinator 0:bb348c97df44 510 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
lypinator 0:bb348c97df44 511 \return Masked and shifted value.
lypinator 0:bb348c97df44 512 */
lypinator 0:bb348c97df44 513 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
lypinator 0:bb348c97df44 514
lypinator 0:bb348c97df44 515 /**
lypinator 0:bb348c97df44 516 \brief Mask and shift a register value to extract a bit filed value.
lypinator 0:bb348c97df44 517 \param[in] field Name of the register bit field.
lypinator 0:bb348c97df44 518 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
lypinator 0:bb348c97df44 519 \return Masked and shifted bit field value.
lypinator 0:bb348c97df44 520 */
lypinator 0:bb348c97df44 521 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
lypinator 0:bb348c97df44 522
lypinator 0:bb348c97df44 523 /*@} end of group CMSIS_core_bitfield */
lypinator 0:bb348c97df44 524
lypinator 0:bb348c97df44 525
lypinator 0:bb348c97df44 526 /**
lypinator 0:bb348c97df44 527 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 528 \defgroup CMSIS_core_base Core Definitions
lypinator 0:bb348c97df44 529 \brief Definitions for base addresses, unions, and structures.
lypinator 0:bb348c97df44 530 @{
lypinator 0:bb348c97df44 531 */
lypinator 0:bb348c97df44 532
lypinator 0:bb348c97df44 533 /* Memory mapping of Core Hardware */
lypinator 0:bb348c97df44 534 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
lypinator 0:bb348c97df44 535 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
lypinator 0:bb348c97df44 536 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
lypinator 0:bb348c97df44 537 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
lypinator 0:bb348c97df44 538
lypinator 0:bb348c97df44 539 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
lypinator 0:bb348c97df44 540 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
lypinator 0:bb348c97df44 541 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
lypinator 0:bb348c97df44 542
lypinator 0:bb348c97df44 543
lypinator 0:bb348c97df44 544 /*@} */
lypinator 0:bb348c97df44 545
lypinator 0:bb348c97df44 546
lypinator 0:bb348c97df44 547
lypinator 0:bb348c97df44 548 /*******************************************************************************
lypinator 0:bb348c97df44 549 * Hardware Abstraction Layer
lypinator 0:bb348c97df44 550 Core Function Interface contains:
lypinator 0:bb348c97df44 551 - Core NVIC Functions
lypinator 0:bb348c97df44 552 - Core SysTick Functions
lypinator 0:bb348c97df44 553 - Core Register Access Functions
lypinator 0:bb348c97df44 554 ******************************************************************************/
lypinator 0:bb348c97df44 555 /**
lypinator 0:bb348c97df44 556 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
lypinator 0:bb348c97df44 557 */
lypinator 0:bb348c97df44 558
lypinator 0:bb348c97df44 559
lypinator 0:bb348c97df44 560
lypinator 0:bb348c97df44 561 /* ########################## NVIC functions #################################### */
lypinator 0:bb348c97df44 562 /**
lypinator 0:bb348c97df44 563 \ingroup CMSIS_Core_FunctionInterface
lypinator 0:bb348c97df44 564 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
lypinator 0:bb348c97df44 565 \brief Functions that manage interrupts and exceptions via the NVIC.
lypinator 0:bb348c97df44 566 @{
lypinator 0:bb348c97df44 567 */
lypinator 0:bb348c97df44 568
lypinator 0:bb348c97df44 569 #ifdef CMSIS_NVIC_VIRTUAL
lypinator 0:bb348c97df44 570 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
lypinator 0:bb348c97df44 571 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
lypinator 0:bb348c97df44 572 #endif
lypinator 0:bb348c97df44 573 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
lypinator 0:bb348c97df44 574 #else
lypinator 0:bb348c97df44 575 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
lypinator 0:bb348c97df44 576 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
lypinator 0:bb348c97df44 577 #define NVIC_EnableIRQ __NVIC_EnableIRQ
lypinator 0:bb348c97df44 578 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
lypinator 0:bb348c97df44 579 #define NVIC_DisableIRQ __NVIC_DisableIRQ
lypinator 0:bb348c97df44 580 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
lypinator 0:bb348c97df44 581 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
lypinator 0:bb348c97df44 582 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
lypinator 0:bb348c97df44 583 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
lypinator 0:bb348c97df44 584 #define NVIC_SetPriority __NVIC_SetPriority
lypinator 0:bb348c97df44 585 #define NVIC_GetPriority __NVIC_GetPriority
lypinator 0:bb348c97df44 586 #define NVIC_SystemReset __NVIC_SystemReset
lypinator 0:bb348c97df44 587 #endif /* CMSIS_NVIC_VIRTUAL */
lypinator 0:bb348c97df44 588
lypinator 0:bb348c97df44 589 #ifdef CMSIS_VECTAB_VIRTUAL
lypinator 0:bb348c97df44 590 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
lypinator 0:bb348c97df44 591 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
lypinator 0:bb348c97df44 592 #endif
lypinator 0:bb348c97df44 593 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
lypinator 0:bb348c97df44 594 #else
lypinator 0:bb348c97df44 595 #define NVIC_SetVector __NVIC_SetVector
lypinator 0:bb348c97df44 596 #define NVIC_GetVector __NVIC_GetVector
lypinator 0:bb348c97df44 597 #endif /* (CMSIS_VECTAB_VIRTUAL) */
lypinator 0:bb348c97df44 598
lypinator 0:bb348c97df44 599 #define NVIC_USER_IRQ_OFFSET 16
lypinator 0:bb348c97df44 600
lypinator 0:bb348c97df44 601
lypinator 0:bb348c97df44 602 /* Interrupt Priorities are WORD accessible only under Armv6-M */
lypinator 0:bb348c97df44 603 /* The following MACROS handle generation of the register offset and byte masks */
lypinator 0:bb348c97df44 604 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
lypinator 0:bb348c97df44 605 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
lypinator 0:bb348c97df44 606 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
lypinator 0:bb348c97df44 607
lypinator 0:bb348c97df44 608
lypinator 0:bb348c97df44 609 /**
lypinator 0:bb348c97df44 610 \brief Enable Interrupt
lypinator 0:bb348c97df44 611 \details Enables a device specific interrupt in the NVIC interrupt controller.
lypinator 0:bb348c97df44 612 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 613 \note IRQn must not be negative.
lypinator 0:bb348c97df44 614 */
lypinator 0:bb348c97df44 615 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 616 {
lypinator 0:bb348c97df44 617 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 618 {
lypinator 0:bb348c97df44 619 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 620 }
lypinator 0:bb348c97df44 621 }
lypinator 0:bb348c97df44 622
lypinator 0:bb348c97df44 623
lypinator 0:bb348c97df44 624 /**
lypinator 0:bb348c97df44 625 \brief Get Interrupt Enable status
lypinator 0:bb348c97df44 626 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
lypinator 0:bb348c97df44 627 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 628 \return 0 Interrupt is not enabled.
lypinator 0:bb348c97df44 629 \return 1 Interrupt is enabled.
lypinator 0:bb348c97df44 630 \note IRQn must not be negative.
lypinator 0:bb348c97df44 631 */
lypinator 0:bb348c97df44 632 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 633 {
lypinator 0:bb348c97df44 634 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 635 {
lypinator 0:bb348c97df44 636 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
lypinator 0:bb348c97df44 637 }
lypinator 0:bb348c97df44 638 else
lypinator 0:bb348c97df44 639 {
lypinator 0:bb348c97df44 640 return(0U);
lypinator 0:bb348c97df44 641 }
lypinator 0:bb348c97df44 642 }
lypinator 0:bb348c97df44 643
lypinator 0:bb348c97df44 644
lypinator 0:bb348c97df44 645 /**
lypinator 0:bb348c97df44 646 \brief Disable Interrupt
lypinator 0:bb348c97df44 647 \details Disables a device specific interrupt in the NVIC interrupt controller.
lypinator 0:bb348c97df44 648 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 649 \note IRQn must not be negative.
lypinator 0:bb348c97df44 650 */
lypinator 0:bb348c97df44 651 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 652 {
lypinator 0:bb348c97df44 653 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 654 {
lypinator 0:bb348c97df44 655 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 656 __DSB();
lypinator 0:bb348c97df44 657 __ISB();
lypinator 0:bb348c97df44 658 }
lypinator 0:bb348c97df44 659 }
lypinator 0:bb348c97df44 660
lypinator 0:bb348c97df44 661
lypinator 0:bb348c97df44 662 /**
lypinator 0:bb348c97df44 663 \brief Get Pending Interrupt
lypinator 0:bb348c97df44 664 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
lypinator 0:bb348c97df44 665 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 666 \return 0 Interrupt status is not pending.
lypinator 0:bb348c97df44 667 \return 1 Interrupt status is pending.
lypinator 0:bb348c97df44 668 \note IRQn must not be negative.
lypinator 0:bb348c97df44 669 */
lypinator 0:bb348c97df44 670 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 671 {
lypinator 0:bb348c97df44 672 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 673 {
lypinator 0:bb348c97df44 674 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
lypinator 0:bb348c97df44 675 }
lypinator 0:bb348c97df44 676 else
lypinator 0:bb348c97df44 677 {
lypinator 0:bb348c97df44 678 return(0U);
lypinator 0:bb348c97df44 679 }
lypinator 0:bb348c97df44 680 }
lypinator 0:bb348c97df44 681
lypinator 0:bb348c97df44 682
lypinator 0:bb348c97df44 683 /**
lypinator 0:bb348c97df44 684 \brief Set Pending Interrupt
lypinator 0:bb348c97df44 685 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
lypinator 0:bb348c97df44 686 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 687 \note IRQn must not be negative.
lypinator 0:bb348c97df44 688 */
lypinator 0:bb348c97df44 689 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 690 {
lypinator 0:bb348c97df44 691 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 692 {
lypinator 0:bb348c97df44 693 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 694 }
lypinator 0:bb348c97df44 695 }
lypinator 0:bb348c97df44 696
lypinator 0:bb348c97df44 697
lypinator 0:bb348c97df44 698 /**
lypinator 0:bb348c97df44 699 \brief Clear Pending Interrupt
lypinator 0:bb348c97df44 700 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
lypinator 0:bb348c97df44 701 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 702 \note IRQn must not be negative.
lypinator 0:bb348c97df44 703 */
lypinator 0:bb348c97df44 704 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 705 {
lypinator 0:bb348c97df44 706 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 707 {
lypinator 0:bb348c97df44 708 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 709 }
lypinator 0:bb348c97df44 710 }
lypinator 0:bb348c97df44 711
lypinator 0:bb348c97df44 712
lypinator 0:bb348c97df44 713 /**
lypinator 0:bb348c97df44 714 \brief Set Interrupt Priority
lypinator 0:bb348c97df44 715 \details Sets the priority of a device specific interrupt or a processor exception.
lypinator 0:bb348c97df44 716 The interrupt number can be positive to specify a device specific interrupt,
lypinator 0:bb348c97df44 717 or negative to specify a processor exception.
lypinator 0:bb348c97df44 718 \param [in] IRQn Interrupt number.
lypinator 0:bb348c97df44 719 \param [in] priority Priority to set.
lypinator 0:bb348c97df44 720 \note The priority cannot be set for every processor exception.
lypinator 0:bb348c97df44 721 */
lypinator 0:bb348c97df44 722 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
lypinator 0:bb348c97df44 723 {
lypinator 0:bb348c97df44 724 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 725 {
lypinator 0:bb348c97df44 726 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
lypinator 0:bb348c97df44 727 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
lypinator 0:bb348c97df44 728 }
lypinator 0:bb348c97df44 729 else
lypinator 0:bb348c97df44 730 {
lypinator 0:bb348c97df44 731 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
lypinator 0:bb348c97df44 732 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
lypinator 0:bb348c97df44 733 }
lypinator 0:bb348c97df44 734 }
lypinator 0:bb348c97df44 735
lypinator 0:bb348c97df44 736
lypinator 0:bb348c97df44 737 /**
lypinator 0:bb348c97df44 738 \brief Get Interrupt Priority
lypinator 0:bb348c97df44 739 \details Reads the priority of a device specific interrupt or a processor exception.
lypinator 0:bb348c97df44 740 The interrupt number can be positive to specify a device specific interrupt,
lypinator 0:bb348c97df44 741 or negative to specify a processor exception.
lypinator 0:bb348c97df44 742 \param [in] IRQn Interrupt number.
lypinator 0:bb348c97df44 743 \return Interrupt Priority.
lypinator 0:bb348c97df44 744 Value is aligned automatically to the implemented priority bits of the microcontroller.
lypinator 0:bb348c97df44 745 */
lypinator 0:bb348c97df44 746 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
lypinator 0:bb348c97df44 747 {
lypinator 0:bb348c97df44 748
lypinator 0:bb348c97df44 749 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 750 {
lypinator 0:bb348c97df44 751 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
lypinator 0:bb348c97df44 752 }
lypinator 0:bb348c97df44 753 else
lypinator 0:bb348c97df44 754 {
lypinator 0:bb348c97df44 755 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
lypinator 0:bb348c97df44 756 }
lypinator 0:bb348c97df44 757 }
lypinator 0:bb348c97df44 758
lypinator 0:bb348c97df44 759
lypinator 0:bb348c97df44 760 /**
lypinator 0:bb348c97df44 761 \brief Set Interrupt Vector
lypinator 0:bb348c97df44 762 \details Sets an interrupt vector in SRAM based interrupt vector table.
lypinator 0:bb348c97df44 763 The interrupt number can be positive to specify a device specific interrupt,
lypinator 0:bb348c97df44 764 or negative to specify a processor exception.
lypinator 0:bb348c97df44 765 Address 0 must be mapped to SRAM.
lypinator 0:bb348c97df44 766 \param [in] IRQn Interrupt number
lypinator 0:bb348c97df44 767 \param [in] vector Address of interrupt handler function
lypinator 0:bb348c97df44 768 */
lypinator 0:bb348c97df44 769 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
lypinator 0:bb348c97df44 770 {
lypinator 0:bb348c97df44 771 uint32_t *vectors = (uint32_t *)0x0U;
lypinator 0:bb348c97df44 772 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
lypinator 0:bb348c97df44 773 }
lypinator 0:bb348c97df44 774
lypinator 0:bb348c97df44 775
lypinator 0:bb348c97df44 776 /**
lypinator 0:bb348c97df44 777 \brief Get Interrupt Vector
lypinator 0:bb348c97df44 778 \details Reads an interrupt vector from interrupt vector table.
lypinator 0:bb348c97df44 779 The interrupt number can be positive to specify a device specific interrupt,
lypinator 0:bb348c97df44 780 or negative to specify a processor exception.
lypinator 0:bb348c97df44 781 \param [in] IRQn Interrupt number.
lypinator 0:bb348c97df44 782 \return Address of interrupt handler function
lypinator 0:bb348c97df44 783 */
lypinator 0:bb348c97df44 784 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
lypinator 0:bb348c97df44 785 {
lypinator 0:bb348c97df44 786 uint32_t *vectors = (uint32_t *)0x0U;
lypinator 0:bb348c97df44 787 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
lypinator 0:bb348c97df44 788 }
lypinator 0:bb348c97df44 789
lypinator 0:bb348c97df44 790
lypinator 0:bb348c97df44 791 /**
lypinator 0:bb348c97df44 792 \brief System Reset
lypinator 0:bb348c97df44 793 \details Initiates a system reset request to reset the MCU.
lypinator 0:bb348c97df44 794 */
lypinator 0:bb348c97df44 795 __STATIC_INLINE void __NVIC_SystemReset(void)
lypinator 0:bb348c97df44 796 {
lypinator 0:bb348c97df44 797 __DSB(); /* Ensure all outstanding memory accesses included
lypinator 0:bb348c97df44 798 buffered write are completed before reset */
lypinator 0:bb348c97df44 799 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
lypinator 0:bb348c97df44 800 SCB_AIRCR_SYSRESETREQ_Msk);
lypinator 0:bb348c97df44 801 __DSB(); /* Ensure completion of memory access */
lypinator 0:bb348c97df44 802
lypinator 0:bb348c97df44 803 for(;;) /* wait until reset */
lypinator 0:bb348c97df44 804 {
lypinator 0:bb348c97df44 805 __NOP();
lypinator 0:bb348c97df44 806 }
lypinator 0:bb348c97df44 807 }
lypinator 0:bb348c97df44 808
lypinator 0:bb348c97df44 809 /*@} end of CMSIS_Core_NVICFunctions */
lypinator 0:bb348c97df44 810
lypinator 0:bb348c97df44 811
lypinator 0:bb348c97df44 812 /* ########################## FPU functions #################################### */
lypinator 0:bb348c97df44 813 /**
lypinator 0:bb348c97df44 814 \ingroup CMSIS_Core_FunctionInterface
lypinator 0:bb348c97df44 815 \defgroup CMSIS_Core_FpuFunctions FPU Functions
lypinator 0:bb348c97df44 816 \brief Function that provides FPU type.
lypinator 0:bb348c97df44 817 @{
lypinator 0:bb348c97df44 818 */
lypinator 0:bb348c97df44 819
lypinator 0:bb348c97df44 820 /**
lypinator 0:bb348c97df44 821 \brief get FPU type
lypinator 0:bb348c97df44 822 \details returns the FPU type
lypinator 0:bb348c97df44 823 \returns
lypinator 0:bb348c97df44 824 - \b 0: No FPU
lypinator 0:bb348c97df44 825 - \b 1: Single precision FPU
lypinator 0:bb348c97df44 826 - \b 2: Double + Single precision FPU
lypinator 0:bb348c97df44 827 */
lypinator 0:bb348c97df44 828 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
lypinator 0:bb348c97df44 829 {
lypinator 0:bb348c97df44 830 return 0U; /* No FPU */
lypinator 0:bb348c97df44 831 }
lypinator 0:bb348c97df44 832
lypinator 0:bb348c97df44 833
lypinator 0:bb348c97df44 834 /*@} end of CMSIS_Core_FpuFunctions */
lypinator 0:bb348c97df44 835
lypinator 0:bb348c97df44 836
lypinator 0:bb348c97df44 837
lypinator 0:bb348c97df44 838 /* ################################## SysTick function ############################################ */
lypinator 0:bb348c97df44 839 /**
lypinator 0:bb348c97df44 840 \ingroup CMSIS_Core_FunctionInterface
lypinator 0:bb348c97df44 841 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
lypinator 0:bb348c97df44 842 \brief Functions that configure the System.
lypinator 0:bb348c97df44 843 @{
lypinator 0:bb348c97df44 844 */
lypinator 0:bb348c97df44 845
lypinator 0:bb348c97df44 846 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
lypinator 0:bb348c97df44 847
lypinator 0:bb348c97df44 848 /**
lypinator 0:bb348c97df44 849 \brief System Tick Configuration
lypinator 0:bb348c97df44 850 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
lypinator 0:bb348c97df44 851 Counter is in free running mode to generate periodic interrupts.
lypinator 0:bb348c97df44 852 \param [in] ticks Number of ticks between two interrupts.
lypinator 0:bb348c97df44 853 \return 0 Function succeeded.
lypinator 0:bb348c97df44 854 \return 1 Function failed.
lypinator 0:bb348c97df44 855 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
lypinator 0:bb348c97df44 856 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
lypinator 0:bb348c97df44 857 must contain a vendor-specific implementation of this function.
lypinator 0:bb348c97df44 858 */
lypinator 0:bb348c97df44 859 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
lypinator 0:bb348c97df44 860 {
lypinator 0:bb348c97df44 861 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
lypinator 0:bb348c97df44 862 {
lypinator 0:bb348c97df44 863 return (1UL); /* Reload value impossible */
lypinator 0:bb348c97df44 864 }
lypinator 0:bb348c97df44 865
lypinator 0:bb348c97df44 866 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
lypinator 0:bb348c97df44 867 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
lypinator 0:bb348c97df44 868 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
lypinator 0:bb348c97df44 869 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
lypinator 0:bb348c97df44 870 SysTick_CTRL_TICKINT_Msk |
lypinator 0:bb348c97df44 871 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
lypinator 0:bb348c97df44 872 return (0UL); /* Function successful */
lypinator 0:bb348c97df44 873 }
lypinator 0:bb348c97df44 874
lypinator 0:bb348c97df44 875 #endif
lypinator 0:bb348c97df44 876
lypinator 0:bb348c97df44 877 /*@} end of CMSIS_Core_SysTickFunctions */
lypinator 0:bb348c97df44 878
lypinator 0:bb348c97df44 879
lypinator 0:bb348c97df44 880
lypinator 0:bb348c97df44 881
lypinator 0:bb348c97df44 882 #ifdef __cplusplus
lypinator 0:bb348c97df44 883 }
lypinator 0:bb348c97df44 884 #endif
lypinator 0:bb348c97df44 885
lypinator 0:bb348c97df44 886 #endif /* __CORE_CM0_H_DEPENDANT */
lypinator 0:bb348c97df44 887
lypinator 0:bb348c97df44 888 #endif /* __CMSIS_GENERIC */