Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/cmsis/TARGET_CORTEX_M/cmsis_gcc.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**************************************************************************//**
lypinator 0:bb348c97df44 2 * @file cmsis_gcc.h
lypinator 0:bb348c97df44 3 * @brief CMSIS compiler GCC header file
lypinator 0:bb348c97df44 4 * @version V5.0.3
lypinator 0:bb348c97df44 5 * @date 16. January 2018
lypinator 0:bb348c97df44 6 ******************************************************************************/
lypinator 0:bb348c97df44 7 /*
lypinator 0:bb348c97df44 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * SPDX-License-Identifier: Apache-2.0
lypinator 0:bb348c97df44 11 *
lypinator 0:bb348c97df44 12 * Licensed under the Apache License, Version 2.0 (the License); you may
lypinator 0:bb348c97df44 13 * not use this file except in compliance with the License.
lypinator 0:bb348c97df44 14 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 15 *
lypinator 0:bb348c97df44 16 * www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 17 *
lypinator 0:bb348c97df44 18 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
lypinator 0:bb348c97df44 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 21 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 22 * limitations under the License.
lypinator 0:bb348c97df44 23 */
lypinator 0:bb348c97df44 24
lypinator 0:bb348c97df44 25 #ifndef __CMSIS_GCC_H
lypinator 0:bb348c97df44 26 #define __CMSIS_GCC_H
lypinator 0:bb348c97df44 27
lypinator 0:bb348c97df44 28 /* ignore some GCC warnings */
lypinator 0:bb348c97df44 29 #pragma GCC diagnostic push
lypinator 0:bb348c97df44 30 #pragma GCC diagnostic ignored "-Wsign-conversion"
lypinator 0:bb348c97df44 31 #pragma GCC diagnostic ignored "-Wconversion"
lypinator 0:bb348c97df44 32 #pragma GCC diagnostic ignored "-Wunused-parameter"
lypinator 0:bb348c97df44 33
lypinator 0:bb348c97df44 34 /* Fallback for __has_builtin */
lypinator 0:bb348c97df44 35 #ifndef __has_builtin
lypinator 0:bb348c97df44 36 #define __has_builtin(x) (0)
lypinator 0:bb348c97df44 37 #endif
lypinator 0:bb348c97df44 38
lypinator 0:bb348c97df44 39 /* CMSIS compiler specific defines */
lypinator 0:bb348c97df44 40 #ifndef __ASM
lypinator 0:bb348c97df44 41 #define __ASM __asm
lypinator 0:bb348c97df44 42 #endif
lypinator 0:bb348c97df44 43 #ifndef __INLINE
lypinator 0:bb348c97df44 44 #define __INLINE inline
lypinator 0:bb348c97df44 45 #endif
lypinator 0:bb348c97df44 46 #ifndef __STATIC_INLINE
lypinator 0:bb348c97df44 47 #define __STATIC_INLINE static inline
lypinator 0:bb348c97df44 48 #endif
lypinator 0:bb348c97df44 49 #ifndef __STATIC_FORCEINLINE
lypinator 0:bb348c97df44 50 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
lypinator 0:bb348c97df44 51 #endif
lypinator 0:bb348c97df44 52 #ifndef __NO_RETURN
lypinator 0:bb348c97df44 53 #define __NO_RETURN __attribute__((__noreturn__))
lypinator 0:bb348c97df44 54 #endif
lypinator 0:bb348c97df44 55 #ifndef __USED
lypinator 0:bb348c97df44 56 #define __USED __attribute__((used))
lypinator 0:bb348c97df44 57 #endif
lypinator 0:bb348c97df44 58 #ifndef __WEAK
lypinator 0:bb348c97df44 59 #define __WEAK __attribute__((weak))
lypinator 0:bb348c97df44 60 #endif
lypinator 0:bb348c97df44 61 #ifndef __PACKED
lypinator 0:bb348c97df44 62 #define __PACKED __attribute__((packed, aligned(1)))
lypinator 0:bb348c97df44 63 #endif
lypinator 0:bb348c97df44 64 #ifndef __PACKED_STRUCT
lypinator 0:bb348c97df44 65 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
lypinator 0:bb348c97df44 66 #endif
lypinator 0:bb348c97df44 67 #ifndef __PACKED_UNION
lypinator 0:bb348c97df44 68 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
lypinator 0:bb348c97df44 69 #endif
lypinator 0:bb348c97df44 70 #ifndef __UNALIGNED_UINT32 /* deprecated */
lypinator 0:bb348c97df44 71 #pragma GCC diagnostic push
lypinator 0:bb348c97df44 72 #pragma GCC diagnostic ignored "-Wpacked"
lypinator 0:bb348c97df44 73 #pragma GCC diagnostic ignored "-Wattributes"
lypinator 0:bb348c97df44 74 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
lypinator 0:bb348c97df44 75 #pragma GCC diagnostic pop
lypinator 0:bb348c97df44 76 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
lypinator 0:bb348c97df44 77 #endif
lypinator 0:bb348c97df44 78 #ifndef __UNALIGNED_UINT16_WRITE
lypinator 0:bb348c97df44 79 #pragma GCC diagnostic push
lypinator 0:bb348c97df44 80 #pragma GCC diagnostic ignored "-Wpacked"
lypinator 0:bb348c97df44 81 #pragma GCC diagnostic ignored "-Wattributes"
lypinator 0:bb348c97df44 82 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
lypinator 0:bb348c97df44 83 #pragma GCC diagnostic pop
lypinator 0:bb348c97df44 84 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
lypinator 0:bb348c97df44 85 #endif
lypinator 0:bb348c97df44 86 #ifndef __UNALIGNED_UINT16_READ
lypinator 0:bb348c97df44 87 #pragma GCC diagnostic push
lypinator 0:bb348c97df44 88 #pragma GCC diagnostic ignored "-Wpacked"
lypinator 0:bb348c97df44 89 #pragma GCC diagnostic ignored "-Wattributes"
lypinator 0:bb348c97df44 90 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
lypinator 0:bb348c97df44 91 #pragma GCC diagnostic pop
lypinator 0:bb348c97df44 92 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
lypinator 0:bb348c97df44 93 #endif
lypinator 0:bb348c97df44 94 #ifndef __UNALIGNED_UINT32_WRITE
lypinator 0:bb348c97df44 95 #pragma GCC diagnostic push
lypinator 0:bb348c97df44 96 #pragma GCC diagnostic ignored "-Wpacked"
lypinator 0:bb348c97df44 97 #pragma GCC diagnostic ignored "-Wattributes"
lypinator 0:bb348c97df44 98 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
lypinator 0:bb348c97df44 99 #pragma GCC diagnostic pop
lypinator 0:bb348c97df44 100 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
lypinator 0:bb348c97df44 101 #endif
lypinator 0:bb348c97df44 102 #ifndef __UNALIGNED_UINT32_READ
lypinator 0:bb348c97df44 103 #pragma GCC diagnostic push
lypinator 0:bb348c97df44 104 #pragma GCC diagnostic ignored "-Wpacked"
lypinator 0:bb348c97df44 105 #pragma GCC diagnostic ignored "-Wattributes"
lypinator 0:bb348c97df44 106 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
lypinator 0:bb348c97df44 107 #pragma GCC diagnostic pop
lypinator 0:bb348c97df44 108 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
lypinator 0:bb348c97df44 109 #endif
lypinator 0:bb348c97df44 110 #ifndef __ALIGNED
lypinator 0:bb348c97df44 111 #define __ALIGNED(x) __attribute__((aligned(x)))
lypinator 0:bb348c97df44 112 #endif
lypinator 0:bb348c97df44 113 #ifndef __RESTRICT
lypinator 0:bb348c97df44 114 #define __RESTRICT __restrict
lypinator 0:bb348c97df44 115 #endif
lypinator 0:bb348c97df44 116
lypinator 0:bb348c97df44 117
lypinator 0:bb348c97df44 118 /* ########################### Core Function Access ########################### */
lypinator 0:bb348c97df44 119 /** \ingroup CMSIS_Core_FunctionInterface
lypinator 0:bb348c97df44 120 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
lypinator 0:bb348c97df44 121 @{
lypinator 0:bb348c97df44 122 */
lypinator 0:bb348c97df44 123
lypinator 0:bb348c97df44 124 /**
lypinator 0:bb348c97df44 125 \brief Enable IRQ Interrupts
lypinator 0:bb348c97df44 126 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
lypinator 0:bb348c97df44 127 Can only be executed in Privileged modes.
lypinator 0:bb348c97df44 128 */
lypinator 0:bb348c97df44 129 __STATIC_FORCEINLINE void __enable_irq(void)
lypinator 0:bb348c97df44 130 {
lypinator 0:bb348c97df44 131 __ASM volatile ("cpsie i" : : : "memory");
lypinator 0:bb348c97df44 132 }
lypinator 0:bb348c97df44 133
lypinator 0:bb348c97df44 134
lypinator 0:bb348c97df44 135 /**
lypinator 0:bb348c97df44 136 \brief Disable IRQ Interrupts
lypinator 0:bb348c97df44 137 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
lypinator 0:bb348c97df44 138 Can only be executed in Privileged modes.
lypinator 0:bb348c97df44 139 */
lypinator 0:bb348c97df44 140 __STATIC_FORCEINLINE void __disable_irq(void)
lypinator 0:bb348c97df44 141 {
lypinator 0:bb348c97df44 142 __ASM volatile ("cpsid i" : : : "memory");
lypinator 0:bb348c97df44 143 }
lypinator 0:bb348c97df44 144
lypinator 0:bb348c97df44 145
lypinator 0:bb348c97df44 146 /**
lypinator 0:bb348c97df44 147 \brief Get Control Register
lypinator 0:bb348c97df44 148 \details Returns the content of the Control Register.
lypinator 0:bb348c97df44 149 \return Control Register value
lypinator 0:bb348c97df44 150 */
lypinator 0:bb348c97df44 151 __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
lypinator 0:bb348c97df44 152 {
lypinator 0:bb348c97df44 153 uint32_t result;
lypinator 0:bb348c97df44 154
lypinator 0:bb348c97df44 155 __ASM volatile ("MRS %0, control" : "=r" (result) );
lypinator 0:bb348c97df44 156 return(result);
lypinator 0:bb348c97df44 157 }
lypinator 0:bb348c97df44 158
lypinator 0:bb348c97df44 159
lypinator 0:bb348c97df44 160 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 161 /**
lypinator 0:bb348c97df44 162 \brief Get Control Register (non-secure)
lypinator 0:bb348c97df44 163 \details Returns the content of the non-secure Control Register when in secure mode.
lypinator 0:bb348c97df44 164 \return non-secure Control Register value
lypinator 0:bb348c97df44 165 */
lypinator 0:bb348c97df44 166 __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
lypinator 0:bb348c97df44 167 {
lypinator 0:bb348c97df44 168 uint32_t result;
lypinator 0:bb348c97df44 169
lypinator 0:bb348c97df44 170 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
lypinator 0:bb348c97df44 171 return(result);
lypinator 0:bb348c97df44 172 }
lypinator 0:bb348c97df44 173 #endif
lypinator 0:bb348c97df44 174
lypinator 0:bb348c97df44 175
lypinator 0:bb348c97df44 176 /**
lypinator 0:bb348c97df44 177 \brief Set Control Register
lypinator 0:bb348c97df44 178 \details Writes the given value to the Control Register.
lypinator 0:bb348c97df44 179 \param [in] control Control Register value to set
lypinator 0:bb348c97df44 180 */
lypinator 0:bb348c97df44 181 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
lypinator 0:bb348c97df44 182 {
lypinator 0:bb348c97df44 183 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
lypinator 0:bb348c97df44 184 }
lypinator 0:bb348c97df44 185
lypinator 0:bb348c97df44 186
lypinator 0:bb348c97df44 187 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 188 /**
lypinator 0:bb348c97df44 189 \brief Set Control Register (non-secure)
lypinator 0:bb348c97df44 190 \details Writes the given value to the non-secure Control Register when in secure state.
lypinator 0:bb348c97df44 191 \param [in] control Control Register value to set
lypinator 0:bb348c97df44 192 */
lypinator 0:bb348c97df44 193 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
lypinator 0:bb348c97df44 194 {
lypinator 0:bb348c97df44 195 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
lypinator 0:bb348c97df44 196 }
lypinator 0:bb348c97df44 197 #endif
lypinator 0:bb348c97df44 198
lypinator 0:bb348c97df44 199
lypinator 0:bb348c97df44 200 /**
lypinator 0:bb348c97df44 201 \brief Get IPSR Register
lypinator 0:bb348c97df44 202 \details Returns the content of the IPSR Register.
lypinator 0:bb348c97df44 203 \return IPSR Register value
lypinator 0:bb348c97df44 204 */
lypinator 0:bb348c97df44 205 __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
lypinator 0:bb348c97df44 206 {
lypinator 0:bb348c97df44 207 uint32_t result;
lypinator 0:bb348c97df44 208
lypinator 0:bb348c97df44 209 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
lypinator 0:bb348c97df44 210 return(result);
lypinator 0:bb348c97df44 211 }
lypinator 0:bb348c97df44 212
lypinator 0:bb348c97df44 213
lypinator 0:bb348c97df44 214 /**
lypinator 0:bb348c97df44 215 \brief Get APSR Register
lypinator 0:bb348c97df44 216 \details Returns the content of the APSR Register.
lypinator 0:bb348c97df44 217 \return APSR Register value
lypinator 0:bb348c97df44 218 */
lypinator 0:bb348c97df44 219 __STATIC_FORCEINLINE uint32_t __get_APSR(void)
lypinator 0:bb348c97df44 220 {
lypinator 0:bb348c97df44 221 uint32_t result;
lypinator 0:bb348c97df44 222
lypinator 0:bb348c97df44 223 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
lypinator 0:bb348c97df44 224 return(result);
lypinator 0:bb348c97df44 225 }
lypinator 0:bb348c97df44 226
lypinator 0:bb348c97df44 227
lypinator 0:bb348c97df44 228 /**
lypinator 0:bb348c97df44 229 \brief Get xPSR Register
lypinator 0:bb348c97df44 230 \details Returns the content of the xPSR Register.
lypinator 0:bb348c97df44 231 \return xPSR Register value
lypinator 0:bb348c97df44 232 */
lypinator 0:bb348c97df44 233 __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
lypinator 0:bb348c97df44 234 {
lypinator 0:bb348c97df44 235 uint32_t result;
lypinator 0:bb348c97df44 236
lypinator 0:bb348c97df44 237 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
lypinator 0:bb348c97df44 238 return(result);
lypinator 0:bb348c97df44 239 }
lypinator 0:bb348c97df44 240
lypinator 0:bb348c97df44 241
lypinator 0:bb348c97df44 242 /**
lypinator 0:bb348c97df44 243 \brief Get Process Stack Pointer
lypinator 0:bb348c97df44 244 \details Returns the current value of the Process Stack Pointer (PSP).
lypinator 0:bb348c97df44 245 \return PSP Register value
lypinator 0:bb348c97df44 246 */
lypinator 0:bb348c97df44 247 __STATIC_FORCEINLINE uint32_t __get_PSP(void)
lypinator 0:bb348c97df44 248 {
lypinator 0:bb348c97df44 249 register uint32_t result;
lypinator 0:bb348c97df44 250
lypinator 0:bb348c97df44 251 __ASM volatile ("MRS %0, psp" : "=r" (result) );
lypinator 0:bb348c97df44 252 return(result);
lypinator 0:bb348c97df44 253 }
lypinator 0:bb348c97df44 254
lypinator 0:bb348c97df44 255
lypinator 0:bb348c97df44 256 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 257 /**
lypinator 0:bb348c97df44 258 \brief Get Process Stack Pointer (non-secure)
lypinator 0:bb348c97df44 259 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
lypinator 0:bb348c97df44 260 \return PSP Register value
lypinator 0:bb348c97df44 261 */
lypinator 0:bb348c97df44 262 __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
lypinator 0:bb348c97df44 263 {
lypinator 0:bb348c97df44 264 register uint32_t result;
lypinator 0:bb348c97df44 265
lypinator 0:bb348c97df44 266 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
lypinator 0:bb348c97df44 267 return(result);
lypinator 0:bb348c97df44 268 }
lypinator 0:bb348c97df44 269 #endif
lypinator 0:bb348c97df44 270
lypinator 0:bb348c97df44 271
lypinator 0:bb348c97df44 272 /**
lypinator 0:bb348c97df44 273 \brief Set Process Stack Pointer
lypinator 0:bb348c97df44 274 \details Assigns the given value to the Process Stack Pointer (PSP).
lypinator 0:bb348c97df44 275 \param [in] topOfProcStack Process Stack Pointer value to set
lypinator 0:bb348c97df44 276 */
lypinator 0:bb348c97df44 277 __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
lypinator 0:bb348c97df44 278 {
lypinator 0:bb348c97df44 279 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
lypinator 0:bb348c97df44 280 }
lypinator 0:bb348c97df44 281
lypinator 0:bb348c97df44 282
lypinator 0:bb348c97df44 283 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 284 /**
lypinator 0:bb348c97df44 285 \brief Set Process Stack Pointer (non-secure)
lypinator 0:bb348c97df44 286 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
lypinator 0:bb348c97df44 287 \param [in] topOfProcStack Process Stack Pointer value to set
lypinator 0:bb348c97df44 288 */
lypinator 0:bb348c97df44 289 __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
lypinator 0:bb348c97df44 290 {
lypinator 0:bb348c97df44 291 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
lypinator 0:bb348c97df44 292 }
lypinator 0:bb348c97df44 293 #endif
lypinator 0:bb348c97df44 294
lypinator 0:bb348c97df44 295
lypinator 0:bb348c97df44 296 /**
lypinator 0:bb348c97df44 297 \brief Get Main Stack Pointer
lypinator 0:bb348c97df44 298 \details Returns the current value of the Main Stack Pointer (MSP).
lypinator 0:bb348c97df44 299 \return MSP Register value
lypinator 0:bb348c97df44 300 */
lypinator 0:bb348c97df44 301 __STATIC_FORCEINLINE uint32_t __get_MSP(void)
lypinator 0:bb348c97df44 302 {
lypinator 0:bb348c97df44 303 register uint32_t result;
lypinator 0:bb348c97df44 304
lypinator 0:bb348c97df44 305 __ASM volatile ("MRS %0, msp" : "=r" (result) );
lypinator 0:bb348c97df44 306 return(result);
lypinator 0:bb348c97df44 307 }
lypinator 0:bb348c97df44 308
lypinator 0:bb348c97df44 309
lypinator 0:bb348c97df44 310 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 311 /**
lypinator 0:bb348c97df44 312 \brief Get Main Stack Pointer (non-secure)
lypinator 0:bb348c97df44 313 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
lypinator 0:bb348c97df44 314 \return MSP Register value
lypinator 0:bb348c97df44 315 */
lypinator 0:bb348c97df44 316 __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
lypinator 0:bb348c97df44 317 {
lypinator 0:bb348c97df44 318 register uint32_t result;
lypinator 0:bb348c97df44 319
lypinator 0:bb348c97df44 320 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
lypinator 0:bb348c97df44 321 return(result);
lypinator 0:bb348c97df44 322 }
lypinator 0:bb348c97df44 323 #endif
lypinator 0:bb348c97df44 324
lypinator 0:bb348c97df44 325
lypinator 0:bb348c97df44 326 /**
lypinator 0:bb348c97df44 327 \brief Set Main Stack Pointer
lypinator 0:bb348c97df44 328 \details Assigns the given value to the Main Stack Pointer (MSP).
lypinator 0:bb348c97df44 329 \param [in] topOfMainStack Main Stack Pointer value to set
lypinator 0:bb348c97df44 330 */
lypinator 0:bb348c97df44 331 __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
lypinator 0:bb348c97df44 332 {
lypinator 0:bb348c97df44 333 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
lypinator 0:bb348c97df44 334 }
lypinator 0:bb348c97df44 335
lypinator 0:bb348c97df44 336
lypinator 0:bb348c97df44 337 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 338 /**
lypinator 0:bb348c97df44 339 \brief Set Main Stack Pointer (non-secure)
lypinator 0:bb348c97df44 340 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
lypinator 0:bb348c97df44 341 \param [in] topOfMainStack Main Stack Pointer value to set
lypinator 0:bb348c97df44 342 */
lypinator 0:bb348c97df44 343 __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
lypinator 0:bb348c97df44 344 {
lypinator 0:bb348c97df44 345 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
lypinator 0:bb348c97df44 346 }
lypinator 0:bb348c97df44 347 #endif
lypinator 0:bb348c97df44 348
lypinator 0:bb348c97df44 349
lypinator 0:bb348c97df44 350 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 351 /**
lypinator 0:bb348c97df44 352 \brief Get Stack Pointer (non-secure)
lypinator 0:bb348c97df44 353 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
lypinator 0:bb348c97df44 354 \return SP Register value
lypinator 0:bb348c97df44 355 */
lypinator 0:bb348c97df44 356 __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
lypinator 0:bb348c97df44 357 {
lypinator 0:bb348c97df44 358 register uint32_t result;
lypinator 0:bb348c97df44 359
lypinator 0:bb348c97df44 360 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
lypinator 0:bb348c97df44 361 return(result);
lypinator 0:bb348c97df44 362 }
lypinator 0:bb348c97df44 363
lypinator 0:bb348c97df44 364
lypinator 0:bb348c97df44 365 /**
lypinator 0:bb348c97df44 366 \brief Set Stack Pointer (non-secure)
lypinator 0:bb348c97df44 367 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
lypinator 0:bb348c97df44 368 \param [in] topOfStack Stack Pointer value to set
lypinator 0:bb348c97df44 369 */
lypinator 0:bb348c97df44 370 __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
lypinator 0:bb348c97df44 371 {
lypinator 0:bb348c97df44 372 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
lypinator 0:bb348c97df44 373 }
lypinator 0:bb348c97df44 374 #endif
lypinator 0:bb348c97df44 375
lypinator 0:bb348c97df44 376
lypinator 0:bb348c97df44 377 /**
lypinator 0:bb348c97df44 378 \brief Get Priority Mask
lypinator 0:bb348c97df44 379 \details Returns the current state of the priority mask bit from the Priority Mask Register.
lypinator 0:bb348c97df44 380 \return Priority Mask value
lypinator 0:bb348c97df44 381 */
lypinator 0:bb348c97df44 382 __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
lypinator 0:bb348c97df44 383 {
lypinator 0:bb348c97df44 384 uint32_t result;
lypinator 0:bb348c97df44 385
lypinator 0:bb348c97df44 386 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
lypinator 0:bb348c97df44 387 return(result);
lypinator 0:bb348c97df44 388 }
lypinator 0:bb348c97df44 389
lypinator 0:bb348c97df44 390
lypinator 0:bb348c97df44 391 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 392 /**
lypinator 0:bb348c97df44 393 \brief Get Priority Mask (non-secure)
lypinator 0:bb348c97df44 394 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
lypinator 0:bb348c97df44 395 \return Priority Mask value
lypinator 0:bb348c97df44 396 */
lypinator 0:bb348c97df44 397 __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
lypinator 0:bb348c97df44 398 {
lypinator 0:bb348c97df44 399 uint32_t result;
lypinator 0:bb348c97df44 400
lypinator 0:bb348c97df44 401 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
lypinator 0:bb348c97df44 402 return(result);
lypinator 0:bb348c97df44 403 }
lypinator 0:bb348c97df44 404 #endif
lypinator 0:bb348c97df44 405
lypinator 0:bb348c97df44 406
lypinator 0:bb348c97df44 407 /**
lypinator 0:bb348c97df44 408 \brief Set Priority Mask
lypinator 0:bb348c97df44 409 \details Assigns the given value to the Priority Mask Register.
lypinator 0:bb348c97df44 410 \param [in] priMask Priority Mask
lypinator 0:bb348c97df44 411 */
lypinator 0:bb348c97df44 412 __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
lypinator 0:bb348c97df44 413 {
lypinator 0:bb348c97df44 414 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
lypinator 0:bb348c97df44 415 }
lypinator 0:bb348c97df44 416
lypinator 0:bb348c97df44 417
lypinator 0:bb348c97df44 418 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 419 /**
lypinator 0:bb348c97df44 420 \brief Set Priority Mask (non-secure)
lypinator 0:bb348c97df44 421 \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
lypinator 0:bb348c97df44 422 \param [in] priMask Priority Mask
lypinator 0:bb348c97df44 423 */
lypinator 0:bb348c97df44 424 __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
lypinator 0:bb348c97df44 425 {
lypinator 0:bb348c97df44 426 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
lypinator 0:bb348c97df44 427 }
lypinator 0:bb348c97df44 428 #endif
lypinator 0:bb348c97df44 429
lypinator 0:bb348c97df44 430
lypinator 0:bb348c97df44 431 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
lypinator 0:bb348c97df44 432 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 433 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
lypinator 0:bb348c97df44 434 /**
lypinator 0:bb348c97df44 435 \brief Enable FIQ
lypinator 0:bb348c97df44 436 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
lypinator 0:bb348c97df44 437 Can only be executed in Privileged modes.
lypinator 0:bb348c97df44 438 */
lypinator 0:bb348c97df44 439 __STATIC_FORCEINLINE void __enable_fault_irq(void)
lypinator 0:bb348c97df44 440 {
lypinator 0:bb348c97df44 441 __ASM volatile ("cpsie f" : : : "memory");
lypinator 0:bb348c97df44 442 }
lypinator 0:bb348c97df44 443
lypinator 0:bb348c97df44 444
lypinator 0:bb348c97df44 445 /**
lypinator 0:bb348c97df44 446 \brief Disable FIQ
lypinator 0:bb348c97df44 447 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
lypinator 0:bb348c97df44 448 Can only be executed in Privileged modes.
lypinator 0:bb348c97df44 449 */
lypinator 0:bb348c97df44 450 __STATIC_FORCEINLINE void __disable_fault_irq(void)
lypinator 0:bb348c97df44 451 {
lypinator 0:bb348c97df44 452 __ASM volatile ("cpsid f" : : : "memory");
lypinator 0:bb348c97df44 453 }
lypinator 0:bb348c97df44 454
lypinator 0:bb348c97df44 455
lypinator 0:bb348c97df44 456 /**
lypinator 0:bb348c97df44 457 \brief Get Base Priority
lypinator 0:bb348c97df44 458 \details Returns the current value of the Base Priority register.
lypinator 0:bb348c97df44 459 \return Base Priority register value
lypinator 0:bb348c97df44 460 */
lypinator 0:bb348c97df44 461 __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
lypinator 0:bb348c97df44 462 {
lypinator 0:bb348c97df44 463 uint32_t result;
lypinator 0:bb348c97df44 464
lypinator 0:bb348c97df44 465 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
lypinator 0:bb348c97df44 466 return(result);
lypinator 0:bb348c97df44 467 }
lypinator 0:bb348c97df44 468
lypinator 0:bb348c97df44 469
lypinator 0:bb348c97df44 470 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 471 /**
lypinator 0:bb348c97df44 472 \brief Get Base Priority (non-secure)
lypinator 0:bb348c97df44 473 \details Returns the current value of the non-secure Base Priority register when in secure state.
lypinator 0:bb348c97df44 474 \return Base Priority register value
lypinator 0:bb348c97df44 475 */
lypinator 0:bb348c97df44 476 __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
lypinator 0:bb348c97df44 477 {
lypinator 0:bb348c97df44 478 uint32_t result;
lypinator 0:bb348c97df44 479
lypinator 0:bb348c97df44 480 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
lypinator 0:bb348c97df44 481 return(result);
lypinator 0:bb348c97df44 482 }
lypinator 0:bb348c97df44 483 #endif
lypinator 0:bb348c97df44 484
lypinator 0:bb348c97df44 485
lypinator 0:bb348c97df44 486 /**
lypinator 0:bb348c97df44 487 \brief Set Base Priority
lypinator 0:bb348c97df44 488 \details Assigns the given value to the Base Priority register.
lypinator 0:bb348c97df44 489 \param [in] basePri Base Priority value to set
lypinator 0:bb348c97df44 490 */
lypinator 0:bb348c97df44 491 __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
lypinator 0:bb348c97df44 492 {
lypinator 0:bb348c97df44 493 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
lypinator 0:bb348c97df44 494 }
lypinator 0:bb348c97df44 495
lypinator 0:bb348c97df44 496
lypinator 0:bb348c97df44 497 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 498 /**
lypinator 0:bb348c97df44 499 \brief Set Base Priority (non-secure)
lypinator 0:bb348c97df44 500 \details Assigns the given value to the non-secure Base Priority register when in secure state.
lypinator 0:bb348c97df44 501 \param [in] basePri Base Priority value to set
lypinator 0:bb348c97df44 502 */
lypinator 0:bb348c97df44 503 __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
lypinator 0:bb348c97df44 504 {
lypinator 0:bb348c97df44 505 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
lypinator 0:bb348c97df44 506 }
lypinator 0:bb348c97df44 507 #endif
lypinator 0:bb348c97df44 508
lypinator 0:bb348c97df44 509
lypinator 0:bb348c97df44 510 /**
lypinator 0:bb348c97df44 511 \brief Set Base Priority with condition
lypinator 0:bb348c97df44 512 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
lypinator 0:bb348c97df44 513 or the new value increases the BASEPRI priority level.
lypinator 0:bb348c97df44 514 \param [in] basePri Base Priority value to set
lypinator 0:bb348c97df44 515 */
lypinator 0:bb348c97df44 516 __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
lypinator 0:bb348c97df44 517 {
lypinator 0:bb348c97df44 518 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
lypinator 0:bb348c97df44 519 }
lypinator 0:bb348c97df44 520
lypinator 0:bb348c97df44 521
lypinator 0:bb348c97df44 522 /**
lypinator 0:bb348c97df44 523 \brief Get Fault Mask
lypinator 0:bb348c97df44 524 \details Returns the current value of the Fault Mask register.
lypinator 0:bb348c97df44 525 \return Fault Mask register value
lypinator 0:bb348c97df44 526 */
lypinator 0:bb348c97df44 527 __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
lypinator 0:bb348c97df44 528 {
lypinator 0:bb348c97df44 529 uint32_t result;
lypinator 0:bb348c97df44 530
lypinator 0:bb348c97df44 531 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
lypinator 0:bb348c97df44 532 return(result);
lypinator 0:bb348c97df44 533 }
lypinator 0:bb348c97df44 534
lypinator 0:bb348c97df44 535
lypinator 0:bb348c97df44 536 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 537 /**
lypinator 0:bb348c97df44 538 \brief Get Fault Mask (non-secure)
lypinator 0:bb348c97df44 539 \details Returns the current value of the non-secure Fault Mask register when in secure state.
lypinator 0:bb348c97df44 540 \return Fault Mask register value
lypinator 0:bb348c97df44 541 */
lypinator 0:bb348c97df44 542 __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
lypinator 0:bb348c97df44 543 {
lypinator 0:bb348c97df44 544 uint32_t result;
lypinator 0:bb348c97df44 545
lypinator 0:bb348c97df44 546 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
lypinator 0:bb348c97df44 547 return(result);
lypinator 0:bb348c97df44 548 }
lypinator 0:bb348c97df44 549 #endif
lypinator 0:bb348c97df44 550
lypinator 0:bb348c97df44 551
lypinator 0:bb348c97df44 552 /**
lypinator 0:bb348c97df44 553 \brief Set Fault Mask
lypinator 0:bb348c97df44 554 \details Assigns the given value to the Fault Mask register.
lypinator 0:bb348c97df44 555 \param [in] faultMask Fault Mask value to set
lypinator 0:bb348c97df44 556 */
lypinator 0:bb348c97df44 557 __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
lypinator 0:bb348c97df44 558 {
lypinator 0:bb348c97df44 559 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
lypinator 0:bb348c97df44 560 }
lypinator 0:bb348c97df44 561
lypinator 0:bb348c97df44 562
lypinator 0:bb348c97df44 563 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 564 /**
lypinator 0:bb348c97df44 565 \brief Set Fault Mask (non-secure)
lypinator 0:bb348c97df44 566 \details Assigns the given value to the non-secure Fault Mask register when in secure state.
lypinator 0:bb348c97df44 567 \param [in] faultMask Fault Mask value to set
lypinator 0:bb348c97df44 568 */
lypinator 0:bb348c97df44 569 __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
lypinator 0:bb348c97df44 570 {
lypinator 0:bb348c97df44 571 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
lypinator 0:bb348c97df44 572 }
lypinator 0:bb348c97df44 573 #endif
lypinator 0:bb348c97df44 574
lypinator 0:bb348c97df44 575 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
lypinator 0:bb348c97df44 576 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 577 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
lypinator 0:bb348c97df44 578
lypinator 0:bb348c97df44 579
lypinator 0:bb348c97df44 580 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
lypinator 0:bb348c97df44 581 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
lypinator 0:bb348c97df44 582
lypinator 0:bb348c97df44 583 /**
lypinator 0:bb348c97df44 584 \brief Get Process Stack Pointer Limit
lypinator 0:bb348c97df44 585 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
lypinator 0:bb348c97df44 586 Stack Pointer Limit register hence zero is returned always in non-secure
lypinator 0:bb348c97df44 587 mode.
lypinator 0:bb348c97df44 588
lypinator 0:bb348c97df44 589 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
lypinator 0:bb348c97df44 590 \return PSPLIM Register value
lypinator 0:bb348c97df44 591 */
lypinator 0:bb348c97df44 592 __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
lypinator 0:bb348c97df44 593 {
lypinator 0:bb348c97df44 594 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
lypinator 0:bb348c97df44 595 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
lypinator 0:bb348c97df44 596 // without main extensions, the non-secure PSPLIM is RAZ/WI
lypinator 0:bb348c97df44 597 return 0U;
lypinator 0:bb348c97df44 598 #else
lypinator 0:bb348c97df44 599 register uint32_t result;
lypinator 0:bb348c97df44 600 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
lypinator 0:bb348c97df44 601 return result;
lypinator 0:bb348c97df44 602 #endif
lypinator 0:bb348c97df44 603 }
lypinator 0:bb348c97df44 604
lypinator 0:bb348c97df44 605 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 606 /**
lypinator 0:bb348c97df44 607 \brief Get Process Stack Pointer Limit (non-secure)
lypinator 0:bb348c97df44 608 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
lypinator 0:bb348c97df44 609 Stack Pointer Limit register hence zero is returned always.
lypinator 0:bb348c97df44 610
lypinator 0:bb348c97df44 611 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
lypinator 0:bb348c97df44 612 \return PSPLIM Register value
lypinator 0:bb348c97df44 613 */
lypinator 0:bb348c97df44 614 __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
lypinator 0:bb348c97df44 615 {
lypinator 0:bb348c97df44 616 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
lypinator 0:bb348c97df44 617 // without main extensions, the non-secure PSPLIM is RAZ/WI
lypinator 0:bb348c97df44 618 return 0U;
lypinator 0:bb348c97df44 619 #else
lypinator 0:bb348c97df44 620 register uint32_t result;
lypinator 0:bb348c97df44 621 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
lypinator 0:bb348c97df44 622 return result;
lypinator 0:bb348c97df44 623 #endif
lypinator 0:bb348c97df44 624 }
lypinator 0:bb348c97df44 625 #endif
lypinator 0:bb348c97df44 626
lypinator 0:bb348c97df44 627
lypinator 0:bb348c97df44 628 /**
lypinator 0:bb348c97df44 629 \brief Set Process Stack Pointer Limit
lypinator 0:bb348c97df44 630 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
lypinator 0:bb348c97df44 631 Stack Pointer Limit register hence the write is silently ignored in non-secure
lypinator 0:bb348c97df44 632 mode.
lypinator 0:bb348c97df44 633
lypinator 0:bb348c97df44 634 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
lypinator 0:bb348c97df44 635 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
lypinator 0:bb348c97df44 636 */
lypinator 0:bb348c97df44 637 __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
lypinator 0:bb348c97df44 638 {
lypinator 0:bb348c97df44 639 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
lypinator 0:bb348c97df44 640 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
lypinator 0:bb348c97df44 641 // without main extensions, the non-secure PSPLIM is RAZ/WI
lypinator 0:bb348c97df44 642 (void)ProcStackPtrLimit;
lypinator 0:bb348c97df44 643 #else
lypinator 0:bb348c97df44 644 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
lypinator 0:bb348c97df44 645 #endif
lypinator 0:bb348c97df44 646 }
lypinator 0:bb348c97df44 647
lypinator 0:bb348c97df44 648
lypinator 0:bb348c97df44 649 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 650 /**
lypinator 0:bb348c97df44 651 \brief Set Process Stack Pointer (non-secure)
lypinator 0:bb348c97df44 652 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
lypinator 0:bb348c97df44 653 Stack Pointer Limit register hence the write is silently ignored.
lypinator 0:bb348c97df44 654
lypinator 0:bb348c97df44 655 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
lypinator 0:bb348c97df44 656 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
lypinator 0:bb348c97df44 657 */
lypinator 0:bb348c97df44 658 __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
lypinator 0:bb348c97df44 659 {
lypinator 0:bb348c97df44 660 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
lypinator 0:bb348c97df44 661 // without main extensions, the non-secure PSPLIM is RAZ/WI
lypinator 0:bb348c97df44 662 (void)ProcStackPtrLimit;
lypinator 0:bb348c97df44 663 #else
lypinator 0:bb348c97df44 664 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
lypinator 0:bb348c97df44 665 #endif
lypinator 0:bb348c97df44 666 }
lypinator 0:bb348c97df44 667 #endif
lypinator 0:bb348c97df44 668
lypinator 0:bb348c97df44 669
lypinator 0:bb348c97df44 670 /**
lypinator 0:bb348c97df44 671 \brief Get Main Stack Pointer Limit
lypinator 0:bb348c97df44 672 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
lypinator 0:bb348c97df44 673 Stack Pointer Limit register hence zero is returned always in non-secure
lypinator 0:bb348c97df44 674 mode.
lypinator 0:bb348c97df44 675
lypinator 0:bb348c97df44 676 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
lypinator 0:bb348c97df44 677 \return MSPLIM Register value
lypinator 0:bb348c97df44 678 */
lypinator 0:bb348c97df44 679 __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
lypinator 0:bb348c97df44 680 {
lypinator 0:bb348c97df44 681 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
lypinator 0:bb348c97df44 682 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
lypinator 0:bb348c97df44 683 // without main extensions, the non-secure MSPLIM is RAZ/WI
lypinator 0:bb348c97df44 684 return 0U;
lypinator 0:bb348c97df44 685 #else
lypinator 0:bb348c97df44 686 register uint32_t result;
lypinator 0:bb348c97df44 687 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
lypinator 0:bb348c97df44 688 return result;
lypinator 0:bb348c97df44 689 #endif
lypinator 0:bb348c97df44 690 }
lypinator 0:bb348c97df44 691
lypinator 0:bb348c97df44 692
lypinator 0:bb348c97df44 693 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 694 /**
lypinator 0:bb348c97df44 695 \brief Get Main Stack Pointer Limit (non-secure)
lypinator 0:bb348c97df44 696 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
lypinator 0:bb348c97df44 697 Stack Pointer Limit register hence zero is returned always.
lypinator 0:bb348c97df44 698
lypinator 0:bb348c97df44 699 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
lypinator 0:bb348c97df44 700 \return MSPLIM Register value
lypinator 0:bb348c97df44 701 */
lypinator 0:bb348c97df44 702 __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
lypinator 0:bb348c97df44 703 {
lypinator 0:bb348c97df44 704 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
lypinator 0:bb348c97df44 705 // without main extensions, the non-secure MSPLIM is RAZ/WI
lypinator 0:bb348c97df44 706 return 0U;
lypinator 0:bb348c97df44 707 #else
lypinator 0:bb348c97df44 708 register uint32_t result;
lypinator 0:bb348c97df44 709 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
lypinator 0:bb348c97df44 710 return result;
lypinator 0:bb348c97df44 711 #endif
lypinator 0:bb348c97df44 712 }
lypinator 0:bb348c97df44 713 #endif
lypinator 0:bb348c97df44 714
lypinator 0:bb348c97df44 715
lypinator 0:bb348c97df44 716 /**
lypinator 0:bb348c97df44 717 \brief Set Main Stack Pointer Limit
lypinator 0:bb348c97df44 718 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
lypinator 0:bb348c97df44 719 Stack Pointer Limit register hence the write is silently ignored in non-secure
lypinator 0:bb348c97df44 720 mode.
lypinator 0:bb348c97df44 721
lypinator 0:bb348c97df44 722 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
lypinator 0:bb348c97df44 723 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
lypinator 0:bb348c97df44 724 */
lypinator 0:bb348c97df44 725 __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
lypinator 0:bb348c97df44 726 {
lypinator 0:bb348c97df44 727 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
lypinator 0:bb348c97df44 728 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
lypinator 0:bb348c97df44 729 // without main extensions, the non-secure MSPLIM is RAZ/WI
lypinator 0:bb348c97df44 730 (void)MainStackPtrLimit;
lypinator 0:bb348c97df44 731 #else
lypinator 0:bb348c97df44 732 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
lypinator 0:bb348c97df44 733 #endif
lypinator 0:bb348c97df44 734 }
lypinator 0:bb348c97df44 735
lypinator 0:bb348c97df44 736
lypinator 0:bb348c97df44 737 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 738 /**
lypinator 0:bb348c97df44 739 \brief Set Main Stack Pointer Limit (non-secure)
lypinator 0:bb348c97df44 740 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
lypinator 0:bb348c97df44 741 Stack Pointer Limit register hence the write is silently ignored.
lypinator 0:bb348c97df44 742
lypinator 0:bb348c97df44 743 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
lypinator 0:bb348c97df44 744 \param [in] MainStackPtrLimit Main Stack Pointer value to set
lypinator 0:bb348c97df44 745 */
lypinator 0:bb348c97df44 746 __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
lypinator 0:bb348c97df44 747 {
lypinator 0:bb348c97df44 748 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
lypinator 0:bb348c97df44 749 // without main extensions, the non-secure MSPLIM is RAZ/WI
lypinator 0:bb348c97df44 750 (void)MainStackPtrLimit;
lypinator 0:bb348c97df44 751 #else
lypinator 0:bb348c97df44 752 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
lypinator 0:bb348c97df44 753 #endif
lypinator 0:bb348c97df44 754 }
lypinator 0:bb348c97df44 755 #endif
lypinator 0:bb348c97df44 756
lypinator 0:bb348c97df44 757 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
lypinator 0:bb348c97df44 758 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
lypinator 0:bb348c97df44 759
lypinator 0:bb348c97df44 760
lypinator 0:bb348c97df44 761 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 762 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
lypinator 0:bb348c97df44 763
lypinator 0:bb348c97df44 764 /**
lypinator 0:bb348c97df44 765 \brief Get FPSCR
lypinator 0:bb348c97df44 766 \details Returns the current value of the Floating Point Status/Control register.
lypinator 0:bb348c97df44 767 \return Floating Point Status/Control register value
lypinator 0:bb348c97df44 768 */
lypinator 0:bb348c97df44 769 __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
lypinator 0:bb348c97df44 770 {
lypinator 0:bb348c97df44 771 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
lypinator 0:bb348c97df44 772 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
lypinator 0:bb348c97df44 773 #if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
lypinator 0:bb348c97df44 774 /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
lypinator 0:bb348c97df44 775 return __builtin_arm_get_fpscr();
lypinator 0:bb348c97df44 776 #else
lypinator 0:bb348c97df44 777 uint32_t result;
lypinator 0:bb348c97df44 778
lypinator 0:bb348c97df44 779 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
lypinator 0:bb348c97df44 780 return(result);
lypinator 0:bb348c97df44 781 #endif
lypinator 0:bb348c97df44 782 #else
lypinator 0:bb348c97df44 783 return(0U);
lypinator 0:bb348c97df44 784 #endif
lypinator 0:bb348c97df44 785 }
lypinator 0:bb348c97df44 786
lypinator 0:bb348c97df44 787
lypinator 0:bb348c97df44 788 /**
lypinator 0:bb348c97df44 789 \brief Set FPSCR
lypinator 0:bb348c97df44 790 \details Assigns the given value to the Floating Point Status/Control register.
lypinator 0:bb348c97df44 791 \param [in] fpscr Floating Point Status/Control value to set
lypinator 0:bb348c97df44 792 */
lypinator 0:bb348c97df44 793 __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
lypinator 0:bb348c97df44 794 {
lypinator 0:bb348c97df44 795 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
lypinator 0:bb348c97df44 796 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
lypinator 0:bb348c97df44 797 #if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
lypinator 0:bb348c97df44 798 /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
lypinator 0:bb348c97df44 799 __builtin_arm_set_fpscr(fpscr);
lypinator 0:bb348c97df44 800 #else
lypinator 0:bb348c97df44 801 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
lypinator 0:bb348c97df44 802 #endif
lypinator 0:bb348c97df44 803 #else
lypinator 0:bb348c97df44 804 (void)fpscr;
lypinator 0:bb348c97df44 805 #endif
lypinator 0:bb348c97df44 806 }
lypinator 0:bb348c97df44 807
lypinator 0:bb348c97df44 808 #endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 809 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
lypinator 0:bb348c97df44 810
lypinator 0:bb348c97df44 811
lypinator 0:bb348c97df44 812
lypinator 0:bb348c97df44 813 /*@} end of CMSIS_Core_RegAccFunctions */
lypinator 0:bb348c97df44 814
lypinator 0:bb348c97df44 815
lypinator 0:bb348c97df44 816 /* ########################## Core Instruction Access ######################### */
lypinator 0:bb348c97df44 817 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
lypinator 0:bb348c97df44 818 Access to dedicated instructions
lypinator 0:bb348c97df44 819 @{
lypinator 0:bb348c97df44 820 */
lypinator 0:bb348c97df44 821
lypinator 0:bb348c97df44 822 /* Define macros for porting to both thumb1 and thumb2.
lypinator 0:bb348c97df44 823 * For thumb1, use low register (r0-r7), specified by constraint "l"
lypinator 0:bb348c97df44 824 * Otherwise, use general registers, specified by constraint "r" */
lypinator 0:bb348c97df44 825 #if defined (__thumb__) && !defined (__thumb2__)
lypinator 0:bb348c97df44 826 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
lypinator 0:bb348c97df44 827 #define __CMSIS_GCC_RW_REG(r) "+l" (r)
lypinator 0:bb348c97df44 828 #define __CMSIS_GCC_USE_REG(r) "l" (r)
lypinator 0:bb348c97df44 829 #else
lypinator 0:bb348c97df44 830 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
lypinator 0:bb348c97df44 831 #define __CMSIS_GCC_RW_REG(r) "+r" (r)
lypinator 0:bb348c97df44 832 #define __CMSIS_GCC_USE_REG(r) "r" (r)
lypinator 0:bb348c97df44 833 #endif
lypinator 0:bb348c97df44 834
lypinator 0:bb348c97df44 835 /**
lypinator 0:bb348c97df44 836 \brief No Operation
lypinator 0:bb348c97df44 837 \details No Operation does nothing. This instruction can be used for code alignment purposes.
lypinator 0:bb348c97df44 838 */
lypinator 0:bb348c97df44 839 #define __NOP() __ASM volatile ("nop")
lypinator 0:bb348c97df44 840
lypinator 0:bb348c97df44 841 /**
lypinator 0:bb348c97df44 842 \brief Wait For Interrupt
lypinator 0:bb348c97df44 843 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
lypinator 0:bb348c97df44 844 */
lypinator 0:bb348c97df44 845 #define __WFI() __ASM volatile ("wfi")
lypinator 0:bb348c97df44 846
lypinator 0:bb348c97df44 847
lypinator 0:bb348c97df44 848 /**
lypinator 0:bb348c97df44 849 \brief Wait For Event
lypinator 0:bb348c97df44 850 \details Wait For Event is a hint instruction that permits the processor to enter
lypinator 0:bb348c97df44 851 a low-power state until one of a number of events occurs.
lypinator 0:bb348c97df44 852 */
lypinator 0:bb348c97df44 853 #define __WFE() __ASM volatile ("wfe")
lypinator 0:bb348c97df44 854
lypinator 0:bb348c97df44 855
lypinator 0:bb348c97df44 856 /**
lypinator 0:bb348c97df44 857 \brief Send Event
lypinator 0:bb348c97df44 858 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
lypinator 0:bb348c97df44 859 */
lypinator 0:bb348c97df44 860 #define __SEV() __ASM volatile ("sev")
lypinator 0:bb348c97df44 861
lypinator 0:bb348c97df44 862
lypinator 0:bb348c97df44 863 /**
lypinator 0:bb348c97df44 864 \brief Instruction Synchronization Barrier
lypinator 0:bb348c97df44 865 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
lypinator 0:bb348c97df44 866 so that all instructions following the ISB are fetched from cache or memory,
lypinator 0:bb348c97df44 867 after the instruction has been completed.
lypinator 0:bb348c97df44 868 */
lypinator 0:bb348c97df44 869 __STATIC_FORCEINLINE void __ISB(void)
lypinator 0:bb348c97df44 870 {
lypinator 0:bb348c97df44 871 __ASM volatile ("isb 0xF":::"memory");
lypinator 0:bb348c97df44 872 }
lypinator 0:bb348c97df44 873
lypinator 0:bb348c97df44 874
lypinator 0:bb348c97df44 875 /**
lypinator 0:bb348c97df44 876 \brief Data Synchronization Barrier
lypinator 0:bb348c97df44 877 \details Acts as a special kind of Data Memory Barrier.
lypinator 0:bb348c97df44 878 It completes when all explicit memory accesses before this instruction complete.
lypinator 0:bb348c97df44 879 */
lypinator 0:bb348c97df44 880 __STATIC_FORCEINLINE void __DSB(void)
lypinator 0:bb348c97df44 881 {
lypinator 0:bb348c97df44 882 __ASM volatile ("dsb 0xF":::"memory");
lypinator 0:bb348c97df44 883 }
lypinator 0:bb348c97df44 884
lypinator 0:bb348c97df44 885
lypinator 0:bb348c97df44 886 /**
lypinator 0:bb348c97df44 887 \brief Data Memory Barrier
lypinator 0:bb348c97df44 888 \details Ensures the apparent order of the explicit memory operations before
lypinator 0:bb348c97df44 889 and after the instruction, without ensuring their completion.
lypinator 0:bb348c97df44 890 */
lypinator 0:bb348c97df44 891 __STATIC_FORCEINLINE void __DMB(void)
lypinator 0:bb348c97df44 892 {
lypinator 0:bb348c97df44 893 __ASM volatile ("dmb 0xF":::"memory");
lypinator 0:bb348c97df44 894 }
lypinator 0:bb348c97df44 895
lypinator 0:bb348c97df44 896
lypinator 0:bb348c97df44 897 /**
lypinator 0:bb348c97df44 898 \brief Reverse byte order (32 bit)
lypinator 0:bb348c97df44 899 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
lypinator 0:bb348c97df44 900 \param [in] value Value to reverse
lypinator 0:bb348c97df44 901 \return Reversed value
lypinator 0:bb348c97df44 902 */
lypinator 0:bb348c97df44 903 __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
lypinator 0:bb348c97df44 904 {
lypinator 0:bb348c97df44 905 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
lypinator 0:bb348c97df44 906 return __builtin_bswap32(value);
lypinator 0:bb348c97df44 907 #else
lypinator 0:bb348c97df44 908 uint32_t result;
lypinator 0:bb348c97df44 909
lypinator 0:bb348c97df44 910 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
lypinator 0:bb348c97df44 911 return result;
lypinator 0:bb348c97df44 912 #endif
lypinator 0:bb348c97df44 913 }
lypinator 0:bb348c97df44 914
lypinator 0:bb348c97df44 915
lypinator 0:bb348c97df44 916 /**
lypinator 0:bb348c97df44 917 \brief Reverse byte order (16 bit)
lypinator 0:bb348c97df44 918 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
lypinator 0:bb348c97df44 919 \param [in] value Value to reverse
lypinator 0:bb348c97df44 920 \return Reversed value
lypinator 0:bb348c97df44 921 */
lypinator 0:bb348c97df44 922 __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
lypinator 0:bb348c97df44 923 {
lypinator 0:bb348c97df44 924 uint32_t result;
lypinator 0:bb348c97df44 925
lypinator 0:bb348c97df44 926 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
lypinator 0:bb348c97df44 927 return result;
lypinator 0:bb348c97df44 928 }
lypinator 0:bb348c97df44 929
lypinator 0:bb348c97df44 930
lypinator 0:bb348c97df44 931 /**
lypinator 0:bb348c97df44 932 \brief Reverse byte order (16 bit)
lypinator 0:bb348c97df44 933 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
lypinator 0:bb348c97df44 934 \param [in] value Value to reverse
lypinator 0:bb348c97df44 935 \return Reversed value
lypinator 0:bb348c97df44 936 */
lypinator 0:bb348c97df44 937 __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
lypinator 0:bb348c97df44 938 {
lypinator 0:bb348c97df44 939 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
lypinator 0:bb348c97df44 940 return (int16_t)__builtin_bswap16(value);
lypinator 0:bb348c97df44 941 #else
lypinator 0:bb348c97df44 942 int16_t result;
lypinator 0:bb348c97df44 943
lypinator 0:bb348c97df44 944 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
lypinator 0:bb348c97df44 945 return result;
lypinator 0:bb348c97df44 946 #endif
lypinator 0:bb348c97df44 947 }
lypinator 0:bb348c97df44 948
lypinator 0:bb348c97df44 949
lypinator 0:bb348c97df44 950 /**
lypinator 0:bb348c97df44 951 \brief Rotate Right in unsigned value (32 bit)
lypinator 0:bb348c97df44 952 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
lypinator 0:bb348c97df44 953 \param [in] op1 Value to rotate
lypinator 0:bb348c97df44 954 \param [in] op2 Number of Bits to rotate
lypinator 0:bb348c97df44 955 \return Rotated value
lypinator 0:bb348c97df44 956 */
lypinator 0:bb348c97df44 957 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 958 {
lypinator 0:bb348c97df44 959 op2 %= 32U;
lypinator 0:bb348c97df44 960 if (op2 == 0U)
lypinator 0:bb348c97df44 961 {
lypinator 0:bb348c97df44 962 return op1;
lypinator 0:bb348c97df44 963 }
lypinator 0:bb348c97df44 964 return (op1 >> op2) | (op1 << (32U - op2));
lypinator 0:bb348c97df44 965 }
lypinator 0:bb348c97df44 966
lypinator 0:bb348c97df44 967
lypinator 0:bb348c97df44 968 /**
lypinator 0:bb348c97df44 969 \brief Breakpoint
lypinator 0:bb348c97df44 970 \details Causes the processor to enter Debug state.
lypinator 0:bb348c97df44 971 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
lypinator 0:bb348c97df44 972 \param [in] value is ignored by the processor.
lypinator 0:bb348c97df44 973 If required, a debugger can use it to store additional information about the breakpoint.
lypinator 0:bb348c97df44 974 */
lypinator 0:bb348c97df44 975 #define __BKPT(value) __ASM volatile ("bkpt "#value)
lypinator 0:bb348c97df44 976
lypinator 0:bb348c97df44 977
lypinator 0:bb348c97df44 978 /**
lypinator 0:bb348c97df44 979 \brief Reverse bit order of value
lypinator 0:bb348c97df44 980 \details Reverses the bit order of the given value.
lypinator 0:bb348c97df44 981 \param [in] value Value to reverse
lypinator 0:bb348c97df44 982 \return Reversed value
lypinator 0:bb348c97df44 983 */
lypinator 0:bb348c97df44 984 __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
lypinator 0:bb348c97df44 985 {
lypinator 0:bb348c97df44 986 uint32_t result;
lypinator 0:bb348c97df44 987
lypinator 0:bb348c97df44 988 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
lypinator 0:bb348c97df44 989 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 990 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
lypinator 0:bb348c97df44 991 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
lypinator 0:bb348c97df44 992 #else
lypinator 0:bb348c97df44 993 uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
lypinator 0:bb348c97df44 994
lypinator 0:bb348c97df44 995 result = value; /* r will be reversed bits of v; first get LSB of v */
lypinator 0:bb348c97df44 996 for (value >>= 1U; value != 0U; value >>= 1U)
lypinator 0:bb348c97df44 997 {
lypinator 0:bb348c97df44 998 result <<= 1U;
lypinator 0:bb348c97df44 999 result |= value & 1U;
lypinator 0:bb348c97df44 1000 s--;
lypinator 0:bb348c97df44 1001 }
lypinator 0:bb348c97df44 1002 result <<= s; /* shift when v's highest bits are zero */
lypinator 0:bb348c97df44 1003 #endif
lypinator 0:bb348c97df44 1004 return result;
lypinator 0:bb348c97df44 1005 }
lypinator 0:bb348c97df44 1006
lypinator 0:bb348c97df44 1007
lypinator 0:bb348c97df44 1008 /**
lypinator 0:bb348c97df44 1009 \brief Count leading zeros
lypinator 0:bb348c97df44 1010 \details Counts the number of leading zeros of a data value.
lypinator 0:bb348c97df44 1011 \param [in] value Value to count the leading zeros
lypinator 0:bb348c97df44 1012 \return number of leading zeros in value
lypinator 0:bb348c97df44 1013 */
lypinator 0:bb348c97df44 1014 #define __CLZ (uint8_t)__builtin_clz
lypinator 0:bb348c97df44 1015
lypinator 0:bb348c97df44 1016
lypinator 0:bb348c97df44 1017 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
lypinator 0:bb348c97df44 1018 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 1019 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
lypinator 0:bb348c97df44 1020 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
lypinator 0:bb348c97df44 1021 /**
lypinator 0:bb348c97df44 1022 \brief LDR Exclusive (8 bit)
lypinator 0:bb348c97df44 1023 \details Executes a exclusive LDR instruction for 8 bit value.
lypinator 0:bb348c97df44 1024 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1025 \return value of type uint8_t at (*ptr)
lypinator 0:bb348c97df44 1026 */
lypinator 0:bb348c97df44 1027 __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
lypinator 0:bb348c97df44 1028 {
lypinator 0:bb348c97df44 1029 uint32_t result;
lypinator 0:bb348c97df44 1030
lypinator 0:bb348c97df44 1031 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
lypinator 0:bb348c97df44 1032 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
lypinator 0:bb348c97df44 1033 #else
lypinator 0:bb348c97df44 1034 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
lypinator 0:bb348c97df44 1035 accepted by assembler. So has to use following less efficient pattern.
lypinator 0:bb348c97df44 1036 */
lypinator 0:bb348c97df44 1037 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
lypinator 0:bb348c97df44 1038 #endif
lypinator 0:bb348c97df44 1039 return ((uint8_t) result); /* Add explicit type cast here */
lypinator 0:bb348c97df44 1040 }
lypinator 0:bb348c97df44 1041
lypinator 0:bb348c97df44 1042
lypinator 0:bb348c97df44 1043 /**
lypinator 0:bb348c97df44 1044 \brief LDR Exclusive (16 bit)
lypinator 0:bb348c97df44 1045 \details Executes a exclusive LDR instruction for 16 bit values.
lypinator 0:bb348c97df44 1046 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1047 \return value of type uint16_t at (*ptr)
lypinator 0:bb348c97df44 1048 */
lypinator 0:bb348c97df44 1049 __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
lypinator 0:bb348c97df44 1050 {
lypinator 0:bb348c97df44 1051 uint32_t result;
lypinator 0:bb348c97df44 1052
lypinator 0:bb348c97df44 1053 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
lypinator 0:bb348c97df44 1054 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
lypinator 0:bb348c97df44 1055 #else
lypinator 0:bb348c97df44 1056 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
lypinator 0:bb348c97df44 1057 accepted by assembler. So has to use following less efficient pattern.
lypinator 0:bb348c97df44 1058 */
lypinator 0:bb348c97df44 1059 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
lypinator 0:bb348c97df44 1060 #endif
lypinator 0:bb348c97df44 1061 return ((uint16_t) result); /* Add explicit type cast here */
lypinator 0:bb348c97df44 1062 }
lypinator 0:bb348c97df44 1063
lypinator 0:bb348c97df44 1064
lypinator 0:bb348c97df44 1065 /**
lypinator 0:bb348c97df44 1066 \brief LDR Exclusive (32 bit)
lypinator 0:bb348c97df44 1067 \details Executes a exclusive LDR instruction for 32 bit values.
lypinator 0:bb348c97df44 1068 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1069 \return value of type uint32_t at (*ptr)
lypinator 0:bb348c97df44 1070 */
lypinator 0:bb348c97df44 1071 __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
lypinator 0:bb348c97df44 1072 {
lypinator 0:bb348c97df44 1073 uint32_t result;
lypinator 0:bb348c97df44 1074
lypinator 0:bb348c97df44 1075 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
lypinator 0:bb348c97df44 1076 return(result);
lypinator 0:bb348c97df44 1077 }
lypinator 0:bb348c97df44 1078
lypinator 0:bb348c97df44 1079
lypinator 0:bb348c97df44 1080 /**
lypinator 0:bb348c97df44 1081 \brief STR Exclusive (8 bit)
lypinator 0:bb348c97df44 1082 \details Executes a exclusive STR instruction for 8 bit values.
lypinator 0:bb348c97df44 1083 \param [in] value Value to store
lypinator 0:bb348c97df44 1084 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1085 \return 0 Function succeeded
lypinator 0:bb348c97df44 1086 \return 1 Function failed
lypinator 0:bb348c97df44 1087 */
lypinator 0:bb348c97df44 1088 __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
lypinator 0:bb348c97df44 1089 {
lypinator 0:bb348c97df44 1090 uint32_t result;
lypinator 0:bb348c97df44 1091
lypinator 0:bb348c97df44 1092 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
lypinator 0:bb348c97df44 1093 return(result);
lypinator 0:bb348c97df44 1094 }
lypinator 0:bb348c97df44 1095
lypinator 0:bb348c97df44 1096
lypinator 0:bb348c97df44 1097 /**
lypinator 0:bb348c97df44 1098 \brief STR Exclusive (16 bit)
lypinator 0:bb348c97df44 1099 \details Executes a exclusive STR instruction for 16 bit values.
lypinator 0:bb348c97df44 1100 \param [in] value Value to store
lypinator 0:bb348c97df44 1101 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1102 \return 0 Function succeeded
lypinator 0:bb348c97df44 1103 \return 1 Function failed
lypinator 0:bb348c97df44 1104 */
lypinator 0:bb348c97df44 1105 __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
lypinator 0:bb348c97df44 1106 {
lypinator 0:bb348c97df44 1107 uint32_t result;
lypinator 0:bb348c97df44 1108
lypinator 0:bb348c97df44 1109 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
lypinator 0:bb348c97df44 1110 return(result);
lypinator 0:bb348c97df44 1111 }
lypinator 0:bb348c97df44 1112
lypinator 0:bb348c97df44 1113
lypinator 0:bb348c97df44 1114 /**
lypinator 0:bb348c97df44 1115 \brief STR Exclusive (32 bit)
lypinator 0:bb348c97df44 1116 \details Executes a exclusive STR instruction for 32 bit values.
lypinator 0:bb348c97df44 1117 \param [in] value Value to store
lypinator 0:bb348c97df44 1118 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1119 \return 0 Function succeeded
lypinator 0:bb348c97df44 1120 \return 1 Function failed
lypinator 0:bb348c97df44 1121 */
lypinator 0:bb348c97df44 1122 __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
lypinator 0:bb348c97df44 1123 {
lypinator 0:bb348c97df44 1124 uint32_t result;
lypinator 0:bb348c97df44 1125
lypinator 0:bb348c97df44 1126 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
lypinator 0:bb348c97df44 1127 return(result);
lypinator 0:bb348c97df44 1128 }
lypinator 0:bb348c97df44 1129
lypinator 0:bb348c97df44 1130
lypinator 0:bb348c97df44 1131 /**
lypinator 0:bb348c97df44 1132 \brief Remove the exclusive lock
lypinator 0:bb348c97df44 1133 \details Removes the exclusive lock which is created by LDREX.
lypinator 0:bb348c97df44 1134 */
lypinator 0:bb348c97df44 1135 __STATIC_FORCEINLINE void __CLREX(void)
lypinator 0:bb348c97df44 1136 {
lypinator 0:bb348c97df44 1137 __ASM volatile ("clrex" ::: "memory");
lypinator 0:bb348c97df44 1138 }
lypinator 0:bb348c97df44 1139
lypinator 0:bb348c97df44 1140 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
lypinator 0:bb348c97df44 1141 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 1142 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
lypinator 0:bb348c97df44 1143 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
lypinator 0:bb348c97df44 1144
lypinator 0:bb348c97df44 1145
lypinator 0:bb348c97df44 1146 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
lypinator 0:bb348c97df44 1147 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 1148 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
lypinator 0:bb348c97df44 1149 /**
lypinator 0:bb348c97df44 1150 \brief Signed Saturate
lypinator 0:bb348c97df44 1151 \details Saturates a signed value.
lypinator 0:bb348c97df44 1152 \param [in] ARG1 Value to be saturated
lypinator 0:bb348c97df44 1153 \param [in] ARG2 Bit position to saturate to (1..32)
lypinator 0:bb348c97df44 1154 \return Saturated value
lypinator 0:bb348c97df44 1155 */
lypinator 0:bb348c97df44 1156 #define __SSAT(ARG1,ARG2) \
lypinator 0:bb348c97df44 1157 __extension__ \
lypinator 0:bb348c97df44 1158 ({ \
lypinator 0:bb348c97df44 1159 int32_t __RES, __ARG1 = (ARG1); \
lypinator 0:bb348c97df44 1160 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
lypinator 0:bb348c97df44 1161 __RES; \
lypinator 0:bb348c97df44 1162 })
lypinator 0:bb348c97df44 1163
lypinator 0:bb348c97df44 1164
lypinator 0:bb348c97df44 1165 /**
lypinator 0:bb348c97df44 1166 \brief Unsigned Saturate
lypinator 0:bb348c97df44 1167 \details Saturates an unsigned value.
lypinator 0:bb348c97df44 1168 \param [in] ARG1 Value to be saturated
lypinator 0:bb348c97df44 1169 \param [in] ARG2 Bit position to saturate to (0..31)
lypinator 0:bb348c97df44 1170 \return Saturated value
lypinator 0:bb348c97df44 1171 */
lypinator 0:bb348c97df44 1172 #define __USAT(ARG1,ARG2) \
lypinator 0:bb348c97df44 1173 __extension__ \
lypinator 0:bb348c97df44 1174 ({ \
lypinator 0:bb348c97df44 1175 uint32_t __RES, __ARG1 = (ARG1); \
lypinator 0:bb348c97df44 1176 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
lypinator 0:bb348c97df44 1177 __RES; \
lypinator 0:bb348c97df44 1178 })
lypinator 0:bb348c97df44 1179
lypinator 0:bb348c97df44 1180
lypinator 0:bb348c97df44 1181 /**
lypinator 0:bb348c97df44 1182 \brief Rotate Right with Extend (32 bit)
lypinator 0:bb348c97df44 1183 \details Moves each bit of a bitstring right by one bit.
lypinator 0:bb348c97df44 1184 The carry input is shifted in at the left end of the bitstring.
lypinator 0:bb348c97df44 1185 \param [in] value Value to rotate
lypinator 0:bb348c97df44 1186 \return Rotated value
lypinator 0:bb348c97df44 1187 */
lypinator 0:bb348c97df44 1188 __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
lypinator 0:bb348c97df44 1189 {
lypinator 0:bb348c97df44 1190 uint32_t result;
lypinator 0:bb348c97df44 1191
lypinator 0:bb348c97df44 1192 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
lypinator 0:bb348c97df44 1193 return(result);
lypinator 0:bb348c97df44 1194 }
lypinator 0:bb348c97df44 1195
lypinator 0:bb348c97df44 1196
lypinator 0:bb348c97df44 1197 /**
lypinator 0:bb348c97df44 1198 \brief LDRT Unprivileged (8 bit)
lypinator 0:bb348c97df44 1199 \details Executes a Unprivileged LDRT instruction for 8 bit value.
lypinator 0:bb348c97df44 1200 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1201 \return value of type uint8_t at (*ptr)
lypinator 0:bb348c97df44 1202 */
lypinator 0:bb348c97df44 1203 __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
lypinator 0:bb348c97df44 1204 {
lypinator 0:bb348c97df44 1205 uint32_t result;
lypinator 0:bb348c97df44 1206
lypinator 0:bb348c97df44 1207 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
lypinator 0:bb348c97df44 1208 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
lypinator 0:bb348c97df44 1209 #else
lypinator 0:bb348c97df44 1210 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
lypinator 0:bb348c97df44 1211 accepted by assembler. So has to use following less efficient pattern.
lypinator 0:bb348c97df44 1212 */
lypinator 0:bb348c97df44 1213 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
lypinator 0:bb348c97df44 1214 #endif
lypinator 0:bb348c97df44 1215 return ((uint8_t) result); /* Add explicit type cast here */
lypinator 0:bb348c97df44 1216 }
lypinator 0:bb348c97df44 1217
lypinator 0:bb348c97df44 1218
lypinator 0:bb348c97df44 1219 /**
lypinator 0:bb348c97df44 1220 \brief LDRT Unprivileged (16 bit)
lypinator 0:bb348c97df44 1221 \details Executes a Unprivileged LDRT instruction for 16 bit values.
lypinator 0:bb348c97df44 1222 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1223 \return value of type uint16_t at (*ptr)
lypinator 0:bb348c97df44 1224 */
lypinator 0:bb348c97df44 1225 __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
lypinator 0:bb348c97df44 1226 {
lypinator 0:bb348c97df44 1227 uint32_t result;
lypinator 0:bb348c97df44 1228
lypinator 0:bb348c97df44 1229 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
lypinator 0:bb348c97df44 1230 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
lypinator 0:bb348c97df44 1231 #else
lypinator 0:bb348c97df44 1232 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
lypinator 0:bb348c97df44 1233 accepted by assembler. So has to use following less efficient pattern.
lypinator 0:bb348c97df44 1234 */
lypinator 0:bb348c97df44 1235 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
lypinator 0:bb348c97df44 1236 #endif
lypinator 0:bb348c97df44 1237 return ((uint16_t) result); /* Add explicit type cast here */
lypinator 0:bb348c97df44 1238 }
lypinator 0:bb348c97df44 1239
lypinator 0:bb348c97df44 1240
lypinator 0:bb348c97df44 1241 /**
lypinator 0:bb348c97df44 1242 \brief LDRT Unprivileged (32 bit)
lypinator 0:bb348c97df44 1243 \details Executes a Unprivileged LDRT instruction for 32 bit values.
lypinator 0:bb348c97df44 1244 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1245 \return value of type uint32_t at (*ptr)
lypinator 0:bb348c97df44 1246 */
lypinator 0:bb348c97df44 1247 __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
lypinator 0:bb348c97df44 1248 {
lypinator 0:bb348c97df44 1249 uint32_t result;
lypinator 0:bb348c97df44 1250
lypinator 0:bb348c97df44 1251 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
lypinator 0:bb348c97df44 1252 return(result);
lypinator 0:bb348c97df44 1253 }
lypinator 0:bb348c97df44 1254
lypinator 0:bb348c97df44 1255
lypinator 0:bb348c97df44 1256 /**
lypinator 0:bb348c97df44 1257 \brief STRT Unprivileged (8 bit)
lypinator 0:bb348c97df44 1258 \details Executes a Unprivileged STRT instruction for 8 bit values.
lypinator 0:bb348c97df44 1259 \param [in] value Value to store
lypinator 0:bb348c97df44 1260 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1261 */
lypinator 0:bb348c97df44 1262 __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
lypinator 0:bb348c97df44 1263 {
lypinator 0:bb348c97df44 1264 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
lypinator 0:bb348c97df44 1265 }
lypinator 0:bb348c97df44 1266
lypinator 0:bb348c97df44 1267
lypinator 0:bb348c97df44 1268 /**
lypinator 0:bb348c97df44 1269 \brief STRT Unprivileged (16 bit)
lypinator 0:bb348c97df44 1270 \details Executes a Unprivileged STRT instruction for 16 bit values.
lypinator 0:bb348c97df44 1271 \param [in] value Value to store
lypinator 0:bb348c97df44 1272 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1273 */
lypinator 0:bb348c97df44 1274 __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
lypinator 0:bb348c97df44 1275 {
lypinator 0:bb348c97df44 1276 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
lypinator 0:bb348c97df44 1277 }
lypinator 0:bb348c97df44 1278
lypinator 0:bb348c97df44 1279
lypinator 0:bb348c97df44 1280 /**
lypinator 0:bb348c97df44 1281 \brief STRT Unprivileged (32 bit)
lypinator 0:bb348c97df44 1282 \details Executes a Unprivileged STRT instruction for 32 bit values.
lypinator 0:bb348c97df44 1283 \param [in] value Value to store
lypinator 0:bb348c97df44 1284 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1285 */
lypinator 0:bb348c97df44 1286 __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
lypinator 0:bb348c97df44 1287 {
lypinator 0:bb348c97df44 1288 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
lypinator 0:bb348c97df44 1289 }
lypinator 0:bb348c97df44 1290
lypinator 0:bb348c97df44 1291 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
lypinator 0:bb348c97df44 1292 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 1293 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
lypinator 0:bb348c97df44 1294
lypinator 0:bb348c97df44 1295 /**
lypinator 0:bb348c97df44 1296 \brief Signed Saturate
lypinator 0:bb348c97df44 1297 \details Saturates a signed value.
lypinator 0:bb348c97df44 1298 \param [in] value Value to be saturated
lypinator 0:bb348c97df44 1299 \param [in] sat Bit position to saturate to (1..32)
lypinator 0:bb348c97df44 1300 \return Saturated value
lypinator 0:bb348c97df44 1301 */
lypinator 0:bb348c97df44 1302 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
lypinator 0:bb348c97df44 1303 {
lypinator 0:bb348c97df44 1304 if ((sat >= 1U) && (sat <= 32U))
lypinator 0:bb348c97df44 1305 {
lypinator 0:bb348c97df44 1306 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
lypinator 0:bb348c97df44 1307 const int32_t min = -1 - max ;
lypinator 0:bb348c97df44 1308 if (val > max)
lypinator 0:bb348c97df44 1309 {
lypinator 0:bb348c97df44 1310 return max;
lypinator 0:bb348c97df44 1311 }
lypinator 0:bb348c97df44 1312 else if (val < min)
lypinator 0:bb348c97df44 1313 {
lypinator 0:bb348c97df44 1314 return min;
lypinator 0:bb348c97df44 1315 }
lypinator 0:bb348c97df44 1316 }
lypinator 0:bb348c97df44 1317 return val;
lypinator 0:bb348c97df44 1318 }
lypinator 0:bb348c97df44 1319
lypinator 0:bb348c97df44 1320 /**
lypinator 0:bb348c97df44 1321 \brief Unsigned Saturate
lypinator 0:bb348c97df44 1322 \details Saturates an unsigned value.
lypinator 0:bb348c97df44 1323 \param [in] value Value to be saturated
lypinator 0:bb348c97df44 1324 \param [in] sat Bit position to saturate to (0..31)
lypinator 0:bb348c97df44 1325 \return Saturated value
lypinator 0:bb348c97df44 1326 */
lypinator 0:bb348c97df44 1327 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
lypinator 0:bb348c97df44 1328 {
lypinator 0:bb348c97df44 1329 if (sat <= 31U)
lypinator 0:bb348c97df44 1330 {
lypinator 0:bb348c97df44 1331 const uint32_t max = ((1U << sat) - 1U);
lypinator 0:bb348c97df44 1332 if (val > (int32_t)max)
lypinator 0:bb348c97df44 1333 {
lypinator 0:bb348c97df44 1334 return max;
lypinator 0:bb348c97df44 1335 }
lypinator 0:bb348c97df44 1336 else if (val < 0)
lypinator 0:bb348c97df44 1337 {
lypinator 0:bb348c97df44 1338 return 0U;
lypinator 0:bb348c97df44 1339 }
lypinator 0:bb348c97df44 1340 }
lypinator 0:bb348c97df44 1341 return (uint32_t)val;
lypinator 0:bb348c97df44 1342 }
lypinator 0:bb348c97df44 1343
lypinator 0:bb348c97df44 1344 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
lypinator 0:bb348c97df44 1345 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 1346 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
lypinator 0:bb348c97df44 1347
lypinator 0:bb348c97df44 1348
lypinator 0:bb348c97df44 1349 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
lypinator 0:bb348c97df44 1350 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
lypinator 0:bb348c97df44 1351 /**
lypinator 0:bb348c97df44 1352 \brief Load-Acquire (8 bit)
lypinator 0:bb348c97df44 1353 \details Executes a LDAB instruction for 8 bit value.
lypinator 0:bb348c97df44 1354 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1355 \return value of type uint8_t at (*ptr)
lypinator 0:bb348c97df44 1356 */
lypinator 0:bb348c97df44 1357 __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
lypinator 0:bb348c97df44 1358 {
lypinator 0:bb348c97df44 1359 uint32_t result;
lypinator 0:bb348c97df44 1360
lypinator 0:bb348c97df44 1361 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
lypinator 0:bb348c97df44 1362 return ((uint8_t) result);
lypinator 0:bb348c97df44 1363 }
lypinator 0:bb348c97df44 1364
lypinator 0:bb348c97df44 1365
lypinator 0:bb348c97df44 1366 /**
lypinator 0:bb348c97df44 1367 \brief Load-Acquire (16 bit)
lypinator 0:bb348c97df44 1368 \details Executes a LDAH instruction for 16 bit values.
lypinator 0:bb348c97df44 1369 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1370 \return value of type uint16_t at (*ptr)
lypinator 0:bb348c97df44 1371 */
lypinator 0:bb348c97df44 1372 __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
lypinator 0:bb348c97df44 1373 {
lypinator 0:bb348c97df44 1374 uint32_t result;
lypinator 0:bb348c97df44 1375
lypinator 0:bb348c97df44 1376 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
lypinator 0:bb348c97df44 1377 return ((uint16_t) result);
lypinator 0:bb348c97df44 1378 }
lypinator 0:bb348c97df44 1379
lypinator 0:bb348c97df44 1380
lypinator 0:bb348c97df44 1381 /**
lypinator 0:bb348c97df44 1382 \brief Load-Acquire (32 bit)
lypinator 0:bb348c97df44 1383 \details Executes a LDA instruction for 32 bit values.
lypinator 0:bb348c97df44 1384 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1385 \return value of type uint32_t at (*ptr)
lypinator 0:bb348c97df44 1386 */
lypinator 0:bb348c97df44 1387 __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
lypinator 0:bb348c97df44 1388 {
lypinator 0:bb348c97df44 1389 uint32_t result;
lypinator 0:bb348c97df44 1390
lypinator 0:bb348c97df44 1391 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
lypinator 0:bb348c97df44 1392 return(result);
lypinator 0:bb348c97df44 1393 }
lypinator 0:bb348c97df44 1394
lypinator 0:bb348c97df44 1395
lypinator 0:bb348c97df44 1396 /**
lypinator 0:bb348c97df44 1397 \brief Store-Release (8 bit)
lypinator 0:bb348c97df44 1398 \details Executes a STLB instruction for 8 bit values.
lypinator 0:bb348c97df44 1399 \param [in] value Value to store
lypinator 0:bb348c97df44 1400 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1401 */
lypinator 0:bb348c97df44 1402 __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
lypinator 0:bb348c97df44 1403 {
lypinator 0:bb348c97df44 1404 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
lypinator 0:bb348c97df44 1405 }
lypinator 0:bb348c97df44 1406
lypinator 0:bb348c97df44 1407
lypinator 0:bb348c97df44 1408 /**
lypinator 0:bb348c97df44 1409 \brief Store-Release (16 bit)
lypinator 0:bb348c97df44 1410 \details Executes a STLH instruction for 16 bit values.
lypinator 0:bb348c97df44 1411 \param [in] value Value to store
lypinator 0:bb348c97df44 1412 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1413 */
lypinator 0:bb348c97df44 1414 __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
lypinator 0:bb348c97df44 1415 {
lypinator 0:bb348c97df44 1416 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
lypinator 0:bb348c97df44 1417 }
lypinator 0:bb348c97df44 1418
lypinator 0:bb348c97df44 1419
lypinator 0:bb348c97df44 1420 /**
lypinator 0:bb348c97df44 1421 \brief Store-Release (32 bit)
lypinator 0:bb348c97df44 1422 \details Executes a STL instruction for 32 bit values.
lypinator 0:bb348c97df44 1423 \param [in] value Value to store
lypinator 0:bb348c97df44 1424 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1425 */
lypinator 0:bb348c97df44 1426 __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
lypinator 0:bb348c97df44 1427 {
lypinator 0:bb348c97df44 1428 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
lypinator 0:bb348c97df44 1429 }
lypinator 0:bb348c97df44 1430
lypinator 0:bb348c97df44 1431
lypinator 0:bb348c97df44 1432 /**
lypinator 0:bb348c97df44 1433 \brief Load-Acquire Exclusive (8 bit)
lypinator 0:bb348c97df44 1434 \details Executes a LDAB exclusive instruction for 8 bit value.
lypinator 0:bb348c97df44 1435 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1436 \return value of type uint8_t at (*ptr)
lypinator 0:bb348c97df44 1437 */
lypinator 0:bb348c97df44 1438 __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
lypinator 0:bb348c97df44 1439 {
lypinator 0:bb348c97df44 1440 uint32_t result;
lypinator 0:bb348c97df44 1441
lypinator 0:bb348c97df44 1442 __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
lypinator 0:bb348c97df44 1443 return ((uint8_t) result);
lypinator 0:bb348c97df44 1444 }
lypinator 0:bb348c97df44 1445
lypinator 0:bb348c97df44 1446
lypinator 0:bb348c97df44 1447 /**
lypinator 0:bb348c97df44 1448 \brief Load-Acquire Exclusive (16 bit)
lypinator 0:bb348c97df44 1449 \details Executes a LDAH exclusive instruction for 16 bit values.
lypinator 0:bb348c97df44 1450 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1451 \return value of type uint16_t at (*ptr)
lypinator 0:bb348c97df44 1452 */
lypinator 0:bb348c97df44 1453 __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
lypinator 0:bb348c97df44 1454 {
lypinator 0:bb348c97df44 1455 uint32_t result;
lypinator 0:bb348c97df44 1456
lypinator 0:bb348c97df44 1457 __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
lypinator 0:bb348c97df44 1458 return ((uint16_t) result);
lypinator 0:bb348c97df44 1459 }
lypinator 0:bb348c97df44 1460
lypinator 0:bb348c97df44 1461
lypinator 0:bb348c97df44 1462 /**
lypinator 0:bb348c97df44 1463 \brief Load-Acquire Exclusive (32 bit)
lypinator 0:bb348c97df44 1464 \details Executes a LDA exclusive instruction for 32 bit values.
lypinator 0:bb348c97df44 1465 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1466 \return value of type uint32_t at (*ptr)
lypinator 0:bb348c97df44 1467 */
lypinator 0:bb348c97df44 1468 __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
lypinator 0:bb348c97df44 1469 {
lypinator 0:bb348c97df44 1470 uint32_t result;
lypinator 0:bb348c97df44 1471
lypinator 0:bb348c97df44 1472 __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
lypinator 0:bb348c97df44 1473 return(result);
lypinator 0:bb348c97df44 1474 }
lypinator 0:bb348c97df44 1475
lypinator 0:bb348c97df44 1476
lypinator 0:bb348c97df44 1477 /**
lypinator 0:bb348c97df44 1478 \brief Store-Release Exclusive (8 bit)
lypinator 0:bb348c97df44 1479 \details Executes a STLB exclusive instruction for 8 bit values.
lypinator 0:bb348c97df44 1480 \param [in] value Value to store
lypinator 0:bb348c97df44 1481 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1482 \return 0 Function succeeded
lypinator 0:bb348c97df44 1483 \return 1 Function failed
lypinator 0:bb348c97df44 1484 */
lypinator 0:bb348c97df44 1485 __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
lypinator 0:bb348c97df44 1486 {
lypinator 0:bb348c97df44 1487 uint32_t result;
lypinator 0:bb348c97df44 1488
lypinator 0:bb348c97df44 1489 __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
lypinator 0:bb348c97df44 1490 return(result);
lypinator 0:bb348c97df44 1491 }
lypinator 0:bb348c97df44 1492
lypinator 0:bb348c97df44 1493
lypinator 0:bb348c97df44 1494 /**
lypinator 0:bb348c97df44 1495 \brief Store-Release Exclusive (16 bit)
lypinator 0:bb348c97df44 1496 \details Executes a STLH exclusive instruction for 16 bit values.
lypinator 0:bb348c97df44 1497 \param [in] value Value to store
lypinator 0:bb348c97df44 1498 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1499 \return 0 Function succeeded
lypinator 0:bb348c97df44 1500 \return 1 Function failed
lypinator 0:bb348c97df44 1501 */
lypinator 0:bb348c97df44 1502 __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
lypinator 0:bb348c97df44 1503 {
lypinator 0:bb348c97df44 1504 uint32_t result;
lypinator 0:bb348c97df44 1505
lypinator 0:bb348c97df44 1506 __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
lypinator 0:bb348c97df44 1507 return(result);
lypinator 0:bb348c97df44 1508 }
lypinator 0:bb348c97df44 1509
lypinator 0:bb348c97df44 1510
lypinator 0:bb348c97df44 1511 /**
lypinator 0:bb348c97df44 1512 \brief Store-Release Exclusive (32 bit)
lypinator 0:bb348c97df44 1513 \details Executes a STL exclusive instruction for 32 bit values.
lypinator 0:bb348c97df44 1514 \param [in] value Value to store
lypinator 0:bb348c97df44 1515 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1516 \return 0 Function succeeded
lypinator 0:bb348c97df44 1517 \return 1 Function failed
lypinator 0:bb348c97df44 1518 */
lypinator 0:bb348c97df44 1519 __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
lypinator 0:bb348c97df44 1520 {
lypinator 0:bb348c97df44 1521 uint32_t result;
lypinator 0:bb348c97df44 1522
lypinator 0:bb348c97df44 1523 __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
lypinator 0:bb348c97df44 1524 return(result);
lypinator 0:bb348c97df44 1525 }
lypinator 0:bb348c97df44 1526
lypinator 0:bb348c97df44 1527 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
lypinator 0:bb348c97df44 1528 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
lypinator 0:bb348c97df44 1529
lypinator 0:bb348c97df44 1530 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
lypinator 0:bb348c97df44 1531
lypinator 0:bb348c97df44 1532
lypinator 0:bb348c97df44 1533 /* ################### Compiler specific Intrinsics ########################### */
lypinator 0:bb348c97df44 1534 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
lypinator 0:bb348c97df44 1535 Access to dedicated SIMD instructions
lypinator 0:bb348c97df44 1536 @{
lypinator 0:bb348c97df44 1537 */
lypinator 0:bb348c97df44 1538
lypinator 0:bb348c97df44 1539 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
lypinator 0:bb348c97df44 1540
lypinator 0:bb348c97df44 1541 __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1542 {
lypinator 0:bb348c97df44 1543 uint32_t result;
lypinator 0:bb348c97df44 1544
lypinator 0:bb348c97df44 1545 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1546 return(result);
lypinator 0:bb348c97df44 1547 }
lypinator 0:bb348c97df44 1548
lypinator 0:bb348c97df44 1549 __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1550 {
lypinator 0:bb348c97df44 1551 uint32_t result;
lypinator 0:bb348c97df44 1552
lypinator 0:bb348c97df44 1553 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1554 return(result);
lypinator 0:bb348c97df44 1555 }
lypinator 0:bb348c97df44 1556
lypinator 0:bb348c97df44 1557 __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1558 {
lypinator 0:bb348c97df44 1559 uint32_t result;
lypinator 0:bb348c97df44 1560
lypinator 0:bb348c97df44 1561 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1562 return(result);
lypinator 0:bb348c97df44 1563 }
lypinator 0:bb348c97df44 1564
lypinator 0:bb348c97df44 1565 __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1566 {
lypinator 0:bb348c97df44 1567 uint32_t result;
lypinator 0:bb348c97df44 1568
lypinator 0:bb348c97df44 1569 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1570 return(result);
lypinator 0:bb348c97df44 1571 }
lypinator 0:bb348c97df44 1572
lypinator 0:bb348c97df44 1573 __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1574 {
lypinator 0:bb348c97df44 1575 uint32_t result;
lypinator 0:bb348c97df44 1576
lypinator 0:bb348c97df44 1577 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1578 return(result);
lypinator 0:bb348c97df44 1579 }
lypinator 0:bb348c97df44 1580
lypinator 0:bb348c97df44 1581 __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1582 {
lypinator 0:bb348c97df44 1583 uint32_t result;
lypinator 0:bb348c97df44 1584
lypinator 0:bb348c97df44 1585 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1586 return(result);
lypinator 0:bb348c97df44 1587 }
lypinator 0:bb348c97df44 1588
lypinator 0:bb348c97df44 1589
lypinator 0:bb348c97df44 1590 __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1591 {
lypinator 0:bb348c97df44 1592 uint32_t result;
lypinator 0:bb348c97df44 1593
lypinator 0:bb348c97df44 1594 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1595 return(result);
lypinator 0:bb348c97df44 1596 }
lypinator 0:bb348c97df44 1597
lypinator 0:bb348c97df44 1598 __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1599 {
lypinator 0:bb348c97df44 1600 uint32_t result;
lypinator 0:bb348c97df44 1601
lypinator 0:bb348c97df44 1602 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1603 return(result);
lypinator 0:bb348c97df44 1604 }
lypinator 0:bb348c97df44 1605
lypinator 0:bb348c97df44 1606 __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1607 {
lypinator 0:bb348c97df44 1608 uint32_t result;
lypinator 0:bb348c97df44 1609
lypinator 0:bb348c97df44 1610 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1611 return(result);
lypinator 0:bb348c97df44 1612 }
lypinator 0:bb348c97df44 1613
lypinator 0:bb348c97df44 1614 __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1615 {
lypinator 0:bb348c97df44 1616 uint32_t result;
lypinator 0:bb348c97df44 1617
lypinator 0:bb348c97df44 1618 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1619 return(result);
lypinator 0:bb348c97df44 1620 }
lypinator 0:bb348c97df44 1621
lypinator 0:bb348c97df44 1622 __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1623 {
lypinator 0:bb348c97df44 1624 uint32_t result;
lypinator 0:bb348c97df44 1625
lypinator 0:bb348c97df44 1626 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1627 return(result);
lypinator 0:bb348c97df44 1628 }
lypinator 0:bb348c97df44 1629
lypinator 0:bb348c97df44 1630 __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1631 {
lypinator 0:bb348c97df44 1632 uint32_t result;
lypinator 0:bb348c97df44 1633
lypinator 0:bb348c97df44 1634 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1635 return(result);
lypinator 0:bb348c97df44 1636 }
lypinator 0:bb348c97df44 1637
lypinator 0:bb348c97df44 1638
lypinator 0:bb348c97df44 1639 __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1640 {
lypinator 0:bb348c97df44 1641 uint32_t result;
lypinator 0:bb348c97df44 1642
lypinator 0:bb348c97df44 1643 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1644 return(result);
lypinator 0:bb348c97df44 1645 }
lypinator 0:bb348c97df44 1646
lypinator 0:bb348c97df44 1647 __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1648 {
lypinator 0:bb348c97df44 1649 uint32_t result;
lypinator 0:bb348c97df44 1650
lypinator 0:bb348c97df44 1651 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1652 return(result);
lypinator 0:bb348c97df44 1653 }
lypinator 0:bb348c97df44 1654
lypinator 0:bb348c97df44 1655 __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1656 {
lypinator 0:bb348c97df44 1657 uint32_t result;
lypinator 0:bb348c97df44 1658
lypinator 0:bb348c97df44 1659 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1660 return(result);
lypinator 0:bb348c97df44 1661 }
lypinator 0:bb348c97df44 1662
lypinator 0:bb348c97df44 1663 __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1664 {
lypinator 0:bb348c97df44 1665 uint32_t result;
lypinator 0:bb348c97df44 1666
lypinator 0:bb348c97df44 1667 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1668 return(result);
lypinator 0:bb348c97df44 1669 }
lypinator 0:bb348c97df44 1670
lypinator 0:bb348c97df44 1671 __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1672 {
lypinator 0:bb348c97df44 1673 uint32_t result;
lypinator 0:bb348c97df44 1674
lypinator 0:bb348c97df44 1675 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1676 return(result);
lypinator 0:bb348c97df44 1677 }
lypinator 0:bb348c97df44 1678
lypinator 0:bb348c97df44 1679 __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1680 {
lypinator 0:bb348c97df44 1681 uint32_t result;
lypinator 0:bb348c97df44 1682
lypinator 0:bb348c97df44 1683 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1684 return(result);
lypinator 0:bb348c97df44 1685 }
lypinator 0:bb348c97df44 1686
lypinator 0:bb348c97df44 1687 __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1688 {
lypinator 0:bb348c97df44 1689 uint32_t result;
lypinator 0:bb348c97df44 1690
lypinator 0:bb348c97df44 1691 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1692 return(result);
lypinator 0:bb348c97df44 1693 }
lypinator 0:bb348c97df44 1694
lypinator 0:bb348c97df44 1695 __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1696 {
lypinator 0:bb348c97df44 1697 uint32_t result;
lypinator 0:bb348c97df44 1698
lypinator 0:bb348c97df44 1699 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1700 return(result);
lypinator 0:bb348c97df44 1701 }
lypinator 0:bb348c97df44 1702
lypinator 0:bb348c97df44 1703 __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1704 {
lypinator 0:bb348c97df44 1705 uint32_t result;
lypinator 0:bb348c97df44 1706
lypinator 0:bb348c97df44 1707 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1708 return(result);
lypinator 0:bb348c97df44 1709 }
lypinator 0:bb348c97df44 1710
lypinator 0:bb348c97df44 1711 __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1712 {
lypinator 0:bb348c97df44 1713 uint32_t result;
lypinator 0:bb348c97df44 1714
lypinator 0:bb348c97df44 1715 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1716 return(result);
lypinator 0:bb348c97df44 1717 }
lypinator 0:bb348c97df44 1718
lypinator 0:bb348c97df44 1719 __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1720 {
lypinator 0:bb348c97df44 1721 uint32_t result;
lypinator 0:bb348c97df44 1722
lypinator 0:bb348c97df44 1723 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1724 return(result);
lypinator 0:bb348c97df44 1725 }
lypinator 0:bb348c97df44 1726
lypinator 0:bb348c97df44 1727 __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1728 {
lypinator 0:bb348c97df44 1729 uint32_t result;
lypinator 0:bb348c97df44 1730
lypinator 0:bb348c97df44 1731 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1732 return(result);
lypinator 0:bb348c97df44 1733 }
lypinator 0:bb348c97df44 1734
lypinator 0:bb348c97df44 1735 __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1736 {
lypinator 0:bb348c97df44 1737 uint32_t result;
lypinator 0:bb348c97df44 1738
lypinator 0:bb348c97df44 1739 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1740 return(result);
lypinator 0:bb348c97df44 1741 }
lypinator 0:bb348c97df44 1742
lypinator 0:bb348c97df44 1743 __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1744 {
lypinator 0:bb348c97df44 1745 uint32_t result;
lypinator 0:bb348c97df44 1746
lypinator 0:bb348c97df44 1747 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1748 return(result);
lypinator 0:bb348c97df44 1749 }
lypinator 0:bb348c97df44 1750
lypinator 0:bb348c97df44 1751 __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1752 {
lypinator 0:bb348c97df44 1753 uint32_t result;
lypinator 0:bb348c97df44 1754
lypinator 0:bb348c97df44 1755 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1756 return(result);
lypinator 0:bb348c97df44 1757 }
lypinator 0:bb348c97df44 1758
lypinator 0:bb348c97df44 1759 __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1760 {
lypinator 0:bb348c97df44 1761 uint32_t result;
lypinator 0:bb348c97df44 1762
lypinator 0:bb348c97df44 1763 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1764 return(result);
lypinator 0:bb348c97df44 1765 }
lypinator 0:bb348c97df44 1766
lypinator 0:bb348c97df44 1767 __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1768 {
lypinator 0:bb348c97df44 1769 uint32_t result;
lypinator 0:bb348c97df44 1770
lypinator 0:bb348c97df44 1771 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1772 return(result);
lypinator 0:bb348c97df44 1773 }
lypinator 0:bb348c97df44 1774
lypinator 0:bb348c97df44 1775 __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1776 {
lypinator 0:bb348c97df44 1777 uint32_t result;
lypinator 0:bb348c97df44 1778
lypinator 0:bb348c97df44 1779 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1780 return(result);
lypinator 0:bb348c97df44 1781 }
lypinator 0:bb348c97df44 1782
lypinator 0:bb348c97df44 1783 __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1784 {
lypinator 0:bb348c97df44 1785 uint32_t result;
lypinator 0:bb348c97df44 1786
lypinator 0:bb348c97df44 1787 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1788 return(result);
lypinator 0:bb348c97df44 1789 }
lypinator 0:bb348c97df44 1790
lypinator 0:bb348c97df44 1791 __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1792 {
lypinator 0:bb348c97df44 1793 uint32_t result;
lypinator 0:bb348c97df44 1794
lypinator 0:bb348c97df44 1795 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1796 return(result);
lypinator 0:bb348c97df44 1797 }
lypinator 0:bb348c97df44 1798
lypinator 0:bb348c97df44 1799 __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1800 {
lypinator 0:bb348c97df44 1801 uint32_t result;
lypinator 0:bb348c97df44 1802
lypinator 0:bb348c97df44 1803 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1804 return(result);
lypinator 0:bb348c97df44 1805 }
lypinator 0:bb348c97df44 1806
lypinator 0:bb348c97df44 1807 __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1808 {
lypinator 0:bb348c97df44 1809 uint32_t result;
lypinator 0:bb348c97df44 1810
lypinator 0:bb348c97df44 1811 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1812 return(result);
lypinator 0:bb348c97df44 1813 }
lypinator 0:bb348c97df44 1814
lypinator 0:bb348c97df44 1815 __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1816 {
lypinator 0:bb348c97df44 1817 uint32_t result;
lypinator 0:bb348c97df44 1818
lypinator 0:bb348c97df44 1819 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1820 return(result);
lypinator 0:bb348c97df44 1821 }
lypinator 0:bb348c97df44 1822
lypinator 0:bb348c97df44 1823 __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1824 {
lypinator 0:bb348c97df44 1825 uint32_t result;
lypinator 0:bb348c97df44 1826
lypinator 0:bb348c97df44 1827 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1828 return(result);
lypinator 0:bb348c97df44 1829 }
lypinator 0:bb348c97df44 1830
lypinator 0:bb348c97df44 1831 __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1832 {
lypinator 0:bb348c97df44 1833 uint32_t result;
lypinator 0:bb348c97df44 1834
lypinator 0:bb348c97df44 1835 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1836 return(result);
lypinator 0:bb348c97df44 1837 }
lypinator 0:bb348c97df44 1838
lypinator 0:bb348c97df44 1839 __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
lypinator 0:bb348c97df44 1840 {
lypinator 0:bb348c97df44 1841 uint32_t result;
lypinator 0:bb348c97df44 1842
lypinator 0:bb348c97df44 1843 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
lypinator 0:bb348c97df44 1844 return(result);
lypinator 0:bb348c97df44 1845 }
lypinator 0:bb348c97df44 1846
lypinator 0:bb348c97df44 1847 #define __SSAT16(ARG1,ARG2) \
lypinator 0:bb348c97df44 1848 ({ \
lypinator 0:bb348c97df44 1849 int32_t __RES, __ARG1 = (ARG1); \
lypinator 0:bb348c97df44 1850 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
lypinator 0:bb348c97df44 1851 __RES; \
lypinator 0:bb348c97df44 1852 })
lypinator 0:bb348c97df44 1853
lypinator 0:bb348c97df44 1854 #define __USAT16(ARG1,ARG2) \
lypinator 0:bb348c97df44 1855 ({ \
lypinator 0:bb348c97df44 1856 uint32_t __RES, __ARG1 = (ARG1); \
lypinator 0:bb348c97df44 1857 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
lypinator 0:bb348c97df44 1858 __RES; \
lypinator 0:bb348c97df44 1859 })
lypinator 0:bb348c97df44 1860
lypinator 0:bb348c97df44 1861 __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
lypinator 0:bb348c97df44 1862 {
lypinator 0:bb348c97df44 1863 uint32_t result;
lypinator 0:bb348c97df44 1864
lypinator 0:bb348c97df44 1865 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
lypinator 0:bb348c97df44 1866 return(result);
lypinator 0:bb348c97df44 1867 }
lypinator 0:bb348c97df44 1868
lypinator 0:bb348c97df44 1869 __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1870 {
lypinator 0:bb348c97df44 1871 uint32_t result;
lypinator 0:bb348c97df44 1872
lypinator 0:bb348c97df44 1873 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1874 return(result);
lypinator 0:bb348c97df44 1875 }
lypinator 0:bb348c97df44 1876
lypinator 0:bb348c97df44 1877 __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
lypinator 0:bb348c97df44 1878 {
lypinator 0:bb348c97df44 1879 uint32_t result;
lypinator 0:bb348c97df44 1880
lypinator 0:bb348c97df44 1881 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
lypinator 0:bb348c97df44 1882 return(result);
lypinator 0:bb348c97df44 1883 }
lypinator 0:bb348c97df44 1884
lypinator 0:bb348c97df44 1885 __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1886 {
lypinator 0:bb348c97df44 1887 uint32_t result;
lypinator 0:bb348c97df44 1888
lypinator 0:bb348c97df44 1889 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1890 return(result);
lypinator 0:bb348c97df44 1891 }
lypinator 0:bb348c97df44 1892
lypinator 0:bb348c97df44 1893 __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1894 {
lypinator 0:bb348c97df44 1895 uint32_t result;
lypinator 0:bb348c97df44 1896
lypinator 0:bb348c97df44 1897 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1898 return(result);
lypinator 0:bb348c97df44 1899 }
lypinator 0:bb348c97df44 1900
lypinator 0:bb348c97df44 1901 __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1902 {
lypinator 0:bb348c97df44 1903 uint32_t result;
lypinator 0:bb348c97df44 1904
lypinator 0:bb348c97df44 1905 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1906 return(result);
lypinator 0:bb348c97df44 1907 }
lypinator 0:bb348c97df44 1908
lypinator 0:bb348c97df44 1909 __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
lypinator 0:bb348c97df44 1910 {
lypinator 0:bb348c97df44 1911 uint32_t result;
lypinator 0:bb348c97df44 1912
lypinator 0:bb348c97df44 1913 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
lypinator 0:bb348c97df44 1914 return(result);
lypinator 0:bb348c97df44 1915 }
lypinator 0:bb348c97df44 1916
lypinator 0:bb348c97df44 1917 __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
lypinator 0:bb348c97df44 1918 {
lypinator 0:bb348c97df44 1919 uint32_t result;
lypinator 0:bb348c97df44 1920
lypinator 0:bb348c97df44 1921 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
lypinator 0:bb348c97df44 1922 return(result);
lypinator 0:bb348c97df44 1923 }
lypinator 0:bb348c97df44 1924
lypinator 0:bb348c97df44 1925 __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
lypinator 0:bb348c97df44 1926 {
lypinator 0:bb348c97df44 1927 union llreg_u{
lypinator 0:bb348c97df44 1928 uint32_t w32[2];
lypinator 0:bb348c97df44 1929 uint64_t w64;
lypinator 0:bb348c97df44 1930 } llr;
lypinator 0:bb348c97df44 1931 llr.w64 = acc;
lypinator 0:bb348c97df44 1932
lypinator 0:bb348c97df44 1933 #ifndef __ARMEB__ /* Little endian */
lypinator 0:bb348c97df44 1934 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
lypinator 0:bb348c97df44 1935 #else /* Big endian */
lypinator 0:bb348c97df44 1936 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
lypinator 0:bb348c97df44 1937 #endif
lypinator 0:bb348c97df44 1938
lypinator 0:bb348c97df44 1939 return(llr.w64);
lypinator 0:bb348c97df44 1940 }
lypinator 0:bb348c97df44 1941
lypinator 0:bb348c97df44 1942 __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
lypinator 0:bb348c97df44 1943 {
lypinator 0:bb348c97df44 1944 union llreg_u{
lypinator 0:bb348c97df44 1945 uint32_t w32[2];
lypinator 0:bb348c97df44 1946 uint64_t w64;
lypinator 0:bb348c97df44 1947 } llr;
lypinator 0:bb348c97df44 1948 llr.w64 = acc;
lypinator 0:bb348c97df44 1949
lypinator 0:bb348c97df44 1950 #ifndef __ARMEB__ /* Little endian */
lypinator 0:bb348c97df44 1951 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
lypinator 0:bb348c97df44 1952 #else /* Big endian */
lypinator 0:bb348c97df44 1953 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
lypinator 0:bb348c97df44 1954 #endif
lypinator 0:bb348c97df44 1955
lypinator 0:bb348c97df44 1956 return(llr.w64);
lypinator 0:bb348c97df44 1957 }
lypinator 0:bb348c97df44 1958
lypinator 0:bb348c97df44 1959 __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1960 {
lypinator 0:bb348c97df44 1961 uint32_t result;
lypinator 0:bb348c97df44 1962
lypinator 0:bb348c97df44 1963 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1964 return(result);
lypinator 0:bb348c97df44 1965 }
lypinator 0:bb348c97df44 1966
lypinator 0:bb348c97df44 1967 __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1968 {
lypinator 0:bb348c97df44 1969 uint32_t result;
lypinator 0:bb348c97df44 1970
lypinator 0:bb348c97df44 1971 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1972 return(result);
lypinator 0:bb348c97df44 1973 }
lypinator 0:bb348c97df44 1974
lypinator 0:bb348c97df44 1975 __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
lypinator 0:bb348c97df44 1976 {
lypinator 0:bb348c97df44 1977 uint32_t result;
lypinator 0:bb348c97df44 1978
lypinator 0:bb348c97df44 1979 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
lypinator 0:bb348c97df44 1980 return(result);
lypinator 0:bb348c97df44 1981 }
lypinator 0:bb348c97df44 1982
lypinator 0:bb348c97df44 1983 __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
lypinator 0:bb348c97df44 1984 {
lypinator 0:bb348c97df44 1985 uint32_t result;
lypinator 0:bb348c97df44 1986
lypinator 0:bb348c97df44 1987 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
lypinator 0:bb348c97df44 1988 return(result);
lypinator 0:bb348c97df44 1989 }
lypinator 0:bb348c97df44 1990
lypinator 0:bb348c97df44 1991 __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
lypinator 0:bb348c97df44 1992 {
lypinator 0:bb348c97df44 1993 union llreg_u{
lypinator 0:bb348c97df44 1994 uint32_t w32[2];
lypinator 0:bb348c97df44 1995 uint64_t w64;
lypinator 0:bb348c97df44 1996 } llr;
lypinator 0:bb348c97df44 1997 llr.w64 = acc;
lypinator 0:bb348c97df44 1998
lypinator 0:bb348c97df44 1999 #ifndef __ARMEB__ /* Little endian */
lypinator 0:bb348c97df44 2000 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
lypinator 0:bb348c97df44 2001 #else /* Big endian */
lypinator 0:bb348c97df44 2002 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
lypinator 0:bb348c97df44 2003 #endif
lypinator 0:bb348c97df44 2004
lypinator 0:bb348c97df44 2005 return(llr.w64);
lypinator 0:bb348c97df44 2006 }
lypinator 0:bb348c97df44 2007
lypinator 0:bb348c97df44 2008 __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
lypinator 0:bb348c97df44 2009 {
lypinator 0:bb348c97df44 2010 union llreg_u{
lypinator 0:bb348c97df44 2011 uint32_t w32[2];
lypinator 0:bb348c97df44 2012 uint64_t w64;
lypinator 0:bb348c97df44 2013 } llr;
lypinator 0:bb348c97df44 2014 llr.w64 = acc;
lypinator 0:bb348c97df44 2015
lypinator 0:bb348c97df44 2016 #ifndef __ARMEB__ /* Little endian */
lypinator 0:bb348c97df44 2017 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
lypinator 0:bb348c97df44 2018 #else /* Big endian */
lypinator 0:bb348c97df44 2019 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
lypinator 0:bb348c97df44 2020 #endif
lypinator 0:bb348c97df44 2021
lypinator 0:bb348c97df44 2022 return(llr.w64);
lypinator 0:bb348c97df44 2023 }
lypinator 0:bb348c97df44 2024
lypinator 0:bb348c97df44 2025 __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 2026 {
lypinator 0:bb348c97df44 2027 uint32_t result;
lypinator 0:bb348c97df44 2028
lypinator 0:bb348c97df44 2029 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 2030 return(result);
lypinator 0:bb348c97df44 2031 }
lypinator 0:bb348c97df44 2032
lypinator 0:bb348c97df44 2033 __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
lypinator 0:bb348c97df44 2034 {
lypinator 0:bb348c97df44 2035 int32_t result;
lypinator 0:bb348c97df44 2036
lypinator 0:bb348c97df44 2037 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 2038 return(result);
lypinator 0:bb348c97df44 2039 }
lypinator 0:bb348c97df44 2040
lypinator 0:bb348c97df44 2041 __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
lypinator 0:bb348c97df44 2042 {
lypinator 0:bb348c97df44 2043 int32_t result;
lypinator 0:bb348c97df44 2044
lypinator 0:bb348c97df44 2045 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 2046 return(result);
lypinator 0:bb348c97df44 2047 }
lypinator 0:bb348c97df44 2048
lypinator 0:bb348c97df44 2049 #if 0
lypinator 0:bb348c97df44 2050 #define __PKHBT(ARG1,ARG2,ARG3) \
lypinator 0:bb348c97df44 2051 ({ \
lypinator 0:bb348c97df44 2052 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
lypinator 0:bb348c97df44 2053 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
lypinator 0:bb348c97df44 2054 __RES; \
lypinator 0:bb348c97df44 2055 })
lypinator 0:bb348c97df44 2056
lypinator 0:bb348c97df44 2057 #define __PKHTB(ARG1,ARG2,ARG3) \
lypinator 0:bb348c97df44 2058 ({ \
lypinator 0:bb348c97df44 2059 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
lypinator 0:bb348c97df44 2060 if (ARG3 == 0) \
lypinator 0:bb348c97df44 2061 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
lypinator 0:bb348c97df44 2062 else \
lypinator 0:bb348c97df44 2063 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
lypinator 0:bb348c97df44 2064 __RES; \
lypinator 0:bb348c97df44 2065 })
lypinator 0:bb348c97df44 2066 #endif
lypinator 0:bb348c97df44 2067
lypinator 0:bb348c97df44 2068 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
lypinator 0:bb348c97df44 2069 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
lypinator 0:bb348c97df44 2070
lypinator 0:bb348c97df44 2071 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
lypinator 0:bb348c97df44 2072 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
lypinator 0:bb348c97df44 2073
lypinator 0:bb348c97df44 2074 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
lypinator 0:bb348c97df44 2075 {
lypinator 0:bb348c97df44 2076 int32_t result;
lypinator 0:bb348c97df44 2077
lypinator 0:bb348c97df44 2078 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
lypinator 0:bb348c97df44 2079 return(result);
lypinator 0:bb348c97df44 2080 }
lypinator 0:bb348c97df44 2081
lypinator 0:bb348c97df44 2082 #endif /* (__ARM_FEATURE_DSP == 1) */
lypinator 0:bb348c97df44 2083 /*@} end of group CMSIS_SIMD_intrinsics */
lypinator 0:bb348c97df44 2084
lypinator 0:bb348c97df44 2085
lypinator 0:bb348c97df44 2086 #pragma GCC diagnostic pop
lypinator 0:bb348c97df44 2087
lypinator 0:bb348c97df44 2088 #endif /* __CMSIS_GCC_H */