Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/cmsis/TARGET_CORTEX_M/cmsis_armclang.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**************************************************************************//**
lypinator 0:bb348c97df44 2 * @file cmsis_armclang.h
lypinator 0:bb348c97df44 3 * @brief CMSIS compiler armclang (Arm Compiler 6) header file
lypinator 0:bb348c97df44 4 * @version V5.0.4
lypinator 0:bb348c97df44 5 * @date 10. January 2018
lypinator 0:bb348c97df44 6 ******************************************************************************/
lypinator 0:bb348c97df44 7 /*
lypinator 0:bb348c97df44 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * SPDX-License-Identifier: Apache-2.0
lypinator 0:bb348c97df44 11 *
lypinator 0:bb348c97df44 12 * Licensed under the Apache License, Version 2.0 (the License); you may
lypinator 0:bb348c97df44 13 * not use this file except in compliance with the License.
lypinator 0:bb348c97df44 14 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 15 *
lypinator 0:bb348c97df44 16 * www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 17 *
lypinator 0:bb348c97df44 18 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
lypinator 0:bb348c97df44 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 21 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 22 * limitations under the License.
lypinator 0:bb348c97df44 23 */
lypinator 0:bb348c97df44 24
lypinator 0:bb348c97df44 25 /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
lypinator 0:bb348c97df44 26
lypinator 0:bb348c97df44 27 #ifndef __CMSIS_ARMCLANG_H
lypinator 0:bb348c97df44 28 #define __CMSIS_ARMCLANG_H
lypinator 0:bb348c97df44 29
lypinator 0:bb348c97df44 30 #pragma clang system_header /* treat file as system include file */
lypinator 0:bb348c97df44 31
lypinator 0:bb348c97df44 32 #ifndef __ARM_COMPAT_H
lypinator 0:bb348c97df44 33 #include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
lypinator 0:bb348c97df44 34 #endif
lypinator 0:bb348c97df44 35
lypinator 0:bb348c97df44 36 /* CMSIS compiler specific defines */
lypinator 0:bb348c97df44 37 #ifndef __ASM
lypinator 0:bb348c97df44 38 #define __ASM __asm
lypinator 0:bb348c97df44 39 #endif
lypinator 0:bb348c97df44 40 #ifndef __INLINE
lypinator 0:bb348c97df44 41 #define __INLINE __inline
lypinator 0:bb348c97df44 42 #endif
lypinator 0:bb348c97df44 43 #ifndef __STATIC_INLINE
lypinator 0:bb348c97df44 44 #define __STATIC_INLINE static __inline
lypinator 0:bb348c97df44 45 #endif
lypinator 0:bb348c97df44 46 #ifndef __STATIC_FORCEINLINE
lypinator 0:bb348c97df44 47 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
lypinator 0:bb348c97df44 48 #endif
lypinator 0:bb348c97df44 49 #ifndef __NO_RETURN
lypinator 0:bb348c97df44 50 #define __NO_RETURN __attribute__((__noreturn__))
lypinator 0:bb348c97df44 51 #endif
lypinator 0:bb348c97df44 52 #ifndef __USED
lypinator 0:bb348c97df44 53 #define __USED __attribute__((used))
lypinator 0:bb348c97df44 54 #endif
lypinator 0:bb348c97df44 55 #ifndef __WEAK
lypinator 0:bb348c97df44 56 #define __WEAK __attribute__((weak))
lypinator 0:bb348c97df44 57 #endif
lypinator 0:bb348c97df44 58 #ifndef __PACKED
lypinator 0:bb348c97df44 59 #define __PACKED __attribute__((packed, aligned(1)))
lypinator 0:bb348c97df44 60 #endif
lypinator 0:bb348c97df44 61 #ifndef __PACKED_STRUCT
lypinator 0:bb348c97df44 62 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
lypinator 0:bb348c97df44 63 #endif
lypinator 0:bb348c97df44 64 #ifndef __PACKED_UNION
lypinator 0:bb348c97df44 65 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
lypinator 0:bb348c97df44 66 #endif
lypinator 0:bb348c97df44 67 #ifndef __UNALIGNED_UINT32 /* deprecated */
lypinator 0:bb348c97df44 68 #pragma clang diagnostic push
lypinator 0:bb348c97df44 69 #pragma clang diagnostic ignored "-Wpacked"
lypinator 0:bb348c97df44 70 /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
lypinator 0:bb348c97df44 71 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
lypinator 0:bb348c97df44 72 #pragma clang diagnostic pop
lypinator 0:bb348c97df44 73 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
lypinator 0:bb348c97df44 74 #endif
lypinator 0:bb348c97df44 75 #ifndef __UNALIGNED_UINT16_WRITE
lypinator 0:bb348c97df44 76 #pragma clang diagnostic push
lypinator 0:bb348c97df44 77 #pragma clang diagnostic ignored "-Wpacked"
lypinator 0:bb348c97df44 78 /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
lypinator 0:bb348c97df44 79 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
lypinator 0:bb348c97df44 80 #pragma clang diagnostic pop
lypinator 0:bb348c97df44 81 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
lypinator 0:bb348c97df44 82 #endif
lypinator 0:bb348c97df44 83 #ifndef __UNALIGNED_UINT16_READ
lypinator 0:bb348c97df44 84 #pragma clang diagnostic push
lypinator 0:bb348c97df44 85 #pragma clang diagnostic ignored "-Wpacked"
lypinator 0:bb348c97df44 86 /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
lypinator 0:bb348c97df44 87 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
lypinator 0:bb348c97df44 88 #pragma clang diagnostic pop
lypinator 0:bb348c97df44 89 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
lypinator 0:bb348c97df44 90 #endif
lypinator 0:bb348c97df44 91 #ifndef __UNALIGNED_UINT32_WRITE
lypinator 0:bb348c97df44 92 #pragma clang diagnostic push
lypinator 0:bb348c97df44 93 #pragma clang diagnostic ignored "-Wpacked"
lypinator 0:bb348c97df44 94 /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
lypinator 0:bb348c97df44 95 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
lypinator 0:bb348c97df44 96 #pragma clang diagnostic pop
lypinator 0:bb348c97df44 97 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
lypinator 0:bb348c97df44 98 #endif
lypinator 0:bb348c97df44 99 #ifndef __UNALIGNED_UINT32_READ
lypinator 0:bb348c97df44 100 #pragma clang diagnostic push
lypinator 0:bb348c97df44 101 #pragma clang diagnostic ignored "-Wpacked"
lypinator 0:bb348c97df44 102 /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
lypinator 0:bb348c97df44 103 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
lypinator 0:bb348c97df44 104 #pragma clang diagnostic pop
lypinator 0:bb348c97df44 105 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
lypinator 0:bb348c97df44 106 #endif
lypinator 0:bb348c97df44 107 #ifndef __ALIGNED
lypinator 0:bb348c97df44 108 #define __ALIGNED(x) __attribute__((aligned(x)))
lypinator 0:bb348c97df44 109 #endif
lypinator 0:bb348c97df44 110 #ifndef __RESTRICT
lypinator 0:bb348c97df44 111 #define __RESTRICT __restrict
lypinator 0:bb348c97df44 112 #endif
lypinator 0:bb348c97df44 113
lypinator 0:bb348c97df44 114
lypinator 0:bb348c97df44 115 /* ########################### Core Function Access ########################### */
lypinator 0:bb348c97df44 116 /** \ingroup CMSIS_Core_FunctionInterface
lypinator 0:bb348c97df44 117 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
lypinator 0:bb348c97df44 118 @{
lypinator 0:bb348c97df44 119 */
lypinator 0:bb348c97df44 120
lypinator 0:bb348c97df44 121 /**
lypinator 0:bb348c97df44 122 \brief Enable IRQ Interrupts
lypinator 0:bb348c97df44 123 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
lypinator 0:bb348c97df44 124 Can only be executed in Privileged modes.
lypinator 0:bb348c97df44 125 */
lypinator 0:bb348c97df44 126 /* intrinsic void __enable_irq(); see arm_compat.h */
lypinator 0:bb348c97df44 127
lypinator 0:bb348c97df44 128
lypinator 0:bb348c97df44 129 /**
lypinator 0:bb348c97df44 130 \brief Disable IRQ Interrupts
lypinator 0:bb348c97df44 131 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
lypinator 0:bb348c97df44 132 Can only be executed in Privileged modes.
lypinator 0:bb348c97df44 133 */
lypinator 0:bb348c97df44 134 /* intrinsic void __disable_irq(); see arm_compat.h */
lypinator 0:bb348c97df44 135
lypinator 0:bb348c97df44 136
lypinator 0:bb348c97df44 137 /**
lypinator 0:bb348c97df44 138 \brief Get Control Register
lypinator 0:bb348c97df44 139 \details Returns the content of the Control Register.
lypinator 0:bb348c97df44 140 \return Control Register value
lypinator 0:bb348c97df44 141 */
lypinator 0:bb348c97df44 142 __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
lypinator 0:bb348c97df44 143 {
lypinator 0:bb348c97df44 144 uint32_t result;
lypinator 0:bb348c97df44 145
lypinator 0:bb348c97df44 146 __ASM volatile ("MRS %0, control" : "=r" (result) );
lypinator 0:bb348c97df44 147 return(result);
lypinator 0:bb348c97df44 148 }
lypinator 0:bb348c97df44 149
lypinator 0:bb348c97df44 150
lypinator 0:bb348c97df44 151 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 152 /**
lypinator 0:bb348c97df44 153 \brief Get Control Register (non-secure)
lypinator 0:bb348c97df44 154 \details Returns the content of the non-secure Control Register when in secure mode.
lypinator 0:bb348c97df44 155 \return non-secure Control Register value
lypinator 0:bb348c97df44 156 */
lypinator 0:bb348c97df44 157 __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
lypinator 0:bb348c97df44 158 {
lypinator 0:bb348c97df44 159 uint32_t result;
lypinator 0:bb348c97df44 160
lypinator 0:bb348c97df44 161 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
lypinator 0:bb348c97df44 162 return(result);
lypinator 0:bb348c97df44 163 }
lypinator 0:bb348c97df44 164 #endif
lypinator 0:bb348c97df44 165
lypinator 0:bb348c97df44 166
lypinator 0:bb348c97df44 167 /**
lypinator 0:bb348c97df44 168 \brief Set Control Register
lypinator 0:bb348c97df44 169 \details Writes the given value to the Control Register.
lypinator 0:bb348c97df44 170 \param [in] control Control Register value to set
lypinator 0:bb348c97df44 171 */
lypinator 0:bb348c97df44 172 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
lypinator 0:bb348c97df44 173 {
lypinator 0:bb348c97df44 174 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
lypinator 0:bb348c97df44 175 }
lypinator 0:bb348c97df44 176
lypinator 0:bb348c97df44 177
lypinator 0:bb348c97df44 178 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 179 /**
lypinator 0:bb348c97df44 180 \brief Set Control Register (non-secure)
lypinator 0:bb348c97df44 181 \details Writes the given value to the non-secure Control Register when in secure state.
lypinator 0:bb348c97df44 182 \param [in] control Control Register value to set
lypinator 0:bb348c97df44 183 */
lypinator 0:bb348c97df44 184 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
lypinator 0:bb348c97df44 185 {
lypinator 0:bb348c97df44 186 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
lypinator 0:bb348c97df44 187 }
lypinator 0:bb348c97df44 188 #endif
lypinator 0:bb348c97df44 189
lypinator 0:bb348c97df44 190
lypinator 0:bb348c97df44 191 /**
lypinator 0:bb348c97df44 192 \brief Get IPSR Register
lypinator 0:bb348c97df44 193 \details Returns the content of the IPSR Register.
lypinator 0:bb348c97df44 194 \return IPSR Register value
lypinator 0:bb348c97df44 195 */
lypinator 0:bb348c97df44 196 __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
lypinator 0:bb348c97df44 197 {
lypinator 0:bb348c97df44 198 uint32_t result;
lypinator 0:bb348c97df44 199
lypinator 0:bb348c97df44 200 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
lypinator 0:bb348c97df44 201 return(result);
lypinator 0:bb348c97df44 202 }
lypinator 0:bb348c97df44 203
lypinator 0:bb348c97df44 204
lypinator 0:bb348c97df44 205 /**
lypinator 0:bb348c97df44 206 \brief Get APSR Register
lypinator 0:bb348c97df44 207 \details Returns the content of the APSR Register.
lypinator 0:bb348c97df44 208 \return APSR Register value
lypinator 0:bb348c97df44 209 */
lypinator 0:bb348c97df44 210 __STATIC_FORCEINLINE uint32_t __get_APSR(void)
lypinator 0:bb348c97df44 211 {
lypinator 0:bb348c97df44 212 uint32_t result;
lypinator 0:bb348c97df44 213
lypinator 0:bb348c97df44 214 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
lypinator 0:bb348c97df44 215 return(result);
lypinator 0:bb348c97df44 216 }
lypinator 0:bb348c97df44 217
lypinator 0:bb348c97df44 218
lypinator 0:bb348c97df44 219 /**
lypinator 0:bb348c97df44 220 \brief Get xPSR Register
lypinator 0:bb348c97df44 221 \details Returns the content of the xPSR Register.
lypinator 0:bb348c97df44 222 \return xPSR Register value
lypinator 0:bb348c97df44 223 */
lypinator 0:bb348c97df44 224 __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
lypinator 0:bb348c97df44 225 {
lypinator 0:bb348c97df44 226 uint32_t result;
lypinator 0:bb348c97df44 227
lypinator 0:bb348c97df44 228 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
lypinator 0:bb348c97df44 229 return(result);
lypinator 0:bb348c97df44 230 }
lypinator 0:bb348c97df44 231
lypinator 0:bb348c97df44 232
lypinator 0:bb348c97df44 233 /**
lypinator 0:bb348c97df44 234 \brief Get Process Stack Pointer
lypinator 0:bb348c97df44 235 \details Returns the current value of the Process Stack Pointer (PSP).
lypinator 0:bb348c97df44 236 \return PSP Register value
lypinator 0:bb348c97df44 237 */
lypinator 0:bb348c97df44 238 __STATIC_FORCEINLINE uint32_t __get_PSP(void)
lypinator 0:bb348c97df44 239 {
lypinator 0:bb348c97df44 240 register uint32_t result;
lypinator 0:bb348c97df44 241
lypinator 0:bb348c97df44 242 __ASM volatile ("MRS %0, psp" : "=r" (result) );
lypinator 0:bb348c97df44 243 return(result);
lypinator 0:bb348c97df44 244 }
lypinator 0:bb348c97df44 245
lypinator 0:bb348c97df44 246
lypinator 0:bb348c97df44 247 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 248 /**
lypinator 0:bb348c97df44 249 \brief Get Process Stack Pointer (non-secure)
lypinator 0:bb348c97df44 250 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
lypinator 0:bb348c97df44 251 \return PSP Register value
lypinator 0:bb348c97df44 252 */
lypinator 0:bb348c97df44 253 __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
lypinator 0:bb348c97df44 254 {
lypinator 0:bb348c97df44 255 register uint32_t result;
lypinator 0:bb348c97df44 256
lypinator 0:bb348c97df44 257 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
lypinator 0:bb348c97df44 258 return(result);
lypinator 0:bb348c97df44 259 }
lypinator 0:bb348c97df44 260 #endif
lypinator 0:bb348c97df44 261
lypinator 0:bb348c97df44 262
lypinator 0:bb348c97df44 263 /**
lypinator 0:bb348c97df44 264 \brief Set Process Stack Pointer
lypinator 0:bb348c97df44 265 \details Assigns the given value to the Process Stack Pointer (PSP).
lypinator 0:bb348c97df44 266 \param [in] topOfProcStack Process Stack Pointer value to set
lypinator 0:bb348c97df44 267 */
lypinator 0:bb348c97df44 268 __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
lypinator 0:bb348c97df44 269 {
lypinator 0:bb348c97df44 270 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
lypinator 0:bb348c97df44 271 }
lypinator 0:bb348c97df44 272
lypinator 0:bb348c97df44 273
lypinator 0:bb348c97df44 274 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 275 /**
lypinator 0:bb348c97df44 276 \brief Set Process Stack Pointer (non-secure)
lypinator 0:bb348c97df44 277 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
lypinator 0:bb348c97df44 278 \param [in] topOfProcStack Process Stack Pointer value to set
lypinator 0:bb348c97df44 279 */
lypinator 0:bb348c97df44 280 __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
lypinator 0:bb348c97df44 281 {
lypinator 0:bb348c97df44 282 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
lypinator 0:bb348c97df44 283 }
lypinator 0:bb348c97df44 284 #endif
lypinator 0:bb348c97df44 285
lypinator 0:bb348c97df44 286
lypinator 0:bb348c97df44 287 /**
lypinator 0:bb348c97df44 288 \brief Get Main Stack Pointer
lypinator 0:bb348c97df44 289 \details Returns the current value of the Main Stack Pointer (MSP).
lypinator 0:bb348c97df44 290 \return MSP Register value
lypinator 0:bb348c97df44 291 */
lypinator 0:bb348c97df44 292 __STATIC_FORCEINLINE uint32_t __get_MSP(void)
lypinator 0:bb348c97df44 293 {
lypinator 0:bb348c97df44 294 register uint32_t result;
lypinator 0:bb348c97df44 295
lypinator 0:bb348c97df44 296 __ASM volatile ("MRS %0, msp" : "=r" (result) );
lypinator 0:bb348c97df44 297 return(result);
lypinator 0:bb348c97df44 298 }
lypinator 0:bb348c97df44 299
lypinator 0:bb348c97df44 300
lypinator 0:bb348c97df44 301 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 302 /**
lypinator 0:bb348c97df44 303 \brief Get Main Stack Pointer (non-secure)
lypinator 0:bb348c97df44 304 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
lypinator 0:bb348c97df44 305 \return MSP Register value
lypinator 0:bb348c97df44 306 */
lypinator 0:bb348c97df44 307 __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
lypinator 0:bb348c97df44 308 {
lypinator 0:bb348c97df44 309 register uint32_t result;
lypinator 0:bb348c97df44 310
lypinator 0:bb348c97df44 311 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
lypinator 0:bb348c97df44 312 return(result);
lypinator 0:bb348c97df44 313 }
lypinator 0:bb348c97df44 314 #endif
lypinator 0:bb348c97df44 315
lypinator 0:bb348c97df44 316
lypinator 0:bb348c97df44 317 /**
lypinator 0:bb348c97df44 318 \brief Set Main Stack Pointer
lypinator 0:bb348c97df44 319 \details Assigns the given value to the Main Stack Pointer (MSP).
lypinator 0:bb348c97df44 320 \param [in] topOfMainStack Main Stack Pointer value to set
lypinator 0:bb348c97df44 321 */
lypinator 0:bb348c97df44 322 __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
lypinator 0:bb348c97df44 323 {
lypinator 0:bb348c97df44 324 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
lypinator 0:bb348c97df44 325 }
lypinator 0:bb348c97df44 326
lypinator 0:bb348c97df44 327
lypinator 0:bb348c97df44 328 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 329 /**
lypinator 0:bb348c97df44 330 \brief Set Main Stack Pointer (non-secure)
lypinator 0:bb348c97df44 331 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
lypinator 0:bb348c97df44 332 \param [in] topOfMainStack Main Stack Pointer value to set
lypinator 0:bb348c97df44 333 */
lypinator 0:bb348c97df44 334 __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
lypinator 0:bb348c97df44 335 {
lypinator 0:bb348c97df44 336 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
lypinator 0:bb348c97df44 337 }
lypinator 0:bb348c97df44 338 #endif
lypinator 0:bb348c97df44 339
lypinator 0:bb348c97df44 340
lypinator 0:bb348c97df44 341 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 342 /**
lypinator 0:bb348c97df44 343 \brief Get Stack Pointer (non-secure)
lypinator 0:bb348c97df44 344 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
lypinator 0:bb348c97df44 345 \return SP Register value
lypinator 0:bb348c97df44 346 */
lypinator 0:bb348c97df44 347 __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
lypinator 0:bb348c97df44 348 {
lypinator 0:bb348c97df44 349 register uint32_t result;
lypinator 0:bb348c97df44 350
lypinator 0:bb348c97df44 351 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
lypinator 0:bb348c97df44 352 return(result);
lypinator 0:bb348c97df44 353 }
lypinator 0:bb348c97df44 354
lypinator 0:bb348c97df44 355
lypinator 0:bb348c97df44 356 /**
lypinator 0:bb348c97df44 357 \brief Set Stack Pointer (non-secure)
lypinator 0:bb348c97df44 358 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
lypinator 0:bb348c97df44 359 \param [in] topOfStack Stack Pointer value to set
lypinator 0:bb348c97df44 360 */
lypinator 0:bb348c97df44 361 __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
lypinator 0:bb348c97df44 362 {
lypinator 0:bb348c97df44 363 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
lypinator 0:bb348c97df44 364 }
lypinator 0:bb348c97df44 365 #endif
lypinator 0:bb348c97df44 366
lypinator 0:bb348c97df44 367
lypinator 0:bb348c97df44 368 /**
lypinator 0:bb348c97df44 369 \brief Get Priority Mask
lypinator 0:bb348c97df44 370 \details Returns the current state of the priority mask bit from the Priority Mask Register.
lypinator 0:bb348c97df44 371 \return Priority Mask value
lypinator 0:bb348c97df44 372 */
lypinator 0:bb348c97df44 373 __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
lypinator 0:bb348c97df44 374 {
lypinator 0:bb348c97df44 375 uint32_t result;
lypinator 0:bb348c97df44 376
lypinator 0:bb348c97df44 377 __ASM volatile ("MRS %0, primask" : "=r" (result) );
lypinator 0:bb348c97df44 378 return(result);
lypinator 0:bb348c97df44 379 }
lypinator 0:bb348c97df44 380
lypinator 0:bb348c97df44 381
lypinator 0:bb348c97df44 382 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 383 /**
lypinator 0:bb348c97df44 384 \brief Get Priority Mask (non-secure)
lypinator 0:bb348c97df44 385 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
lypinator 0:bb348c97df44 386 \return Priority Mask value
lypinator 0:bb348c97df44 387 */
lypinator 0:bb348c97df44 388 __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
lypinator 0:bb348c97df44 389 {
lypinator 0:bb348c97df44 390 uint32_t result;
lypinator 0:bb348c97df44 391
lypinator 0:bb348c97df44 392 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
lypinator 0:bb348c97df44 393 return(result);
lypinator 0:bb348c97df44 394 }
lypinator 0:bb348c97df44 395 #endif
lypinator 0:bb348c97df44 396
lypinator 0:bb348c97df44 397
lypinator 0:bb348c97df44 398 /**
lypinator 0:bb348c97df44 399 \brief Set Priority Mask
lypinator 0:bb348c97df44 400 \details Assigns the given value to the Priority Mask Register.
lypinator 0:bb348c97df44 401 \param [in] priMask Priority Mask
lypinator 0:bb348c97df44 402 */
lypinator 0:bb348c97df44 403 __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
lypinator 0:bb348c97df44 404 {
lypinator 0:bb348c97df44 405 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
lypinator 0:bb348c97df44 406 }
lypinator 0:bb348c97df44 407
lypinator 0:bb348c97df44 408
lypinator 0:bb348c97df44 409 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 410 /**
lypinator 0:bb348c97df44 411 \brief Set Priority Mask (non-secure)
lypinator 0:bb348c97df44 412 \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
lypinator 0:bb348c97df44 413 \param [in] priMask Priority Mask
lypinator 0:bb348c97df44 414 */
lypinator 0:bb348c97df44 415 __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
lypinator 0:bb348c97df44 416 {
lypinator 0:bb348c97df44 417 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
lypinator 0:bb348c97df44 418 }
lypinator 0:bb348c97df44 419 #endif
lypinator 0:bb348c97df44 420
lypinator 0:bb348c97df44 421
lypinator 0:bb348c97df44 422 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
lypinator 0:bb348c97df44 423 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 424 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
lypinator 0:bb348c97df44 425 /**
lypinator 0:bb348c97df44 426 \brief Enable FIQ
lypinator 0:bb348c97df44 427 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
lypinator 0:bb348c97df44 428 Can only be executed in Privileged modes.
lypinator 0:bb348c97df44 429 */
lypinator 0:bb348c97df44 430 #define __enable_fault_irq __enable_fiq /* see arm_compat.h */
lypinator 0:bb348c97df44 431
lypinator 0:bb348c97df44 432
lypinator 0:bb348c97df44 433 /**
lypinator 0:bb348c97df44 434 \brief Disable FIQ
lypinator 0:bb348c97df44 435 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
lypinator 0:bb348c97df44 436 Can only be executed in Privileged modes.
lypinator 0:bb348c97df44 437 */
lypinator 0:bb348c97df44 438 #define __disable_fault_irq __disable_fiq /* see arm_compat.h */
lypinator 0:bb348c97df44 439
lypinator 0:bb348c97df44 440
lypinator 0:bb348c97df44 441 /**
lypinator 0:bb348c97df44 442 \brief Get Base Priority
lypinator 0:bb348c97df44 443 \details Returns the current value of the Base Priority register.
lypinator 0:bb348c97df44 444 \return Base Priority register value
lypinator 0:bb348c97df44 445 */
lypinator 0:bb348c97df44 446 __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
lypinator 0:bb348c97df44 447 {
lypinator 0:bb348c97df44 448 uint32_t result;
lypinator 0:bb348c97df44 449
lypinator 0:bb348c97df44 450 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
lypinator 0:bb348c97df44 451 return(result);
lypinator 0:bb348c97df44 452 }
lypinator 0:bb348c97df44 453
lypinator 0:bb348c97df44 454
lypinator 0:bb348c97df44 455 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 456 /**
lypinator 0:bb348c97df44 457 \brief Get Base Priority (non-secure)
lypinator 0:bb348c97df44 458 \details Returns the current value of the non-secure Base Priority register when in secure state.
lypinator 0:bb348c97df44 459 \return Base Priority register value
lypinator 0:bb348c97df44 460 */
lypinator 0:bb348c97df44 461 __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
lypinator 0:bb348c97df44 462 {
lypinator 0:bb348c97df44 463 uint32_t result;
lypinator 0:bb348c97df44 464
lypinator 0:bb348c97df44 465 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
lypinator 0:bb348c97df44 466 return(result);
lypinator 0:bb348c97df44 467 }
lypinator 0:bb348c97df44 468 #endif
lypinator 0:bb348c97df44 469
lypinator 0:bb348c97df44 470
lypinator 0:bb348c97df44 471 /**
lypinator 0:bb348c97df44 472 \brief Set Base Priority
lypinator 0:bb348c97df44 473 \details Assigns the given value to the Base Priority register.
lypinator 0:bb348c97df44 474 \param [in] basePri Base Priority value to set
lypinator 0:bb348c97df44 475 */
lypinator 0:bb348c97df44 476 __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
lypinator 0:bb348c97df44 477 {
lypinator 0:bb348c97df44 478 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
lypinator 0:bb348c97df44 479 }
lypinator 0:bb348c97df44 480
lypinator 0:bb348c97df44 481
lypinator 0:bb348c97df44 482 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 483 /**
lypinator 0:bb348c97df44 484 \brief Set Base Priority (non-secure)
lypinator 0:bb348c97df44 485 \details Assigns the given value to the non-secure Base Priority register when in secure state.
lypinator 0:bb348c97df44 486 \param [in] basePri Base Priority value to set
lypinator 0:bb348c97df44 487 */
lypinator 0:bb348c97df44 488 __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
lypinator 0:bb348c97df44 489 {
lypinator 0:bb348c97df44 490 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
lypinator 0:bb348c97df44 491 }
lypinator 0:bb348c97df44 492 #endif
lypinator 0:bb348c97df44 493
lypinator 0:bb348c97df44 494
lypinator 0:bb348c97df44 495 /**
lypinator 0:bb348c97df44 496 \brief Set Base Priority with condition
lypinator 0:bb348c97df44 497 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
lypinator 0:bb348c97df44 498 or the new value increases the BASEPRI priority level.
lypinator 0:bb348c97df44 499 \param [in] basePri Base Priority value to set
lypinator 0:bb348c97df44 500 */
lypinator 0:bb348c97df44 501 __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
lypinator 0:bb348c97df44 502 {
lypinator 0:bb348c97df44 503 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
lypinator 0:bb348c97df44 504 }
lypinator 0:bb348c97df44 505
lypinator 0:bb348c97df44 506
lypinator 0:bb348c97df44 507 /**
lypinator 0:bb348c97df44 508 \brief Get Fault Mask
lypinator 0:bb348c97df44 509 \details Returns the current value of the Fault Mask register.
lypinator 0:bb348c97df44 510 \return Fault Mask register value
lypinator 0:bb348c97df44 511 */
lypinator 0:bb348c97df44 512 __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
lypinator 0:bb348c97df44 513 {
lypinator 0:bb348c97df44 514 uint32_t result;
lypinator 0:bb348c97df44 515
lypinator 0:bb348c97df44 516 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
lypinator 0:bb348c97df44 517 return(result);
lypinator 0:bb348c97df44 518 }
lypinator 0:bb348c97df44 519
lypinator 0:bb348c97df44 520
lypinator 0:bb348c97df44 521 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 522 /**
lypinator 0:bb348c97df44 523 \brief Get Fault Mask (non-secure)
lypinator 0:bb348c97df44 524 \details Returns the current value of the non-secure Fault Mask register when in secure state.
lypinator 0:bb348c97df44 525 \return Fault Mask register value
lypinator 0:bb348c97df44 526 */
lypinator 0:bb348c97df44 527 __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
lypinator 0:bb348c97df44 528 {
lypinator 0:bb348c97df44 529 uint32_t result;
lypinator 0:bb348c97df44 530
lypinator 0:bb348c97df44 531 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
lypinator 0:bb348c97df44 532 return(result);
lypinator 0:bb348c97df44 533 }
lypinator 0:bb348c97df44 534 #endif
lypinator 0:bb348c97df44 535
lypinator 0:bb348c97df44 536
lypinator 0:bb348c97df44 537 /**
lypinator 0:bb348c97df44 538 \brief Set Fault Mask
lypinator 0:bb348c97df44 539 \details Assigns the given value to the Fault Mask register.
lypinator 0:bb348c97df44 540 \param [in] faultMask Fault Mask value to set
lypinator 0:bb348c97df44 541 */
lypinator 0:bb348c97df44 542 __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
lypinator 0:bb348c97df44 543 {
lypinator 0:bb348c97df44 544 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
lypinator 0:bb348c97df44 545 }
lypinator 0:bb348c97df44 546
lypinator 0:bb348c97df44 547
lypinator 0:bb348c97df44 548 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 549 /**
lypinator 0:bb348c97df44 550 \brief Set Fault Mask (non-secure)
lypinator 0:bb348c97df44 551 \details Assigns the given value to the non-secure Fault Mask register when in secure state.
lypinator 0:bb348c97df44 552 \param [in] faultMask Fault Mask value to set
lypinator 0:bb348c97df44 553 */
lypinator 0:bb348c97df44 554 __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
lypinator 0:bb348c97df44 555 {
lypinator 0:bb348c97df44 556 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
lypinator 0:bb348c97df44 557 }
lypinator 0:bb348c97df44 558 #endif
lypinator 0:bb348c97df44 559
lypinator 0:bb348c97df44 560 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
lypinator 0:bb348c97df44 561 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 562 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
lypinator 0:bb348c97df44 563
lypinator 0:bb348c97df44 564
lypinator 0:bb348c97df44 565 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
lypinator 0:bb348c97df44 566 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
lypinator 0:bb348c97df44 567
lypinator 0:bb348c97df44 568 /**
lypinator 0:bb348c97df44 569 \brief Get Process Stack Pointer Limit
lypinator 0:bb348c97df44 570 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
lypinator 0:bb348c97df44 571 Stack Pointer Limit register hence zero is returned always in non-secure
lypinator 0:bb348c97df44 572 mode.
lypinator 0:bb348c97df44 573
lypinator 0:bb348c97df44 574 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
lypinator 0:bb348c97df44 575 \return PSPLIM Register value
lypinator 0:bb348c97df44 576 */
lypinator 0:bb348c97df44 577 __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
lypinator 0:bb348c97df44 578 {
lypinator 0:bb348c97df44 579 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
lypinator 0:bb348c97df44 580 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
lypinator 0:bb348c97df44 581 // without main extensions, the non-secure PSPLIM is RAZ/WI
lypinator 0:bb348c97df44 582 return 0U;
lypinator 0:bb348c97df44 583 #else
lypinator 0:bb348c97df44 584 register uint32_t result;
lypinator 0:bb348c97df44 585 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
lypinator 0:bb348c97df44 586 return result;
lypinator 0:bb348c97df44 587 #endif
lypinator 0:bb348c97df44 588 }
lypinator 0:bb348c97df44 589
lypinator 0:bb348c97df44 590 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 591 /**
lypinator 0:bb348c97df44 592 \brief Get Process Stack Pointer Limit (non-secure)
lypinator 0:bb348c97df44 593 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
lypinator 0:bb348c97df44 594 Stack Pointer Limit register hence zero is returned always in non-secure
lypinator 0:bb348c97df44 595 mode.
lypinator 0:bb348c97df44 596
lypinator 0:bb348c97df44 597 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
lypinator 0:bb348c97df44 598 \return PSPLIM Register value
lypinator 0:bb348c97df44 599 */
lypinator 0:bb348c97df44 600 __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
lypinator 0:bb348c97df44 601 {
lypinator 0:bb348c97df44 602 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
lypinator 0:bb348c97df44 603 // without main extensions, the non-secure PSPLIM is RAZ/WI
lypinator 0:bb348c97df44 604 return 0U;
lypinator 0:bb348c97df44 605 #else
lypinator 0:bb348c97df44 606 register uint32_t result;
lypinator 0:bb348c97df44 607 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
lypinator 0:bb348c97df44 608 return result;
lypinator 0:bb348c97df44 609 #endif
lypinator 0:bb348c97df44 610 }
lypinator 0:bb348c97df44 611 #endif
lypinator 0:bb348c97df44 612
lypinator 0:bb348c97df44 613
lypinator 0:bb348c97df44 614 /**
lypinator 0:bb348c97df44 615 \brief Set Process Stack Pointer Limit
lypinator 0:bb348c97df44 616 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
lypinator 0:bb348c97df44 617 Stack Pointer Limit register hence the write is silently ignored in non-secure
lypinator 0:bb348c97df44 618 mode.
lypinator 0:bb348c97df44 619
lypinator 0:bb348c97df44 620 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
lypinator 0:bb348c97df44 621 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
lypinator 0:bb348c97df44 622 */
lypinator 0:bb348c97df44 623 __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
lypinator 0:bb348c97df44 624 {
lypinator 0:bb348c97df44 625 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
lypinator 0:bb348c97df44 626 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
lypinator 0:bb348c97df44 627 // without main extensions, the non-secure PSPLIM is RAZ/WI
lypinator 0:bb348c97df44 628 (void)ProcStackPtrLimit;
lypinator 0:bb348c97df44 629 #else
lypinator 0:bb348c97df44 630 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
lypinator 0:bb348c97df44 631 #endif
lypinator 0:bb348c97df44 632 }
lypinator 0:bb348c97df44 633
lypinator 0:bb348c97df44 634
lypinator 0:bb348c97df44 635 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 636 /**
lypinator 0:bb348c97df44 637 \brief Set Process Stack Pointer (non-secure)
lypinator 0:bb348c97df44 638 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
lypinator 0:bb348c97df44 639 Stack Pointer Limit register hence the write is silently ignored in non-secure
lypinator 0:bb348c97df44 640 mode.
lypinator 0:bb348c97df44 641
lypinator 0:bb348c97df44 642 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
lypinator 0:bb348c97df44 643 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
lypinator 0:bb348c97df44 644 */
lypinator 0:bb348c97df44 645 __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
lypinator 0:bb348c97df44 646 {
lypinator 0:bb348c97df44 647 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
lypinator 0:bb348c97df44 648 // without main extensions, the non-secure PSPLIM is RAZ/WI
lypinator 0:bb348c97df44 649 (void)ProcStackPtrLimit;
lypinator 0:bb348c97df44 650 #else
lypinator 0:bb348c97df44 651 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
lypinator 0:bb348c97df44 652 #endif
lypinator 0:bb348c97df44 653 }
lypinator 0:bb348c97df44 654 #endif
lypinator 0:bb348c97df44 655
lypinator 0:bb348c97df44 656
lypinator 0:bb348c97df44 657 /**
lypinator 0:bb348c97df44 658 \brief Get Main Stack Pointer Limit
lypinator 0:bb348c97df44 659 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
lypinator 0:bb348c97df44 660 Stack Pointer Limit register hence zero is returned always.
lypinator 0:bb348c97df44 661
lypinator 0:bb348c97df44 662 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
lypinator 0:bb348c97df44 663 \return MSPLIM Register value
lypinator 0:bb348c97df44 664 */
lypinator 0:bb348c97df44 665 __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
lypinator 0:bb348c97df44 666 {
lypinator 0:bb348c97df44 667 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
lypinator 0:bb348c97df44 668 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
lypinator 0:bb348c97df44 669 // without main extensions, the non-secure MSPLIM is RAZ/WI
lypinator 0:bb348c97df44 670 return 0U;
lypinator 0:bb348c97df44 671 #else
lypinator 0:bb348c97df44 672 register uint32_t result;
lypinator 0:bb348c97df44 673 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
lypinator 0:bb348c97df44 674 return result;
lypinator 0:bb348c97df44 675 #endif
lypinator 0:bb348c97df44 676 }
lypinator 0:bb348c97df44 677
lypinator 0:bb348c97df44 678
lypinator 0:bb348c97df44 679 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 680 /**
lypinator 0:bb348c97df44 681 \brief Get Main Stack Pointer Limit (non-secure)
lypinator 0:bb348c97df44 682 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
lypinator 0:bb348c97df44 683 Stack Pointer Limit register hence zero is returned always.
lypinator 0:bb348c97df44 684
lypinator 0:bb348c97df44 685 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
lypinator 0:bb348c97df44 686 \return MSPLIM Register value
lypinator 0:bb348c97df44 687 */
lypinator 0:bb348c97df44 688 __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
lypinator 0:bb348c97df44 689 {
lypinator 0:bb348c97df44 690 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
lypinator 0:bb348c97df44 691 // without main extensions, the non-secure MSPLIM is RAZ/WI
lypinator 0:bb348c97df44 692 return 0U;
lypinator 0:bb348c97df44 693 #else
lypinator 0:bb348c97df44 694 register uint32_t result;
lypinator 0:bb348c97df44 695 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
lypinator 0:bb348c97df44 696 return result;
lypinator 0:bb348c97df44 697 #endif
lypinator 0:bb348c97df44 698 }
lypinator 0:bb348c97df44 699 #endif
lypinator 0:bb348c97df44 700
lypinator 0:bb348c97df44 701
lypinator 0:bb348c97df44 702 /**
lypinator 0:bb348c97df44 703 \brief Set Main Stack Pointer Limit
lypinator 0:bb348c97df44 704 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
lypinator 0:bb348c97df44 705 Stack Pointer Limit register hence the write is silently ignored.
lypinator 0:bb348c97df44 706
lypinator 0:bb348c97df44 707 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
lypinator 0:bb348c97df44 708 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
lypinator 0:bb348c97df44 709 */
lypinator 0:bb348c97df44 710 __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
lypinator 0:bb348c97df44 711 {
lypinator 0:bb348c97df44 712 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
lypinator 0:bb348c97df44 713 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
lypinator 0:bb348c97df44 714 // without main extensions, the non-secure MSPLIM is RAZ/WI
lypinator 0:bb348c97df44 715 (void)MainStackPtrLimit;
lypinator 0:bb348c97df44 716 #else
lypinator 0:bb348c97df44 717 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
lypinator 0:bb348c97df44 718 #endif
lypinator 0:bb348c97df44 719 }
lypinator 0:bb348c97df44 720
lypinator 0:bb348c97df44 721
lypinator 0:bb348c97df44 722 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
lypinator 0:bb348c97df44 723 /**
lypinator 0:bb348c97df44 724 \brief Set Main Stack Pointer Limit (non-secure)
lypinator 0:bb348c97df44 725 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
lypinator 0:bb348c97df44 726 Stack Pointer Limit register hence the write is silently ignored.
lypinator 0:bb348c97df44 727
lypinator 0:bb348c97df44 728 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
lypinator 0:bb348c97df44 729 \param [in] MainStackPtrLimit Main Stack Pointer value to set
lypinator 0:bb348c97df44 730 */
lypinator 0:bb348c97df44 731 __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
lypinator 0:bb348c97df44 732 {
lypinator 0:bb348c97df44 733 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
lypinator 0:bb348c97df44 734 // without main extensions, the non-secure MSPLIM is RAZ/WI
lypinator 0:bb348c97df44 735 (void)MainStackPtrLimit;
lypinator 0:bb348c97df44 736 #else
lypinator 0:bb348c97df44 737 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
lypinator 0:bb348c97df44 738 #endif
lypinator 0:bb348c97df44 739 }
lypinator 0:bb348c97df44 740 #endif
lypinator 0:bb348c97df44 741
lypinator 0:bb348c97df44 742 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
lypinator 0:bb348c97df44 743 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
lypinator 0:bb348c97df44 744
lypinator 0:bb348c97df44 745
lypinator 0:bb348c97df44 746 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 747 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
lypinator 0:bb348c97df44 748
lypinator 0:bb348c97df44 749 /**
lypinator 0:bb348c97df44 750 \brief Get FPSCR
lypinator 0:bb348c97df44 751 \details Returns the current value of the Floating Point Status/Control register.
lypinator 0:bb348c97df44 752 \return Floating Point Status/Control register value
lypinator 0:bb348c97df44 753 */
lypinator 0:bb348c97df44 754 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
lypinator 0:bb348c97df44 755 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
lypinator 0:bb348c97df44 756 #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
lypinator 0:bb348c97df44 757 #else
lypinator 0:bb348c97df44 758 #define __get_FPSCR() ((uint32_t)0U)
lypinator 0:bb348c97df44 759 #endif
lypinator 0:bb348c97df44 760
lypinator 0:bb348c97df44 761 /**
lypinator 0:bb348c97df44 762 \brief Set FPSCR
lypinator 0:bb348c97df44 763 \details Assigns the given value to the Floating Point Status/Control register.
lypinator 0:bb348c97df44 764 \param [in] fpscr Floating Point Status/Control value to set
lypinator 0:bb348c97df44 765 */
lypinator 0:bb348c97df44 766 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
lypinator 0:bb348c97df44 767 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
lypinator 0:bb348c97df44 768 #define __set_FPSCR __builtin_arm_set_fpscr
lypinator 0:bb348c97df44 769 #else
lypinator 0:bb348c97df44 770 #define __set_FPSCR(x) ((void)(x))
lypinator 0:bb348c97df44 771 #endif
lypinator 0:bb348c97df44 772
lypinator 0:bb348c97df44 773 #endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 774 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
lypinator 0:bb348c97df44 775
lypinator 0:bb348c97df44 776
lypinator 0:bb348c97df44 777
lypinator 0:bb348c97df44 778 /*@} end of CMSIS_Core_RegAccFunctions */
lypinator 0:bb348c97df44 779
lypinator 0:bb348c97df44 780
lypinator 0:bb348c97df44 781 /* ########################## Core Instruction Access ######################### */
lypinator 0:bb348c97df44 782 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
lypinator 0:bb348c97df44 783 Access to dedicated instructions
lypinator 0:bb348c97df44 784 @{
lypinator 0:bb348c97df44 785 */
lypinator 0:bb348c97df44 786
lypinator 0:bb348c97df44 787 /* Define macros for porting to both thumb1 and thumb2.
lypinator 0:bb348c97df44 788 * For thumb1, use low register (r0-r7), specified by constraint "l"
lypinator 0:bb348c97df44 789 * Otherwise, use general registers, specified by constraint "r" */
lypinator 0:bb348c97df44 790 #if defined (__thumb__) && !defined (__thumb2__)
lypinator 0:bb348c97df44 791 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
lypinator 0:bb348c97df44 792 #define __CMSIS_GCC_USE_REG(r) "l" (r)
lypinator 0:bb348c97df44 793 #else
lypinator 0:bb348c97df44 794 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
lypinator 0:bb348c97df44 795 #define __CMSIS_GCC_USE_REG(r) "r" (r)
lypinator 0:bb348c97df44 796 #endif
lypinator 0:bb348c97df44 797
lypinator 0:bb348c97df44 798 /**
lypinator 0:bb348c97df44 799 \brief No Operation
lypinator 0:bb348c97df44 800 \details No Operation does nothing. This instruction can be used for code alignment purposes.
lypinator 0:bb348c97df44 801 */
lypinator 0:bb348c97df44 802 #define __NOP __builtin_arm_nop
lypinator 0:bb348c97df44 803
lypinator 0:bb348c97df44 804 /**
lypinator 0:bb348c97df44 805 \brief Wait For Interrupt
lypinator 0:bb348c97df44 806 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
lypinator 0:bb348c97df44 807 */
lypinator 0:bb348c97df44 808 #define __WFI __builtin_arm_wfi
lypinator 0:bb348c97df44 809
lypinator 0:bb348c97df44 810
lypinator 0:bb348c97df44 811 /**
lypinator 0:bb348c97df44 812 \brief Wait For Event
lypinator 0:bb348c97df44 813 \details Wait For Event is a hint instruction that permits the processor to enter
lypinator 0:bb348c97df44 814 a low-power state until one of a number of events occurs.
lypinator 0:bb348c97df44 815 */
lypinator 0:bb348c97df44 816 #define __WFE __builtin_arm_wfe
lypinator 0:bb348c97df44 817
lypinator 0:bb348c97df44 818
lypinator 0:bb348c97df44 819 /**
lypinator 0:bb348c97df44 820 \brief Send Event
lypinator 0:bb348c97df44 821 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
lypinator 0:bb348c97df44 822 */
lypinator 0:bb348c97df44 823 #define __SEV __builtin_arm_sev
lypinator 0:bb348c97df44 824
lypinator 0:bb348c97df44 825
lypinator 0:bb348c97df44 826 /**
lypinator 0:bb348c97df44 827 \brief Instruction Synchronization Barrier
lypinator 0:bb348c97df44 828 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
lypinator 0:bb348c97df44 829 so that all instructions following the ISB are fetched from cache or memory,
lypinator 0:bb348c97df44 830 after the instruction has been completed.
lypinator 0:bb348c97df44 831 */
lypinator 0:bb348c97df44 832 #define __ISB() __builtin_arm_isb(0xF);
lypinator 0:bb348c97df44 833
lypinator 0:bb348c97df44 834 /**
lypinator 0:bb348c97df44 835 \brief Data Synchronization Barrier
lypinator 0:bb348c97df44 836 \details Acts as a special kind of Data Memory Barrier.
lypinator 0:bb348c97df44 837 It completes when all explicit memory accesses before this instruction complete.
lypinator 0:bb348c97df44 838 */
lypinator 0:bb348c97df44 839 #define __DSB() __builtin_arm_dsb(0xF);
lypinator 0:bb348c97df44 840
lypinator 0:bb348c97df44 841
lypinator 0:bb348c97df44 842 /**
lypinator 0:bb348c97df44 843 \brief Data Memory Barrier
lypinator 0:bb348c97df44 844 \details Ensures the apparent order of the explicit memory operations before
lypinator 0:bb348c97df44 845 and after the instruction, without ensuring their completion.
lypinator 0:bb348c97df44 846 */
lypinator 0:bb348c97df44 847 #define __DMB() __builtin_arm_dmb(0xF);
lypinator 0:bb348c97df44 848
lypinator 0:bb348c97df44 849
lypinator 0:bb348c97df44 850 /**
lypinator 0:bb348c97df44 851 \brief Reverse byte order (32 bit)
lypinator 0:bb348c97df44 852 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
lypinator 0:bb348c97df44 853 \param [in] value Value to reverse
lypinator 0:bb348c97df44 854 \return Reversed value
lypinator 0:bb348c97df44 855 */
lypinator 0:bb348c97df44 856 #define __REV(value) __builtin_bswap32(value)
lypinator 0:bb348c97df44 857
lypinator 0:bb348c97df44 858
lypinator 0:bb348c97df44 859 /**
lypinator 0:bb348c97df44 860 \brief Reverse byte order (16 bit)
lypinator 0:bb348c97df44 861 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
lypinator 0:bb348c97df44 862 \param [in] value Value to reverse
lypinator 0:bb348c97df44 863 \return Reversed value
lypinator 0:bb348c97df44 864 */
lypinator 0:bb348c97df44 865 #define __REV16(value) __ROR(__REV(value), 16)
lypinator 0:bb348c97df44 866
lypinator 0:bb348c97df44 867
lypinator 0:bb348c97df44 868 /**
lypinator 0:bb348c97df44 869 \brief Reverse byte order (16 bit)
lypinator 0:bb348c97df44 870 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
lypinator 0:bb348c97df44 871 \param [in] value Value to reverse
lypinator 0:bb348c97df44 872 \return Reversed value
lypinator 0:bb348c97df44 873 */
lypinator 0:bb348c97df44 874 #define __REVSH(value) (int16_t)__builtin_bswap16(value)
lypinator 0:bb348c97df44 875
lypinator 0:bb348c97df44 876
lypinator 0:bb348c97df44 877 /**
lypinator 0:bb348c97df44 878 \brief Rotate Right in unsigned value (32 bit)
lypinator 0:bb348c97df44 879 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
lypinator 0:bb348c97df44 880 \param [in] op1 Value to rotate
lypinator 0:bb348c97df44 881 \param [in] op2 Number of Bits to rotate
lypinator 0:bb348c97df44 882 \return Rotated value
lypinator 0:bb348c97df44 883 */
lypinator 0:bb348c97df44 884 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 885 {
lypinator 0:bb348c97df44 886 op2 %= 32U;
lypinator 0:bb348c97df44 887 if (op2 == 0U)
lypinator 0:bb348c97df44 888 {
lypinator 0:bb348c97df44 889 return op1;
lypinator 0:bb348c97df44 890 }
lypinator 0:bb348c97df44 891 return (op1 >> op2) | (op1 << (32U - op2));
lypinator 0:bb348c97df44 892 }
lypinator 0:bb348c97df44 893
lypinator 0:bb348c97df44 894
lypinator 0:bb348c97df44 895 /**
lypinator 0:bb348c97df44 896 \brief Breakpoint
lypinator 0:bb348c97df44 897 \details Causes the processor to enter Debug state.
lypinator 0:bb348c97df44 898 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
lypinator 0:bb348c97df44 899 \param [in] value is ignored by the processor.
lypinator 0:bb348c97df44 900 If required, a debugger can use it to store additional information about the breakpoint.
lypinator 0:bb348c97df44 901 */
lypinator 0:bb348c97df44 902 #define __BKPT(value) __ASM volatile ("bkpt "#value)
lypinator 0:bb348c97df44 903
lypinator 0:bb348c97df44 904
lypinator 0:bb348c97df44 905 /**
lypinator 0:bb348c97df44 906 \brief Reverse bit order of value
lypinator 0:bb348c97df44 907 \details Reverses the bit order of the given value.
lypinator 0:bb348c97df44 908 \param [in] value Value to reverse
lypinator 0:bb348c97df44 909 \return Reversed value
lypinator 0:bb348c97df44 910 */
lypinator 0:bb348c97df44 911 #define __RBIT __builtin_arm_rbit
lypinator 0:bb348c97df44 912
lypinator 0:bb348c97df44 913 /**
lypinator 0:bb348c97df44 914 \brief Count leading zeros
lypinator 0:bb348c97df44 915 \details Counts the number of leading zeros of a data value.
lypinator 0:bb348c97df44 916 \param [in] value Value to count the leading zeros
lypinator 0:bb348c97df44 917 \return number of leading zeros in value
lypinator 0:bb348c97df44 918 */
lypinator 0:bb348c97df44 919 #define __CLZ (uint8_t)__builtin_clz
lypinator 0:bb348c97df44 920
lypinator 0:bb348c97df44 921
lypinator 0:bb348c97df44 922 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
lypinator 0:bb348c97df44 923 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 924 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
lypinator 0:bb348c97df44 925 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
lypinator 0:bb348c97df44 926 /**
lypinator 0:bb348c97df44 927 \brief LDR Exclusive (8 bit)
lypinator 0:bb348c97df44 928 \details Executes a exclusive LDR instruction for 8 bit value.
lypinator 0:bb348c97df44 929 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 930 \return value of type uint8_t at (*ptr)
lypinator 0:bb348c97df44 931 */
lypinator 0:bb348c97df44 932 #define __LDREXB (uint8_t)__builtin_arm_ldrex
lypinator 0:bb348c97df44 933
lypinator 0:bb348c97df44 934
lypinator 0:bb348c97df44 935 /**
lypinator 0:bb348c97df44 936 \brief LDR Exclusive (16 bit)
lypinator 0:bb348c97df44 937 \details Executes a exclusive LDR instruction for 16 bit values.
lypinator 0:bb348c97df44 938 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 939 \return value of type uint16_t at (*ptr)
lypinator 0:bb348c97df44 940 */
lypinator 0:bb348c97df44 941 #define __LDREXH (uint16_t)__builtin_arm_ldrex
lypinator 0:bb348c97df44 942
lypinator 0:bb348c97df44 943
lypinator 0:bb348c97df44 944 /**
lypinator 0:bb348c97df44 945 \brief LDR Exclusive (32 bit)
lypinator 0:bb348c97df44 946 \details Executes a exclusive LDR instruction for 32 bit values.
lypinator 0:bb348c97df44 947 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 948 \return value of type uint32_t at (*ptr)
lypinator 0:bb348c97df44 949 */
lypinator 0:bb348c97df44 950 #define __LDREXW (uint32_t)__builtin_arm_ldrex
lypinator 0:bb348c97df44 951
lypinator 0:bb348c97df44 952
lypinator 0:bb348c97df44 953 /**
lypinator 0:bb348c97df44 954 \brief STR Exclusive (8 bit)
lypinator 0:bb348c97df44 955 \details Executes a exclusive STR instruction for 8 bit values.
lypinator 0:bb348c97df44 956 \param [in] value Value to store
lypinator 0:bb348c97df44 957 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 958 \return 0 Function succeeded
lypinator 0:bb348c97df44 959 \return 1 Function failed
lypinator 0:bb348c97df44 960 */
lypinator 0:bb348c97df44 961 #define __STREXB (uint32_t)__builtin_arm_strex
lypinator 0:bb348c97df44 962
lypinator 0:bb348c97df44 963
lypinator 0:bb348c97df44 964 /**
lypinator 0:bb348c97df44 965 \brief STR Exclusive (16 bit)
lypinator 0:bb348c97df44 966 \details Executes a exclusive STR instruction for 16 bit values.
lypinator 0:bb348c97df44 967 \param [in] value Value to store
lypinator 0:bb348c97df44 968 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 969 \return 0 Function succeeded
lypinator 0:bb348c97df44 970 \return 1 Function failed
lypinator 0:bb348c97df44 971 */
lypinator 0:bb348c97df44 972 #define __STREXH (uint32_t)__builtin_arm_strex
lypinator 0:bb348c97df44 973
lypinator 0:bb348c97df44 974
lypinator 0:bb348c97df44 975 /**
lypinator 0:bb348c97df44 976 \brief STR Exclusive (32 bit)
lypinator 0:bb348c97df44 977 \details Executes a exclusive STR instruction for 32 bit values.
lypinator 0:bb348c97df44 978 \param [in] value Value to store
lypinator 0:bb348c97df44 979 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 980 \return 0 Function succeeded
lypinator 0:bb348c97df44 981 \return 1 Function failed
lypinator 0:bb348c97df44 982 */
lypinator 0:bb348c97df44 983 #define __STREXW (uint32_t)__builtin_arm_strex
lypinator 0:bb348c97df44 984
lypinator 0:bb348c97df44 985
lypinator 0:bb348c97df44 986 /**
lypinator 0:bb348c97df44 987 \brief Remove the exclusive lock
lypinator 0:bb348c97df44 988 \details Removes the exclusive lock which is created by LDREX.
lypinator 0:bb348c97df44 989 */
lypinator 0:bb348c97df44 990 #define __CLREX __builtin_arm_clrex
lypinator 0:bb348c97df44 991
lypinator 0:bb348c97df44 992 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
lypinator 0:bb348c97df44 993 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 994 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
lypinator 0:bb348c97df44 995 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
lypinator 0:bb348c97df44 996
lypinator 0:bb348c97df44 997
lypinator 0:bb348c97df44 998 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
lypinator 0:bb348c97df44 999 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 1000 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
lypinator 0:bb348c97df44 1001
lypinator 0:bb348c97df44 1002 /**
lypinator 0:bb348c97df44 1003 \brief Signed Saturate
lypinator 0:bb348c97df44 1004 \details Saturates a signed value.
lypinator 0:bb348c97df44 1005 \param [in] value Value to be saturated
lypinator 0:bb348c97df44 1006 \param [in] sat Bit position to saturate to (1..32)
lypinator 0:bb348c97df44 1007 \return Saturated value
lypinator 0:bb348c97df44 1008 */
lypinator 0:bb348c97df44 1009 #define __SSAT __builtin_arm_ssat
lypinator 0:bb348c97df44 1010
lypinator 0:bb348c97df44 1011
lypinator 0:bb348c97df44 1012 /**
lypinator 0:bb348c97df44 1013 \brief Unsigned Saturate
lypinator 0:bb348c97df44 1014 \details Saturates an unsigned value.
lypinator 0:bb348c97df44 1015 \param [in] value Value to be saturated
lypinator 0:bb348c97df44 1016 \param [in] sat Bit position to saturate to (0..31)
lypinator 0:bb348c97df44 1017 \return Saturated value
lypinator 0:bb348c97df44 1018 */
lypinator 0:bb348c97df44 1019 #define __USAT __builtin_arm_usat
lypinator 0:bb348c97df44 1020
lypinator 0:bb348c97df44 1021
lypinator 0:bb348c97df44 1022 /**
lypinator 0:bb348c97df44 1023 \brief Rotate Right with Extend (32 bit)
lypinator 0:bb348c97df44 1024 \details Moves each bit of a bitstring right by one bit.
lypinator 0:bb348c97df44 1025 The carry input is shifted in at the left end of the bitstring.
lypinator 0:bb348c97df44 1026 \param [in] value Value to rotate
lypinator 0:bb348c97df44 1027 \return Rotated value
lypinator 0:bb348c97df44 1028 */
lypinator 0:bb348c97df44 1029 __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
lypinator 0:bb348c97df44 1030 {
lypinator 0:bb348c97df44 1031 uint32_t result;
lypinator 0:bb348c97df44 1032
lypinator 0:bb348c97df44 1033 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
lypinator 0:bb348c97df44 1034 return(result);
lypinator 0:bb348c97df44 1035 }
lypinator 0:bb348c97df44 1036
lypinator 0:bb348c97df44 1037
lypinator 0:bb348c97df44 1038 /**
lypinator 0:bb348c97df44 1039 \brief LDRT Unprivileged (8 bit)
lypinator 0:bb348c97df44 1040 \details Executes a Unprivileged LDRT instruction for 8 bit value.
lypinator 0:bb348c97df44 1041 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1042 \return value of type uint8_t at (*ptr)
lypinator 0:bb348c97df44 1043 */
lypinator 0:bb348c97df44 1044 __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
lypinator 0:bb348c97df44 1045 {
lypinator 0:bb348c97df44 1046 uint32_t result;
lypinator 0:bb348c97df44 1047
lypinator 0:bb348c97df44 1048 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
lypinator 0:bb348c97df44 1049 return ((uint8_t) result); /* Add explicit type cast here */
lypinator 0:bb348c97df44 1050 }
lypinator 0:bb348c97df44 1051
lypinator 0:bb348c97df44 1052
lypinator 0:bb348c97df44 1053 /**
lypinator 0:bb348c97df44 1054 \brief LDRT Unprivileged (16 bit)
lypinator 0:bb348c97df44 1055 \details Executes a Unprivileged LDRT instruction for 16 bit values.
lypinator 0:bb348c97df44 1056 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1057 \return value of type uint16_t at (*ptr)
lypinator 0:bb348c97df44 1058 */
lypinator 0:bb348c97df44 1059 __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
lypinator 0:bb348c97df44 1060 {
lypinator 0:bb348c97df44 1061 uint32_t result;
lypinator 0:bb348c97df44 1062
lypinator 0:bb348c97df44 1063 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
lypinator 0:bb348c97df44 1064 return ((uint16_t) result); /* Add explicit type cast here */
lypinator 0:bb348c97df44 1065 }
lypinator 0:bb348c97df44 1066
lypinator 0:bb348c97df44 1067
lypinator 0:bb348c97df44 1068 /**
lypinator 0:bb348c97df44 1069 \brief LDRT Unprivileged (32 bit)
lypinator 0:bb348c97df44 1070 \details Executes a Unprivileged LDRT instruction for 32 bit values.
lypinator 0:bb348c97df44 1071 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1072 \return value of type uint32_t at (*ptr)
lypinator 0:bb348c97df44 1073 */
lypinator 0:bb348c97df44 1074 __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
lypinator 0:bb348c97df44 1075 {
lypinator 0:bb348c97df44 1076 uint32_t result;
lypinator 0:bb348c97df44 1077
lypinator 0:bb348c97df44 1078 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
lypinator 0:bb348c97df44 1079 return(result);
lypinator 0:bb348c97df44 1080 }
lypinator 0:bb348c97df44 1081
lypinator 0:bb348c97df44 1082
lypinator 0:bb348c97df44 1083 /**
lypinator 0:bb348c97df44 1084 \brief STRT Unprivileged (8 bit)
lypinator 0:bb348c97df44 1085 \details Executes a Unprivileged STRT instruction for 8 bit values.
lypinator 0:bb348c97df44 1086 \param [in] value Value to store
lypinator 0:bb348c97df44 1087 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1088 */
lypinator 0:bb348c97df44 1089 __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
lypinator 0:bb348c97df44 1090 {
lypinator 0:bb348c97df44 1091 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
lypinator 0:bb348c97df44 1092 }
lypinator 0:bb348c97df44 1093
lypinator 0:bb348c97df44 1094
lypinator 0:bb348c97df44 1095 /**
lypinator 0:bb348c97df44 1096 \brief STRT Unprivileged (16 bit)
lypinator 0:bb348c97df44 1097 \details Executes a Unprivileged STRT instruction for 16 bit values.
lypinator 0:bb348c97df44 1098 \param [in] value Value to store
lypinator 0:bb348c97df44 1099 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1100 */
lypinator 0:bb348c97df44 1101 __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
lypinator 0:bb348c97df44 1102 {
lypinator 0:bb348c97df44 1103 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
lypinator 0:bb348c97df44 1104 }
lypinator 0:bb348c97df44 1105
lypinator 0:bb348c97df44 1106
lypinator 0:bb348c97df44 1107 /**
lypinator 0:bb348c97df44 1108 \brief STRT Unprivileged (32 bit)
lypinator 0:bb348c97df44 1109 \details Executes a Unprivileged STRT instruction for 32 bit values.
lypinator 0:bb348c97df44 1110 \param [in] value Value to store
lypinator 0:bb348c97df44 1111 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1112 */
lypinator 0:bb348c97df44 1113 __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
lypinator 0:bb348c97df44 1114 {
lypinator 0:bb348c97df44 1115 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
lypinator 0:bb348c97df44 1116 }
lypinator 0:bb348c97df44 1117
lypinator 0:bb348c97df44 1118 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
lypinator 0:bb348c97df44 1119 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 1120 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
lypinator 0:bb348c97df44 1121
lypinator 0:bb348c97df44 1122 /**
lypinator 0:bb348c97df44 1123 \brief Signed Saturate
lypinator 0:bb348c97df44 1124 \details Saturates a signed value.
lypinator 0:bb348c97df44 1125 \param [in] value Value to be saturated
lypinator 0:bb348c97df44 1126 \param [in] sat Bit position to saturate to (1..32)
lypinator 0:bb348c97df44 1127 \return Saturated value
lypinator 0:bb348c97df44 1128 */
lypinator 0:bb348c97df44 1129 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
lypinator 0:bb348c97df44 1130 {
lypinator 0:bb348c97df44 1131 if ((sat >= 1U) && (sat <= 32U))
lypinator 0:bb348c97df44 1132 {
lypinator 0:bb348c97df44 1133 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
lypinator 0:bb348c97df44 1134 const int32_t min = -1 - max ;
lypinator 0:bb348c97df44 1135 if (val > max)
lypinator 0:bb348c97df44 1136 {
lypinator 0:bb348c97df44 1137 return max;
lypinator 0:bb348c97df44 1138 }
lypinator 0:bb348c97df44 1139 else if (val < min)
lypinator 0:bb348c97df44 1140 {
lypinator 0:bb348c97df44 1141 return min;
lypinator 0:bb348c97df44 1142 }
lypinator 0:bb348c97df44 1143 }
lypinator 0:bb348c97df44 1144 return val;
lypinator 0:bb348c97df44 1145 }
lypinator 0:bb348c97df44 1146
lypinator 0:bb348c97df44 1147 /**
lypinator 0:bb348c97df44 1148 \brief Unsigned Saturate
lypinator 0:bb348c97df44 1149 \details Saturates an unsigned value.
lypinator 0:bb348c97df44 1150 \param [in] value Value to be saturated
lypinator 0:bb348c97df44 1151 \param [in] sat Bit position to saturate to (0..31)
lypinator 0:bb348c97df44 1152 \return Saturated value
lypinator 0:bb348c97df44 1153 */
lypinator 0:bb348c97df44 1154 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
lypinator 0:bb348c97df44 1155 {
lypinator 0:bb348c97df44 1156 if (sat <= 31U)
lypinator 0:bb348c97df44 1157 {
lypinator 0:bb348c97df44 1158 const uint32_t max = ((1U << sat) - 1U);
lypinator 0:bb348c97df44 1159 if (val > (int32_t)max)
lypinator 0:bb348c97df44 1160 {
lypinator 0:bb348c97df44 1161 return max;
lypinator 0:bb348c97df44 1162 }
lypinator 0:bb348c97df44 1163 else if (val < 0)
lypinator 0:bb348c97df44 1164 {
lypinator 0:bb348c97df44 1165 return 0U;
lypinator 0:bb348c97df44 1166 }
lypinator 0:bb348c97df44 1167 }
lypinator 0:bb348c97df44 1168 return (uint32_t)val;
lypinator 0:bb348c97df44 1169 }
lypinator 0:bb348c97df44 1170
lypinator 0:bb348c97df44 1171 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
lypinator 0:bb348c97df44 1172 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 1173 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
lypinator 0:bb348c97df44 1174
lypinator 0:bb348c97df44 1175
lypinator 0:bb348c97df44 1176 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
lypinator 0:bb348c97df44 1177 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
lypinator 0:bb348c97df44 1178 /**
lypinator 0:bb348c97df44 1179 \brief Load-Acquire (8 bit)
lypinator 0:bb348c97df44 1180 \details Executes a LDAB instruction for 8 bit value.
lypinator 0:bb348c97df44 1181 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1182 \return value of type uint8_t at (*ptr)
lypinator 0:bb348c97df44 1183 */
lypinator 0:bb348c97df44 1184 __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
lypinator 0:bb348c97df44 1185 {
lypinator 0:bb348c97df44 1186 uint32_t result;
lypinator 0:bb348c97df44 1187
lypinator 0:bb348c97df44 1188 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
lypinator 0:bb348c97df44 1189 return ((uint8_t) result);
lypinator 0:bb348c97df44 1190 }
lypinator 0:bb348c97df44 1191
lypinator 0:bb348c97df44 1192
lypinator 0:bb348c97df44 1193 /**
lypinator 0:bb348c97df44 1194 \brief Load-Acquire (16 bit)
lypinator 0:bb348c97df44 1195 \details Executes a LDAH instruction for 16 bit values.
lypinator 0:bb348c97df44 1196 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1197 \return value of type uint16_t at (*ptr)
lypinator 0:bb348c97df44 1198 */
lypinator 0:bb348c97df44 1199 __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
lypinator 0:bb348c97df44 1200 {
lypinator 0:bb348c97df44 1201 uint32_t result;
lypinator 0:bb348c97df44 1202
lypinator 0:bb348c97df44 1203 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
lypinator 0:bb348c97df44 1204 return ((uint16_t) result);
lypinator 0:bb348c97df44 1205 }
lypinator 0:bb348c97df44 1206
lypinator 0:bb348c97df44 1207
lypinator 0:bb348c97df44 1208 /**
lypinator 0:bb348c97df44 1209 \brief Load-Acquire (32 bit)
lypinator 0:bb348c97df44 1210 \details Executes a LDA instruction for 32 bit values.
lypinator 0:bb348c97df44 1211 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1212 \return value of type uint32_t at (*ptr)
lypinator 0:bb348c97df44 1213 */
lypinator 0:bb348c97df44 1214 __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
lypinator 0:bb348c97df44 1215 {
lypinator 0:bb348c97df44 1216 uint32_t result;
lypinator 0:bb348c97df44 1217
lypinator 0:bb348c97df44 1218 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
lypinator 0:bb348c97df44 1219 return(result);
lypinator 0:bb348c97df44 1220 }
lypinator 0:bb348c97df44 1221
lypinator 0:bb348c97df44 1222
lypinator 0:bb348c97df44 1223 /**
lypinator 0:bb348c97df44 1224 \brief Store-Release (8 bit)
lypinator 0:bb348c97df44 1225 \details Executes a STLB instruction for 8 bit values.
lypinator 0:bb348c97df44 1226 \param [in] value Value to store
lypinator 0:bb348c97df44 1227 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1228 */
lypinator 0:bb348c97df44 1229 __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
lypinator 0:bb348c97df44 1230 {
lypinator 0:bb348c97df44 1231 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
lypinator 0:bb348c97df44 1232 }
lypinator 0:bb348c97df44 1233
lypinator 0:bb348c97df44 1234
lypinator 0:bb348c97df44 1235 /**
lypinator 0:bb348c97df44 1236 \brief Store-Release (16 bit)
lypinator 0:bb348c97df44 1237 \details Executes a STLH instruction for 16 bit values.
lypinator 0:bb348c97df44 1238 \param [in] value Value to store
lypinator 0:bb348c97df44 1239 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1240 */
lypinator 0:bb348c97df44 1241 __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
lypinator 0:bb348c97df44 1242 {
lypinator 0:bb348c97df44 1243 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
lypinator 0:bb348c97df44 1244 }
lypinator 0:bb348c97df44 1245
lypinator 0:bb348c97df44 1246
lypinator 0:bb348c97df44 1247 /**
lypinator 0:bb348c97df44 1248 \brief Store-Release (32 bit)
lypinator 0:bb348c97df44 1249 \details Executes a STL instruction for 32 bit values.
lypinator 0:bb348c97df44 1250 \param [in] value Value to store
lypinator 0:bb348c97df44 1251 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1252 */
lypinator 0:bb348c97df44 1253 __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
lypinator 0:bb348c97df44 1254 {
lypinator 0:bb348c97df44 1255 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
lypinator 0:bb348c97df44 1256 }
lypinator 0:bb348c97df44 1257
lypinator 0:bb348c97df44 1258
lypinator 0:bb348c97df44 1259 /**
lypinator 0:bb348c97df44 1260 \brief Load-Acquire Exclusive (8 bit)
lypinator 0:bb348c97df44 1261 \details Executes a LDAB exclusive instruction for 8 bit value.
lypinator 0:bb348c97df44 1262 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1263 \return value of type uint8_t at (*ptr)
lypinator 0:bb348c97df44 1264 */
lypinator 0:bb348c97df44 1265 #define __LDAEXB (uint8_t)__builtin_arm_ldaex
lypinator 0:bb348c97df44 1266
lypinator 0:bb348c97df44 1267
lypinator 0:bb348c97df44 1268 /**
lypinator 0:bb348c97df44 1269 \brief Load-Acquire Exclusive (16 bit)
lypinator 0:bb348c97df44 1270 \details Executes a LDAH exclusive instruction for 16 bit values.
lypinator 0:bb348c97df44 1271 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1272 \return value of type uint16_t at (*ptr)
lypinator 0:bb348c97df44 1273 */
lypinator 0:bb348c97df44 1274 #define __LDAEXH (uint16_t)__builtin_arm_ldaex
lypinator 0:bb348c97df44 1275
lypinator 0:bb348c97df44 1276
lypinator 0:bb348c97df44 1277 /**
lypinator 0:bb348c97df44 1278 \brief Load-Acquire Exclusive (32 bit)
lypinator 0:bb348c97df44 1279 \details Executes a LDA exclusive instruction for 32 bit values.
lypinator 0:bb348c97df44 1280 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 1281 \return value of type uint32_t at (*ptr)
lypinator 0:bb348c97df44 1282 */
lypinator 0:bb348c97df44 1283 #define __LDAEX (uint32_t)__builtin_arm_ldaex
lypinator 0:bb348c97df44 1284
lypinator 0:bb348c97df44 1285
lypinator 0:bb348c97df44 1286 /**
lypinator 0:bb348c97df44 1287 \brief Store-Release Exclusive (8 bit)
lypinator 0:bb348c97df44 1288 \details Executes a STLB exclusive instruction for 8 bit values.
lypinator 0:bb348c97df44 1289 \param [in] value Value to store
lypinator 0:bb348c97df44 1290 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1291 \return 0 Function succeeded
lypinator 0:bb348c97df44 1292 \return 1 Function failed
lypinator 0:bb348c97df44 1293 */
lypinator 0:bb348c97df44 1294 #define __STLEXB (uint32_t)__builtin_arm_stlex
lypinator 0:bb348c97df44 1295
lypinator 0:bb348c97df44 1296
lypinator 0:bb348c97df44 1297 /**
lypinator 0:bb348c97df44 1298 \brief Store-Release Exclusive (16 bit)
lypinator 0:bb348c97df44 1299 \details Executes a STLH exclusive instruction for 16 bit values.
lypinator 0:bb348c97df44 1300 \param [in] value Value to store
lypinator 0:bb348c97df44 1301 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1302 \return 0 Function succeeded
lypinator 0:bb348c97df44 1303 \return 1 Function failed
lypinator 0:bb348c97df44 1304 */
lypinator 0:bb348c97df44 1305 #define __STLEXH (uint32_t)__builtin_arm_stlex
lypinator 0:bb348c97df44 1306
lypinator 0:bb348c97df44 1307
lypinator 0:bb348c97df44 1308 /**
lypinator 0:bb348c97df44 1309 \brief Store-Release Exclusive (32 bit)
lypinator 0:bb348c97df44 1310 \details Executes a STL exclusive instruction for 32 bit values.
lypinator 0:bb348c97df44 1311 \param [in] value Value to store
lypinator 0:bb348c97df44 1312 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 1313 \return 0 Function succeeded
lypinator 0:bb348c97df44 1314 \return 1 Function failed
lypinator 0:bb348c97df44 1315 */
lypinator 0:bb348c97df44 1316 #define __STLEX (uint32_t)__builtin_arm_stlex
lypinator 0:bb348c97df44 1317
lypinator 0:bb348c97df44 1318 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
lypinator 0:bb348c97df44 1319 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
lypinator 0:bb348c97df44 1320
lypinator 0:bb348c97df44 1321 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
lypinator 0:bb348c97df44 1322
lypinator 0:bb348c97df44 1323
lypinator 0:bb348c97df44 1324 /* ################### Compiler specific Intrinsics ########################### */
lypinator 0:bb348c97df44 1325 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
lypinator 0:bb348c97df44 1326 Access to dedicated SIMD instructions
lypinator 0:bb348c97df44 1327 @{
lypinator 0:bb348c97df44 1328 */
lypinator 0:bb348c97df44 1329
lypinator 0:bb348c97df44 1330 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
lypinator 0:bb348c97df44 1331
lypinator 0:bb348c97df44 1332 __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1333 {
lypinator 0:bb348c97df44 1334 uint32_t result;
lypinator 0:bb348c97df44 1335
lypinator 0:bb348c97df44 1336 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1337 return(result);
lypinator 0:bb348c97df44 1338 }
lypinator 0:bb348c97df44 1339
lypinator 0:bb348c97df44 1340 __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1341 {
lypinator 0:bb348c97df44 1342 uint32_t result;
lypinator 0:bb348c97df44 1343
lypinator 0:bb348c97df44 1344 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1345 return(result);
lypinator 0:bb348c97df44 1346 }
lypinator 0:bb348c97df44 1347
lypinator 0:bb348c97df44 1348 __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1349 {
lypinator 0:bb348c97df44 1350 uint32_t result;
lypinator 0:bb348c97df44 1351
lypinator 0:bb348c97df44 1352 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1353 return(result);
lypinator 0:bb348c97df44 1354 }
lypinator 0:bb348c97df44 1355
lypinator 0:bb348c97df44 1356 __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1357 {
lypinator 0:bb348c97df44 1358 uint32_t result;
lypinator 0:bb348c97df44 1359
lypinator 0:bb348c97df44 1360 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1361 return(result);
lypinator 0:bb348c97df44 1362 }
lypinator 0:bb348c97df44 1363
lypinator 0:bb348c97df44 1364 __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1365 {
lypinator 0:bb348c97df44 1366 uint32_t result;
lypinator 0:bb348c97df44 1367
lypinator 0:bb348c97df44 1368 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1369 return(result);
lypinator 0:bb348c97df44 1370 }
lypinator 0:bb348c97df44 1371
lypinator 0:bb348c97df44 1372 __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1373 {
lypinator 0:bb348c97df44 1374 uint32_t result;
lypinator 0:bb348c97df44 1375
lypinator 0:bb348c97df44 1376 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1377 return(result);
lypinator 0:bb348c97df44 1378 }
lypinator 0:bb348c97df44 1379
lypinator 0:bb348c97df44 1380
lypinator 0:bb348c97df44 1381 __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1382 {
lypinator 0:bb348c97df44 1383 uint32_t result;
lypinator 0:bb348c97df44 1384
lypinator 0:bb348c97df44 1385 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1386 return(result);
lypinator 0:bb348c97df44 1387 }
lypinator 0:bb348c97df44 1388
lypinator 0:bb348c97df44 1389 __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1390 {
lypinator 0:bb348c97df44 1391 uint32_t result;
lypinator 0:bb348c97df44 1392
lypinator 0:bb348c97df44 1393 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1394 return(result);
lypinator 0:bb348c97df44 1395 }
lypinator 0:bb348c97df44 1396
lypinator 0:bb348c97df44 1397 __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1398 {
lypinator 0:bb348c97df44 1399 uint32_t result;
lypinator 0:bb348c97df44 1400
lypinator 0:bb348c97df44 1401 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1402 return(result);
lypinator 0:bb348c97df44 1403 }
lypinator 0:bb348c97df44 1404
lypinator 0:bb348c97df44 1405 __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1406 {
lypinator 0:bb348c97df44 1407 uint32_t result;
lypinator 0:bb348c97df44 1408
lypinator 0:bb348c97df44 1409 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1410 return(result);
lypinator 0:bb348c97df44 1411 }
lypinator 0:bb348c97df44 1412
lypinator 0:bb348c97df44 1413 __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1414 {
lypinator 0:bb348c97df44 1415 uint32_t result;
lypinator 0:bb348c97df44 1416
lypinator 0:bb348c97df44 1417 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1418 return(result);
lypinator 0:bb348c97df44 1419 }
lypinator 0:bb348c97df44 1420
lypinator 0:bb348c97df44 1421 __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1422 {
lypinator 0:bb348c97df44 1423 uint32_t result;
lypinator 0:bb348c97df44 1424
lypinator 0:bb348c97df44 1425 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1426 return(result);
lypinator 0:bb348c97df44 1427 }
lypinator 0:bb348c97df44 1428
lypinator 0:bb348c97df44 1429
lypinator 0:bb348c97df44 1430 __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1431 {
lypinator 0:bb348c97df44 1432 uint32_t result;
lypinator 0:bb348c97df44 1433
lypinator 0:bb348c97df44 1434 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1435 return(result);
lypinator 0:bb348c97df44 1436 }
lypinator 0:bb348c97df44 1437
lypinator 0:bb348c97df44 1438 __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1439 {
lypinator 0:bb348c97df44 1440 uint32_t result;
lypinator 0:bb348c97df44 1441
lypinator 0:bb348c97df44 1442 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1443 return(result);
lypinator 0:bb348c97df44 1444 }
lypinator 0:bb348c97df44 1445
lypinator 0:bb348c97df44 1446 __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1447 {
lypinator 0:bb348c97df44 1448 uint32_t result;
lypinator 0:bb348c97df44 1449
lypinator 0:bb348c97df44 1450 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1451 return(result);
lypinator 0:bb348c97df44 1452 }
lypinator 0:bb348c97df44 1453
lypinator 0:bb348c97df44 1454 __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1455 {
lypinator 0:bb348c97df44 1456 uint32_t result;
lypinator 0:bb348c97df44 1457
lypinator 0:bb348c97df44 1458 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1459 return(result);
lypinator 0:bb348c97df44 1460 }
lypinator 0:bb348c97df44 1461
lypinator 0:bb348c97df44 1462 __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1463 {
lypinator 0:bb348c97df44 1464 uint32_t result;
lypinator 0:bb348c97df44 1465
lypinator 0:bb348c97df44 1466 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1467 return(result);
lypinator 0:bb348c97df44 1468 }
lypinator 0:bb348c97df44 1469
lypinator 0:bb348c97df44 1470 __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1471 {
lypinator 0:bb348c97df44 1472 uint32_t result;
lypinator 0:bb348c97df44 1473
lypinator 0:bb348c97df44 1474 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1475 return(result);
lypinator 0:bb348c97df44 1476 }
lypinator 0:bb348c97df44 1477
lypinator 0:bb348c97df44 1478 __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1479 {
lypinator 0:bb348c97df44 1480 uint32_t result;
lypinator 0:bb348c97df44 1481
lypinator 0:bb348c97df44 1482 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1483 return(result);
lypinator 0:bb348c97df44 1484 }
lypinator 0:bb348c97df44 1485
lypinator 0:bb348c97df44 1486 __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1487 {
lypinator 0:bb348c97df44 1488 uint32_t result;
lypinator 0:bb348c97df44 1489
lypinator 0:bb348c97df44 1490 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1491 return(result);
lypinator 0:bb348c97df44 1492 }
lypinator 0:bb348c97df44 1493
lypinator 0:bb348c97df44 1494 __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1495 {
lypinator 0:bb348c97df44 1496 uint32_t result;
lypinator 0:bb348c97df44 1497
lypinator 0:bb348c97df44 1498 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1499 return(result);
lypinator 0:bb348c97df44 1500 }
lypinator 0:bb348c97df44 1501
lypinator 0:bb348c97df44 1502 __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1503 {
lypinator 0:bb348c97df44 1504 uint32_t result;
lypinator 0:bb348c97df44 1505
lypinator 0:bb348c97df44 1506 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1507 return(result);
lypinator 0:bb348c97df44 1508 }
lypinator 0:bb348c97df44 1509
lypinator 0:bb348c97df44 1510 __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1511 {
lypinator 0:bb348c97df44 1512 uint32_t result;
lypinator 0:bb348c97df44 1513
lypinator 0:bb348c97df44 1514 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1515 return(result);
lypinator 0:bb348c97df44 1516 }
lypinator 0:bb348c97df44 1517
lypinator 0:bb348c97df44 1518 __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1519 {
lypinator 0:bb348c97df44 1520 uint32_t result;
lypinator 0:bb348c97df44 1521
lypinator 0:bb348c97df44 1522 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1523 return(result);
lypinator 0:bb348c97df44 1524 }
lypinator 0:bb348c97df44 1525
lypinator 0:bb348c97df44 1526 __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1527 {
lypinator 0:bb348c97df44 1528 uint32_t result;
lypinator 0:bb348c97df44 1529
lypinator 0:bb348c97df44 1530 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1531 return(result);
lypinator 0:bb348c97df44 1532 }
lypinator 0:bb348c97df44 1533
lypinator 0:bb348c97df44 1534 __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1535 {
lypinator 0:bb348c97df44 1536 uint32_t result;
lypinator 0:bb348c97df44 1537
lypinator 0:bb348c97df44 1538 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1539 return(result);
lypinator 0:bb348c97df44 1540 }
lypinator 0:bb348c97df44 1541
lypinator 0:bb348c97df44 1542 __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1543 {
lypinator 0:bb348c97df44 1544 uint32_t result;
lypinator 0:bb348c97df44 1545
lypinator 0:bb348c97df44 1546 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1547 return(result);
lypinator 0:bb348c97df44 1548 }
lypinator 0:bb348c97df44 1549
lypinator 0:bb348c97df44 1550 __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1551 {
lypinator 0:bb348c97df44 1552 uint32_t result;
lypinator 0:bb348c97df44 1553
lypinator 0:bb348c97df44 1554 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1555 return(result);
lypinator 0:bb348c97df44 1556 }
lypinator 0:bb348c97df44 1557
lypinator 0:bb348c97df44 1558 __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1559 {
lypinator 0:bb348c97df44 1560 uint32_t result;
lypinator 0:bb348c97df44 1561
lypinator 0:bb348c97df44 1562 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1563 return(result);
lypinator 0:bb348c97df44 1564 }
lypinator 0:bb348c97df44 1565
lypinator 0:bb348c97df44 1566 __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1567 {
lypinator 0:bb348c97df44 1568 uint32_t result;
lypinator 0:bb348c97df44 1569
lypinator 0:bb348c97df44 1570 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1571 return(result);
lypinator 0:bb348c97df44 1572 }
lypinator 0:bb348c97df44 1573
lypinator 0:bb348c97df44 1574 __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1575 {
lypinator 0:bb348c97df44 1576 uint32_t result;
lypinator 0:bb348c97df44 1577
lypinator 0:bb348c97df44 1578 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1579 return(result);
lypinator 0:bb348c97df44 1580 }
lypinator 0:bb348c97df44 1581
lypinator 0:bb348c97df44 1582 __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1583 {
lypinator 0:bb348c97df44 1584 uint32_t result;
lypinator 0:bb348c97df44 1585
lypinator 0:bb348c97df44 1586 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1587 return(result);
lypinator 0:bb348c97df44 1588 }
lypinator 0:bb348c97df44 1589
lypinator 0:bb348c97df44 1590 __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1591 {
lypinator 0:bb348c97df44 1592 uint32_t result;
lypinator 0:bb348c97df44 1593
lypinator 0:bb348c97df44 1594 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1595 return(result);
lypinator 0:bb348c97df44 1596 }
lypinator 0:bb348c97df44 1597
lypinator 0:bb348c97df44 1598 __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1599 {
lypinator 0:bb348c97df44 1600 uint32_t result;
lypinator 0:bb348c97df44 1601
lypinator 0:bb348c97df44 1602 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1603 return(result);
lypinator 0:bb348c97df44 1604 }
lypinator 0:bb348c97df44 1605
lypinator 0:bb348c97df44 1606 __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1607 {
lypinator 0:bb348c97df44 1608 uint32_t result;
lypinator 0:bb348c97df44 1609
lypinator 0:bb348c97df44 1610 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1611 return(result);
lypinator 0:bb348c97df44 1612 }
lypinator 0:bb348c97df44 1613
lypinator 0:bb348c97df44 1614 __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1615 {
lypinator 0:bb348c97df44 1616 uint32_t result;
lypinator 0:bb348c97df44 1617
lypinator 0:bb348c97df44 1618 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1619 return(result);
lypinator 0:bb348c97df44 1620 }
lypinator 0:bb348c97df44 1621
lypinator 0:bb348c97df44 1622 __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1623 {
lypinator 0:bb348c97df44 1624 uint32_t result;
lypinator 0:bb348c97df44 1625
lypinator 0:bb348c97df44 1626 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1627 return(result);
lypinator 0:bb348c97df44 1628 }
lypinator 0:bb348c97df44 1629
lypinator 0:bb348c97df44 1630 __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
lypinator 0:bb348c97df44 1631 {
lypinator 0:bb348c97df44 1632 uint32_t result;
lypinator 0:bb348c97df44 1633
lypinator 0:bb348c97df44 1634 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
lypinator 0:bb348c97df44 1635 return(result);
lypinator 0:bb348c97df44 1636 }
lypinator 0:bb348c97df44 1637
lypinator 0:bb348c97df44 1638 #define __SSAT16(ARG1,ARG2) \
lypinator 0:bb348c97df44 1639 ({ \
lypinator 0:bb348c97df44 1640 int32_t __RES, __ARG1 = (ARG1); \
lypinator 0:bb348c97df44 1641 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
lypinator 0:bb348c97df44 1642 __RES; \
lypinator 0:bb348c97df44 1643 })
lypinator 0:bb348c97df44 1644
lypinator 0:bb348c97df44 1645 #define __USAT16(ARG1,ARG2) \
lypinator 0:bb348c97df44 1646 ({ \
lypinator 0:bb348c97df44 1647 uint32_t __RES, __ARG1 = (ARG1); \
lypinator 0:bb348c97df44 1648 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
lypinator 0:bb348c97df44 1649 __RES; \
lypinator 0:bb348c97df44 1650 })
lypinator 0:bb348c97df44 1651
lypinator 0:bb348c97df44 1652 __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
lypinator 0:bb348c97df44 1653 {
lypinator 0:bb348c97df44 1654 uint32_t result;
lypinator 0:bb348c97df44 1655
lypinator 0:bb348c97df44 1656 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
lypinator 0:bb348c97df44 1657 return(result);
lypinator 0:bb348c97df44 1658 }
lypinator 0:bb348c97df44 1659
lypinator 0:bb348c97df44 1660 __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1661 {
lypinator 0:bb348c97df44 1662 uint32_t result;
lypinator 0:bb348c97df44 1663
lypinator 0:bb348c97df44 1664 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1665 return(result);
lypinator 0:bb348c97df44 1666 }
lypinator 0:bb348c97df44 1667
lypinator 0:bb348c97df44 1668 __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
lypinator 0:bb348c97df44 1669 {
lypinator 0:bb348c97df44 1670 uint32_t result;
lypinator 0:bb348c97df44 1671
lypinator 0:bb348c97df44 1672 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
lypinator 0:bb348c97df44 1673 return(result);
lypinator 0:bb348c97df44 1674 }
lypinator 0:bb348c97df44 1675
lypinator 0:bb348c97df44 1676 __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1677 {
lypinator 0:bb348c97df44 1678 uint32_t result;
lypinator 0:bb348c97df44 1679
lypinator 0:bb348c97df44 1680 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1681 return(result);
lypinator 0:bb348c97df44 1682 }
lypinator 0:bb348c97df44 1683
lypinator 0:bb348c97df44 1684 __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1685 {
lypinator 0:bb348c97df44 1686 uint32_t result;
lypinator 0:bb348c97df44 1687
lypinator 0:bb348c97df44 1688 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1689 return(result);
lypinator 0:bb348c97df44 1690 }
lypinator 0:bb348c97df44 1691
lypinator 0:bb348c97df44 1692 __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1693 {
lypinator 0:bb348c97df44 1694 uint32_t result;
lypinator 0:bb348c97df44 1695
lypinator 0:bb348c97df44 1696 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1697 return(result);
lypinator 0:bb348c97df44 1698 }
lypinator 0:bb348c97df44 1699
lypinator 0:bb348c97df44 1700 __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
lypinator 0:bb348c97df44 1701 {
lypinator 0:bb348c97df44 1702 uint32_t result;
lypinator 0:bb348c97df44 1703
lypinator 0:bb348c97df44 1704 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
lypinator 0:bb348c97df44 1705 return(result);
lypinator 0:bb348c97df44 1706 }
lypinator 0:bb348c97df44 1707
lypinator 0:bb348c97df44 1708 __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
lypinator 0:bb348c97df44 1709 {
lypinator 0:bb348c97df44 1710 uint32_t result;
lypinator 0:bb348c97df44 1711
lypinator 0:bb348c97df44 1712 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
lypinator 0:bb348c97df44 1713 return(result);
lypinator 0:bb348c97df44 1714 }
lypinator 0:bb348c97df44 1715
lypinator 0:bb348c97df44 1716 __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
lypinator 0:bb348c97df44 1717 {
lypinator 0:bb348c97df44 1718 union llreg_u{
lypinator 0:bb348c97df44 1719 uint32_t w32[2];
lypinator 0:bb348c97df44 1720 uint64_t w64;
lypinator 0:bb348c97df44 1721 } llr;
lypinator 0:bb348c97df44 1722 llr.w64 = acc;
lypinator 0:bb348c97df44 1723
lypinator 0:bb348c97df44 1724 #ifndef __ARMEB__ /* Little endian */
lypinator 0:bb348c97df44 1725 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
lypinator 0:bb348c97df44 1726 #else /* Big endian */
lypinator 0:bb348c97df44 1727 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
lypinator 0:bb348c97df44 1728 #endif
lypinator 0:bb348c97df44 1729
lypinator 0:bb348c97df44 1730 return(llr.w64);
lypinator 0:bb348c97df44 1731 }
lypinator 0:bb348c97df44 1732
lypinator 0:bb348c97df44 1733 __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
lypinator 0:bb348c97df44 1734 {
lypinator 0:bb348c97df44 1735 union llreg_u{
lypinator 0:bb348c97df44 1736 uint32_t w32[2];
lypinator 0:bb348c97df44 1737 uint64_t w64;
lypinator 0:bb348c97df44 1738 } llr;
lypinator 0:bb348c97df44 1739 llr.w64 = acc;
lypinator 0:bb348c97df44 1740
lypinator 0:bb348c97df44 1741 #ifndef __ARMEB__ /* Little endian */
lypinator 0:bb348c97df44 1742 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
lypinator 0:bb348c97df44 1743 #else /* Big endian */
lypinator 0:bb348c97df44 1744 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
lypinator 0:bb348c97df44 1745 #endif
lypinator 0:bb348c97df44 1746
lypinator 0:bb348c97df44 1747 return(llr.w64);
lypinator 0:bb348c97df44 1748 }
lypinator 0:bb348c97df44 1749
lypinator 0:bb348c97df44 1750 __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1751 {
lypinator 0:bb348c97df44 1752 uint32_t result;
lypinator 0:bb348c97df44 1753
lypinator 0:bb348c97df44 1754 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1755 return(result);
lypinator 0:bb348c97df44 1756 }
lypinator 0:bb348c97df44 1757
lypinator 0:bb348c97df44 1758 __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1759 {
lypinator 0:bb348c97df44 1760 uint32_t result;
lypinator 0:bb348c97df44 1761
lypinator 0:bb348c97df44 1762 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1763 return(result);
lypinator 0:bb348c97df44 1764 }
lypinator 0:bb348c97df44 1765
lypinator 0:bb348c97df44 1766 __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
lypinator 0:bb348c97df44 1767 {
lypinator 0:bb348c97df44 1768 uint32_t result;
lypinator 0:bb348c97df44 1769
lypinator 0:bb348c97df44 1770 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
lypinator 0:bb348c97df44 1771 return(result);
lypinator 0:bb348c97df44 1772 }
lypinator 0:bb348c97df44 1773
lypinator 0:bb348c97df44 1774 __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
lypinator 0:bb348c97df44 1775 {
lypinator 0:bb348c97df44 1776 uint32_t result;
lypinator 0:bb348c97df44 1777
lypinator 0:bb348c97df44 1778 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
lypinator 0:bb348c97df44 1779 return(result);
lypinator 0:bb348c97df44 1780 }
lypinator 0:bb348c97df44 1781
lypinator 0:bb348c97df44 1782 __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
lypinator 0:bb348c97df44 1783 {
lypinator 0:bb348c97df44 1784 union llreg_u{
lypinator 0:bb348c97df44 1785 uint32_t w32[2];
lypinator 0:bb348c97df44 1786 uint64_t w64;
lypinator 0:bb348c97df44 1787 } llr;
lypinator 0:bb348c97df44 1788 llr.w64 = acc;
lypinator 0:bb348c97df44 1789
lypinator 0:bb348c97df44 1790 #ifndef __ARMEB__ /* Little endian */
lypinator 0:bb348c97df44 1791 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
lypinator 0:bb348c97df44 1792 #else /* Big endian */
lypinator 0:bb348c97df44 1793 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
lypinator 0:bb348c97df44 1794 #endif
lypinator 0:bb348c97df44 1795
lypinator 0:bb348c97df44 1796 return(llr.w64);
lypinator 0:bb348c97df44 1797 }
lypinator 0:bb348c97df44 1798
lypinator 0:bb348c97df44 1799 __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
lypinator 0:bb348c97df44 1800 {
lypinator 0:bb348c97df44 1801 union llreg_u{
lypinator 0:bb348c97df44 1802 uint32_t w32[2];
lypinator 0:bb348c97df44 1803 uint64_t w64;
lypinator 0:bb348c97df44 1804 } llr;
lypinator 0:bb348c97df44 1805 llr.w64 = acc;
lypinator 0:bb348c97df44 1806
lypinator 0:bb348c97df44 1807 #ifndef __ARMEB__ /* Little endian */
lypinator 0:bb348c97df44 1808 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
lypinator 0:bb348c97df44 1809 #else /* Big endian */
lypinator 0:bb348c97df44 1810 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
lypinator 0:bb348c97df44 1811 #endif
lypinator 0:bb348c97df44 1812
lypinator 0:bb348c97df44 1813 return(llr.w64);
lypinator 0:bb348c97df44 1814 }
lypinator 0:bb348c97df44 1815
lypinator 0:bb348c97df44 1816 __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 1817 {
lypinator 0:bb348c97df44 1818 uint32_t result;
lypinator 0:bb348c97df44 1819
lypinator 0:bb348c97df44 1820 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1821 return(result);
lypinator 0:bb348c97df44 1822 }
lypinator 0:bb348c97df44 1823
lypinator 0:bb348c97df44 1824 __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
lypinator 0:bb348c97df44 1825 {
lypinator 0:bb348c97df44 1826 int32_t result;
lypinator 0:bb348c97df44 1827
lypinator 0:bb348c97df44 1828 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1829 return(result);
lypinator 0:bb348c97df44 1830 }
lypinator 0:bb348c97df44 1831
lypinator 0:bb348c97df44 1832 __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
lypinator 0:bb348c97df44 1833 {
lypinator 0:bb348c97df44 1834 int32_t result;
lypinator 0:bb348c97df44 1835
lypinator 0:bb348c97df44 1836 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
lypinator 0:bb348c97df44 1837 return(result);
lypinator 0:bb348c97df44 1838 }
lypinator 0:bb348c97df44 1839
lypinator 0:bb348c97df44 1840 #if 0
lypinator 0:bb348c97df44 1841 #define __PKHBT(ARG1,ARG2,ARG3) \
lypinator 0:bb348c97df44 1842 ({ \
lypinator 0:bb348c97df44 1843 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
lypinator 0:bb348c97df44 1844 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
lypinator 0:bb348c97df44 1845 __RES; \
lypinator 0:bb348c97df44 1846 })
lypinator 0:bb348c97df44 1847
lypinator 0:bb348c97df44 1848 #define __PKHTB(ARG1,ARG2,ARG3) \
lypinator 0:bb348c97df44 1849 ({ \
lypinator 0:bb348c97df44 1850 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
lypinator 0:bb348c97df44 1851 if (ARG3 == 0) \
lypinator 0:bb348c97df44 1852 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
lypinator 0:bb348c97df44 1853 else \
lypinator 0:bb348c97df44 1854 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
lypinator 0:bb348c97df44 1855 __RES; \
lypinator 0:bb348c97df44 1856 })
lypinator 0:bb348c97df44 1857 #endif
lypinator 0:bb348c97df44 1858
lypinator 0:bb348c97df44 1859 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
lypinator 0:bb348c97df44 1860 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
lypinator 0:bb348c97df44 1861
lypinator 0:bb348c97df44 1862 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
lypinator 0:bb348c97df44 1863 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
lypinator 0:bb348c97df44 1864
lypinator 0:bb348c97df44 1865 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
lypinator 0:bb348c97df44 1866 {
lypinator 0:bb348c97df44 1867 int32_t result;
lypinator 0:bb348c97df44 1868
lypinator 0:bb348c97df44 1869 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
lypinator 0:bb348c97df44 1870 return(result);
lypinator 0:bb348c97df44 1871 }
lypinator 0:bb348c97df44 1872
lypinator 0:bb348c97df44 1873 #endif /* (__ARM_FEATURE_DSP == 1) */
lypinator 0:bb348c97df44 1874 /*@} end of group CMSIS_SIMD_intrinsics */
lypinator 0:bb348c97df44 1875
lypinator 0:bb348c97df44 1876
lypinator 0:bb348c97df44 1877 #endif /* __CMSIS_ARMCLANG_H */