Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/cmsis/TARGET_CORTEX_A/irq_ctrl_gic.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**************************************************************************//**
lypinator 0:bb348c97df44 2 * @file irq_ctrl_gic.c
lypinator 0:bb348c97df44 3 * @brief Interrupt controller handling implementation for GIC
lypinator 0:bb348c97df44 4 * @version V1.0.1
lypinator 0:bb348c97df44 5 * @date 9. April 2018
lypinator 0:bb348c97df44 6 ******************************************************************************/
lypinator 0:bb348c97df44 7 /*
lypinator 0:bb348c97df44 8 * Copyright (c) 2017 ARM Limited. All rights reserved.
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * SPDX-License-Identifier: Apache-2.0
lypinator 0:bb348c97df44 11 *
lypinator 0:bb348c97df44 12 * Licensed under the Apache License, Version 2.0 (the License); you may
lypinator 0:bb348c97df44 13 * not use this file except in compliance with the License.
lypinator 0:bb348c97df44 14 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 15 *
lypinator 0:bb348c97df44 16 * www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 17 *
lypinator 0:bb348c97df44 18 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
lypinator 0:bb348c97df44 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 21 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 22 * limitations under the License.
lypinator 0:bb348c97df44 23 */
lypinator 0:bb348c97df44 24
lypinator 0:bb348c97df44 25 #include <stddef.h>
lypinator 0:bb348c97df44 26
lypinator 0:bb348c97df44 27 #include "RTE_Components.h"
lypinator 0:bb348c97df44 28 #include CMSIS_device_header
lypinator 0:bb348c97df44 29
lypinator 0:bb348c97df44 30 #include "irq_ctrl.h"
lypinator 0:bb348c97df44 31
lypinator 0:bb348c97df44 32 #if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)
lypinator 0:bb348c97df44 33
lypinator 0:bb348c97df44 34 /// Number of implemented interrupt lines
lypinator 0:bb348c97df44 35 #ifndef IRQ_GIC_LINE_COUNT
lypinator 0:bb348c97df44 36 #define IRQ_GIC_LINE_COUNT (1020U)
lypinator 0:bb348c97df44 37 #endif
lypinator 0:bb348c97df44 38
lypinator 0:bb348c97df44 39 static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
lypinator 0:bb348c97df44 40 static uint32_t IRQ_ID0;
lypinator 0:bb348c97df44 41
lypinator 0:bb348c97df44 42 /// Initialize interrupt controller.
lypinator 0:bb348c97df44 43 __WEAK int32_t IRQ_Initialize (void) {
lypinator 0:bb348c97df44 44 uint32_t i;
lypinator 0:bb348c97df44 45
lypinator 0:bb348c97df44 46 for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
lypinator 0:bb348c97df44 47 IRQTable[i] = (IRQHandler_t)NULL;
lypinator 0:bb348c97df44 48 }
lypinator 0:bb348c97df44 49 GIC_Enable();
lypinator 0:bb348c97df44 50 return (0);
lypinator 0:bb348c97df44 51 }
lypinator 0:bb348c97df44 52
lypinator 0:bb348c97df44 53
lypinator 0:bb348c97df44 54 /// Register interrupt handler.
lypinator 0:bb348c97df44 55 __WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
lypinator 0:bb348c97df44 56 int32_t status;
lypinator 0:bb348c97df44 57
lypinator 0:bb348c97df44 58 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
lypinator 0:bb348c97df44 59 IRQTable[irqn] = handler;
lypinator 0:bb348c97df44 60 status = 0;
lypinator 0:bb348c97df44 61 } else {
lypinator 0:bb348c97df44 62 status = -1;
lypinator 0:bb348c97df44 63 }
lypinator 0:bb348c97df44 64
lypinator 0:bb348c97df44 65 return (status);
lypinator 0:bb348c97df44 66 }
lypinator 0:bb348c97df44 67
lypinator 0:bb348c97df44 68
lypinator 0:bb348c97df44 69 /// Get the registered interrupt handler.
lypinator 0:bb348c97df44 70 __WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
lypinator 0:bb348c97df44 71 IRQHandler_t h;
lypinator 0:bb348c97df44 72
lypinator 0:bb348c97df44 73 // Ignore CPUID field (software generated interrupts)
lypinator 0:bb348c97df44 74 irqn &= 0x3FFU;
lypinator 0:bb348c97df44 75
lypinator 0:bb348c97df44 76 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
lypinator 0:bb348c97df44 77 h = IRQTable[irqn];
lypinator 0:bb348c97df44 78 } else {
lypinator 0:bb348c97df44 79 h = (IRQHandler_t)0;
lypinator 0:bb348c97df44 80 }
lypinator 0:bb348c97df44 81
lypinator 0:bb348c97df44 82 return (h);
lypinator 0:bb348c97df44 83 }
lypinator 0:bb348c97df44 84
lypinator 0:bb348c97df44 85
lypinator 0:bb348c97df44 86 /// Enable interrupt.
lypinator 0:bb348c97df44 87 __WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) {
lypinator 0:bb348c97df44 88 int32_t status;
lypinator 0:bb348c97df44 89
lypinator 0:bb348c97df44 90 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
lypinator 0:bb348c97df44 91 GIC_EnableIRQ ((IRQn_Type)irqn);
lypinator 0:bb348c97df44 92 status = 0;
lypinator 0:bb348c97df44 93 } else {
lypinator 0:bb348c97df44 94 status = -1;
lypinator 0:bb348c97df44 95 }
lypinator 0:bb348c97df44 96
lypinator 0:bb348c97df44 97 return (status);
lypinator 0:bb348c97df44 98 }
lypinator 0:bb348c97df44 99
lypinator 0:bb348c97df44 100
lypinator 0:bb348c97df44 101 /// Disable interrupt.
lypinator 0:bb348c97df44 102 __WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) {
lypinator 0:bb348c97df44 103 int32_t status;
lypinator 0:bb348c97df44 104
lypinator 0:bb348c97df44 105 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
lypinator 0:bb348c97df44 106 GIC_DisableIRQ ((IRQn_Type)irqn);
lypinator 0:bb348c97df44 107 status = 0;
lypinator 0:bb348c97df44 108 } else {
lypinator 0:bb348c97df44 109 status = -1;
lypinator 0:bb348c97df44 110 }
lypinator 0:bb348c97df44 111
lypinator 0:bb348c97df44 112 return (status);
lypinator 0:bb348c97df44 113 }
lypinator 0:bb348c97df44 114
lypinator 0:bb348c97df44 115
lypinator 0:bb348c97df44 116 /// Get interrupt enable state.
lypinator 0:bb348c97df44 117 __WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
lypinator 0:bb348c97df44 118 uint32_t enable;
lypinator 0:bb348c97df44 119
lypinator 0:bb348c97df44 120 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
lypinator 0:bb348c97df44 121 enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
lypinator 0:bb348c97df44 122 } else {
lypinator 0:bb348c97df44 123 enable = 0U;
lypinator 0:bb348c97df44 124 }
lypinator 0:bb348c97df44 125
lypinator 0:bb348c97df44 126 return (enable);
lypinator 0:bb348c97df44 127 }
lypinator 0:bb348c97df44 128
lypinator 0:bb348c97df44 129
lypinator 0:bb348c97df44 130 /// Configure interrupt request mode.
lypinator 0:bb348c97df44 131 __WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
lypinator 0:bb348c97df44 132 uint32_t val;
lypinator 0:bb348c97df44 133 uint8_t cfg;
lypinator 0:bb348c97df44 134 uint8_t secure;
lypinator 0:bb348c97df44 135 uint8_t cpu;
lypinator 0:bb348c97df44 136 int32_t status = 0;
lypinator 0:bb348c97df44 137
lypinator 0:bb348c97df44 138 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
lypinator 0:bb348c97df44 139 // Check triggering mode
lypinator 0:bb348c97df44 140 val = (mode & IRQ_MODE_TRIG_Msk);
lypinator 0:bb348c97df44 141
lypinator 0:bb348c97df44 142 if (val == IRQ_MODE_TRIG_LEVEL) {
lypinator 0:bb348c97df44 143 cfg = 0x00U;
lypinator 0:bb348c97df44 144 } else if (val == IRQ_MODE_TRIG_EDGE) {
lypinator 0:bb348c97df44 145 cfg = 0x02U;
lypinator 0:bb348c97df44 146 } else {
lypinator 0:bb348c97df44 147 cfg = 0x00U;
lypinator 0:bb348c97df44 148 status = -1;
lypinator 0:bb348c97df44 149 }
lypinator 0:bb348c97df44 150
lypinator 0:bb348c97df44 151 // Check interrupt type
lypinator 0:bb348c97df44 152 val = mode & IRQ_MODE_TYPE_Msk;
lypinator 0:bb348c97df44 153
lypinator 0:bb348c97df44 154 if (val != IRQ_MODE_TYPE_IRQ) {
lypinator 0:bb348c97df44 155 status = -1;
lypinator 0:bb348c97df44 156 }
lypinator 0:bb348c97df44 157
lypinator 0:bb348c97df44 158 // Check interrupt domain
lypinator 0:bb348c97df44 159 val = mode & IRQ_MODE_DOMAIN_Msk;
lypinator 0:bb348c97df44 160
lypinator 0:bb348c97df44 161 if (val == IRQ_MODE_DOMAIN_NONSECURE) {
lypinator 0:bb348c97df44 162 secure = 0U;
lypinator 0:bb348c97df44 163 } else {
lypinator 0:bb348c97df44 164 // Check security extensions support
lypinator 0:bb348c97df44 165 val = GIC_DistributorInfo() & (1UL << 10U);
lypinator 0:bb348c97df44 166
lypinator 0:bb348c97df44 167 if (val != 0U) {
lypinator 0:bb348c97df44 168 // Security extensions are supported
lypinator 0:bb348c97df44 169 secure = 1U;
lypinator 0:bb348c97df44 170 } else {
lypinator 0:bb348c97df44 171 secure = 0U;
lypinator 0:bb348c97df44 172 status = -1;
lypinator 0:bb348c97df44 173 }
lypinator 0:bb348c97df44 174 }
lypinator 0:bb348c97df44 175
lypinator 0:bb348c97df44 176 // Check interrupt CPU targets
lypinator 0:bb348c97df44 177 val = mode & IRQ_MODE_CPU_Msk;
lypinator 0:bb348c97df44 178
lypinator 0:bb348c97df44 179 if (val == IRQ_MODE_CPU_ALL) {
lypinator 0:bb348c97df44 180 cpu = 0xFFU;
lypinator 0:bb348c97df44 181 } else {
lypinator 0:bb348c97df44 182 cpu = val >> IRQ_MODE_CPU_Pos;
lypinator 0:bb348c97df44 183 }
lypinator 0:bb348c97df44 184
lypinator 0:bb348c97df44 185 // Apply configuration if no mode error
lypinator 0:bb348c97df44 186 if (status == 0) {
lypinator 0:bb348c97df44 187 GIC_SetConfiguration((IRQn_Type)irqn, cfg);
lypinator 0:bb348c97df44 188 GIC_SetTarget ((IRQn_Type)irqn, cpu);
lypinator 0:bb348c97df44 189
lypinator 0:bb348c97df44 190 if (secure != 0U) {
lypinator 0:bb348c97df44 191 GIC_SetGroup ((IRQn_Type)irqn, secure);
lypinator 0:bb348c97df44 192 }
lypinator 0:bb348c97df44 193 }
lypinator 0:bb348c97df44 194 }
lypinator 0:bb348c97df44 195
lypinator 0:bb348c97df44 196 return (status);
lypinator 0:bb348c97df44 197 }
lypinator 0:bb348c97df44 198
lypinator 0:bb348c97df44 199
lypinator 0:bb348c97df44 200 /// Get interrupt mode configuration.
lypinator 0:bb348c97df44 201 __WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
lypinator 0:bb348c97df44 202 uint32_t mode;
lypinator 0:bb348c97df44 203 uint32_t val;
lypinator 0:bb348c97df44 204
lypinator 0:bb348c97df44 205 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
lypinator 0:bb348c97df44 206 mode = IRQ_MODE_TYPE_IRQ;
lypinator 0:bb348c97df44 207
lypinator 0:bb348c97df44 208 // Get trigger mode
lypinator 0:bb348c97df44 209 val = GIC_GetConfiguration((IRQn_Type)irqn);
lypinator 0:bb348c97df44 210
lypinator 0:bb348c97df44 211 if ((val & 2U) != 0U) {
lypinator 0:bb348c97df44 212 // Corresponding interrupt is edge triggered
lypinator 0:bb348c97df44 213 mode |= IRQ_MODE_TRIG_EDGE;
lypinator 0:bb348c97df44 214 } else {
lypinator 0:bb348c97df44 215 // Corresponding interrupt is level triggered
lypinator 0:bb348c97df44 216 mode |= IRQ_MODE_TRIG_LEVEL;
lypinator 0:bb348c97df44 217 }
lypinator 0:bb348c97df44 218
lypinator 0:bb348c97df44 219 // Get interrupt CPU targets
lypinator 0:bb348c97df44 220 mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;
lypinator 0:bb348c97df44 221
lypinator 0:bb348c97df44 222 } else {
lypinator 0:bb348c97df44 223 mode = IRQ_MODE_ERROR;
lypinator 0:bb348c97df44 224 }
lypinator 0:bb348c97df44 225
lypinator 0:bb348c97df44 226 return (mode);
lypinator 0:bb348c97df44 227 }
lypinator 0:bb348c97df44 228
lypinator 0:bb348c97df44 229
lypinator 0:bb348c97df44 230 /// Get ID number of current interrupt request (IRQ).
lypinator 0:bb348c97df44 231 __WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) {
lypinator 0:bb348c97df44 232 IRQn_ID_t irqn;
lypinator 0:bb348c97df44 233 uint32_t prio;
lypinator 0:bb348c97df44 234
lypinator 0:bb348c97df44 235 /* Dummy read to avoid GIC 390 errata 801120 */
lypinator 0:bb348c97df44 236 GIC_GetHighPendingIRQ();
lypinator 0:bb348c97df44 237
lypinator 0:bb348c97df44 238 irqn = GIC_AcknowledgePending();
lypinator 0:bb348c97df44 239
lypinator 0:bb348c97df44 240 __DSB();
lypinator 0:bb348c97df44 241
lypinator 0:bb348c97df44 242 /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014) */
lypinator 0:bb348c97df44 243 /* The following workaround code is for a single-core system. It would be */
lypinator 0:bb348c97df44 244 /* different in a multi-core system. */
lypinator 0:bb348c97df44 245 /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */
lypinator 0:bb348c97df44 246 /* so unlock it, otherwise service the interrupt as normal. */
lypinator 0:bb348c97df44 247 /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2 */
lypinator 0:bb348c97df44 248 /* so will not occur here. */
lypinator 0:bb348c97df44 249
lypinator 0:bb348c97df44 250 if ((irqn == 0) || (irqn >= 0x3FE)) {
lypinator 0:bb348c97df44 251 /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */
lypinator 0:bb348c97df44 252 prio = GIC_GetPriority((IRQn_Type)0);
lypinator 0:bb348c97df44 253 GIC_SetPriority ((IRQn_Type)0, prio);
lypinator 0:bb348c97df44 254
lypinator 0:bb348c97df44 255 __DSB();
lypinator 0:bb348c97df44 256
lypinator 0:bb348c97df44 257 if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) {
lypinator 0:bb348c97df44 258 /* If the ID is 0, is active and has not been seen before */
lypinator 0:bb348c97df44 259 IRQ_ID0 = 1U;
lypinator 0:bb348c97df44 260 }
lypinator 0:bb348c97df44 261 /* End of Workaround GIC 390 errata 733075 */
lypinator 0:bb348c97df44 262 }
lypinator 0:bb348c97df44 263
lypinator 0:bb348c97df44 264 return (irqn);
lypinator 0:bb348c97df44 265 }
lypinator 0:bb348c97df44 266
lypinator 0:bb348c97df44 267
lypinator 0:bb348c97df44 268 /// Get ID number of current fast interrupt request (FIQ).
lypinator 0:bb348c97df44 269 __WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) {
lypinator 0:bb348c97df44 270 return ((IRQn_ID_t)-1);
lypinator 0:bb348c97df44 271 }
lypinator 0:bb348c97df44 272
lypinator 0:bb348c97df44 273
lypinator 0:bb348c97df44 274 /// Signal end of interrupt processing.
lypinator 0:bb348c97df44 275 __WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
lypinator 0:bb348c97df44 276 int32_t status;
lypinator 0:bb348c97df44 277 IRQn_Type irq = (IRQn_Type)irqn;
lypinator 0:bb348c97df44 278
lypinator 0:bb348c97df44 279 irqn &= 0x3FFU;
lypinator 0:bb348c97df44 280
lypinator 0:bb348c97df44 281 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
lypinator 0:bb348c97df44 282 GIC_EndInterrupt (irq);
lypinator 0:bb348c97df44 283
lypinator 0:bb348c97df44 284 if (irqn == 0) {
lypinator 0:bb348c97df44 285 IRQ_ID0 = 0U;
lypinator 0:bb348c97df44 286 }
lypinator 0:bb348c97df44 287
lypinator 0:bb348c97df44 288 status = 0;
lypinator 0:bb348c97df44 289 } else {
lypinator 0:bb348c97df44 290 status = -1;
lypinator 0:bb348c97df44 291 }
lypinator 0:bb348c97df44 292
lypinator 0:bb348c97df44 293 return (status);
lypinator 0:bb348c97df44 294 }
lypinator 0:bb348c97df44 295
lypinator 0:bb348c97df44 296
lypinator 0:bb348c97df44 297 /// Set interrupt pending flag.
lypinator 0:bb348c97df44 298 __WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) {
lypinator 0:bb348c97df44 299 int32_t status;
lypinator 0:bb348c97df44 300
lypinator 0:bb348c97df44 301 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
lypinator 0:bb348c97df44 302 GIC_SetPendingIRQ ((IRQn_Type)irqn);
lypinator 0:bb348c97df44 303 status = 0;
lypinator 0:bb348c97df44 304 } else {
lypinator 0:bb348c97df44 305 status = -1;
lypinator 0:bb348c97df44 306 }
lypinator 0:bb348c97df44 307
lypinator 0:bb348c97df44 308 return (status);
lypinator 0:bb348c97df44 309 }
lypinator 0:bb348c97df44 310
lypinator 0:bb348c97df44 311 /// Get interrupt pending flag.
lypinator 0:bb348c97df44 312 __WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
lypinator 0:bb348c97df44 313 uint32_t pending;
lypinator 0:bb348c97df44 314
lypinator 0:bb348c97df44 315 if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
lypinator 0:bb348c97df44 316 pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
lypinator 0:bb348c97df44 317 } else {
lypinator 0:bb348c97df44 318 pending = 0U;
lypinator 0:bb348c97df44 319 }
lypinator 0:bb348c97df44 320
lypinator 0:bb348c97df44 321 return (pending & 1U);
lypinator 0:bb348c97df44 322 }
lypinator 0:bb348c97df44 323
lypinator 0:bb348c97df44 324
lypinator 0:bb348c97df44 325 /// Clear interrupt pending flag.
lypinator 0:bb348c97df44 326 __WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
lypinator 0:bb348c97df44 327 int32_t status;
lypinator 0:bb348c97df44 328
lypinator 0:bb348c97df44 329 if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
lypinator 0:bb348c97df44 330 GIC_ClearPendingIRQ ((IRQn_Type)irqn);
lypinator 0:bb348c97df44 331 status = 0;
lypinator 0:bb348c97df44 332 } else {
lypinator 0:bb348c97df44 333 status = -1;
lypinator 0:bb348c97df44 334 }
lypinator 0:bb348c97df44 335
lypinator 0:bb348c97df44 336 return (status);
lypinator 0:bb348c97df44 337 }
lypinator 0:bb348c97df44 338
lypinator 0:bb348c97df44 339
lypinator 0:bb348c97df44 340 /// Set interrupt priority value.
lypinator 0:bb348c97df44 341 __WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
lypinator 0:bb348c97df44 342 int32_t status;
lypinator 0:bb348c97df44 343
lypinator 0:bb348c97df44 344 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
lypinator 0:bb348c97df44 345 GIC_SetPriority ((IRQn_Type)irqn, priority);
lypinator 0:bb348c97df44 346 status = 0;
lypinator 0:bb348c97df44 347 } else {
lypinator 0:bb348c97df44 348 status = -1;
lypinator 0:bb348c97df44 349 }
lypinator 0:bb348c97df44 350
lypinator 0:bb348c97df44 351 return (status);
lypinator 0:bb348c97df44 352 }
lypinator 0:bb348c97df44 353
lypinator 0:bb348c97df44 354
lypinator 0:bb348c97df44 355 /// Get interrupt priority.
lypinator 0:bb348c97df44 356 __WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
lypinator 0:bb348c97df44 357 uint32_t priority;
lypinator 0:bb348c97df44 358
lypinator 0:bb348c97df44 359 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
lypinator 0:bb348c97df44 360 priority = GIC_GetPriority ((IRQn_Type)irqn);
lypinator 0:bb348c97df44 361 } else {
lypinator 0:bb348c97df44 362 priority = IRQ_PRIORITY_ERROR;
lypinator 0:bb348c97df44 363 }
lypinator 0:bb348c97df44 364
lypinator 0:bb348c97df44 365 return (priority);
lypinator 0:bb348c97df44 366 }
lypinator 0:bb348c97df44 367
lypinator 0:bb348c97df44 368
lypinator 0:bb348c97df44 369 /// Set priority masking threshold.
lypinator 0:bb348c97df44 370 __WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) {
lypinator 0:bb348c97df44 371 GIC_SetInterfacePriorityMask (priority);
lypinator 0:bb348c97df44 372 return (0);
lypinator 0:bb348c97df44 373 }
lypinator 0:bb348c97df44 374
lypinator 0:bb348c97df44 375
lypinator 0:bb348c97df44 376 /// Get priority masking threshold
lypinator 0:bb348c97df44 377 __WEAK uint32_t IRQ_GetPriorityMask (void) {
lypinator 0:bb348c97df44 378 return GIC_GetInterfacePriorityMask();
lypinator 0:bb348c97df44 379 }
lypinator 0:bb348c97df44 380
lypinator 0:bb348c97df44 381
lypinator 0:bb348c97df44 382 /// Set priority grouping field split point
lypinator 0:bb348c97df44 383 __WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
lypinator 0:bb348c97df44 384 int32_t status;
lypinator 0:bb348c97df44 385
lypinator 0:bb348c97df44 386 if (bits == IRQ_PRIORITY_Msk) {
lypinator 0:bb348c97df44 387 bits = 7U;
lypinator 0:bb348c97df44 388 }
lypinator 0:bb348c97df44 389
lypinator 0:bb348c97df44 390 if (bits < 8U) {
lypinator 0:bb348c97df44 391 GIC_SetBinaryPoint (7U - bits);
lypinator 0:bb348c97df44 392 status = 0;
lypinator 0:bb348c97df44 393 } else {
lypinator 0:bb348c97df44 394 status = -1;
lypinator 0:bb348c97df44 395 }
lypinator 0:bb348c97df44 396
lypinator 0:bb348c97df44 397 return (status);
lypinator 0:bb348c97df44 398 }
lypinator 0:bb348c97df44 399
lypinator 0:bb348c97df44 400
lypinator 0:bb348c97df44 401 /// Get priority grouping field split point
lypinator 0:bb348c97df44 402 __WEAK uint32_t IRQ_GetPriorityGroupBits (void) {
lypinator 0:bb348c97df44 403 uint32_t bp;
lypinator 0:bb348c97df44 404
lypinator 0:bb348c97df44 405 bp = GIC_GetBinaryPoint() & 0x07U;
lypinator 0:bb348c97df44 406
lypinator 0:bb348c97df44 407 return (7U - bp);
lypinator 0:bb348c97df44 408 }
lypinator 0:bb348c97df44 409
lypinator 0:bb348c97df44 410 #endif