Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/cmsis/TARGET_CORTEX_A/irq_ctrl.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**************************************************************************//**
lypinator 0:bb348c97df44 2 * @file irq_ctrl.h
lypinator 0:bb348c97df44 3 * @brief Interrupt Controller API header file
lypinator 0:bb348c97df44 4 * @version V1.0.0
lypinator 0:bb348c97df44 5 * @date 23. June 2017
lypinator 0:bb348c97df44 6 ******************************************************************************/
lypinator 0:bb348c97df44 7 /*
lypinator 0:bb348c97df44 8 * Copyright (c) 2017 ARM Limited. All rights reserved.
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * SPDX-License-Identifier: Apache-2.0
lypinator 0:bb348c97df44 11 *
lypinator 0:bb348c97df44 12 * Licensed under the Apache License, Version 2.0 (the License); you may
lypinator 0:bb348c97df44 13 * not use this file except in compliance with the License.
lypinator 0:bb348c97df44 14 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 15 *
lypinator 0:bb348c97df44 16 * www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 17 *
lypinator 0:bb348c97df44 18 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
lypinator 0:bb348c97df44 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 21 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 22 * limitations under the License.
lypinator 0:bb348c97df44 23 */
lypinator 0:bb348c97df44 24
lypinator 0:bb348c97df44 25 #if defined ( __ICCARM__ )
lypinator 0:bb348c97df44 26 #pragma system_include /* treat file as system include file for MISRA check */
lypinator 0:bb348c97df44 27 #elif defined (__clang__)
lypinator 0:bb348c97df44 28 #pragma clang system_header /* treat file as system include file */
lypinator 0:bb348c97df44 29 #endif
lypinator 0:bb348c97df44 30
lypinator 0:bb348c97df44 31 #ifndef IRQ_CTRL_H_
lypinator 0:bb348c97df44 32 #define IRQ_CTRL_H_
lypinator 0:bb348c97df44 33
lypinator 0:bb348c97df44 34 #include <stdint.h>
lypinator 0:bb348c97df44 35
lypinator 0:bb348c97df44 36 #ifndef IRQHANDLER_T
lypinator 0:bb348c97df44 37 #define IRQHANDLER_T
lypinator 0:bb348c97df44 38 /// Interrupt handler data type
lypinator 0:bb348c97df44 39 typedef void (*IRQHandler_t) (void);
lypinator 0:bb348c97df44 40 #endif
lypinator 0:bb348c97df44 41
lypinator 0:bb348c97df44 42 #ifndef IRQN_ID_T
lypinator 0:bb348c97df44 43 #define IRQN_ID_T
lypinator 0:bb348c97df44 44 /// Interrupt ID number data type
lypinator 0:bb348c97df44 45 typedef int32_t IRQn_ID_t;
lypinator 0:bb348c97df44 46 #endif
lypinator 0:bb348c97df44 47
lypinator 0:bb348c97df44 48 /* Interrupt mode bit-masks */
lypinator 0:bb348c97df44 49 #define IRQ_MODE_TRIG_Pos (0U)
lypinator 0:bb348c97df44 50 #define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
lypinator 0:bb348c97df44 51 #define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt
lypinator 0:bb348c97df44 52 #define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt
lypinator 0:bb348c97df44 53 #define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt
lypinator 0:bb348c97df44 54 #define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt
lypinator 0:bb348c97df44 55 #define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt
lypinator 0:bb348c97df44 56 #define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt
lypinator 0:bb348c97df44 57 #define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt
lypinator 0:bb348c97df44 58
lypinator 0:bb348c97df44 59 #define IRQ_MODE_TYPE_Pos (3U)
lypinator 0:bb348c97df44 60 #define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos)
lypinator 0:bb348c97df44 61 #define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line
lypinator 0:bb348c97df44 62 #define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line
lypinator 0:bb348c97df44 63
lypinator 0:bb348c97df44 64 #define IRQ_MODE_DOMAIN_Pos (4U)
lypinator 0:bb348c97df44 65 #define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos)
lypinator 0:bb348c97df44 66 #define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain
lypinator 0:bb348c97df44 67 #define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain
lypinator 0:bb348c97df44 68
lypinator 0:bb348c97df44 69 #define IRQ_MODE_CPU_Pos (5U)
lypinator 0:bb348c97df44 70 #define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos)
lypinator 0:bb348c97df44 71 #define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs
lypinator 0:bb348c97df44 72 #define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0
lypinator 0:bb348c97df44 73 #define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1
lypinator 0:bb348c97df44 74 #define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2
lypinator 0:bb348c97df44 75 #define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3
lypinator 0:bb348c97df44 76 #define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4
lypinator 0:bb348c97df44 77 #define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5
lypinator 0:bb348c97df44 78 #define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6
lypinator 0:bb348c97df44 79 #define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7
lypinator 0:bb348c97df44 80
lypinator 0:bb348c97df44 81 #define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error
lypinator 0:bb348c97df44 82
lypinator 0:bb348c97df44 83 /* Interrupt priority bit-masks */
lypinator 0:bb348c97df44 84 #define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask
lypinator 0:bb348c97df44 85 #define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error
lypinator 0:bb348c97df44 86
lypinator 0:bb348c97df44 87 /// Initialize interrupt controller.
lypinator 0:bb348c97df44 88 /// \return 0 on success, -1 on error.
lypinator 0:bb348c97df44 89 int32_t IRQ_Initialize (void);
lypinator 0:bb348c97df44 90
lypinator 0:bb348c97df44 91 /// Register interrupt handler.
lypinator 0:bb348c97df44 92 /// \param[in] irqn interrupt ID number
lypinator 0:bb348c97df44 93 /// \param[in] handler interrupt handler function address
lypinator 0:bb348c97df44 94 /// \return 0 on success, -1 on error.
lypinator 0:bb348c97df44 95 int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);
lypinator 0:bb348c97df44 96
lypinator 0:bb348c97df44 97 /// Get the registered interrupt handler.
lypinator 0:bb348c97df44 98 /// \param[in] irqn interrupt ID number
lypinator 0:bb348c97df44 99 /// \return registered interrupt handler function address.
lypinator 0:bb348c97df44 100 IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn);
lypinator 0:bb348c97df44 101
lypinator 0:bb348c97df44 102 /// Enable interrupt.
lypinator 0:bb348c97df44 103 /// \param[in] irqn interrupt ID number
lypinator 0:bb348c97df44 104 /// \return 0 on success, -1 on error.
lypinator 0:bb348c97df44 105 int32_t IRQ_Enable (IRQn_ID_t irqn);
lypinator 0:bb348c97df44 106
lypinator 0:bb348c97df44 107 /// Disable interrupt.
lypinator 0:bb348c97df44 108 /// \param[in] irqn interrupt ID number
lypinator 0:bb348c97df44 109 /// \return 0 on success, -1 on error.
lypinator 0:bb348c97df44 110 int32_t IRQ_Disable (IRQn_ID_t irqn);
lypinator 0:bb348c97df44 111
lypinator 0:bb348c97df44 112 /// Get interrupt enable state.
lypinator 0:bb348c97df44 113 /// \param[in] irqn interrupt ID number
lypinator 0:bb348c97df44 114 /// \return 0 - interrupt is disabled, 1 - interrupt is enabled.
lypinator 0:bb348c97df44 115 uint32_t IRQ_GetEnableState (IRQn_ID_t irqn);
lypinator 0:bb348c97df44 116
lypinator 0:bb348c97df44 117 /// Configure interrupt request mode.
lypinator 0:bb348c97df44 118 /// \param[in] irqn interrupt ID number
lypinator 0:bb348c97df44 119 /// \param[in] mode mode configuration
lypinator 0:bb348c97df44 120 /// \return 0 on success, -1 on error.
lypinator 0:bb348c97df44 121 int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode);
lypinator 0:bb348c97df44 122
lypinator 0:bb348c97df44 123 /// Get interrupt mode configuration.
lypinator 0:bb348c97df44 124 /// \param[in] irqn interrupt ID number
lypinator 0:bb348c97df44 125 /// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.
lypinator 0:bb348c97df44 126 uint32_t IRQ_GetMode (IRQn_ID_t irqn);
lypinator 0:bb348c97df44 127
lypinator 0:bb348c97df44 128 /// Get ID number of current interrupt request (IRQ).
lypinator 0:bb348c97df44 129 /// \return interrupt ID number.
lypinator 0:bb348c97df44 130 IRQn_ID_t IRQ_GetActiveIRQ (void);
lypinator 0:bb348c97df44 131
lypinator 0:bb348c97df44 132 /// Get ID number of current fast interrupt request (FIQ).
lypinator 0:bb348c97df44 133 /// \return interrupt ID number.
lypinator 0:bb348c97df44 134 IRQn_ID_t IRQ_GetActiveFIQ (void);
lypinator 0:bb348c97df44 135
lypinator 0:bb348c97df44 136 /// Signal end of interrupt processing.
lypinator 0:bb348c97df44 137 /// \param[in] irqn interrupt ID number
lypinator 0:bb348c97df44 138 /// \return 0 on success, -1 on error.
lypinator 0:bb348c97df44 139 int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn);
lypinator 0:bb348c97df44 140
lypinator 0:bb348c97df44 141 /// Set interrupt pending flag.
lypinator 0:bb348c97df44 142 /// \param[in] irqn interrupt ID number
lypinator 0:bb348c97df44 143 /// \return 0 on success, -1 on error.
lypinator 0:bb348c97df44 144 int32_t IRQ_SetPending (IRQn_ID_t irqn);
lypinator 0:bb348c97df44 145
lypinator 0:bb348c97df44 146 /// Get interrupt pending flag.
lypinator 0:bb348c97df44 147 /// \param[in] irqn interrupt ID number
lypinator 0:bb348c97df44 148 /// \return 0 - interrupt is not pending, 1 - interrupt is pending.
lypinator 0:bb348c97df44 149 uint32_t IRQ_GetPending (IRQn_ID_t irqn);
lypinator 0:bb348c97df44 150
lypinator 0:bb348c97df44 151 /// Clear interrupt pending flag.
lypinator 0:bb348c97df44 152 /// \param[in] irqn interrupt ID number
lypinator 0:bb348c97df44 153 /// \return 0 on success, -1 on error.
lypinator 0:bb348c97df44 154 int32_t IRQ_ClearPending (IRQn_ID_t irqn);
lypinator 0:bb348c97df44 155
lypinator 0:bb348c97df44 156 /// Set interrupt priority value.
lypinator 0:bb348c97df44 157 /// \param[in] irqn interrupt ID number
lypinator 0:bb348c97df44 158 /// \param[in] priority interrupt priority value
lypinator 0:bb348c97df44 159 /// \return 0 on success, -1 on error.
lypinator 0:bb348c97df44 160 int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);
lypinator 0:bb348c97df44 161
lypinator 0:bb348c97df44 162 /// Get interrupt priority.
lypinator 0:bb348c97df44 163 /// \param[in] irqn interrupt ID number
lypinator 0:bb348c97df44 164 /// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.
lypinator 0:bb348c97df44 165 uint32_t IRQ_GetPriority (IRQn_ID_t irqn);
lypinator 0:bb348c97df44 166
lypinator 0:bb348c97df44 167 /// Set priority masking threshold.
lypinator 0:bb348c97df44 168 /// \param[in] priority priority masking threshold value
lypinator 0:bb348c97df44 169 /// \return 0 on success, -1 on error.
lypinator 0:bb348c97df44 170 int32_t IRQ_SetPriorityMask (uint32_t priority);
lypinator 0:bb348c97df44 171
lypinator 0:bb348c97df44 172 /// Get priority masking threshold
lypinator 0:bb348c97df44 173 /// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.
lypinator 0:bb348c97df44 174 uint32_t IRQ_GetPriorityMask (void);
lypinator 0:bb348c97df44 175
lypinator 0:bb348c97df44 176 /// Set priority grouping field split point
lypinator 0:bb348c97df44 177 /// \param[in] bits number of MSB bits included in the group priority field comparison
lypinator 0:bb348c97df44 178 /// \return 0 on success, -1 on error.
lypinator 0:bb348c97df44 179 int32_t IRQ_SetPriorityGroupBits (uint32_t bits);
lypinator 0:bb348c97df44 180
lypinator 0:bb348c97df44 181 /// Get priority grouping field split point
lypinator 0:bb348c97df44 182 /// \return current number of MSB bits included in the group priority field comparison with
lypinator 0:bb348c97df44 183 /// optional IRQ_PRIORITY_ERROR bit set.
lypinator 0:bb348c97df44 184 uint32_t IRQ_GetPriorityGroupBits (void);
lypinator 0:bb348c97df44 185
lypinator 0:bb348c97df44 186 #endif // IRQ_CTRL_H_