DevLibMemoryController - Initial commit

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Initial commit

mbed-dev-master/cmsis/TARGET_CORTEX_A/core_ca.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:: lypinator
Date:: Wed Sep 16 01:11:49 2020 +0000
Revision:: 0:bb348c97df44

Added PWM

Who changed what in which revision?

User	Revision	Line number	New contents of line
lypinator	0:bb348c97df44	1	/************************************************************************//
lypinator	0:bb348c97df44	2	* @file core_ca.h
lypinator	0:bb348c97df44	3	* @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
lypinator	0:bb348c97df44	4	* @version V1.00
lypinator	0:bb348c97df44	5	* @date 22. Feb 2017
lypinator	0:bb348c97df44	6	******************************************************************************/
lypinator	0:bb348c97df44	7	/*
lypinator	0:bb348c97df44	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
lypinator	0:bb348c97df44	9	*
lypinator	0:bb348c97df44	10	* SPDX-License-Identifier: Apache-2.0
lypinator	0:bb348c97df44	11	*
lypinator	0:bb348c97df44	12	* Licensed under the Apache License, Version 2.0 (the License); you may
lypinator	0:bb348c97df44	13	* not use this file except in compliance with the License.
lypinator	0:bb348c97df44	14	* You may obtain a copy of the License at
lypinator	0:bb348c97df44	15	*
lypinator	0:bb348c97df44	16	* www.apache.org/licenses/LICENSE-2.0
lypinator	0:bb348c97df44	17	*
lypinator	0:bb348c97df44	18	* Unless required by applicable law or agreed to in writing, software
lypinator	0:bb348c97df44	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
lypinator	0:bb348c97df44	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator	0:bb348c97df44	21	* See the License for the specific language governing permissions and
lypinator	0:bb348c97df44	22	* limitations under the License.
lypinator	0:bb348c97df44	23	*/
lypinator	0:bb348c97df44	24
lypinator	0:bb348c97df44	25	#if defined ( __ICCARM__ )
lypinator	0:bb348c97df44	26	#pragma system_include /* treat file as system include file for MISRA check */
lypinator	0:bb348c97df44	27	#elif defined (__clang__)
lypinator	0:bb348c97df44	28	#pragma clang system_header /* treat file as system include file */
lypinator	0:bb348c97df44	29	#endif
lypinator	0:bb348c97df44	30
lypinator	0:bb348c97df44	31	#ifdef __cplusplus
lypinator	0:bb348c97df44	32	extern "C" {
lypinator	0:bb348c97df44	33	#endif
lypinator	0:bb348c97df44	34
lypinator	0:bb348c97df44	35	#ifndef __CORE_CA_H_GENERIC
lypinator	0:bb348c97df44	36	#define __CORE_CA_H_GENERIC
lypinator	0:bb348c97df44	37
lypinator	0:bb348c97df44	38
lypinator	0:bb348c97df44	39	/*******************************************************************************
lypinator	0:bb348c97df44	40	* CMSIS definitions
lypinator	0:bb348c97df44	41	******************************************************************************/
lypinator	0:bb348c97df44	42
lypinator	0:bb348c97df44	43	/* CMSIS CA definitions */
lypinator	0:bb348c97df44	44	#define __CA_CMSIS_VERSION_MAIN (1U) /!< \brief [31:16] CMSIS-Core(A) main version /
lypinator	0:bb348c97df44	45	#define __CA_CMSIS_VERSION_SUB (1U) /!< \brief [15:0] CMSIS-Core(A) sub version /
lypinator	0:bb348c97df44	46	#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) \| \
lypinator	0:bb348c97df44	47	__CA_CMSIS_VERSION_SUB ) /!< \brief CMSIS-Core(A) version number /
lypinator	0:bb348c97df44	48
lypinator	0:bb348c97df44	49	#if defined ( __CC_ARM )
lypinator	0:bb348c97df44	50	#if defined __TARGET_FPU_VFP
lypinator	0:bb348c97df44	51	#if (__FPU_PRESENT == 1)
lypinator	0:bb348c97df44	52	#define __FPU_USED 1U
lypinator	0:bb348c97df44	53	#else
lypinator	0:bb348c97df44	54	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator	0:bb348c97df44	55	#define __FPU_USED 0U
lypinator	0:bb348c97df44	56	#endif
lypinator	0:bb348c97df44	57	#else
lypinator	0:bb348c97df44	58	#define __FPU_USED 0U
lypinator	0:bb348c97df44	59	#endif
lypinator	0:bb348c97df44	60
lypinator	0:bb348c97df44	61	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
lypinator	0:bb348c97df44	62	#if defined __ARM_PCS_VFP
lypinator	0:bb348c97df44	63	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
lypinator	0:bb348c97df44	64	#define __FPU_USED 1U
lypinator	0:bb348c97df44	65	#else
lypinator	0:bb348c97df44	66	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator	0:bb348c97df44	67	#define __FPU_USED 0U
lypinator	0:bb348c97df44	68	#endif
lypinator	0:bb348c97df44	69	#else
lypinator	0:bb348c97df44	70	#define __FPU_USED 0U
lypinator	0:bb348c97df44	71	#endif
lypinator	0:bb348c97df44	72
lypinator	0:bb348c97df44	73	#elif defined ( __ICCARM__ )
lypinator	0:bb348c97df44	74	#if defined __ARMVFP__
lypinator	0:bb348c97df44	75	#if (__FPU_PRESENT == 1)
lypinator	0:bb348c97df44	76	#define __FPU_USED 1U
lypinator	0:bb348c97df44	77	#else
lypinator	0:bb348c97df44	78	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator	0:bb348c97df44	79	#define __FPU_USED 0U
lypinator	0:bb348c97df44	80	#endif
lypinator	0:bb348c97df44	81	#else
lypinator	0:bb348c97df44	82	#define __FPU_USED 0U
lypinator	0:bb348c97df44	83	#endif
lypinator	0:bb348c97df44	84
lypinator	0:bb348c97df44	85	#elif defined ( __TMS470__ )
lypinator	0:bb348c97df44	86	#if defined __TI_VFP_SUPPORT__
lypinator	0:bb348c97df44	87	#if (__FPU_PRESENT == 1)
lypinator	0:bb348c97df44	88	#define __FPU_USED 1U
lypinator	0:bb348c97df44	89	#else
lypinator	0:bb348c97df44	90	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator	0:bb348c97df44	91	#define __FPU_USED 0U
lypinator	0:bb348c97df44	92	#endif
lypinator	0:bb348c97df44	93	#else
lypinator	0:bb348c97df44	94	#define __FPU_USED 0U
lypinator	0:bb348c97df44	95	#endif
lypinator	0:bb348c97df44	96
lypinator	0:bb348c97df44	97	#elif defined ( __GNUC__ )
lypinator	0:bb348c97df44	98	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
lypinator	0:bb348c97df44	99	#if (__FPU_PRESENT == 1)
lypinator	0:bb348c97df44	100	#define __FPU_USED 1U
lypinator	0:bb348c97df44	101	#else
lypinator	0:bb348c97df44	102	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator	0:bb348c97df44	103	#define __FPU_USED 0U
lypinator	0:bb348c97df44	104	#endif
lypinator	0:bb348c97df44	105	#else
lypinator	0:bb348c97df44	106	#define __FPU_USED 0U
lypinator	0:bb348c97df44	107	#endif
lypinator	0:bb348c97df44	108
lypinator	0:bb348c97df44	109	#elif defined ( __TASKING__ )
lypinator	0:bb348c97df44	110	#if defined __FPU_VFP__
lypinator	0:bb348c97df44	111	#if (__FPU_PRESENT == 1)
lypinator	0:bb348c97df44	112	#define __FPU_USED 1U
lypinator	0:bb348c97df44	113	#else
lypinator	0:bb348c97df44	114	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator	0:bb348c97df44	115	#define __FPU_USED 0U
lypinator	0:bb348c97df44	116	#endif
lypinator	0:bb348c97df44	117	#else
lypinator	0:bb348c97df44	118	#define __FPU_USED 0U
lypinator	0:bb348c97df44	119	#endif
lypinator	0:bb348c97df44	120	#endif
lypinator	0:bb348c97df44	121
lypinator	0:bb348c97df44	122	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
lypinator	0:bb348c97df44	123
lypinator	0:bb348c97df44	124	#ifdef __cplusplus
lypinator	0:bb348c97df44	125	}
lypinator	0:bb348c97df44	126	#endif
lypinator	0:bb348c97df44	127
lypinator	0:bb348c97df44	128	#endif /* __CORE_CA_H_GENERIC */
lypinator	0:bb348c97df44	129
lypinator	0:bb348c97df44	130	#ifndef __CMSIS_GENERIC
lypinator	0:bb348c97df44	131
lypinator	0:bb348c97df44	132	#ifndef __CORE_CA_H_DEPENDANT
lypinator	0:bb348c97df44	133	#define __CORE_CA_H_DEPENDANT
lypinator	0:bb348c97df44	134
lypinator	0:bb348c97df44	135	#ifdef __cplusplus
lypinator	0:bb348c97df44	136	extern "C" {
lypinator	0:bb348c97df44	137	#endif
lypinator	0:bb348c97df44	138
lypinator	0:bb348c97df44	139	/* check device defines and use defaults */
lypinator	0:bb348c97df44	140	#if defined __CHECK_DEVICE_DEFINES
lypinator	0:bb348c97df44	141	#ifndef __CA_REV
lypinator	0:bb348c97df44	142	#define __CA_REV 0x0000U
lypinator	0:bb348c97df44	143	#warning "__CA_REV not defined in device header file; using default!"
lypinator	0:bb348c97df44	144	#endif
lypinator	0:bb348c97df44	145
lypinator	0:bb348c97df44	146	#ifndef __FPU_PRESENT
lypinator	0:bb348c97df44	147	#define __FPU_PRESENT 0U
lypinator	0:bb348c97df44	148	#warning "__FPU_PRESENT not defined in device header file; using default!"
lypinator	0:bb348c97df44	149	#endif
lypinator	0:bb348c97df44	150
lypinator	0:bb348c97df44	151	#ifndef __GIC_PRESENT
lypinator	0:bb348c97df44	152	#define __GIC_PRESENT 1U
lypinator	0:bb348c97df44	153	#warning "__GIC_PRESENT not defined in device header file; using default!"
lypinator	0:bb348c97df44	154	#endif
lypinator	0:bb348c97df44	155
lypinator	0:bb348c97df44	156	#ifndef __TIM_PRESENT
lypinator	0:bb348c97df44	157	#define __TIM_PRESENT 1U
lypinator	0:bb348c97df44	158	#warning "__TIM_PRESENT not defined in device header file; using default!"
lypinator	0:bb348c97df44	159	#endif
lypinator	0:bb348c97df44	160
lypinator	0:bb348c97df44	161	#ifndef __L2C_PRESENT
lypinator	0:bb348c97df44	162	#define __L2C_PRESENT 0U
lypinator	0:bb348c97df44	163	#warning "__L2C_PRESENT not defined in device header file; using default!"
lypinator	0:bb348c97df44	164	#endif
lypinator	0:bb348c97df44	165	#endif
lypinator	0:bb348c97df44	166
lypinator	0:bb348c97df44	167	/* IO definitions (access restrictions to peripheral registers) */
lypinator	0:bb348c97df44	168	#ifdef __cplusplus
lypinator	0:bb348c97df44	169	#define __I volatile /!< \brief Defines 'read only' permissions /
lypinator	0:bb348c97df44	170	#else
lypinator	0:bb348c97df44	171	#define __I volatile const /!< \brief Defines 'read only' permissions /
lypinator	0:bb348c97df44	172	#endif
lypinator	0:bb348c97df44	173	#define __O volatile /!< \brief Defines 'write only' permissions /
lypinator	0:bb348c97df44	174	#define __IO volatile /!< \brief Defines 'read / write' permissions /
lypinator	0:bb348c97df44	175
lypinator	0:bb348c97df44	176	/* following defines should be used for structure members */
lypinator	0:bb348c97df44	177	#define __IM volatile const /!< \brief Defines 'read only' structure member permissions /
lypinator	0:bb348c97df44	178	#define __OM volatile /!< \brief Defines 'write only' structure member permissions /
lypinator	0:bb348c97df44	179	#define __IOM volatile /!< \brief Defines 'read / write' structure member permissions /
lypinator	0:bb348c97df44	180	#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas
lypinator	0:bb348c97df44	181
lypinator	0:bb348c97df44	182	/*******************************************************************************
lypinator	0:bb348c97df44	183	* Register Abstraction
lypinator	0:bb348c97df44	184	Core Register contain:
lypinator	0:bb348c97df44	185	- CPSR
lypinator	0:bb348c97df44	186	- CP15 Registers
lypinator	0:bb348c97df44	187	- L2C-310 Cache Controller
lypinator	0:bb348c97df44	188	- Generic Interrupt Controller Distributor
lypinator	0:bb348c97df44	189	- Generic Interrupt Controller Interface
lypinator	0:bb348c97df44	190	******************************************************************************/
lypinator	0:bb348c97df44	191
lypinator	0:bb348c97df44	192	/* Core Register CPSR */
lypinator	0:bb348c97df44	193	typedef union
lypinator	0:bb348c97df44	194	{
lypinator	0:bb348c97df44	195	struct
lypinator	0:bb348c97df44	196	{
lypinator	0:bb348c97df44	197	uint32_t M:5; /!< \brief bit: 0.. 4 Mode field /
lypinator	0:bb348c97df44	198	uint32_t T:1; /!< \brief bit: 5 Thumb execution state bit /
lypinator	0:bb348c97df44	199	uint32_t F:1; /!< \brief bit: 6 FIQ mask bit /
lypinator	0:bb348c97df44	200	uint32_t I:1; /!< \brief bit: 7 IRQ mask bit /
lypinator	0:bb348c97df44	201	uint32_t A:1; /!< \brief bit: 8 Asynchronous abort mask bit /
lypinator	0:bb348c97df44	202	uint32_t E:1; /!< \brief bit: 9 Endianness execution state bit /
lypinator	0:bb348c97df44	203	uint32_t IT1:6; /!< \brief bit: 10..15 If-Then execution state bits 2-7 /
lypinator	0:bb348c97df44	204	uint32_t GE:4; /!< \brief bit: 16..19 Greater than or Equal flags /
lypinator	0:bb348c97df44	205	RESERVED(0:4, uint32_t)
lypinator	0:bb348c97df44	206	uint32_t J:1; /!< \brief bit: 24 Jazelle bit /
lypinator	0:bb348c97df44	207	uint32_t IT0:2; /!< \brief bit: 25..26 If-Then execution state bits 0-1 /
lypinator	0:bb348c97df44	208	uint32_t Q:1; /!< \brief bit: 27 Saturation condition flag /
lypinator	0:bb348c97df44	209	uint32_t V:1; /!< \brief bit: 28 Overflow condition code flag /
lypinator	0:bb348c97df44	210	uint32_t C:1; /!< \brief bit: 29 Carry condition code flag /
lypinator	0:bb348c97df44	211	uint32_t Z:1; /!< \brief bit: 30 Zero condition code flag /
lypinator	0:bb348c97df44	212	uint32_t N:1; /!< \brief bit: 31 Negative condition code flag /
lypinator	0:bb348c97df44	213	} b; /!< \brief Structure used for bit access /
lypinator	0:bb348c97df44	214	uint32_t w; /!< \brief Type used for word access /
lypinator	0:bb348c97df44	215	} CPSR_Type;
lypinator	0:bb348c97df44	216
lypinator	0:bb348c97df44	217
lypinator	0:bb348c97df44	218
lypinator	0:bb348c97df44	219	/* CPSR Register Definitions */
lypinator	0:bb348c97df44	220	#define CPSR_N_Pos 31U /!< \brief CPSR: N Position /
lypinator	0:bb348c97df44	221	#define CPSR_N_Msk (1UL << CPSR_N_Pos) /!< \brief CPSR: N Mask /
lypinator	0:bb348c97df44	222
lypinator	0:bb348c97df44	223	#define CPSR_Z_Pos 30U /!< \brief CPSR: Z Position /
lypinator	0:bb348c97df44	224	#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /!< \brief CPSR: Z Mask /
lypinator	0:bb348c97df44	225
lypinator	0:bb348c97df44	226	#define CPSR_C_Pos 29U /!< \brief CPSR: C Position /
lypinator	0:bb348c97df44	227	#define CPSR_C_Msk (1UL << CPSR_C_Pos) /!< \brief CPSR: C Mask /
lypinator	0:bb348c97df44	228
lypinator	0:bb348c97df44	229	#define CPSR_V_Pos 28U /!< \brief CPSR: V Position /
lypinator	0:bb348c97df44	230	#define CPSR_V_Msk (1UL << CPSR_V_Pos) /!< \brief CPSR: V Mask /
lypinator	0:bb348c97df44	231
lypinator	0:bb348c97df44	232	#define CPSR_Q_Pos 27U /!< \brief CPSR: Q Position /
lypinator	0:bb348c97df44	233	#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /!< \brief CPSR: Q Mask /
lypinator	0:bb348c97df44	234
lypinator	0:bb348c97df44	235	#define CPSR_IT0_Pos 25U /!< \brief CPSR: IT0 Position /
lypinator	0:bb348c97df44	236	#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /!< \brief CPSR: IT0 Mask /
lypinator	0:bb348c97df44	237
lypinator	0:bb348c97df44	238	#define CPSR_J_Pos 24U /!< \brief CPSR: J Position /
lypinator	0:bb348c97df44	239	#define CPSR_J_Msk (1UL << CPSR_J_Pos) /!< \brief CPSR: J Mask /
lypinator	0:bb348c97df44	240
lypinator	0:bb348c97df44	241	#define CPSR_GE_Pos 16U /!< \brief CPSR: GE Position /
lypinator	0:bb348c97df44	242	#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /!< \brief CPSR: GE Mask /
lypinator	0:bb348c97df44	243
lypinator	0:bb348c97df44	244	#define CPSR_IT1_Pos 10U /!< \brief CPSR: IT1 Position /
lypinator	0:bb348c97df44	245	#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /!< \brief CPSR: IT1 Mask /
lypinator	0:bb348c97df44	246
lypinator	0:bb348c97df44	247	#define CPSR_E_Pos 9U /!< \brief CPSR: E Position /
lypinator	0:bb348c97df44	248	#define CPSR_E_Msk (1UL << CPSR_E_Pos) /!< \brief CPSR: E Mask /
lypinator	0:bb348c97df44	249
lypinator	0:bb348c97df44	250	#define CPSR_A_Pos 8U /!< \brief CPSR: A Position /
lypinator	0:bb348c97df44	251	#define CPSR_A_Msk (1UL << CPSR_A_Pos) /!< \brief CPSR: A Mask /
lypinator	0:bb348c97df44	252
lypinator	0:bb348c97df44	253	#define CPSR_I_Pos 7U /!< \brief CPSR: I Position /
lypinator	0:bb348c97df44	254	#define CPSR_I_Msk (1UL << CPSR_I_Pos) /!< \brief CPSR: I Mask /
lypinator	0:bb348c97df44	255
lypinator	0:bb348c97df44	256	#define CPSR_F_Pos 6U /!< \brief CPSR: F Position /
lypinator	0:bb348c97df44	257	#define CPSR_F_Msk (1UL << CPSR_F_Pos) /!< \brief CPSR: F Mask /
lypinator	0:bb348c97df44	258
lypinator	0:bb348c97df44	259	#define CPSR_T_Pos 5U /!< \brief CPSR: T Position /
lypinator	0:bb348c97df44	260	#define CPSR_T_Msk (1UL << CPSR_T_Pos) /!< \brief CPSR: T Mask /
lypinator	0:bb348c97df44	261
lypinator	0:bb348c97df44	262	#define CPSR_M_Pos 0U /!< \brief CPSR: M Position /
lypinator	0:bb348c97df44	263	#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /!< \brief CPSR: M Mask /
lypinator	0:bb348c97df44	264
lypinator	0:bb348c97df44	265	#define CPSR_M_USR 0x10U /!< \brief CPSR: M User mode (PL0) /
lypinator	0:bb348c97df44	266	#define CPSR_M_FIQ 0x11U /!< \brief CPSR: M Fast Interrupt mode (PL1) /
lypinator	0:bb348c97df44	267	#define CPSR_M_IRQ 0x12U /!< \brief CPSR: M Interrupt mode (PL1) /
lypinator	0:bb348c97df44	268	#define CPSR_M_SVC 0x13U /!< \brief CPSR: M Supervisor mode (PL1) /
lypinator	0:bb348c97df44	269	#define CPSR_M_MON 0x16U /!< \brief CPSR: M Monitor mode (PL1) /
lypinator	0:bb348c97df44	270	#define CPSR_M_ABT 0x17U /!< \brief CPSR: M Abort mode (PL1) /
lypinator	0:bb348c97df44	271	#define CPSR_M_HYP 0x1AU /!< \brief CPSR: M Hypervisor mode (PL2) /
lypinator	0:bb348c97df44	272	#define CPSR_M_UND 0x1BU /!< \brief CPSR: M Undefined mode (PL1) /
lypinator	0:bb348c97df44	273	#define CPSR_M_SYS 0x1FU /!< \brief CPSR: M System mode (PL1) /
lypinator	0:bb348c97df44	274
lypinator	0:bb348c97df44	275	/* CP15 Register SCTLR */
lypinator	0:bb348c97df44	276	typedef union
lypinator	0:bb348c97df44	277	{
lypinator	0:bb348c97df44	278	struct
lypinator	0:bb348c97df44	279	{
lypinator	0:bb348c97df44	280	uint32_t M:1; /!< \brief bit: 0 MMU enable /
lypinator	0:bb348c97df44	281	uint32_t A:1; /!< \brief bit: 1 Alignment check enable /
lypinator	0:bb348c97df44	282	uint32_t C:1; /!< \brief bit: 2 Cache enable /
lypinator	0:bb348c97df44	283	RESERVED(0:2, uint32_t)
lypinator	0:bb348c97df44	284	uint32_t CP15BEN:1; /!< \brief bit: 5 CP15 barrier enable /
lypinator	0:bb348c97df44	285	RESERVED(1:1, uint32_t)
lypinator	0:bb348c97df44	286	uint32_t B:1; /!< \brief bit: 7 Endianness model /
lypinator	0:bb348c97df44	287	RESERVED(2:2, uint32_t)
lypinator	0:bb348c97df44	288	uint32_t SW:1; /!< \brief bit: 10 SWP and SWPB enable /
lypinator	0:bb348c97df44	289	uint32_t Z:1; /!< \brief bit: 11 Branch prediction enable /
lypinator	0:bb348c97df44	290	uint32_t I:1; /!< \brief bit: 12 Instruction cache enable /
lypinator	0:bb348c97df44	291	uint32_t V:1; /!< \brief bit: 13 Vectors bit /
lypinator	0:bb348c97df44	292	uint32_t RR:1; /!< \brief bit: 14 Round Robin select /
lypinator	0:bb348c97df44	293	RESERVED(3:2, uint32_t)
lypinator	0:bb348c97df44	294	uint32_t HA:1; /!< \brief bit: 17 Hardware Access flag enable /
lypinator	0:bb348c97df44	295	RESERVED(4:1, uint32_t)
lypinator	0:bb348c97df44	296	uint32_t WXN:1; /!< \brief bit: 19 Write permission implies XN /
lypinator	0:bb348c97df44	297	uint32_t UWXN:1; /!< \brief bit: 20 Unprivileged write permission implies PL1 XN /
lypinator	0:bb348c97df44	298	uint32_t FI:1; /!< \brief bit: 21 Fast interrupts configuration enable /
lypinator	0:bb348c97df44	299	uint32_t U:1; /!< \brief bit: 22 Alignment model /
lypinator	0:bb348c97df44	300	RESERVED(5:1, uint32_t)
lypinator	0:bb348c97df44	301	uint32_t VE:1; /!< \brief bit: 24 Interrupt Vectors Enable /
lypinator	0:bb348c97df44	302	uint32_t EE:1; /!< \brief bit: 25 Exception Endianness /
lypinator	0:bb348c97df44	303	RESERVED(6:1, uint32_t)
lypinator	0:bb348c97df44	304	uint32_t NMFI:1; /!< \brief bit: 27 Non-maskable FIQ (NMFI) support /
lypinator	0:bb348c97df44	305	uint32_t TRE:1; /!< \brief bit: 28 TEX remap enable. /
lypinator	0:bb348c97df44	306	uint32_t AFE:1; /!< \brief bit: 29 Access flag enable /
lypinator	0:bb348c97df44	307	uint32_t TE:1; /!< \brief bit: 30 Thumb Exception enable /
lypinator	0:bb348c97df44	308	RESERVED(7:1, uint32_t)
lypinator	0:bb348c97df44	309	} b; /!< \brief Structure used for bit access /
lypinator	0:bb348c97df44	310	uint32_t w; /!< \brief Type used for word access /
lypinator	0:bb348c97df44	311	} SCTLR_Type;
lypinator	0:bb348c97df44	312
lypinator	0:bb348c97df44	313	#define SCTLR_TE_Pos 30U /!< \brief SCTLR: TE Position /
lypinator	0:bb348c97df44	314	#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /!< \brief SCTLR: TE Mask /
lypinator	0:bb348c97df44	315
lypinator	0:bb348c97df44	316	#define SCTLR_AFE_Pos 29U /!< \brief SCTLR: AFE Position /
lypinator	0:bb348c97df44	317	#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /!< \brief SCTLR: AFE Mask /
lypinator	0:bb348c97df44	318
lypinator	0:bb348c97df44	319	#define SCTLR_TRE_Pos 28U /!< \brief SCTLR: TRE Position /
lypinator	0:bb348c97df44	320	#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /!< \brief SCTLR: TRE Mask /
lypinator	0:bb348c97df44	321
lypinator	0:bb348c97df44	322	#define SCTLR_NMFI_Pos 27U /!< \brief SCTLR: NMFI Position /
lypinator	0:bb348c97df44	323	#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /!< \brief SCTLR: NMFI Mask /
lypinator	0:bb348c97df44	324
lypinator	0:bb348c97df44	325	#define SCTLR_EE_Pos 25U /!< \brief SCTLR: EE Position /
lypinator	0:bb348c97df44	326	#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /!< \brief SCTLR: EE Mask /
lypinator	0:bb348c97df44	327
lypinator	0:bb348c97df44	328	#define SCTLR_VE_Pos 24U /!< \brief SCTLR: VE Position /
lypinator	0:bb348c97df44	329	#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /!< \brief SCTLR: VE Mask /
lypinator	0:bb348c97df44	330
lypinator	0:bb348c97df44	331	#define SCTLR_U_Pos 22U /!< \brief SCTLR: U Position /
lypinator	0:bb348c97df44	332	#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /!< \brief SCTLR: U Mask /
lypinator	0:bb348c97df44	333
lypinator	0:bb348c97df44	334	#define SCTLR_FI_Pos 21U /!< \brief SCTLR: FI Position /
lypinator	0:bb348c97df44	335	#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /!< \brief SCTLR: FI Mask /
lypinator	0:bb348c97df44	336
lypinator	0:bb348c97df44	337	#define SCTLR_UWXN_Pos 20U /!< \brief SCTLR: UWXN Position /
lypinator	0:bb348c97df44	338	#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /!< \brief SCTLR: UWXN Mask /
lypinator	0:bb348c97df44	339
lypinator	0:bb348c97df44	340	#define SCTLR_WXN_Pos 19U /!< \brief SCTLR: WXN Position /
lypinator	0:bb348c97df44	341	#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /!< \brief SCTLR: WXN Mask /
lypinator	0:bb348c97df44	342
lypinator	0:bb348c97df44	343	#define SCTLR_HA_Pos 17U /!< \brief SCTLR: HA Position /
lypinator	0:bb348c97df44	344	#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /!< \brief SCTLR: HA Mask /
lypinator	0:bb348c97df44	345
lypinator	0:bb348c97df44	346	#define SCTLR_RR_Pos 14U /!< \brief SCTLR: RR Position /
lypinator	0:bb348c97df44	347	#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /!< \brief SCTLR: RR Mask /
lypinator	0:bb348c97df44	348
lypinator	0:bb348c97df44	349	#define SCTLR_V_Pos 13U /!< \brief SCTLR: V Position /
lypinator	0:bb348c97df44	350	#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /!< \brief SCTLR: V Mask /
lypinator	0:bb348c97df44	351
lypinator	0:bb348c97df44	352	#define SCTLR_I_Pos 12U /!< \brief SCTLR: I Position /
lypinator	0:bb348c97df44	353	#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /!< \brief SCTLR: I Mask /
lypinator	0:bb348c97df44	354
lypinator	0:bb348c97df44	355	#define SCTLR_Z_Pos 11U /!< \brief SCTLR: Z Position /
lypinator	0:bb348c97df44	356	#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /!< \brief SCTLR: Z Mask /
lypinator	0:bb348c97df44	357
lypinator	0:bb348c97df44	358	#define SCTLR_SW_Pos 10U /!< \brief SCTLR: SW Position /
lypinator	0:bb348c97df44	359	#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /!< \brief SCTLR: SW Mask /
lypinator	0:bb348c97df44	360
lypinator	0:bb348c97df44	361	#define SCTLR_B_Pos 7U /!< \brief SCTLR: B Position /
lypinator	0:bb348c97df44	362	#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /!< \brief SCTLR: B Mask /
lypinator	0:bb348c97df44	363
lypinator	0:bb348c97df44	364	#define SCTLR_CP15BEN_Pos 5U /!< \brief SCTLR: CP15BEN Position /
lypinator	0:bb348c97df44	365	#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /!< \brief SCTLR: CP15BEN Mask /
lypinator	0:bb348c97df44	366
lypinator	0:bb348c97df44	367	#define SCTLR_C_Pos 2U /!< \brief SCTLR: C Position /
lypinator	0:bb348c97df44	368	#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /!< \brief SCTLR: C Mask /
lypinator	0:bb348c97df44	369
lypinator	0:bb348c97df44	370	#define SCTLR_A_Pos 1U /!< \brief SCTLR: A Position /
lypinator	0:bb348c97df44	371	#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /!< \brief SCTLR: A Mask /
lypinator	0:bb348c97df44	372
lypinator	0:bb348c97df44	373	#define SCTLR_M_Pos 0U /!< \brief SCTLR: M Position /
lypinator	0:bb348c97df44	374	#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /!< \brief SCTLR: M Mask /
lypinator	0:bb348c97df44	375
lypinator	0:bb348c97df44	376	/* CP15 Register ACTLR */
lypinator	0:bb348c97df44	377	typedef union
lypinator	0:bb348c97df44	378	{
lypinator	0:bb348c97df44	379	#if __CORTEX_A == 5 \|\| defined(DOXYGEN)
lypinator	0:bb348c97df44	380	/** \brief Structure used for bit access on Cortex-A5 */
lypinator	0:bb348c97df44	381	struct
lypinator	0:bb348c97df44	382	{
lypinator	0:bb348c97df44	383	uint32_t FW:1; /!< \brief bit: 0 Cache and TLB maintenance broadcast /
lypinator	0:bb348c97df44	384	RESERVED(0:5, uint32_t)
lypinator	0:bb348c97df44	385	uint32_t SMP:1; /!< \brief bit: 6 Enables coherent requests to the processor /
lypinator	0:bb348c97df44	386	uint32_t EXCL:1; /!< \brief bit: 7 Exclusive L1/L2 cache control /
lypinator	0:bb348c97df44	387	RESERVED(1:2, uint32_t)
lypinator	0:bb348c97df44	388	uint32_t DODMBS:1; /!< \brief bit: 10 Disable optimized data memory barrier behavior /
lypinator	0:bb348c97df44	389	uint32_t DWBST:1; /!< \brief bit: 11 AXI data write bursts to Normal memory /
lypinator	0:bb348c97df44	390	uint32_t RADIS:1; /!< \brief bit: 12 L1 Data Cache read-allocate mode disable /
lypinator	0:bb348c97df44	391	uint32_t L1PCTL:2; /!< \brief bit:13..14 L1 Data prefetch control /
lypinator	0:bb348c97df44	392	uint32_t BP:2; /!< \brief bit:16..15 Branch prediction policy /
lypinator	0:bb348c97df44	393	uint32_t RSDIS:1; /!< \brief bit: 17 Disable return stack operation /
lypinator	0:bb348c97df44	394	uint32_t BTDIS:1; /!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) /
lypinator	0:bb348c97df44	395	RESERVED(3:9, uint32_t)
lypinator	0:bb348c97df44	396	uint32_t DBDI:1; /!< \brief bit: 28 Disable branch dual issue /
lypinator	0:bb348c97df44	397	RESERVED(7:3, uint32_t)
lypinator	0:bb348c97df44	398	} b;
lypinator	0:bb348c97df44	399	#endif
lypinator	0:bb348c97df44	400	#if __CORTEX_A == 7 \|\| defined(DOXYGEN)
lypinator	0:bb348c97df44	401	/** \brief Structure used for bit access on Cortex-A7 */
lypinator	0:bb348c97df44	402	struct
lypinator	0:bb348c97df44	403	{
lypinator	0:bb348c97df44	404	RESERVED(0:6, uint32_t)
lypinator	0:bb348c97df44	405	uint32_t SMP:1; /!< \brief bit: 6 Enables coherent requests to the processor /
lypinator	0:bb348c97df44	406	RESERVED(1:3, uint32_t)
lypinator	0:bb348c97df44	407	uint32_t DODMBS:1; /!< \brief bit: 10 Disable optimized data memory barrier behavior /
lypinator	0:bb348c97df44	408	uint32_t L2RADIS:1; /!< \brief bit: 11 L2 Data Cache read-allocate mode disable /
lypinator	0:bb348c97df44	409	uint32_t L1RADIS:1; /!< \brief bit: 12 L1 Data Cache read-allocate mode disable /
lypinator	0:bb348c97df44	410	uint32_t L1PCTL:2; /!< \brief bit:13..14 L1 Data prefetch control /
lypinator	0:bb348c97df44	411	uint32_t DDVM:1; /!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions /
lypinator	0:bb348c97df44	412	RESERVED(3:12, uint32_t)
lypinator	0:bb348c97df44	413	uint32_t DDI:1; /!< \brief bit: 28 Disable dual issue /
lypinator	0:bb348c97df44	414	RESERVED(7:3, uint32_t)
lypinator	0:bb348c97df44	415	} b;
lypinator	0:bb348c97df44	416	#endif
lypinator	0:bb348c97df44	417	#if __CORTEX_A == 9 \|\| defined(DOXYGEN)
lypinator	0:bb348c97df44	418	/** \brief Structure used for bit access on Cortex-A9 */
lypinator	0:bb348c97df44	419	struct
lypinator	0:bb348c97df44	420	{
lypinator	0:bb348c97df44	421	uint32_t FW:1; /!< \brief bit: 0 Cache and TLB maintenance broadcast /
lypinator	0:bb348c97df44	422	RESERVED(0:1, uint32_t)
lypinator	0:bb348c97df44	423	uint32_t L1PE:1; /!< \brief bit: 2 Dside prefetch /
lypinator	0:bb348c97df44	424	uint32_t WFLZM:1; /!< \brief bit: 3 Cache and TLB maintenance broadcast /
lypinator	0:bb348c97df44	425	RESERVED(1:2, uint32_t)
lypinator	0:bb348c97df44	426	uint32_t SMP:1; /!< \brief bit: 6 Enables coherent requests to the processor /
lypinator	0:bb348c97df44	427	uint32_t EXCL:1; /!< \brief bit: 7 Exclusive L1/L2 cache control /
lypinator	0:bb348c97df44	428	uint32_t AOW:1; /!< \brief bit: 8 Enable allocation in one cache way only /
lypinator	0:bb348c97df44	429	uint32_t PARITY:1; /!< \brief bit: 9 Support for parity checking, if implemented /
lypinator	0:bb348c97df44	430	RESERVED(7:22, uint32_t)
lypinator	0:bb348c97df44	431	} b;
lypinator	0:bb348c97df44	432	#endif
lypinator	0:bb348c97df44	433	uint32_t w; /!< \brief Type used for word access /
lypinator	0:bb348c97df44	434	} ACTLR_Type;
lypinator	0:bb348c97df44	435
lypinator	0:bb348c97df44	436	#define ACTLR_DDI_Pos 28U /!< \brief ACTLR: DDI Position /
lypinator	0:bb348c97df44	437	#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /!< \brief ACTLR: DDI Mask /
lypinator	0:bb348c97df44	438
lypinator	0:bb348c97df44	439	#define ACTLR_DBDI_Pos 28U /!< \brief ACTLR: DBDI Position /
lypinator	0:bb348c97df44	440	#define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /!< \brief ACTLR: DBDI Mask /
lypinator	0:bb348c97df44	441
lypinator	0:bb348c97df44	442	#define ACTLR_BTDIS_Pos 18U /!< \brief ACTLR: BTDIS Position /
lypinator	0:bb348c97df44	443	#define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /!< \brief ACTLR: BTDIS Mask /
lypinator	0:bb348c97df44	444
lypinator	0:bb348c97df44	445	#define ACTLR_RSDIS_Pos 17U /!< \brief ACTLR: RSDIS Position /
lypinator	0:bb348c97df44	446	#define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /!< \brief ACTLR: RSDIS Mask /
lypinator	0:bb348c97df44	447
lypinator	0:bb348c97df44	448	#define ACTLR_BP_Pos 15U /!< \brief ACTLR: BP Position /
lypinator	0:bb348c97df44	449	#define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /!< \brief ACTLR: BP Mask /
lypinator	0:bb348c97df44	450
lypinator	0:bb348c97df44	451	#define ACTLR_DDVM_Pos 15U /!< \brief ACTLR: DDVM Position /
lypinator	0:bb348c97df44	452	#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /!< \brief ACTLR: DDVM Mask /
lypinator	0:bb348c97df44	453
lypinator	0:bb348c97df44	454	#define ACTLR_L1PCTL_Pos 13U /!< \brief ACTLR: L1PCTL Position /
lypinator	0:bb348c97df44	455	#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /!< \brief ACTLR: L1PCTL Mask /
lypinator	0:bb348c97df44	456
lypinator	0:bb348c97df44	457	#define ACTLR_RADIS_Pos 12U /!< \brief ACTLR: RADIS Position /
lypinator	0:bb348c97df44	458	#define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /!< \brief ACTLR: RADIS Mask /
lypinator	0:bb348c97df44	459
lypinator	0:bb348c97df44	460	#define ACTLR_L1RADIS_Pos 12U /!< \brief ACTLR: L1RADIS Position /
lypinator	0:bb348c97df44	461	#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /!< \brief ACTLR: L1RADIS Mask /
lypinator	0:bb348c97df44	462
lypinator	0:bb348c97df44	463	#define ACTLR_DWBST_Pos 11U /!< \brief ACTLR: DWBST Position /
lypinator	0:bb348c97df44	464	#define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /!< \brief ACTLR: DWBST Mask /
lypinator	0:bb348c97df44	465
lypinator	0:bb348c97df44	466	#define ACTLR_L2RADIS_Pos 11U /!< \brief ACTLR: L2RADIS Position /
lypinator	0:bb348c97df44	467	#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /!< \brief ACTLR: L2RADIS Mask /
lypinator	0:bb348c97df44	468
lypinator	0:bb348c97df44	469	#define ACTLR_DODMBS_Pos 10U /!< \brief ACTLR: DODMBS Position /
lypinator	0:bb348c97df44	470	#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /!< \brief ACTLR: DODMBS Mask /
lypinator	0:bb348c97df44	471
lypinator	0:bb348c97df44	472	#define ACTLR_PARITY_Pos 9U /!< \brief ACTLR: PARITY Position /
lypinator	0:bb348c97df44	473	#define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /!< \brief ACTLR: PARITY Mask /
lypinator	0:bb348c97df44	474
lypinator	0:bb348c97df44	475	#define ACTLR_AOW_Pos 8U /!< \brief ACTLR: AOW Position /
lypinator	0:bb348c97df44	476	#define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /!< \brief ACTLR: AOW Mask /
lypinator	0:bb348c97df44	477
lypinator	0:bb348c97df44	478	#define ACTLR_EXCL_Pos 7U /!< \brief ACTLR: EXCL Position /
lypinator	0:bb348c97df44	479	#define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /!< \brief ACTLR: EXCL Mask /
lypinator	0:bb348c97df44	480
lypinator	0:bb348c97df44	481	#define ACTLR_SMP_Pos 6U /!< \brief ACTLR: SMP Position /
lypinator	0:bb348c97df44	482	#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /!< \brief ACTLR: SMP Mask /
lypinator	0:bb348c97df44	483
lypinator	0:bb348c97df44	484	#define ACTLR_WFLZM_Pos 3U /!< \brief ACTLR: WFLZM Position /
lypinator	0:bb348c97df44	485	#define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /!< \brief ACTLR: WFLZM Mask /
lypinator	0:bb348c97df44	486
lypinator	0:bb348c97df44	487	#define ACTLR_L1PE_Pos 2U /!< \brief ACTLR: L1PE Position /
lypinator	0:bb348c97df44	488	#define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /!< \brief ACTLR: L1PE Mask /
lypinator	0:bb348c97df44	489
lypinator	0:bb348c97df44	490	#define ACTLR_FW_Pos 0U /!< \brief ACTLR: FW Position /
lypinator	0:bb348c97df44	491	#define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /!< \brief ACTLR: FW Mask /
lypinator	0:bb348c97df44	492
lypinator	0:bb348c97df44	493	/* CP15 Register CPACR */
lypinator	0:bb348c97df44	494	typedef union
lypinator	0:bb348c97df44	495	{
lypinator	0:bb348c97df44	496	struct
lypinator	0:bb348c97df44	497	{
lypinator	0:bb348c97df44	498	uint32_t CP0:2; /!< \brief bit: 0..1 Access rights for coprocessor 0 /
lypinator	0:bb348c97df44	499	uint32_t CP1:2; /!< \brief bit: 2..3 Access rights for coprocessor 1 /
lypinator	0:bb348c97df44	500	uint32_t CP2:2; /!< \brief bit: 4..5 Access rights for coprocessor 2 /
lypinator	0:bb348c97df44	501	uint32_t CP3:2; /!< \brief bit: 6..7 Access rights for coprocessor 3 /
lypinator	0:bb348c97df44	502	uint32_t CP4:2; /!< \brief bit: 8..9 Access rights for coprocessor 4 /
lypinator	0:bb348c97df44	503	uint32_t CP5:2; /!< \brief bit:10..11 Access rights for coprocessor 5 /
lypinator	0:bb348c97df44	504	uint32_t CP6:2; /!< \brief bit:12..13 Access rights for coprocessor 6 /
lypinator	0:bb348c97df44	505	uint32_t CP7:2; /!< \brief bit:14..15 Access rights for coprocessor 7 /
lypinator	0:bb348c97df44	506	uint32_t CP8:2; /!< \brief bit:16..17 Access rights for coprocessor 8 /
lypinator	0:bb348c97df44	507	uint32_t CP9:2; /!< \brief bit:18..19 Access rights for coprocessor 9 /
lypinator	0:bb348c97df44	508	uint32_t CP10:2; /!< \brief bit:20..21 Access rights for coprocessor 10 /
lypinator	0:bb348c97df44	509	uint32_t CP11:2; /!< \brief bit:22..23 Access rights for coprocessor 11 /
lypinator	0:bb348c97df44	510	uint32_t CP12:2; /!< \brief bit:24..25 Access rights for coprocessor 11 /
lypinator	0:bb348c97df44	511	uint32_t CP13:2; /!< \brief bit:26..27 Access rights for coprocessor 11 /
lypinator	0:bb348c97df44	512	uint32_t TRCDIS:1; /!< \brief bit: 28 Disable CP14 access to trace registers /
lypinator	0:bb348c97df44	513	RESERVED(0:1, uint32_t)
lypinator	0:bb348c97df44	514	uint32_t D32DIS:1; /!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file /
lypinator	0:bb348c97df44	515	uint32_t ASEDIS:1; /!< \brief bit: 31 Disable Advanced SIMD Functionality /
lypinator	0:bb348c97df44	516	} b; /!< \brief Structure used for bit access /
lypinator	0:bb348c97df44	517	uint32_t w; /!< \brief Type used for word access /
lypinator	0:bb348c97df44	518	} CPACR_Type;
lypinator	0:bb348c97df44	519
lypinator	0:bb348c97df44	520	#define CPACR_ASEDIS_Pos 31U /!< \brief CPACR: ASEDIS Position /
lypinator	0:bb348c97df44	521	#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /!< \brief CPACR: ASEDIS Mask /
lypinator	0:bb348c97df44	522
lypinator	0:bb348c97df44	523	#define CPACR_D32DIS_Pos 30U /!< \brief CPACR: D32DIS Position /
lypinator	0:bb348c97df44	524	#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /!< \brief CPACR: D32DIS Mask /
lypinator	0:bb348c97df44	525
lypinator	0:bb348c97df44	526	#define CPACR_TRCDIS_Pos 28U /!< \brief CPACR: D32DIS Position /
lypinator	0:bb348c97df44	527	#define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /!< \brief CPACR: D32DIS Mask /
lypinator	0:bb348c97df44	528
lypinator	0:bb348c97df44	529	#define CPACR_CP_Pos_(n) (n2U) /!< \brief CPACR: CPn Position */
lypinator	0:bb348c97df44	530	#define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /!< \brief CPACR: CPn Mask /
lypinator	0:bb348c97df44	531
lypinator	0:bb348c97df44	532	#define CPACR_CP_NA 0U /!< \brief CPACR CPn field: Access denied. /
lypinator	0:bb348c97df44	533	#define CPACR_CP_PL1 1U /!< \brief CPACR CPn field: Accessible from PL1 only. /
lypinator	0:bb348c97df44	534	#define CPACR_CP_FA 3U /!< \brief CPACR CPn field: Full access. /
lypinator	0:bb348c97df44	535
lypinator	0:bb348c97df44	536	/* CP15 Register DFSR */
lypinator	0:bb348c97df44	537	typedef union
lypinator	0:bb348c97df44	538	{
lypinator	0:bb348c97df44	539	struct
lypinator	0:bb348c97df44	540	{
lypinator	0:bb348c97df44	541	uint32_t FS0:4; /!< \brief bit: 0.. 3 Fault Status bits bit 0-3 /
lypinator	0:bb348c97df44	542	uint32_t Domain:4; /!< \brief bit: 4.. 7 Fault on which domain /
lypinator	0:bb348c97df44	543	RESERVED(0:1, uint32_t)
lypinator	0:bb348c97df44	544	uint32_t LPAE:1; /!< \brief bit: 9 Large Physical Address Extension /
lypinator	0:bb348c97df44	545	uint32_t FS1:1; /!< \brief bit: 10 Fault Status bits bit 4 /
lypinator	0:bb348c97df44	546	uint32_t WnR:1; /!< \brief bit: 11 Write not Read bit /
lypinator	0:bb348c97df44	547	uint32_t ExT:1; /!< \brief bit: 12 External abort type /
lypinator	0:bb348c97df44	548	uint32_t CM:1; /!< \brief bit: 13 Cache maintenance fault /
lypinator	0:bb348c97df44	549	RESERVED(1:18, uint32_t)
lypinator	0:bb348c97df44	550	} s; /!< \brief Structure used for bit access in short format /
lypinator	0:bb348c97df44	551	struct
lypinator	0:bb348c97df44	552	{
lypinator	0:bb348c97df44	553	uint32_t STATUS:5; /!< \brief bit: 0.. 5 Fault Status bits /
lypinator	0:bb348c97df44	554	RESERVED(0:3, uint32_t)
lypinator	0:bb348c97df44	555	uint32_t LPAE:1; /!< \brief bit: 9 Large Physical Address Extension /
lypinator	0:bb348c97df44	556	RESERVED(1:1, uint32_t)
lypinator	0:bb348c97df44	557	uint32_t WnR:1; /!< \brief bit: 11 Write not Read bit /
lypinator	0:bb348c97df44	558	uint32_t ExT:1; /!< \brief bit: 12 External abort type /
lypinator	0:bb348c97df44	559	uint32_t CM:1; /!< \brief bit: 13 Cache maintenance fault /
lypinator	0:bb348c97df44	560	RESERVED(2:18, uint32_t)
lypinator	0:bb348c97df44	561	} l; /!< \brief Structure used for bit access in long format /
lypinator	0:bb348c97df44	562	uint32_t w; /!< \brief Type used for word access /
lypinator	0:bb348c97df44	563	} DFSR_Type;
lypinator	0:bb348c97df44	564
lypinator	0:bb348c97df44	565	#define DFSR_CM_Pos 13U /!< \brief DFSR: CM Position /
lypinator	0:bb348c97df44	566	#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /!< \brief DFSR: CM Mask /
lypinator	0:bb348c97df44	567
lypinator	0:bb348c97df44	568	#define DFSR_Ext_Pos 12U /!< \brief DFSR: Ext Position /
lypinator	0:bb348c97df44	569	#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /!< \brief DFSR: Ext Mask /
lypinator	0:bb348c97df44	570
lypinator	0:bb348c97df44	571	#define DFSR_WnR_Pos 11U /!< \brief DFSR: WnR Position /
lypinator	0:bb348c97df44	572	#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /!< \brief DFSR: WnR Mask /
lypinator	0:bb348c97df44	573
lypinator	0:bb348c97df44	574	#define DFSR_FS1_Pos 10U /!< \brief DFSR: FS1 Position /
lypinator	0:bb348c97df44	575	#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /!< \brief DFSR: FS1 Mask /
lypinator	0:bb348c97df44	576
lypinator	0:bb348c97df44	577	#define DFSR_LPAE_Pos 9U /!< \brief DFSR: LPAE Position /
lypinator	0:bb348c97df44	578	#define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /!< \brief DFSR: LPAE Mask /
lypinator	0:bb348c97df44	579
lypinator	0:bb348c97df44	580	#define DFSR_Domain_Pos 4U /!< \brief DFSR: Domain Position /
lypinator	0:bb348c97df44	581	#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /!< \brief DFSR: Domain Mask /
lypinator	0:bb348c97df44	582
lypinator	0:bb348c97df44	583	#define DFSR_FS0_Pos 0U /!< \brief DFSR: FS0 Position /
lypinator	0:bb348c97df44	584	#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /!< \brief DFSR: FS0 Mask /
lypinator	0:bb348c97df44	585
lypinator	0:bb348c97df44	586	#define DFSR_STATUS_Pos 0U /!< \brief DFSR: STATUS Position /
lypinator	0:bb348c97df44	587	#define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /!< \brief DFSR: STATUS Mask /
lypinator	0:bb348c97df44	588
lypinator	0:bb348c97df44	589	/* CP15 Register IFSR */
lypinator	0:bb348c97df44	590	typedef union
lypinator	0:bb348c97df44	591	{
lypinator	0:bb348c97df44	592	struct
lypinator	0:bb348c97df44	593	{
lypinator	0:bb348c97df44	594	uint32_t FS0:4; /!< \brief bit: 0.. 3 Fault Status bits bit 0-3 /
lypinator	0:bb348c97df44	595	RESERVED(0:5, uint32_t)
lypinator	0:bb348c97df44	596	uint32_t LPAE:1; /!< \brief bit: 9 Large Physical Address Extension /
lypinator	0:bb348c97df44	597	uint32_t FS1:1; /!< \brief bit: 10 Fault Status bits bit 4 /
lypinator	0:bb348c97df44	598	RESERVED(1:1, uint32_t)
lypinator	0:bb348c97df44	599	uint32_t ExT:1; /!< \brief bit: 12 External abort type /
lypinator	0:bb348c97df44	600	RESERVED(2:19, uint32_t)
lypinator	0:bb348c97df44	601	} s; /!< \brief Structure used for bit access in short format /
lypinator	0:bb348c97df44	602	struct
lypinator	0:bb348c97df44	603	{
lypinator	0:bb348c97df44	604	uint32_t STATUS:6; /!< \brief bit: 0.. 5 Fault Status bits /
lypinator	0:bb348c97df44	605	RESERVED(0:3, uint32_t)
lypinator	0:bb348c97df44	606	uint32_t LPAE:1; /!< \brief bit: 9 Large Physical Address Extension /
lypinator	0:bb348c97df44	607	RESERVED(1:2, uint32_t)
lypinator	0:bb348c97df44	608	uint32_t ExT:1; /!< \brief bit: 12 External abort type /
lypinator	0:bb348c97df44	609	RESERVED(2:19, uint32_t)
lypinator	0:bb348c97df44	610	} l; /!< \brief Structure used for bit access in long format /
lypinator	0:bb348c97df44	611	uint32_t w; /!< \brief Type used for word access /
lypinator	0:bb348c97df44	612	} IFSR_Type;
lypinator	0:bb348c97df44	613
lypinator	0:bb348c97df44	614	#define IFSR_ExT_Pos 12U /!< \brief IFSR: ExT Position /
lypinator	0:bb348c97df44	615	#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /!< \brief IFSR: ExT Mask /
lypinator	0:bb348c97df44	616
lypinator	0:bb348c97df44	617	#define IFSR_FS1_Pos 10U /!< \brief IFSR: FS1 Position /
lypinator	0:bb348c97df44	618	#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /!< \brief IFSR: FS1 Mask /
lypinator	0:bb348c97df44	619
lypinator	0:bb348c97df44	620	#define IFSR_LPAE_Pos 9U /!< \brief IFSR: LPAE Position /
lypinator	0:bb348c97df44	621	#define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /!< \brief IFSR: LPAE Mask /
lypinator	0:bb348c97df44	622
lypinator	0:bb348c97df44	623	#define IFSR_FS0_Pos 0U /!< \brief IFSR: FS0 Position /
lypinator	0:bb348c97df44	624	#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /!< \brief IFSR: FS0 Mask /
lypinator	0:bb348c97df44	625
lypinator	0:bb348c97df44	626	#define IFSR_STATUS_Pos 0U /!< \brief IFSR: STATUS Position /
lypinator	0:bb348c97df44	627	#define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /!< \brief IFSR: STATUS Mask /
lypinator	0:bb348c97df44	628
lypinator	0:bb348c97df44	629	/* CP15 Register ISR */
lypinator	0:bb348c97df44	630	typedef union
lypinator	0:bb348c97df44	631	{
lypinator	0:bb348c97df44	632	struct
lypinator	0:bb348c97df44	633	{
lypinator	0:bb348c97df44	634	RESERVED(0:6, uint32_t)
lypinator	0:bb348c97df44	635	uint32_t F:1; /!< \brief bit: 6 FIQ pending bit /
lypinator	0:bb348c97df44	636	uint32_t I:1; /!< \brief bit: 7 IRQ pending bit /
lypinator	0:bb348c97df44	637	uint32_t A:1; /!< \brief bit: 8 External abort pending bit /
lypinator	0:bb348c97df44	638	RESERVED(1:23, uint32_t)
lypinator	0:bb348c97df44	639	} b; /!< \brief Structure used for bit access /
lypinator	0:bb348c97df44	640	uint32_t w; /!< \brief Type used for word access /
lypinator	0:bb348c97df44	641	} ISR_Type;
lypinator	0:bb348c97df44	642
lypinator	0:bb348c97df44	643	#define ISR_A_Pos 13U /!< \brief ISR: A Position /
lypinator	0:bb348c97df44	644	#define ISR_A_Msk (1UL << ISR_A_Pos) /!< \brief ISR: A Mask /
lypinator	0:bb348c97df44	645
lypinator	0:bb348c97df44	646	#define ISR_I_Pos 12U /!< \brief ISR: I Position /
lypinator	0:bb348c97df44	647	#define ISR_I_Msk (1UL << ISR_I_Pos) /!< \brief ISR: I Mask /
lypinator	0:bb348c97df44	648
lypinator	0:bb348c97df44	649	#define ISR_F_Pos 11U /!< \brief ISR: F Position /
lypinator	0:bb348c97df44	650	#define ISR_F_Msk (1UL << ISR_F_Pos) /!< \brief ISR: F Mask /
lypinator	0:bb348c97df44	651
lypinator	0:bb348c97df44	652	/* DACR Register */
lypinator	0:bb348c97df44	653	#define DACR_D_Pos_(n) (2Un) /!< \brief DACR: Dn Position */
lypinator	0:bb348c97df44	654	#define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /!< \brief DACR: Dn Mask /
lypinator	0:bb348c97df44	655	#define DACR_Dn_NOACCESS 0U /!< \brief DACR Dn field: No access /
lypinator	0:bb348c97df44	656	#define DACR_Dn_CLIENT 1U /!< \brief DACR Dn field: Client /
lypinator	0:bb348c97df44	657	#define DACR_Dn_MANAGER 3U /!< \brief DACR Dn field: Manager /
lypinator	0:bb348c97df44	658
lypinator	0:bb348c97df44	659	/**
lypinator	0:bb348c97df44	660	\brief Mask and shift a bit field value for use in a register bit range.
lypinator	0:bb348c97df44	661	\param [in] field Name of the register bit field.
lypinator	0:bb348c97df44	662	\param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
lypinator	0:bb348c97df44	663	\return Masked and shifted value.
lypinator	0:bb348c97df44	664	*/
lypinator	0:bb348c97df44	665	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
lypinator	0:bb348c97df44	666
lypinator	0:bb348c97df44	667	/**
lypinator	0:bb348c97df44	668	\brief Mask and shift a register value to extract a bit filed value.
lypinator	0:bb348c97df44	669	\param [in] field Name of the register bit field.
lypinator	0:bb348c97df44	670	\param [in] value Value of register. This parameter is interpreted as an uint32_t type.
lypinator	0:bb348c97df44	671	\return Masked and shifted bit field value.
lypinator	0:bb348c97df44	672	*/
lypinator	0:bb348c97df44	673	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
lypinator	0:bb348c97df44	674
lypinator	0:bb348c97df44	675
lypinator	0:bb348c97df44	676	/**
lypinator	0:bb348c97df44	677	\brief Union type to access the L2C_310 Cache Controller.
lypinator	0:bb348c97df44	678	*/
lypinator	0:bb348c97df44	679	#if (__L2C_PRESENT == 1U) \|\| defined(DOXYGEN)
lypinator	0:bb348c97df44	680	typedef struct
lypinator	0:bb348c97df44	681	{
lypinator	0:bb348c97df44	682	__IM uint32_t CACHE_ID; /!< \brief Offset: 0x0000 (R/ ) Cache ID Register /
lypinator	0:bb348c97df44	683	__IM uint32_t CACHE_TYPE; /!< \brief Offset: 0x0004 (R/ ) Cache Type Register /
lypinator	0:bb348c97df44	684	RESERVED(0[0x3e], uint32_t)
lypinator	0:bb348c97df44	685	__IOM uint32_t CONTROL; /!< \brief Offset: 0x0100 (R/W) Control Register /
lypinator	0:bb348c97df44	686	__IOM uint32_t AUX_CNT; /!< \brief Offset: 0x0104 (R/W) Auxiliary Control /
lypinator	0:bb348c97df44	687	RESERVED(1[0x3e], uint32_t)
lypinator	0:bb348c97df44	688	__IOM uint32_t EVENT_CONTROL; /!< \brief Offset: 0x0200 (R/W) Event Counter Control /
lypinator	0:bb348c97df44	689	__IOM uint32_t EVENT_COUNTER1_CONF; /!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration /
lypinator	0:bb348c97df44	690	__IOM uint32_t EVENT_COUNTER0_CONF; /!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration /
lypinator	0:bb348c97df44	691	RESERVED(2[0x2], uint32_t)
lypinator	0:bb348c97df44	692	__IOM uint32_t INTERRUPT_MASK; /!< \brief Offset: 0x0214 (R/W) Interrupt Mask /
lypinator	0:bb348c97df44	693	__IM uint32_t MASKED_INT_STATUS; /!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status /
lypinator	0:bb348c97df44	694	__IM uint32_t RAW_INT_STATUS; /!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status /
lypinator	0:bb348c97df44	695	__OM uint32_t INTERRUPT_CLEAR; /!< \brief Offset: 0x0220 ( /W) Interrupt Clear /
lypinator	0:bb348c97df44	696	RESERVED(3[0x143], uint32_t)
lypinator	0:bb348c97df44	697	__IOM uint32_t CACHE_SYNC; /!< \brief Offset: 0x0730 (R/W) Cache Sync /
lypinator	0:bb348c97df44	698	RESERVED(4[0xf], uint32_t)
lypinator	0:bb348c97df44	699	__IOM uint32_t INV_LINE_PA; /!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA /
lypinator	0:bb348c97df44	700	RESERVED(6[2], uint32_t)
lypinator	0:bb348c97df44	701	__IOM uint32_t INV_WAY; /!< \brief Offset: 0x077c (R/W) Invalidate by Way /
lypinator	0:bb348c97df44	702	RESERVED(5[0xc], uint32_t)
lypinator	0:bb348c97df44	703	__IOM uint32_t CLEAN_LINE_PA; /!< \brief Offset: 0x07b0 (R/W) Clean Line by PA /
lypinator	0:bb348c97df44	704	RESERVED(7[1], uint32_t)
lypinator	0:bb348c97df44	705	__IOM uint32_t CLEAN_LINE_INDEX_WAY; /!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way /
lypinator	0:bb348c97df44	706	__IOM uint32_t CLEAN_WAY; /!< \brief Offset: 0x07bc (R/W) Clean by Way /
lypinator	0:bb348c97df44	707	RESERVED(8[0xc], uint32_t)
lypinator	0:bb348c97df44	708	__IOM uint32_t CLEAN_INV_LINE_PA; /!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA /
lypinator	0:bb348c97df44	709	RESERVED(9[1], uint32_t)
lypinator	0:bb348c97df44	710	__IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way /
lypinator	0:bb348c97df44	711	__IOM uint32_t CLEAN_INV_WAY; /!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way /
lypinator	0:bb348c97df44	712	RESERVED(10[0x40], uint32_t)
lypinator	0:bb348c97df44	713	__IOM uint32_t DATA_LOCK_0_WAY; /!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way /
lypinator	0:bb348c97df44	714	__IOM uint32_t INST_LOCK_0_WAY; /!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way /
lypinator	0:bb348c97df44	715	__IOM uint32_t DATA_LOCK_1_WAY; /!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way /
lypinator	0:bb348c97df44	716	__IOM uint32_t INST_LOCK_1_WAY; /!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way /
lypinator	0:bb348c97df44	717	__IOM uint32_t DATA_LOCK_2_WAY; /!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way /
lypinator	0:bb348c97df44	718	__IOM uint32_t INST_LOCK_2_WAY; /!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way /
lypinator	0:bb348c97df44	719	__IOM uint32_t DATA_LOCK_3_WAY; /!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way /
lypinator	0:bb348c97df44	720	__IOM uint32_t INST_LOCK_3_WAY; /!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way /
lypinator	0:bb348c97df44	721	__IOM uint32_t DATA_LOCK_4_WAY; /!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way /
lypinator	0:bb348c97df44	722	__IOM uint32_t INST_LOCK_4_WAY; /!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way /
lypinator	0:bb348c97df44	723	__IOM uint32_t DATA_LOCK_5_WAY; /!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way /
lypinator	0:bb348c97df44	724	__IOM uint32_t INST_LOCK_5_WAY; /!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way /
lypinator	0:bb348c97df44	725	__IOM uint32_t DATA_LOCK_6_WAY; /!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way /
lypinator	0:bb348c97df44	726	__IOM uint32_t INST_LOCK_6_WAY; /!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way /
lypinator	0:bb348c97df44	727	__IOM uint32_t DATA_LOCK_7_WAY; /!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way /
lypinator	0:bb348c97df44	728	__IOM uint32_t INST_LOCK_7_WAY; /!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way /
lypinator	0:bb348c97df44	729	RESERVED(11[0x4], uint32_t)
lypinator	0:bb348c97df44	730	__IOM uint32_t LOCK_LINE_EN; /!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable /
lypinator	0:bb348c97df44	731	__IOM uint32_t UNLOCK_ALL_BY_WAY; /!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way /
lypinator	0:bb348c97df44	732	RESERVED(12[0xaa], uint32_t)
lypinator	0:bb348c97df44	733	__IOM uint32_t ADDRESS_FILTER_START; /!< \brief Offset: 0x0c00 (R/W) Address Filtering Start /
lypinator	0:bb348c97df44	734	__IOM uint32_t ADDRESS_FILTER_END; /!< \brief Offset: 0x0c04 (R/W) Address Filtering End /
lypinator	0:bb348c97df44	735	RESERVED(13[0xce], uint32_t)
lypinator	0:bb348c97df44	736	__IOM uint32_t DEBUG_CONTROL; /!< \brief Offset: 0x0f40 (R/W) Debug Control Register /
lypinator	0:bb348c97df44	737	} L2C_310_TypeDef;
lypinator	0:bb348c97df44	738
lypinator	0:bb348c97df44	739	#define L2C_310 ((L2C_310_TypeDef )L2C_310_BASE) /!< \brief L2C_310 register set access pointer */
lypinator	0:bb348c97df44	740	#endif
lypinator	0:bb348c97df44	741
lypinator	0:bb348c97df44	742	#if (__GIC_PRESENT == 1U) \|\| defined(DOXYGEN)
lypinator	0:bb348c97df44	743
lypinator	0:bb348c97df44	744	/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
lypinator	0:bb348c97df44	745	*/
lypinator	0:bb348c97df44	746	typedef struct
lypinator	0:bb348c97df44	747	{
lypinator	0:bb348c97df44	748	__IOM uint32_t CTLR; /!< \brief Offset: 0x000 (R/W) Distributor Control Register /
lypinator	0:bb348c97df44	749	__IM uint32_t TYPER; /!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register /
lypinator	0:bb348c97df44	750	__IM uint32_t IIDR; /!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register /
lypinator	0:bb348c97df44	751	RESERVED(0, uint32_t)
lypinator	0:bb348c97df44	752	__IOM uint32_t STATUSR; /!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional /
lypinator	0:bb348c97df44	753	RESERVED(1[11], uint32_t)
lypinator	0:bb348c97df44	754	__OM uint32_t SETSPI_NSR; /!< \brief Offset: 0x040 ( /W) Set SPI Register /
lypinator	0:bb348c97df44	755	RESERVED(2, uint32_t)
lypinator	0:bb348c97df44	756	__OM uint32_t CLRSPI_NSR; /!< \brief Offset: 0x048 ( /W) Clear SPI Register /
lypinator	0:bb348c97df44	757	RESERVED(3, uint32_t)
lypinator	0:bb348c97df44	758	__OM uint32_t SETSPI_SR; /!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register /
lypinator	0:bb348c97df44	759	RESERVED(4, uint32_t)
lypinator	0:bb348c97df44	760	__OM uint32_t CLRSPI_SR; /!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register /
lypinator	0:bb348c97df44	761	RESERVED(5[9], uint32_t)
lypinator	0:bb348c97df44	762	__IOM uint32_t IGROUPR[32]; /!< \brief Offset: 0x080 (R/W) Interrupt Group Registers /
lypinator	0:bb348c97df44	763	__IOM uint32_t ISENABLER[32]; /!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers /
lypinator	0:bb348c97df44	764	__IOM uint32_t ICENABLER[32]; /!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers /
lypinator	0:bb348c97df44	765	__IOM uint32_t ISPENDR[32]; /!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers /
lypinator	0:bb348c97df44	766	__IOM uint32_t ICPENDR[32]; /!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers /
lypinator	0:bb348c97df44	767	__IOM uint32_t ISACTIVER[32]; /!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers /
lypinator	0:bb348c97df44	768	__IOM uint32_t ICACTIVER[32]; /!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers /
lypinator	0:bb348c97df44	769	__IOM uint32_t IPRIORITYR[255]; /!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers /
lypinator	0:bb348c97df44	770	RESERVED(6, uint32_t)
lypinator	0:bb348c97df44	771	__IOM uint32_t ITARGETSR[255]; /!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers /
lypinator	0:bb348c97df44	772	RESERVED(7, uint32_t)
lypinator	0:bb348c97df44	773	__IOM uint32_t ICFGR[64]; /!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers /
lypinator	0:bb348c97df44	774	__IOM uint32_t IGRPMODR[32]; /!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers /
lypinator	0:bb348c97df44	775	RESERVED(8[32], uint32_t)
lypinator	0:bb348c97df44	776	__IOM uint32_t NSACR[64]; /!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers /
lypinator	0:bb348c97df44	777	__OM uint32_t SGIR; /!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register /
lypinator	0:bb348c97df44	778	RESERVED(9[3], uint32_t)
lypinator	0:bb348c97df44	779	__IOM uint32_t CPENDSGIR[4]; /!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers /
lypinator	0:bb348c97df44	780	__IOM uint32_t SPENDSGIR[4]; /!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers /
lypinator	0:bb348c97df44	781	RESERVED(10[5236], uint32_t)
lypinator	0:bb348c97df44	782	__IOM uint64_t IROUTER[988]; /!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers /
lypinator	0:bb348c97df44	783	} GICDistributor_Type;
lypinator	0:bb348c97df44	784
lypinator	0:bb348c97df44	785	#define GICDistributor ((GICDistributor_Type ) GIC_DISTRIBUTOR_BASE ) /!< \brief GIC Distributor register set access pointer */
lypinator	0:bb348c97df44	786
lypinator	0:bb348c97df44	787	/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC)
lypinator	0:bb348c97df44	788	*/
lypinator	0:bb348c97df44	789	typedef struct
lypinator	0:bb348c97df44	790	{
lypinator	0:bb348c97df44	791	__IOM uint32_t CTLR; /!< \brief Offset: 0x000 (R/W) CPU Interface Control Register /
lypinator	0:bb348c97df44	792	__IOM uint32_t PMR; /!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register /
lypinator	0:bb348c97df44	793	__IOM uint32_t BPR; /!< \brief Offset: 0x008 (R/W) Binary Point Register /
lypinator	0:bb348c97df44	794	__IM uint32_t IAR; /!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register /
lypinator	0:bb348c97df44	795	__OM uint32_t EOIR; /!< \brief Offset: 0x010 ( /W) End Of Interrupt Register /
lypinator	0:bb348c97df44	796	__IM uint32_t RPR; /!< \brief Offset: 0x014 (R/ ) Running Priority Register /
lypinator	0:bb348c97df44	797	__IM uint32_t HPPIR; /!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register /
lypinator	0:bb348c97df44	798	__IOM uint32_t ABPR; /!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register /
lypinator	0:bb348c97df44	799	__IM uint32_t AIAR; /!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register /
lypinator	0:bb348c97df44	800	__OM uint32_t AEOIR; /!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register /
lypinator	0:bb348c97df44	801	__IM uint32_t AHPPIR; /!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register /
lypinator	0:bb348c97df44	802	__IOM uint32_t STATUSR; /!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional /
lypinator	0:bb348c97df44	803	RESERVED(1[40], uint32_t)
lypinator	0:bb348c97df44	804	__IOM uint32_t APR[4]; /!< \brief Offset: 0x0D0 (R/W) Active Priority Register /
lypinator	0:bb348c97df44	805	__IOM uint32_t NSAPR[4]; /!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register /
lypinator	0:bb348c97df44	806	RESERVED(2[3], uint32_t)
lypinator	0:bb348c97df44	807	__IM uint32_t IIDR; /!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register /
lypinator	0:bb348c97df44	808	RESERVED(3[960], uint32_t)
lypinator	0:bb348c97df44	809	__OM uint32_t DIR; /!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register /
lypinator	0:bb348c97df44	810	} GICInterface_Type;
lypinator	0:bb348c97df44	811
lypinator	0:bb348c97df44	812	#define GICInterface ((GICInterface_Type ) GIC_INTERFACE_BASE ) /!< \brief GIC Interface register set access pointer */
lypinator	0:bb348c97df44	813	#endif
lypinator	0:bb348c97df44	814
lypinator	0:bb348c97df44	815	#if (__TIM_PRESENT == 1U) \|\| defined(DOXYGEN)
lypinator	0:bb348c97df44	816	#if ((__CORTEX_A == 5U) \|\| (__CORTEX_A == 9U)) \|\| defined(DOXYGEN)
lypinator	0:bb348c97df44	817	/** \brief Structure type to access the Private Timer
lypinator	0:bb348c97df44	818	*/
lypinator	0:bb348c97df44	819	typedef struct
lypinator	0:bb348c97df44	820	{
lypinator	0:bb348c97df44	821	__IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register
lypinator	0:bb348c97df44	822	__IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register
lypinator	0:bb348c97df44	823	__IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register
lypinator	0:bb348c97df44	824	__IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register
lypinator	0:bb348c97df44	825	RESERVED(0[4], uint32_t)
lypinator	0:bb348c97df44	826	__IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register
lypinator	0:bb348c97df44	827	__IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register
lypinator	0:bb348c97df44	828	__IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register
lypinator	0:bb348c97df44	829	__IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register
lypinator	0:bb348c97df44	830	__IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register
lypinator	0:bb348c97df44	831	__OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register
lypinator	0:bb348c97df44	832	} Timer_Type;
lypinator	0:bb348c97df44	833	#define PTIM ((Timer_Type ) TIMER_BASE ) /!< \brief Timer register struct */
lypinator	0:bb348c97df44	834	#endif
lypinator	0:bb348c97df44	835	#endif
lypinator	0:bb348c97df44	836
lypinator	0:bb348c97df44	837	/*******************************************************************************
lypinator	0:bb348c97df44	838	* Hardware Abstraction Layer
lypinator	0:bb348c97df44	839	Core Function Interface contains:
lypinator	0:bb348c97df44	840	- L1 Cache Functions
lypinator	0:bb348c97df44	841	- L2C-310 Cache Controller Functions
lypinator	0:bb348c97df44	842	- PL1 Timer Functions
lypinator	0:bb348c97df44	843	- GIC Functions
lypinator	0:bb348c97df44	844	- MMU Functions
lypinator	0:bb348c97df44	845	******************************************************************************/
lypinator	0:bb348c97df44	846
lypinator	0:bb348c97df44	847	/* ########################## L1 Cache functions ################################# */
lypinator	0:bb348c97df44	848
lypinator	0:bb348c97df44	849	/** \brief Enable Caches by setting I and C bits in SCTLR register.
lypinator	0:bb348c97df44	850	*/
lypinator	0:bb348c97df44	851	__STATIC_FORCEINLINE void L1C_EnableCaches(void) {
lypinator	0:bb348c97df44	852	__set_SCTLR( __get_SCTLR() \| SCTLR_I_Msk \| SCTLR_C_Msk);
lypinator	0:bb348c97df44	853	__ISB();
lypinator	0:bb348c97df44	854	}
lypinator	0:bb348c97df44	855
lypinator	0:bb348c97df44	856	/** \brief Disable Caches by clearing I and C bits in SCTLR register.
lypinator	0:bb348c97df44	857	*/
lypinator	0:bb348c97df44	858	__STATIC_FORCEINLINE void L1C_DisableCaches(void) {
lypinator	0:bb348c97df44	859	__set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk));
lypinator	0:bb348c97df44	860	__ISB();
lypinator	0:bb348c97df44	861	}
lypinator	0:bb348c97df44	862
lypinator	0:bb348c97df44	863	/** \brief Enable Branch Prediction by setting Z bit in SCTLR register.
lypinator	0:bb348c97df44	864	*/
lypinator	0:bb348c97df44	865	__STATIC_FORCEINLINE void L1C_EnableBTAC(void) {
lypinator	0:bb348c97df44	866	__set_SCTLR( __get_SCTLR() \| SCTLR_Z_Msk);
lypinator	0:bb348c97df44	867	__ISB();
lypinator	0:bb348c97df44	868	}
lypinator	0:bb348c97df44	869
lypinator	0:bb348c97df44	870	/** \brief Disable Branch Prediction by clearing Z bit in SCTLR register.
lypinator	0:bb348c97df44	871	*/
lypinator	0:bb348c97df44	872	__STATIC_FORCEINLINE void L1C_DisableBTAC(void) {
lypinator	0:bb348c97df44	873	__set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk));
lypinator	0:bb348c97df44	874	__ISB();
lypinator	0:bb348c97df44	875	}
lypinator	0:bb348c97df44	876
lypinator	0:bb348c97df44	877	/** \brief Invalidate entire branch predictor array
lypinator	0:bb348c97df44	878	*/
lypinator	0:bb348c97df44	879	__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) {
lypinator	0:bb348c97df44	880	__set_BPIALL(0);
lypinator	0:bb348c97df44	881	__DSB(); //ensure completion of the invalidation
lypinator	0:bb348c97df44	882	__ISB(); //ensure instruction fetch path sees new state
lypinator	0:bb348c97df44	883	}
lypinator	0:bb348c97df44	884
lypinator	0:bb348c97df44	885	/** \brief Invalidate the whole instruction cache
lypinator	0:bb348c97df44	886	*/
lypinator	0:bb348c97df44	887	__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) {
lypinator	0:bb348c97df44	888	__set_ICIALLU(0);
lypinator	0:bb348c97df44	889	__DSB(); //ensure completion of the invalidation
lypinator	0:bb348c97df44	890	__ISB(); //ensure instruction fetch path sees new I cache state
lypinator	0:bb348c97df44	891	}
lypinator	0:bb348c97df44	892
lypinator	0:bb348c97df44	893	/** \brief Clean data cache line by address.
lypinator	0:bb348c97df44	894	* \param [in] va Pointer to data to clear the cache for.
lypinator	0:bb348c97df44	895	*/
lypinator	0:bb348c97df44	896	__STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) {
lypinator	0:bb348c97df44	897	__set_DCCMVAC((uint32_t)va);
lypinator	0:bb348c97df44	898	__DMB(); //ensure the ordering of data cache maintenance operations and their effects
lypinator	0:bb348c97df44	899	}
lypinator	0:bb348c97df44	900
lypinator	0:bb348c97df44	901	/** \brief Invalidate data cache line by address.
lypinator	0:bb348c97df44	902	* \param [in] va Pointer to data to invalidate the cache for.
lypinator	0:bb348c97df44	903	*/
lypinator	0:bb348c97df44	904	__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) {
lypinator	0:bb348c97df44	905	__set_DCIMVAC((uint32_t)va);
lypinator	0:bb348c97df44	906	__DMB(); //ensure the ordering of data cache maintenance operations and their effects
lypinator	0:bb348c97df44	907	}
lypinator	0:bb348c97df44	908
lypinator	0:bb348c97df44	909	/** \brief Clean and Invalidate data cache by address.
lypinator	0:bb348c97df44	910	* \param [in] va Pointer to data to invalidate the cache for.
lypinator	0:bb348c97df44	911	*/
lypinator	0:bb348c97df44	912	__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
lypinator	0:bb348c97df44	913	__set_DCCIMVAC((uint32_t)va);
lypinator	0:bb348c97df44	914	__DMB(); //ensure the ordering of data cache maintenance operations and their effects
lypinator	0:bb348c97df44	915	}
lypinator	0:bb348c97df44	916
lypinator	0:bb348c97df44	917	/** \brief Calculate log2 rounded up
lypinator	0:bb348c97df44	918	* - log(0) => 0
lypinator	0:bb348c97df44	919	* - log(1) => 0
lypinator	0:bb348c97df44	920	* - log(2) => 1
lypinator	0:bb348c97df44	921	* - log(3) => 2
lypinator	0:bb348c97df44	922	* - log(4) => 2
lypinator	0:bb348c97df44	923	* - log(5) => 3
lypinator	0:bb348c97df44	924	* : :
lypinator	0:bb348c97df44	925	* - log(16) => 4
lypinator	0:bb348c97df44	926	* - log(32) => 5
lypinator	0:bb348c97df44	927	* : :
lypinator	0:bb348c97df44	928	* \param [in] n input value parameter
lypinator	0:bb348c97df44	929	* \return log2(n)
lypinator	0:bb348c97df44	930	*/
lypinator	0:bb348c97df44	931	__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n)
lypinator	0:bb348c97df44	932	{
lypinator	0:bb348c97df44	933	if (n < 2U) {
lypinator	0:bb348c97df44	934	return 0U;
lypinator	0:bb348c97df44	935	}
lypinator	0:bb348c97df44	936	uint8_t log = 0U;
lypinator	0:bb348c97df44	937	uint32_t t = n;
lypinator	0:bb348c97df44	938	while(t > 1U)
lypinator	0:bb348c97df44	939	{
lypinator	0:bb348c97df44	940	log++;
lypinator	0:bb348c97df44	941	t >>= 1U;
lypinator	0:bb348c97df44	942	}
lypinator	0:bb348c97df44	943	if (n & 1U) { log++; }
lypinator	0:bb348c97df44	944	return log;
lypinator	0:bb348c97df44	945	}
lypinator	0:bb348c97df44	946
lypinator	0:bb348c97df44	947	/** \brief Apply cache maintenance to given cache level.
lypinator	0:bb348c97df44	948	* \param [in] level cache level to be maintained
lypinator	0:bb348c97df44	949	* \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean
lypinator	0:bb348c97df44	950	*/
lypinator	0:bb348c97df44	951	__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint)
lypinator	0:bb348c97df44	952	{
lypinator	0:bb348c97df44	953	uint32_t Dummy;
lypinator	0:bb348c97df44	954	uint32_t ccsidr;
lypinator	0:bb348c97df44	955	uint32_t num_sets;
lypinator	0:bb348c97df44	956	uint32_t num_ways;
lypinator	0:bb348c97df44	957	uint32_t shift_way;
lypinator	0:bb348c97df44	958	uint32_t log2_linesize;
lypinator	0:bb348c97df44	959	int32_t log2_num_ways;
lypinator	0:bb348c97df44	960
lypinator	0:bb348c97df44	961	Dummy = level << 1U;
lypinator	0:bb348c97df44	962	/* set csselr, select ccsidr register */
lypinator	0:bb348c97df44	963	__set_CSSELR(Dummy);
lypinator	0:bb348c97df44	964	/* get current ccsidr register */
lypinator	0:bb348c97df44	965	ccsidr = __get_CCSIDR();
lypinator	0:bb348c97df44	966	num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U;
lypinator	0:bb348c97df44	967	num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U;
lypinator	0:bb348c97df44	968	log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U;
lypinator	0:bb348c97df44	969	log2_num_ways = __log2_up(num_ways);
lypinator	0:bb348c97df44	970	if ((log2_num_ways < 0) \|\| (log2_num_ways > 32)) {
lypinator	0:bb348c97df44	971	return; // FATAL ERROR
lypinator	0:bb348c97df44	972	}
lypinator	0:bb348c97df44	973	shift_way = 32U - (uint32_t)log2_num_ways;
lypinator	0:bb348c97df44	974	for(int32_t way = num_ways-1; way >= 0; way--)
lypinator	0:bb348c97df44	975	{
lypinator	0:bb348c97df44	976	for(int32_t set = num_sets-1; set >= 0; set--)
lypinator	0:bb348c97df44	977	{
lypinator	0:bb348c97df44	978	Dummy = (level << 1U) \| (((uint32_t)set) << log2_linesize) \| (((uint32_t)way) << shift_way);
lypinator	0:bb348c97df44	979	switch (maint)
lypinator	0:bb348c97df44	980	{
lypinator	0:bb348c97df44	981	case 0U: __set_DCISW(Dummy); break;
lypinator	0:bb348c97df44	982	case 1U: __set_DCCSW(Dummy); break;
lypinator	0:bb348c97df44	983	default: __set_DCCISW(Dummy); break;
lypinator	0:bb348c97df44	984	}
lypinator	0:bb348c97df44	985	}
lypinator	0:bb348c97df44	986	}
lypinator	0:bb348c97df44	987	__DMB();
lypinator	0:bb348c97df44	988	}
lypinator	0:bb348c97df44	989
lypinator	0:bb348c97df44	990	/** \brief Clean and Invalidate the entire data or unified cache
lypinator	0:bb348c97df44	991	* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
lypinator	0:bb348c97df44	992	* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
lypinator	0:bb348c97df44	993	*/
lypinator	0:bb348c97df44	994	__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) {
lypinator	0:bb348c97df44	995	uint32_t clidr;
lypinator	0:bb348c97df44	996	uint32_t cache_type;
lypinator	0:bb348c97df44	997	clidr = __get_CLIDR();
lypinator	0:bb348c97df44	998	for(uint32_t i = 0U; i<7U; i++)
lypinator	0:bb348c97df44	999	{
lypinator	0:bb348c97df44	1000	cache_type = (clidr >> i*3U) & 0x7UL;
lypinator	0:bb348c97df44	1001	if ((cache_type >= 2U) && (cache_type <= 4U))
lypinator	0:bb348c97df44	1002	{
lypinator	0:bb348c97df44	1003	__L1C_MaintainDCacheSetWay(i, op);
lypinator	0:bb348c97df44	1004	}
lypinator	0:bb348c97df44	1005	}
lypinator	0:bb348c97df44	1006	}
lypinator	0:bb348c97df44	1007
lypinator	0:bb348c97df44	1008	/** \brief Clean and Invalidate the entire data or unified cache
lypinator	0:bb348c97df44	1009	* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
lypinator	0:bb348c97df44	1010	* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
lypinator	0:bb348c97df44	1011	* \deprecated Use generic L1C_CleanInvalidateCache instead.
lypinator	0:bb348c97df44	1012	*/
lypinator	0:bb348c97df44	1013	CMSIS_DEPRECATED
lypinator	0:bb348c97df44	1014	__STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) {
lypinator	0:bb348c97df44	1015	L1C_CleanInvalidateCache(op);
lypinator	0:bb348c97df44	1016	}
lypinator	0:bb348c97df44	1017
lypinator	0:bb348c97df44	1018	/** \brief Invalidate the whole data cache.
lypinator	0:bb348c97df44	1019	*/
lypinator	0:bb348c97df44	1020	__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) {
lypinator	0:bb348c97df44	1021	L1C_CleanInvalidateCache(0);
lypinator	0:bb348c97df44	1022	}
lypinator	0:bb348c97df44	1023
lypinator	0:bb348c97df44	1024	/** \brief Clean the whole data cache.
lypinator	0:bb348c97df44	1025	*/
lypinator	0:bb348c97df44	1026	__STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) {
lypinator	0:bb348c97df44	1027	L1C_CleanInvalidateCache(1);
lypinator	0:bb348c97df44	1028	}
lypinator	0:bb348c97df44	1029
lypinator	0:bb348c97df44	1030	/** \brief Clean and invalidate the whole data cache.
lypinator	0:bb348c97df44	1031	*/
lypinator	0:bb348c97df44	1032	__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) {
lypinator	0:bb348c97df44	1033	L1C_CleanInvalidateCache(2);
lypinator	0:bb348c97df44	1034	}
lypinator	0:bb348c97df44	1035
lypinator	0:bb348c97df44	1036	/* ########################## L2 Cache functions ################################# */
lypinator	0:bb348c97df44	1037	#if (__L2C_PRESENT == 1U) \|\| defined(DOXYGEN)
lypinator	0:bb348c97df44	1038	/** \brief Cache Sync operation by writing CACHE_SYNC register.
lypinator	0:bb348c97df44	1039	*/
lypinator	0:bb348c97df44	1040	__STATIC_INLINE void L2C_Sync(void)
lypinator	0:bb348c97df44	1041	{
lypinator	0:bb348c97df44	1042	L2C_310->CACHE_SYNC = 0x0;
lypinator	0:bb348c97df44	1043	}
lypinator	0:bb348c97df44	1044
lypinator	0:bb348c97df44	1045	/** \brief Read cache controller cache ID from CACHE_ID register.
lypinator	0:bb348c97df44	1046	* \return L2C_310_TypeDef::CACHE_ID
lypinator	0:bb348c97df44	1047	*/
lypinator	0:bb348c97df44	1048	__STATIC_INLINE int L2C_GetID (void)
lypinator	0:bb348c97df44	1049	{
lypinator	0:bb348c97df44	1050	return L2C_310->CACHE_ID;
lypinator	0:bb348c97df44	1051	}
lypinator	0:bb348c97df44	1052
lypinator	0:bb348c97df44	1053	/** \brief Read cache controller cache type from CACHE_TYPE register.
lypinator	0:bb348c97df44	1054	* \return L2C_310_TypeDef::CACHE_TYPE
lypinator	0:bb348c97df44	1055	*/
lypinator	0:bb348c97df44	1056	__STATIC_INLINE int L2C_GetType (void)
lypinator	0:bb348c97df44	1057	{
lypinator	0:bb348c97df44	1058	return L2C_310->CACHE_TYPE;
lypinator	0:bb348c97df44	1059	}
lypinator	0:bb348c97df44	1060
lypinator	0:bb348c97df44	1061	/** \brief Invalidate all cache by way
lypinator	0:bb348c97df44	1062	*/
lypinator	0:bb348c97df44	1063	__STATIC_INLINE void L2C_InvAllByWay (void)
lypinator	0:bb348c97df44	1064	{
lypinator	0:bb348c97df44	1065	unsigned int assoc;
lypinator	0:bb348c97df44	1066
lypinator	0:bb348c97df44	1067	if (L2C_310->AUX_CNT & (1U << 16U)) {
lypinator	0:bb348c97df44	1068	assoc = 16U;
lypinator	0:bb348c97df44	1069	} else {
lypinator	0:bb348c97df44	1070	assoc = 8U;
lypinator	0:bb348c97df44	1071	}
lypinator	0:bb348c97df44	1072
lypinator	0:bb348c97df44	1073	L2C_310->INV_WAY = (1U << assoc) - 1U;
lypinator	0:bb348c97df44	1074	while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
lypinator	0:bb348c97df44	1075
lypinator	0:bb348c97df44	1076	L2C_Sync();
lypinator	0:bb348c97df44	1077	}
lypinator	0:bb348c97df44	1078
lypinator	0:bb348c97df44	1079	/** \brief Clean and Invalidate all cache by way
lypinator	0:bb348c97df44	1080	*/
lypinator	0:bb348c97df44	1081	__STATIC_INLINE void L2C_CleanInvAllByWay (void)
lypinator	0:bb348c97df44	1082	{
lypinator	0:bb348c97df44	1083	unsigned int assoc;
lypinator	0:bb348c97df44	1084
lypinator	0:bb348c97df44	1085	if (L2C_310->AUX_CNT & (1U << 16U)) {
lypinator	0:bb348c97df44	1086	assoc = 16U;
lypinator	0:bb348c97df44	1087	} else {
lypinator	0:bb348c97df44	1088	assoc = 8U;
lypinator	0:bb348c97df44	1089	}
lypinator	0:bb348c97df44	1090
lypinator	0:bb348c97df44	1091	L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U;
lypinator	0:bb348c97df44	1092	while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
lypinator	0:bb348c97df44	1093
lypinator	0:bb348c97df44	1094	L2C_Sync();
lypinator	0:bb348c97df44	1095	}
lypinator	0:bb348c97df44	1096
lypinator	0:bb348c97df44	1097	/** \brief Enable Level 2 Cache
lypinator	0:bb348c97df44	1098	*/
lypinator	0:bb348c97df44	1099	__STATIC_INLINE void L2C_Enable(void)
lypinator	0:bb348c97df44	1100	{
lypinator	0:bb348c97df44	1101	L2C_310->CONTROL = 0;
lypinator	0:bb348c97df44	1102	L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
lypinator	0:bb348c97df44	1103	L2C_310->DEBUG_CONTROL = 0;
lypinator	0:bb348c97df44	1104	L2C_310->DATA_LOCK_0_WAY = 0;
lypinator	0:bb348c97df44	1105	L2C_310->CACHE_SYNC = 0;
lypinator	0:bb348c97df44	1106	L2C_310->CONTROL = 0x01;
lypinator	0:bb348c97df44	1107	L2C_Sync();
lypinator	0:bb348c97df44	1108	}
lypinator	0:bb348c97df44	1109
lypinator	0:bb348c97df44	1110	/** \brief Disable Level 2 Cache
lypinator	0:bb348c97df44	1111	*/
lypinator	0:bb348c97df44	1112	__STATIC_INLINE void L2C_Disable(void)
lypinator	0:bb348c97df44	1113	{
lypinator	0:bb348c97df44	1114	L2C_310->CONTROL = 0x00;
lypinator	0:bb348c97df44	1115	L2C_Sync();
lypinator	0:bb348c97df44	1116	}
lypinator	0:bb348c97df44	1117
lypinator	0:bb348c97df44	1118	/** \brief Invalidate cache by physical address
lypinator	0:bb348c97df44	1119	* \param [in] pa Pointer to data to invalidate cache for.
lypinator	0:bb348c97df44	1120	*/
lypinator	0:bb348c97df44	1121	__STATIC_INLINE void L2C_InvPa (void *pa)
lypinator	0:bb348c97df44	1122	{
lypinator	0:bb348c97df44	1123	L2C_310->INV_LINE_PA = (unsigned int)pa;
lypinator	0:bb348c97df44	1124	L2C_Sync();
lypinator	0:bb348c97df44	1125	}
lypinator	0:bb348c97df44	1126
lypinator	0:bb348c97df44	1127	/** \brief Clean cache by physical address
lypinator	0:bb348c97df44	1128	* \param [in] pa Pointer to data to invalidate cache for.
lypinator	0:bb348c97df44	1129	*/
lypinator	0:bb348c97df44	1130	__STATIC_INLINE void L2C_CleanPa (void *pa)
lypinator	0:bb348c97df44	1131	{
lypinator	0:bb348c97df44	1132	L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
lypinator	0:bb348c97df44	1133	L2C_Sync();
lypinator	0:bb348c97df44	1134	}
lypinator	0:bb348c97df44	1135
lypinator	0:bb348c97df44	1136	/** \brief Clean and invalidate cache by physical address
lypinator	0:bb348c97df44	1137	* \param [in] pa Pointer to data to invalidate cache for.
lypinator	0:bb348c97df44	1138	*/
lypinator	0:bb348c97df44	1139	__STATIC_INLINE void L2C_CleanInvPa (void *pa)
lypinator	0:bb348c97df44	1140	{
lypinator	0:bb348c97df44	1141	L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
lypinator	0:bb348c97df44	1142	L2C_Sync();
lypinator	0:bb348c97df44	1143	}
lypinator	0:bb348c97df44	1144	#endif
lypinator	0:bb348c97df44	1145
lypinator	0:bb348c97df44	1146	/* ########################## GIC functions ###################################### */
lypinator	0:bb348c97df44	1147	#if (__GIC_PRESENT == 1U) \|\| defined(DOXYGEN)
lypinator	0:bb348c97df44	1148
lypinator	0:bb348c97df44	1149	/** \brief Enable the interrupt distributor using the GIC's CTLR register.
lypinator	0:bb348c97df44	1150	*/
lypinator	0:bb348c97df44	1151	__STATIC_INLINE void GIC_EnableDistributor(void)
lypinator	0:bb348c97df44	1152	{
lypinator	0:bb348c97df44	1153	GICDistributor->CTLR \|= 1U;
lypinator	0:bb348c97df44	1154	}
lypinator	0:bb348c97df44	1155
lypinator	0:bb348c97df44	1156	/** \brief Disable the interrupt distributor using the GIC's CTLR register.
lypinator	0:bb348c97df44	1157	*/
lypinator	0:bb348c97df44	1158	__STATIC_INLINE void GIC_DisableDistributor(void)
lypinator	0:bb348c97df44	1159	{
lypinator	0:bb348c97df44	1160	GICDistributor->CTLR &=~1U;
lypinator	0:bb348c97df44	1161	}
lypinator	0:bb348c97df44	1162
lypinator	0:bb348c97df44	1163	/** \brief Read the GIC's TYPER register.
lypinator	0:bb348c97df44	1164	* \return GICDistributor_Type::TYPER
lypinator	0:bb348c97df44	1165	*/
lypinator	0:bb348c97df44	1166	__STATIC_INLINE uint32_t GIC_DistributorInfo(void)
lypinator	0:bb348c97df44	1167	{
lypinator	0:bb348c97df44	1168	return (GICDistributor->TYPER);
lypinator	0:bb348c97df44	1169	}
lypinator	0:bb348c97df44	1170
lypinator	0:bb348c97df44	1171	/** \brief Reads the GIC's IIDR register.
lypinator	0:bb348c97df44	1172	* \return GICDistributor_Type::IIDR
lypinator	0:bb348c97df44	1173	*/
lypinator	0:bb348c97df44	1174	__STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
lypinator	0:bb348c97df44	1175	{
lypinator	0:bb348c97df44	1176	return (GICDistributor->IIDR);
lypinator	0:bb348c97df44	1177	}
lypinator	0:bb348c97df44	1178
lypinator	0:bb348c97df44	1179	/** \brief Sets the GIC's ITARGETSR register for the given interrupt.
lypinator	0:bb348c97df44	1180	* \param [in] IRQn Interrupt to be configured.
lypinator	0:bb348c97df44	1181	* \param [in] cpu_target CPU interfaces to assign this interrupt to.
lypinator	0:bb348c97df44	1182	*/
lypinator	0:bb348c97df44	1183	__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
lypinator	0:bb348c97df44	1184	{
lypinator	0:bb348c97df44	1185	uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
lypinator	0:bb348c97df44	1186	GICDistributor->ITARGETSR[IRQn / 4U] = mask \| ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U));
lypinator	0:bb348c97df44	1187	}
lypinator	0:bb348c97df44	1188
lypinator	0:bb348c97df44	1189	/** \brief Read the GIC's ITARGETSR register.
lypinator	0:bb348c97df44	1190	* \param [in] IRQn Interrupt to acquire the configuration for.
lypinator	0:bb348c97df44	1191	* \return GICDistributor_Type::ITARGETSR
lypinator	0:bb348c97df44	1192	*/
lypinator	0:bb348c97df44	1193	__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1194	{
lypinator	0:bb348c97df44	1195	return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
lypinator	0:bb348c97df44	1196	}
lypinator	0:bb348c97df44	1197
lypinator	0:bb348c97df44	1198	/** \brief Enable the CPU's interrupt interface.
lypinator	0:bb348c97df44	1199	*/
lypinator	0:bb348c97df44	1200	__STATIC_INLINE void GIC_EnableInterface(void)
lypinator	0:bb348c97df44	1201	{
lypinator	0:bb348c97df44	1202	GICInterface->CTLR \|= 1U; //enable interface
lypinator	0:bb348c97df44	1203	}
lypinator	0:bb348c97df44	1204
lypinator	0:bb348c97df44	1205	/** \brief Disable the CPU's interrupt interface.
lypinator	0:bb348c97df44	1206	*/
lypinator	0:bb348c97df44	1207	__STATIC_INLINE void GIC_DisableInterface(void)
lypinator	0:bb348c97df44	1208	{
lypinator	0:bb348c97df44	1209	GICInterface->CTLR &=~1U; //disable distributor
lypinator	0:bb348c97df44	1210	}
lypinator	0:bb348c97df44	1211
lypinator	0:bb348c97df44	1212	/** \brief Read the CPU's IAR register.
lypinator	0:bb348c97df44	1213	* \return GICInterface_Type::IAR
lypinator	0:bb348c97df44	1214	*/
lypinator	0:bb348c97df44	1215	__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
lypinator	0:bb348c97df44	1216	{
lypinator	0:bb348c97df44	1217	return (IRQn_Type)(GICInterface->IAR);
lypinator	0:bb348c97df44	1218	}
lypinator	0:bb348c97df44	1219
lypinator	0:bb348c97df44	1220	/** \brief Writes the given interrupt number to the CPU's EOIR register.
lypinator	0:bb348c97df44	1221	* \param [in] IRQn The interrupt to be signaled as finished.
lypinator	0:bb348c97df44	1222	*/
lypinator	0:bb348c97df44	1223	__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1224	{
lypinator	0:bb348c97df44	1225	GICInterface->EOIR = IRQn;
lypinator	0:bb348c97df44	1226	}
lypinator	0:bb348c97df44	1227
lypinator	0:bb348c97df44	1228	/** \brief Enables the given interrupt using GIC's ISENABLER register.
lypinator	0:bb348c97df44	1229	* \param [in] IRQn The interrupt to be enabled.
lypinator	0:bb348c97df44	1230	*/
lypinator	0:bb348c97df44	1231	__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1232	{
lypinator	0:bb348c97df44	1233	GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
lypinator	0:bb348c97df44	1234	}
lypinator	0:bb348c97df44	1235
lypinator	0:bb348c97df44	1236	/** \brief Get interrupt enable status using GIC's ISENABLER register.
lypinator	0:bb348c97df44	1237	* \param [in] IRQn The interrupt to be queried.
lypinator	0:bb348c97df44	1238	* \return 0 - interrupt is not enabled, 1 - interrupt is enabled.
lypinator	0:bb348c97df44	1239	*/
lypinator	0:bb348c97df44	1240	__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1241	{
lypinator	0:bb348c97df44	1242	return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
lypinator	0:bb348c97df44	1243	}
lypinator	0:bb348c97df44	1244
lypinator	0:bb348c97df44	1245	/** \brief Disables the given interrupt using GIC's ICENABLER register.
lypinator	0:bb348c97df44	1246	* \param [in] IRQn The interrupt to be disabled.
lypinator	0:bb348c97df44	1247	*/
lypinator	0:bb348c97df44	1248	__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1249	{
lypinator	0:bb348c97df44	1250	GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
lypinator	0:bb348c97df44	1251	}
lypinator	0:bb348c97df44	1252
lypinator	0:bb348c97df44	1253	/** \brief Get interrupt pending status from GIC's ISPENDR register.
lypinator	0:bb348c97df44	1254	* \param [in] IRQn The interrupt to be queried.
lypinator	0:bb348c97df44	1255	* \return 0 - interrupt is not pending, 1 - interrupt is pendig.
lypinator	0:bb348c97df44	1256	*/
lypinator	0:bb348c97df44	1257	__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1258	{
lypinator	0:bb348c97df44	1259	uint32_t pend;
lypinator	0:bb348c97df44	1260
lypinator	0:bb348c97df44	1261	if (IRQn >= 16U) {
lypinator	0:bb348c97df44	1262	pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
lypinator	0:bb348c97df44	1263	} else {
lypinator	0:bb348c97df44	1264	// INTID 0-15 Software Generated Interrupt
lypinator	0:bb348c97df44	1265	pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
lypinator	0:bb348c97df44	1266	// No CPU identification offered
lypinator	0:bb348c97df44	1267	if (pend != 0U) {
lypinator	0:bb348c97df44	1268	pend = 1U;
lypinator	0:bb348c97df44	1269	} else {
lypinator	0:bb348c97df44	1270	pend = 0U;
lypinator	0:bb348c97df44	1271	}
lypinator	0:bb348c97df44	1272	}
lypinator	0:bb348c97df44	1273
lypinator	0:bb348c97df44	1274	return (pend);
lypinator	0:bb348c97df44	1275	}
lypinator	0:bb348c97df44	1276
lypinator	0:bb348c97df44	1277	/** \brief Sets the given interrupt as pending using GIC's ISPENDR register.
lypinator	0:bb348c97df44	1278	* \param [in] IRQn The interrupt to be enabled.
lypinator	0:bb348c97df44	1279	*/
lypinator	0:bb348c97df44	1280	__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1281	{
lypinator	0:bb348c97df44	1282	if (IRQn >= 16U) {
lypinator	0:bb348c97df44	1283	GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
lypinator	0:bb348c97df44	1284	} else {
lypinator	0:bb348c97df44	1285	// INTID 0-15 Software Generated Interrupt
lypinator	0:bb348c97df44	1286	GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
lypinator	0:bb348c97df44	1287	// Forward the interrupt to the CPU interface that requested it
lypinator	0:bb348c97df44	1288	GICDistributor->SGIR = (IRQn \| 0x02000000U);
lypinator	0:bb348c97df44	1289	}
lypinator	0:bb348c97df44	1290	}
lypinator	0:bb348c97df44	1291
lypinator	0:bb348c97df44	1292	/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register.
lypinator	0:bb348c97df44	1293	* \param [in] IRQn The interrupt to be enabled.
lypinator	0:bb348c97df44	1294	*/
lypinator	0:bb348c97df44	1295	__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1296	{
lypinator	0:bb348c97df44	1297	if (IRQn >= 16U) {
lypinator	0:bb348c97df44	1298	GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
lypinator	0:bb348c97df44	1299	} else {
lypinator	0:bb348c97df44	1300	// INTID 0-15 Software Generated Interrupt
lypinator	0:bb348c97df44	1301	GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
lypinator	0:bb348c97df44	1302	}
lypinator	0:bb348c97df44	1303	}
lypinator	0:bb348c97df44	1304
lypinator	0:bb348c97df44	1305	/** \brief Sets the interrupt configuration using GIC's ICFGR register.
lypinator	0:bb348c97df44	1306	* \param [in] IRQn The interrupt to be configured.
lypinator	0:bb348c97df44	1307	* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
lypinator	0:bb348c97df44	1308	* Bit 1: 0 - level sensitive, 1 - edge triggered
lypinator	0:bb348c97df44	1309	*/
lypinator	0:bb348c97df44	1310	__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config)
lypinator	0:bb348c97df44	1311	{
lypinator	0:bb348c97df44	1312	uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U];
lypinator	0:bb348c97df44	1313	uint32_t shift = (IRQn % 16U) << 1U;
lypinator	0:bb348c97df44	1314
lypinator	0:bb348c97df44	1315	icfgr &= (~(3U << shift));
lypinator	0:bb348c97df44	1316	icfgr \|= ( int_config << shift);
lypinator	0:bb348c97df44	1317
lypinator	0:bb348c97df44	1318	GICDistributor->ICFGR[IRQn / 16U] = icfgr;
lypinator	0:bb348c97df44	1319	}
lypinator	0:bb348c97df44	1320
lypinator	0:bb348c97df44	1321	/** \brief Get the interrupt configuration from the GIC's ICFGR register.
lypinator	0:bb348c97df44	1322	* \param [in] IRQn Interrupt to acquire the configuration for.
lypinator	0:bb348c97df44	1323	* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
lypinator	0:bb348c97df44	1324	* Bit 1: 0 - level sensitive, 1 - edge triggered
lypinator	0:bb348c97df44	1325	*/
lypinator	0:bb348c97df44	1326	__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1327	{
lypinator	0:bb348c97df44	1328	return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U));
lypinator	0:bb348c97df44	1329	}
lypinator	0:bb348c97df44	1330
lypinator	0:bb348c97df44	1331	/** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register.
lypinator	0:bb348c97df44	1332	* \param [in] IRQn The interrupt to be configured.
lypinator	0:bb348c97df44	1333	* \param [in] priority The priority for the interrupt, lower values denote higher priorities.
lypinator	0:bb348c97df44	1334	*/
lypinator	0:bb348c97df44	1335	__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
lypinator	0:bb348c97df44	1336	{
lypinator	0:bb348c97df44	1337	uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
lypinator	0:bb348c97df44	1338	GICDistributor->IPRIORITYR[IRQn / 4U] = mask \| ((priority & 0xFFUL) << ((IRQn % 4U) * 8U));
lypinator	0:bb348c97df44	1339	}
lypinator	0:bb348c97df44	1340
lypinator	0:bb348c97df44	1341	/** \brief Read the current interrupt priority from GIC's IPRIORITYR register.
lypinator	0:bb348c97df44	1342	* \param [in] IRQn The interrupt to be queried.
lypinator	0:bb348c97df44	1343	*/
lypinator	0:bb348c97df44	1344	__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1345	{
lypinator	0:bb348c97df44	1346	return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
lypinator	0:bb348c97df44	1347	}
lypinator	0:bb348c97df44	1348
lypinator	0:bb348c97df44	1349	/** \brief Set the interrupt priority mask using CPU's PMR register.
lypinator	0:bb348c97df44	1350	* \param [in] priority Priority mask to be set.
lypinator	0:bb348c97df44	1351	*/
lypinator	0:bb348c97df44	1352	__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)
lypinator	0:bb348c97df44	1353	{
lypinator	0:bb348c97df44	1354	GICInterface->PMR = priority & 0xFFUL; //set priority mask
lypinator	0:bb348c97df44	1355	}
lypinator	0:bb348c97df44	1356
lypinator	0:bb348c97df44	1357	/** \brief Read the current interrupt priority mask from CPU's PMR register.
lypinator	0:bb348c97df44	1358	* \result GICInterface_Type::PMR
lypinator	0:bb348c97df44	1359	*/
lypinator	0:bb348c97df44	1360	__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)
lypinator	0:bb348c97df44	1361	{
lypinator	0:bb348c97df44	1362	return GICInterface->PMR;
lypinator	0:bb348c97df44	1363	}
lypinator	0:bb348c97df44	1364
lypinator	0:bb348c97df44	1365	/** \brief Configures the group priority and subpriority split point using CPU's BPR register.
lypinator	0:bb348c97df44	1366	* \param [in] binary_point Amount of bits used as subpriority.
lypinator	0:bb348c97df44	1367	*/
lypinator	0:bb348c97df44	1368	__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
lypinator	0:bb348c97df44	1369	{
lypinator	0:bb348c97df44	1370	GICInterface->BPR = binary_point & 7U; //set binary point
lypinator	0:bb348c97df44	1371	}
lypinator	0:bb348c97df44	1372
lypinator	0:bb348c97df44	1373	/** \brief Read the current group priority and subpriority split point from CPU's BPR register.
lypinator	0:bb348c97df44	1374	* \return GICInterface_Type::BPR
lypinator	0:bb348c97df44	1375	*/
lypinator	0:bb348c97df44	1376	__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)
lypinator	0:bb348c97df44	1377	{
lypinator	0:bb348c97df44	1378	return GICInterface->BPR;
lypinator	0:bb348c97df44	1379	}
lypinator	0:bb348c97df44	1380
lypinator	0:bb348c97df44	1381	/** \brief Get the status for a given interrupt.
lypinator	0:bb348c97df44	1382	* \param [in] IRQn The interrupt to get status for.
lypinator	0:bb348c97df44	1383	* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active
lypinator	0:bb348c97df44	1384	*/
lypinator	0:bb348c97df44	1385	__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1386	{
lypinator	0:bb348c97df44	1387	uint32_t pending, active;
lypinator	0:bb348c97df44	1388
lypinator	0:bb348c97df44	1389	active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
lypinator	0:bb348c97df44	1390	pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
lypinator	0:bb348c97df44	1391
lypinator	0:bb348c97df44	1392	return ((active<<1U) \| pending);
lypinator	0:bb348c97df44	1393	}
lypinator	0:bb348c97df44	1394
lypinator	0:bb348c97df44	1395	/** \brief Generate a software interrupt using GIC's SGIR register.
lypinator	0:bb348c97df44	1396	* \param [in] IRQn Software interrupt to be generated.
lypinator	0:bb348c97df44	1397	* \param [in] target_list List of CPUs the software interrupt should be forwarded to.
lypinator	0:bb348c97df44	1398	* \param [in] filter_list Filter to be applied to determine interrupt receivers.
lypinator	0:bb348c97df44	1399	*/
lypinator	0:bb348c97df44	1400	__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
lypinator	0:bb348c97df44	1401	{
lypinator	0:bb348c97df44	1402	GICDistributor->SGIR = ((filter_list & 3U) << 24U) \| ((target_list & 0xFFUL) << 16U) \| (IRQn & 0x0FUL);
lypinator	0:bb348c97df44	1403	}
lypinator	0:bb348c97df44	1404
lypinator	0:bb348c97df44	1405	/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.
lypinator	0:bb348c97df44	1406	* \return GICInterface_Type::HPPIR
lypinator	0:bb348c97df44	1407	*/
lypinator	0:bb348c97df44	1408	__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void)
lypinator	0:bb348c97df44	1409	{
lypinator	0:bb348c97df44	1410	return GICInterface->HPPIR;
lypinator	0:bb348c97df44	1411	}
lypinator	0:bb348c97df44	1412
lypinator	0:bb348c97df44	1413	/** \brief Provides information about the implementer and revision of the CPU interface.
lypinator	0:bb348c97df44	1414	* \return GICInterface_Type::IIDR
lypinator	0:bb348c97df44	1415	*/
lypinator	0:bb348c97df44	1416	__STATIC_INLINE uint32_t GIC_GetInterfaceId(void)
lypinator	0:bb348c97df44	1417	{
lypinator	0:bb348c97df44	1418	return GICInterface->IIDR;
lypinator	0:bb348c97df44	1419	}
lypinator	0:bb348c97df44	1420
lypinator	0:bb348c97df44	1421	/** \brief Set the interrupt group from the GIC's IGROUPR register.
lypinator	0:bb348c97df44	1422	* \param [in] IRQn The interrupt to be queried.
lypinator	0:bb348c97df44	1423	* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1
lypinator	0:bb348c97df44	1424	*/
lypinator	0:bb348c97df44	1425	__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group)
lypinator	0:bb348c97df44	1426	{
lypinator	0:bb348c97df44	1427	uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U];
lypinator	0:bb348c97df44	1428	uint32_t shift = (IRQn % 32U);
lypinator	0:bb348c97df44	1429
lypinator	0:bb348c97df44	1430	igroupr &= (~(1U << shift));
lypinator	0:bb348c97df44	1431	igroupr \|= ( (group & 1U) << shift);
lypinator	0:bb348c97df44	1432
lypinator	0:bb348c97df44	1433	GICDistributor->IGROUPR[IRQn / 32U] = igroupr;
lypinator	0:bb348c97df44	1434	}
lypinator	0:bb348c97df44	1435	#define GIC_SetSecurity GIC_SetGroup
lypinator	0:bb348c97df44	1436
lypinator	0:bb348c97df44	1437	/** \brief Get the interrupt group from the GIC's IGROUPR register.
lypinator	0:bb348c97df44	1438	* \param [in] IRQn The interrupt to be queried.
lypinator	0:bb348c97df44	1439	* \return 0 - Group 0, 1 - Group 1
lypinator	0:bb348c97df44	1440	*/
lypinator	0:bb348c97df44	1441	__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn)
lypinator	0:bb348c97df44	1442	{
lypinator	0:bb348c97df44	1443	return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
lypinator	0:bb348c97df44	1444	}
lypinator	0:bb348c97df44	1445	#define GIC_GetSecurity GIC_GetGroup
lypinator	0:bb348c97df44	1446
lypinator	0:bb348c97df44	1447	/** \brief Initialize the interrupt distributor.
lypinator	0:bb348c97df44	1448	*/
lypinator	0:bb348c97df44	1449	__STATIC_INLINE void GIC_DistInit(void)
lypinator	0:bb348c97df44	1450	{
lypinator	0:bb348c97df44	1451	uint32_t i;
lypinator	0:bb348c97df44	1452	uint32_t num_irq = 0U;
lypinator	0:bb348c97df44	1453	uint32_t priority_field;
lypinator	0:bb348c97df44	1454
lypinator	0:bb348c97df44	1455	//A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
lypinator	0:bb348c97df44	1456	//configuring all of the interrupts as Secure.
lypinator	0:bb348c97df44	1457
lypinator	0:bb348c97df44	1458	//Disable interrupt forwarding
lypinator	0:bb348c97df44	1459	GIC_DisableDistributor();
lypinator	0:bb348c97df44	1460	//Get the maximum number of interrupts that the GIC supports
lypinator	0:bb348c97df44	1461	num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U);
lypinator	0:bb348c97df44	1462
lypinator	0:bb348c97df44	1463	/* Priority level is implementation defined.
lypinator	0:bb348c97df44	1464	To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
lypinator	0:bb348c97df44	1465	priority field and read back the value stored.*/
lypinator	0:bb348c97df44	1466	GIC_SetPriority((IRQn_Type)0U, 0xFFU);
lypinator	0:bb348c97df44	1467	priority_field = GIC_GetPriority((IRQn_Type)0U);
lypinator	0:bb348c97df44	1468
lypinator	0:bb348c97df44	1469	for (i = 32U; i < num_irq; i++)
lypinator	0:bb348c97df44	1470	{
lypinator	0:bb348c97df44	1471	//Disable the SPI interrupt
lypinator	0:bb348c97df44	1472	GIC_DisableIRQ((IRQn_Type)i);
lypinator	0:bb348c97df44	1473	//Set level-sensitive (and N-N model)
lypinator	0:bb348c97df44	1474	GIC_SetConfiguration((IRQn_Type)i, 0U);
lypinator	0:bb348c97df44	1475	//Set priority
lypinator	0:bb348c97df44	1476	GIC_SetPriority((IRQn_Type)i, priority_field/2U);
lypinator	0:bb348c97df44	1477	//Set target list to CPU0
lypinator	0:bb348c97df44	1478	GIC_SetTarget((IRQn_Type)i, 1U);
lypinator	0:bb348c97df44	1479	}
lypinator	0:bb348c97df44	1480	//Enable distributor
lypinator	0:bb348c97df44	1481	GIC_EnableDistributor();
lypinator	0:bb348c97df44	1482	}
lypinator	0:bb348c97df44	1483
lypinator	0:bb348c97df44	1484	/** \brief Initialize the CPU's interrupt interface
lypinator	0:bb348c97df44	1485	*/
lypinator	0:bb348c97df44	1486	__STATIC_INLINE void GIC_CPUInterfaceInit(void)
lypinator	0:bb348c97df44	1487	{
lypinator	0:bb348c97df44	1488	uint32_t i;
lypinator	0:bb348c97df44	1489	uint32_t priority_field;
lypinator	0:bb348c97df44	1490
lypinator	0:bb348c97df44	1491	//A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
lypinator	0:bb348c97df44	1492	//configuring all of the interrupts as Secure.
lypinator	0:bb348c97df44	1493
lypinator	0:bb348c97df44	1494	//Disable interrupt forwarding
lypinator	0:bb348c97df44	1495	GIC_DisableInterface();
lypinator	0:bb348c97df44	1496
lypinator	0:bb348c97df44	1497	/* Priority level is implementation defined.
lypinator	0:bb348c97df44	1498	To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
lypinator	0:bb348c97df44	1499	priority field and read back the value stored.*/
lypinator	0:bb348c97df44	1500	GIC_SetPriority((IRQn_Type)0U, 0xFFU);
lypinator	0:bb348c97df44	1501	priority_field = GIC_GetPriority((IRQn_Type)0U);
lypinator	0:bb348c97df44	1502
lypinator	0:bb348c97df44	1503	//SGI and PPI
lypinator	0:bb348c97df44	1504	for (i = 0U; i < 32U; i++)
lypinator	0:bb348c97df44	1505	{
lypinator	0:bb348c97df44	1506	if(i > 15U) {
lypinator	0:bb348c97df44	1507	//Set level-sensitive (and N-N model) for PPI
lypinator	0:bb348c97df44	1508	GIC_SetConfiguration((IRQn_Type)i, 0U);
lypinator	0:bb348c97df44	1509	}
lypinator	0:bb348c97df44	1510	//Disable SGI and PPI interrupts
lypinator	0:bb348c97df44	1511	GIC_DisableIRQ((IRQn_Type)i);
lypinator	0:bb348c97df44	1512	//Set priority
lypinator	0:bb348c97df44	1513	GIC_SetPriority((IRQn_Type)i, priority_field/2U);
lypinator	0:bb348c97df44	1514	}
lypinator	0:bb348c97df44	1515	//Enable interface
lypinator	0:bb348c97df44	1516	GIC_EnableInterface();
lypinator	0:bb348c97df44	1517	//Set binary point to 0
lypinator	0:bb348c97df44	1518	GIC_SetBinaryPoint(0U);
lypinator	0:bb348c97df44	1519	//Set priority mask
lypinator	0:bb348c97df44	1520	GIC_SetInterfacePriorityMask(0xFFU);
lypinator	0:bb348c97df44	1521	}
lypinator	0:bb348c97df44	1522
lypinator	0:bb348c97df44	1523	/** \brief Initialize and enable the GIC
lypinator	0:bb348c97df44	1524	*/
lypinator	0:bb348c97df44	1525	__STATIC_INLINE void GIC_Enable(void)
lypinator	0:bb348c97df44	1526	{
lypinator	0:bb348c97df44	1527	GIC_DistInit();
lypinator	0:bb348c97df44	1528	GIC_CPUInterfaceInit(); //per CPU
lypinator	0:bb348c97df44	1529	}
lypinator	0:bb348c97df44	1530	#endif
lypinator	0:bb348c97df44	1531
lypinator	0:bb348c97df44	1532	/* ########################## Generic Timer functions ############################ */
lypinator	0:bb348c97df44	1533	#if (__TIM_PRESENT == 1U) \|\| defined(DOXYGEN)
lypinator	0:bb348c97df44	1534
lypinator	0:bb348c97df44	1535	/* PL1 Physical Timer */
lypinator	0:bb348c97df44	1536	#if (__CORTEX_A == 7U) \|\| defined(DOXYGEN)
lypinator	0:bb348c97df44	1537
lypinator	0:bb348c97df44	1538	/** \brief Physical Timer Control register */
lypinator	0:bb348c97df44	1539	typedef union
lypinator	0:bb348c97df44	1540	{
lypinator	0:bb348c97df44	1541	struct
lypinator	0:bb348c97df44	1542	{
lypinator	0:bb348c97df44	1543	uint32_t ENABLE:1; /!< \brief bit: 0 Enables the timer. /
lypinator	0:bb348c97df44	1544	uint32_t IMASK:1; /!< \brief bit: 1 Timer output signal mask bit. /
lypinator	0:bb348c97df44	1545	uint32_t ISTATUS:1; /!< \brief bit: 2 The status of the timer. /
lypinator	0:bb348c97df44	1546	RESERVED(0:29, uint32_t)
lypinator	0:bb348c97df44	1547	} b; /!< \brief Structure used for bit access /
lypinator	0:bb348c97df44	1548	uint32_t w; /!< \brief Type used for word access /
lypinator	0:bb348c97df44	1549	} CNTP_CTL_Type;
lypinator	0:bb348c97df44	1550
lypinator	0:bb348c97df44	1551	/** \brief Configures the frequency the timer shall run at.
lypinator	0:bb348c97df44	1552	* \param [in] value The timer frequency in Hz.
lypinator	0:bb348c97df44	1553	*/
lypinator	0:bb348c97df44	1554	__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value)
lypinator	0:bb348c97df44	1555	{
lypinator	0:bb348c97df44	1556	__set_CNTFRQ(value);
lypinator	0:bb348c97df44	1557	__ISB();
lypinator	0:bb348c97df44	1558	}
lypinator	0:bb348c97df44	1559
lypinator	0:bb348c97df44	1560	/** \brief Sets the reset value of the timer.
lypinator	0:bb348c97df44	1561	* \param [in] value The value the timer is loaded with.
lypinator	0:bb348c97df44	1562	*/
lypinator	0:bb348c97df44	1563	__STATIC_INLINE void PL1_SetLoadValue(uint32_t value)
lypinator	0:bb348c97df44	1564	{
lypinator	0:bb348c97df44	1565	__set_CNTP_TVAL(value);
lypinator	0:bb348c97df44	1566	__ISB();
lypinator	0:bb348c97df44	1567	}
lypinator	0:bb348c97df44	1568
lypinator	0:bb348c97df44	1569	/** \brief Get the current counter value.
lypinator	0:bb348c97df44	1570	* \return Current counter value.
lypinator	0:bb348c97df44	1571	*/
lypinator	0:bb348c97df44	1572	__STATIC_INLINE uint32_t PL1_GetCurrentValue(void)
lypinator	0:bb348c97df44	1573	{
lypinator	0:bb348c97df44	1574	return(__get_CNTP_TVAL());
lypinator	0:bb348c97df44	1575	}
lypinator	0:bb348c97df44	1576
lypinator	0:bb348c97df44	1577	/** \brief Get the current physical counter value.
lypinator	0:bb348c97df44	1578	* \return Current physical counter value.
lypinator	0:bb348c97df44	1579	*/
lypinator	0:bb348c97df44	1580	__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void)
lypinator	0:bb348c97df44	1581	{
lypinator	0:bb348c97df44	1582	return(__get_CNTPCT());
lypinator	0:bb348c97df44	1583	}
lypinator	0:bb348c97df44	1584
lypinator	0:bb348c97df44	1585	/** \brief Set the physical compare value.
lypinator	0:bb348c97df44	1586	* \param [in] value New physical timer compare value.
lypinator	0:bb348c97df44	1587	*/
lypinator	0:bb348c97df44	1588	__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value)
lypinator	0:bb348c97df44	1589	{
lypinator	0:bb348c97df44	1590	__set_CNTP_CVAL(value);
lypinator	0:bb348c97df44	1591	__ISB();
lypinator	0:bb348c97df44	1592	}
lypinator	0:bb348c97df44	1593
lypinator	0:bb348c97df44	1594	/** \brief Get the physical compare value.
lypinator	0:bb348c97df44	1595	* \return Physical compare value.
lypinator	0:bb348c97df44	1596	*/
lypinator	0:bb348c97df44	1597	__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void)
lypinator	0:bb348c97df44	1598	{
lypinator	0:bb348c97df44	1599	return(__get_CNTP_CVAL());
lypinator	0:bb348c97df44	1600	}
lypinator	0:bb348c97df44	1601
lypinator	0:bb348c97df44	1602	/** \brief Configure the timer by setting the control value.
lypinator	0:bb348c97df44	1603	* \param [in] value New timer control value.
lypinator	0:bb348c97df44	1604	*/
lypinator	0:bb348c97df44	1605	__STATIC_INLINE void PL1_SetControl(uint32_t value)
lypinator	0:bb348c97df44	1606	{
lypinator	0:bb348c97df44	1607	__set_CNTP_CTL(value);
lypinator	0:bb348c97df44	1608	__ISB();
lypinator	0:bb348c97df44	1609	}
lypinator	0:bb348c97df44	1610
lypinator	0:bb348c97df44	1611	/** \brief Get the control value.
lypinator	0:bb348c97df44	1612	* \return Control value.
lypinator	0:bb348c97df44	1613	*/
lypinator	0:bb348c97df44	1614	__STATIC_INLINE uint32_t PL1_GetControl(void)
lypinator	0:bb348c97df44	1615	{
lypinator	0:bb348c97df44	1616	return(__get_CNTP_CTL());
lypinator	0:bb348c97df44	1617	}
lypinator	0:bb348c97df44	1618	#endif
lypinator	0:bb348c97df44	1619
lypinator	0:bb348c97df44	1620	/* Private Timer */
lypinator	0:bb348c97df44	1621	#if ((__CORTEX_A == 5U) \|\| (__CORTEX_A == 9U)) \|\| defined(DOXYGEN)
lypinator	0:bb348c97df44	1622	/** \brief Set the load value to timers LOAD register.
lypinator	0:bb348c97df44	1623	* \param [in] value The load value to be set.
lypinator	0:bb348c97df44	1624	*/
lypinator	0:bb348c97df44	1625	__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value)
lypinator	0:bb348c97df44	1626	{
lypinator	0:bb348c97df44	1627	PTIM->LOAD = value;
lypinator	0:bb348c97df44	1628	}
lypinator	0:bb348c97df44	1629
lypinator	0:bb348c97df44	1630	/** \brief Get the load value from timers LOAD register.
lypinator	0:bb348c97df44	1631	* \return Timer_Type::LOAD
lypinator	0:bb348c97df44	1632	*/
lypinator	0:bb348c97df44	1633	__STATIC_INLINE uint32_t PTIM_GetLoadValue(void)
lypinator	0:bb348c97df44	1634	{
lypinator	0:bb348c97df44	1635	return(PTIM->LOAD);
lypinator	0:bb348c97df44	1636	}
lypinator	0:bb348c97df44	1637
lypinator	0:bb348c97df44	1638	/** \brief Set current counter value from its COUNTER register.
lypinator	0:bb348c97df44	1639	*/
lypinator	0:bb348c97df44	1640	__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value)
lypinator	0:bb348c97df44	1641	{
lypinator	0:bb348c97df44	1642	PTIM->COUNTER = value;
lypinator	0:bb348c97df44	1643	}
lypinator	0:bb348c97df44	1644
lypinator	0:bb348c97df44	1645	/** \brief Get current counter value from timers COUNTER register.
lypinator	0:bb348c97df44	1646	* \result Timer_Type::COUNTER
lypinator	0:bb348c97df44	1647	*/
lypinator	0:bb348c97df44	1648	__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void)
lypinator	0:bb348c97df44	1649	{
lypinator	0:bb348c97df44	1650	return(PTIM->COUNTER);
lypinator	0:bb348c97df44	1651	}
lypinator	0:bb348c97df44	1652
lypinator	0:bb348c97df44	1653	/** \brief Configure the timer using its CONTROL register.
lypinator	0:bb348c97df44	1654	* \param [in] value The new configuration value to be set.
lypinator	0:bb348c97df44	1655	*/
lypinator	0:bb348c97df44	1656	__STATIC_INLINE void PTIM_SetControl(uint32_t value)
lypinator	0:bb348c97df44	1657	{
lypinator	0:bb348c97df44	1658	PTIM->CONTROL = value;
lypinator	0:bb348c97df44	1659	}
lypinator	0:bb348c97df44	1660
lypinator	0:bb348c97df44	1661	/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register.
lypinator	0:bb348c97df44	1662	* \return Timer_Type::CONTROL
lypinator	0:bb348c97df44	1663	*/
lypinator	0:bb348c97df44	1664	__STATIC_INLINE uint32_t PTIM_GetControl(void)
lypinator	0:bb348c97df44	1665	{
lypinator	0:bb348c97df44	1666	return(PTIM->CONTROL);
lypinator	0:bb348c97df44	1667	}
lypinator	0:bb348c97df44	1668
lypinator	0:bb348c97df44	1669	/** ref Timer_Type::CONTROL Get the event flag in timers ISR register.
lypinator	0:bb348c97df44	1670	* \return 0 - flag is not set, 1- flag is set
lypinator	0:bb348c97df44	1671	*/
lypinator	0:bb348c97df44	1672	__STATIC_INLINE uint32_t PTIM_GetEventFlag(void)
lypinator	0:bb348c97df44	1673	{
lypinator	0:bb348c97df44	1674	return (PTIM->ISR & 1UL);
lypinator	0:bb348c97df44	1675	}
lypinator	0:bb348c97df44	1676
lypinator	0:bb348c97df44	1677	/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register.
lypinator	0:bb348c97df44	1678	*/
lypinator	0:bb348c97df44	1679	__STATIC_INLINE void PTIM_ClearEventFlag(void)
lypinator	0:bb348c97df44	1680	{
lypinator	0:bb348c97df44	1681	PTIM->ISR = 1;
lypinator	0:bb348c97df44	1682	}
lypinator	0:bb348c97df44	1683	#endif
lypinator	0:bb348c97df44	1684	#endif
lypinator	0:bb348c97df44	1685
lypinator	0:bb348c97df44	1686	/* ########################## MMU functions ###################################### */
lypinator	0:bb348c97df44	1687
lypinator	0:bb348c97df44	1688	#define SECTION_DESCRIPTOR (0x2)
lypinator	0:bb348c97df44	1689	#define SECTION_MASK (0xFFFFFFFC)
lypinator	0:bb348c97df44	1690
lypinator	0:bb348c97df44	1691	#define SECTION_TEXCB_MASK (0xFFFF8FF3)
lypinator	0:bb348c97df44	1692	#define SECTION_B_SHIFT (2)
lypinator	0:bb348c97df44	1693	#define SECTION_C_SHIFT (3)
lypinator	0:bb348c97df44	1694	#define SECTION_TEX0_SHIFT (12)
lypinator	0:bb348c97df44	1695	#define SECTION_TEX1_SHIFT (13)
lypinator	0:bb348c97df44	1696	#define SECTION_TEX2_SHIFT (14)
lypinator	0:bb348c97df44	1697
lypinator	0:bb348c97df44	1698	#define SECTION_XN_MASK (0xFFFFFFEF)
lypinator	0:bb348c97df44	1699	#define SECTION_XN_SHIFT (4)
lypinator	0:bb348c97df44	1700
lypinator	0:bb348c97df44	1701	#define SECTION_DOMAIN_MASK (0xFFFFFE1F)
lypinator	0:bb348c97df44	1702	#define SECTION_DOMAIN_SHIFT (5)
lypinator	0:bb348c97df44	1703
lypinator	0:bb348c97df44	1704	#define SECTION_P_MASK (0xFFFFFDFF)
lypinator	0:bb348c97df44	1705	#define SECTION_P_SHIFT (9)
lypinator	0:bb348c97df44	1706
lypinator	0:bb348c97df44	1707	#define SECTION_AP_MASK (0xFFFF73FF)
lypinator	0:bb348c97df44	1708	#define SECTION_AP_SHIFT (10)
lypinator	0:bb348c97df44	1709	#define SECTION_AP2_SHIFT (15)
lypinator	0:bb348c97df44	1710
lypinator	0:bb348c97df44	1711	#define SECTION_S_MASK (0xFFFEFFFF)
lypinator	0:bb348c97df44	1712	#define SECTION_S_SHIFT (16)
lypinator	0:bb348c97df44	1713
lypinator	0:bb348c97df44	1714	#define SECTION_NG_MASK (0xFFFDFFFF)
lypinator	0:bb348c97df44	1715	#define SECTION_NG_SHIFT (17)
lypinator	0:bb348c97df44	1716
lypinator	0:bb348c97df44	1717	#define SECTION_NS_MASK (0xFFF7FFFF)
lypinator	0:bb348c97df44	1718	#define SECTION_NS_SHIFT (19)
lypinator	0:bb348c97df44	1719
lypinator	0:bb348c97df44	1720	#define PAGE_L1_DESCRIPTOR (0x1)
lypinator	0:bb348c97df44	1721	#define PAGE_L1_MASK (0xFFFFFFFC)
lypinator	0:bb348c97df44	1722
lypinator	0:bb348c97df44	1723	#define PAGE_L2_4K_DESC (0x2)
lypinator	0:bb348c97df44	1724	#define PAGE_L2_4K_MASK (0xFFFFFFFD)
lypinator	0:bb348c97df44	1725
lypinator	0:bb348c97df44	1726	#define PAGE_L2_64K_DESC (0x1)
lypinator	0:bb348c97df44	1727	#define PAGE_L2_64K_MASK (0xFFFFFFFC)
lypinator	0:bb348c97df44	1728
lypinator	0:bb348c97df44	1729	#define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
lypinator	0:bb348c97df44	1730	#define PAGE_4K_B_SHIFT (2)
lypinator	0:bb348c97df44	1731	#define PAGE_4K_C_SHIFT (3)
lypinator	0:bb348c97df44	1732	#define PAGE_4K_TEX0_SHIFT (6)
lypinator	0:bb348c97df44	1733	#define PAGE_4K_TEX1_SHIFT (7)
lypinator	0:bb348c97df44	1734	#define PAGE_4K_TEX2_SHIFT (8)
lypinator	0:bb348c97df44	1735
lypinator	0:bb348c97df44	1736	#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
lypinator	0:bb348c97df44	1737	#define PAGE_64K_B_SHIFT (2)
lypinator	0:bb348c97df44	1738	#define PAGE_64K_C_SHIFT (3)
lypinator	0:bb348c97df44	1739	#define PAGE_64K_TEX0_SHIFT (12)
lypinator	0:bb348c97df44	1740	#define PAGE_64K_TEX1_SHIFT (13)
lypinator	0:bb348c97df44	1741	#define PAGE_64K_TEX2_SHIFT (14)
lypinator	0:bb348c97df44	1742
lypinator	0:bb348c97df44	1743	#define PAGE_TEXCB_MASK (0xFFFF8FF3)
lypinator	0:bb348c97df44	1744	#define PAGE_B_SHIFT (2)
lypinator	0:bb348c97df44	1745	#define PAGE_C_SHIFT (3)
lypinator	0:bb348c97df44	1746	#define PAGE_TEX_SHIFT (12)
lypinator	0:bb348c97df44	1747
lypinator	0:bb348c97df44	1748	#define PAGE_XN_4K_MASK (0xFFFFFFFE)
lypinator	0:bb348c97df44	1749	#define PAGE_XN_4K_SHIFT (0)
lypinator	0:bb348c97df44	1750	#define PAGE_XN_64K_MASK (0xFFFF7FFF)
lypinator	0:bb348c97df44	1751	#define PAGE_XN_64K_SHIFT (15)
lypinator	0:bb348c97df44	1752
lypinator	0:bb348c97df44	1753	#define PAGE_DOMAIN_MASK (0xFFFFFE1F)
lypinator	0:bb348c97df44	1754	#define PAGE_DOMAIN_SHIFT (5)
lypinator	0:bb348c97df44	1755
lypinator	0:bb348c97df44	1756	#define PAGE_P_MASK (0xFFFFFDFF)
lypinator	0:bb348c97df44	1757	#define PAGE_P_SHIFT (9)
lypinator	0:bb348c97df44	1758
lypinator	0:bb348c97df44	1759	#define PAGE_AP_MASK (0xFFFFFDCF)
lypinator	0:bb348c97df44	1760	#define PAGE_AP_SHIFT (4)
lypinator	0:bb348c97df44	1761	#define PAGE_AP2_SHIFT (9)
lypinator	0:bb348c97df44	1762
lypinator	0:bb348c97df44	1763	#define PAGE_S_MASK (0xFFFFFBFF)
lypinator	0:bb348c97df44	1764	#define PAGE_S_SHIFT (10)
lypinator	0:bb348c97df44	1765
lypinator	0:bb348c97df44	1766	#define PAGE_NG_MASK (0xFFFFF7FF)
lypinator	0:bb348c97df44	1767	#define PAGE_NG_SHIFT (11)
lypinator	0:bb348c97df44	1768
lypinator	0:bb348c97df44	1769	#define PAGE_NS_MASK (0xFFFFFFF7)
lypinator	0:bb348c97df44	1770	#define PAGE_NS_SHIFT (3)
lypinator	0:bb348c97df44	1771
lypinator	0:bb348c97df44	1772	#define OFFSET_1M (0x00100000)
lypinator	0:bb348c97df44	1773	#define OFFSET_64K (0x00010000)
lypinator	0:bb348c97df44	1774	#define OFFSET_4K (0x00001000)
lypinator	0:bb348c97df44	1775
lypinator	0:bb348c97df44	1776	#define DESCRIPTOR_FAULT (0x00000000)
lypinator	0:bb348c97df44	1777
lypinator	0:bb348c97df44	1778	/* Attributes enumerations */
lypinator	0:bb348c97df44	1779
lypinator	0:bb348c97df44	1780	/* Region size attributes */
lypinator	0:bb348c97df44	1781	typedef enum
lypinator	0:bb348c97df44	1782	{
lypinator	0:bb348c97df44	1783	SECTION,
lypinator	0:bb348c97df44	1784	PAGE_4k,
lypinator	0:bb348c97df44	1785	PAGE_64k,
lypinator	0:bb348c97df44	1786	} mmu_region_size_Type;
lypinator	0:bb348c97df44	1787
lypinator	0:bb348c97df44	1788	/* Region type attributes */
lypinator	0:bb348c97df44	1789	typedef enum
lypinator	0:bb348c97df44	1790	{
lypinator	0:bb348c97df44	1791	NORMAL,
lypinator	0:bb348c97df44	1792	DEVICE,
lypinator	0:bb348c97df44	1793	SHARED_DEVICE,
lypinator	0:bb348c97df44	1794	NON_SHARED_DEVICE,
lypinator	0:bb348c97df44	1795	STRONGLY_ORDERED
lypinator	0:bb348c97df44	1796	} mmu_memory_Type;
lypinator	0:bb348c97df44	1797
lypinator	0:bb348c97df44	1798	/* Region cacheability attributes */
lypinator	0:bb348c97df44	1799	typedef enum
lypinator	0:bb348c97df44	1800	{
lypinator	0:bb348c97df44	1801	NON_CACHEABLE,
lypinator	0:bb348c97df44	1802	WB_WA,
lypinator	0:bb348c97df44	1803	WT,
lypinator	0:bb348c97df44	1804	WB_NO_WA,
lypinator	0:bb348c97df44	1805	} mmu_cacheability_Type;
lypinator	0:bb348c97df44	1806
lypinator	0:bb348c97df44	1807	/* Region parity check attributes */
lypinator	0:bb348c97df44	1808	typedef enum
lypinator	0:bb348c97df44	1809	{
lypinator	0:bb348c97df44	1810	ECC_DISABLED,
lypinator	0:bb348c97df44	1811	ECC_ENABLED,
lypinator	0:bb348c97df44	1812	} mmu_ecc_check_Type;
lypinator	0:bb348c97df44	1813
lypinator	0:bb348c97df44	1814	/* Region execution attributes */
lypinator	0:bb348c97df44	1815	typedef enum
lypinator	0:bb348c97df44	1816	{
lypinator	0:bb348c97df44	1817	EXECUTE,
lypinator	0:bb348c97df44	1818	NON_EXECUTE,
lypinator	0:bb348c97df44	1819	} mmu_execute_Type;
lypinator	0:bb348c97df44	1820
lypinator	0:bb348c97df44	1821	/* Region global attributes */
lypinator	0:bb348c97df44	1822	typedef enum
lypinator	0:bb348c97df44	1823	{
lypinator	0:bb348c97df44	1824	GLOBAL,
lypinator	0:bb348c97df44	1825	NON_GLOBAL,
lypinator	0:bb348c97df44	1826	} mmu_global_Type;
lypinator	0:bb348c97df44	1827
lypinator	0:bb348c97df44	1828	/* Region shareability attributes */
lypinator	0:bb348c97df44	1829	typedef enum
lypinator	0:bb348c97df44	1830	{
lypinator	0:bb348c97df44	1831	NON_SHARED,
lypinator	0:bb348c97df44	1832	SHARED,
lypinator	0:bb348c97df44	1833	} mmu_shared_Type;
lypinator	0:bb348c97df44	1834
lypinator	0:bb348c97df44	1835	/* Region security attributes */
lypinator	0:bb348c97df44	1836	typedef enum
lypinator	0:bb348c97df44	1837	{
lypinator	0:bb348c97df44	1838	SECURE,
lypinator	0:bb348c97df44	1839	NON_SECURE,
lypinator	0:bb348c97df44	1840	} mmu_secure_Type;
lypinator	0:bb348c97df44	1841
lypinator	0:bb348c97df44	1842	/* Region access attributes */
lypinator	0:bb348c97df44	1843	typedef enum
lypinator	0:bb348c97df44	1844	{
lypinator	0:bb348c97df44	1845	NO_ACCESS,
lypinator	0:bb348c97df44	1846	RW,
lypinator	0:bb348c97df44	1847	READ,
lypinator	0:bb348c97df44	1848	} mmu_access_Type;
lypinator	0:bb348c97df44	1849
lypinator	0:bb348c97df44	1850	/* Memory Region definition */
lypinator	0:bb348c97df44	1851	typedef struct RegionStruct {
lypinator	0:bb348c97df44	1852	mmu_region_size_Type rg_t;
lypinator	0:bb348c97df44	1853	mmu_memory_Type mem_t;
lypinator	0:bb348c97df44	1854	uint8_t domain;
lypinator	0:bb348c97df44	1855	mmu_cacheability_Type inner_norm_t;
lypinator	0:bb348c97df44	1856	mmu_cacheability_Type outer_norm_t;
lypinator	0:bb348c97df44	1857	mmu_ecc_check_Type e_t;
lypinator	0:bb348c97df44	1858	mmu_execute_Type xn_t;
lypinator	0:bb348c97df44	1859	mmu_global_Type g_t;
lypinator	0:bb348c97df44	1860	mmu_secure_Type sec_t;
lypinator	0:bb348c97df44	1861	mmu_access_Type priv_t;
lypinator	0:bb348c97df44	1862	mmu_access_Type user_t;
lypinator	0:bb348c97df44	1863	mmu_shared_Type sh_t;
lypinator	0:bb348c97df44	1864
lypinator	0:bb348c97df44	1865	} mmu_region_attributes_Type;
lypinator	0:bb348c97df44	1866
lypinator	0:bb348c97df44	1867	//Following macros define the descriptors and attributes
lypinator	0:bb348c97df44	1868	//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
lypinator	0:bb348c97df44	1869	#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
lypinator	0:bb348c97df44	1870	region.domain = 0x0; \
lypinator	0:bb348c97df44	1871	region.e_t = ECC_DISABLED; \
lypinator	0:bb348c97df44	1872	region.g_t = GLOBAL; \
lypinator	0:bb348c97df44	1873	region.inner_norm_t = WB_WA; \
lypinator	0:bb348c97df44	1874	region.outer_norm_t = WB_WA; \
lypinator	0:bb348c97df44	1875	region.mem_t = NORMAL; \
lypinator	0:bb348c97df44	1876	region.sec_t = SECURE; \
lypinator	0:bb348c97df44	1877	region.xn_t = EXECUTE; \
lypinator	0:bb348c97df44	1878	region.priv_t = RW; \
lypinator	0:bb348c97df44	1879	region.user_t = RW; \
lypinator	0:bb348c97df44	1880	region.sh_t = NON_SHARED; \
lypinator	0:bb348c97df44	1881	MMU_GetSectionDescriptor(&descriptor_l1, region);
lypinator	0:bb348c97df44	1882
lypinator	0:bb348c97df44	1883	//Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0
lypinator	0:bb348c97df44	1884	#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \
lypinator	0:bb348c97df44	1885	region.domain = 0x0; \
lypinator	0:bb348c97df44	1886	region.e_t = ECC_DISABLED; \
lypinator	0:bb348c97df44	1887	region.g_t = GLOBAL; \
lypinator	0:bb348c97df44	1888	region.inner_norm_t = NON_CACHEABLE; \
lypinator	0:bb348c97df44	1889	region.outer_norm_t = NON_CACHEABLE; \
lypinator	0:bb348c97df44	1890	region.mem_t = NORMAL; \
lypinator	0:bb348c97df44	1891	region.sec_t = SECURE; \
lypinator	0:bb348c97df44	1892	region.xn_t = EXECUTE; \
lypinator	0:bb348c97df44	1893	region.priv_t = RW; \
lypinator	0:bb348c97df44	1894	region.user_t = RW; \
lypinator	0:bb348c97df44	1895	region.sh_t = NON_SHARED; \
lypinator	0:bb348c97df44	1896	MMU_GetSectionDescriptor(&descriptor_l1, region);
lypinator	0:bb348c97df44	1897
lypinator	0:bb348c97df44	1898	//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
lypinator	0:bb348c97df44	1899	#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
lypinator	0:bb348c97df44	1900	region.domain = 0x0; \
lypinator	0:bb348c97df44	1901	region.e_t = ECC_DISABLED; \
lypinator	0:bb348c97df44	1902	region.g_t = GLOBAL; \
lypinator	0:bb348c97df44	1903	region.inner_norm_t = WB_WA; \
lypinator	0:bb348c97df44	1904	region.outer_norm_t = WB_WA; \
lypinator	0:bb348c97df44	1905	region.mem_t = NORMAL; \
lypinator	0:bb348c97df44	1906	region.sec_t = SECURE; \
lypinator	0:bb348c97df44	1907	region.xn_t = EXECUTE; \
lypinator	0:bb348c97df44	1908	region.priv_t = READ; \
lypinator	0:bb348c97df44	1909	region.user_t = READ; \
lypinator	0:bb348c97df44	1910	region.sh_t = NON_SHARED; \
lypinator	0:bb348c97df44	1911	MMU_GetSectionDescriptor(&descriptor_l1, region);
lypinator	0:bb348c97df44	1912
lypinator	0:bb348c97df44	1913	//Sect_Normal_RO. Sect_Normal_Cod, but not executable
lypinator	0:bb348c97df44	1914	#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
lypinator	0:bb348c97df44	1915	region.domain = 0x0; \
lypinator	0:bb348c97df44	1916	region.e_t = ECC_DISABLED; \
lypinator	0:bb348c97df44	1917	region.g_t = GLOBAL; \
lypinator	0:bb348c97df44	1918	region.inner_norm_t = WB_WA; \
lypinator	0:bb348c97df44	1919	region.outer_norm_t = WB_WA; \
lypinator	0:bb348c97df44	1920	region.mem_t = NORMAL; \
lypinator	0:bb348c97df44	1921	region.sec_t = SECURE; \
lypinator	0:bb348c97df44	1922	region.xn_t = NON_EXECUTE; \
lypinator	0:bb348c97df44	1923	region.priv_t = READ; \
lypinator	0:bb348c97df44	1924	region.user_t = READ; \
lypinator	0:bb348c97df44	1925	region.sh_t = NON_SHARED; \
lypinator	0:bb348c97df44	1926	MMU_GetSectionDescriptor(&descriptor_l1, region);
lypinator	0:bb348c97df44	1927
lypinator	0:bb348c97df44	1928	//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
lypinator	0:bb348c97df44	1929	#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
lypinator	0:bb348c97df44	1930	region.domain = 0x0; \
lypinator	0:bb348c97df44	1931	region.e_t = ECC_DISABLED; \
lypinator	0:bb348c97df44	1932	region.g_t = GLOBAL; \
lypinator	0:bb348c97df44	1933	region.inner_norm_t = WB_WA; \
lypinator	0:bb348c97df44	1934	region.outer_norm_t = WB_WA; \
lypinator	0:bb348c97df44	1935	region.mem_t = NORMAL; \
lypinator	0:bb348c97df44	1936	region.sec_t = SECURE; \
lypinator	0:bb348c97df44	1937	region.xn_t = NON_EXECUTE; \
lypinator	0:bb348c97df44	1938	region.priv_t = RW; \
lypinator	0:bb348c97df44	1939	region.user_t = RW; \
lypinator	0:bb348c97df44	1940	region.sh_t = NON_SHARED; \
lypinator	0:bb348c97df44	1941	MMU_GetSectionDescriptor(&descriptor_l1, region);
lypinator	0:bb348c97df44	1942	//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
lypinator	0:bb348c97df44	1943	#define section_so(descriptor_l1, region) region.rg_t = SECTION; \
lypinator	0:bb348c97df44	1944	region.domain = 0x0; \
lypinator	0:bb348c97df44	1945	region.e_t = ECC_DISABLED; \
lypinator	0:bb348c97df44	1946	region.g_t = GLOBAL; \
lypinator	0:bb348c97df44	1947	region.inner_norm_t = NON_CACHEABLE; \
lypinator	0:bb348c97df44	1948	region.outer_norm_t = NON_CACHEABLE; \
lypinator	0:bb348c97df44	1949	region.mem_t = STRONGLY_ORDERED; \
lypinator	0:bb348c97df44	1950	region.sec_t = SECURE; \
lypinator	0:bb348c97df44	1951	region.xn_t = NON_EXECUTE; \
lypinator	0:bb348c97df44	1952	region.priv_t = RW; \
lypinator	0:bb348c97df44	1953	region.user_t = RW; \
lypinator	0:bb348c97df44	1954	region.sh_t = NON_SHARED; \
lypinator	0:bb348c97df44	1955	MMU_GetSectionDescriptor(&descriptor_l1, region);
lypinator	0:bb348c97df44	1956
lypinator	0:bb348c97df44	1957	//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
lypinator	0:bb348c97df44	1958	#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
lypinator	0:bb348c97df44	1959	region.domain = 0x0; \
lypinator	0:bb348c97df44	1960	region.e_t = ECC_DISABLED; \
lypinator	0:bb348c97df44	1961	region.g_t = GLOBAL; \
lypinator	0:bb348c97df44	1962	region.inner_norm_t = NON_CACHEABLE; \
lypinator	0:bb348c97df44	1963	region.outer_norm_t = NON_CACHEABLE; \
lypinator	0:bb348c97df44	1964	region.mem_t = STRONGLY_ORDERED; \
lypinator	0:bb348c97df44	1965	region.sec_t = SECURE; \
lypinator	0:bb348c97df44	1966	region.xn_t = NON_EXECUTE; \
lypinator	0:bb348c97df44	1967	region.priv_t = READ; \
lypinator	0:bb348c97df44	1968	region.user_t = READ; \
lypinator	0:bb348c97df44	1969	region.sh_t = NON_SHARED; \
lypinator	0:bb348c97df44	1970	MMU_GetSectionDescriptor(&descriptor_l1, region);
lypinator	0:bb348c97df44	1971
lypinator	0:bb348c97df44	1972	//Sect_Device_RW. Sect_Device_RO, but writeable
lypinator	0:bb348c97df44	1973	#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
lypinator	0:bb348c97df44	1974	region.domain = 0x0; \
lypinator	0:bb348c97df44	1975	region.e_t = ECC_DISABLED; \
lypinator	0:bb348c97df44	1976	region.g_t = GLOBAL; \
lypinator	0:bb348c97df44	1977	region.inner_norm_t = NON_CACHEABLE; \
lypinator	0:bb348c97df44	1978	region.outer_norm_t = NON_CACHEABLE; \
lypinator	0:bb348c97df44	1979	region.mem_t = STRONGLY_ORDERED; \
lypinator	0:bb348c97df44	1980	region.sec_t = SECURE; \
lypinator	0:bb348c97df44	1981	region.xn_t = NON_EXECUTE; \
lypinator	0:bb348c97df44	1982	region.priv_t = RW; \
lypinator	0:bb348c97df44	1983	region.user_t = RW; \
lypinator	0:bb348c97df44	1984	region.sh_t = NON_SHARED; \
lypinator	0:bb348c97df44	1985	MMU_GetSectionDescriptor(&descriptor_l1, region);
lypinator	0:bb348c97df44	1986	//Page_4k_Device_RW. Shared device, not executable, rw, domain 0
lypinator	0:bb348c97df44	1987	#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
lypinator	0:bb348c97df44	1988	region.domain = 0x0; \
lypinator	0:bb348c97df44	1989	region.e_t = ECC_DISABLED; \
lypinator	0:bb348c97df44	1990	region.g_t = GLOBAL; \
lypinator	0:bb348c97df44	1991	region.inner_norm_t = NON_CACHEABLE; \
lypinator	0:bb348c97df44	1992	region.outer_norm_t = NON_CACHEABLE; \
lypinator	0:bb348c97df44	1993	region.mem_t = SHARED_DEVICE; \
lypinator	0:bb348c97df44	1994	region.sec_t = SECURE; \
lypinator	0:bb348c97df44	1995	region.xn_t = NON_EXECUTE; \
lypinator	0:bb348c97df44	1996	region.priv_t = RW; \
lypinator	0:bb348c97df44	1997	region.user_t = RW; \
lypinator	0:bb348c97df44	1998	region.sh_t = NON_SHARED; \
lypinator	0:bb348c97df44	1999	MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
lypinator	0:bb348c97df44	2000
lypinator	0:bb348c97df44	2001	//Page_64k_Device_RW. Shared device, not executable, rw, domain 0
lypinator	0:bb348c97df44	2002	#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
lypinator	0:bb348c97df44	2003	region.domain = 0x0; \
lypinator	0:bb348c97df44	2004	region.e_t = ECC_DISABLED; \
lypinator	0:bb348c97df44	2005	region.g_t = GLOBAL; \
lypinator	0:bb348c97df44	2006	region.inner_norm_t = NON_CACHEABLE; \
lypinator	0:bb348c97df44	2007	region.outer_norm_t = NON_CACHEABLE; \
lypinator	0:bb348c97df44	2008	region.mem_t = SHARED_DEVICE; \
lypinator	0:bb348c97df44	2009	region.sec_t = SECURE; \
lypinator	0:bb348c97df44	2010	region.xn_t = NON_EXECUTE; \
lypinator	0:bb348c97df44	2011	region.priv_t = RW; \
lypinator	0:bb348c97df44	2012	region.user_t = RW; \
lypinator	0:bb348c97df44	2013	region.sh_t = NON_SHARED; \
lypinator	0:bb348c97df44	2014	MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
lypinator	0:bb348c97df44	2015
lypinator	0:bb348c97df44	2016	/** \brief Set section execution-never attribute
lypinator	0:bb348c97df44	2017
lypinator	0:bb348c97df44	2018	\param [out] descriptor_l1 L1 descriptor.
lypinator	0:bb348c97df44	2019	\param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
lypinator	0:bb348c97df44	2020
lypinator	0:bb348c97df44	2021	\return 0
lypinator	0:bb348c97df44	2022	*/
lypinator	0:bb348c97df44	2023	__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
lypinator	0:bb348c97df44	2024	{
lypinator	0:bb348c97df44	2025	*descriptor_l1 &= SECTION_XN_MASK;
lypinator	0:bb348c97df44	2026	*descriptor_l1 \|= ((xn & 0x1) << SECTION_XN_SHIFT);
lypinator	0:bb348c97df44	2027	return 0;
lypinator	0:bb348c97df44	2028	}
lypinator	0:bb348c97df44	2029
lypinator	0:bb348c97df44	2030	/** \brief Set section domain
lypinator	0:bb348c97df44	2031
lypinator	0:bb348c97df44	2032	\param [out] descriptor_l1 L1 descriptor.
lypinator	0:bb348c97df44	2033	\param [in] domain Section domain
lypinator	0:bb348c97df44	2034
lypinator	0:bb348c97df44	2035	\return 0
lypinator	0:bb348c97df44	2036	*/
lypinator	0:bb348c97df44	2037	__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
lypinator	0:bb348c97df44	2038	{
lypinator	0:bb348c97df44	2039	*descriptor_l1 &= SECTION_DOMAIN_MASK;
lypinator	0:bb348c97df44	2040	*descriptor_l1 \|= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
lypinator	0:bb348c97df44	2041	return 0;
lypinator	0:bb348c97df44	2042	}
lypinator	0:bb348c97df44	2043
lypinator	0:bb348c97df44	2044	/** \brief Set section parity check
lypinator	0:bb348c97df44	2045
lypinator	0:bb348c97df44	2046	\param [out] descriptor_l1 L1 descriptor.
lypinator	0:bb348c97df44	2047	\param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
lypinator	0:bb348c97df44	2048
lypinator	0:bb348c97df44	2049	\return 0
lypinator	0:bb348c97df44	2050	*/
lypinator	0:bb348c97df44	2051	__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
lypinator	0:bb348c97df44	2052	{
lypinator	0:bb348c97df44	2053	*descriptor_l1 &= SECTION_P_MASK;
lypinator	0:bb348c97df44	2054	*descriptor_l1 \|= ((p_bit & 0x1) << SECTION_P_SHIFT);
lypinator	0:bb348c97df44	2055	return 0;
lypinator	0:bb348c97df44	2056	}
lypinator	0:bb348c97df44	2057
lypinator	0:bb348c97df44	2058	/** \brief Set section access privileges
lypinator	0:bb348c97df44	2059
lypinator	0:bb348c97df44	2060	\param [out] descriptor_l1 L1 descriptor.
lypinator	0:bb348c97df44	2061	\param [in] user User Level Access: NO_ACCESS, RW, READ
lypinator	0:bb348c97df44	2062	\param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
lypinator	0:bb348c97df44	2063	\param [in] afe Access flag enable
lypinator	0:bb348c97df44	2064
lypinator	0:bb348c97df44	2065	\return 0
lypinator	0:bb348c97df44	2066	*/
lypinator	0:bb348c97df44	2067	__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
lypinator	0:bb348c97df44	2068	{
lypinator	0:bb348c97df44	2069	uint32_t ap = 0;
lypinator	0:bb348c97df44	2070
lypinator	0:bb348c97df44	2071	if (afe == 0) { //full access
lypinator	0:bb348c97df44	2072	if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
lypinator	0:bb348c97df44	2073	else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
lypinator	0:bb348c97df44	2074	else if ((priv == RW) && (user == READ)) { ap = 0x2; }
lypinator	0:bb348c97df44	2075	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
lypinator	0:bb348c97df44	2076	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
lypinator	0:bb348c97df44	2077	else if ((priv == READ) && (user == READ)) { ap = 0x7; }
lypinator	0:bb348c97df44	2078	}
lypinator	0:bb348c97df44	2079
lypinator	0:bb348c97df44	2080	else { //Simplified access
lypinator	0:bb348c97df44	2081	if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
lypinator	0:bb348c97df44	2082	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
lypinator	0:bb348c97df44	2083	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
lypinator	0:bb348c97df44	2084	else if ((priv == READ) && (user == READ)) { ap = 0x7; }
lypinator	0:bb348c97df44	2085	}
lypinator	0:bb348c97df44	2086
lypinator	0:bb348c97df44	2087	*descriptor_l1 &= SECTION_AP_MASK;
lypinator	0:bb348c97df44	2088	*descriptor_l1 \|= (ap & 0x3) << SECTION_AP_SHIFT;
lypinator	0:bb348c97df44	2089	*descriptor_l1 \|= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
lypinator	0:bb348c97df44	2090
lypinator	0:bb348c97df44	2091	return 0;
lypinator	0:bb348c97df44	2092	}
lypinator	0:bb348c97df44	2093
lypinator	0:bb348c97df44	2094	/** \brief Set section shareability
lypinator	0:bb348c97df44	2095
lypinator	0:bb348c97df44	2096	\param [out] descriptor_l1 L1 descriptor.
lypinator	0:bb348c97df44	2097	\param [in] s_bit Section shareability: NON_SHARED, SHARED
lypinator	0:bb348c97df44	2098
lypinator	0:bb348c97df44	2099	\return 0
lypinator	0:bb348c97df44	2100	*/
lypinator	0:bb348c97df44	2101	__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
lypinator	0:bb348c97df44	2102	{
lypinator	0:bb348c97df44	2103	*descriptor_l1 &= SECTION_S_MASK;
lypinator	0:bb348c97df44	2104	*descriptor_l1 \|= ((s_bit & 0x1) << SECTION_S_SHIFT);
lypinator	0:bb348c97df44	2105	return 0;
lypinator	0:bb348c97df44	2106	}
lypinator	0:bb348c97df44	2107
lypinator	0:bb348c97df44	2108	/** \brief Set section Global attribute
lypinator	0:bb348c97df44	2109
lypinator	0:bb348c97df44	2110	\param [out] descriptor_l1 L1 descriptor.
lypinator	0:bb348c97df44	2111	\param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
lypinator	0:bb348c97df44	2112
lypinator	0:bb348c97df44	2113	\return 0
lypinator	0:bb348c97df44	2114	*/
lypinator	0:bb348c97df44	2115	__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
lypinator	0:bb348c97df44	2116	{
lypinator	0:bb348c97df44	2117	*descriptor_l1 &= SECTION_NG_MASK;
lypinator	0:bb348c97df44	2118	*descriptor_l1 \|= ((g_bit & 0x1) << SECTION_NG_SHIFT);
lypinator	0:bb348c97df44	2119	return 0;
lypinator	0:bb348c97df44	2120	}
lypinator	0:bb348c97df44	2121
lypinator	0:bb348c97df44	2122	/** \brief Set section Security attribute
lypinator	0:bb348c97df44	2123
lypinator	0:bb348c97df44	2124	\param [out] descriptor_l1 L1 descriptor.
lypinator	0:bb348c97df44	2125	\param [in] s_bit Section Security attribute: SECURE, NON_SECURE
lypinator	0:bb348c97df44	2126
lypinator	0:bb348c97df44	2127	\return 0
lypinator	0:bb348c97df44	2128	*/
lypinator	0:bb348c97df44	2129	__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
lypinator	0:bb348c97df44	2130	{
lypinator	0:bb348c97df44	2131	*descriptor_l1 &= SECTION_NS_MASK;
lypinator	0:bb348c97df44	2132	*descriptor_l1 \|= ((s_bit & 0x1) << SECTION_NS_SHIFT);
lypinator	0:bb348c97df44	2133	return 0;
lypinator	0:bb348c97df44	2134	}
lypinator	0:bb348c97df44	2135
lypinator	0:bb348c97df44	2136	/* Page 4k or 64k */
lypinator	0:bb348c97df44	2137	/** \brief Set 4k/64k page execution-never attribute
lypinator	0:bb348c97df44	2138
lypinator	0:bb348c97df44	2139	\param [out] descriptor_l2 L2 descriptor.
lypinator	0:bb348c97df44	2140	\param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
lypinator	0:bb348c97df44	2141	\param [in] page Page size: PAGE_4k, PAGE_64k,
lypinator	0:bb348c97df44	2142
lypinator	0:bb348c97df44	2143	\return 0
lypinator	0:bb348c97df44	2144	*/
lypinator	0:bb348c97df44	2145	__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
lypinator	0:bb348c97df44	2146	{
lypinator	0:bb348c97df44	2147	if (page == PAGE_4k)
lypinator	0:bb348c97df44	2148	{
lypinator	0:bb348c97df44	2149	*descriptor_l2 &= PAGE_XN_4K_MASK;
lypinator	0:bb348c97df44	2150	*descriptor_l2 \|= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
lypinator	0:bb348c97df44	2151	}
lypinator	0:bb348c97df44	2152	else
lypinator	0:bb348c97df44	2153	{
lypinator	0:bb348c97df44	2154	*descriptor_l2 &= PAGE_XN_64K_MASK;
lypinator	0:bb348c97df44	2155	*descriptor_l2 \|= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
lypinator	0:bb348c97df44	2156	}
lypinator	0:bb348c97df44	2157	return 0;
lypinator	0:bb348c97df44	2158	}
lypinator	0:bb348c97df44	2159
lypinator	0:bb348c97df44	2160	/** \brief Set 4k/64k page domain
lypinator	0:bb348c97df44	2161
lypinator	0:bb348c97df44	2162	\param [out] descriptor_l1 L1 descriptor.
lypinator	0:bb348c97df44	2163	\param [in] domain Page domain
lypinator	0:bb348c97df44	2164
lypinator	0:bb348c97df44	2165	\return 0
lypinator	0:bb348c97df44	2166	*/
lypinator	0:bb348c97df44	2167	__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
lypinator	0:bb348c97df44	2168	{
lypinator	0:bb348c97df44	2169	*descriptor_l1 &= PAGE_DOMAIN_MASK;
lypinator	0:bb348c97df44	2170	*descriptor_l1 \|= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
lypinator	0:bb348c97df44	2171	return 0;
lypinator	0:bb348c97df44	2172	}
lypinator	0:bb348c97df44	2173
lypinator	0:bb348c97df44	2174	/** \brief Set 4k/64k page parity check
lypinator	0:bb348c97df44	2175
lypinator	0:bb348c97df44	2176	\param [out] descriptor_l1 L1 descriptor.
lypinator	0:bb348c97df44	2177	\param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
lypinator	0:bb348c97df44	2178
lypinator	0:bb348c97df44	2179	\return 0
lypinator	0:bb348c97df44	2180	*/
lypinator	0:bb348c97df44	2181	__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
lypinator	0:bb348c97df44	2182	{
lypinator	0:bb348c97df44	2183	*descriptor_l1 &= SECTION_P_MASK;
lypinator	0:bb348c97df44	2184	*descriptor_l1 \|= ((p_bit & 0x1) << SECTION_P_SHIFT);
lypinator	0:bb348c97df44	2185	return 0;
lypinator	0:bb348c97df44	2186	}
lypinator	0:bb348c97df44	2187
lypinator	0:bb348c97df44	2188	/** \brief Set 4k/64k page access privileges
lypinator	0:bb348c97df44	2189
lypinator	0:bb348c97df44	2190	\param [out] descriptor_l2 L2 descriptor.
lypinator	0:bb348c97df44	2191	\param [in] user User Level Access: NO_ACCESS, RW, READ
lypinator	0:bb348c97df44	2192	\param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
lypinator	0:bb348c97df44	2193	\param [in] afe Access flag enable
lypinator	0:bb348c97df44	2194
lypinator	0:bb348c97df44	2195	\return 0
lypinator	0:bb348c97df44	2196	*/
lypinator	0:bb348c97df44	2197	__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
lypinator	0:bb348c97df44	2198	{
lypinator	0:bb348c97df44	2199	uint32_t ap = 0;
lypinator	0:bb348c97df44	2200
lypinator	0:bb348c97df44	2201	if (afe == 0) { //full access
lypinator	0:bb348c97df44	2202	if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
lypinator	0:bb348c97df44	2203	else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
lypinator	0:bb348c97df44	2204	else if ((priv == RW) && (user == READ)) { ap = 0x2; }
lypinator	0:bb348c97df44	2205	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
lypinator	0:bb348c97df44	2206	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
lypinator	0:bb348c97df44	2207	else if ((priv == READ) && (user == READ)) { ap = 0x6; }
lypinator	0:bb348c97df44	2208	}
lypinator	0:bb348c97df44	2209
lypinator	0:bb348c97df44	2210	else { //Simplified access
lypinator	0:bb348c97df44	2211	if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
lypinator	0:bb348c97df44	2212	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
lypinator	0:bb348c97df44	2213	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
lypinator	0:bb348c97df44	2214	else if ((priv == READ) && (user == READ)) { ap = 0x7; }
lypinator	0:bb348c97df44	2215	}
lypinator	0:bb348c97df44	2216
lypinator	0:bb348c97df44	2217	*descriptor_l2 &= PAGE_AP_MASK;
lypinator	0:bb348c97df44	2218	*descriptor_l2 \|= (ap & 0x3) << PAGE_AP_SHIFT;
lypinator	0:bb348c97df44	2219	*descriptor_l2 \|= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
lypinator	0:bb348c97df44	2220
lypinator	0:bb348c97df44	2221	return 0;
lypinator	0:bb348c97df44	2222	}
lypinator	0:bb348c97df44	2223
lypinator	0:bb348c97df44	2224	/** \brief Set 4k/64k page shareability
lypinator	0:bb348c97df44	2225
lypinator	0:bb348c97df44	2226	\param [out] descriptor_l2 L2 descriptor.
lypinator	0:bb348c97df44	2227	\param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
lypinator	0:bb348c97df44	2228
lypinator	0:bb348c97df44	2229	\return 0
lypinator	0:bb348c97df44	2230	*/
lypinator	0:bb348c97df44	2231	__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
lypinator	0:bb348c97df44	2232	{
lypinator	0:bb348c97df44	2233	*descriptor_l2 &= PAGE_S_MASK;
lypinator	0:bb348c97df44	2234	*descriptor_l2 \|= ((s_bit & 0x1) << PAGE_S_SHIFT);
lypinator	0:bb348c97df44	2235	return 0;
lypinator	0:bb348c97df44	2236	}
lypinator	0:bb348c97df44	2237
lypinator	0:bb348c97df44	2238	/** \brief Set 4k/64k page Global attribute
lypinator	0:bb348c97df44	2239
lypinator	0:bb348c97df44	2240	\param [out] descriptor_l2 L2 descriptor.
lypinator	0:bb348c97df44	2241	\param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
lypinator	0:bb348c97df44	2242
lypinator	0:bb348c97df44	2243	\return 0
lypinator	0:bb348c97df44	2244	*/
lypinator	0:bb348c97df44	2245	__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
lypinator	0:bb348c97df44	2246	{
lypinator	0:bb348c97df44	2247	*descriptor_l2 &= PAGE_NG_MASK;
lypinator	0:bb348c97df44	2248	*descriptor_l2 \|= ((g_bit & 0x1) << PAGE_NG_SHIFT);
lypinator	0:bb348c97df44	2249	return 0;
lypinator	0:bb348c97df44	2250	}
lypinator	0:bb348c97df44	2251
lypinator	0:bb348c97df44	2252	/** \brief Set 4k/64k page Security attribute
lypinator	0:bb348c97df44	2253
lypinator	0:bb348c97df44	2254	\param [out] descriptor_l1 L1 descriptor.
lypinator	0:bb348c97df44	2255	\param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
lypinator	0:bb348c97df44	2256
lypinator	0:bb348c97df44	2257	\return 0
lypinator	0:bb348c97df44	2258	*/
lypinator	0:bb348c97df44	2259	__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
lypinator	0:bb348c97df44	2260	{
lypinator	0:bb348c97df44	2261	*descriptor_l1 &= PAGE_NS_MASK;
lypinator	0:bb348c97df44	2262	*descriptor_l1 \|= ((s_bit & 0x1) << PAGE_NS_SHIFT);
lypinator	0:bb348c97df44	2263	return 0;
lypinator	0:bb348c97df44	2264	}
lypinator	0:bb348c97df44	2265
lypinator	0:bb348c97df44	2266	/** \brief Set Section memory attributes
lypinator	0:bb348c97df44	2267
lypinator	0:bb348c97df44	2268	\param [out] descriptor_l1 L1 descriptor.
lypinator	0:bb348c97df44	2269	\param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
lypinator	0:bb348c97df44	2270	\param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
lypinator	0:bb348c97df44	2271	\param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
lypinator	0:bb348c97df44	2272
lypinator	0:bb348c97df44	2273	\return 0
lypinator	0:bb348c97df44	2274	*/
lypinator	0:bb348c97df44	2275	__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
lypinator	0:bb348c97df44	2276	{
lypinator	0:bb348c97df44	2277	*descriptor_l1 &= SECTION_TEXCB_MASK;
lypinator	0:bb348c97df44	2278
lypinator	0:bb348c97df44	2279	if (STRONGLY_ORDERED == mem)
lypinator	0:bb348c97df44	2280	{
lypinator	0:bb348c97df44	2281	return 0;
lypinator	0:bb348c97df44	2282	}
lypinator	0:bb348c97df44	2283	else if (SHARED_DEVICE == mem)
lypinator	0:bb348c97df44	2284	{
lypinator	0:bb348c97df44	2285	*descriptor_l1 \|= (1 << SECTION_B_SHIFT);
lypinator	0:bb348c97df44	2286	}
lypinator	0:bb348c97df44	2287	else if (NON_SHARED_DEVICE == mem)
lypinator	0:bb348c97df44	2288	{
lypinator	0:bb348c97df44	2289	*descriptor_l1 \|= (1 << SECTION_TEX1_SHIFT);
lypinator	0:bb348c97df44	2290	}
lypinator	0:bb348c97df44	2291	else if (NORMAL == mem)
lypinator	0:bb348c97df44	2292	{
lypinator	0:bb348c97df44	2293	*descriptor_l1 \|= 1 << SECTION_TEX2_SHIFT;
lypinator	0:bb348c97df44	2294	switch(inner)
lypinator	0:bb348c97df44	2295	{
lypinator	0:bb348c97df44	2296	case NON_CACHEABLE:
lypinator	0:bb348c97df44	2297	break;
lypinator	0:bb348c97df44	2298	case WB_WA:
lypinator	0:bb348c97df44	2299	*descriptor_l1 \|= (1 << SECTION_B_SHIFT);
lypinator	0:bb348c97df44	2300	break;
lypinator	0:bb348c97df44	2301	case WT:
lypinator	0:bb348c97df44	2302	*descriptor_l1 \|= 1 << SECTION_C_SHIFT;
lypinator	0:bb348c97df44	2303	break;
lypinator	0:bb348c97df44	2304	case WB_NO_WA:
lypinator	0:bb348c97df44	2305	*descriptor_l1 \|= (1 << SECTION_B_SHIFT) \| (1 << SECTION_C_SHIFT);
lypinator	0:bb348c97df44	2306	break;
lypinator	0:bb348c97df44	2307	}
lypinator	0:bb348c97df44	2308	switch(outer)
lypinator	0:bb348c97df44	2309	{
lypinator	0:bb348c97df44	2310	case NON_CACHEABLE:
lypinator	0:bb348c97df44	2311	break;
lypinator	0:bb348c97df44	2312	case WB_WA:
lypinator	0:bb348c97df44	2313	*descriptor_l1 \|= (1 << SECTION_TEX0_SHIFT);
lypinator	0:bb348c97df44	2314	break;
lypinator	0:bb348c97df44	2315	case WT:
lypinator	0:bb348c97df44	2316	*descriptor_l1 \|= 1 << SECTION_TEX1_SHIFT;
lypinator	0:bb348c97df44	2317	break;
lypinator	0:bb348c97df44	2318	case WB_NO_WA:
lypinator	0:bb348c97df44	2319	*descriptor_l1 \|= (1 << SECTION_TEX0_SHIFT) \| (1 << SECTION_TEX0_SHIFT);
lypinator	0:bb348c97df44	2320	break;
lypinator	0:bb348c97df44	2321	}
lypinator	0:bb348c97df44	2322	}
lypinator	0:bb348c97df44	2323	return 0;
lypinator	0:bb348c97df44	2324	}
lypinator	0:bb348c97df44	2325
lypinator	0:bb348c97df44	2326	/** \brief Set 4k/64k page memory attributes
lypinator	0:bb348c97df44	2327
lypinator	0:bb348c97df44	2328	\param [out] descriptor_l2 L2 descriptor.
lypinator	0:bb348c97df44	2329	\param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
lypinator	0:bb348c97df44	2330	\param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
lypinator	0:bb348c97df44	2331	\param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
lypinator	0:bb348c97df44	2332	\param [in] page Page size
lypinator	0:bb348c97df44	2333
lypinator	0:bb348c97df44	2334	\return 0
lypinator	0:bb348c97df44	2335	*/
lypinator	0:bb348c97df44	2336	__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
lypinator	0:bb348c97df44	2337	{
lypinator	0:bb348c97df44	2338	*descriptor_l2 &= PAGE_4K_TEXCB_MASK;
lypinator	0:bb348c97df44	2339
lypinator	0:bb348c97df44	2340	if (page == PAGE_64k)
lypinator	0:bb348c97df44	2341	{
lypinator	0:bb348c97df44	2342	//same as section
lypinator	0:bb348c97df44	2343	MMU_MemorySection(descriptor_l2, mem, outer, inner);
lypinator	0:bb348c97df44	2344	}
lypinator	0:bb348c97df44	2345	else
lypinator	0:bb348c97df44	2346	{
lypinator	0:bb348c97df44	2347	if (STRONGLY_ORDERED == mem)
lypinator	0:bb348c97df44	2348	{
lypinator	0:bb348c97df44	2349	return 0;
lypinator	0:bb348c97df44	2350	}
lypinator	0:bb348c97df44	2351	else if (SHARED_DEVICE == mem)
lypinator	0:bb348c97df44	2352	{
lypinator	0:bb348c97df44	2353	*descriptor_l2 \|= (1 << PAGE_4K_B_SHIFT);
lypinator	0:bb348c97df44	2354	}
lypinator	0:bb348c97df44	2355	else if (NON_SHARED_DEVICE == mem)
lypinator	0:bb348c97df44	2356	{
lypinator	0:bb348c97df44	2357	*descriptor_l2 \|= (1 << PAGE_4K_TEX1_SHIFT);
lypinator	0:bb348c97df44	2358	}
lypinator	0:bb348c97df44	2359	else if (NORMAL == mem)
lypinator	0:bb348c97df44	2360	{
lypinator	0:bb348c97df44	2361	*descriptor_l2 \|= 1 << PAGE_4K_TEX2_SHIFT;
lypinator	0:bb348c97df44	2362	switch(inner)
lypinator	0:bb348c97df44	2363	{
lypinator	0:bb348c97df44	2364	case NON_CACHEABLE:
lypinator	0:bb348c97df44	2365	break;
lypinator	0:bb348c97df44	2366	case WB_WA:
lypinator	0:bb348c97df44	2367	*descriptor_l2 \|= (1 << PAGE_4K_B_SHIFT);
lypinator	0:bb348c97df44	2368	break;
lypinator	0:bb348c97df44	2369	case WT:
lypinator	0:bb348c97df44	2370	*descriptor_l2 \|= 1 << PAGE_4K_C_SHIFT;
lypinator	0:bb348c97df44	2371	break;
lypinator	0:bb348c97df44	2372	case WB_NO_WA:
lypinator	0:bb348c97df44	2373	*descriptor_l2 \|= (1 << PAGE_4K_B_SHIFT) \| (1 << PAGE_4K_C_SHIFT);
lypinator	0:bb348c97df44	2374	break;
lypinator	0:bb348c97df44	2375	}
lypinator	0:bb348c97df44	2376	switch(outer)
lypinator	0:bb348c97df44	2377	{
lypinator	0:bb348c97df44	2378	case NON_CACHEABLE:
lypinator	0:bb348c97df44	2379	break;
lypinator	0:bb348c97df44	2380	case WB_WA:
lypinator	0:bb348c97df44	2381	*descriptor_l2 \|= (1 << PAGE_4K_TEX0_SHIFT);
lypinator	0:bb348c97df44	2382	break;
lypinator	0:bb348c97df44	2383	case WT:
lypinator	0:bb348c97df44	2384	*descriptor_l2 \|= 1 << PAGE_4K_TEX1_SHIFT;
lypinator	0:bb348c97df44	2385	break;
lypinator	0:bb348c97df44	2386	case WB_NO_WA:
lypinator	0:bb348c97df44	2387	*descriptor_l2 \|= (1 << PAGE_4K_TEX0_SHIFT) \| (1 << PAGE_4K_TEX0_SHIFT);
lypinator	0:bb348c97df44	2388	break;
lypinator	0:bb348c97df44	2389	}
lypinator	0:bb348c97df44	2390	}
lypinator	0:bb348c97df44	2391	}
lypinator	0:bb348c97df44	2392
lypinator	0:bb348c97df44	2393	return 0;
lypinator	0:bb348c97df44	2394	}
lypinator	0:bb348c97df44	2395
lypinator	0:bb348c97df44	2396	/** \brief Create a L1 section descriptor
lypinator	0:bb348c97df44	2397
lypinator	0:bb348c97df44	2398	\param [out] descriptor L1 descriptor
lypinator	0:bb348c97df44	2399	\param [in] reg Section attributes
lypinator	0:bb348c97df44	2400
lypinator	0:bb348c97df44	2401	\return 0
lypinator	0:bb348c97df44	2402	*/
lypinator	0:bb348c97df44	2403	__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
lypinator	0:bb348c97df44	2404	{
lypinator	0:bb348c97df44	2405	*descriptor = 0;
lypinator	0:bb348c97df44	2406
lypinator	0:bb348c97df44	2407	MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
lypinator	0:bb348c97df44	2408	MMU_XNSection(descriptor,reg.xn_t);
lypinator	0:bb348c97df44	2409	MMU_DomainSection(descriptor, reg.domain);
lypinator	0:bb348c97df44	2410	MMU_PSection(descriptor, reg.e_t);
lypinator	0:bb348c97df44	2411	MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1);
lypinator	0:bb348c97df44	2412	MMU_SharedSection(descriptor,reg.sh_t);
lypinator	0:bb348c97df44	2413	MMU_GlobalSection(descriptor,reg.g_t);
lypinator	0:bb348c97df44	2414	MMU_SecureSection(descriptor,reg.sec_t);
lypinator	0:bb348c97df44	2415	*descriptor &= SECTION_MASK;
lypinator	0:bb348c97df44	2416	*descriptor \|= SECTION_DESCRIPTOR;
lypinator	0:bb348c97df44	2417
lypinator	0:bb348c97df44	2418	return 0;
lypinator	0:bb348c97df44	2419	}
lypinator	0:bb348c97df44	2420
lypinator	0:bb348c97df44	2421
lypinator	0:bb348c97df44	2422	/** \brief Create a L1 and L2 4k/64k page descriptor
lypinator	0:bb348c97df44	2423
lypinator	0:bb348c97df44	2424	\param [out] descriptor L1 descriptor
lypinator	0:bb348c97df44	2425	\param [out] descriptor2 L2 descriptor
lypinator	0:bb348c97df44	2426	\param [in] reg 4k/64k page attributes
lypinator	0:bb348c97df44	2427
lypinator	0:bb348c97df44	2428	\return 0
lypinator	0:bb348c97df44	2429	*/
lypinator	0:bb348c97df44	2430	__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t descriptor, uint32_t descriptor2, mmu_region_attributes_Type reg)
lypinator	0:bb348c97df44	2431	{
lypinator	0:bb348c97df44	2432	*descriptor = 0;
lypinator	0:bb348c97df44	2433	*descriptor2 = 0;
lypinator	0:bb348c97df44	2434
lypinator	0:bb348c97df44	2435	switch (reg.rg_t)
lypinator	0:bb348c97df44	2436	{
lypinator	0:bb348c97df44	2437	case PAGE_4k:
lypinator	0:bb348c97df44	2438	MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
lypinator	0:bb348c97df44	2439	MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
lypinator	0:bb348c97df44	2440	MMU_DomainPage(descriptor, reg.domain);
lypinator	0:bb348c97df44	2441	MMU_PPage(descriptor, reg.e_t);
lypinator	0:bb348c97df44	2442	MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
lypinator	0:bb348c97df44	2443	MMU_SharedPage(descriptor2,reg.sh_t);
lypinator	0:bb348c97df44	2444	MMU_GlobalPage(descriptor2,reg.g_t);
lypinator	0:bb348c97df44	2445	MMU_SecurePage(descriptor,reg.sec_t);
lypinator	0:bb348c97df44	2446	*descriptor &= PAGE_L1_MASK;
lypinator	0:bb348c97df44	2447	*descriptor \|= PAGE_L1_DESCRIPTOR;
lypinator	0:bb348c97df44	2448	*descriptor2 &= PAGE_L2_4K_MASK;
lypinator	0:bb348c97df44	2449	*descriptor2 \|= PAGE_L2_4K_DESC;
lypinator	0:bb348c97df44	2450	break;
lypinator	0:bb348c97df44	2451
lypinator	0:bb348c97df44	2452	case PAGE_64k:
lypinator	0:bb348c97df44	2453	MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
lypinator	0:bb348c97df44	2454	MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
lypinator	0:bb348c97df44	2455	MMU_DomainPage(descriptor, reg.domain);
lypinator	0:bb348c97df44	2456	MMU_PPage(descriptor, reg.e_t);
lypinator	0:bb348c97df44	2457	MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
lypinator	0:bb348c97df44	2458	MMU_SharedPage(descriptor2,reg.sh_t);
lypinator	0:bb348c97df44	2459	MMU_GlobalPage(descriptor2,reg.g_t);
lypinator	0:bb348c97df44	2460	MMU_SecurePage(descriptor,reg.sec_t);
lypinator	0:bb348c97df44	2461	*descriptor &= PAGE_L1_MASK;
lypinator	0:bb348c97df44	2462	*descriptor \|= PAGE_L1_DESCRIPTOR;
lypinator	0:bb348c97df44	2463	*descriptor2 &= PAGE_L2_64K_MASK;
lypinator	0:bb348c97df44	2464	*descriptor2 \|= PAGE_L2_64K_DESC;
lypinator	0:bb348c97df44	2465	break;
lypinator	0:bb348c97df44	2466
lypinator	0:bb348c97df44	2467	case SECTION:
lypinator	0:bb348c97df44	2468	//error
lypinator	0:bb348c97df44	2469	break;
lypinator	0:bb348c97df44	2470	}
lypinator	0:bb348c97df44	2471
lypinator	0:bb348c97df44	2472	return 0;
lypinator	0:bb348c97df44	2473	}
lypinator	0:bb348c97df44	2474
lypinator	0:bb348c97df44	2475	/** \brief Create a 1MB Section
lypinator	0:bb348c97df44	2476
lypinator	0:bb348c97df44	2477	\param [in] ttb Translation table base address
lypinator	0:bb348c97df44	2478	\param [in] base_address Section base address
lypinator	0:bb348c97df44	2479	\param [in] count Number of sections to create
lypinator	0:bb348c97df44	2480	\param [in] descriptor_l1 L1 descriptor (region attributes)
lypinator	0:bb348c97df44	2481
lypinator	0:bb348c97df44	2482	*/
lypinator	0:bb348c97df44	2483	__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
lypinator	0:bb348c97df44	2484	{
lypinator	0:bb348c97df44	2485	uint32_t offset;
lypinator	0:bb348c97df44	2486	uint32_t entry;
lypinator	0:bb348c97df44	2487	uint32_t i;
lypinator	0:bb348c97df44	2488
lypinator	0:bb348c97df44	2489	offset = base_address >> 20;
lypinator	0:bb348c97df44	2490	entry = (base_address & 0xFFF00000) \| descriptor_l1;
lypinator	0:bb348c97df44	2491
lypinator	0:bb348c97df44	2492	//4 bytes aligned
lypinator	0:bb348c97df44	2493	ttb = ttb + offset;
lypinator	0:bb348c97df44	2494
lypinator	0:bb348c97df44	2495	for (i = 0; i < count; i++ )
lypinator	0:bb348c97df44	2496	{
lypinator	0:bb348c97df44	2497	//4 bytes aligned
lypinator	0:bb348c97df44	2498	*ttb++ = entry;
lypinator	0:bb348c97df44	2499	entry += OFFSET_1M;
lypinator	0:bb348c97df44	2500	}
lypinator	0:bb348c97df44	2501	}
lypinator	0:bb348c97df44	2502
lypinator	0:bb348c97df44	2503	/** \brief Create a 4k page entry
lypinator	0:bb348c97df44	2504
lypinator	0:bb348c97df44	2505	\param [in] ttb L1 table base address
lypinator	0:bb348c97df44	2506	\param [in] base_address 4k base address
lypinator	0:bb348c97df44	2507	\param [in] count Number of 4k pages to create
lypinator	0:bb348c97df44	2508	\param [in] descriptor_l1 L1 descriptor (region attributes)
lypinator	0:bb348c97df44	2509	\param [in] ttb_l2 L2 table base address
lypinator	0:bb348c97df44	2510	\param [in] descriptor_l2 L2 descriptor (region attributes)
lypinator	0:bb348c97df44	2511
lypinator	0:bb348c97df44	2512	*/
lypinator	0:bb348c97df44	2513	__STATIC_INLINE void MMU_TTPage4k(uint32_t ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t ttb_l2, uint32_t descriptor_l2 )
lypinator	0:bb348c97df44	2514	{
lypinator	0:bb348c97df44	2515
lypinator	0:bb348c97df44	2516	uint32_t offset, offset2;
lypinator	0:bb348c97df44	2517	uint32_t entry, entry2;
lypinator	0:bb348c97df44	2518	uint32_t i;
lypinator	0:bb348c97df44	2519
lypinator	0:bb348c97df44	2520	offset = base_address >> 20;
lypinator	0:bb348c97df44	2521	entry = ((int)ttb_l2 & 0xFFFFFC00) \| descriptor_l1;
lypinator	0:bb348c97df44	2522
lypinator	0:bb348c97df44	2523	//4 bytes aligned
lypinator	0:bb348c97df44	2524	ttb += offset;
lypinator	0:bb348c97df44	2525	//create l1_entry
lypinator	0:bb348c97df44	2526	*ttb = entry;
lypinator	0:bb348c97df44	2527
lypinator	0:bb348c97df44	2528	offset2 = (base_address & 0xff000) >> 12;
lypinator	0:bb348c97df44	2529	ttb_l2 += offset2;
lypinator	0:bb348c97df44	2530	entry2 = (base_address & 0xFFFFF000) \| descriptor_l2;
lypinator	0:bb348c97df44	2531	for (i = 0; i < count; i++ )
lypinator	0:bb348c97df44	2532	{
lypinator	0:bb348c97df44	2533	//4 bytes aligned
lypinator	0:bb348c97df44	2534	*ttb_l2++ = entry2;
lypinator	0:bb348c97df44	2535	entry2 += OFFSET_4K;
lypinator	0:bb348c97df44	2536	}
lypinator	0:bb348c97df44	2537	}
lypinator	0:bb348c97df44	2538
lypinator	0:bb348c97df44	2539	/** \brief Create a 64k page entry
lypinator	0:bb348c97df44	2540
lypinator	0:bb348c97df44	2541	\param [in] ttb L1 table base address
lypinator	0:bb348c97df44	2542	\param [in] base_address 64k base address
lypinator	0:bb348c97df44	2543	\param [in] count Number of 64k pages to create
lypinator	0:bb348c97df44	2544	\param [in] descriptor_l1 L1 descriptor (region attributes)
lypinator	0:bb348c97df44	2545	\param [in] ttb_l2 L2 table base address
lypinator	0:bb348c97df44	2546	\param [in] descriptor_l2 L2 descriptor (region attributes)
lypinator	0:bb348c97df44	2547
lypinator	0:bb348c97df44	2548	*/
lypinator	0:bb348c97df44	2549	__STATIC_INLINE void MMU_TTPage64k(uint32_t ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t ttb_l2, uint32_t descriptor_l2 )
lypinator	0:bb348c97df44	2550	{
lypinator	0:bb348c97df44	2551	uint32_t offset, offset2;
lypinator	0:bb348c97df44	2552	uint32_t entry, entry2;
lypinator	0:bb348c97df44	2553	uint32_t i,j;
lypinator	0:bb348c97df44	2554
lypinator	0:bb348c97df44	2555
lypinator	0:bb348c97df44	2556	offset = base_address >> 20;
lypinator	0:bb348c97df44	2557	entry = ((int)ttb_l2 & 0xFFFFFC00) \| descriptor_l1;
lypinator	0:bb348c97df44	2558
lypinator	0:bb348c97df44	2559	//4 bytes aligned
lypinator	0:bb348c97df44	2560	ttb += offset;
lypinator	0:bb348c97df44	2561	//create l1_entry
lypinator	0:bb348c97df44	2562	*ttb = entry;
lypinator	0:bb348c97df44	2563
lypinator	0:bb348c97df44	2564	offset2 = (base_address & 0xff000) >> 12;
lypinator	0:bb348c97df44	2565	ttb_l2 += offset2;
lypinator	0:bb348c97df44	2566	entry2 = (base_address & 0xFFFF0000) \| descriptor_l2;
lypinator	0:bb348c97df44	2567	for (i = 0; i < count; i++ )
lypinator	0:bb348c97df44	2568	{
lypinator	0:bb348c97df44	2569	//create 16 entries
lypinator	0:bb348c97df44	2570	for (j = 0; j < 16; j++)
lypinator	0:bb348c97df44	2571	{
lypinator	0:bb348c97df44	2572	//4 bytes aligned
lypinator	0:bb348c97df44	2573	*ttb_l2++ = entry2;
lypinator	0:bb348c97df44	2574	}
lypinator	0:bb348c97df44	2575	entry2 += OFFSET_64K;
lypinator	0:bb348c97df44	2576	}
lypinator	0:bb348c97df44	2577	}
lypinator	0:bb348c97df44	2578
lypinator	0:bb348c97df44	2579	/** \brief Enable MMU
lypinator	0:bb348c97df44	2580	*/
lypinator	0:bb348c97df44	2581	__STATIC_INLINE void MMU_Enable(void)
lypinator	0:bb348c97df44	2582	{
lypinator	0:bb348c97df44	2583	// Set M bit 0 to enable the MMU
lypinator	0:bb348c97df44	2584	// Set AFE bit to enable simplified access permissions model
lypinator	0:bb348c97df44	2585	// Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
lypinator	0:bb348c97df44	2586	__set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) \| 1 \| (1 << 29));
lypinator	0:bb348c97df44	2587	__ISB();
lypinator	0:bb348c97df44	2588	}
lypinator	0:bb348c97df44	2589
lypinator	0:bb348c97df44	2590	/** \brief Disable MMU
lypinator	0:bb348c97df44	2591	*/
lypinator	0:bb348c97df44	2592	__STATIC_INLINE void MMU_Disable(void)
lypinator	0:bb348c97df44	2593	{
lypinator	0:bb348c97df44	2594	// Clear M bit 0 to disable the MMU
lypinator	0:bb348c97df44	2595	__set_SCTLR( __get_SCTLR() & ~1);
lypinator	0:bb348c97df44	2596	__ISB();
lypinator	0:bb348c97df44	2597	}
lypinator	0:bb348c97df44	2598
lypinator	0:bb348c97df44	2599	/** \brief Invalidate entire unified TLB
lypinator	0:bb348c97df44	2600	*/
lypinator	0:bb348c97df44	2601
lypinator	0:bb348c97df44	2602	__STATIC_INLINE void MMU_InvalidateTLB(void)
lypinator	0:bb348c97df44	2603	{
lypinator	0:bb348c97df44	2604	__set_TLBIALL(0);
lypinator	0:bb348c97df44	2605	__DSB(); //ensure completion of the invalidation
lypinator	0:bb348c97df44	2606	__ISB(); //ensure instruction fetch path sees new state
lypinator	0:bb348c97df44	2607	}
lypinator	0:bb348c97df44	2608
lypinator	0:bb348c97df44	2609
lypinator	0:bb348c97df44	2610	#ifdef __cplusplus
lypinator	0:bb348c97df44	2611	}
lypinator	0:bb348c97df44	2612	#endif
lypinator	0:bb348c97df44	2613
lypinator	0:bb348c97df44	2614	#endif /* __CORE_CA_H_DEPENDANT */
lypinator	0:bb348c97df44	2615
lypinator	0:bb348c97df44	2616	#endif /* __CMSIS_GENERIC */

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Type:	Program
Created:	16 Sep 2020
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

mbed-dev-master/cmsis/TARGET_CORTEX_A/core_ca.h@0:bb348c97df44, 2020-09-16 (annotated)

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