Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**************************************************************************//**
lypinator 0:bb348c97df44 2 * @file cmsis_iccarm.h
lypinator 0:bb348c97df44 3 * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
lypinator 0:bb348c97df44 4 * @version V5.0.5
lypinator 0:bb348c97df44 5 * @date 10. January 2018
lypinator 0:bb348c97df44 6 ******************************************************************************/
lypinator 0:bb348c97df44 7
lypinator 0:bb348c97df44 8 //------------------------------------------------------------------------------
lypinator 0:bb348c97df44 9 //
lypinator 0:bb348c97df44 10 // Copyright (c) 2017-2018 IAR Systems
lypinator 0:bb348c97df44 11 //
lypinator 0:bb348c97df44 12 // Licensed under the Apache License, Version 2.0 (the "License")
lypinator 0:bb348c97df44 13 // you may not use this file except in compliance with the License.
lypinator 0:bb348c97df44 14 // You may obtain a copy of the License at
lypinator 0:bb348c97df44 15 // http://www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 16 //
lypinator 0:bb348c97df44 17 // Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 18 // distributed under the License is distributed on an "AS IS" BASIS,
lypinator 0:bb348c97df44 19 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 20 // See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 21 // limitations under the License.
lypinator 0:bb348c97df44 22 //
lypinator 0:bb348c97df44 23 //------------------------------------------------------------------------------
lypinator 0:bb348c97df44 24
lypinator 0:bb348c97df44 25
lypinator 0:bb348c97df44 26 #ifndef __CMSIS_ICCARM_H__
lypinator 0:bb348c97df44 27 #define __CMSIS_ICCARM_H__
lypinator 0:bb348c97df44 28
lypinator 0:bb348c97df44 29 #ifndef __ICCARM__
lypinator 0:bb348c97df44 30 #error This file should only be compiled by ICCARM
lypinator 0:bb348c97df44 31 #endif
lypinator 0:bb348c97df44 32
lypinator 0:bb348c97df44 33 #pragma system_include
lypinator 0:bb348c97df44 34
lypinator 0:bb348c97df44 35 #define __IAR_FT _Pragma("inline=forced") __intrinsic
lypinator 0:bb348c97df44 36
lypinator 0:bb348c97df44 37 #if (__VER__ >= 8000000)
lypinator 0:bb348c97df44 38 #define __ICCARM_V8 1
lypinator 0:bb348c97df44 39 #else
lypinator 0:bb348c97df44 40 #define __ICCARM_V8 0
lypinator 0:bb348c97df44 41 #endif
lypinator 0:bb348c97df44 42
lypinator 0:bb348c97df44 43 #pragma language=extended
lypinator 0:bb348c97df44 44
lypinator 0:bb348c97df44 45 #ifndef __ALIGNED
lypinator 0:bb348c97df44 46 #if __ICCARM_V8
lypinator 0:bb348c97df44 47 #define __ALIGNED(x) __attribute__((aligned(x)))
lypinator 0:bb348c97df44 48 #elif (__VER__ >= 7080000)
lypinator 0:bb348c97df44 49 /* Needs IAR language extensions */
lypinator 0:bb348c97df44 50 #define __ALIGNED(x) __attribute__((aligned(x)))
lypinator 0:bb348c97df44 51 #else
lypinator 0:bb348c97df44 52 #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
lypinator 0:bb348c97df44 53 #define __ALIGNED(x)
lypinator 0:bb348c97df44 54 #endif
lypinator 0:bb348c97df44 55 #endif
lypinator 0:bb348c97df44 56
lypinator 0:bb348c97df44 57
lypinator 0:bb348c97df44 58 /* Define compiler macros for CPU architecture, used in CMSIS 5.
lypinator 0:bb348c97df44 59 */
lypinator 0:bb348c97df44 60 #if __ARM_ARCH_7A__
lypinator 0:bb348c97df44 61 /* Macro already defined */
lypinator 0:bb348c97df44 62 #else
lypinator 0:bb348c97df44 63 #if defined(__ARM7A__)
lypinator 0:bb348c97df44 64 #define __ARM_ARCH_7A__ 1
lypinator 0:bb348c97df44 65 #endif
lypinator 0:bb348c97df44 66 #endif
lypinator 0:bb348c97df44 67
lypinator 0:bb348c97df44 68 #ifndef __ASM
lypinator 0:bb348c97df44 69 #define __ASM __asm
lypinator 0:bb348c97df44 70 #endif
lypinator 0:bb348c97df44 71
lypinator 0:bb348c97df44 72 #ifndef __INLINE
lypinator 0:bb348c97df44 73 #define __INLINE inline
lypinator 0:bb348c97df44 74 #endif
lypinator 0:bb348c97df44 75
lypinator 0:bb348c97df44 76 #ifndef __NO_RETURN
lypinator 0:bb348c97df44 77 #if __ICCARM_V8
lypinator 0:bb348c97df44 78 #define __NO_RETURN __attribute__((__noreturn__))
lypinator 0:bb348c97df44 79 #else
lypinator 0:bb348c97df44 80 #define __NO_RETURN _Pragma("object_attribute=__noreturn")
lypinator 0:bb348c97df44 81 #endif
lypinator 0:bb348c97df44 82 #endif
lypinator 0:bb348c97df44 83
lypinator 0:bb348c97df44 84 #ifndef __PACKED
lypinator 0:bb348c97df44 85 /* Needs IAR language extensions */
lypinator 0:bb348c97df44 86 #if __ICCARM_V8
lypinator 0:bb348c97df44 87 #define __PACKED __attribute__((packed, aligned(1)))
lypinator 0:bb348c97df44 88 #else
lypinator 0:bb348c97df44 89 #define __PACKED __packed
lypinator 0:bb348c97df44 90 #endif
lypinator 0:bb348c97df44 91 #endif
lypinator 0:bb348c97df44 92
lypinator 0:bb348c97df44 93 #ifndef __PACKED_STRUCT
lypinator 0:bb348c97df44 94 /* Needs IAR language extensions */
lypinator 0:bb348c97df44 95 #if __ICCARM_V8
lypinator 0:bb348c97df44 96 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
lypinator 0:bb348c97df44 97 #else
lypinator 0:bb348c97df44 98 #define __PACKED_STRUCT __packed struct
lypinator 0:bb348c97df44 99 #endif
lypinator 0:bb348c97df44 100 #endif
lypinator 0:bb348c97df44 101
lypinator 0:bb348c97df44 102 #ifndef __PACKED_UNION
lypinator 0:bb348c97df44 103 /* Needs IAR language extensions */
lypinator 0:bb348c97df44 104 #if __ICCARM_V8
lypinator 0:bb348c97df44 105 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
lypinator 0:bb348c97df44 106 #else
lypinator 0:bb348c97df44 107 #define __PACKED_UNION __packed union
lypinator 0:bb348c97df44 108 #endif
lypinator 0:bb348c97df44 109 #endif
lypinator 0:bb348c97df44 110
lypinator 0:bb348c97df44 111 #ifndef __RESTRICT
lypinator 0:bb348c97df44 112 #define __RESTRICT restrict
lypinator 0:bb348c97df44 113 #endif
lypinator 0:bb348c97df44 114
lypinator 0:bb348c97df44 115 #ifndef __STATIC_INLINE
lypinator 0:bb348c97df44 116 #define __STATIC_INLINE static inline
lypinator 0:bb348c97df44 117 #endif
lypinator 0:bb348c97df44 118
lypinator 0:bb348c97df44 119 #ifndef __FORCEINLINE
lypinator 0:bb348c97df44 120 #define __FORCEINLINE _Pragma("inline=forced")
lypinator 0:bb348c97df44 121 #endif
lypinator 0:bb348c97df44 122
lypinator 0:bb348c97df44 123 #ifndef __STATIC_FORCEINLINE
lypinator 0:bb348c97df44 124 #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
lypinator 0:bb348c97df44 125 #endif
lypinator 0:bb348c97df44 126
lypinator 0:bb348c97df44 127 #ifndef CMSIS_DEPRECATED
lypinator 0:bb348c97df44 128 #define CMSIS_DEPRECATED __attribute__((deprecated))
lypinator 0:bb348c97df44 129 #endif
lypinator 0:bb348c97df44 130
lypinator 0:bb348c97df44 131 #ifndef __UNALIGNED_UINT16_READ
lypinator 0:bb348c97df44 132 #pragma language=save
lypinator 0:bb348c97df44 133 #pragma language=extended
lypinator 0:bb348c97df44 134 __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
lypinator 0:bb348c97df44 135 {
lypinator 0:bb348c97df44 136 return *(__packed uint16_t*)(ptr);
lypinator 0:bb348c97df44 137 }
lypinator 0:bb348c97df44 138 #pragma language=restore
lypinator 0:bb348c97df44 139 #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
lypinator 0:bb348c97df44 140 #endif
lypinator 0:bb348c97df44 141
lypinator 0:bb348c97df44 142
lypinator 0:bb348c97df44 143 #ifndef __UNALIGNED_UINT16_WRITE
lypinator 0:bb348c97df44 144 #pragma language=save
lypinator 0:bb348c97df44 145 #pragma language=extended
lypinator 0:bb348c97df44 146 __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
lypinator 0:bb348c97df44 147 {
lypinator 0:bb348c97df44 148 *(__packed uint16_t*)(ptr) = val;;
lypinator 0:bb348c97df44 149 }
lypinator 0:bb348c97df44 150 #pragma language=restore
lypinator 0:bb348c97df44 151 #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
lypinator 0:bb348c97df44 152 #endif
lypinator 0:bb348c97df44 153
lypinator 0:bb348c97df44 154 #ifndef __UNALIGNED_UINT32_READ
lypinator 0:bb348c97df44 155 #pragma language=save
lypinator 0:bb348c97df44 156 #pragma language=extended
lypinator 0:bb348c97df44 157 __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
lypinator 0:bb348c97df44 158 {
lypinator 0:bb348c97df44 159 return *(__packed uint32_t*)(ptr);
lypinator 0:bb348c97df44 160 }
lypinator 0:bb348c97df44 161 #pragma language=restore
lypinator 0:bb348c97df44 162 #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
lypinator 0:bb348c97df44 163 #endif
lypinator 0:bb348c97df44 164
lypinator 0:bb348c97df44 165 #ifndef __UNALIGNED_UINT32_WRITE
lypinator 0:bb348c97df44 166 #pragma language=save
lypinator 0:bb348c97df44 167 #pragma language=extended
lypinator 0:bb348c97df44 168 __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
lypinator 0:bb348c97df44 169 {
lypinator 0:bb348c97df44 170 *(__packed uint32_t*)(ptr) = val;;
lypinator 0:bb348c97df44 171 }
lypinator 0:bb348c97df44 172 #pragma language=restore
lypinator 0:bb348c97df44 173 #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
lypinator 0:bb348c97df44 174 #endif
lypinator 0:bb348c97df44 175
lypinator 0:bb348c97df44 176 #if 0
lypinator 0:bb348c97df44 177 #ifndef __UNALIGNED_UINT32 /* deprecated */
lypinator 0:bb348c97df44 178 #pragma language=save
lypinator 0:bb348c97df44 179 #pragma language=extended
lypinator 0:bb348c97df44 180 __packed struct __iar_u32 { uint32_t v; };
lypinator 0:bb348c97df44 181 #pragma language=restore
lypinator 0:bb348c97df44 182 #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
lypinator 0:bb348c97df44 183 #endif
lypinator 0:bb348c97df44 184 #endif
lypinator 0:bb348c97df44 185
lypinator 0:bb348c97df44 186 #ifndef __USED
lypinator 0:bb348c97df44 187 #if __ICCARM_V8
lypinator 0:bb348c97df44 188 #define __USED __attribute__((used))
lypinator 0:bb348c97df44 189 #else
lypinator 0:bb348c97df44 190 #define __USED _Pragma("__root")
lypinator 0:bb348c97df44 191 #endif
lypinator 0:bb348c97df44 192 #endif
lypinator 0:bb348c97df44 193
lypinator 0:bb348c97df44 194 #ifndef __WEAK
lypinator 0:bb348c97df44 195 #if __ICCARM_V8
lypinator 0:bb348c97df44 196 #define __WEAK __attribute__((weak))
lypinator 0:bb348c97df44 197 #else
lypinator 0:bb348c97df44 198 #define __WEAK _Pragma("__weak")
lypinator 0:bb348c97df44 199 #endif
lypinator 0:bb348c97df44 200 #endif
lypinator 0:bb348c97df44 201
lypinator 0:bb348c97df44 202
lypinator 0:bb348c97df44 203 #ifndef __ICCARM_INTRINSICS_VERSION__
lypinator 0:bb348c97df44 204 #define __ICCARM_INTRINSICS_VERSION__ 0
lypinator 0:bb348c97df44 205 #endif
lypinator 0:bb348c97df44 206
lypinator 0:bb348c97df44 207 #if __ICCARM_INTRINSICS_VERSION__ == 2
lypinator 0:bb348c97df44 208
lypinator 0:bb348c97df44 209 #if defined(__CLZ)
lypinator 0:bb348c97df44 210 #undef __CLZ
lypinator 0:bb348c97df44 211 #endif
lypinator 0:bb348c97df44 212 #if defined(__REVSH)
lypinator 0:bb348c97df44 213 #undef __REVSH
lypinator 0:bb348c97df44 214 #endif
lypinator 0:bb348c97df44 215 #if defined(__RBIT)
lypinator 0:bb348c97df44 216 #undef __RBIT
lypinator 0:bb348c97df44 217 #endif
lypinator 0:bb348c97df44 218 #if defined(__SSAT)
lypinator 0:bb348c97df44 219 #undef __SSAT
lypinator 0:bb348c97df44 220 #endif
lypinator 0:bb348c97df44 221 #if defined(__USAT)
lypinator 0:bb348c97df44 222 #undef __USAT
lypinator 0:bb348c97df44 223 #endif
lypinator 0:bb348c97df44 224
lypinator 0:bb348c97df44 225 #include "iccarm_builtin.h"
lypinator 0:bb348c97df44 226
lypinator 0:bb348c97df44 227 #define __enable_irq __iar_builtin_enable_interrupt
lypinator 0:bb348c97df44 228 #define __disable_irq __iar_builtin_disable_interrupt
lypinator 0:bb348c97df44 229 #define __enable_fault_irq __iar_builtin_enable_fiq
lypinator 0:bb348c97df44 230 #define __disable_fault_irq __iar_builtin_disable_fiq
lypinator 0:bb348c97df44 231 #define __arm_rsr __iar_builtin_rsr
lypinator 0:bb348c97df44 232 #define __arm_wsr __iar_builtin_wsr
lypinator 0:bb348c97df44 233
lypinator 0:bb348c97df44 234 #if __FPU_PRESENT
lypinator 0:bb348c97df44 235 #define __get_FPSCR() (__arm_rsr("FPSCR"))
lypinator 0:bb348c97df44 236 #else
lypinator 0:bb348c97df44 237 #define __get_FPSCR() ( 0 )
lypinator 0:bb348c97df44 238 #endif
lypinator 0:bb348c97df44 239
lypinator 0:bb348c97df44 240 #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", VALUE))
lypinator 0:bb348c97df44 241
lypinator 0:bb348c97df44 242 #define __get_CPSR() (__arm_rsr("CPSR"))
lypinator 0:bb348c97df44 243 #define __get_mode() (__get_CPSR() & 0x1FU)
lypinator 0:bb348c97df44 244
lypinator 0:bb348c97df44 245 #define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE)))
lypinator 0:bb348c97df44 246 #define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE)))
lypinator 0:bb348c97df44 247
lypinator 0:bb348c97df44 248
lypinator 0:bb348c97df44 249 #define __get_FPEXC() (__arm_rsr("FPEXC"))
lypinator 0:bb348c97df44 250 #define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE))
lypinator 0:bb348c97df44 251
lypinator 0:bb348c97df44 252 #define __get_CP(cp, op1, RT, CRn, CRm, op2) \
lypinator 0:bb348c97df44 253 ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2))
lypinator 0:bb348c97df44 254
lypinator 0:bb348c97df44 255 #define __set_CP(cp, op1, RT, CRn, CRm, op2) \
lypinator 0:bb348c97df44 256 (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT)))
lypinator 0:bb348c97df44 257
lypinator 0:bb348c97df44 258 #define __get_CP64(cp, op1, Rt, CRm) \
lypinator 0:bb348c97df44 259 __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
lypinator 0:bb348c97df44 260
lypinator 0:bb348c97df44 261 #define __set_CP64(cp, op1, Rt, CRm) \
lypinator 0:bb348c97df44 262 __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
lypinator 0:bb348c97df44 263
lypinator 0:bb348c97df44 264 #include "cmsis_cp15.h"
lypinator 0:bb348c97df44 265
lypinator 0:bb348c97df44 266 #define __NOP __iar_builtin_no_operation
lypinator 0:bb348c97df44 267
lypinator 0:bb348c97df44 268 #define __CLZ __iar_builtin_CLZ
lypinator 0:bb348c97df44 269 #define __CLREX __iar_builtin_CLREX
lypinator 0:bb348c97df44 270
lypinator 0:bb348c97df44 271 #define __DMB __iar_builtin_DMB
lypinator 0:bb348c97df44 272 #define __DSB __iar_builtin_DSB
lypinator 0:bb348c97df44 273 #define __ISB __iar_builtin_ISB
lypinator 0:bb348c97df44 274
lypinator 0:bb348c97df44 275 #define __LDREXB __iar_builtin_LDREXB
lypinator 0:bb348c97df44 276 #define __LDREXH __iar_builtin_LDREXH
lypinator 0:bb348c97df44 277 #define __LDREXW __iar_builtin_LDREX
lypinator 0:bb348c97df44 278
lypinator 0:bb348c97df44 279 #define __RBIT __iar_builtin_RBIT
lypinator 0:bb348c97df44 280 #define __REV __iar_builtin_REV
lypinator 0:bb348c97df44 281 #define __REV16 __iar_builtin_REV16
lypinator 0:bb348c97df44 282
lypinator 0:bb348c97df44 283 __IAR_FT int16_t __REVSH(int16_t val)
lypinator 0:bb348c97df44 284 {
lypinator 0:bb348c97df44 285 return (int16_t) __iar_builtin_REVSH(val);
lypinator 0:bb348c97df44 286 }
lypinator 0:bb348c97df44 287
lypinator 0:bb348c97df44 288 #define __ROR __iar_builtin_ROR
lypinator 0:bb348c97df44 289 #define __RRX __iar_builtin_RRX
lypinator 0:bb348c97df44 290
lypinator 0:bb348c97df44 291 #define __SEV __iar_builtin_SEV
lypinator 0:bb348c97df44 292
lypinator 0:bb348c97df44 293 #define __SSAT __iar_builtin_SSAT
lypinator 0:bb348c97df44 294
lypinator 0:bb348c97df44 295 #define __STREXB __iar_builtin_STREXB
lypinator 0:bb348c97df44 296 #define __STREXH __iar_builtin_STREXH
lypinator 0:bb348c97df44 297 #define __STREXW __iar_builtin_STREX
lypinator 0:bb348c97df44 298
lypinator 0:bb348c97df44 299 #define __USAT __iar_builtin_USAT
lypinator 0:bb348c97df44 300
lypinator 0:bb348c97df44 301 #define __WFE __iar_builtin_WFE
lypinator 0:bb348c97df44 302 #define __WFI __iar_builtin_WFI
lypinator 0:bb348c97df44 303
lypinator 0:bb348c97df44 304 #define __SADD8 __iar_builtin_SADD8
lypinator 0:bb348c97df44 305 #define __QADD8 __iar_builtin_QADD8
lypinator 0:bb348c97df44 306 #define __SHADD8 __iar_builtin_SHADD8
lypinator 0:bb348c97df44 307 #define __UADD8 __iar_builtin_UADD8
lypinator 0:bb348c97df44 308 #define __UQADD8 __iar_builtin_UQADD8
lypinator 0:bb348c97df44 309 #define __UHADD8 __iar_builtin_UHADD8
lypinator 0:bb348c97df44 310 #define __SSUB8 __iar_builtin_SSUB8
lypinator 0:bb348c97df44 311 #define __QSUB8 __iar_builtin_QSUB8
lypinator 0:bb348c97df44 312 #define __SHSUB8 __iar_builtin_SHSUB8
lypinator 0:bb348c97df44 313 #define __USUB8 __iar_builtin_USUB8
lypinator 0:bb348c97df44 314 #define __UQSUB8 __iar_builtin_UQSUB8
lypinator 0:bb348c97df44 315 #define __UHSUB8 __iar_builtin_UHSUB8
lypinator 0:bb348c97df44 316 #define __SADD16 __iar_builtin_SADD16
lypinator 0:bb348c97df44 317 #define __QADD16 __iar_builtin_QADD16
lypinator 0:bb348c97df44 318 #define __SHADD16 __iar_builtin_SHADD16
lypinator 0:bb348c97df44 319 #define __UADD16 __iar_builtin_UADD16
lypinator 0:bb348c97df44 320 #define __UQADD16 __iar_builtin_UQADD16
lypinator 0:bb348c97df44 321 #define __UHADD16 __iar_builtin_UHADD16
lypinator 0:bb348c97df44 322 #define __SSUB16 __iar_builtin_SSUB16
lypinator 0:bb348c97df44 323 #define __QSUB16 __iar_builtin_QSUB16
lypinator 0:bb348c97df44 324 #define __SHSUB16 __iar_builtin_SHSUB16
lypinator 0:bb348c97df44 325 #define __USUB16 __iar_builtin_USUB16
lypinator 0:bb348c97df44 326 #define __UQSUB16 __iar_builtin_UQSUB16
lypinator 0:bb348c97df44 327 #define __UHSUB16 __iar_builtin_UHSUB16
lypinator 0:bb348c97df44 328 #define __SASX __iar_builtin_SASX
lypinator 0:bb348c97df44 329 #define __QASX __iar_builtin_QASX
lypinator 0:bb348c97df44 330 #define __SHASX __iar_builtin_SHASX
lypinator 0:bb348c97df44 331 #define __UASX __iar_builtin_UASX
lypinator 0:bb348c97df44 332 #define __UQASX __iar_builtin_UQASX
lypinator 0:bb348c97df44 333 #define __UHASX __iar_builtin_UHASX
lypinator 0:bb348c97df44 334 #define __SSAX __iar_builtin_SSAX
lypinator 0:bb348c97df44 335 #define __QSAX __iar_builtin_QSAX
lypinator 0:bb348c97df44 336 #define __SHSAX __iar_builtin_SHSAX
lypinator 0:bb348c97df44 337 #define __USAX __iar_builtin_USAX
lypinator 0:bb348c97df44 338 #define __UQSAX __iar_builtin_UQSAX
lypinator 0:bb348c97df44 339 #define __UHSAX __iar_builtin_UHSAX
lypinator 0:bb348c97df44 340 #define __USAD8 __iar_builtin_USAD8
lypinator 0:bb348c97df44 341 #define __USADA8 __iar_builtin_USADA8
lypinator 0:bb348c97df44 342 #define __SSAT16 __iar_builtin_SSAT16
lypinator 0:bb348c97df44 343 #define __USAT16 __iar_builtin_USAT16
lypinator 0:bb348c97df44 344 #define __UXTB16 __iar_builtin_UXTB16
lypinator 0:bb348c97df44 345 #define __UXTAB16 __iar_builtin_UXTAB16
lypinator 0:bb348c97df44 346 #define __SXTB16 __iar_builtin_SXTB16
lypinator 0:bb348c97df44 347 #define __SXTAB16 __iar_builtin_SXTAB16
lypinator 0:bb348c97df44 348 #define __SMUAD __iar_builtin_SMUAD
lypinator 0:bb348c97df44 349 #define __SMUADX __iar_builtin_SMUADX
lypinator 0:bb348c97df44 350 #define __SMMLA __iar_builtin_SMMLA
lypinator 0:bb348c97df44 351 #define __SMLAD __iar_builtin_SMLAD
lypinator 0:bb348c97df44 352 #define __SMLADX __iar_builtin_SMLADX
lypinator 0:bb348c97df44 353 #define __SMLALD __iar_builtin_SMLALD
lypinator 0:bb348c97df44 354 #define __SMLALDX __iar_builtin_SMLALDX
lypinator 0:bb348c97df44 355 #define __SMUSD __iar_builtin_SMUSD
lypinator 0:bb348c97df44 356 #define __SMUSDX __iar_builtin_SMUSDX
lypinator 0:bb348c97df44 357 #define __SMLSD __iar_builtin_SMLSD
lypinator 0:bb348c97df44 358 #define __SMLSDX __iar_builtin_SMLSDX
lypinator 0:bb348c97df44 359 #define __SMLSLD __iar_builtin_SMLSLD
lypinator 0:bb348c97df44 360 #define __SMLSLDX __iar_builtin_SMLSLDX
lypinator 0:bb348c97df44 361 #define __SEL __iar_builtin_SEL
lypinator 0:bb348c97df44 362 #define __QADD __iar_builtin_QADD
lypinator 0:bb348c97df44 363 #define __QSUB __iar_builtin_QSUB
lypinator 0:bb348c97df44 364 #define __PKHBT __iar_builtin_PKHBT
lypinator 0:bb348c97df44 365 #define __PKHTB __iar_builtin_PKHTB
lypinator 0:bb348c97df44 366
lypinator 0:bb348c97df44 367 #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
lypinator 0:bb348c97df44 368
lypinator 0:bb348c97df44 369 #if !__FPU_PRESENT
lypinator 0:bb348c97df44 370 #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
lypinator 0:bb348c97df44 371 #endif
lypinator 0:bb348c97df44 372
lypinator 0:bb348c97df44 373 #ifdef __INTRINSICS_INCLUDED
lypinator 0:bb348c97df44 374 #error intrinsics.h is already included previously!
lypinator 0:bb348c97df44 375 #endif
lypinator 0:bb348c97df44 376
lypinator 0:bb348c97df44 377 #include <intrinsics.h>
lypinator 0:bb348c97df44 378
lypinator 0:bb348c97df44 379 #if !__FPU_PRESENT
lypinator 0:bb348c97df44 380 #define __get_FPSCR() (0)
lypinator 0:bb348c97df44 381 #endif
lypinator 0:bb348c97df44 382
lypinator 0:bb348c97df44 383 #pragma diag_suppress=Pe940
lypinator 0:bb348c97df44 384 #pragma diag_suppress=Pe177
lypinator 0:bb348c97df44 385
lypinator 0:bb348c97df44 386 #define __enable_irq __enable_interrupt
lypinator 0:bb348c97df44 387 #define __disable_irq __disable_interrupt
lypinator 0:bb348c97df44 388 #define __enable_fault_irq __enable_fiq
lypinator 0:bb348c97df44 389 #define __disable_fault_irq __disable_fiq
lypinator 0:bb348c97df44 390 #define __NOP __no_operation
lypinator 0:bb348c97df44 391
lypinator 0:bb348c97df44 392 #define __get_xPSR __get_PSR
lypinator 0:bb348c97df44 393
lypinator 0:bb348c97df44 394 __IAR_FT void __set_mode(uint32_t mode)
lypinator 0:bb348c97df44 395 {
lypinator 0:bb348c97df44 396 __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
lypinator 0:bb348c97df44 397 }
lypinator 0:bb348c97df44 398
lypinator 0:bb348c97df44 399 __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
lypinator 0:bb348c97df44 400 {
lypinator 0:bb348c97df44 401 return __LDREX((unsigned long *)ptr);
lypinator 0:bb348c97df44 402 }
lypinator 0:bb348c97df44 403
lypinator 0:bb348c97df44 404 __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
lypinator 0:bb348c97df44 405 {
lypinator 0:bb348c97df44 406 return __STREX(value, (unsigned long *)ptr);
lypinator 0:bb348c97df44 407 }
lypinator 0:bb348c97df44 408
lypinator 0:bb348c97df44 409
lypinator 0:bb348c97df44 410 __IAR_FT uint32_t __RRX(uint32_t value)
lypinator 0:bb348c97df44 411 {
lypinator 0:bb348c97df44 412 uint32_t result;
lypinator 0:bb348c97df44 413 __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
lypinator 0:bb348c97df44 414 return(result);
lypinator 0:bb348c97df44 415 }
lypinator 0:bb348c97df44 416
lypinator 0:bb348c97df44 417
lypinator 0:bb348c97df44 418 __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 419 {
lypinator 0:bb348c97df44 420 return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
lypinator 0:bb348c97df44 421 }
lypinator 0:bb348c97df44 422
lypinator 0:bb348c97df44 423 __IAR_FT uint32_t __get_FPEXC(void)
lypinator 0:bb348c97df44 424 {
lypinator 0:bb348c97df44 425 #if (__FPU_PRESENT == 1)
lypinator 0:bb348c97df44 426 uint32_t result;
lypinator 0:bb348c97df44 427 __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
lypinator 0:bb348c97df44 428 return(result);
lypinator 0:bb348c97df44 429 #else
lypinator 0:bb348c97df44 430 return(0);
lypinator 0:bb348c97df44 431 #endif
lypinator 0:bb348c97df44 432 }
lypinator 0:bb348c97df44 433
lypinator 0:bb348c97df44 434 __IAR_FT void __set_FPEXC(uint32_t fpexc)
lypinator 0:bb348c97df44 435 {
lypinator 0:bb348c97df44 436 #if (__FPU_PRESENT == 1)
lypinator 0:bb348c97df44 437 __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
lypinator 0:bb348c97df44 438 #endif
lypinator 0:bb348c97df44 439 }
lypinator 0:bb348c97df44 440
lypinator 0:bb348c97df44 441
lypinator 0:bb348c97df44 442 #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \
lypinator 0:bb348c97df44 443 __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
lypinator 0:bb348c97df44 444 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \
lypinator 0:bb348c97df44 445 __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
lypinator 0:bb348c97df44 446 #define __get_CP64(cp, op1, Rt, CRm) \
lypinator 0:bb348c97df44 447 __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
lypinator 0:bb348c97df44 448 #define __set_CP64(cp, op1, Rt, CRm) \
lypinator 0:bb348c97df44 449 __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
lypinator 0:bb348c97df44 450
lypinator 0:bb348c97df44 451 #include "cmsis_cp15.h"
lypinator 0:bb348c97df44 452
lypinator 0:bb348c97df44 453 #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
lypinator 0:bb348c97df44 454
lypinator 0:bb348c97df44 455 #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
lypinator 0:bb348c97df44 456
lypinator 0:bb348c97df44 457
lypinator 0:bb348c97df44 458 __IAR_FT uint32_t __get_SP_usr(void)
lypinator 0:bb348c97df44 459 {
lypinator 0:bb348c97df44 460 uint32_t cpsr;
lypinator 0:bb348c97df44 461 uint32_t result;
lypinator 0:bb348c97df44 462 __ASM volatile(
lypinator 0:bb348c97df44 463 "MRS %0, cpsr \n"
lypinator 0:bb348c97df44 464 "CPS #0x1F \n" // no effect in USR mode
lypinator 0:bb348c97df44 465 "MOV %1, sp \n"
lypinator 0:bb348c97df44 466 "MSR cpsr_c, %2 \n" // no effect in USR mode
lypinator 0:bb348c97df44 467 "ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
lypinator 0:bb348c97df44 468 );
lypinator 0:bb348c97df44 469 return result;
lypinator 0:bb348c97df44 470 }
lypinator 0:bb348c97df44 471
lypinator 0:bb348c97df44 472 __IAR_FT void __set_SP_usr(uint32_t topOfProcStack)
lypinator 0:bb348c97df44 473 {
lypinator 0:bb348c97df44 474 uint32_t cpsr;
lypinator 0:bb348c97df44 475 __ASM volatile(
lypinator 0:bb348c97df44 476 "MRS %0, cpsr \n"
lypinator 0:bb348c97df44 477 "CPS #0x1F \n" // no effect in USR mode
lypinator 0:bb348c97df44 478 "MOV sp, %1 \n"
lypinator 0:bb348c97df44 479 "MSR cpsr_c, %2 \n" // no effect in USR mode
lypinator 0:bb348c97df44 480 "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
lypinator 0:bb348c97df44 481 );
lypinator 0:bb348c97df44 482 }
lypinator 0:bb348c97df44 483
lypinator 0:bb348c97df44 484 #define __get_mode() (__get_CPSR() & 0x1FU)
lypinator 0:bb348c97df44 485
lypinator 0:bb348c97df44 486 __STATIC_INLINE
lypinator 0:bb348c97df44 487 void __FPU_Enable(void)
lypinator 0:bb348c97df44 488 {
lypinator 0:bb348c97df44 489 __ASM volatile(
lypinator 0:bb348c97df44 490 //Permit access to VFP/NEON, registers by modifying CPACR
lypinator 0:bb348c97df44 491 " MRC p15,0,R1,c1,c0,2 \n"
lypinator 0:bb348c97df44 492 " ORR R1,R1,#0x00F00000 \n"
lypinator 0:bb348c97df44 493 " MCR p15,0,R1,c1,c0,2 \n"
lypinator 0:bb348c97df44 494
lypinator 0:bb348c97df44 495 //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
lypinator 0:bb348c97df44 496 " ISB \n"
lypinator 0:bb348c97df44 497
lypinator 0:bb348c97df44 498 //Enable VFP/NEON
lypinator 0:bb348c97df44 499 " VMRS R1,FPEXC \n"
lypinator 0:bb348c97df44 500 " ORR R1,R1,#0x40000000 \n"
lypinator 0:bb348c97df44 501 " VMSR FPEXC,R1 \n"
lypinator 0:bb348c97df44 502
lypinator 0:bb348c97df44 503 //Initialise VFP/NEON registers to 0
lypinator 0:bb348c97df44 504 " MOV R2,#0 \n"
lypinator 0:bb348c97df44 505
lypinator 0:bb348c97df44 506 //Initialise D16 registers to 0
lypinator 0:bb348c97df44 507 " VMOV D0, R2,R2 \n"
lypinator 0:bb348c97df44 508 " VMOV D1, R2,R2 \n"
lypinator 0:bb348c97df44 509 " VMOV D2, R2,R2 \n"
lypinator 0:bb348c97df44 510 " VMOV D3, R2,R2 \n"
lypinator 0:bb348c97df44 511 " VMOV D4, R2,R2 \n"
lypinator 0:bb348c97df44 512 " VMOV D5, R2,R2 \n"
lypinator 0:bb348c97df44 513 " VMOV D6, R2,R2 \n"
lypinator 0:bb348c97df44 514 " VMOV D7, R2,R2 \n"
lypinator 0:bb348c97df44 515 " VMOV D8, R2,R2 \n"
lypinator 0:bb348c97df44 516 " VMOV D9, R2,R2 \n"
lypinator 0:bb348c97df44 517 " VMOV D10,R2,R2 \n"
lypinator 0:bb348c97df44 518 " VMOV D11,R2,R2 \n"
lypinator 0:bb348c97df44 519 " VMOV D12,R2,R2 \n"
lypinator 0:bb348c97df44 520 " VMOV D13,R2,R2 \n"
lypinator 0:bb348c97df44 521 " VMOV D14,R2,R2 \n"
lypinator 0:bb348c97df44 522 " VMOV D15,R2,R2 \n"
lypinator 0:bb348c97df44 523
lypinator 0:bb348c97df44 524 #ifdef __ARM_ADVANCED_SIMD__
lypinator 0:bb348c97df44 525 //Initialise D32 registers to 0
lypinator 0:bb348c97df44 526 " VMOV D16,R2,R2 \n"
lypinator 0:bb348c97df44 527 " VMOV D17,R2,R2 \n"
lypinator 0:bb348c97df44 528 " VMOV D18,R2,R2 \n"
lypinator 0:bb348c97df44 529 " VMOV D19,R2,R2 \n"
lypinator 0:bb348c97df44 530 " VMOV D20,R2,R2 \n"
lypinator 0:bb348c97df44 531 " VMOV D21,R2,R2 \n"
lypinator 0:bb348c97df44 532 " VMOV D22,R2,R2 \n"
lypinator 0:bb348c97df44 533 " VMOV D23,R2,R2 \n"
lypinator 0:bb348c97df44 534 " VMOV D24,R2,R2 \n"
lypinator 0:bb348c97df44 535 " VMOV D25,R2,R2 \n"
lypinator 0:bb348c97df44 536 " VMOV D26,R2,R2 \n"
lypinator 0:bb348c97df44 537 " VMOV D27,R2,R2 \n"
lypinator 0:bb348c97df44 538 " VMOV D28,R2,R2 \n"
lypinator 0:bb348c97df44 539 " VMOV D29,R2,R2 \n"
lypinator 0:bb348c97df44 540 " VMOV D30,R2,R2 \n"
lypinator 0:bb348c97df44 541 " VMOV D31,R2,R2 \n"
lypinator 0:bb348c97df44 542 #endif
lypinator 0:bb348c97df44 543
lypinator 0:bb348c97df44 544 //Initialise FPSCR to a known state
lypinator 0:bb348c97df44 545 " VMRS R2,FPSCR \n"
lypinator 0:bb348c97df44 546 " MOV32 R3,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
lypinator 0:bb348c97df44 547 " AND R2,R2,R3 \n"
lypinator 0:bb348c97df44 548 " VMSR FPSCR,R2 \n");
lypinator 0:bb348c97df44 549 }
lypinator 0:bb348c97df44 550
lypinator 0:bb348c97df44 551
lypinator 0:bb348c97df44 552
lypinator 0:bb348c97df44 553 #undef __IAR_FT
lypinator 0:bb348c97df44 554 #undef __ICCARM_V8
lypinator 0:bb348c97df44 555
lypinator 0:bb348c97df44 556 #pragma diag_default=Pe940
lypinator 0:bb348c97df44 557 #pragma diag_default=Pe177
lypinator 0:bb348c97df44 558
lypinator 0:bb348c97df44 559 #endif /* __CMSIS_ICCARM_H__ */