Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/cmsis/TARGET_CORTEX_A/cmsis_gcc.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

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lypinator 0:bb348c97df44 1 /**************************************************************************//**
lypinator 0:bb348c97df44 2 * @file cmsis_gcc.h
lypinator 0:bb348c97df44 3 * @brief CMSIS compiler specific macros, functions, instructions
lypinator 0:bb348c97df44 4 * @version V1.0.1
lypinator 0:bb348c97df44 5 * @date 07. Sep 2017
lypinator 0:bb348c97df44 6 ******************************************************************************/
lypinator 0:bb348c97df44 7 /*
lypinator 0:bb348c97df44 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * SPDX-License-Identifier: Apache-2.0
lypinator 0:bb348c97df44 11 *
lypinator 0:bb348c97df44 12 * Licensed under the Apache License, Version 2.0 (the License); you may
lypinator 0:bb348c97df44 13 * not use this file except in compliance with the License.
lypinator 0:bb348c97df44 14 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 15 *
lypinator 0:bb348c97df44 16 * www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 17 *
lypinator 0:bb348c97df44 18 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
lypinator 0:bb348c97df44 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 21 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 22 * limitations under the License.
lypinator 0:bb348c97df44 23 */
lypinator 0:bb348c97df44 24
lypinator 0:bb348c97df44 25 #ifndef __CMSIS_GCC_H
lypinator 0:bb348c97df44 26 #define __CMSIS_GCC_H
lypinator 0:bb348c97df44 27
lypinator 0:bb348c97df44 28 /* ignore some GCC warnings */
lypinator 0:bb348c97df44 29 #pragma GCC diagnostic push
lypinator 0:bb348c97df44 30 #pragma GCC diagnostic ignored "-Wsign-conversion"
lypinator 0:bb348c97df44 31 #pragma GCC diagnostic ignored "-Wconversion"
lypinator 0:bb348c97df44 32 #pragma GCC diagnostic ignored "-Wunused-parameter"
lypinator 0:bb348c97df44 33
lypinator 0:bb348c97df44 34 /* Fallback for __has_builtin */
lypinator 0:bb348c97df44 35 #ifndef __has_builtin
lypinator 0:bb348c97df44 36 #define __has_builtin(x) (0)
lypinator 0:bb348c97df44 37 #endif
lypinator 0:bb348c97df44 38
lypinator 0:bb348c97df44 39 /* CMSIS compiler specific defines */
lypinator 0:bb348c97df44 40 #ifndef __ASM
lypinator 0:bb348c97df44 41 #define __ASM asm
lypinator 0:bb348c97df44 42 #endif
lypinator 0:bb348c97df44 43 #ifndef __INLINE
lypinator 0:bb348c97df44 44 #define __INLINE inline
lypinator 0:bb348c97df44 45 #endif
lypinator 0:bb348c97df44 46 #ifndef __FORCEINLINE
lypinator 0:bb348c97df44 47 #define __FORCEINLINE __attribute__((always_inline))
lypinator 0:bb348c97df44 48 #endif
lypinator 0:bb348c97df44 49 #ifndef __STATIC_INLINE
lypinator 0:bb348c97df44 50 #define __STATIC_INLINE static inline
lypinator 0:bb348c97df44 51 #endif
lypinator 0:bb348c97df44 52 #ifndef __STATIC_FORCEINLINE
lypinator 0:bb348c97df44 53 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
lypinator 0:bb348c97df44 54 #endif
lypinator 0:bb348c97df44 55 #ifndef __NO_RETURN
lypinator 0:bb348c97df44 56 #define __NO_RETURN __attribute__((__noreturn__))
lypinator 0:bb348c97df44 57 #endif
lypinator 0:bb348c97df44 58 #ifndef CMSIS_DEPRECATED
lypinator 0:bb348c97df44 59 #define CMSIS_DEPRECATED __attribute__((deprecated))
lypinator 0:bb348c97df44 60 #endif
lypinator 0:bb348c97df44 61 #ifndef __USED
lypinator 0:bb348c97df44 62 #define __USED __attribute__((used))
lypinator 0:bb348c97df44 63 #endif
lypinator 0:bb348c97df44 64 #ifndef __WEAK
lypinator 0:bb348c97df44 65 #define __WEAK __attribute__((weak))
lypinator 0:bb348c97df44 66 #endif
lypinator 0:bb348c97df44 67 #ifndef __PACKED
lypinator 0:bb348c97df44 68 #define __PACKED __attribute__((packed, aligned(1)))
lypinator 0:bb348c97df44 69 #endif
lypinator 0:bb348c97df44 70 #ifndef __PACKED_STRUCT
lypinator 0:bb348c97df44 71 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
lypinator 0:bb348c97df44 72 #endif
lypinator 0:bb348c97df44 73 #ifndef __UNALIGNED_UINT16_WRITE
lypinator 0:bb348c97df44 74 #pragma GCC diagnostic push
lypinator 0:bb348c97df44 75 #pragma GCC diagnostic ignored "-Wpacked"
lypinator 0:bb348c97df44 76 /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
lypinator 0:bb348c97df44 77 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
lypinator 0:bb348c97df44 78 #pragma GCC diagnostic pop
lypinator 0:bb348c97df44 79 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
lypinator 0:bb348c97df44 80 #endif
lypinator 0:bb348c97df44 81 #ifndef __UNALIGNED_UINT16_READ
lypinator 0:bb348c97df44 82 #pragma GCC diagnostic push
lypinator 0:bb348c97df44 83 #pragma GCC diagnostic ignored "-Wpacked"
lypinator 0:bb348c97df44 84 /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
lypinator 0:bb348c97df44 85 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
lypinator 0:bb348c97df44 86 #pragma GCC diagnostic pop
lypinator 0:bb348c97df44 87 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
lypinator 0:bb348c97df44 88 #endif
lypinator 0:bb348c97df44 89 #ifndef __UNALIGNED_UINT32_WRITE
lypinator 0:bb348c97df44 90 #pragma GCC diagnostic push
lypinator 0:bb348c97df44 91 #pragma GCC diagnostic ignored "-Wpacked"
lypinator 0:bb348c97df44 92 /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
lypinator 0:bb348c97df44 93 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
lypinator 0:bb348c97df44 94 #pragma GCC diagnostic pop
lypinator 0:bb348c97df44 95 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
lypinator 0:bb348c97df44 96 #endif
lypinator 0:bb348c97df44 97 #ifndef __UNALIGNED_UINT32_READ
lypinator 0:bb348c97df44 98 #pragma GCC diagnostic push
lypinator 0:bb348c97df44 99 #pragma GCC diagnostic ignored "-Wpacked"
lypinator 0:bb348c97df44 100 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
lypinator 0:bb348c97df44 101 #pragma GCC diagnostic pop
lypinator 0:bb348c97df44 102 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
lypinator 0:bb348c97df44 103 #endif
lypinator 0:bb348c97df44 104 #ifndef __ALIGNED
lypinator 0:bb348c97df44 105 #define __ALIGNED(x) __attribute__((aligned(x)))
lypinator 0:bb348c97df44 106 #endif
lypinator 0:bb348c97df44 107
lypinator 0:bb348c97df44 108 /* ########################## Core Instruction Access ######################### */
lypinator 0:bb348c97df44 109 /**
lypinator 0:bb348c97df44 110 \brief No Operation
lypinator 0:bb348c97df44 111 */
lypinator 0:bb348c97df44 112 #define __NOP() __ASM volatile ("nop")
lypinator 0:bb348c97df44 113
lypinator 0:bb348c97df44 114 /**
lypinator 0:bb348c97df44 115 \brief Wait For Interrupt
lypinator 0:bb348c97df44 116 */
lypinator 0:bb348c97df44 117 #define __WFI() __ASM volatile ("wfi")
lypinator 0:bb348c97df44 118
lypinator 0:bb348c97df44 119 /**
lypinator 0:bb348c97df44 120 \brief Wait For Event
lypinator 0:bb348c97df44 121 */
lypinator 0:bb348c97df44 122 #define __WFE() __ASM volatile ("wfe")
lypinator 0:bb348c97df44 123
lypinator 0:bb348c97df44 124 /**
lypinator 0:bb348c97df44 125 \brief Send Event
lypinator 0:bb348c97df44 126 */
lypinator 0:bb348c97df44 127 #define __SEV() __ASM volatile ("sev")
lypinator 0:bb348c97df44 128
lypinator 0:bb348c97df44 129 /**
lypinator 0:bb348c97df44 130 \brief Instruction Synchronization Barrier
lypinator 0:bb348c97df44 131 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
lypinator 0:bb348c97df44 132 so that all instructions following the ISB are fetched from cache or memory,
lypinator 0:bb348c97df44 133 after the instruction has been completed.
lypinator 0:bb348c97df44 134 */
lypinator 0:bb348c97df44 135 __STATIC_FORCEINLINE void __ISB(void)
lypinator 0:bb348c97df44 136 {
lypinator 0:bb348c97df44 137 __ASM volatile ("isb 0xF":::"memory");
lypinator 0:bb348c97df44 138 }
lypinator 0:bb348c97df44 139
lypinator 0:bb348c97df44 140
lypinator 0:bb348c97df44 141 /**
lypinator 0:bb348c97df44 142 \brief Data Synchronization Barrier
lypinator 0:bb348c97df44 143 \details Acts as a special kind of Data Memory Barrier.
lypinator 0:bb348c97df44 144 It completes when all explicit memory accesses before this instruction complete.
lypinator 0:bb348c97df44 145 */
lypinator 0:bb348c97df44 146 __STATIC_FORCEINLINE void __DSB(void)
lypinator 0:bb348c97df44 147 {
lypinator 0:bb348c97df44 148 __ASM volatile ("dsb 0xF":::"memory");
lypinator 0:bb348c97df44 149 }
lypinator 0:bb348c97df44 150
lypinator 0:bb348c97df44 151 /**
lypinator 0:bb348c97df44 152 \brief Data Memory Barrier
lypinator 0:bb348c97df44 153 \details Ensures the apparent order of the explicit memory operations before
lypinator 0:bb348c97df44 154 and after the instruction, without ensuring their completion.
lypinator 0:bb348c97df44 155 */
lypinator 0:bb348c97df44 156 __STATIC_FORCEINLINE void __DMB(void)
lypinator 0:bb348c97df44 157 {
lypinator 0:bb348c97df44 158 __ASM volatile ("dmb 0xF":::"memory");
lypinator 0:bb348c97df44 159 }
lypinator 0:bb348c97df44 160
lypinator 0:bb348c97df44 161 /**
lypinator 0:bb348c97df44 162 \brief Reverse byte order (32 bit)
lypinator 0:bb348c97df44 163 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
lypinator 0:bb348c97df44 164 \param [in] value Value to reverse
lypinator 0:bb348c97df44 165 \return Reversed value
lypinator 0:bb348c97df44 166 */
lypinator 0:bb348c97df44 167 __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
lypinator 0:bb348c97df44 168 {
lypinator 0:bb348c97df44 169 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
lypinator 0:bb348c97df44 170 return __builtin_bswap32(value);
lypinator 0:bb348c97df44 171 #else
lypinator 0:bb348c97df44 172 uint32_t result;
lypinator 0:bb348c97df44 173
lypinator 0:bb348c97df44 174 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
lypinator 0:bb348c97df44 175 return result;
lypinator 0:bb348c97df44 176 #endif
lypinator 0:bb348c97df44 177 }
lypinator 0:bb348c97df44 178
lypinator 0:bb348c97df44 179 /**
lypinator 0:bb348c97df44 180 \brief Reverse byte order (16 bit)
lypinator 0:bb348c97df44 181 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
lypinator 0:bb348c97df44 182 \param [in] value Value to reverse
lypinator 0:bb348c97df44 183 \return Reversed value
lypinator 0:bb348c97df44 184 */
lypinator 0:bb348c97df44 185 #ifndef __NO_EMBEDDED_ASM
lypinator 0:bb348c97df44 186 __attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
lypinator 0:bb348c97df44 187 {
lypinator 0:bb348c97df44 188 uint32_t result;
lypinator 0:bb348c97df44 189 __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
lypinator 0:bb348c97df44 190 return result;
lypinator 0:bb348c97df44 191 }
lypinator 0:bb348c97df44 192 #endif
lypinator 0:bb348c97df44 193
lypinator 0:bb348c97df44 194 /**
lypinator 0:bb348c97df44 195 \brief Reverse byte order (16 bit)
lypinator 0:bb348c97df44 196 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
lypinator 0:bb348c97df44 197 \param [in] value Value to reverse
lypinator 0:bb348c97df44 198 \return Reversed value
lypinator 0:bb348c97df44 199 */
lypinator 0:bb348c97df44 200 __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
lypinator 0:bb348c97df44 201 {
lypinator 0:bb348c97df44 202 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
lypinator 0:bb348c97df44 203 return (int16_t)__builtin_bswap16(value);
lypinator 0:bb348c97df44 204 #else
lypinator 0:bb348c97df44 205 int16_t result;
lypinator 0:bb348c97df44 206
lypinator 0:bb348c97df44 207 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
lypinator 0:bb348c97df44 208 return result;
lypinator 0:bb348c97df44 209 #endif
lypinator 0:bb348c97df44 210 }
lypinator 0:bb348c97df44 211
lypinator 0:bb348c97df44 212 /**
lypinator 0:bb348c97df44 213 \brief Rotate Right in unsigned value (32 bit)
lypinator 0:bb348c97df44 214 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
lypinator 0:bb348c97df44 215 \param [in] op1 Value to rotate
lypinator 0:bb348c97df44 216 \param [in] op2 Number of Bits to rotate
lypinator 0:bb348c97df44 217 \return Rotated value
lypinator 0:bb348c97df44 218 */
lypinator 0:bb348c97df44 219 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
lypinator 0:bb348c97df44 220 {
lypinator 0:bb348c97df44 221 op2 %= 32U;
lypinator 0:bb348c97df44 222 if (op2 == 0U) {
lypinator 0:bb348c97df44 223 return op1;
lypinator 0:bb348c97df44 224 }
lypinator 0:bb348c97df44 225 return (op1 >> op2) | (op1 << (32U - op2));
lypinator 0:bb348c97df44 226 }
lypinator 0:bb348c97df44 227
lypinator 0:bb348c97df44 228
lypinator 0:bb348c97df44 229 /**
lypinator 0:bb348c97df44 230 \brief Breakpoint
lypinator 0:bb348c97df44 231 \param [in] value is ignored by the processor.
lypinator 0:bb348c97df44 232 If required, a debugger can use it to store additional information about the breakpoint.
lypinator 0:bb348c97df44 233 */
lypinator 0:bb348c97df44 234 #define __BKPT(value) __ASM volatile ("bkpt "#value)
lypinator 0:bb348c97df44 235
lypinator 0:bb348c97df44 236 /**
lypinator 0:bb348c97df44 237 \brief Reverse bit order of value
lypinator 0:bb348c97df44 238 \details Reverses the bit order of the given value.
lypinator 0:bb348c97df44 239 \param [in] value Value to reverse
lypinator 0:bb348c97df44 240 \return Reversed value
lypinator 0:bb348c97df44 241 */
lypinator 0:bb348c97df44 242 __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
lypinator 0:bb348c97df44 243 {
lypinator 0:bb348c97df44 244 uint32_t result;
lypinator 0:bb348c97df44 245
lypinator 0:bb348c97df44 246 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
lypinator 0:bb348c97df44 247 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
lypinator 0:bb348c97df44 248 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
lypinator 0:bb348c97df44 249 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
lypinator 0:bb348c97df44 250 #else
lypinator 0:bb348c97df44 251 int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
lypinator 0:bb348c97df44 252
lypinator 0:bb348c97df44 253 result = value; /* r will be reversed bits of v; first get LSB of v */
lypinator 0:bb348c97df44 254 for (value >>= 1U; value; value >>= 1U)
lypinator 0:bb348c97df44 255 {
lypinator 0:bb348c97df44 256 result <<= 1U;
lypinator 0:bb348c97df44 257 result |= value & 1U;
lypinator 0:bb348c97df44 258 s--;
lypinator 0:bb348c97df44 259 }
lypinator 0:bb348c97df44 260 result <<= s; /* shift when v's highest bits are zero */
lypinator 0:bb348c97df44 261 #endif
lypinator 0:bb348c97df44 262 return result;
lypinator 0:bb348c97df44 263 }
lypinator 0:bb348c97df44 264
lypinator 0:bb348c97df44 265 /**
lypinator 0:bb348c97df44 266 \brief Count leading zeros
lypinator 0:bb348c97df44 267 \param [in] value Value to count the leading zeros
lypinator 0:bb348c97df44 268 \return number of leading zeros in value
lypinator 0:bb348c97df44 269 */
lypinator 0:bb348c97df44 270 #define __CLZ (uint8_t)__builtin_clz
lypinator 0:bb348c97df44 271
lypinator 0:bb348c97df44 272 /**
lypinator 0:bb348c97df44 273 \brief LDR Exclusive (8 bit)
lypinator 0:bb348c97df44 274 \details Executes a exclusive LDR instruction for 8 bit value.
lypinator 0:bb348c97df44 275 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 276 \return value of type uint8_t at (*ptr)
lypinator 0:bb348c97df44 277 */
lypinator 0:bb348c97df44 278 __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
lypinator 0:bb348c97df44 279 {
lypinator 0:bb348c97df44 280 uint32_t result;
lypinator 0:bb348c97df44 281
lypinator 0:bb348c97df44 282 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
lypinator 0:bb348c97df44 283 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
lypinator 0:bb348c97df44 284 #else
lypinator 0:bb348c97df44 285 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
lypinator 0:bb348c97df44 286 accepted by assembler. So has to use following less efficient pattern.
lypinator 0:bb348c97df44 287 */
lypinator 0:bb348c97df44 288 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
lypinator 0:bb348c97df44 289 #endif
lypinator 0:bb348c97df44 290 return ((uint8_t) result); /* Add explicit type cast here */
lypinator 0:bb348c97df44 291 }
lypinator 0:bb348c97df44 292
lypinator 0:bb348c97df44 293
lypinator 0:bb348c97df44 294 /**
lypinator 0:bb348c97df44 295 \brief LDR Exclusive (16 bit)
lypinator 0:bb348c97df44 296 \details Executes a exclusive LDR instruction for 16 bit values.
lypinator 0:bb348c97df44 297 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 298 \return value of type uint16_t at (*ptr)
lypinator 0:bb348c97df44 299 */
lypinator 0:bb348c97df44 300 __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
lypinator 0:bb348c97df44 301 {
lypinator 0:bb348c97df44 302 uint32_t result;
lypinator 0:bb348c97df44 303
lypinator 0:bb348c97df44 304 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
lypinator 0:bb348c97df44 305 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
lypinator 0:bb348c97df44 306 #else
lypinator 0:bb348c97df44 307 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
lypinator 0:bb348c97df44 308 accepted by assembler. So has to use following less efficient pattern.
lypinator 0:bb348c97df44 309 */
lypinator 0:bb348c97df44 310 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
lypinator 0:bb348c97df44 311 #endif
lypinator 0:bb348c97df44 312 return ((uint16_t) result); /* Add explicit type cast here */
lypinator 0:bb348c97df44 313 }
lypinator 0:bb348c97df44 314
lypinator 0:bb348c97df44 315
lypinator 0:bb348c97df44 316 /**
lypinator 0:bb348c97df44 317 \brief LDR Exclusive (32 bit)
lypinator 0:bb348c97df44 318 \details Executes a exclusive LDR instruction for 32 bit values.
lypinator 0:bb348c97df44 319 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 320 \return value of type uint32_t at (*ptr)
lypinator 0:bb348c97df44 321 */
lypinator 0:bb348c97df44 322 __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
lypinator 0:bb348c97df44 323 {
lypinator 0:bb348c97df44 324 uint32_t result;
lypinator 0:bb348c97df44 325
lypinator 0:bb348c97df44 326 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
lypinator 0:bb348c97df44 327 return(result);
lypinator 0:bb348c97df44 328 }
lypinator 0:bb348c97df44 329
lypinator 0:bb348c97df44 330
lypinator 0:bb348c97df44 331 /**
lypinator 0:bb348c97df44 332 \brief STR Exclusive (8 bit)
lypinator 0:bb348c97df44 333 \details Executes a exclusive STR instruction for 8 bit values.
lypinator 0:bb348c97df44 334 \param [in] value Value to store
lypinator 0:bb348c97df44 335 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 336 \return 0 Function succeeded
lypinator 0:bb348c97df44 337 \return 1 Function failed
lypinator 0:bb348c97df44 338 */
lypinator 0:bb348c97df44 339 __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
lypinator 0:bb348c97df44 340 {
lypinator 0:bb348c97df44 341 uint32_t result;
lypinator 0:bb348c97df44 342
lypinator 0:bb348c97df44 343 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
lypinator 0:bb348c97df44 344 return(result);
lypinator 0:bb348c97df44 345 }
lypinator 0:bb348c97df44 346
lypinator 0:bb348c97df44 347
lypinator 0:bb348c97df44 348 /**
lypinator 0:bb348c97df44 349 \brief STR Exclusive (16 bit)
lypinator 0:bb348c97df44 350 \details Executes a exclusive STR instruction for 16 bit values.
lypinator 0:bb348c97df44 351 \param [in] value Value to store
lypinator 0:bb348c97df44 352 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 353 \return 0 Function succeeded
lypinator 0:bb348c97df44 354 \return 1 Function failed
lypinator 0:bb348c97df44 355 */
lypinator 0:bb348c97df44 356 __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
lypinator 0:bb348c97df44 357 {
lypinator 0:bb348c97df44 358 uint32_t result;
lypinator 0:bb348c97df44 359
lypinator 0:bb348c97df44 360 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
lypinator 0:bb348c97df44 361 return(result);
lypinator 0:bb348c97df44 362 }
lypinator 0:bb348c97df44 363
lypinator 0:bb348c97df44 364
lypinator 0:bb348c97df44 365 /**
lypinator 0:bb348c97df44 366 \brief STR Exclusive (32 bit)
lypinator 0:bb348c97df44 367 \details Executes a exclusive STR instruction for 32 bit values.
lypinator 0:bb348c97df44 368 \param [in] value Value to store
lypinator 0:bb348c97df44 369 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 370 \return 0 Function succeeded
lypinator 0:bb348c97df44 371 \return 1 Function failed
lypinator 0:bb348c97df44 372 */
lypinator 0:bb348c97df44 373 __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
lypinator 0:bb348c97df44 374 {
lypinator 0:bb348c97df44 375 uint32_t result;
lypinator 0:bb348c97df44 376
lypinator 0:bb348c97df44 377 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
lypinator 0:bb348c97df44 378 return(result);
lypinator 0:bb348c97df44 379 }
lypinator 0:bb348c97df44 380
lypinator 0:bb348c97df44 381
lypinator 0:bb348c97df44 382 /**
lypinator 0:bb348c97df44 383 \brief Remove the exclusive lock
lypinator 0:bb348c97df44 384 \details Removes the exclusive lock which is created by LDREX.
lypinator 0:bb348c97df44 385 */
lypinator 0:bb348c97df44 386 __STATIC_FORCEINLINE void __CLREX(void)
lypinator 0:bb348c97df44 387 {
lypinator 0:bb348c97df44 388 __ASM volatile ("clrex" ::: "memory");
lypinator 0:bb348c97df44 389 }
lypinator 0:bb348c97df44 390
lypinator 0:bb348c97df44 391 /**
lypinator 0:bb348c97df44 392 \brief Signed Saturate
lypinator 0:bb348c97df44 393 \details Saturates a signed value.
lypinator 0:bb348c97df44 394 \param [in] value Value to be saturated
lypinator 0:bb348c97df44 395 \param [in] sat Bit position to saturate to (1..32)
lypinator 0:bb348c97df44 396 \return Saturated value
lypinator 0:bb348c97df44 397 */
lypinator 0:bb348c97df44 398 #define __SSAT(ARG1,ARG2) \
lypinator 0:bb348c97df44 399 __extension__ \
lypinator 0:bb348c97df44 400 ({ \
lypinator 0:bb348c97df44 401 int32_t __RES, __ARG1 = (ARG1); \
lypinator 0:bb348c97df44 402 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
lypinator 0:bb348c97df44 403 __RES; \
lypinator 0:bb348c97df44 404 })
lypinator 0:bb348c97df44 405
lypinator 0:bb348c97df44 406
lypinator 0:bb348c97df44 407 /**
lypinator 0:bb348c97df44 408 \brief Unsigned Saturate
lypinator 0:bb348c97df44 409 \details Saturates an unsigned value.
lypinator 0:bb348c97df44 410 \param [in] value Value to be saturated
lypinator 0:bb348c97df44 411 \param [in] sat Bit position to saturate to (0..31)
lypinator 0:bb348c97df44 412 \return Saturated value
lypinator 0:bb348c97df44 413 */
lypinator 0:bb348c97df44 414 #define __USAT(ARG1,ARG2) \
lypinator 0:bb348c97df44 415 __extension__ \
lypinator 0:bb348c97df44 416 ({ \
lypinator 0:bb348c97df44 417 uint32_t __RES, __ARG1 = (ARG1); \
lypinator 0:bb348c97df44 418 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
lypinator 0:bb348c97df44 419 __RES; \
lypinator 0:bb348c97df44 420 })
lypinator 0:bb348c97df44 421
lypinator 0:bb348c97df44 422 /* ########################### Core Function Access ########################### */
lypinator 0:bb348c97df44 423
lypinator 0:bb348c97df44 424 /**
lypinator 0:bb348c97df44 425 \brief Enable IRQ Interrupts
lypinator 0:bb348c97df44 426 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
lypinator 0:bb348c97df44 427 Can only be executed in Privileged modes.
lypinator 0:bb348c97df44 428 */
lypinator 0:bb348c97df44 429 __STATIC_FORCEINLINE void __enable_irq(void)
lypinator 0:bb348c97df44 430 {
lypinator 0:bb348c97df44 431 __ASM volatile ("cpsie i" : : : "memory");
lypinator 0:bb348c97df44 432 }
lypinator 0:bb348c97df44 433
lypinator 0:bb348c97df44 434 /**
lypinator 0:bb348c97df44 435 \brief Disable IRQ Interrupts
lypinator 0:bb348c97df44 436 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
lypinator 0:bb348c97df44 437 Can only be executed in Privileged modes.
lypinator 0:bb348c97df44 438 */
lypinator 0:bb348c97df44 439 __STATIC_FORCEINLINE void __disable_irq(void)
lypinator 0:bb348c97df44 440 {
lypinator 0:bb348c97df44 441 __ASM volatile ("cpsid i" : : : "memory");
lypinator 0:bb348c97df44 442 }
lypinator 0:bb348c97df44 443
lypinator 0:bb348c97df44 444 /**
lypinator 0:bb348c97df44 445 \brief Get FPSCR
lypinator 0:bb348c97df44 446 \details Returns the current value of the Floating Point Status/Control register.
lypinator 0:bb348c97df44 447 \return Floating Point Status/Control register value
lypinator 0:bb348c97df44 448 */
lypinator 0:bb348c97df44 449 __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
lypinator 0:bb348c97df44 450 {
lypinator 0:bb348c97df44 451 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
lypinator 0:bb348c97df44 452 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
lypinator 0:bb348c97df44 453 #if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
lypinator 0:bb348c97df44 454 /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
lypinator 0:bb348c97df44 455 return __builtin_arm_get_fpscr();
lypinator 0:bb348c97df44 456 #else
lypinator 0:bb348c97df44 457 uint32_t result;
lypinator 0:bb348c97df44 458
lypinator 0:bb348c97df44 459 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
lypinator 0:bb348c97df44 460 return(result);
lypinator 0:bb348c97df44 461 #endif
lypinator 0:bb348c97df44 462 #else
lypinator 0:bb348c97df44 463 return(0U);
lypinator 0:bb348c97df44 464 #endif
lypinator 0:bb348c97df44 465 }
lypinator 0:bb348c97df44 466
lypinator 0:bb348c97df44 467 /**
lypinator 0:bb348c97df44 468 \brief Set FPSCR
lypinator 0:bb348c97df44 469 \details Assigns the given value to the Floating Point Status/Control register.
lypinator 0:bb348c97df44 470 \param [in] fpscr Floating Point Status/Control value to set
lypinator 0:bb348c97df44 471 */
lypinator 0:bb348c97df44 472 __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
lypinator 0:bb348c97df44 473 {
lypinator 0:bb348c97df44 474 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
lypinator 0:bb348c97df44 475 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
lypinator 0:bb348c97df44 476 #if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
lypinator 0:bb348c97df44 477 /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
lypinator 0:bb348c97df44 478 __builtin_arm_set_fpscr(fpscr);
lypinator 0:bb348c97df44 479 #else
lypinator 0:bb348c97df44 480 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
lypinator 0:bb348c97df44 481 #endif
lypinator 0:bb348c97df44 482 #else
lypinator 0:bb348c97df44 483 (void)fpscr;
lypinator 0:bb348c97df44 484 #endif
lypinator 0:bb348c97df44 485 }
lypinator 0:bb348c97df44 486
lypinator 0:bb348c97df44 487 /** \brief Get CPSR Register
lypinator 0:bb348c97df44 488 \return CPSR Register value
lypinator 0:bb348c97df44 489 */
lypinator 0:bb348c97df44 490 __STATIC_FORCEINLINE uint32_t __get_CPSR(void)
lypinator 0:bb348c97df44 491 {
lypinator 0:bb348c97df44 492 uint32_t result;
lypinator 0:bb348c97df44 493 __ASM volatile("MRS %0, cpsr" : "=r" (result) );
lypinator 0:bb348c97df44 494 return(result);
lypinator 0:bb348c97df44 495 }
lypinator 0:bb348c97df44 496
lypinator 0:bb348c97df44 497 /** \brief Set CPSR Register
lypinator 0:bb348c97df44 498 \param [in] cpsr CPSR value to set
lypinator 0:bb348c97df44 499 */
lypinator 0:bb348c97df44 500 __STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
lypinator 0:bb348c97df44 501 {
lypinator 0:bb348c97df44 502 __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
lypinator 0:bb348c97df44 503 }
lypinator 0:bb348c97df44 504
lypinator 0:bb348c97df44 505 /** \brief Get Mode
lypinator 0:bb348c97df44 506 \return Processor Mode
lypinator 0:bb348c97df44 507 */
lypinator 0:bb348c97df44 508 __STATIC_FORCEINLINE uint32_t __get_mode(void)
lypinator 0:bb348c97df44 509 {
lypinator 0:bb348c97df44 510 return (__get_CPSR() & 0x1FU);
lypinator 0:bb348c97df44 511 }
lypinator 0:bb348c97df44 512
lypinator 0:bb348c97df44 513 /** \brief Set Mode
lypinator 0:bb348c97df44 514 \param [in] mode Mode value to set
lypinator 0:bb348c97df44 515 */
lypinator 0:bb348c97df44 516 __STATIC_FORCEINLINE void __set_mode(uint32_t mode)
lypinator 0:bb348c97df44 517 {
lypinator 0:bb348c97df44 518 __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
lypinator 0:bb348c97df44 519 }
lypinator 0:bb348c97df44 520
lypinator 0:bb348c97df44 521 /** \brief Get Stack Pointer
lypinator 0:bb348c97df44 522 \return Stack Pointer value
lypinator 0:bb348c97df44 523 */
lypinator 0:bb348c97df44 524 __STATIC_FORCEINLINE uint32_t __get_SP(void)
lypinator 0:bb348c97df44 525 {
lypinator 0:bb348c97df44 526 uint32_t result;
lypinator 0:bb348c97df44 527 __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
lypinator 0:bb348c97df44 528 return result;
lypinator 0:bb348c97df44 529 }
lypinator 0:bb348c97df44 530
lypinator 0:bb348c97df44 531 /** \brief Set Stack Pointer
lypinator 0:bb348c97df44 532 \param [in] stack Stack Pointer value to set
lypinator 0:bb348c97df44 533 */
lypinator 0:bb348c97df44 534 __STATIC_FORCEINLINE void __set_SP(uint32_t stack)
lypinator 0:bb348c97df44 535 {
lypinator 0:bb348c97df44 536 __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
lypinator 0:bb348c97df44 537 }
lypinator 0:bb348c97df44 538
lypinator 0:bb348c97df44 539 /** \brief Get USR/SYS Stack Pointer
lypinator 0:bb348c97df44 540 \return USR/SYS Stack Pointer value
lypinator 0:bb348c97df44 541 */
lypinator 0:bb348c97df44 542 __STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
lypinator 0:bb348c97df44 543 {
lypinator 0:bb348c97df44 544 uint32_t cpsr = __get_CPSR();
lypinator 0:bb348c97df44 545 uint32_t result;
lypinator 0:bb348c97df44 546 __ASM volatile(
lypinator 0:bb348c97df44 547 "CPS #0x1F \n"
lypinator 0:bb348c97df44 548 "MOV %0, sp " : "=r"(result) : : "memory"
lypinator 0:bb348c97df44 549 );
lypinator 0:bb348c97df44 550 __set_CPSR(cpsr);
lypinator 0:bb348c97df44 551 __ISB();
lypinator 0:bb348c97df44 552 return result;
lypinator 0:bb348c97df44 553 }
lypinator 0:bb348c97df44 554
lypinator 0:bb348c97df44 555 /** \brief Set USR/SYS Stack Pointer
lypinator 0:bb348c97df44 556 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
lypinator 0:bb348c97df44 557 */
lypinator 0:bb348c97df44 558 __STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
lypinator 0:bb348c97df44 559 {
lypinator 0:bb348c97df44 560 uint32_t cpsr = __get_CPSR();
lypinator 0:bb348c97df44 561 __ASM volatile(
lypinator 0:bb348c97df44 562 "CPS #0x1F \n"
lypinator 0:bb348c97df44 563 "MOV sp, %0 " : : "r" (topOfProcStack) : "memory"
lypinator 0:bb348c97df44 564 );
lypinator 0:bb348c97df44 565 __set_CPSR(cpsr);
lypinator 0:bb348c97df44 566 __ISB();
lypinator 0:bb348c97df44 567 }
lypinator 0:bb348c97df44 568
lypinator 0:bb348c97df44 569 /** \brief Get FPEXC
lypinator 0:bb348c97df44 570 \return Floating Point Exception Control register value
lypinator 0:bb348c97df44 571 */
lypinator 0:bb348c97df44 572 __STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
lypinator 0:bb348c97df44 573 {
lypinator 0:bb348c97df44 574 #if (__FPU_PRESENT == 1)
lypinator 0:bb348c97df44 575 uint32_t result;
lypinator 0:bb348c97df44 576 __ASM volatile("VMRS %0, fpexc" : "=r" (result) );
lypinator 0:bb348c97df44 577 return(result);
lypinator 0:bb348c97df44 578 #else
lypinator 0:bb348c97df44 579 return(0);
lypinator 0:bb348c97df44 580 #endif
lypinator 0:bb348c97df44 581 }
lypinator 0:bb348c97df44 582
lypinator 0:bb348c97df44 583 /** \brief Set FPEXC
lypinator 0:bb348c97df44 584 \param [in] fpexc Floating Point Exception Control value to set
lypinator 0:bb348c97df44 585 */
lypinator 0:bb348c97df44 586 __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
lypinator 0:bb348c97df44 587 {
lypinator 0:bb348c97df44 588 #if (__FPU_PRESENT == 1)
lypinator 0:bb348c97df44 589 __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
lypinator 0:bb348c97df44 590 #endif
lypinator 0:bb348c97df44 591 }
lypinator 0:bb348c97df44 592
lypinator 0:bb348c97df44 593 /*
lypinator 0:bb348c97df44 594 * Include common core functions to access Coprocessor 15 registers
lypinator 0:bb348c97df44 595 */
lypinator 0:bb348c97df44 596
lypinator 0:bb348c97df44 597 #define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
lypinator 0:bb348c97df44 598 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
lypinator 0:bb348c97df44 599 #define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
lypinator 0:bb348c97df44 600 #define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
lypinator 0:bb348c97df44 601
lypinator 0:bb348c97df44 602 #include "cmsis_cp15.h"
lypinator 0:bb348c97df44 603
lypinator 0:bb348c97df44 604 /** \brief Enable Floating Point Unit
lypinator 0:bb348c97df44 605
lypinator 0:bb348c97df44 606 Critical section, called from undef handler, so systick is disabled
lypinator 0:bb348c97df44 607 */
lypinator 0:bb348c97df44 608 __STATIC_INLINE void __FPU_Enable(void)
lypinator 0:bb348c97df44 609 {
lypinator 0:bb348c97df44 610 __ASM volatile(
lypinator 0:bb348c97df44 611 //Permit access to VFP/NEON, registers by modifying CPACR
lypinator 0:bb348c97df44 612 " MRC p15,0,R1,c1,c0,2 \n"
lypinator 0:bb348c97df44 613 " ORR R1,R1,#0x00F00000 \n"
lypinator 0:bb348c97df44 614 " MCR p15,0,R1,c1,c0,2 \n"
lypinator 0:bb348c97df44 615
lypinator 0:bb348c97df44 616 //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
lypinator 0:bb348c97df44 617 " ISB \n"
lypinator 0:bb348c97df44 618
lypinator 0:bb348c97df44 619 //Enable VFP/NEON
lypinator 0:bb348c97df44 620 " VMRS R1,FPEXC \n"
lypinator 0:bb348c97df44 621 " ORR R1,R1,#0x40000000 \n"
lypinator 0:bb348c97df44 622 " VMSR FPEXC,R1 \n"
lypinator 0:bb348c97df44 623
lypinator 0:bb348c97df44 624 //Initialise VFP/NEON registers to 0
lypinator 0:bb348c97df44 625 " MOV R2,#0 \n"
lypinator 0:bb348c97df44 626
lypinator 0:bb348c97df44 627 //Initialise D16 registers to 0
lypinator 0:bb348c97df44 628 " VMOV D0, R2,R2 \n"
lypinator 0:bb348c97df44 629 " VMOV D1, R2,R2 \n"
lypinator 0:bb348c97df44 630 " VMOV D2, R2,R2 \n"
lypinator 0:bb348c97df44 631 " VMOV D3, R2,R2 \n"
lypinator 0:bb348c97df44 632 " VMOV D4, R2,R2 \n"
lypinator 0:bb348c97df44 633 " VMOV D5, R2,R2 \n"
lypinator 0:bb348c97df44 634 " VMOV D6, R2,R2 \n"
lypinator 0:bb348c97df44 635 " VMOV D7, R2,R2 \n"
lypinator 0:bb348c97df44 636 " VMOV D8, R2,R2 \n"
lypinator 0:bb348c97df44 637 " VMOV D9, R2,R2 \n"
lypinator 0:bb348c97df44 638 " VMOV D10,R2,R2 \n"
lypinator 0:bb348c97df44 639 " VMOV D11,R2,R2 \n"
lypinator 0:bb348c97df44 640 " VMOV D12,R2,R2 \n"
lypinator 0:bb348c97df44 641 " VMOV D13,R2,R2 \n"
lypinator 0:bb348c97df44 642 " VMOV D14,R2,R2 \n"
lypinator 0:bb348c97df44 643 " VMOV D15,R2,R2 \n"
lypinator 0:bb348c97df44 644
lypinator 0:bb348c97df44 645 #if (defined(__ARM_NEON) && (__ARM_NEON == 1))
lypinator 0:bb348c97df44 646 //Initialise D32 registers to 0
lypinator 0:bb348c97df44 647 " VMOV D16,R2,R2 \n"
lypinator 0:bb348c97df44 648 " VMOV D17,R2,R2 \n"
lypinator 0:bb348c97df44 649 " VMOV D18,R2,R2 \n"
lypinator 0:bb348c97df44 650 " VMOV D19,R2,R2 \n"
lypinator 0:bb348c97df44 651 " VMOV D20,R2,R2 \n"
lypinator 0:bb348c97df44 652 " VMOV D21,R2,R2 \n"
lypinator 0:bb348c97df44 653 " VMOV D22,R2,R2 \n"
lypinator 0:bb348c97df44 654 " VMOV D23,R2,R2 \n"
lypinator 0:bb348c97df44 655 " VMOV D24,R2,R2 \n"
lypinator 0:bb348c97df44 656 " VMOV D25,R2,R2 \n"
lypinator 0:bb348c97df44 657 " VMOV D26,R2,R2 \n"
lypinator 0:bb348c97df44 658 " VMOV D27,R2,R2 \n"
lypinator 0:bb348c97df44 659 " VMOV D28,R2,R2 \n"
lypinator 0:bb348c97df44 660 " VMOV D29,R2,R2 \n"
lypinator 0:bb348c97df44 661 " VMOV D30,R2,R2 \n"
lypinator 0:bb348c97df44 662 " VMOV D31,R2,R2 \n"
lypinator 0:bb348c97df44 663 #endif
lypinator 0:bb348c97df44 664
lypinator 0:bb348c97df44 665 //Initialise FPSCR to a known state
lypinator 0:bb348c97df44 666 " VMRS R2,FPSCR \n"
lypinator 0:bb348c97df44 667 " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
lypinator 0:bb348c97df44 668 " AND R2,R2,R3 \n"
lypinator 0:bb348c97df44 669 " VMSR FPSCR,R2 "
lypinator 0:bb348c97df44 670 );
lypinator 0:bb348c97df44 671 }
lypinator 0:bb348c97df44 672
lypinator 0:bb348c97df44 673 #pragma GCC diagnostic pop
lypinator 0:bb348c97df44 674
lypinator 0:bb348c97df44 675 #endif /* __CMSIS_GCC_H */