Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/cmsis/TARGET_CORTEX_A/cmsis_armcc.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**************************************************************************//**
lypinator 0:bb348c97df44 2 * @file cmsis_armcc.h
lypinator 0:bb348c97df44 3 * @brief CMSIS compiler specific macros, functions, instructions
lypinator 0:bb348c97df44 4 * @version V1.0.2
lypinator 0:bb348c97df44 5 * @date 10. January 2018
lypinator 0:bb348c97df44 6 ******************************************************************************/
lypinator 0:bb348c97df44 7 /*
lypinator 0:bb348c97df44 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * SPDX-License-Identifier: Apache-2.0
lypinator 0:bb348c97df44 11 *
lypinator 0:bb348c97df44 12 * Licensed under the Apache License, Version 2.0 (the License); you may
lypinator 0:bb348c97df44 13 * not use this file except in compliance with the License.
lypinator 0:bb348c97df44 14 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 15 *
lypinator 0:bb348c97df44 16 * www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 17 *
lypinator 0:bb348c97df44 18 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
lypinator 0:bb348c97df44 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 21 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 22 * limitations under the License.
lypinator 0:bb348c97df44 23 */
lypinator 0:bb348c97df44 24
lypinator 0:bb348c97df44 25 #ifndef __CMSIS_ARMCC_H
lypinator 0:bb348c97df44 26 #define __CMSIS_ARMCC_H
lypinator 0:bb348c97df44 27
lypinator 0:bb348c97df44 28 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
lypinator 0:bb348c97df44 29 #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
lypinator 0:bb348c97df44 30 #endif
lypinator 0:bb348c97df44 31
lypinator 0:bb348c97df44 32 /* CMSIS compiler control architecture macros */
lypinator 0:bb348c97df44 33 #if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A == 1))
lypinator 0:bb348c97df44 34 #define __ARM_ARCH_7A__ 1
lypinator 0:bb348c97df44 35 #endif
lypinator 0:bb348c97df44 36
lypinator 0:bb348c97df44 37 /* CMSIS compiler specific defines */
lypinator 0:bb348c97df44 38 #ifndef __ASM
lypinator 0:bb348c97df44 39 #define __ASM __asm
lypinator 0:bb348c97df44 40 #endif
lypinator 0:bb348c97df44 41 #ifndef __INLINE
lypinator 0:bb348c97df44 42 #define __INLINE __inline
lypinator 0:bb348c97df44 43 #endif
lypinator 0:bb348c97df44 44 #ifndef __FORCEINLINE
lypinator 0:bb348c97df44 45 #define __FORCEINLINE __forceinline
lypinator 0:bb348c97df44 46 #endif
lypinator 0:bb348c97df44 47 #ifndef __STATIC_INLINE
lypinator 0:bb348c97df44 48 #define __STATIC_INLINE static __inline
lypinator 0:bb348c97df44 49 #endif
lypinator 0:bb348c97df44 50 #ifndef __STATIC_FORCEINLINE
lypinator 0:bb348c97df44 51 #define __STATIC_FORCEINLINE static __forceinline
lypinator 0:bb348c97df44 52 #endif
lypinator 0:bb348c97df44 53 #ifndef __NO_RETURN
lypinator 0:bb348c97df44 54 #define __NO_RETURN __declspec(noreturn)
lypinator 0:bb348c97df44 55 #endif
lypinator 0:bb348c97df44 56 #ifndef CMSIS_DEPRECATED
lypinator 0:bb348c97df44 57 #define CMSIS_DEPRECATED __attribute__((deprecated))
lypinator 0:bb348c97df44 58 #endif
lypinator 0:bb348c97df44 59 #ifndef __USED
lypinator 0:bb348c97df44 60 #define __USED __attribute__((used))
lypinator 0:bb348c97df44 61 #endif
lypinator 0:bb348c97df44 62 #ifndef __WEAK
lypinator 0:bb348c97df44 63 #define __WEAK __attribute__((weak))
lypinator 0:bb348c97df44 64 #endif
lypinator 0:bb348c97df44 65 #ifndef __PACKED
lypinator 0:bb348c97df44 66 #define __PACKED __attribute__((packed))
lypinator 0:bb348c97df44 67 #endif
lypinator 0:bb348c97df44 68 #ifndef __PACKED_STRUCT
lypinator 0:bb348c97df44 69 #define __PACKED_STRUCT __packed struct
lypinator 0:bb348c97df44 70 #endif
lypinator 0:bb348c97df44 71 #ifndef __UNALIGNED_UINT16_WRITE
lypinator 0:bb348c97df44 72 #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
lypinator 0:bb348c97df44 73 #endif
lypinator 0:bb348c97df44 74 #ifndef __UNALIGNED_UINT16_READ
lypinator 0:bb348c97df44 75 #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
lypinator 0:bb348c97df44 76 #endif
lypinator 0:bb348c97df44 77 #ifndef __UNALIGNED_UINT32_WRITE
lypinator 0:bb348c97df44 78 #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
lypinator 0:bb348c97df44 79 #endif
lypinator 0:bb348c97df44 80 #ifndef __UNALIGNED_UINT32_READ
lypinator 0:bb348c97df44 81 #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
lypinator 0:bb348c97df44 82 #endif
lypinator 0:bb348c97df44 83 #ifndef __ALIGNED
lypinator 0:bb348c97df44 84 #define __ALIGNED(x) __attribute__((aligned(x)))
lypinator 0:bb348c97df44 85 #endif
lypinator 0:bb348c97df44 86 #ifndef __PACKED
lypinator 0:bb348c97df44 87 #define __PACKED __attribute__((packed))
lypinator 0:bb348c97df44 88 #endif
lypinator 0:bb348c97df44 89
lypinator 0:bb348c97df44 90 /* ########################## Core Instruction Access ######################### */
lypinator 0:bb348c97df44 91 /**
lypinator 0:bb348c97df44 92 \brief No Operation
lypinator 0:bb348c97df44 93 */
lypinator 0:bb348c97df44 94 #define __NOP __nop
lypinator 0:bb348c97df44 95
lypinator 0:bb348c97df44 96 /**
lypinator 0:bb348c97df44 97 \brief Wait For Interrupt
lypinator 0:bb348c97df44 98 */
lypinator 0:bb348c97df44 99 #define __WFI __wfi
lypinator 0:bb348c97df44 100
lypinator 0:bb348c97df44 101 /**
lypinator 0:bb348c97df44 102 \brief Wait For Event
lypinator 0:bb348c97df44 103 */
lypinator 0:bb348c97df44 104 #define __WFE __wfe
lypinator 0:bb348c97df44 105
lypinator 0:bb348c97df44 106 /**
lypinator 0:bb348c97df44 107 \brief Send Event
lypinator 0:bb348c97df44 108 */
lypinator 0:bb348c97df44 109 #define __SEV __sev
lypinator 0:bb348c97df44 110
lypinator 0:bb348c97df44 111 /**
lypinator 0:bb348c97df44 112 \brief Instruction Synchronization Barrier
lypinator 0:bb348c97df44 113 */
lypinator 0:bb348c97df44 114 #define __ISB() do {\
lypinator 0:bb348c97df44 115 __schedule_barrier();\
lypinator 0:bb348c97df44 116 __isb(0xF);\
lypinator 0:bb348c97df44 117 __schedule_barrier();\
lypinator 0:bb348c97df44 118 } while (0U)
lypinator 0:bb348c97df44 119
lypinator 0:bb348c97df44 120 /**
lypinator 0:bb348c97df44 121 \brief Data Synchronization Barrier
lypinator 0:bb348c97df44 122 */
lypinator 0:bb348c97df44 123 #define __DSB() do {\
lypinator 0:bb348c97df44 124 __schedule_barrier();\
lypinator 0:bb348c97df44 125 __dsb(0xF);\
lypinator 0:bb348c97df44 126 __schedule_barrier();\
lypinator 0:bb348c97df44 127 } while (0U)
lypinator 0:bb348c97df44 128
lypinator 0:bb348c97df44 129 /**
lypinator 0:bb348c97df44 130 \brief Data Memory Barrier
lypinator 0:bb348c97df44 131 */
lypinator 0:bb348c97df44 132 #define __DMB() do {\
lypinator 0:bb348c97df44 133 __schedule_barrier();\
lypinator 0:bb348c97df44 134 __dmb(0xF);\
lypinator 0:bb348c97df44 135 __schedule_barrier();\
lypinator 0:bb348c97df44 136 } while (0U)
lypinator 0:bb348c97df44 137
lypinator 0:bb348c97df44 138 /**
lypinator 0:bb348c97df44 139 \brief Reverse byte order (32 bit)
lypinator 0:bb348c97df44 140 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
lypinator 0:bb348c97df44 141 \param [in] value Value to reverse
lypinator 0:bb348c97df44 142 \return Reversed value
lypinator 0:bb348c97df44 143 */
lypinator 0:bb348c97df44 144 #define __REV __rev
lypinator 0:bb348c97df44 145
lypinator 0:bb348c97df44 146 /**
lypinator 0:bb348c97df44 147 \brief Reverse byte order (16 bit)
lypinator 0:bb348c97df44 148 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
lypinator 0:bb348c97df44 149 \param [in] value Value to reverse
lypinator 0:bb348c97df44 150 \return Reversed value
lypinator 0:bb348c97df44 151 */
lypinator 0:bb348c97df44 152 #ifndef __NO_EMBEDDED_ASM
lypinator 0:bb348c97df44 153 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
lypinator 0:bb348c97df44 154 {
lypinator 0:bb348c97df44 155 rev16 r0, r0
lypinator 0:bb348c97df44 156 bx lr
lypinator 0:bb348c97df44 157 }
lypinator 0:bb348c97df44 158 #endif
lypinator 0:bb348c97df44 159
lypinator 0:bb348c97df44 160 /**
lypinator 0:bb348c97df44 161 \brief Reverse byte order (16 bit)
lypinator 0:bb348c97df44 162 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
lypinator 0:bb348c97df44 163 \param [in] value Value to reverse
lypinator 0:bb348c97df44 164 \return Reversed value
lypinator 0:bb348c97df44 165 */
lypinator 0:bb348c97df44 166 #ifndef __NO_EMBEDDED_ASM
lypinator 0:bb348c97df44 167 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
lypinator 0:bb348c97df44 168 {
lypinator 0:bb348c97df44 169 revsh r0, r0
lypinator 0:bb348c97df44 170 bx lr
lypinator 0:bb348c97df44 171 }
lypinator 0:bb348c97df44 172 #endif
lypinator 0:bb348c97df44 173
lypinator 0:bb348c97df44 174 /**
lypinator 0:bb348c97df44 175 \brief Rotate Right in unsigned value (32 bit)
lypinator 0:bb348c97df44 176 \param [in] op1 Value to rotate
lypinator 0:bb348c97df44 177 \param [in] op2 Number of Bits to rotate
lypinator 0:bb348c97df44 178 \return Rotated value
lypinator 0:bb348c97df44 179 */
lypinator 0:bb348c97df44 180 #define __ROR __ror
lypinator 0:bb348c97df44 181
lypinator 0:bb348c97df44 182 /**
lypinator 0:bb348c97df44 183 \brief Breakpoint
lypinator 0:bb348c97df44 184 \param [in] value is ignored by the processor.
lypinator 0:bb348c97df44 185 If required, a debugger can use it to store additional information about the breakpoint.
lypinator 0:bb348c97df44 186 */
lypinator 0:bb348c97df44 187 #define __BKPT(value) __breakpoint(value)
lypinator 0:bb348c97df44 188
lypinator 0:bb348c97df44 189 /**
lypinator 0:bb348c97df44 190 \brief Reverse bit order of value
lypinator 0:bb348c97df44 191 \param [in] value Value to reverse
lypinator 0:bb348c97df44 192 \return Reversed value
lypinator 0:bb348c97df44 193 */
lypinator 0:bb348c97df44 194 #define __RBIT __rbit
lypinator 0:bb348c97df44 195
lypinator 0:bb348c97df44 196 /**
lypinator 0:bb348c97df44 197 \brief Count leading zeros
lypinator 0:bb348c97df44 198 \param [in] value Value to count the leading zeros
lypinator 0:bb348c97df44 199 \return number of leading zeros in value
lypinator 0:bb348c97df44 200 */
lypinator 0:bb348c97df44 201 #define __CLZ __clz
lypinator 0:bb348c97df44 202
lypinator 0:bb348c97df44 203 /**
lypinator 0:bb348c97df44 204 \brief LDR Exclusive (8 bit)
lypinator 0:bb348c97df44 205 \details Executes a exclusive LDR instruction for 8 bit value.
lypinator 0:bb348c97df44 206 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 207 \return value of type uint8_t at (*ptr)
lypinator 0:bb348c97df44 208 */
lypinator 0:bb348c97df44 209 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
lypinator 0:bb348c97df44 210 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
lypinator 0:bb348c97df44 211 #else
lypinator 0:bb348c97df44 212 #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
lypinator 0:bb348c97df44 213 #endif
lypinator 0:bb348c97df44 214
lypinator 0:bb348c97df44 215 /**
lypinator 0:bb348c97df44 216 \brief LDR Exclusive (16 bit)
lypinator 0:bb348c97df44 217 \details Executes a exclusive LDR instruction for 16 bit values.
lypinator 0:bb348c97df44 218 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 219 \return value of type uint16_t at (*ptr)
lypinator 0:bb348c97df44 220 */
lypinator 0:bb348c97df44 221 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
lypinator 0:bb348c97df44 222 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
lypinator 0:bb348c97df44 223 #else
lypinator 0:bb348c97df44 224 #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
lypinator 0:bb348c97df44 225 #endif
lypinator 0:bb348c97df44 226
lypinator 0:bb348c97df44 227 /**
lypinator 0:bb348c97df44 228 \brief LDR Exclusive (32 bit)
lypinator 0:bb348c97df44 229 \details Executes a exclusive LDR instruction for 32 bit values.
lypinator 0:bb348c97df44 230 \param [in] ptr Pointer to data
lypinator 0:bb348c97df44 231 \return value of type uint32_t at (*ptr)
lypinator 0:bb348c97df44 232 */
lypinator 0:bb348c97df44 233 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
lypinator 0:bb348c97df44 234 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
lypinator 0:bb348c97df44 235 #else
lypinator 0:bb348c97df44 236 #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
lypinator 0:bb348c97df44 237 #endif
lypinator 0:bb348c97df44 238
lypinator 0:bb348c97df44 239 /**
lypinator 0:bb348c97df44 240 \brief STR Exclusive (8 bit)
lypinator 0:bb348c97df44 241 \details Executes a exclusive STR instruction for 8 bit values.
lypinator 0:bb348c97df44 242 \param [in] value Value to store
lypinator 0:bb348c97df44 243 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 244 \return 0 Function succeeded
lypinator 0:bb348c97df44 245 \return 1 Function failed
lypinator 0:bb348c97df44 246 */
lypinator 0:bb348c97df44 247 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
lypinator 0:bb348c97df44 248 #define __STREXB(value, ptr) __strex(value, ptr)
lypinator 0:bb348c97df44 249 #else
lypinator 0:bb348c97df44 250 #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
lypinator 0:bb348c97df44 251 #endif
lypinator 0:bb348c97df44 252
lypinator 0:bb348c97df44 253 /**
lypinator 0:bb348c97df44 254 \brief STR Exclusive (16 bit)
lypinator 0:bb348c97df44 255 \details Executes a exclusive STR instruction for 16 bit values.
lypinator 0:bb348c97df44 256 \param [in] value Value to store
lypinator 0:bb348c97df44 257 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 258 \return 0 Function succeeded
lypinator 0:bb348c97df44 259 \return 1 Function failed
lypinator 0:bb348c97df44 260 */
lypinator 0:bb348c97df44 261 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
lypinator 0:bb348c97df44 262 #define __STREXH(value, ptr) __strex(value, ptr)
lypinator 0:bb348c97df44 263 #else
lypinator 0:bb348c97df44 264 #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
lypinator 0:bb348c97df44 265 #endif
lypinator 0:bb348c97df44 266
lypinator 0:bb348c97df44 267 /**
lypinator 0:bb348c97df44 268 \brief STR Exclusive (32 bit)
lypinator 0:bb348c97df44 269 \details Executes a exclusive STR instruction for 32 bit values.
lypinator 0:bb348c97df44 270 \param [in] value Value to store
lypinator 0:bb348c97df44 271 \param [in] ptr Pointer to location
lypinator 0:bb348c97df44 272 \return 0 Function succeeded
lypinator 0:bb348c97df44 273 \return 1 Function failed
lypinator 0:bb348c97df44 274 */
lypinator 0:bb348c97df44 275 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
lypinator 0:bb348c97df44 276 #define __STREXW(value, ptr) __strex(value, ptr)
lypinator 0:bb348c97df44 277 #else
lypinator 0:bb348c97df44 278 #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
lypinator 0:bb348c97df44 279 #endif
lypinator 0:bb348c97df44 280
lypinator 0:bb348c97df44 281 /**
lypinator 0:bb348c97df44 282 \brief Remove the exclusive lock
lypinator 0:bb348c97df44 283 \details Removes the exclusive lock which is created by LDREX.
lypinator 0:bb348c97df44 284 */
lypinator 0:bb348c97df44 285 #define __CLREX __clrex
lypinator 0:bb348c97df44 286
lypinator 0:bb348c97df44 287
lypinator 0:bb348c97df44 288 /**
lypinator 0:bb348c97df44 289 \brief Signed Saturate
lypinator 0:bb348c97df44 290 \details Saturates a signed value.
lypinator 0:bb348c97df44 291 \param [in] value Value to be saturated
lypinator 0:bb348c97df44 292 \param [in] sat Bit position to saturate to (1..32)
lypinator 0:bb348c97df44 293 \return Saturated value
lypinator 0:bb348c97df44 294 */
lypinator 0:bb348c97df44 295 #define __SSAT __ssat
lypinator 0:bb348c97df44 296
lypinator 0:bb348c97df44 297 /**
lypinator 0:bb348c97df44 298 \brief Unsigned Saturate
lypinator 0:bb348c97df44 299 \details Saturates an unsigned value.
lypinator 0:bb348c97df44 300 \param [in] value Value to be saturated
lypinator 0:bb348c97df44 301 \param [in] sat Bit position to saturate to (0..31)
lypinator 0:bb348c97df44 302 \return Saturated value
lypinator 0:bb348c97df44 303 */
lypinator 0:bb348c97df44 304 #define __USAT __usat
lypinator 0:bb348c97df44 305
lypinator 0:bb348c97df44 306 /* ########################### Core Function Access ########################### */
lypinator 0:bb348c97df44 307
lypinator 0:bb348c97df44 308 /**
lypinator 0:bb348c97df44 309 \brief Get FPSCR (Floating Point Status/Control)
lypinator 0:bb348c97df44 310 \return Floating Point Status/Control register value
lypinator 0:bb348c97df44 311 */
lypinator 0:bb348c97df44 312 __STATIC_INLINE uint32_t __get_FPSCR(void)
lypinator 0:bb348c97df44 313 {
lypinator 0:bb348c97df44 314 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
lypinator 0:bb348c97df44 315 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
lypinator 0:bb348c97df44 316 register uint32_t __regfpscr __ASM("fpscr");
lypinator 0:bb348c97df44 317 return(__regfpscr);
lypinator 0:bb348c97df44 318 #else
lypinator 0:bb348c97df44 319 return(0U);
lypinator 0:bb348c97df44 320 #endif
lypinator 0:bb348c97df44 321 }
lypinator 0:bb348c97df44 322
lypinator 0:bb348c97df44 323 /**
lypinator 0:bb348c97df44 324 \brief Set FPSCR (Floating Point Status/Control)
lypinator 0:bb348c97df44 325 \param [in] fpscr Floating Point Status/Control value to set
lypinator 0:bb348c97df44 326 */
lypinator 0:bb348c97df44 327 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
lypinator 0:bb348c97df44 328 {
lypinator 0:bb348c97df44 329 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
lypinator 0:bb348c97df44 330 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
lypinator 0:bb348c97df44 331 register uint32_t __regfpscr __ASM("fpscr");
lypinator 0:bb348c97df44 332 __regfpscr = (fpscr);
lypinator 0:bb348c97df44 333 #else
lypinator 0:bb348c97df44 334 (void)fpscr;
lypinator 0:bb348c97df44 335 #endif
lypinator 0:bb348c97df44 336 }
lypinator 0:bb348c97df44 337
lypinator 0:bb348c97df44 338 /** \brief Get CPSR (Current Program Status Register)
lypinator 0:bb348c97df44 339 \return CPSR Register value
lypinator 0:bb348c97df44 340 */
lypinator 0:bb348c97df44 341 __STATIC_INLINE uint32_t __get_CPSR(void)
lypinator 0:bb348c97df44 342 {
lypinator 0:bb348c97df44 343 register uint32_t __regCPSR __ASM("cpsr");
lypinator 0:bb348c97df44 344 return(__regCPSR);
lypinator 0:bb348c97df44 345 }
lypinator 0:bb348c97df44 346
lypinator 0:bb348c97df44 347
lypinator 0:bb348c97df44 348 /** \brief Set CPSR (Current Program Status Register)
lypinator 0:bb348c97df44 349 \param [in] cpsr CPSR value to set
lypinator 0:bb348c97df44 350 */
lypinator 0:bb348c97df44 351 __STATIC_INLINE void __set_CPSR(uint32_t cpsr)
lypinator 0:bb348c97df44 352 {
lypinator 0:bb348c97df44 353 register uint32_t __regCPSR __ASM("cpsr");
lypinator 0:bb348c97df44 354 __regCPSR = cpsr;
lypinator 0:bb348c97df44 355 }
lypinator 0:bb348c97df44 356
lypinator 0:bb348c97df44 357 /** \brief Get Mode
lypinator 0:bb348c97df44 358 \return Processor Mode
lypinator 0:bb348c97df44 359 */
lypinator 0:bb348c97df44 360 __STATIC_INLINE uint32_t __get_mode(void)
lypinator 0:bb348c97df44 361 {
lypinator 0:bb348c97df44 362 return (__get_CPSR() & 0x1FU);
lypinator 0:bb348c97df44 363 }
lypinator 0:bb348c97df44 364
lypinator 0:bb348c97df44 365 /** \brief Set Mode
lypinator 0:bb348c97df44 366 \param [in] mode Mode value to set
lypinator 0:bb348c97df44 367 */
lypinator 0:bb348c97df44 368 __STATIC_INLINE __ASM void __set_mode(uint32_t mode)
lypinator 0:bb348c97df44 369 {
lypinator 0:bb348c97df44 370 MOV r1, lr
lypinator 0:bb348c97df44 371 MSR CPSR_C, r0
lypinator 0:bb348c97df44 372 BX r1
lypinator 0:bb348c97df44 373 }
lypinator 0:bb348c97df44 374
lypinator 0:bb348c97df44 375 /** \brief Get Stack Pointer
lypinator 0:bb348c97df44 376 \return Stack Pointer
lypinator 0:bb348c97df44 377 */
lypinator 0:bb348c97df44 378 __STATIC_INLINE __ASM uint32_t __get_SP(void)
lypinator 0:bb348c97df44 379 {
lypinator 0:bb348c97df44 380 MOV r0, sp
lypinator 0:bb348c97df44 381 BX lr
lypinator 0:bb348c97df44 382 }
lypinator 0:bb348c97df44 383
lypinator 0:bb348c97df44 384 /** \brief Set Stack Pointer
lypinator 0:bb348c97df44 385 \param [in] stack Stack Pointer value to set
lypinator 0:bb348c97df44 386 */
lypinator 0:bb348c97df44 387 __STATIC_INLINE __ASM void __set_SP(uint32_t stack)
lypinator 0:bb348c97df44 388 {
lypinator 0:bb348c97df44 389 MOV sp, r0
lypinator 0:bb348c97df44 390 BX lr
lypinator 0:bb348c97df44 391 }
lypinator 0:bb348c97df44 392
lypinator 0:bb348c97df44 393
lypinator 0:bb348c97df44 394 /** \brief Get USR/SYS Stack Pointer
lypinator 0:bb348c97df44 395 \return USR/SYSStack Pointer
lypinator 0:bb348c97df44 396 */
lypinator 0:bb348c97df44 397 __STATIC_INLINE __ASM uint32_t __get_SP_usr(void)
lypinator 0:bb348c97df44 398 {
lypinator 0:bb348c97df44 399 ARM
lypinator 0:bb348c97df44 400 PRESERVE8
lypinator 0:bb348c97df44 401
lypinator 0:bb348c97df44 402 MRS R1, CPSR
lypinator 0:bb348c97df44 403 CPS #0x1F ;no effect in USR mode
lypinator 0:bb348c97df44 404 MOV R0, SP
lypinator 0:bb348c97df44 405 MSR CPSR_c, R1 ;no effect in USR mode
lypinator 0:bb348c97df44 406 ISB
lypinator 0:bb348c97df44 407 BX LR
lypinator 0:bb348c97df44 408 }
lypinator 0:bb348c97df44 409
lypinator 0:bb348c97df44 410 /** \brief Set USR/SYS Stack Pointer
lypinator 0:bb348c97df44 411 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
lypinator 0:bb348c97df44 412 */
lypinator 0:bb348c97df44 413 __STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack)
lypinator 0:bb348c97df44 414 {
lypinator 0:bb348c97df44 415 ARM
lypinator 0:bb348c97df44 416 PRESERVE8
lypinator 0:bb348c97df44 417
lypinator 0:bb348c97df44 418 MRS R1, CPSR
lypinator 0:bb348c97df44 419 CPS #0x1F ;no effect in USR mode
lypinator 0:bb348c97df44 420 MOV SP, R0
lypinator 0:bb348c97df44 421 MSR CPSR_c, R1 ;no effect in USR mode
lypinator 0:bb348c97df44 422 ISB
lypinator 0:bb348c97df44 423 BX LR
lypinator 0:bb348c97df44 424 }
lypinator 0:bb348c97df44 425
lypinator 0:bb348c97df44 426 /** \brief Get FPEXC (Floating Point Exception Control Register)
lypinator 0:bb348c97df44 427 \return Floating Point Exception Control Register value
lypinator 0:bb348c97df44 428 */
lypinator 0:bb348c97df44 429 __STATIC_INLINE uint32_t __get_FPEXC(void)
lypinator 0:bb348c97df44 430 {
lypinator 0:bb348c97df44 431 #if (__FPU_PRESENT == 1)
lypinator 0:bb348c97df44 432 register uint32_t __regfpexc __ASM("fpexc");
lypinator 0:bb348c97df44 433 return(__regfpexc);
lypinator 0:bb348c97df44 434 #else
lypinator 0:bb348c97df44 435 return(0);
lypinator 0:bb348c97df44 436 #endif
lypinator 0:bb348c97df44 437 }
lypinator 0:bb348c97df44 438
lypinator 0:bb348c97df44 439 /** \brief Set FPEXC (Floating Point Exception Control Register)
lypinator 0:bb348c97df44 440 \param [in] fpexc Floating Point Exception Control value to set
lypinator 0:bb348c97df44 441 */
lypinator 0:bb348c97df44 442 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
lypinator 0:bb348c97df44 443 {
lypinator 0:bb348c97df44 444 #if (__FPU_PRESENT == 1)
lypinator 0:bb348c97df44 445 register uint32_t __regfpexc __ASM("fpexc");
lypinator 0:bb348c97df44 446 __regfpexc = (fpexc);
lypinator 0:bb348c97df44 447 #endif
lypinator 0:bb348c97df44 448 }
lypinator 0:bb348c97df44 449
lypinator 0:bb348c97df44 450 /*
lypinator 0:bb348c97df44 451 * Include common core functions to access Coprocessor 15 registers
lypinator 0:bb348c97df44 452 */
lypinator 0:bb348c97df44 453
lypinator 0:bb348c97df44 454 #define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0)
lypinator 0:bb348c97df44 455 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0)
lypinator 0:bb348c97df44 456 #define __get_CP64(cp, op1, Rt, CRm) \
lypinator 0:bb348c97df44 457 do { \
lypinator 0:bb348c97df44 458 uint32_t ltmp, htmp; \
lypinator 0:bb348c97df44 459 __ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
lypinator 0:bb348c97df44 460 (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \
lypinator 0:bb348c97df44 461 } while(0)
lypinator 0:bb348c97df44 462
lypinator 0:bb348c97df44 463 #define __set_CP64(cp, op1, Rt, CRm) \
lypinator 0:bb348c97df44 464 do { \
lypinator 0:bb348c97df44 465 const uint64_t tmp = (Rt); \
lypinator 0:bb348c97df44 466 const uint32_t ltmp = (uint32_t)(tmp); \
lypinator 0:bb348c97df44 467 const uint32_t htmp = (uint32_t)(tmp >> 32U); \
lypinator 0:bb348c97df44 468 __ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
lypinator 0:bb348c97df44 469 } while(0)
lypinator 0:bb348c97df44 470
lypinator 0:bb348c97df44 471 #include "cmsis_cp15.h"
lypinator 0:bb348c97df44 472
lypinator 0:bb348c97df44 473 /** \brief Enable Floating Point Unit
lypinator 0:bb348c97df44 474
lypinator 0:bb348c97df44 475 Critical section, called from undef handler, so systick is disabled
lypinator 0:bb348c97df44 476 */
lypinator 0:bb348c97df44 477 __STATIC_INLINE __ASM void __FPU_Enable(void)
lypinator 0:bb348c97df44 478 {
lypinator 0:bb348c97df44 479 ARM
lypinator 0:bb348c97df44 480
lypinator 0:bb348c97df44 481 //Permit access to VFP/NEON, registers by modifying CPACR
lypinator 0:bb348c97df44 482 MRC p15,0,R1,c1,c0,2
lypinator 0:bb348c97df44 483 ORR R1,R1,#0x00F00000
lypinator 0:bb348c97df44 484 MCR p15,0,R1,c1,c0,2
lypinator 0:bb348c97df44 485
lypinator 0:bb348c97df44 486 //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
lypinator 0:bb348c97df44 487 ISB
lypinator 0:bb348c97df44 488
lypinator 0:bb348c97df44 489 //Enable VFP/NEON
lypinator 0:bb348c97df44 490 VMRS R1,FPEXC
lypinator 0:bb348c97df44 491 ORR R1,R1,#0x40000000
lypinator 0:bb348c97df44 492 VMSR FPEXC,R1
lypinator 0:bb348c97df44 493
lypinator 0:bb348c97df44 494 //Initialise VFP/NEON registers to 0
lypinator 0:bb348c97df44 495 MOV R2,#0
lypinator 0:bb348c97df44 496
lypinator 0:bb348c97df44 497 //Initialise D16 registers to 0
lypinator 0:bb348c97df44 498 VMOV D0, R2,R2
lypinator 0:bb348c97df44 499 VMOV D1, R2,R2
lypinator 0:bb348c97df44 500 VMOV D2, R2,R2
lypinator 0:bb348c97df44 501 VMOV D3, R2,R2
lypinator 0:bb348c97df44 502 VMOV D4, R2,R2
lypinator 0:bb348c97df44 503 VMOV D5, R2,R2
lypinator 0:bb348c97df44 504 VMOV D6, R2,R2
lypinator 0:bb348c97df44 505 VMOV D7, R2,R2
lypinator 0:bb348c97df44 506 VMOV D8, R2,R2
lypinator 0:bb348c97df44 507 VMOV D9, R2,R2
lypinator 0:bb348c97df44 508 VMOV D10,R2,R2
lypinator 0:bb348c97df44 509 VMOV D11,R2,R2
lypinator 0:bb348c97df44 510 VMOV D12,R2,R2
lypinator 0:bb348c97df44 511 VMOV D13,R2,R2
lypinator 0:bb348c97df44 512 VMOV D14,R2,R2
lypinator 0:bb348c97df44 513 VMOV D15,R2,R2
lypinator 0:bb348c97df44 514
lypinator 0:bb348c97df44 515 IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
lypinator 0:bb348c97df44 516 //Initialise D32 registers to 0
lypinator 0:bb348c97df44 517 VMOV D16,R2,R2
lypinator 0:bb348c97df44 518 VMOV D17,R2,R2
lypinator 0:bb348c97df44 519 VMOV D18,R2,R2
lypinator 0:bb348c97df44 520 VMOV D19,R2,R2
lypinator 0:bb348c97df44 521 VMOV D20,R2,R2
lypinator 0:bb348c97df44 522 VMOV D21,R2,R2
lypinator 0:bb348c97df44 523 VMOV D22,R2,R2
lypinator 0:bb348c97df44 524 VMOV D23,R2,R2
lypinator 0:bb348c97df44 525 VMOV D24,R2,R2
lypinator 0:bb348c97df44 526 VMOV D25,R2,R2
lypinator 0:bb348c97df44 527 VMOV D26,R2,R2
lypinator 0:bb348c97df44 528 VMOV D27,R2,R2
lypinator 0:bb348c97df44 529 VMOV D28,R2,R2
lypinator 0:bb348c97df44 530 VMOV D29,R2,R2
lypinator 0:bb348c97df44 531 VMOV D30,R2,R2
lypinator 0:bb348c97df44 532 VMOV D31,R2,R2
lypinator 0:bb348c97df44 533 ENDIF
lypinator 0:bb348c97df44 534
lypinator 0:bb348c97df44 535 //Initialise FPSCR to a known state
lypinator 0:bb348c97df44 536 VMRS R2,FPSCR
lypinator 0:bb348c97df44 537 LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
lypinator 0:bb348c97df44 538 AND R2,R2,R3
lypinator 0:bb348c97df44 539 VMSR FPSCR,R2
lypinator 0:bb348c97df44 540
lypinator 0:bb348c97df44 541 BX LR
lypinator 0:bb348c97df44 542 }
lypinator 0:bb348c97df44 543
lypinator 0:bb348c97df44 544 #endif /* __CMSIS_ARMCC_H */