Diff: targets/hal/TARGET_Freescale/TARGET_K20D50M/clk_freqs.h

Revision:

429:cc5da43e7bf6

Parent:

255:20b371a9491b

diff -r 4ddf7f7eabbb -r cc5da43e7bf6 targets/hal/TARGET_Freescale/TARGET_K20D50M/clk_freqs.h
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/clk_freqs.h	Mon Dec 08 07:30:07 2014 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_K20D50M/clk_freqs.h	Tue Dec 09 14:15:07 2014 +0000
@@ -89,6 +89,24 @@
     return 0;
 }
 
+//Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
+static uint32_t mcgpllfll_frequency(void) { 
+    if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0))   //PLL/FLL is not selected
+        return 0;
+    
+    uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
+    if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {         //FLL is selected
+        SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK;        //MCG peripheral clock is FLL output
+        return MCGClock;
+    } else {                                            //PLL is selected
+        SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK;         //MCG peripheral clock is PLL output
+        return MCGClock;
+    }
+    
+    //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active 
+    //for the peripherals, this is however an unlikely setup
+}
+
 
 #ifdef __cplusplus
 }