Revision 1:3b0bd7db2092, committed 2016-09-22

Comitter:

lloydg

Date:

Thu Sep 22 11:15:01 2016 +0000

Parent:

0:ce5a25daadce

Child:

2:2033db202017

Commit message:

test

Changed in this revision

--- a/M24SR-DISCOVERY_hardware/mbed/AnalogIn.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,128 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGIN_H
-#define MBED_ANALOGIN_H
-
-#include "platform.h"
-
-#if DEVICE_ANALOGIN
-
-#include "analogin_api.h"
-#include "SingletonPtr.h"
-#include "PlatformMutex.h"
-
-namespace mbed {
-
-/** An analog input, used for reading the voltage on a pin
- *
- * @Note Synchronization level: Thread safe
- *
- * Example:
- * @code
- * // Print messages when the AnalogIn is greater than 50%
- *
- * #include "mbed.h"
- *
- * AnalogIn temperature(p20);
- *
- * int main() {
- *     while(1) {
- *         if(temperature > 0.5) {
- *             printf("Too hot! (%f)", temperature.read());
- *         }
- *     }
- * }
- * @endcode
- */
-class AnalogIn {
-
-public:
-
-    /** Create an AnalogIn, connected to the specified pin
-     *
-     * @param pin AnalogIn pin to connect to
-     * @param name (optional) A string to identify the object
-     */
-    AnalogIn(PinName pin) {
-        lock();
-        analogin_init(&_adc, pin);
-        unlock();
-    }
-
-    /** Read the input voltage, represented as a float in the range [0.0, 1.0]
-     *
-     * @returns A floating-point value representing the current input voltage, measured as a percentage
-     */
-    float read() {
-        lock();
-        float ret = analogin_read(&_adc);
-        unlock();
-        return ret;
-    }
-
-    /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
-     *
-     * @returns
-     *   16-bit unsigned short representing the current input voltage, normalised to a 16-bit value
-     */
-    unsigned short read_u16() {
-        lock();
-        unsigned short ret = analogin_read_u16(&_adc);
-        unlock();
-        return ret;
-    }
-
-    /** An operator shorthand for read()
-     *
-     * The float() operator can be used as a shorthand for read() to simplify common code sequences
-     *
-     * Example:
-     * @code
-     * float x = volume.read();
-     * float x = volume;
-     *
-     * if(volume.read() > 0.25) { ... }
-     * if(volume > 0.25) { ... }
-     * @endcode
-     */
-    operator float() {
-        // Underlying call is thread safe
-        return read();
-    }
-
-    virtual ~AnalogIn() {
-        // Do nothing
-    }
-
-protected:
-
-    virtual void lock() {
-        _mutex->lock();
-    }
-
-    virtual void unlock() {
-        _mutex->unlock();
-    }
-
-    analogin_t _adc;
-    static SingletonPtr<PlatformMutex> _mutex;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/AnalogOut.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,146 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGOUT_H
-#define MBED_ANALOGOUT_H
-
-#include "platform.h"
-
-#if DEVICE_ANALOGOUT
-
-#include "analogout_api.h"
-#include "PlatformMutex.h"
-
-namespace mbed {
-
-/** An analog output, used for setting the voltage on a pin
- *
- * @Note Synchronization level: Thread safe
- *
- * Example:
- * @code
- * // Make a sawtooth output
- *
- * #include "mbed.h"
- *
- * AnalogOut tri(p18);
- * int main() {
- *     while(1) {
- *         tri = tri + 0.01;
- *         wait_us(1);
- *         if(tri == 1) {
- *             tri = 0;
- *         }
- *     }
- * }
- * @endcode
- */
-class AnalogOut {
-
-public:
-
-    /** Create an AnalogOut connected to the specified pin
-     *
-     *  @param AnalogOut pin to connect to (18)
-     */
-    AnalogOut(PinName pin) {
-        analogout_init(&_dac, pin);
-    }
-
-    /** Set the output voltage, specified as a percentage (float)
-     *
-     *  @param value A floating-point value representing the output voltage,
-     *    specified as a percentage. The value should lie between
-     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
-     *    Values outside this range will be saturated to 0.0f or 1.0f.
-     */
-    void write(float value) {
-        lock();
-        analogout_write(&_dac, value);
-        unlock();
-    }
-
-    /** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
-     *
-     *  @param value 16-bit unsigned short representing the output voltage,
-     *            normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)
-     */
-    void write_u16(unsigned short value) {
-        lock();
-        analogout_write_u16(&_dac, value);
-        unlock();
-    }
-
-    /** Return the current output voltage setting, measured as a percentage (float)
-     *
-     *  @returns
-     *    A floating-point value representing the current voltage being output on the pin,
-     *    measured as a percentage. The returned value will lie between
-     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
-     *
-     *  @note
-     *    This value may not match exactly the value set by a previous write().
-     */
-    float read() {
-        lock();
-        float ret = analogout_read(&_dac);
-        unlock();
-        return ret;
-    }
-
-    /** An operator shorthand for write()
-     */
-    AnalogOut& operator= (float percent) {
-        // Underlying write call is thread safe
-        write(percent);
-        return *this;
-    }
-
-    AnalogOut& operator= (AnalogOut& rhs) {
-        // Underlying write call is thread safe
-        write(rhs.read());
-        return *this;
-    }
-
-    /** An operator shorthand for read()
-     */
-    operator float() {
-        // Underlying read call is thread safe
-        return read();
-    }
-
-    virtual ~AnalogOut() {
-        // Do nothing
-    }
-
-protected:
-
-    virtual void lock() {
-        _mutex.lock();
-    }
-
-    virtual void unlock() {
-        _mutex.unlock();
-    }
-
-    dac_t _dac;
-    PlatformMutex _mutex;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/BusIn.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,104 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_BUSIN_H
-#define MBED_BUSIN_H
-
-#include "platform.h"
-#include "DigitalIn.h"
-#include "PlatformMutex.h"
-
-namespace mbed {
-
-/** A digital input bus, used for reading the state of a collection of pins
- *
- * @Note Synchronization level: Thread safe
- */
-class BusIn {
-
-public:
-    /* Group: Configuration Methods */
-
-    /** Create an BusIn, connected to the specified pins
-     *
-     * @param <n> DigitalIn pin to connect to bus bit <n> (p5-p30, NC)
-     *
-     * @note
-     *  It is only required to specify as many pin variables as is required
-     *  for the bus; the rest will default to NC (not connected)
-     */
-    BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
-          PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
-          PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
-          PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
-
-    BusIn(PinName pins[16]);
-
-    virtual ~BusIn();
-
-    /** Read the value of the input bus
-     *
-     *  @returns
-     *   An integer with each bit corresponding to the value read from the associated DigitalIn pin
-     */
-    int read();
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone
-     */
-    void mode(PinMode pull);
-
-    /** Binary mask of bus pins connected to actual pins (not NC pins)
-     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
-     *
-     *  @returns
-     *    Binary mask of connected pins
-     */
-    int mask() {
-        // No lock needed since _nc_mask is not modified outside the constructor
-        return _nc_mask;
-    }
-
-    /** A shorthand for read()
-     */
-    operator int();
-
-    /** Access to particular bit in random-iterator fashion
-     */
-    DigitalIn & operator[] (int index);
-
-protected:
-    DigitalIn* _pin[16];
-
-    /** Mask of bus's NC pins
-     * If bit[n] is set to 1 - pin is connected
-     * if bit[n] is cleared - pin is not connected (NC)
-     */
-    int _nc_mask;
-
-    PlatformMutex _mutex;
-
-    /* disallow copy constructor and assignment operators */
-private:
-    virtual void lock();
-    virtual void unlock();
-    BusIn(const BusIn&);
-    BusIn & operator = (const BusIn&);
-};
-
-} // namespace mbed
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/BusInOut.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,123 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_BUSINOUT_H
-#define MBED_BUSINOUT_H
-
-#include "DigitalInOut.h"
-#include "PlatformMutex.h"
-
-namespace mbed {
-
-/** A digital input output bus, used for setting the state of a collection of pins
- *
- * @Note Synchronization level: Thread safe
- */
-class BusInOut {
-
-public:
-
-    /** Create an BusInOut, connected to the specified pins
-     *
-     *  @param p<n> DigitalInOut pin to connect to bus bit p<n> (p5-p30, NC)
-     *
-     *  @note
-     *  It is only required to specify as many pin variables as is required
-     *  for the bus; the rest will default to NC (not connected)
-     */
-    BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
-             PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
-             PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
-             PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
-
-    BusInOut(PinName pins[16]);
-
-    virtual ~BusInOut();
-
-    /* Group: Access Methods */
-
-    /** Write the value to the output bus
-     *
-     *  @param value An integer specifying a bit to write for every corresponding DigitalInOut pin
-     */
-    void write(int value);
-
-    /** Read the value currently output on the bus
-     *
-     *  @returns
-     *    An integer with each bit corresponding to associated DigitalInOut pin setting
-     */
-    int read();
-
-    /** Set as an output
-     */
-    void output();
-
-    /** Set as an input
-     */
-    void input();
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone
-     */
-    void mode(PinMode pull);
-
-    /** Binary mask of bus pins connected to actual pins (not NC pins)
-     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
-     *
-     *  @returns
-     *    Binary mask of connected pins
-     */
-    int mask() {
-        // No lock needed since _nc_mask is not modified outside the constructor
-        return _nc_mask;
-    }
-
-     /** A shorthand for write()
-     */
-    BusInOut& operator= (int v);
-    BusInOut& operator= (BusInOut& rhs);
-
-    /** Access to particular bit in random-iterator fashion
-    */
-    DigitalInOut& operator[] (int index);
-
-    /** A shorthand for read()
-     */
-    operator int();
-
-protected:
-    virtual void lock();
-    virtual void unlock();
-    DigitalInOut* _pin[16];
-
-    /** Mask of bus's NC pins
-     * If bit[n] is set to 1 - pin is connected
-     * if bit[n] is cleared - pin is not connected (NC)
-     */
-    int _nc_mask;
-
-    PlatformMutex _mutex;
-
-    /* disallow copy constructor and assignment operators */
-private:
-    BusInOut(const BusInOut&);
-    BusInOut & operator = (const BusInOut&);
-};
-
-} // namespace mbed
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/BusOut.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,107 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_BUSOUT_H
-#define MBED_BUSOUT_H
-
-#include "DigitalOut.h"
-#include "PlatformMutex.h"
-
-namespace mbed {
-
-/** A digital output bus, used for setting the state of a collection of pins
- */
-class BusOut {
-
-public:
-
-    /** Create an BusOut, connected to the specified pins
-     *
-     *  @param p<n> DigitalOut pin to connect to bus bit <n> (p5-p30, NC)
-     *
-     *  @Note Synchronization level: Thread safe
-     *
-     *  @note
-     *  It is only required to specify as many pin variables as is required
-     *  for the bus; the rest will default to NC (not connected)
-     */
-    BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
-           PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
-           PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
-           PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
-
-    BusOut(PinName pins[16]);
-
-    virtual ~BusOut();
-
-    /** Write the value to the output bus
-     *
-     *  @param value An integer specifying a bit to write for every corresponding DigitalOut pin
-     */
-    void write(int value);
-
-    /** Read the value currently output on the bus
-     *
-     *  @returns
-     *    An integer with each bit corresponding to associated DigitalOut pin setting
-     */
-    int read();
-
-    /** Binary mask of bus pins connected to actual pins (not NC pins)
-     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
-     *
-     *  @returns
-     *    Binary mask of connected pins
-     */
-    int mask() {
-        // No lock needed since _nc_mask is not modified outside the constructor
-        return _nc_mask;
-    }
-
-    /** A shorthand for write()
-     */
-    BusOut& operator= (int v);
-    BusOut& operator= (BusOut& rhs);
-
-    /** Access to particular bit in random-iterator fashion
-     */
-    DigitalOut& operator[] (int index);
-
-    /** A shorthand for read()
-     */
-    operator int();
-
-protected:
-    virtual void lock();
-    virtual void unlock();
-    DigitalOut* _pin[16];
-
-    /** Mask of bus's NC pins
-     * If bit[n] is set to 1 - pin is connected
-     * if bit[n] is cleared - pin is not connected (NC)
-     */
-    int _nc_mask;
-
-    PlatformMutex _mutex;
-
-   /* disallow copy constructor and assignment operators */
-private:
-    BusOut(const BusOut&);
-    BusOut & operator = (const BusOut&);
-};
-
-} // namespace mbed
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/CAN.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,257 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CAN_H
-#define MBED_CAN_H
-
-#include "platform.h"
-
-#if DEVICE_CAN
-
-#include "can_api.h"
-#include "can_helper.h"
-#include "Callback.h"
-#include "PlatformMutex.h"
-
-namespace mbed {
-
-/** CANMessage class
- *
- * @Note Synchronization level: Thread safe
- */
-class CANMessage : public CAN_Message {
-
-public:
-    /** Creates empty CAN message.
-     */
-    CANMessage() : CAN_Message() {
-        len    = 8;
-        type   = CANData;
-        format = CANStandard;
-        id     = 0;
-        memset(data, 0, 8);
-    }
-
-    /** Creates CAN message with specific content.
-     */
-    CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {
-      len    = _len & 0xF;
-      type   = _type;
-      format = _format;
-      id     = _id;
-      memcpy(data, _data, _len);
-    }
-
-    /** Creates CAN remote message.
-     */
-    CANMessage(int _id, CANFormat _format = CANStandard) {
-      len    = 0;
-      type   = CANRemote;
-      format = _format;
-      id     = _id;
-      memset(data, 0, 8);
-    }
-};
-
-/** A can bus client, used for communicating with can devices
- */
-class CAN {
-
-public:
-    /** Creates an CAN interface connected to specific pins.
-     *
-     *  @param rd read from transmitter
-     *  @param td transmit to transmitter
-     *
-     * Example:
-     * @code
-     * #include "mbed.h"
-     *
-     * Ticker ticker;
-     * DigitalOut led1(LED1);
-     * DigitalOut led2(LED2);
-     * CAN can1(p9, p10);
-     * CAN can2(p30, p29);
-     *
-     * char counter = 0;
-     *
-     * void send() {
-     *     if(can1.write(CANMessage(1337, &counter, 1))) {
-     *         printf("Message sent: %d\n", counter);
-     *         counter++;
-     *     }
-     *     led1 = !led1;
-     * }
-     *
-     * int main() {
-     *     ticker.attach(&send, 1);
-     *    CANMessage msg;
-     *     while(1) {
-     *         if(can2.read(msg)) {
-     *             printf("Message received: %d\n\n", msg.data[0]);
-     *             led2 = !led2;
-     *         }
-     *         wait(0.2);
-     *     }
-     * }
-     * @endcode
-     */
-    CAN(PinName rd, PinName td);
-    virtual ~CAN();
-
-    /** Set the frequency of the CAN interface
-     *
-     *  @param hz The bus frequency in hertz
-     *
-     *  @returns
-     *    1 if successful,
-     *    0 otherwise
-     */
-    int frequency(int hz);
-
-    /** Write a CANMessage to the bus.
-     *
-     *  @param msg The CANMessage to write.
-     *
-     *  @returns
-     *    0 if write failed,
-     *    1 if write was successful
-     */
-    int write(CANMessage msg);
-
-    /** Read a CANMessage from the bus.
-     *
-     *  @param msg A CANMessage to read to.
-     *  @param handle message filter handle (0 for any message)
-     *
-     *  @returns
-     *    0 if no message arrived,
-     *    1 if message arrived
-     */
-    int read(CANMessage &msg, int handle = 0);
-
-    /** Reset CAN interface.
-     *
-     * To use after error overflow.
-     */
-    void reset();
-
-    /** Puts or removes the CAN interface into silent monitoring mode
-     *
-     *  @param silent boolean indicating whether to go into silent mode or not
-     */
-    void monitor(bool silent);
-
-    enum Mode {
-        Reset = 0,
-        Normal,
-        Silent,
-        LocalTest,
-        GlobalTest,
-        SilentTest
-    };
-
-    /** Change CAN operation to the specified mode
-     *
-     *  @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest)
-     *
-     *  @returns
-     *    0 if mode change failed or unsupported,
-     *    1 if mode change was successful
-     */
-    int mode(Mode mode);
-
-    /** Filter out incomming messages
-     *
-     *  @param id the id to filter on
-     *  @param mask the mask applied to the id
-     *  @param format format to filter on (Default CANAny)
-     *  @param handle message filter handle (Optional)
-     *
-     *  @returns
-     *    0 if filter change failed or unsupported,
-     *    new filter handle if successful
-     */
-    int filter(unsigned int id, unsigned int mask, CANFormat format = CANAny, int handle = 0);
-
-    /** Returns number of read errors to detect read overflow errors.
-     */
-    unsigned char rderror();
-
-    /** Returns number of write errors to detect write overflow errors.
-     */
-    unsigned char tderror();
-
-    enum IrqType {
-        RxIrq = 0,
-        TxIrq,
-        EwIrq,
-        DoIrq,
-        WuIrq,
-        EpIrq,
-        AlIrq,
-        BeIrq,
-        IdIrq
-    };
-
-    /** Attach a function to call whenever a CAN frame received interrupt is
-     *  generated.
-     *
-     *  @param func A pointer to a void function, or 0 to set as none
-     *  @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error)
-     */
-    void attach(Callback<void()> func, IrqType type=RxIrq);
-
-   /** Attach a member function to call whenever a CAN frame received interrupt
-    *  is generated.
-    *
-    *  @param obj pointer to the object to call the member function on
-    *  @param method pointer to the member function to be called
-    *  @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
-    */
-    template<typename T>
-    void attach(T* obj, void (T::*method)(), IrqType type=RxIrq) {
-        // Underlying call thread safe
-        attach(Callback<void()>(obj, method), type);
-    }
-
-   /** Attach a member function to call whenever a CAN frame received interrupt
-    *  is generated.
-    *
-    *  @param obj pointer to the object to call the member function on
-    *  @param method pointer to the member function to be called
-    *  @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
-    */
-    template<typename T>
-    void attach(T* obj, void (*method)(T*), IrqType type=RxIrq) {
-        // Underlying call thread safe
-        attach(Callback<void()>(obj, method), type);
-    }
-
-    static void _irq_handler(uint32_t id, CanIrqType type);
-
-protected:
-    virtual void lock();
-    virtual void unlock();
-    can_t               _can;
-    Callback<void()>    _irq[9];
-    PlatformMutex       _mutex;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif    // MBED_CAN_H

--- a/M24SR-DISCOVERY_hardware/mbed/CThunk.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,234 +0,0 @@
-/* General C++ Object Thunking class
- *
- * - allows direct callbacks to non-static C++ class functions
- * - keeps track for the corresponding class instance
- * - supports an optional context parameter for the called function
- * - ideally suited for class object receiving interrupts (NVIC_SetVector)
- *
- * Copyright (c) 2014-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/* General C++ Object Thunking class
- *
- * - allows direct callbacks to non-static C++ class functions
- * - keeps track for the corresponding class instance
- * - supports an optional context parameter for the called function
- * - ideally suited for class object receiving interrupts (NVIC_SetVector)
- */
-
-#ifndef __CTHUNK_H__
-#define __CTHUNK_H__
-
-#define CTHUNK_ADDRESS 1
-
-#if (defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__thumb2__)) && ! defined(__CORTEX_A9)
-#define CTHUNK_VARIABLES volatile uint32_t code[1]
-/**
-* CTHUNK disassembly for Cortex-M3/M4 (thumb2):
-* * ldm.w pc,{r0,r1,r2,pc}
-*
-* This instruction loads the arguments for the static thunking function to r0-r2, and
-* branches to that function by loading its address into PC.
-*
-* This is safe for both regular calling and interrupt calling, since it only touches scratch registers
-* which should be saved by the caller, and are automatically saved as part of the IRQ context switch.
-*/
-#define CTHUNK_ASSIGMENT m_thunk.code[0] = 0x8007E89F
-
-#elif defined(__CORTEX_M0PLUS) || defined(__CORTEX_M0) || defined(__CORTEX_A9)
-/*
-* CTHUNK disassembly for Cortex M0 (thumb):
-* * push {r0,r1,r2,r3,r4,lr} save touched registers and return address
-* * movs r4,#4 set up address to load arguments from (immediately following this code block) (1)
-* * add r4,pc set up address to load arguments from (immediately following this code block) (2)
-* * ldm r4!,{r0,r1,r2,r3} load arguments for static thunk function
-* * blx r3 call static thunk function
-* * pop {r0,r1,r2,r3,r4,pc} restore scratch registers and return from function
-*/
-#define CTHUNK_VARIABLES volatile uint32_t code[3]
-#define CTHUNK_ASSIGMENT do {                              \
-                             m_thunk.code[0] = 0x2404B51F; \
-                             m_thunk.code[1] = 0xCC0F447C; \
-                             m_thunk.code[2] = 0xBD1F4798; \
-                         } while (0)
-
-#else
-#error "Target is not currently suported."
-#endif
-
-/* IRQ/Exception compatible thunk entry function */
-typedef void (*CThunkEntry)(void);
-
-/**
- * Class for created a pointer with data bound to it
- *
- * @Note Synchronization level: Not protected
- */
-template<class T>
-class CThunk
-{
-    public:
-        typedef void (T::*CCallbackSimple)(void);
-        typedef void (T::*CCallback)(void* context);
-
-        inline CThunk(T *instance)
-        {
-            init(instance, NULL, NULL);
-        }
-
-        inline CThunk(T *instance, CCallback callback)
-        {
-            init(instance, callback, NULL);
-        }
-
-        ~CThunk() {
-
-        }
-
-        inline CThunk(T *instance, CCallbackSimple callback)
-        {
-            init(instance, (CCallback)callback, NULL);
-        }
-
-        inline CThunk(T &instance, CCallback callback)
-        {
-            init(instance, callback, NULL);
-        }
-
-        inline CThunk(T &instance, CCallbackSimple callback)
-        {
-            init(instance, (CCallback)callback, NULL);
-        }
-
-        inline CThunk(T &instance, CCallback callback, void* context)
-        {
-            init(instance, callback, context);
-        }
-
-        inline void callback(CCallback callback)
-        {
-            m_callback = callback;
-        }
-
-        inline void callback(CCallbackSimple callback)
-        {
-            m_callback = (CCallback)callback;
-        }
-
-        inline void context(void* context)
-        {
-            m_thunk.context = (uint32_t)context;
-        }
-
-        inline void context(uint32_t context)
-        {
-            m_thunk.context = context;
-        }
-        
-        inline uint32_t entry(void)
-        {
-            return (((uint32_t)&m_thunk)|CTHUNK_ADDRESS);
-        }
-
-        /* get thunk entry point for connecting rhunk to an IRQ table */
-        inline operator CThunkEntry(void)
-        {
-            return (CThunkEntry)entry();
-        }
-
-        /* get thunk entry point for connecting rhunk to an IRQ table */
-        inline operator uint32_t(void)
-        {
-            return entry();
-        }
-
-        /* simple test function */
-        inline void call(void)
-        {
-            (((CThunkEntry)(entry()))());
-        }
-
-    private:
-        T* m_instance;
-        volatile CCallback m_callback;
-
-// TODO: this needs proper fix, to refactor toolchain header file and all its use
-// PACKED there is not defined properly for IAR
-#if defined (__ICCARM__)
-        typedef __packed struct
-        {
-            CTHUNK_VARIABLES;
-            volatile uint32_t instance;
-            volatile uint32_t context;
-            volatile uint32_t callback;
-            volatile uint32_t trampoline;
-        }  CThunkTrampoline;
-#else
-        typedef struct
-        {
-            CTHUNK_VARIABLES;
-            volatile uint32_t instance;
-            volatile uint32_t context;
-            volatile uint32_t callback;
-            volatile uint32_t trampoline;
-        } __attribute__((__packed__)) CThunkTrampoline;
-#endif
-
-        static void trampoline(T* instance, void* context, CCallback* callback)
-        {
-            if(instance && *callback) {
-                (static_cast<T*>(instance)->**callback)(context);
-            }
-        }
-
-        volatile CThunkTrampoline m_thunk;
-
-        inline void init(T *instance, CCallback callback, void* context)
-        {
-            /* remember callback - need to add this level of redirection
-               as pointer size for member functions differs between platforms */
-            m_callback = callback;
-
-            /* populate thunking trampoline */
-            CTHUNK_ASSIGMENT;
-            m_thunk.context = (uint32_t)context;
-            m_thunk.instance = (uint32_t)instance;
-            m_thunk.callback = (uint32_t)&m_callback;
-            m_thunk.trampoline = (uint32_t)&trampoline;
-
-#if defined(__CORTEX_A9)
-            /* Data cache clean */
-            /* Cache control */
-            {
-                uint32_t start_addr = (uint32_t)&m_thunk & 0xFFFFFFE0;
-                uint32_t end_addr   = (uint32_t)&m_thunk + sizeof(m_thunk);
-                uint32_t addr;
-                
-                /* Data cache clean and invalid */
-                for (addr = start_addr; addr < end_addr; addr += 0x20) {
-                    __v7_clean_inv_dcache_mva((void *)addr);
-                }
-                /* Instruction cache invalid */
-                __v7_inv_icache_all();
-                __ca9u_inv_tlb_all();
-                __v7_inv_btac();
-            }
-#endif
-            __ISB();
-            __DSB();
-        }
-};
-
-#endif/*__CTHUNK_H__*/

--- a/M24SR-DISCOVERY_hardware/mbed/CallChain.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,173 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CALLCHAIN_H
-#define MBED_CALLCHAIN_H
-
-#include "Callback.h"
-#include <string.h>
-
-namespace mbed {
-
-/** Group one or more functions in an instance of a CallChain, then call them in
- * sequence using CallChain::call(). Used mostly by the interrupt chaining code,
- * but can be used for other purposes.
- *
- * @Note Synchronization level: Not protected
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * CallChain chain;
- *
- * void first(void) {
- *     printf("'first' function.\n");
- * }
- *
- * void second(void) {
- *     printf("'second' function.\n");
- * }
- *
- * class Test {
- * public:
- *     void f(void) {
- *         printf("A::f (class member).\n");
- *     }
- * };
- *
- * int main() {
- *     Test test;
- *
- *     chain.add(second);
- *     chain.add_front(first);
- *     chain.add(&test, &Test::f);
- *     chain.call();
- * }
- * @endcode
- */
-
-typedef Callback<void()> *pFunctionPointer_t;
-class CallChainLink;
-
-class CallChain {
-public:
-    /** Create an empty chain
-     *
-     *  @param size (optional) Initial size of the chain
-     */
-    CallChain(int size = 4);
-    virtual ~CallChain();
-
-    /** Add a function at the end of the chain
-     *
-     *  @param func A pointer to a void function
-     *
-     *  @returns
-     *  The function object created for 'func'
-     */
-    pFunctionPointer_t add(Callback<void()> func);
-
-    /** Add a function at the end of the chain
-     *
-     *  @param obj pointer to the object to call the member function on
-     *  @param method pointer to the member function to be called
-     *
-     *  @returns
-     *  The function object created for 'obj' and 'method'
-     */
-    template<typename T, typename M>
-    pFunctionPointer_t add(T *obj, M method) {
-        return add(Callback<void()>(obj, method));
-    }
-
-    /** Add a function at the beginning of the chain
-     *
-     *  @param func A pointer to a void function
-     *
-     *  @returns
-     *  The function object created for 'func'
-     */
-    pFunctionPointer_t add_front(Callback<void()> func);
-
-    /** Add a function at the beginning of the chain
-     *
-     *  @param tptr pointer to the object to call the member function on
-     *  @param mptr pointer to the member function to be called
-     *
-     *  @returns
-     *  The function object created for 'tptr' and 'mptr'
-     */
-    template<typename T, typename M>
-    pFunctionPointer_t add_front(T *obj, M method) {
-        return add_front(Callback<void()>(obj, method));
-    }
-
-    /** Get the number of functions in the chain
-     */
-    int size() const;
-
-    /** Get a function object from the chain
-     *
-     *  @param i function object index
-     *
-     *  @returns
-     *  The function object at position 'i' in the chain
-     */
-    pFunctionPointer_t get(int i) const;
-
-    /** Look for a function object in the call chain
-     *
-     *  @param f the function object to search
-     *
-     *  @returns
-     *  The index of the function object if found, -1 otherwise.
-     */
-    int find(pFunctionPointer_t f) const;
-
-    /** Clear the call chain (remove all functions in the chain).
-     */
-    void clear();
-
-    /** Remove a function object from the chain
-     *
-     *  @arg f the function object to remove
-     *
-     *  @returns
-     *  true if the function object was found and removed, false otherwise.
-     */
-    bool remove(pFunctionPointer_t f);
-
-    /** Call all the functions in the chain in sequence
-     */
-    void call();
-
-    void operator ()(void) {
-        call();
-    }
-    pFunctionPointer_t operator [](int i) const {
-        return get(i);
-    }
-
-    /* disallow copy constructor and assignment operators */
-private:
-    CallChain(const CallChain&);
-    CallChain & operator = (const CallChain&);
-    CallChainLink *_chain;
-};
-
-} // namespace mbed
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/Callback.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,883 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CALLBACK_H
-#define MBED_CALLBACK_H
-
-#include <string.h>
-#include <stdint.h>
-
-namespace mbed {
-
-
-/** Callback class based on template specialization
- *
- * @Note Synchronization level: Not protected
- */
-template <typename F>
-class Callback;
-
-/** Templated function class
- */
-template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
-class Callback<R(A0, A1, A2, A3, A4)> {
-public:
-    /** Create a Callback with a static function
-     *  @param func Static function to attach
-     */
-    Callback(R (*func)(A0, A1, A2, A3, A4) = 0) {
-        attach(func);
-    }
-
-    /** Create a Callback with a static function and bound pointer
-     *  @param obj  Pointer to object to bind to function
-     *  @param func Static function to attach
-     */
-    template<typename T>
-    Callback(T *obj, R (*func)(T*, A0, A1, A2, A3, A4)) {
-        attach(obj, func);
-    }
-
-    /** Create a Callback with a member function
-     *  @param obj  Pointer to object to invoke member function on
-     *  @param func Member function to attach
-     */
-    template<typename T>
-    Callback(T *obj, R (T::*func)(A0, A1, A2, A3, A4)) {
-        attach(obj, func);
-    }
-
-    /** Create a Callback with another Callback
-     *  @param func Callback to attach
-     */
-    Callback(const Callback<R(A0, A1, A2, A3, A4)> &func) {
-        attach(func);
-    }
-
-    /** Attach a static function
-     *  @param func Static function to attach
-     */
-    void attach(R (*func)(A0, A1, A2, A3, A4)) {
-        memcpy(&_func, &func, sizeof func);
-        _thunk = func ? &Callback::_staticthunk : 0;
-    }
-
-    /** Attach a static function with a bound pointer
-     *  @param obj  Pointer to object to bind to function
-     *  @param func Static function to attach
-     */
-    template <typename T>
-    void attach(T *obj, R (*func)(T*, A0, A1, A2, A3, A4)) {
-        _obj = (void*)obj;
-        memcpy(&_func, &func, sizeof func);
-        _thunk = &Callback::_boundthunk<T>;
-    }
-
-    /** Attach a member function
-     *  @param obj  Pointer to object to invoke member function on
-     *  @param func Member function to attach
-     */
-    template<typename T>
-    void attach(T *obj, R (T::*func)(A0, A1, A2, A3, A4)) {
-        _obj = static_cast<void*>(obj);
-        memcpy(&_func, &func, sizeof func);
-        _thunk = &Callback::_methodthunk<T>;
-    }
-
-    /** Attach a Callback
-     *  @param func The Callback to attach
-     */
-    void attach(const Callback<R(A0, A1, A2, A3, A4)> &func) {
-        _obj = func._obj;
-        memcpy(&_func, &func._func, sizeof _func);
-        _thunk = func._thunk;
-    }
-
-    /** Call the attached function
-     */
-    R call(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
-        if (!_thunk) {
-            return (R)0;
-        }
-        return _thunk(_obj, &_func, a0, a1, a2, a3, a4);
-    }
-
-    /** Call the attached function
-     */
-    R operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
-        return call(a0, a1, a2, a3, a4);
-    }
-
-    /** Test if function has been attached
-     */
-    operator bool() const {
-        return _thunk;
-    }
-
-    /** Static thunk for passing as C-style function
-     *  @param func Callback to call passed as void pointer
-     */
-    static R thunk(void *func, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
-        return static_cast<Callback<R(A0, A1, A2, A3, A4)>*>(func)
-                ->call(a0, a1, a2, a3, a4);
-    }
-
-private:
-    // Internal thunks for various function types
-    static R _staticthunk(void*, void *func, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
-        return (*reinterpret_cast<R (**)(A0, A1, A2, A3, A4)>(func))
-                (a0, a1, a2, a3, a4);
-    }
-
-    template<typename T>
-    static R _boundthunk(void *obj, void *func, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
-        return (*reinterpret_cast<R (**)(T*, A0, A1, A2, A3, A4)>(func))
-                (static_cast<T*>(obj), a0, a1, a2, a3, a4);
-    }
-
-    template<typename T>
-    static R _methodthunk(void *obj, void *func, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
-        return (static_cast<T*>(obj)->*
-                (*reinterpret_cast<R (T::**)(A0, A1, A2, A3, A4)>(func)))
-                (a0, a1, a2, a3, a4);
-    }
-
-    // Stored as pointer to function and pointer to optional object
-    // Function pointer is stored as union of possible function types
-    // to garuntee proper size and alignment
-    struct _class;
-    union {
-        void (*_staticfunc)();
-        void (*_boundfunc)(_class *);
-        void (_class::*_methodfunc)();
-    } _func;
-
-    void *_obj;
-
-    // Thunk registered on attach to dispatch calls
-    R (*_thunk)(void*, void*, A0, A1, A2, A3, A4); 
-};
-
-/** Templated function class
- */
-template <typename R, typename A0, typename A1, typename A2, typename A3>
-class Callback<R(A0, A1, A2, A3)> {
-public:
-    /** Create a Callback with a static function
-     *  @param func Static function to attach
-     */
-    Callback(R (*func)(A0, A1, A2, A3) = 0) {
-        attach(func);
-    }
-
-    /** Create a Callback with a static function and bound pointer
-     *  @param obj  Pointer to object to bind to function
-     *  @param func Static function to attach
-     */
-    template<typename T>
-    Callback(T *obj, R (*func)(T*, A0, A1, A2, A3)) {
-        attach(obj, func);
-    }
-
-    /** Create a Callback with a member function
-     *  @param obj  Pointer to object to invoke member function on
-     *  @param func Member function to attach
-     */
-    template<typename T>
-    Callback(T *obj, R (T::*func)(A0, A1, A2, A3)) {
-        attach(obj, func);
-    }
-
-    /** Create a Callback with another Callback
-     *  @param func Callback to attach
-     */
-    Callback(const Callback<R(A0, A1, A2, A3)> &func) {
-        attach(func);
-    }
-
-    /** Attach a static function
-     *  @param func Static function to attach
-     */
-    void attach(R (*func)(A0, A1, A2, A3)) {
-        memcpy(&_func, &func, sizeof func);
-        _thunk = func ? &Callback::_staticthunk : 0;
-    }
-
-    /** Attach a static function with a bound pointer
-     *  @param obj  Pointer to object to bind to function
-     *  @param func Static function to attach
-     */
-    template <typename T>
-    void attach(T *obj, R (*func)(T*, A0, A1, A2, A3)) {
-        _obj = (void*)obj;
-        memcpy(&_func, &func, sizeof func);
-        _thunk = &Callback::_boundthunk<T>;
-    }
-
-    /** Attach a member function
-     *  @param obj  Pointer to object to invoke member function on
-     *  @param func Member function to attach
-     */
-    template<typename T>
-    void attach(T *obj, R (T::*func)(A0, A1, A2, A3)) {
-        _obj = static_cast<void*>(obj);
-        memcpy(&_func, &func, sizeof func);
-        _thunk = &Callback::_methodthunk<T>;
-    }
-
-    /** Attach a Callback
-     *  @param func The Callback to attach
-     */
-    void attach(const Callback<R(A0, A1, A2, A3)> &func) {
-        _obj = func._obj;
-        memcpy(&_func, &func._func, sizeof _func);
-        _thunk = func._thunk;
-    }
-
-    /** Call the attached function
-     */
-    R call(A0 a0, A1 a1, A2 a2, A3 a3) {
-        if (!_thunk) {
-            return (R)0;
-        }
-        return _thunk(_obj, &_func, a0, a1, a2, a3);
-    }
-
-    /** Call the attached function
-     */
-    R operator()(A0 a0, A1 a1, A2 a2, A3 a3) {
-        return call(a0, a1, a2, a3);
-    }
-
-    /** Test if function has been attached
-     */
-    operator bool() const {
-        return _thunk;
-    }
-
-    /** Static thunk for passing as C-style function
-     *  @param func Callback to call passed as void pointer
-     */
-    static R thunk(void *func, A0 a0, A1 a1, A2 a2, A3 a3) {
-        return static_cast<Callback<R(A0, A1, A2, A3)>*>(func)
-                ->call(a0, a1, a2, a3);
-    }
-
-private:
-    // Internal thunks for various function types
-    static R _staticthunk(void*, void *func, A0 a0, A1 a1, A2 a2, A3 a3) {
-        return (*reinterpret_cast<R (**)(A0, A1, A2, A3)>(func))
-                (a0, a1, a2, a3);
-    }
-
-    template<typename T>
-    static R _boundthunk(void *obj, void *func, A0 a0, A1 a1, A2 a2, A3 a3) {
-        return (*reinterpret_cast<R (**)(T*, A0, A1, A2, A3)>(func))
-                (static_cast<T*>(obj), a0, a1, a2, a3);
-    }
-
-    template<typename T>
-    static R _methodthunk(void *obj, void *func, A0 a0, A1 a1, A2 a2, A3 a3) {
-        return (static_cast<T*>(obj)->*
-                (*reinterpret_cast<R (T::**)(A0, A1, A2, A3)>(func)))
-                (a0, a1, a2, a3);
-    }
-
-    // Stored as pointer to function and pointer to optional object
-    // Function pointer is stored as union of possible function types
-    // to garuntee proper size and alignment
-    struct _class;
-    union {
-        void (*_staticfunc)();
-        void (*_boundfunc)(_class *);
-        void (_class::*_methodfunc)();
-    } _func;
-
-    void *_obj;
-
-    // Thunk registered on attach to dispatch calls
-    R (*_thunk)(void*, void*, A0, A1, A2, A3); 
-};
-
-/** Templated function class
- */
-template <typename R, typename A0, typename A1, typename A2>
-class Callback<R(A0, A1, A2)> {
-public:
-    /** Create a Callback with a static function
-     *  @param func Static function to attach
-     */
-    Callback(R (*func)(A0, A1, A2) = 0) {
-        attach(func);
-    }
-
-    /** Create a Callback with a static function and bound pointer
-     *  @param obj  Pointer to object to bind to function
-     *  @param func Static function to attach
-     */
-    template<typename T>
-    Callback(T *obj, R (*func)(T*, A0, A1, A2)) {
-        attach(obj, func);
-    }
-
-    /** Create a Callback with a member function
-     *  @param obj  Pointer to object to invoke member function on
-     *  @param func Member function to attach
-     */
-    template<typename T>
-    Callback(T *obj, R (T::*func)(A0, A1, A2)) {
-        attach(obj, func);
-    }
-
-    /** Create a Callback with another Callback
-     *  @param func Callback to attach
-     */
-    Callback(const Callback<R(A0, A1, A2)> &func) {
-        attach(func);
-    }
-
-    /** Attach a static function
-     *  @param func Static function to attach
-     */
-    void attach(R (*func)(A0, A1, A2)) {
-        memcpy(&_func, &func, sizeof func);
-        _thunk = func ? &Callback::_staticthunk : 0;
-    }
-
-    /** Attach a static function with a bound pointer
-     *  @param obj  Pointer to object to bind to function
-     *  @param func Static function to attach
-     */
-    template <typename T>
-    void attach(T *obj, R (*func)(T*, A0, A1, A2)) {
-        _obj = (void*)obj;
-        memcpy(&_func, &func, sizeof func);
-        _thunk = &Callback::_boundthunk<T>;
-    }
-
-    /** Attach a member function
-     *  @param obj  Pointer to object to invoke member function on
-     *  @param func Member function to attach
-     */
-    template<typename T>
-    void attach(T *obj, R (T::*func)(A0, A1, A2)) {
-        _obj = static_cast<void*>(obj);
-        memcpy(&_func, &func, sizeof func);
-        _thunk = &Callback::_methodthunk<T>;
-    }
-
-    /** Attach a Callback
-     *  @param func The Callback to attach
-     */
-    void attach(const Callback<R(A0, A1, A2)> &func) {
-        _obj = func._obj;
-        memcpy(&_func, &func._func, sizeof _func);
-        _thunk = func._thunk;
-    }
-
-    /** Call the attached function
-     */
-    R call(A0 a0, A1 a1, A2 a2) {
-        if (!_thunk) {
-            return (R)0;
-        }
-        return _thunk(_obj, &_func, a0, a1, a2);
-    }
-
-    /** Call the attached function
-     */
-    R operator()(A0 a0, A1 a1, A2 a2) {
-        return call(a0, a1, a2);
-    }
-
-    /** Test if function has been attached
-     */
-    operator bool() const {
-        return _thunk;
-    }
-
-    /** Static thunk for passing as C-style function
-     *  @param func Callback to call passed as void pointer
-     */
-    static R thunk(void *func, A0 a0, A1 a1, A2 a2) {
-        return static_cast<Callback<R(A0, A1, A2)>*>(func)
-                ->call(a0, a1, a2);
-    }
-
-private:
-    // Internal thunks for various function types
-    static R _staticthunk(void*, void *func, A0 a0, A1 a1, A2 a2) {
-        return (*reinterpret_cast<R (**)(A0, A1, A2)>(func))
-                (a0, a1, a2);
-    }
-
-    template<typename T>
-    static R _boundthunk(void *obj, void *func, A0 a0, A1 a1, A2 a2) {
-        return (*reinterpret_cast<R (**)(T*, A0, A1, A2)>(func))
-                (static_cast<T*>(obj), a0, a1, a2);
-    }
-
-    template<typename T>
-    static R _methodthunk(void *obj, void *func, A0 a0, A1 a1, A2 a2) {
-        return (static_cast<T*>(obj)->*
-                (*reinterpret_cast<R (T::**)(A0, A1, A2)>(func)))
-                (a0, a1, a2);
-    }
-
-    // Stored as pointer to function and pointer to optional object
-    // Function pointer is stored as union of possible function types
-    // to garuntee proper size and alignment
-    struct _class;
-    union {
-        void (*_staticfunc)();
-        void (*_boundfunc)(_class *);
-        void (_class::*_methodfunc)();
-    } _func;
-
-    void *_obj;
-
-    // Thunk registered on attach to dispatch calls
-    R (*_thunk)(void*, void*, A0, A1, A2);
-};
-
-/** Templated function class
- */
-template <typename R, typename A0, typename A1>
-class Callback<R(A0, A1)> {
-public:
-    /** Create a Callback with a static function
-     *  @param func Static function to attach
-     */
-    Callback(R (*func)(A0, A1) = 0) {
-        attach(func);
-    }
-
-    /** Create a Callback with a static function and bound pointer
-     *  @param obj  Pointer to object to bind to function
-     *  @param func Static function to attach
-     */
-    template<typename T>
-    Callback(T *obj, R (*func)(T*, A0, A1)) {
-        attach(obj, func);
-    }
-
-    /** Create a Callback with a member function
-     *  @param obj  Pointer to object to invoke member function on
-     *  @param func Member function to attach
-     */
-    template<typename T>
-    Callback(T *obj, R (T::*func)(A0, A1)) {
-        attach(obj, func);
-    }
-
-    /** Create a Callback with another Callback
-     *  @param func Callback to attach
-     */
-    Callback(const Callback<R(A0, A1)> &func) {
-        attach(func);
-    }
-
-    /** Attach a static function
-     *  @param func Static function to attach
-     */
-    void attach(R (*func)(A0, A1)) {
-        memcpy(&_func, &func, sizeof func);
-        _thunk = func ? &Callback::_staticthunk : 0;
-    }
-
-    /** Attach a static function with a bound pointer
-     *  @param obj  Pointer to object to bind to function
-     *  @param func Static function to attach
-     */
-    template <typename T>
-    void attach(T *obj, R (*func)(T*, A0, A1)) {
-        _obj = (void*)obj;
-        memcpy(&_func, &func, sizeof func);
-        _thunk = &Callback::_boundthunk<T>;
-    }
-
-    /** Attach a member function
-     *  @param obj  Pointer to object to invoke member function on
-     *  @param func Member function to attach
-     */
-    template<typename T>
-    void attach(T *obj, R (T::*func)(A0, A1)) {
-        _obj = static_cast<void*>(obj);
-        memcpy(&_func, &func, sizeof func);
-        _thunk = &Callback::_methodthunk<T>;
-    }
-
-    /** Attach a Callback
-     *  @param func The Callback to attach
-     */
-    void attach(const Callback<R(A0, A1)> &func) {
-        _obj = func._obj;
-        memcpy(&_func, &func._func, sizeof _func);
-        _thunk = func._thunk;
-    }
-
-    /** Call the attached function
-     */
-    R call(A0 a0, A1 a1) {
-        if (!_thunk) {
-            return (R)0;
-        }
-        return _thunk(_obj, &_func, a0, a1);
-    }
-
-    /** Call the attached function
-     */
-    R operator()(A0 a0, A1 a1) {
-        return call(a0, a1);
-    }
-
-    /** Test if function has been attached
-     */
-    operator bool() const {
-        return _thunk;
-    }
-
-    /** Static thunk for passing as C-style function
-     *  @param func Callback to call passed as void pointer
-     */
-    static R thunk(void *func, A0 a0, A1 a1) {
-        return static_cast<Callback<R(A0, A1)>*>(func)
-                ->call(a0, a1);
-    }
-
-private:
-    // Internal thunks for various function types
-    static R _staticthunk(void*, void *func, A0 a0, A1 a1) {
-        return (*reinterpret_cast<R (**)(A0, A1)>(func))
-                (a0, a1);
-    }
-
-    template<typename T>
-    static R _boundthunk(void *obj, void *func, A0 a0, A1 a1) {
-        return (*reinterpret_cast<R (**)(T*, A0, A1)>(func))
-                (static_cast<T*>(obj), a0, a1);
-    }
-
-    template<typename T>
-    static R _methodthunk(void *obj, void *func, A0 a0, A1 a1) {
-        return (static_cast<T*>(obj)->*
-                (*reinterpret_cast<R (T::**)(A0, A1)>(func)))
-                (a0, a1);
-    }
-
-    // Stored as pointer to function and pointer to optional object
-    // Function pointer is stored as union of possible function types
-    // to garuntee proper size and alignment
-    struct _class;
-    union {
-        void (*_staticfunc)();
-        void (*_boundfunc)(_class *);
-        void (_class::*_methodfunc)();
-    } _func;
-
-    void *_obj;
-
-    // Thunk registered on attach to dispatch calls
-    R (*_thunk)(void*, void*, A0, A1); 
-};
-
-/** Templated function class
- */
-template <typename R, typename A0>
-class Callback<R(A0)> {
-public:
-    /** Create a Callback with a static function
-     *  @param func Static function to attach
-     */
-    Callback(R (*func)(A0) = 0) {
-        attach(func);
-    }
-
-    /** Create a Callback with a static function and bound pointer
-     *  @param obj  Pointer to object to bind to function
-     *  @param func Static function to attach
-     */
-    template<typename T>
-    Callback(T *obj, R (*func)(T*, A0)) {
-        attach(obj, func);
-    }
-
-    /** Create a Callback with a member function
-     *  @param obj  Pointer to object to invoke member function on
-     *  @param func Member function to attach
-     */
-    template<typename T>
-    Callback(T *obj, R (T::*func)(A0)) {
-        attach(obj, func);
-    }
-
-    /** Create a Callback with another Callback
-     *  @param func Callback to attach
-     */
-    Callback(const Callback<R(A0)> &func) {
-        attach(func);
-    }
-
-    /** Attach a static function
-     *  @param func Static function to attach
-     */
-    void attach(R (*func)(A0)) {
-        memcpy(&_func, &func, sizeof func);
-        _thunk = func ? &Callback::_staticthunk : 0;
-    }
-
-    /** Attach a static function with a bound pointer
-     *  @param obj  Pointer to object to bind to function
-     *  @param func Static function to attach
-     */
-    template <typename T>
-    void attach(T *obj, R (*func)(T*, A0)) {
-        _obj = (void*)obj;
-        memcpy(&_func, &func, sizeof func);
-        _thunk = &Callback::_boundthunk<T>;
-    }
-
-    /** Attach a member function
-     *  @param obj  Pointer to object to invoke member function on
-     *  @param func Member function to attach
-     */
-    template<typename T>
-    void attach(T *obj, R (T::*func)(A0)) {
-        _obj = static_cast<void*>(obj);
-        memcpy(&_func, &func, sizeof func);
-        _thunk = &Callback::_methodthunk<T>;
-    }
-
-    /** Attach a Callback
-     *  @param func The Callback to attach
-     */
-    void attach(const Callback<R(A0)> &func) {
-        _obj = func._obj;
-        memcpy(&_func, &func._func, sizeof _func);
-        _thunk = func._thunk;
-    }
-
-    /** Call the attached function
-     */
-    R call(A0 a0) {
-        if (!_thunk) {
-            return (R)0;
-        }
-        return _thunk(_obj, &_func, a0);
-    }
-
-    /** Call the attached function
-     */
-    R operator()(A0 a0) {
-        return call(a0);
-    }
-
-    /** Test if function has been attached
-     */
-    operator bool() const {
-        return _thunk;
-    }
-
-    /** Static thunk for passing as C-style function
-     *  @param func Callback to call passed as void pointer
-     */
-    static R thunk(void *func, A0 a0) {
-        return static_cast<Callback<R(A0)>*>(func)
-                ->call(a0);
-    }
-
-private:
-    // Internal thunks for various function types
-    static R _staticthunk(void*, void *func, A0 a0) {
-        return (*reinterpret_cast<R (**)(A0)>(func))
-                (a0);
-    }
-
-    template<typename T>
-    static R _boundthunk(void *obj, void *func, A0 a0) {
-        return (*reinterpret_cast<R (**)(T*, A0)>(func))
-                (static_cast<T*>(obj), a0);
-    }
-
-    template<typename T>
-    static R _methodthunk(void *obj, void *func, A0 a0) {
-        return (static_cast<T*>(obj)->*
-                (*reinterpret_cast<R (T::**)(A0)>(func)))
-                (a0);
-    }
-
-    // Stored as pointer to function and pointer to optional object
-    // Function pointer is stored as union of possible function types
-    // to garuntee proper size and alignment
-    struct _class;
-    union {
-        void (*_staticfunc)();
-        void (*_boundfunc)(_class *);
-        void (_class::*_methodfunc)();
-    } _func;
-
-    void *_obj;
-
-    // Thunk registered on attach to dispatch calls
-    R (*_thunk)(void*, void*, A0); 
-};
-
-/** Templated function class
- */
-template <typename R>
-class Callback<R()> {
-public:
-    /** Create a Callback with a static function
-     *  @param func Static function to attach
-     */
-    Callback(R (*func)() = 0) {
-        attach(func);
-    }
-
-    /** Create a Callback with a static function and bound pointer
-     *  @param obj  Pointer to object to bind to function
-     *  @param func Static function to attach
-     */
-    template<typename T>
-    Callback(T *obj, R (*func)(T*)) {
-        attach(obj, func);
-    }
-
-    /** Create a Callback with a member function
-     *  @param obj  Pointer to object to invoke member function on
-     *  @param func Member function to attach
-     */
-    template<typename T>
-    Callback(T *obj, R (T::*func)()) {
-        attach(obj, func);
-    }
-
-    /** Create a Callback with another Callback
-     *  @param func Callback to attach
-     */
-    Callback(const Callback<R()> &func) {
-        attach(func);
-    }
-
-    /** Attach a static function
-     *  @param func Static function to attach
-     */
-    void attach(R (*func)()) {
-        memcpy(&_func, &func, sizeof func);
-        _thunk = func ? &Callback::_staticthunk : 0;
-    }
-
-    /** Attach a static function with a bound pointer
-     *  @param obj  Pointer to object to bind to function
-     *  @param func Static function to attach
-     */
-    template <typename T>
-    void attach(T *obj, R (*func)(T*)) {
-        _obj = (void*)obj;
-        memcpy(&_func, &func, sizeof func);
-        _thunk = &Callback::_boundthunk<T>;
-    }
-
-    /** Attach a member function
-     *  @param obj  Pointer to object to invoke member function on
-     *  @param func Member function to attach
-     */
-    template<typename T>
-    void attach(T *obj, R (T::*func)()) {
-        _obj = static_cast<void*>(obj);
-        memcpy(&_func, &func, sizeof func);
-        _thunk = &Callback::_methodthunk<T>;
-    }
-
-    /** Attach a Callback
-     *  @param func The Callback to attach
-     */
-    void attach(const Callback<R()> &func) {
-        _obj = func._obj;
-        memcpy(&_func, &func._func, sizeof _func);
-        _thunk = func._thunk;
-    }
-
-    /** Call the attached function
-     */
-    R call() {
-        if (!_thunk) {
-            return (R)0;
-        }
-        return _thunk(_obj, &_func);
-    }
-
-    /** Call the attached function
-     */
-    R operator()() {
-        return call();
-    }
-
-    /** Test if function has been attached
-     */
-    operator bool() const {
-        return _thunk;
-    }
-
-    /** Static thunk for passing as C-style function
-     *  @param func Callback to call passed as void pointer
-     */
-    static R thunk(void *func) {
-        return static_cast<Callback<R()>*>(func)
-                ->call();
-    }
-
-private:
-    // Internal thunks for various function types
-    static R _staticthunk(void*, void *func) {
-        return (*reinterpret_cast<R (**)()>(func))
-                ();
-    }
-
-    template<typename T>
-    static R _boundthunk(void *obj, void *func) {
-        return (*reinterpret_cast<R (**)(T*)>(func))
-                (static_cast<T*>(obj));
-    }
-
-    template<typename T>
-    static R _methodthunk(void *obj, void *func) {
-        return (static_cast<T*>(obj)->*
-                (*reinterpret_cast<R (T::**)()>(func)))
-                ();
-    }
-
-    // Stored as pointer to function and pointer to optional object
-    // Function pointer is stored as union of possible function types
-    // to garuntee proper size and alignment
-    struct _class;
-    union {
-        void (*_staticfunc)();
-        void (*_boundfunc)(_class *);
-        void (_class::*_methodfunc)();
-    } _func;
-
-    void *_obj;
-
-    // Thunk registered on attach to dispatch calls
-    R (*_thunk)(void*, void*); 
-};
-
- typedef Callback<void(int)> event_callback_t;
-
-
-} // namespace mbed
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/CircularBuffer.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,115 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CIRCULARBUFFER_H
-#define MBED_CIRCULARBUFFER_H
-
-#include "critical.h"
-
-namespace mbed {
-
-/** Templated Circular buffer class
- *
- *  @Note Synchronization level: Interrupt safe
- */
-template<typename T, uint32_t BufferSize, typename CounterType = uint32_t>
-class CircularBuffer {
-public:
-    CircularBuffer() : _head(0), _tail(0), _full(false) {
-    }
-
-    ~CircularBuffer() {
-    }
-
-    /** Push the transaction to the buffer. This overwrites the buffer if it's
-     *  full
-     *
-     * @param data Data to be pushed to the buffer
-     */
-    void push(const T& data) {
-        core_util_critical_section_enter();
-        if (full()) {
-            _tail++;
-            _tail %= BufferSize;
-        }
-        _pool[_head++] = data;
-        _head %= BufferSize;
-        if (_head == _tail) {
-            _full = true;
-        }
-        core_util_critical_section_exit();
-    }
-
-    /** Pop the transaction from the buffer
-     *
-     * @param data Data to be pushed to the buffer
-     * @return True if the buffer is not empty and data contains a transaction, false otherwise
-     */
-    bool pop(T& data) {
-        bool data_popped = false;
-        core_util_critical_section_enter();
-        if (!empty()) {
-            data = _pool[_tail++];
-            _tail %= BufferSize;
-            _full = false;
-            data_popped = true;
-        }
-        core_util_critical_section_exit();
-        return data_popped;
-    }
-
-    /** Check if the buffer is empty
-     *
-     * @return True if the buffer is empty, false if not
-     */
-    bool empty() {
-        core_util_critical_section_enter();
-        bool is_empty = (_head == _tail) && !_full;
-        core_util_critical_section_exit();
-        return is_empty;
-    }
-
-    /** Check if the buffer is full
-     *
-     * @return True if the buffer is full, false if not
-     */
-    bool full() {
-        core_util_critical_section_enter();
-        bool full = _full;
-        core_util_critical_section_exit();
-        return full;
-    }
-
-    /** Reset the buffer
-     *
-     */
-    void reset() {
-        core_util_critical_section_enter();
-        _head = 0;
-        _tail = 0;
-        _full = false;
-        core_util_critical_section_exit();
-    }
-
-private:
-    T _pool[BufferSize];
-    volatile CounterType _head;
-    volatile CounterType _tail;
-    volatile bool _full;
-};
-
-}
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/DigitalIn.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,115 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIGITALIN_H
-#define MBED_DIGITALIN_H
-
-#include "platform.h"
-
-#include "gpio_api.h"
-#include "critical.h"
-
-namespace mbed {
-
-/** A digital input, used for reading the state of a pin
- *
- * @Note Synchronization level: Interrupt safe
- *
- * Example:
- * @code
- * // Flash an LED while a DigitalIn is true
- *
- * #include "mbed.h"
- *
- * DigitalIn enable(p5);
- * DigitalOut led(LED1);
- *
- * int main() {
- *     while(1) {
- *         if(enable) {
- *             led = !led;
- *         }
- *         wait(0.25);
- *     }
- * }
- * @endcode
- */
-class DigitalIn {
-
-public:
-    /** Create a DigitalIn connected to the specified pin
-     *
-     *  @param pin DigitalIn pin to connect to
-     */
-    DigitalIn(PinName pin) : gpio() {
-        // No lock needed in the constructor
-        gpio_init_in(&gpio, pin);
-    }
-
-    /** Create a DigitalIn connected to the specified pin
-     *
-     *  @param pin DigitalIn pin to connect to
-     *  @param mode the initial mode of the pin
-     */
-    DigitalIn(PinName pin, PinMode mode) : gpio() {
-        // No lock needed in the constructor
-        gpio_init_in_ex(&gpio, pin, mode);
-    }
-    /** Read the input, represented as 0 or 1 (int)
-     *
-     *  @returns
-     *    An integer representing the state of the input pin,
-     *    0 for logical 0, 1 for logical 1
-     */
-    int read() {
-        // Thread safe / atomic HAL call
-        return gpio_read(&gpio);
-    }
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone, OpenDrain
-     */
-    void mode(PinMode pull) {
-        core_util_critical_section_enter();
-        gpio_mode(&gpio, pull);
-        core_util_critical_section_exit();
-    }
-
-    /** Return the output setting, represented as 0 or 1 (int)
-     *
-     *  @returns
-     *    Non zero value if pin is connected to uc GPIO
-     *    0 if gpio object was initialized with NC
-     */
-    int is_connected() {
-        // Thread safe / atomic HAL call
-        return gpio_is_connected(&gpio);
-    }
-
-    /** An operator shorthand for read()
-     */
-    operator int() {
-        // Underlying read is thread safe
-        return read();
-    }
-
-protected:
-    gpio_t gpio;
-};
-
-} // namespace mbed
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/DigitalInOut.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,140 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIGITALINOUT_H
-#define MBED_DIGITALINOUT_H
-
-#include "platform.h"
-
-#include "gpio_api.h"
-#include "critical.h"
-
-namespace mbed {
-
-/** A digital input/output, used for setting or reading a bi-directional pin
- *
- * @Note Synchronization level: Interrupt safe
- */
-class DigitalInOut {
-
-public:
-    /** Create a DigitalInOut connected to the specified pin
-     *
-     *  @param pin DigitalInOut pin to connect to
-     */
-    DigitalInOut(PinName pin) : gpio() {
-        // No lock needed in the constructor
-        gpio_init_in(&gpio, pin);
-    }
-
-    /** Create a DigitalInOut connected to the specified pin
-     *
-     *  @param pin DigitalInOut pin to connect to
-     *  @param direction the initial direction of the pin
-     *  @param mode the initial mode of the pin
-     *  @param value the initial value of the pin if is an output
-     */
-    DigitalInOut(PinName pin, PinDirection direction, PinMode mode, int value) : gpio() {
-        // No lock needed in the constructor
-        gpio_init_inout(&gpio, pin, direction, mode, value);
-    }
-
-    /** Set the output, specified as 0 or 1 (int)
-     *
-     *  @param value An integer specifying the pin output value,
-     *      0 for logical 0, 1 (or any other non-zero value) for logical 1
-     */
-    void write(int value) {
-        // Thread safe / atomic HAL call
-        gpio_write(&gpio, value);
-    }
-
-    /** Return the output setting, represented as 0 or 1 (int)
-     *
-     *  @returns
-     *    an integer representing the output setting of the pin if it is an output,
-     *    or read the input if set as an input
-     */
-    int read() {
-        // Thread safe / atomic HAL call
-        return gpio_read(&gpio);
-    }
-
-    /** Set as an output
-     */
-    void output() {
-        core_util_critical_section_enter();
-        gpio_dir(&gpio, PIN_OUTPUT);
-        core_util_critical_section_exit();
-    }
-
-    /** Set as an input
-     */
-    void input() {
-        core_util_critical_section_enter();
-        gpio_dir(&gpio, PIN_INPUT);
-        core_util_critical_section_exit();
-    }
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone, OpenDrain
-     */
-    void mode(PinMode pull) {
-        core_util_critical_section_enter();
-        gpio_mode(&gpio, pull);
-        core_util_critical_section_exit();
-    }
-
-    /** Return the output setting, represented as 0 or 1 (int)
-     *
-     *  @returns
-     *    Non zero value if pin is connected to uc GPIO
-     *    0 if gpio object was initialized with NC
-     */
-    int is_connected() {
-        // Thread safe / atomic HAL call
-        return gpio_is_connected(&gpio);
-    }
-
-    /** A shorthand for write()
-     */
-    DigitalInOut& operator= (int value) {
-        // Underlying write is thread safe
-        write(value);
-        return *this;
-    }
-
-    DigitalInOut& operator= (DigitalInOut& rhs) {
-        core_util_critical_section_enter();
-        write(rhs.read());
-        core_util_critical_section_exit();
-        return *this;
-    }
-
-    /** A shorthand for read()
-     */
-    operator int() {
-        // Underlying call is thread safe
-        return read();
-    }
-
-protected:
-    gpio_t gpio;
-};
-
-} // namespace mbed
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/DigitalOut.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,126 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIGITALOUT_H
-#define MBED_DIGITALOUT_H
-
-#include "platform.h"
-#include "gpio_api.h"
-#include "critical.h"
-
-namespace mbed {
-
-/** A digital output, used for setting the state of a pin
- *
- * @Note Synchronization level: Interrupt safe
- *
- * Example:
- * @code
- * // Toggle a LED
- * #include "mbed.h"
- *
- * DigitalOut led(LED1);
- *
- * int main() {
- *     while(1) {
- *         led = !led;
- *         wait(0.2);
- *     }
- * }
- * @endcode
- */
-class DigitalOut {
-
-public:
-    /** Create a DigitalOut connected to the specified pin
-     *
-     *  @param pin DigitalOut pin to connect to
-     */
-    DigitalOut(PinName pin) : gpio() {
-        // No lock needed in the constructor
-        gpio_init_out(&gpio, pin);
-    }
-
-    /** Create a DigitalOut connected to the specified pin
-     *
-     *  @param pin DigitalOut pin to connect to
-     *  @param value the initial pin value
-     */
-    DigitalOut(PinName pin, int value) : gpio() {
-        // No lock needed in the constructor
-        gpio_init_out_ex(&gpio, pin, value);
-    }
-
-    /** Set the output, specified as 0 or 1 (int)
-     *
-     *  @param value An integer specifying the pin output value,
-     *      0 for logical 0, 1 (or any other non-zero value) for logical 1
-     */
-    void write(int value) {
-        // Thread safe / atomic HAL call
-        gpio_write(&gpio, value);
-    }
-
-    /** Return the output setting, represented as 0 or 1 (int)
-     *
-     *  @returns
-     *    an integer representing the output setting of the pin,
-     *    0 for logical 0, 1 for logical 1
-     */
-    int read() {
-        // Thread safe / atomic HAL call
-        return gpio_read(&gpio);
-    }
-
-    /** Return the output setting, represented as 0 or 1 (int)
-     *
-     *  @returns
-     *    Non zero value if pin is connected to uc GPIO
-     *    0 if gpio object was initialized with NC
-     */
-    int is_connected() {
-        // Thread safe / atomic HAL call
-        return gpio_is_connected(&gpio);
-    }
-
-    /** A shorthand for write()
-     */
-    DigitalOut& operator= (int value) {
-        // Underlying write is thread safe
-        write(value);
-        return *this;
-    }
-
-    DigitalOut& operator= (DigitalOut& rhs) {
-        core_util_critical_section_enter();
-        write(rhs.read());
-        core_util_critical_section_exit();
-        return *this;
-    }
-
-    /** A shorthand for read()
-     */
-    operator int() {
-        // Underlying call is thread safe
-        return read();
-    }
-
-protected:
-    gpio_t gpio;
-};
-
-} // namespace mbed
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/DirHandle.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,120 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIRHANDLE_H
-#define MBED_DIRHANDLE_H
-
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-#   define NAME_MAX 255
-typedef int mode_t;
-
-#else
-#   include <sys/syslimits.h>
-#endif
-
-#include "FileHandle.h"
-
-struct dirent {
-    char d_name[NAME_MAX+1];
-};
-
-namespace mbed {
-
-/** Represents a directory stream. Objects of this type are returned
- *  by a FileSystemLike's opendir method. Implementations must define
- *  at least closedir, readdir and rewinddir.
- *
- *  If a FileSystemLike class defines the opendir method, then the
- *  directories of an object of that type can be accessed by
- *  DIR *d = opendir("/example/directory") (or opendir("/example")
- *  to open the root of the filesystem), and then using readdir(d) etc.
- *
- *  The root directory is considered to contain all FileLike and
- *  FileSystemLike objects, so the DIR* returned by opendir("/") will
- *  reflect this.
- *
- *  @Note Synchronization level: Set by subclass
- */
-class DirHandle {
-
-public:
-    /** Closes the directory.
-     *
-     *  @returns
-     *    0 on success,
-     *   -1 on error.
-     */
-    virtual int closedir()=0;
-
-    /** Return the directory entry at the current position, and
-     *  advances the position to the next entry.
-     *
-     * @returns
-     *  A pointer to a dirent structure representing the
-     *  directory entry at the current position, or NULL on reaching
-     *  end of directory or error.
-     */
-    virtual struct dirent *readdir()=0;
-
-    /** Resets the position to the beginning of the directory.
-     */
-    virtual void rewinddir()=0;
-
-    /** Returns the current position of the DirHandle.
-     *
-     * @returns
-     *   the current position,
-     *  -1 on error.
-     */
-    virtual off_t telldir() { return -1; }
-
-    /** Sets the position of the DirHandle.
-     *
-     *  @param location The location to seek to. Must be a value returned by telldir.
-     */
-    virtual void seekdir(off_t location) { (void)location;}
-
-    virtual ~DirHandle() {}
-
-protected:
-
-    /** Acquire exclusive access to this object.
-     */
-    virtual void lock() {
-        // Stub
-    }
-
-    /** Release exclusive access to this object.
-     */
-    virtual void unlock() {
-        // Stub
-    }
-};
-
-} // namespace mbed
-
-typedef mbed::DirHandle DIR;
-
-extern "C" {
-    DIR *opendir(const char*);
-    struct dirent *readdir(DIR *);
-    int closedir(DIR*);
-    void rewinddir(DIR*);
-    long telldir(DIR*);
-    void seekdir(DIR*, long);
-    int mkdir(const char *name, mode_t n);
-};
-
-#endif /* MBED_DIRHANDLE_H */

--- a/M24SR-DISCOVERY_hardware/mbed/Driver_Common.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-/*
- * Copyright (c) 2006-2016, ARM Limited, All Rights Reserved
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __DRIVER_COMMON_H
-#define __DRIVER_COMMON_H
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))
-
-/**
-\brief Driver Version
-*/
-typedef struct _ARM_DRIVER_VERSION {
-  uint16_t api;                         ///< API version
-  uint16_t drv;                         ///< Driver version
-} ARM_DRIVER_VERSION;
-
-/* General return codes */
-#define ARM_DRIVER_OK                 0 ///< Operation succeeded
-#define ARM_DRIVER_ERROR             -1 ///< Unspecified error
-#define ARM_DRIVER_ERROR_BUSY        -2 ///< Driver is busy
-#define ARM_DRIVER_ERROR_TIMEOUT     -3 ///< Timeout occurred
-#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported
-#define ARM_DRIVER_ERROR_PARAMETER   -5 ///< Parameter error
-#define ARM_DRIVER_ERROR_SPECIFIC    -6 ///< Start of driver specific errors
-
-/**
-\brief General power states
-*/
-typedef enum _ARM_POWER_STATE {
-  ARM_POWER_OFF,                        ///< Power off: no operation possible
-  ARM_POWER_LOW,                        ///< Low Power mode: retain state, detect and signal wake-up events
-  ARM_POWER_FULL                        ///< Power on: full operation at maximum performance
-} ARM_POWER_STATE;
-
-#endif /* __DRIVER_COMMON_H */

--- a/M24SR-DISCOVERY_hardware/mbed/Driver_Storage.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,768 +0,0 @@
-/*
- * Copyright (c) 2006-2016, ARM Limited, All Rights Reserved
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __DRIVER_STORAGE_H
-#define __DRIVER_STORAGE_H
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif // __cplusplus
-
-#include "Driver_Common.h"
-
-#define ARM_STORAGE_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,00)  /* API version */
-
-
-#define _ARM_Driver_Storage_(n)      Driver_Storage##n
-#define  ARM_Driver_Storage_(n) _ARM_Driver_Storage_(n)
-
-#define ARM_STORAGE_INVALID_OFFSET  (0xFFFFFFFFFFFFFFFFULL) ///< Invalid address (relative to a storage controller's
-                                                            ///< address space). A storage block may never start at this address.
-
-#define ARM_STORAGE_INVALID_ADDRESS (0xFFFFFFFFUL)          ///< Invalid address within the processor's memory address space.
-                                                            ///< Refer to memory-mapped storage, i.e. < \ref ARM_DRIVER_STORAGE::ResolveAddress().
-
-/****** Storage specific error codes *****/
-#define ARM_STORAGE_ERROR_NOT_ERASABLE      (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Part (or all) of the range provided to Erase() isn't erasable.
-#define ARM_STORAGE_ERROR_NOT_PROGRAMMABLE  (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Part (or all) of the range provided to ProgramData() isn't programmable.
-#define ARM_STORAGE_ERROR_PROTECTED         (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Part (or all) of the range to Erase() or ProgramData() is protected.
-#define ARM_STORAGE_ERROR_RUNTIME_OR_INTEGRITY_FAILURE (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Runtime or sanity-check failure.
-
-/**
- * \brief Attributes of the storage range within a storage block.
- */
-typedef struct _ARM_STORAGE_BLOCK_ATTRIBUTES {
-  uint32_t erasable      :  1;   ///< Erasing blocks is permitted with a minimum granularity of 'erase_unit'.
-                                 ///<   @note: if 'erasable' is 0--i.e. the 'erase' operation isn't available--then
-                                 ///<   'erase_unit' (see below) is immaterial and should be 0.
-  uint32_t programmable  :  1;   ///< Writing to ranges is permitted with a minimum granularity of 'program_unit'.
-                                 ///<   Writes are typically achieved through the ProgramData operation (following an erase);
-                                 ///<   if storage isn't erasable (see 'erasable' above) but is memory-mapped
-                                 ///<   (i.e. 'memory_mapped'), it can be written directly using memory-store operations.
-  uint32_t executable    :  1;   ///< This storage block can hold program data; the processor can fetch and execute code
-                                 ///<   sourced from it. Often this is accompanied with the device being 'memory_mapped' (see \ref ARM_STORAGE_INFO).
-  uint32_t protectable   :  1;   ///< The entire block can be protected from program and erase operations. Once protection
-                                 ///<   is enabled for a block, its 'erasable' and 'programmable' bits are turned off.
-  uint32_t reserved      : 28;
-  uint32_t erase_unit;           ///< Minimum erase size in bytes.
-                                 ///<   The offset of the start of the erase-range should also be aligned with this value.
-                                 ///<   Applicable if the 'erasable' attribute is set for the block.
-                                 ///<   @note: if 'erasable' (see above) is 0--i.e. the 'erase' operation isn't available--then
-                                 ///<   'erase_unit' is immaterial and should be 0.
-  uint32_t protection_unit;      ///< Minimum protectable size in bytes. Applicable if the 'protectable'
-                                 ///<   attribute is set for the block. This should be a divisor of the block's size. A
-                                 ///<   block can be considered to be made up of consecutive, individually-protectable fragments.
-} ARM_STORAGE_BLOCK_ATTRIBUTES;
-
-/**
- * \brief A storage block is a range of memory with uniform attributes. Storage blocks
- * combine to make up the address map of a storage controller.
- */
-typedef struct _ARM_STORAGE_BLOCK {
-  uint64_t                     addr;       ///< This is the start address of the storage block. It is
-                                           ///<   expressed as an offset from the start of the storage map
-                                           ///<   maintained by the owning storage controller.
-  uint64_t                     size;       ///< This is the size of the storage block, in units of bytes.
-                                           ///<   Together with addr, it describes a range [addr, addr+size).
-  ARM_STORAGE_BLOCK_ATTRIBUTES attributes; ///< Attributes for this block.
-} ARM_STORAGE_BLOCK;
-
-/**
- * The check for a valid ARM_STORAGE_BLOCK.
- */
-#define ARM_STORAGE_VALID_BLOCK(BLK) (((BLK)->addr != ARM_STORAGE_INVALID_OFFSET) && ((BLK)->size != 0))
-
-/**
- * \brief Values for encoding storage memory-types with respect to programmability.
- *
- * Please ensure that the maximum of the following memory types doesn't exceed 16; we
- * encode this in a 4-bit field within ARM_STORAGE_INFO::programmability.
- */
-#define ARM_STORAGE_PROGRAMMABILITY_RAM       (0x0)
-#define ARM_STORAGE_PROGRAMMABILITY_ROM       (0x1) ///< Read-only memory.
-#define ARM_STORAGE_PROGRAMMABILITY_WORM      (0x2) ///< write-once-read-only-memory (WORM).
-#define ARM_STORAGE_PROGRAMMABILITY_ERASABLE  (0x3) ///< re-programmable based on erase. Supports multiple writes.
-
-/**
- * Values for encoding data-retention levels for storage blocks.
- *
- * Please ensure that the maximum of the following retention types doesn't exceed 16; we
- * encode this in a 4-bit field within ARM_STORAGE_INFO::retention_level.
- */
-#define ARM_RETENTION_WHILE_DEVICE_ACTIVE     (0x0) ///< Data is retained only during device activity.
-#define ARM_RETENTION_ACROSS_SLEEP            (0x1) ///< Data is retained across processor sleep.
-#define ARM_RETENTION_ACROSS_DEEP_SLEEP       (0x2) ///< Data is retained across processor deep-sleep.
-#define ARM_RETENTION_BATTERY_BACKED          (0x3) ///< Data is battery-backed. Device can be powered off.
-#define ARM_RETENTION_NVM                     (0x4) ///< Data is retained in non-volatile memory.
-
-/**
- * Device Data Security Protection Features. Applicable mostly to EXTERNAL_NVM.
- */
-typedef struct _ARM_STORAGE_SECURITY_FEATURES {
-  uint32_t acls                :  1; ///< Protection against internal software attacks using ACLs.
-  uint32_t rollback_protection :  1; ///< Roll-back protection. Set to true if the creator of the storage
-                                     ///<   can ensure that an external attacker can't force an
-                                     ///<   older firmware to run or to revert back to a previous state.
-  uint32_t tamper_proof        :  1; ///< Tamper-proof memory (will be deleted on tamper-attempts using board level or chip level sensors).
-  uint32_t internal_flash      :  1; ///< Internal flash.
-  uint32_t reserved1           : 12;
-
-  /**
-   * Encode support for hardening against various classes of attacks.
-   */
-  uint32_t software_attacks     :  1; ///< device software (malware running on the device).
-  uint32_t board_level_attacks  :  1; ///< board level attacks (debug probes, copy protection fuses.)
-  uint32_t chip_level_attacks   :  1; ///< chip level attacks (tamper-protection).
-  uint32_t side_channel_attacks :  1; ///< side channel attacks.
-  uint32_t reserved2            : 12;
-} ARM_STORAGE_SECURITY_FEATURES;
-
-#define ARM_STORAGE_PROGRAM_CYCLES_INFINITE (0UL) /**< Infinite or unknown endurance for reprogramming. */
-
-/**
- * \brief Storage information. This contains device-metadata. It is the return
- *     value from calling GetInfo() on the storage driver.
- *
- * \details These fields serve a different purpose than the ones contained in
- *     \ref ARM_STORAGE_CAPABILITIES, which is another structure containing
- *     device-level metadata. ARM_STORAGE_CAPABILITIES describes the API
- *     capabilities, whereas ARM_STORAGE_INFO describes the device. Furthermore
- *     ARM_STORAGE_CAPABILITIES fits within a single word, and is designed to be
- *     passed around by value; ARM_STORAGE_INFO, on the other hand, contains
- *     metadata which doesn't fit into a single word and requires the use of
- *     pointers to be moved around.
- */
-typedef struct _ARM_STORAGE_INFO {
-  uint64_t                      total_storage;        ///< Total available storage, in bytes.
-  uint32_t                      program_unit;         ///< Minimum programming size in bytes.
-                                                      ///<   The offset of the start of the program-range should also be aligned with this value.
-                                                      ///<   Applicable only if the 'programmable' attribute is set for a block.
-                                                      ///<   @note: setting program_unit to 0 has the effect of disabling the size and alignment
-                                                      ///<   restrictions (setting it to 1 also has the same effect).
-  uint32_t                      optimal_program_unit; ///< Optimal programming page-size in bytes. Some storage controllers
-                                                      ///<   have internal buffers into which to receive data. Writing in chunks of
-                                                      ///<   'optimal_program_unit' would achieve maximum programming speed.
-                                                      ///<   Applicable only if the 'programmable' attribute is set for the underlying block(s).
-  uint32_t                      program_cycles;       ///< A measure of endurance for reprogramming.
-                                                      ///<   Use ARM_STORAGE_PROGRAM_CYCLES_INFINITE for infinite or unknown endurance.
-  uint32_t                      erased_value    :  1; ///< Contents of erased memory (usually 1 to indicate erased bytes with state 0xFF).
-  uint32_t                      memory_mapped   :  1; ///< This storage device has a mapping onto the processor's memory address space.
-                                                      ///<   @note: For a memory-mapped block which isn't erasable but is programmable (i.e. if
-                                                      ///<   'erasable' is set to 0, but 'programmable' is 1), writes should be possible directly to
-                                                      ///<   the memory-mapped storage without going through the ProgramData operation.
-  uint32_t                      programmability :  4; ///< A value to indicate storage programmability.
-  uint32_t                      retention_level :  4;
-  uint32_t                      reserved        : 22;
-  ARM_STORAGE_SECURITY_FEATURES security;             ///< \ref ARM_STORAGE_SECURITY_FEATURES
-} ARM_STORAGE_INFO;
-
-/**
-\brief Operating status of the storage controller.
-*/
-typedef struct _ARM_STORAGE_STATUS {
-  uint32_t busy  : 1;                   ///< Controller busy flag
-  uint32_t error : 1;                   ///< Read/Program/Erase error flag (cleared on start of next operation)
-} ARM_STORAGE_STATUS;
-
-/**
- * \brief Storage Driver API Capabilities.
- *
- * This data structure is designed to fit within a single word so that it can be
- * fetched cheaply using a call to driver->GetCapabilities().
- */
-typedef struct _ARM_STORAGE_CAPABILITIES {
-  uint32_t asynchronous_ops :  1; ///< Used to indicate if APIs like initialize,
-                                  ///<   read, erase, program, etc. can operate in asynchronous mode.
-                                  ///<   Setting this bit to 1 means that the driver is capable
-                                  ///<   of launching asynchronous operations; command completion is
-                                  ///<   signaled by the invocation of a completion callback. If
-                                  ///<   set to 1, drivers may still complete asynchronous
-                                  ///<   operations synchronously as necessary--in which case they
-                                  ///<   return a positive error code to indicate synchronous completion.
-  uint32_t erase_all        :  1; ///< Supports EraseAll operation.
-  uint32_t reserved         : 30;
-} ARM_STORAGE_CAPABILITIES;
-
-/**
- * Command opcodes for Storage. Completion callbacks use these codes to refer to
- * completing commands. Refer to \ref ARM_Storage_Callback_t.
- */
-typedef enum _ARM_STORAGE_OPERATION {
-  ARM_STORAGE_OPERATION_GET_VERSION,
-  ARM_STORAGE_OPERATION_GET_CAPABILITIES,
-  ARM_STORAGE_OPERATION_INITIALIZE,
-  ARM_STORAGE_OPERATION_UNINITIALIZE,
-  ARM_STORAGE_OPERATION_POWER_CONTROL,
-  ARM_STORAGE_OPERATION_READ_DATA,
-  ARM_STORAGE_OPERATION_PROGRAM_DATA,
-  ARM_STORAGE_OPERATION_ERASE,
-  ARM_STORAGE_OPERATION_ERASE_ALL,
-  ARM_STORAGE_OPERATION_GET_STATUS,
-  ARM_STORAGE_OPERATION_GET_INFO,
-  ARM_STORAGE_OPERATION_RESOLVE_ADDRESS,
-  ARM_STORAGE_OPERATION_GET_NEXT_BLOCK,
-  ARM_STORAGE_OPERATION_GET_BLOCK
-} ARM_STORAGE_OPERATION;
-
-/**
- * Declaration of the callback-type for command completion.
- *
- * @param [in] status
- *               A code to indicate the status of the completed operation. For data
- *               transfer operations, the status field is overloaded in case of
- *               success to return the count of items successfully transferred; this
- *               can be done safely because error codes are negative values.
- *
- * @param [in] operation
- *               The command op-code. This value isn't essential for the callback in
- *               the presence of the command instance-id, but it is expected that
- *               this information could be a quick and useful filter.
- */
-typedef void (*ARM_Storage_Callback_t)(int32_t status, ARM_STORAGE_OPERATION operation);
-
-/**
- * This is the set of operations constituting the Storage driver. Their
- * implementation is platform-specific, and needs to be supplied by the
- * porting effort.
- *
- * Some APIs within `ARM_DRIVER_STORAGE` will always operate synchronously:
- * GetVersion, GetCapabilities, GetStatus, GetInfo, ResolveAddress,
- * GetNextBlock, and GetBlock. This means that control returns to the caller
- * with a relevant status code only after the completion of the operation (or
- * the discovery of a failure condition).
- *
- * The remainder of the APIs: Initialize, Uninitialize, PowerControl, ReadData,
- * ProgramData, Erase, EraseAll, can function asynchronously if the underlying
- * controller supports it--i.e. if ARM_STORAGE_CAPABILITIES::asynchronous_ops is
- * set. In the case of asynchronous operation, the invocation returns early
- * (with ARM_DRIVER_OK) and results in a completion callback later. If
- * ARM_STORAGE_CAPABILITIES::asynchronous_ops is not set, then all such APIs
- * execute synchronously, and control returns to the caller with a status code
- * only after the completion of the operation (or the discovery of a failure
- * condition).
- *
- * If ARM_STORAGE_CAPABILITIES::asynchronous_ops is set, a storage driver may
- * still choose to execute asynchronous operations in a synchronous manner. If
- * so, the driver returns a positive value to indicate successful synchronous
- * completion (or an error code in case of failure) and no further invocation of
- * completion callback should be expected. The expected return value for
- * synchronous completion of such asynchronous operations varies depending on
- * the operation. For operations involving data access, it often equals the
- * amount of data transferred or affected. For non data-transfer operations,
- * such as EraseAll or Initialize, it is usually 1.
- *
- * Here's a code snippet to suggest how asynchronous APIs might be used by
- * callers to handle both synchronous and asynchronous execution by the
- * underlying storage driver:
- * \code
- *     ASSERT(ARM_DRIVER_OK == 0); // this is a precondition; it doesn't need to be put in code
- *     int32_t returnValue = drv->asynchronousAPI(...);
- *     if (returnValue < ARM_DRIVER_OK) {
- *         // handle error.
- *     } else if (returnValue == ARM_DRIVER_OK) {
- *         ASSERT(drv->GetCapabilities().asynchronous_ops == 1);
- *         // handle early return from asynchronous execution; remainder of the work is done in the callback handler.
- *     } else {
- *         ASSERT(returnValue == EXPECTED_RETURN_VALUE_FOR_SYNCHRONOUS_COMPLETION);
- *         // handle synchronous completion.
- *     }
- * \endcode
- */
-typedef struct _ARM_DRIVER_STORAGE {
-  /**
-   * \brief Get driver version.
-   *
-   * The function GetVersion() returns version information of the driver implementation in ARM_DRIVER_VERSION.
-   *
-   *    - API version is the version of the CMSIS-Driver specification used to implement this driver.
-   *    - Driver version is source code version of the actual driver implementation.
-   *
-   * Example:
-   * \code
-   *     extern ARM_DRIVER_STORAGE *drv_info;
-   *
-   *     void read_version (void)  {
-   *       ARM_DRIVER_VERSION  version;
-   *
-   *       version = drv_info->GetVersion ();
-   *       if (version.api < 0x10A)   {      // requires at minimum API version 1.10 or higher
-   *         // error handling
-   *         return;
-   *       }
-   *     }
-   * \endcode
-   *
-   * @return \ref ARM_DRIVER_VERSION.
-   *
-   * @note This API returns synchronously--it does not result in an invocation
-   *     of a completion callback.
-   *
-   * @note The function GetVersion() can be called any time to obtain the
-   *     required information from the driver (even before initialization). It
-   *     always returns the same information.
-   */
-  ARM_DRIVER_VERSION (*GetVersion)(void);
-
-  /**
-   * \brief Get driver capabilities.
-   *
-   * \details The function GetCapabilities() returns information about
-   * capabilities in this driver implementation. The data fields of the struct
-   * ARM_STORAGE_CAPABILITIES encode various capabilities, for example if the device
-   * is able to execute operations asynchronously.
-   *
-   * Example:
-   * \code
-   *     extern ARM_DRIVER_STORAGE *drv_info;
-   *
-   *     void read_capabilities (void)  {
-   *       ARM_STORAGE_CAPABILITIES drv_capabilities;
-   *
-   *       drv_capabilities = drv_info->GetCapabilities ();
-   *       // interrogate capabilities
-   *
-   *     }
-   * \endcode
-   *
-   * @return \ref ARM_STORAGE_CAPABILITIES.
-   *
-   * @note This API returns synchronously--it does not result in an invocation
-   *     of a completion callback.
-   *
-   * @note The function GetCapabilities() can be called any time to obtain the
-   *     required information from the driver (even before initialization). It
-   *     always returns the same information.
-   */
-  ARM_STORAGE_CAPABILITIES (*GetCapabilities)(void);
-
-  /**
-   * \brief Initialize the Storage Interface.
-   *
-   * The function Initialize is called when the middleware component starts
-   * operation. In addition to bringing the controller to a ready state,
-   * Initialize() receives a callback handler to be invoked upon completion of
-   * asynchronous operations.
-   *
-   * Initialize() needs to be called explicitly before
-   * powering the peripheral using PowerControl(), and before initiating other
-   * accesses to the storage controller.
-   *
-   * The function performs the following operations:
-   *   - Initializes the resources needed for the Storage interface.
-   *   - Registers the \ref ARM_Storage_Callback_t callback function.
-   *
-   * To start working with a peripheral the functions Initialize and PowerControl need to be called in this order:
-   *     drv->Initialize (...); // Allocate I/O pins
-   *     drv->PowerControl (ARM_POWER_FULL);        // Power up peripheral, setup IRQ/DMA
-   *
-   * - Initialize() typically allocates the I/O resources (pins) for the
-   *   peripheral. The function can be called multiple times; if the I/O resources
-   *   are already initialized it performs no operation and just returns with
-   *   ARM_DRIVER_OK.
-   *
-   * - PowerControl (ARM_POWER_FULL) sets the peripheral registers including
-   *   interrupt (NVIC) and optionally DMA. The function can be called multiple
-   *   times; if the registers are already set it performs no operation and just
-   *   returns with ARM_DRIVER_OK.
-   *
-   * To stop working with a peripheral the functions PowerControl and Uninitialize need to be called in this order:
-   *     drv->PowerControl (ARM_POWER_OFF);     // Terminate any pending transfers, reset IRQ/DMA, power off peripheral
-   *     drv->Uninitialize (...);               // Release I/O pins
-   *
-   * The functions PowerControl and Uninitialize always execute and can be used
-   * to put the peripheral into a Safe State, for example after any data
-   * transmission errors. To restart the peripheral in an error condition,
-   * you should first execute the Stop Sequence and then the Start Sequence.
-   *
-   * @param [in] callback
-   *               Caller-defined callback to be invoked upon command completion
-   *               for asynchronous APIs (including the completion of
-   *               initialization). Use a NULL pointer when no callback
-   *               signals are required.
-   *
-   * @note This API may execute asynchronously if
-   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
-   *     execution is optional even if 'asynchronous_ops' is set.
-   *
-   * @return If asynchronous activity is launched, an invocation returns
-   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
-   *     future with a status value of ARM_DRIVER_OK or an error-code. In the
-   *     case of synchronous execution, control returns after completion with a
-   *     value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
-   */
-  int32_t (*Initialize)(ARM_Storage_Callback_t callback);
-
-  /**
-   * \brief De-initialize the Storage Interface.
-   *
-   * The function Uninitialize() de-initializes the resources of Storage interface.
-   *
-   * It is called when the middleware component stops operation, and wishes to
-   * release the software resources used by the interface.
-   *
-   * @note This API may execute asynchronously if
-   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
-   *     execution is optional even if 'asynchronous_ops' is set.
-   *
-   * @return If asynchronous activity is launched, an invocation returns
-   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
-   *     future with a status value of ARM_DRIVER_OK or an error-code. In the
-   *     case of synchronous execution, control returns after completion with a
-   *     value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
-   */
-  int32_t (*Uninitialize)(void);
-
-  /**
-   * \brief Control the Storage interface power.
-   *
-   * The function \b ARM_Storage_PowerControl operates the power modes of the Storage interface.
-   *
-   * To start working with a peripheral the functions Initialize and PowerControl need to be called in this order:
-   *     drv->Initialize (...);                 // Allocate I/O pins
-   *     drv->PowerControl (ARM_POWER_FULL);    // Power up peripheral, setup IRQ/DMA
-   *
-   * - Initialize() typically allocates the I/O resources (pins) for the
-   *   peripheral. The function can be called multiple times; if the I/O resources
-   *   are already initialized it performs no operation and just returns with
-   *   ARM_DRIVER_OK.
-   *
-   * - PowerControl (ARM_POWER_FULL) sets the peripheral registers including
-   *   interrupt (NVIC) and optionally DMA. The function can be called multiple
-   *   times; if the registers are already set it performs no operation and just
-   *   returns with ARM_DRIVER_OK.
-   *
-   * To stop working with a peripheral the functions PowerControl and Uninitialize need to be called in this order:
-   *
-   *     drv->PowerControl (ARM_POWER_OFF);     // Terminate any pending transfers, reset IRQ/DMA, power off peripheral
-   *     drv->Uninitialize (...);               // Release I/O pins
-   *
-   * The functions PowerControl and Uninitialize always execute and can be used
-   * to put the peripheral into a Safe State, for example after any data
-   * transmission errors. To restart the peripheral in an error condition,
-   * you should first execute the Stop Sequence and then the Start Sequence.
-   *
-   * @param state
-   *          \ref ARM_POWER_STATE. The target power-state for the storage controller.
-   *          The parameter state can have the following values:
-   *              - ARM_POWER_FULL : set-up peripheral for data transfers, enable interrupts
-   *                                 (NVIC) and optionally DMA. Can be called multiple times. If the peripheral
-   *                                 is already in this mode, then the function performs no operation and returns
-   *                                 with ARM_DRIVER_OK.
-   *              - ARM_POWER_LOW : may use power saving. Returns ARM_DRIVER_ERROR_UNSUPPORTED when not implemented.
-   *              - ARM_POWER_OFF : terminates any pending data transfers, disables peripheral, disables related interrupts and DMA.
-   *
-   * @note This API may execute asynchronously if
-   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
-   *     execution is optional even if 'asynchronous_ops' is set.
-   *
-   * @return If asynchronous activity is launched, an invocation returns
-   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
-   *     future with a status value of ARM_DRIVER_OK or an error-code. In the
-   *     case of synchronous execution, control returns after completion with a
-   *     value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
-   */
-  int32_t (*PowerControl)(ARM_POWER_STATE state);
-
-  /**
-   * \brief read the contents of a given address range from the storage device.
-   *
-   * \details Read the contents of a range of storage memory into a buffer
-   *   supplied by the caller. The buffer is owned by the caller and should
-   *   remain accessible for the lifetime of this command.
-   *
-   * @param  [in] addr
-   *                This specifies the address from where to read data.
-   *
-   * @param [out] data
-   *                The destination of the read operation. The buffer
-   *                is owned by the caller and should remain accessible for the
-   *                lifetime of this command.
-   *
-   * @param  [in] size
-   *                The number of bytes requested to read. The data buffer
-   *                should be at least as large as this size.
-   *
-   * @note This API may execute asynchronously if
-   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
-   *     execution is optional even if 'asynchronous_ops' is set.
-   *
-   * @return If asynchronous activity is launched, an invocation returns
-   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
-   *     future with the number of successfully transferred bytes passed in as
-   *     the 'status' parameter. In the case of synchronous execution, control
-   *     returns after completion with a positive transfer-count. Return values
-   *     less than ARM_DRIVER_OK (0) signify errors.
-   */
-  int32_t (*ReadData)(uint64_t addr, void *data, uint32_t size);
-
-  /**
-   * \brief program (write into) the contents of a given address range of the storage device.
-   *
-   * \details Write the contents of a given memory buffer into a range of
-   *   storage memory. In the case of flash memory, the destination range in
-   *   storage memory typically has its contents in an erased state from a
-   *   preceding erase operation. The source memory buffer is owned by the
-   *   caller and should remain accessible for the lifetime of this command.
-   *
-   * @param [in] addr
-   *               This is the start address of the range to be written into. It
-   *               needs to be aligned to the device's \em program_unit
-   *               specified in \ref ARM_STORAGE_INFO.
-   *
-   * @param [in] data
-   *               The source of the write operation. The buffer is owned by the
-   *               caller and should remain accessible for the lifetime of this
-   *               command.
-   *
-   * @param [in] size
-   *               The number of bytes requested to be written. The buffer
-   *               should be at least as large as this size. \note 'size' should
-   *               be a multiple of the device's 'program_unit' (see \ref
-   *               ARM_STORAGE_INFO).
-   *
-   * @note It is best for the middleware to write in units of
-   *     'optimal_program_unit' (\ref ARM_STORAGE_INFO) of the device.
-   *
-   * @note This API may execute asynchronously if
-   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
-   *     execution is optional even if 'asynchronous_ops' is set.
-   *
-   * @return If asynchronous activity is launched, an invocation returns
-   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
-   *     future with the number of successfully transferred bytes passed in as
-   *     the 'status' parameter. In the case of synchronous execution, control
-   *     returns after completion with a positive transfer-count. Return values
-   *     less than ARM_DRIVER_OK (0) signify errors.
-   */
-  int32_t (*ProgramData)(uint64_t addr, const void *data, uint32_t size);
-
-  /**
-   * @brief Erase Storage range.
-   *
-   * @details This function erases a range of storage specified by [addr, addr +
-   *     size). Both 'addr' and 'addr + size' should align with the
-   *     'erase_unit'(s) of the respective owning storage block(s) (see \ref
-   *     ARM_STORAGE_BLOCK and \ref ARM_STORAGE_BLOCK_ATTRIBUTES). The range to
-   *     be erased will have its contents returned to the un-programmed state--
-   *     i.e. to 'erased_value' (see \ref ARM_STORAGE_BLOCK_ATTRIBUTES), which
-   *     is usually 1 to indicate the pattern of all ones: 0xFF.
-   *
-   * @param [in] addr
-   *               This is the start-address of the range to be erased. It must
-   *               start at an 'erase_unit' boundary of the underlying block.
-   *
-   * @param [in] size
-   *               Size (in bytes) of the range to be erased. 'addr + size'
-   *               must be aligned with the 'erase_unit' of the underlying
-   *               block.
-   *
-   * @note This API may execute asynchronously if
-   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
-   *     execution is optional even if 'asynchronous_ops' is set.
-   *
-   * @return
-   *   If the range to be erased doesn't align with the erase_units of the
-   *   respective start and end blocks, ARM_DRIVER_ERROR_PARAMETER is returned.
-   *   If any part of the range is protected, ARM_STORAGE_ERROR_PROTECTED is
-   *   returned. If any part of the range is not erasable,
-   *   ARM_STORAGE_ERROR_NOT_ERASABLE is returned. All such sanity-check
-   *   failures result in the error code being returned synchronously and the
-   *   storage bytes within the range remain unaffected.
-   *   Otherwise the function executes in the following ways:
-   *     If asynchronous activity is launched, an invocation returns
-   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
-   *     future with the number of successfully erased bytes passed in as
-   *     the 'status' parameter. In the case of synchronous execution, control
-   *     returns after completion with a positive erase-count. Return values
-   *     less than ARM_DRIVER_OK (0) signify errors.
-   *
-   * @note Erase() may return a smaller (positive) value than the size of the
-   *     requested range. The returned value indicates the actual number of bytes
-   *     erased. It is the caller's responsibility to follow up with an appropriate
-   *     request to complete the operation.
-   *
-   * @note in the case of a failed erase (except when
-   *     ARM_DRIVER_ERROR_PARAMETER, ARM_STORAGE_ERROR_PROTECTED, or
-   *     ARM_STORAGE_ERROR_NOT_ERASABLE is returned synchronously), the
-   *     requested range should be assumed to be in an unknown state. The
-   *     previous contents may not be retained.
-   */
-  int32_t (*Erase)(uint64_t addr, uint32_t size);
-
-  /**
-   * @brief Erase complete storage. Optional function for faster erase of the complete device.
-   *
-   * This optional function erases the complete device. If the device does not
-   *    support global erase then the function returns the error value \ref
-   *    ARM_DRIVER_ERROR_UNSUPPORTED. The data field \em 'erase_all' =
-   *    \token{1} of the structure \ref ARM_STORAGE_CAPABILITIES encodes that
-   *    \ref ARM_STORAGE_EraseAll is supported.
-   *
-   * @note This API may execute asynchronously if
-   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
-   *     execution is optional even if 'asynchronous_ops' is set.
-   *
-   * @return
-   *   If any part of the storage range is protected,
-   *   ARM_STORAGE_ERROR_PROTECTED is returned. If any part of the storage
-   *   range is not erasable, ARM_STORAGE_ERROR_NOT_ERASABLE is returned. All
-   *   such sanity-check failures result in the error code being returned
-   *   synchronously and the storage bytes within the range remain unaffected.
-   *   Otherwise the function executes in the following ways:
-   *     If asynchronous activity is launched, an invocation returns
-   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
-   *     future with ARM_DRIVER_OK passed in as the 'status' parameter. In the
-   *     case of synchronous execution, control returns after completion with a
-   *     value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
-   */
-  int32_t (*EraseAll)(void);
-
-  /**
-   * @brief Get the status of the current (or previous) command executed by the
-   *     storage controller; stored in the structure \ref ARM_STORAGE_STATUS.
-   *
-   * @return
-   *          The status of the underlying controller.
-   *
-   * @note This API returns synchronously--it does not result in an invocation
-   *     of a completion callback.
-   */
-  ARM_STORAGE_STATUS (*GetStatus)(void);
-
-  /**
-   * @brief Get information about the Storage device; stored in the structure \ref ARM_STORAGE_INFO.
-   *
-   * @param [out] info
-   *                A caller-supplied buffer capable of being filled in with an
-   *                \ref ARM_STORAGE_INFO.
-   *
-   * @return ARM_DRIVER_OK if a ARM_STORAGE_INFO structure containing top level
-   *         metadata about the storage controller is filled into the supplied
-   *         buffer, else an appropriate error value.
-   *
-   * @note It is the caller's responsibility to ensure that the buffer passed in
-   *         is able to be initialized with a \ref ARM_STORAGE_INFO.
-   *
-   * @note This API returns synchronously--it does not result in an invocation
-   *     of a completion callback.
-   */
-  int32_t (*GetInfo)(ARM_STORAGE_INFO *info);
-
-  /**
-   * \brief For memory-mapped storage, resolve an address relative to
-   *     the storage controller into a memory address.
-   *
-   * @param addr
-   *          This is the address for which we want a resolution to the
-   *          processor's physical address space. It is an offset from the
-   *          start of the storage map maintained by the owning storage
-   *          controller.
-   *
-   * @return
-   *          The resolved address in the processor's address space; else
-   *          ARM_STORAGE_INVALID_ADDRESS, if no resolution is possible.
-   *
-   * @note This API returns synchronously. The invocation should return quickly,
-   *     and result in a resolved address.
-   */
-  uint32_t (*ResolveAddress)(uint64_t addr);
-
-  /**
-   * @brief Advance to the successor of the current block (iterator), or fetch
-   *     the first block (if 'prev_block' is passed in as NULL).
-   *
-   * @details This helper function fetches (an iterator to) the next block (or
-   *     the first block if 'prev_block' is passed in as NULL). In the failure
-   *     case, a terminating, invalid block iterator is filled into the out
-   *     parameter: 'next_block'. In combination with \ref
-   *     ARM_STORAGE_VALID_BLOCK(), it can be used to iterate over the sequence
-   *     of blocks within the storage map:
-   *
-   * \code
-   *   ARM_STORAGE_BLOCK block;
-   *   for (drv->GetNextBlock(NULL, &block); ARM_STORAGE_VALID_BLOCK(&block); drv->GetNextBlock(&block, &block)) {
-   *       // make use of block
-   *   }
-   * \endcode
-   *
-   * @param[in]  prev_block
-   *               An existing block (iterator) within the same storage
-   *               controller. The memory buffer holding this block is owned
-   *               by the caller. This pointer may be NULL; if so, the
-   *               invocation fills in the first block into the out parameter:
-   *               'next_block'.
-   *
-   * @param[out] next_block
-   *               A caller-owned buffer large enough to be filled in with
-   *               the following ARM_STORAGE_BLOCK. It is legal to provide the
-   *               same buffer using 'next_block' as was passed in with 'prev_block'. It
-   *               is also legal to pass a NULL into this parameter if the
-   *               caller isn't interested in populating a buffer with the next
-   *               block--i.e. if the caller only wishes to establish the
-   *               presence of a next block.
-   *
-   * @return ARM_DRIVER_OK if a valid next block is found (or first block, if
-   *     prev_block is passed as NULL); upon successful operation, the contents
-   *     of the next (or first) block are filled into the buffer pointed to by
-   *     the parameter 'next_block' and ARM_STORAGE_VALID_BLOCK(next_block) is
-   *     guaranteed to be true. Upon reaching the end of the sequence of blocks
-   *     (iterators), or in case the driver is unable to fetch information about
-   *     the next (or first) block, an error (negative) value is returned and an
-   *     invalid StorageBlock is populated into the supplied buffer. If
-   *     prev_block is NULL, the first block is returned.
-   *
-   * @note This API returns synchronously--it does not result in an invocation
-   *     of a completion callback.
-   */
-   int32_t (*GetNextBlock)(const ARM_STORAGE_BLOCK* prev_block, ARM_STORAGE_BLOCK *next_block);
-
-  /**
-   * @brief Find the storage block (iterator) encompassing a given storage address.
-   *
-   * @param[in]  addr
-   *               Storage address in bytes.
-   *
-   * @param[out] block
-   *               A caller-owned buffer large enough to be filled in with the
-   *               ARM_STORAGE_BLOCK encapsulating the given address. This value
-   *               can also be passed in as NULL if the caller isn't interested
-   *               in populating a buffer with the block--if the caller only
-   *               wishes to establish the presence of a containing storage
-   *               block.
-   *
-   * @return ARM_DRIVER_OK if a containing storage-block is found. In this case,
-   *     if block is non-NULL, the buffer pointed to by it is populated with
-   *     the contents of the storage block--i.e. if block is valid and a block is
-   *     found, ARM_STORAGE_VALID_BLOCK(block) would return true following this
-   *     call. If there is no storage block containing the given offset, or in
-   *     case the driver is unable to resolve an address to a storage-block, an
-   *     error (negative) value is returned and an invalid StorageBlock is
-   *     populated into the supplied buffer.
-   *
-   * @note This API returns synchronously--it does not result in an invocation
-   *     of a completion callback.
-   */
-  int32_t (*GetBlock)(uint64_t addr, ARM_STORAGE_BLOCK *block);
-} const ARM_DRIVER_STORAGE;
-
-#ifdef __cplusplus
-}
-#endif // __cplusplus
-
-#endif /* __DRIVER_STORAGE_H */

--- a/M24SR-DISCOVERY_hardware/mbed/Ethernet.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,172 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ETHERNET_H
-#define MBED_ETHERNET_H
-
-#include "platform.h"
-
-#if DEVICE_ETHERNET
-
-namespace mbed {
-
-/** An ethernet interface, to use with the ethernet pins.
- *
- * @Note Synchronization level: Not protected
- *
- * Example:
- * @code
- * // Read destination and source from every ethernet packet
- *
- * #include "mbed.h"
- *
- * Ethernet eth;
- *
- * int main() {
- *     char buf[0x600];
- *
- *     while(1) {
- *         int size = eth.receive();
- *         if(size > 0) {
- *             eth.read(buf, size);
- *             printf("Destination:  %02X:%02X:%02X:%02X:%02X:%02X\n",
- *                     buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
- *             printf("Source: %02X:%02X:%02X:%02X:%02X:%02X\n",
- *                     buf[6], buf[7], buf[8], buf[9], buf[10], buf[11]);
- *         }
- *
- *         wait(1);
- *     }
- * }
- * @endcode
- */
-class Ethernet {
-
-public:
-
-    /** Initialise the ethernet interface.
-     */
-    Ethernet();
-
-    /** Powers the hardware down.
-     */
-    virtual ~Ethernet();
-
-    enum Mode {
-        AutoNegotiate,
-        HalfDuplex10,
-        FullDuplex10,
-        HalfDuplex100,
-        FullDuplex100
-    };
-
-    /** Writes into an outgoing ethernet packet.
-     *
-     *  It will append size bytes of data to the previously written bytes.
-     *
-     *  @param data An array to write.
-     *  @param size The size of data.
-     *
-     *  @returns
-     *   The number of written bytes.
-     */
-    int write(const char *data, int size);
-
-    /** Send an outgoing ethernet packet.
-     *
-     *  After filling in the data in an ethernet packet it must be send.
-     *  Send will provide a new packet to write to.
-     *
-     *  @returns
-     *    0 if the sending was failed,
-     *    or the size of the packet successfully sent.
-     */
-    int send();
-
-    /** Recevies an arrived ethernet packet.
-     *
-     *  Receiving an ethernet packet will drop the last received ethernet packet
-     *  and make a new ethernet packet ready to read.
-     *  If no ethernet packet is arrived it will return 0.
-     *
-     *  @returns
-     *    0 if no ethernet packet is arrived,
-     *    or the size of the arrived packet.
-     */
-    int receive();
-
-    /** Read from an recevied ethernet packet.
-     *
-     *  After receive returnd a number bigger than 0it is
-     *  possible to read bytes from this packet.
-     *  Read will write up to size bytes into data.
-     *
-     *  It is possible to use read multible times.
-     *  Each time read will start reading after the last read byte before.
-     *
-     *  @returns
-     *  The number of byte read.
-     */
-    int read(char *data, int size);
-
-    /** Gives the ethernet address of the mbed.
-     *
-     *  @param mac Must be a pointer to a 6 byte char array to copy the ethernet address in.
-     */
-    void address(char *mac);
-
-    /** Returns if an ethernet link is pressent or not. It takes a wile after Ethernet initializion to show up.
-     *
-     *  @returns
-     *   0 if no ethernet link is pressent,
-     *   1 if an ethernet link is pressent.
-     *
-     * Example:
-     * @code
-     * // Using the Ethernet link function
-     * #include "mbed.h"
-     *
-     * Ethernet eth;
-     *
-     * int main() {
-     *     wait(1); // Needed after startup.
-     *     if (eth.link()) {
-     *          printf("online\n");
-     *     } else {
-     *          printf("offline\n");
-     *     }
-     * }
-     * @endcode
-     */
-    int link();
-
-    /** Sets the speed and duplex parameters of an ethernet link
-     *
-     * - AutoNegotiate      Auto negotiate speed and duplex
-     * - HalfDuplex10       10 Mbit, half duplex
-     * - FullDuplex10       10 Mbit, full duplex
-     * - HalfDuplex100      100 Mbit, half duplex
-     * - FullDuplex100      100 Mbit, full duplex
-     *
-     *  @param mode the speed and duplex mode to set the link to:
-     */
-    void set_link(Mode mode);
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/FileBase.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,81 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILEBASE_H
-#define MBED_FILEBASE_H
-
-typedef int FILEHANDLE;
-
-#include <stdio.h>
-
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-#    define O_RDONLY 0
-#    define O_WRONLY 1
-#    define O_RDWR   2
-#    define O_CREAT  0x0200
-#    define O_TRUNC  0x0400
-#    define O_APPEND 0x0008
-
-#    define NAME_MAX 255
-
-typedef int mode_t;
-typedef int ssize_t;
-typedef long off_t;
-
-#else
-#    include <sys/fcntl.h>
-#    include <sys/types.h>
-#    include <sys/syslimits.h>
-#endif
-
-#include "platform.h"
-#include "SingletonPtr.h"
-#include "PlatformMutex.h"
-
-namespace mbed {
-
-typedef enum {
-    FilePathType,
-    FileSystemPathType
-} PathType;
-
-class FileBase {
-public:
-    FileBase(const char *name, PathType t);
-
-    virtual ~FileBase();
-
-    const char* getName(void);
-    PathType    getPathType(void);
-
-    static FileBase *lookup(const char *name, unsigned int len);
-
-    static FileBase *get(int n);
-
-    /* disallow copy constructor and assignment operators */
-private:
-    static FileBase *_head;
-    static SingletonPtr<PlatformMutex> _mutex;
-
-    FileBase   *_next;
-    const char * const _name;
-    const PathType _path_type;
-    FileBase(const FileBase&);
-    FileBase & operator = (const FileBase&);
-};
-
-} // namespace mbed
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/FileHandle.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,140 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILEHANDLE_H
-#define MBED_FILEHANDLE_H
-
-typedef int FILEHANDLE;
-
-#include <stdio.h>
-
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-typedef int ssize_t;
-typedef long off_t;
-
-#else
-#   include <sys/types.h>
-#endif
-
-namespace mbed {
-
-/** An OO equivalent of the internal FILEHANDLE variable
- *  and associated _sys_* functions.
- *
- * FileHandle is an abstract class, needing at least sys_write and
- *  sys_read to be implmented for a simple interactive device.
- *
- * No one ever directly tals to/instanciates a FileHandle - it gets
- *  created by FileSystem, and wrapped up by stdio.
- *
- * @Note Synchronization level: Set by subclass
- */
-class FileHandle {
-
-public:
-    /** Write the contents of a buffer to the file
-     *
-     *  @param buffer the buffer to write from
-     *  @param length the number of characters to write
-     *
-     *  @returns
-     *  The number of characters written (possibly 0) on success, -1 on error.
-     */
-    virtual ssize_t write(const void* buffer, size_t length) = 0;
-
-    /** Close the file
-     *
-     *  @returns
-     *  Zero on success, -1 on error.
-     */
-    virtual int close() = 0;
-
-    /** Function read
-     *  Reads the contents of the file into a buffer
-     *
-     *  @param buffer the buffer to read in to
-     *  @param length the number of characters to read
-     *
-     *  @returns
-     *  The number of characters read (zero at end of file) on success, -1 on error.
-     */
-    virtual ssize_t read(void* buffer, size_t length) = 0;
-
-    /** Check if the handle is for a interactive terminal device.
-     * If so, line buffered behaviour is used by default
-     *
-     *  @returns
-     *    1 if it is a terminal,
-     *    0 otherwise
-     */
-    virtual int isatty() = 0;
-
-    /** Move the file position to a given offset from a given location.
-     *
-     *  @param offset The offset from whence to move to
-     *  @param whence SEEK_SET for the start of the file, SEEK_CUR for the
-     *   current file position, or SEEK_END for the end of the file.
-     *
-     *  @returns
-     *    new file position on success,
-     *    -1 on failure or unsupported
-     */
-    virtual off_t lseek(off_t offset, int whence) = 0;
-
-    /** Flush any buffers associated with the FileHandle, ensuring it
-     *  is up to date on disk
-     *
-     *  @returns
-     *    0 on success or un-needed,
-     *   -1 on error
-     */
-    virtual int fsync() = 0;
-
-    virtual off_t flen() {
-        lock();
-        /* remember our current position */
-        off_t pos = lseek(0, SEEK_CUR);
-        if(pos == -1) {
-            unlock();
-            return -1;
-        }
-        /* seek to the end to get the file length */
-        off_t res = lseek(0, SEEK_END);
-        /* return to our old position */
-        lseek(pos, SEEK_SET);
-        unlock();
-        return res;
-    }
-
-    virtual ~FileHandle();
-
-protected:
-
-    /** Acquire exclusive access to this object.
-     */
-    virtual void lock() {
-        // Stub
-    }
-
-    /** Release exclusive access to this object.
-     */
-    virtual void unlock() {
-        // Stub
-    }
-};
-
-} // namespace mbed
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/FileLike.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,47 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILELIKE_H
-#define MBED_FILELIKE_H
-
-#include "FileBase.h"
-#include "FileHandle.h"
-
-namespace mbed {
-
-/* Class FileLike
- *  A file-like object is one that can be opened with fopen by
- *  fopen("/name", mode). It is intersection of the classes Base and
- *  FileHandle.
- *
- *  @Note Synchronization level: Set by subclass
- */
-class FileLike : public FileHandle, public FileBase {
-
-public:
-    /* Constructor FileLike
-     *
-     * Variables
-     *  name - The name to use to open the file.
-     */
-    FileLike(const char *name);
-
-    virtual ~FileLike();
-
-};
-
-} // namespace mbed
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/FilePath.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,46 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILEPATH_H
-#define MBED_FILEPATH_H
-
-#include "platform.h"
-
-#include "FileSystemLike.h"
-#include "FileLike.h"
-
-namespace mbed {
-
-class FilePath {
-public:
-    FilePath(const char* file_path);
-
-    const char* fileName(void);
-
-    bool          isFileSystem(void);
-    FileSystemLike* fileSystem(void);
-
-    bool    isFile(void);
-    FileLike* file(void);
-    bool    exists(void);
-
-private:
-    const char* file_name;
-    FileBase* fb;
-};
-
-} // namespace mbed
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/FileSystemLike.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,106 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILESYSTEMLIKE_H
-#define MBED_FILESYSTEMLIKE_H
-
-#include "platform.h"
-
-#include "FileBase.h"
-#include "FileHandle.h"
-#include "DirHandle.h"
-
-namespace mbed {
-
-/** A filesystem-like object is one that can be used to open files
- *  though it by fopen("/name/filename", mode)
- *
- *  Implementations must define at least open (the default definitions
- *  of the rest of the functions just return error values).
- *
- * @Note Synchronization level: Set by subclass
- */
-class FileSystemLike : public FileBase {
-
-public:
-    /** FileSystemLike constructor
-     *
-     *  @param name The name to use for the filesystem.
-     */
-    FileSystemLike(const char *name);
-
-    virtual ~FileSystemLike();
-
-    static DirHandle *opendir();
-    friend class BaseDirHandle;
-
-    /** Opens a file from the filesystem
-     *
-     *  @param filename The name of the file to open.
-     *  @param flags One of O_RDONLY, O_WRONLY, or O_RDWR, OR'd with
-     *    zero or more of O_CREAT, O_TRUNC, or O_APPEND.
-     *
-     *  @returns
-     *    A pointer to a FileHandle object representing the
-     *   file on success, or NULL on failure.
-     */
-    virtual FileHandle *open(const char *filename, int flags) = 0;
-
-    /** Remove a file from the filesystem.
-     *
-     *  @param filename the name of the file to remove.
-     *  @param returns 0 on success, -1 on failure.
-     */
-    virtual int remove(const char *filename) { (void) filename; return -1; };
-
-    /** Rename a file in the filesystem.
-     *
-     *  @param oldname the name of the file to rename.
-     *  @param newname the name to rename it to.
-     *
-     *  @returns
-     *    0 on success,
-     *   -1 on failure.
-     */
-    virtual int rename(const char *oldname, const char *newname) { (void) oldname, (void) newname; return -1; };
-
-    /** Opens a directory in the filesystem and returns a DirHandle
-     *   representing the directory stream.
-     *
-     *  @param name The name of the directory to open.
-     *
-     *  @returns
-     *    A DirHandle representing the directory stream, or
-     *   NULL on failure.
-     */
-    virtual DirHandle *opendir(const char *name) { (void) name; return NULL; };
-
-    /** Creates a directory in the filesystem.
-     *
-     *  @param name The name of the directory to create.
-     *  @param mode The permissions to create the directory with.
-     *
-     *  @returns
-     *    0 on success,
-     *   -1 on failure.
-     */
-    virtual int mkdir(const char *name, mode_t mode) { (void) name, (void) mode; return -1; }
-
-    // TODO other filesystem functions (mkdir, rm, rn, ls etc)
-};
-
-} // namespace mbed
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/FunctionPointer.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,72 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FUNCTIONPOINTER_H
-#define MBED_FUNCTIONPOINTER_H
-
-#include "Callback.h"
-#include "toolchain.h"
-#include <string.h>
-#include <stdint.h>
-
-namespace mbed {
-
-
-// Declarations for backwards compatibility
-// To be foward compatible, code should adopt the Callback class
-template <typename R, typename A1>
-class FunctionPointerArg1 : public Callback<R(A1)> {
-public:
-    MBED_DEPRECATED_SINCE("mbed-os-5.1",
-        "FunctionPointerArg1<R, A> has been replaced by Callback<R(A)>")
-    FunctionPointerArg1(R (*function)(A1) = 0)
-        : Callback<R(A1)>(function) {}
-
-    template<typename T>
-    MBED_DEPRECATED_SINCE("mbed-os-5.1",
-        "FunctionPointerArg1<R, A> has been replaced by Callback<R(A)>")
-    FunctionPointerArg1(T *object, R (T::*member)(A1))
-        : Callback<R(A1)>(object, member) {}
-
-    R (*get_function())(A1) {
-        return *reinterpret_cast<R (**)(A1)>(this);
-    }
-};
-
-template <typename R>
-class FunctionPointerArg1<R, void> : public Callback<R()> {
-public:
-    MBED_DEPRECATED_SINCE("mbed-os-5.1",
-        "FunctionPointer has been replaced by Callback<void()>")
-    FunctionPointerArg1(R (*function)() = 0)
-        : Callback<R()>(function) {}
-
-    template<typename T>
-    MBED_DEPRECATED_SINCE("mbed-os-5.1",
-        "FunctionPointer has been replaced by Callback<void()>")
-    FunctionPointerArg1(T *object, R (T::*member)())
-        : Callback<R()>(object, member) {}
-
-    R (*get_function())() {
-        return *reinterpret_cast<R (**)()>(this);
-    }
-};
-
-typedef FunctionPointerArg1<void, void> FunctionPointer;
-
-
-} // namespace mbed
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/I2C.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,193 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_I2C_H
-#define MBED_I2C_H
-
-#include "platform.h"
-
-#if DEVICE_I2C
-
-#include "i2c_api.h"
-#include "SingletonPtr.h"
-#include "PlatformMutex.h"
-
-#if DEVICE_I2C_ASYNCH
-#include "CThunk.h"
-#include "dma_api.h"
-#include "FunctionPointer.h"
-#endif
-
-namespace mbed {
-
-/** An I2C Master, used for communicating with I2C slave devices
- *
- * @Note Synchronization level: Thread safe
- *
- * Example:
- * @code
- * // Read from I2C slave at address 0x62
- *
- * #include "mbed.h"
- *
- * I2C i2c(p28, p27);
- *
- * int main() {
- *     int address = 0x62;
- *     char data[2];
- *     i2c.read(address, data, 2);
- * }
- * @endcode
- */
-class I2C {
-
-public:
-    enum RxStatus {
-        NoData,
-        MasterGeneralCall,
-        MasterWrite,
-        MasterRead
-    };
-
-    enum Acknowledge {
-        NoACK = 0,
-        ACK   = 1
-    };
-
-    /** Create an I2C Master interface, connected to the specified pins
-     *
-     *  @param sda I2C data line pin
-     *  @param scl I2C clock line pin
-     */
-    I2C(PinName sda, PinName scl);
-
-    /** Set the frequency of the I2C interface
-     *
-     *  @param hz The bus frequency in hertz
-     */
-    void frequency(int hz);
-
-    /** Read from an I2C slave
-     *
-     * Performs a complete read transaction. The bottom bit of
-     * the address is forced to 1 to indicate a read.
-     *
-     *  @param address 8-bit I2C slave address [ addr | 1 ]
-     *  @param data Pointer to the byte-array to read data in to
-     *  @param length Number of bytes to read
-     *  @param repeated Repeated start, true - don't send stop at end
-     *
-     *  @returns
-     *       0 on success (ack),
-     *   non-0 on failure (nack)
-     */
-    int read(int address, char *data, int length, bool repeated = false);
-
-    /** Read a single byte from the I2C bus
-     *
-     *  @param ack indicates if the byte is to be acknowledged (1 = acknowledge)
-     *
-     *  @returns
-     *    the byte read
-     */
-    int read(int ack);
-
-    /** Write to an I2C slave
-     *
-     * Performs a complete write transaction. The bottom bit of
-     * the address is forced to 0 to indicate a write.
-     *
-     *  @param address 8-bit I2C slave address [ addr | 0 ]
-     *  @param data Pointer to the byte-array data to send
-     *  @param length Number of bytes to send
-     *  @param repeated Repeated start, true - do not send stop at end
-     *
-     *  @returns
-     *       0 on success (ack),
-     *   non-0 on failure (nack)
-     */
-    int write(int address, const char *data, int length, bool repeated = false);
-
-    /** Write single byte out on the I2C bus
-     *
-     *  @param data data to write out on bus
-     *
-     *  @returns
-     *    '1' if an ACK was received,
-     *    '0' otherwise
-     */
-    int write(int data);
-
-    /** Creates a start condition on the I2C bus
-     */
-
-    void start(void);
-
-    /** Creates a stop condition on the I2C bus
-     */
-    void stop(void);
-
-    /** Acquire exclusive access to this I2C bus
-     */
-    virtual void lock(void);
-
-    /** Release exclusive access to this I2C bus
-     */
-    virtual void unlock(void);
-
-    virtual ~I2C() {
-        // Do nothing
-    }
-
-#if DEVICE_I2C_ASYNCH
-
-    /** Start non-blocking I2C transfer.
-     *
-     * @param address   8/10 bit I2c slave address
-     * @param tx_buffer The TX buffer with data to be transfered
-     * @param tx_length The length of TX buffer in bytes
-     * @param rx_buffer The RX buffer which is used for received data
-     * @param rx_length The length of RX buffer in bytes
-     * @param event     The logical OR of events to modify
-     * @param callback  The event callback function
-     * @param repeated Repeated start, true - do not send stop at end
-     * @return Zero if the transfer has started, or -1 if I2C peripheral is busy
-     */
-    int transfer(int address, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, const event_callback_t& callback, int event = I2C_EVENT_TRANSFER_COMPLETE, bool repeated = false);
-
-    /** Abort the on-going I2C transfer
-     */
-    void abort_transfer();
-protected:
-    void irq_handler_asynch(void);
-    event_callback_t _callback;
-    CThunk<I2C> _irq;
-    DMAUsage _usage;
-#endif
-
-protected:
-    void aquire();
-
-    i2c_t _i2c;
-    static I2C  *_owner;
-    int         _hz;
-    static SingletonPtr<PlatformMutex> _mutex;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/I2CSlave.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,156 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_I2C_SLAVE_H
-#define MBED_I2C_SLAVE_H
-
-#include "platform.h"
-
-#if DEVICE_I2CSLAVE
-
-#include "i2c_api.h"
-
-namespace mbed {
-
-/** An I2C Slave, used for communicating with an I2C Master device
- *
- * @Note Synchronization level: Not protected
- *
- * Example:
- * @code
- * // Simple I2C responder
- * #include <mbed.h>
- *
- * I2CSlave slave(p9, p10);
- *
- * int main() {
- *     char buf[10];
- *     char msg[] = "Slave!";
- *
- *     slave.address(0xA0);
- *     while (1) {
- *         int i = slave.receive();
- *         switch (i) {
- *             case I2CSlave::ReadAddressed:
- *                 slave.write(msg, strlen(msg) + 1); // Includes null char
- *                 break;
- *             case I2CSlave::WriteGeneral:
- *                 slave.read(buf, 10);
- *                 printf("Read G: %s\n", buf);
- *                 break;
- *             case I2CSlave::WriteAddressed:
- *                 slave.read(buf, 10);
- *                 printf("Read A: %s\n", buf);
- *                 break;
- *         }
- *         for(int i = 0; i < 10; i++) buf[i] = 0;    // Clear buffer
- *     }
- * }
- * @endcode
- */
-class I2CSlave {
-
-public:
-    enum RxStatus {
-        NoData         = 0,
-        ReadAddressed  = 1,
-        WriteGeneral   = 2,
-        WriteAddressed = 3
-    };
-
-    /** Create an I2C Slave interface, connected to the specified pins.
-     *
-     *  @param sda I2C data line pin
-     *  @param scl I2C clock line pin
-     */
-    I2CSlave(PinName sda, PinName scl);
-
-    /** Set the frequency of the I2C interface
-     *
-     *  @param hz The bus frequency in hertz
-     */
-    void frequency(int hz);
-
-    /** Checks to see if this I2C Slave has been addressed.
-     *
-     *  @returns
-     *  A status indicating if the device has been addressed, and how
-     *  - NoData            - the slave has not been addressed
-     *  - ReadAddressed     - the master has requested a read from this slave
-     *  - WriteAddressed    - the master is writing to this slave
-     *  - WriteGeneral      - the master is writing to all slave
-     */
-    int receive(void);
-
-    /** Read from an I2C master.
-     *
-     *  @param data pointer to the byte array to read data in to
-     *  @param length maximum number of bytes to read
-     *
-     *  @returns
-     *       0 on success,
-     *   non-0 otherwise
-     */
-    int read(char *data, int length);
-
-    /** Read a single byte from an I2C master.
-     *
-     *  @returns
-     *    the byte read
-     */
-    int read(void);
-
-    /** Write to an I2C master.
-     *
-     *  @param data pointer to the byte array to be transmitted
-     *  @param length the number of bytes to transmite
-     *
-     *  @returns
-     *       0 on success,
-     *   non-0 otherwise
-     */
-    int write(const char *data, int length);
-
-    /** Write a single byte to an I2C master.
-     *
-     *  @data the byte to write
-     *
-     *  @returns
-     *    '1' if an ACK was received,
-     *    '0' otherwise
-     */
-    int write(int data);
-
-    /** Sets the I2C slave address.
-     *
-     *  @param address The address to set for the slave (ignoring the least
-     *  signifcant bit). If set to 0, the slave will only respond to the
-     *  general call address.
-     */
-    void address(int address);
-
-    /** Reset the I2C slave back into the known ready receiving state.
-     */
-    void stop(void);
-
-protected:
-    i2c_t _i2c;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/InterruptIn.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,147 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_INTERRUPTIN_H
-#define MBED_INTERRUPTIN_H
-
-#include "platform.h"
-
-#if DEVICE_INTERRUPTIN
-
-#include "gpio_api.h"
-#include "gpio_irq_api.h"
-#include "Callback.h"
-#include "critical.h"
-
-namespace mbed {
-
-/** A digital interrupt input, used to call a function on a rising or falling edge
- *
- * @Note Synchronization level: Interrupt safe
- *
- * Example:
- * @code
- * // Flash an LED while waiting for events
- *
- * #include "mbed.h"
- *
- * InterruptIn event(p16);
- * DigitalOut led(LED1);
- *
- * void trigger() {
- *     printf("triggered!\n");
- * }
- *
- * int main() {
- *     event.rise(&trigger);
- *     while(1) {
- *         led = !led;
- *         wait(0.25);
- *     }
- * }
- * @endcode
- */
-class InterruptIn {
-
-public:
-
-    /** Create an InterruptIn connected to the specified pin
-     *
-     *  @param pin InterruptIn pin to connect to
-     *  @param name (optional) A string to identify the object
-     */
-    InterruptIn(PinName pin);
-    virtual ~InterruptIn();
-
-    /** Read the input, represented as 0 or 1 (int)
-     *
-     *  @returns
-     *    An integer representing the state of the input pin,
-     *    0 for logical 0, 1 for logical 1
-     */
-    int read();
-
-    /** An operator shorthand for read()
-     */
-    operator int();
-
-
-    /** Attach a function to call when a rising edge occurs on the input
-     *
-     *  @param func A pointer to a void function, or 0 to set as none
-     */
-    void rise(Callback<void()> func);
-
-    /** Attach a member function to call when a rising edge occurs on the input
-     *
-     *  @param obj pointer to the object to call the member function on
-     *  @param method pointer to the member function to be called
-     */
-    template<typename T, typename M>
-    void rise(T *obj, M method) {
-        core_util_critical_section_enter();
-        rise(Callback<void()>(obj, method));
-        core_util_critical_section_exit();
-    }
-
-    /** Attach a function to call when a falling edge occurs on the input
-     *
-     *  @param func A pointer to a void function, or 0 to set as none
-     */
-    void fall(Callback<void()> func);
-
-    /** Attach a member function to call when a falling edge occurs on the input
-     *
-     *  @param obj pointer to the object to call the member function on
-     *  @param method pointer to the member function to be called
-     */
-    template<typename T, typename M>
-    void fall(T *obj, M method) {
-        core_util_critical_section_enter();
-        fall(Callback<void()>(obj, method));
-        core_util_critical_section_exit();
-    }
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone
-     */
-    void mode(PinMode pull);
-
-    /** Enable IRQ. This method depends on hw implementation, might enable one
-     *  port interrupts. For further information, check gpio_irq_enable().
-     */
-    void enable_irq();
-
-    /** Disable IRQ. This method depends on hw implementation, might disable one
-     *  port interrupts. For further information, check gpio_irq_disable().
-     */
-    void disable_irq();
-
-    static void _irq_handler(uint32_t id, gpio_irq_event event);
-
-protected:
-    gpio_t gpio;
-    gpio_irq_t gpio_irq;
-
-    Callback<void()> _rise;
-    Callback<void()> _fall;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/InterruptManager.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,156 +0,0 @@
-#ifndef MBED_INTERRUPTMANAGER_H
-#define MBED_INTERRUPTMANAGER_H
-
-#include "cmsis.h"
-#include "CallChain.h"
-#include "PlatformMutex.h"
-#include <string.h>
-
-namespace mbed {
-
-/** Use this singleton if you need to chain interrupt handlers.
- *
- * @Note Synchronization level: Thread safe
- *
- * Example (for LPC1768):
- * @code
- * #include "InterruptManager.h"
- * #include "mbed.h"
- *
- * Ticker flipper;
- * DigitalOut led1(LED1);
- * DigitalOut led2(LED2);
- *
- * void flip(void) {
- *     led1 = !led1;
- * }
- *
- * void handler(void) {
- *     led2 = !led1;
- * }
- *
- * int main() {
- *     led1 = led2 = 0;
- *     flipper.attach(&flip, 1.0);
- *     InterruptManager::get()->add_handler(handler, TIMER3_IRQn);
- * }
- * @endcode
- */
-class InterruptManager {
-public:
-    /** Return the only instance of this class
-     */
-    static InterruptManager* get();
-
-    /** Destroy the current instance of the interrupt manager
-     */
-    static void destroy();
-
-    /** Add a handler for an interrupt at the end of the handler list
-     *
-     *  @param function the handler to add
-     *  @param irq interrupt number
-     *
-     *  @returns
-     *  The function object created for 'function'
-     */
-    pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq) {
-        // Underlying call is thread safe
-        return add_common(function, irq);
-    }
-
-    /** Add a handler for an interrupt at the beginning of the handler list
-     *
-     *  @param function the handler to add
-     *  @param irq interrupt number
-     *
-     *  @returns
-     *  The function object created for 'function'
-     */
-    pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq) {
-        // Underlying call is thread safe
-        return add_common(function, irq, true);
-    }
-
-    /** Add a handler for an interrupt at the end of the handler list
-     *
-     *  @param tptr pointer to the object that has the handler function
-     *  @param mptr pointer to the actual handler function
-     *  @param irq interrupt number
-     *
-     *  @returns
-     *  The function object created for 'tptr' and 'mptr'
-     */
-    template<typename T>
-    pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
-        // Underlying call is thread safe
-        return add_common(tptr, mptr, irq);
-    }
-
-    /** Add a handler for an interrupt at the beginning of the handler list
-     *
-     *  @param tptr pointer to the object that has the handler function
-     *  @param mptr pointer to the actual handler function
-     *  @param irq interrupt number
-     *
-     *  @returns
-     *  The function object created for 'tptr' and 'mptr'
-     */
-    template<typename T>
-    pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
-        // Underlying call is thread safe
-        return add_common(tptr, mptr, irq, true);
-    }
-
-    /** Remove a handler from an interrupt
-     *
-     *  @param handler the function object for the handler to remove
-     *  @param irq the interrupt number
-     *
-     *  @returns
-     *  true if the handler was found and removed, false otherwise
-     */
-    bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq);
-
-private:
-    InterruptManager();
-    ~InterruptManager();
-
-    void lock();
-    void unlock();
-
-    // We declare the copy contructor and the assignment operator, but we don't
-    // implement them. This way, if someone tries to copy/assign our instance,
-    // he will get an error at compile time.
-    InterruptManager(const InterruptManager&);
-    InterruptManager& operator =(const InterruptManager&);
-
-    template<typename T>
-    pFunctionPointer_t add_common(T *tptr, void (T::*mptr)(void), IRQn_Type irq, bool front=false) {
-        _mutex.lock();
-        int irq_pos = get_irq_index(irq);
-        bool change = must_replace_vector(irq);
-
-        pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(tptr, mptr) : _chains[irq_pos]->add(tptr, mptr);
-        if (change)
-            NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
-        _mutex.unlock();
-        return pf;
-    }
-
-    pFunctionPointer_t add_common(void (*function)(void), IRQn_Type irq, bool front=false);
-    bool must_replace_vector(IRQn_Type irq);
-    int get_irq_index(IRQn_Type irq);
-    void irq_helper();
-    void add_helper(void (*function)(void), IRQn_Type irq, bool front=false);
-    static void static_irq_helper();
-
-    CallChain* _chains[NVIC_NUM_VECTORS];
-    static InterruptManager* _instance;
-    PlatformMutex _mutex;
-};
-
-} // namespace mbed
-
-#endif
-

--- a/M24SR-DISCOVERY_hardware/mbed/LocalFileSystem.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,110 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_LOCALFILESYSTEM_H
-#define MBED_LOCALFILESYSTEM_H
-
-#include "platform.h"
-
-#if DEVICE_LOCALFILESYSTEM
-
-#include "FileSystemLike.h"
-#include "PlatformMutex.h"
-
-namespace mbed {
-
-FILEHANDLE local_file_open(const char* name, int flags);
-
-class LocalFileHandle : public FileHandle {
-
-public:
-    LocalFileHandle(FILEHANDLE fh);
-
-    virtual int close();
-
-    virtual ssize_t write(const void *buffer, size_t length);
-
-    virtual ssize_t read(void *buffer, size_t length);
-
-    virtual int isatty();
-
-    virtual off_t lseek(off_t position, int whence);
-
-    virtual int fsync();
-
-    virtual off_t flen();
-
-protected:
-    virtual void lock();
-    virtual void unlock();
-    FILEHANDLE _fh;
-    int pos;
-    PlatformMutex _mutex;
-};
-
-/** A filesystem for accessing the local mbed Microcontroller USB disk drive
- *
- *  This allows programs to read and write files on the same disk drive that is used to program the
- *  mbed Microcontroller. Once created, the standard C file access functions are used to open,
- *  read and write files.
- *
- * @Note Synchronization level: Thread safe
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * LocalFileSystem local("local");               // Create the local filesystem under the name "local"
- *
- * int main() {
- *     FILE *fp = fopen("/local/out.txt", "w");  // Open "out.txt" on the local file system for writing
- *     fprintf(fp, "Hello World!");
- *     fclose(fp);
- *     remove("/local/out.txt");                 // Removes the file "out.txt" from the local file system
- *
- *     DIR *d = opendir("/local");               // Opens the root directory of the local file system
- *     struct dirent *p;
- *     while((p = readdir(d)) != NULL) {         // Print the names of the files in the local file system
- *       printf("%s\n", p->d_name);              // to stdout.
- *     }
- *     closedir(d);
- * }
- * @endcode
- *
- * @note
- *  If the microcontroller program makes an access to the local drive, it will be marked as "removed"
- *  on the Host computer. This means it is no longer accessible from the Host Computer.
- *
- *  The drive will only re-appear when the microcontroller program exists. Note that if the program does
- *  not exit, you will need to hold down reset on the mbed Microcontroller to be able to see the drive again!
- */
-class LocalFileSystem : public FileSystemLike {
-    // No modifiable state
-
-public:
-    LocalFileSystem(const char* n) : FileSystemLike(n) {
-
-    }
-
-    virtual FileHandle *open(const char* name, int flags);
-    virtual int remove(const char *filename);
-    virtual DirHandle *opendir(const char *name);
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/LowPowerTicker.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,46 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_LOWPOWERTICKER_H
-#define MBED_LOWPOWERTICKER_H
-
-#include "platform.h"
-#include "Ticker.h"
-
-#if DEVICE_LOWPOWERTIMER
-
-#include "lp_ticker_api.h"
-
-namespace mbed {
-
-/** Low Power Ticker
- *
- * @Note Synchronization level: Interrupt safe
- */
-class LowPowerTicker : public Ticker {
-
-public:
-    LowPowerTicker() : Ticker(get_lp_ticker_data()) {
-    }
-
-    virtual ~LowPowerTicker() {
-    }
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/LowPowerTimeout.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,44 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_LOWPOWERTIMEOUT_H
-#define MBED_LOWPOWERTIMEOUT_H
-
-#include "platform.h"
-
-#if DEVICE_LOWPOWERTIMER
-
-#include "lp_ticker_api.h"
-#include "LowPowerTicker.h"
-
-namespace mbed {
-
-/** Low Power Timout
- *
- * @Note Synchronization level: Interrupt safe
- */
-class LowPowerTimeout : public LowPowerTicker {
-
-private:
-    virtual void handler(void) {
-        _function.call();
-    }
-};
-
-}
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/LowPowerTimer.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,44 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_LOWPOWERTIMER_H
-#define MBED_LOWPOWERTIMER_H
-
-#include "platform.h"
-#include "Timer.h"
-
-#if DEVICE_LOWPOWERTIMER
-
-#include "lp_ticker_api.h"
-
-namespace mbed {
-
-/** Low power timer
- *
- * @Note Synchronization level: Interrupt safe
- */
-class LowPowerTimer : public Timer {
-
-public:
-    LowPowerTimer() : Timer(get_lp_ticker_data()) {
-    }
-
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/PlatformMutex.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,46 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef PLATFORM_MUTEX_H
-#define PLATFORM_MUTEX_H
-
-#ifdef MBED_CONF_RTOS_PRESENT
-#include "Mutex.h"
-typedef rtos::Mutex PlatformMutex;
-#else
-/** A stub mutex for when an RTOS is not present
-*/
-class PlatformMutex {
-public:
-    PlatformMutex() {
-        // Stub
-
-    }
-    ~PlatformMutex() {
-        // Stub
-    }
-
-    void lock() {
-        // Do nothing
-    }
-
-    void unlock() {
-        // Do nothing
-    }
-};
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/PortIn.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,100 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTIN_H
-#define MBED_PORTIN_H
-
-#include "platform.h"
-
-#if DEVICE_PORTIN
-
-#include "port_api.h"
-#include "critical.h"
-
-namespace mbed {
-
-/** A multiple pin digital input
- *
- * @Note Synchronization level: Interrupt safe
- *
- *  Example:
- * @code
- * // Switch on an LED if any of mbed pins 21-26 is high
- *
- * #include "mbed.h"
- *
- * PortIn     p(Port2, 0x0000003F);   // p21-p26
- * DigitalOut ind(LED4);
- *
- * int main() {
- *     while(1) {
- *         int pins = p.read();
- *         if(pins) {
- *             ind = 1;
- *         } else {
- *             ind = 0;
- *         }
- *     }
- * }
- * @endcode
- */
-class PortIn {
-public:
-
-    /** Create an PortIn, connected to the specified port
-     *
-     *  @param port Port to connect to (Port0-Port5)
-     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
-        */
-    PortIn(PortName port, int mask = 0xFFFFFFFF) {
-        core_util_critical_section_enter();
-        port_init(&_port, port, mask, PIN_INPUT);
-        core_util_critical_section_exit();
-    }
-
-    /** Read the value currently output on the port
-     *
-     *  @returns
-     *    An integer with each bit corresponding to associated port pin setting
-     */
-    int read() {
-        return port_read(&_port);
-    }
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone, OpenDrain
-     */
-    void mode(PinMode mode) {
-        core_util_critical_section_enter();
-        port_mode(&_port, mode);
-        core_util_critical_section_exit();
-    }
-
-    /** A shorthand for read()
-     */
-    operator int() {
-        return read();
-    }
-
-private:
-    port_t _port;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/PortInOut.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,115 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTINOUT_H
-#define MBED_PORTINOUT_H
-
-#include "platform.h"
-
-#if DEVICE_PORTINOUT
-
-#include "port_api.h"
-#include "critical.h"
-
-namespace mbed {
-
-/** A multiple pin digital in/out used to set/read multiple bi-directional pins
- *
- * @Note Synchronization level: Interrupt safe
- */
-class PortInOut {
-public:
-
-    /** Create an PortInOut, connected to the specified port
-     *
-     *  @param port Port to connect to (Port0-Port5)
-     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
-     */
-    PortInOut(PortName port, int mask = 0xFFFFFFFF) {
-        core_util_critical_section_enter();
-        port_init(&_port, port, mask, PIN_INPUT);
-        core_util_critical_section_exit();
-    }
-
-    /** Write the value to the output port
-     *
-     *  @param value An integer specifying a bit to write for every corresponding port pin
-     */
-    void write(int value) {
-        port_write(&_port, value);
-    }
-
-    /** Read the value currently output on the port
-     *
-     *  @returns
-     *    An integer with each bit corresponding to associated port pin setting
-     */
-    int read() {
-        return port_read(&_port);
-    }
-
-    /** Set as an output
-     */
-    void output() {
-        core_util_critical_section_enter();
-        port_dir(&_port, PIN_OUTPUT);
-        core_util_critical_section_exit();
-    }
-
-    /** Set as an input
-     */
-    void input() {
-        core_util_critical_section_enter();
-        port_dir(&_port, PIN_INPUT);
-        core_util_critical_section_exit();
-    }
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone, OpenDrain
-     */
-    void mode(PinMode mode) {
-        core_util_critical_section_enter();
-        port_mode(&_port, mode);
-        core_util_critical_section_exit();
-    }
-
-    /** A shorthand for write()
-     */
-    PortInOut& operator= (int value) {
-        write(value);
-        return *this;
-    }
-
-    PortInOut& operator= (PortInOut& rhs) {
-        write(rhs.read());
-        return *this;
-    }
-
-    /** A shorthand for read()
-     */
-    operator int() {
-        return read();
-    }
-
-private:
-    port_t _port;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/PortOut.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,109 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTOUT_H
-#define MBED_PORTOUT_H
-
-#include "platform.h"
-
-#if DEVICE_PORTOUT
-
-#include "port_api.h"
-#include "critical.h"
-
-namespace mbed {
-/** A multiple pin digital out
- *
- * @Note Synchronization level: Interrupt safe
- *
- * Example:
- * @code
- * // Toggle all four LEDs
- *
- * #include "mbed.h"
- *
- * // LED1 = P1.18  LED2 = P1.20  LED3 = P1.21  LED4 = P1.23
- * #define LED_MASK 0x00B40000
- *
- * PortOut ledport(Port1, LED_MASK);
- *
- * int main() {
- *     while(1) {
- *         ledport = LED_MASK;
- *         wait(1);
- *         ledport = 0;
- *         wait(1);
- *     }
- * }
- * @endcode
- */
-class PortOut {
-public:
-
-    /** Create an PortOut, connected to the specified port
-     *
-     *  @param port Port to connect to (Port0-Port5)
-     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
-     */
-    PortOut(PortName port, int mask = 0xFFFFFFFF) {
-        core_util_critical_section_enter();
-        port_init(&_port, port, mask, PIN_OUTPUT);
-        core_util_critical_section_exit();
-    }
-
-    /** Write the value to the output port
-     *
-     *  @param value An integer specifying a bit to write for every corresponding PortOut pin
-     */
-    void write(int value) {
-        port_write(&_port, value);
-    }
-
-    /** Read the value currently output on the port
-     *
-     *  @returns
-     *    An integer with each bit corresponding to associated PortOut pin setting
-     */
-    int read() {
-        return port_read(&_port);
-    }
-
-    /** A shorthand for write()
-     */
-    PortOut& operator= (int value) {
-        write(value);
-        return *this;
-    }
-
-    PortOut& operator= (PortOut& rhs) {
-        write(rhs.read());
-        return *this;
-    }
-
-    /** A shorthand for read()
-     */
-    operator int() {
-        return read();
-    }
-
-private:
-    port_t _port;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/PwmOut.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,181 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PWMOUT_H
-#define MBED_PWMOUT_H
-
-#include "platform.h"
-
-#if DEVICE_PWMOUT
-#include "pwmout_api.h"
-#include "critical.h"
-
-namespace mbed {
-
-/** A pulse-width modulation digital output
- *
- * @Note Synchronization level: Interrupt safe
- *
- * Example
- * @code
- * // Fade a led on.
- * #include "mbed.h"
- *
- * PwmOut led(LED1);
- *
- * int main() {
- *     while(1) {
- *         led = led + 0.01;
- *         wait(0.2);
- *         if(led == 1.0) {
- *             led = 0;
- *         }
- *     }
- * }
- * @endcode
- *
- * @note
- *  On the LPC1768 and LPC2368, the PWMs all share the same
- *  period - if you change the period for one, you change it for all.
- *  Although routines that change the period maintain the duty cycle
- *  for its PWM, all other PWMs will require their duty cycle to be
- *  refreshed.
- */
-class PwmOut {
-
-public:
-
-    /** Create a PwmOut connected to the specified pin
-     *
-     *  @param pin PwmOut pin to connect to
-     */
-    PwmOut(PinName pin) {
-        core_util_critical_section_enter();
-        pwmout_init(&_pwm, pin);
-        core_util_critical_section_exit();
-    }
-
-    /** Set the ouput duty-cycle, specified as a percentage (float)
-     *
-     *  @param value A floating-point value representing the output duty-cycle,
-     *    specified as a percentage. The value should lie between
-     *    0.0f (representing on 0%) and 1.0f (representing on 100%).
-     *    Values outside this range will be saturated to 0.0f or 1.0f.
-     */
-    void write(float value) {
-        core_util_critical_section_enter();
-        pwmout_write(&_pwm, value);
-        core_util_critical_section_exit();
-    }
-
-    /** Return the current output duty-cycle setting, measured as a percentage (float)
-     *
-     *  @returns
-     *    A floating-point value representing the current duty-cycle being output on the pin,
-     *    measured as a percentage. The returned value will lie between
-     *    0.0f (representing on 0%) and 1.0f (representing on 100%).
-     *
-     *  @note
-     *  This value may not match exactly the value set by a previous <write>.
-     */
-    float read() {
-        core_util_critical_section_enter();
-        float val = pwmout_read(&_pwm);
-        core_util_critical_section_exit();
-        return val;
-    }
-
-    /** Set the PWM period, specified in seconds (float), keeping the duty cycle the same.
-     *
-     *  @note
-     *   The resolution is currently in microseconds; periods smaller than this
-     *   will be set to zero.
-     */
-    void period(float seconds) {
-        core_util_critical_section_enter();
-        pwmout_period(&_pwm, seconds);
-        core_util_critical_section_exit();
-    }
-
-    /** Set the PWM period, specified in milli-seconds (int), keeping the duty cycle the same.
-     */
-    void period_ms(int ms) {
-        core_util_critical_section_enter();
-        pwmout_period_ms(&_pwm, ms);
-        core_util_critical_section_exit();
-    }
-
-    /** Set the PWM period, specified in micro-seconds (int), keeping the duty cycle the same.
-     */
-    void period_us(int us) {
-        core_util_critical_section_enter();
-        pwmout_period_us(&_pwm, us);
-        core_util_critical_section_exit();
-    }
-
-    /** Set the PWM pulsewidth, specified in seconds (float), keeping the period the same.
-     */
-    void pulsewidth(float seconds) {
-        core_util_critical_section_enter();
-        pwmout_pulsewidth(&_pwm, seconds);
-        core_util_critical_section_exit();
-    }
-
-    /** Set the PWM pulsewidth, specified in milli-seconds (int), keeping the period the same.
-     */
-    void pulsewidth_ms(int ms) {
-        core_util_critical_section_enter();
-        pwmout_pulsewidth_ms(&_pwm, ms);
-        core_util_critical_section_exit();
-    }
-
-    /** Set the PWM pulsewidth, specified in micro-seconds (int), keeping the period the same.
-     */
-    void pulsewidth_us(int us) {
-        core_util_critical_section_enter();
-        pwmout_pulsewidth_us(&_pwm, us);
-        core_util_critical_section_exit();
-    }
-
-    /** A operator shorthand for write()
-     */
-    PwmOut& operator= (float value) {
-        // Underlying call is thread safe
-        write(value);
-        return *this;
-    }
-
-    PwmOut& operator= (PwmOut& rhs) {
-        // Underlying call is thread safe
-        write(rhs.read());
-        return *this;
-    }
-
-    /** An operator shorthand for read()
-     */
-    operator float() {
-        // Underlying call is thread safe
-        return read();
-    }
-
-protected:
-    pwmout_t _pwm;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/RawSerial.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,102 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_RAW_SERIAL_H
-#define MBED_RAW_SERIAL_H
-
-#include "platform.h"
-
-#if DEVICE_SERIAL
-
-#include "SerialBase.h"
-#include "serial_api.h"
-
-namespace mbed {
-
-/** A serial port (UART) for communication with other serial devices
- * This is a variation of the Serial class that doesn't use streams,
- * thus making it safe to use in interrupt handlers with the RTOS.
- *
- * Can be used for Full Duplex communication, or Simplex by specifying
- * one pin as NC (Not Connected)
- *
- * @Note Synchronization level: Not protected
- *
- * Example:
- * @code
- * // Send a char to the PC
- *
- * #include "mbed.h"
- *
- * RawSerial pc(USBTX, USBRX);
- *
- * int main() {
- *     pc.putc('A');
- * }
- * @endcode
- */
-class RawSerial: public SerialBase {
-
-public:
-    /** Create a RawSerial port, connected to the specified transmit and receive pins
-     *
-     *  @param tx Transmit pin
-     *  @param rx Receive pin
-     *
-     *  @note
-     *    Either tx or rx may be specified as NC if unused
-     */
-    RawSerial(PinName tx, PinName rx);
-
-    /** Write a char to the serial port
-     *
-     * @param c The char to write
-     *
-     * @returns The written char or -1 if an error occured
-     */
-    int putc(int c);
-
-    /** Read a char from the serial port
-     *
-     * @returns The char read from the serial port
-     */
-    int getc();
-
-    /** Write a string to the serial port
-     *
-     * @param str The string to write
-     *
-     * @returns 0 if the write succeeds, EOF for error
-     */
-    int puts(const char *str);
-
-    int printf(const char *format, ...);
-
-protected:
-
-    /** Acquire exclusive access to this serial port
-     */
-    virtual void lock(void);
-
-    /** Release exclusive access to this serial port
-     */
-    virtual void unlock(void);
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/SPI.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,261 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SPI_H
-#define MBED_SPI_H
-
-#include "platform.h"
-
-#if DEVICE_SPI
-
-#include "PlatformMutex.h"
-#include "spi_api.h"
-#include "SingletonPtr.h"
-
-#if DEVICE_SPI_ASYNCH
-#include "CThunk.h"
-#include "dma_api.h"
-#include "CircularBuffer.h"
-#include "FunctionPointer.h"
-#include "Transaction.h"
-#endif
-
-namespace mbed {
-
-/** A SPI Master, used for communicating with SPI slave devices
- *
- * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
- *
- * Most SPI devices will also require Chip Select and Reset signals. These
- * can be controlled using <DigitalOut> pins
- *
- * @Note Synchronization level: Thread safe
- *
- * Example:
- * @code
- * // Send a byte to a SPI slave, and record the response
- *
- * #include "mbed.h"
- *
- * // hardware ssel (where applicable)
- * //SPI device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
- *
- * // software ssel
- * SPI device(p5, p6, p7); // mosi, miso, sclk
- * DigitalOut cs(p8); // ssel
- *
- * int main() {
- *     // hardware ssel (where applicable)
- *     //int response = device.write(0xFF);
- *
- *     device.lock();
- *     // software ssel
- *     cs = 0;
- *     int response = device.write(0xFF);
- *     cs = 1;
- *     device.unlock();
- *
- * }
- * @endcode
- */
-class SPI {
-
-public:
-
-    /** Create a SPI master connected to the specified pins
-     *
-     *  mosi or miso can be specfied as NC if not used
-     *
-     *  @param mosi SPI Master Out, Slave In pin
-     *  @param miso SPI Master In, Slave Out pin
-     *  @param sclk SPI Clock pin
-     *  @param ssel SPI chip select pin
-     */
-    SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel=NC);
-
-    /** Configure the data transmission format
-     *
-     *  @param bits Number of bits per SPI frame (4 - 16)
-     *  @param mode Clock polarity and phase mode (0 - 3)
-     *
-     * @code
-     * mode | POL PHA
-     * -----+--------
-     *   0  |  0   0
-     *   1  |  0   1
-     *   2  |  1   0
-     *   3  |  1   1
-     * @endcode
-     */
-    void format(int bits, int mode = 0);
-
-    /** Set the spi bus clock frequency
-     *
-     *  @param hz SCLK frequency in hz (default = 1MHz)
-     */
-    void frequency(int hz = 1000000);
-
-    /** Write to the SPI Slave and return the response
-     *
-     *  @param value Data to be sent to the SPI slave
-     *
-     *  @returns
-     *    Response from the SPI slave
-    */
-    virtual int write(int value);
-
-    /** Acquire exclusive access to this SPI bus
-     */
-    virtual void lock(void);
-
-    /** Release exclusive access to this SPI bus
-     */
-    virtual void unlock(void);
-
-#if DEVICE_SPI_ASYNCH
-
-    /** Start non-blocking SPI transfer using 8bit buffers.
-     *
-     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
-     *                  the default SPI value is sent
-     * @param tx_length The length of TX buffer in bytes
-     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
-     *                  received data are ignored
-     * @param rx_length The length of RX buffer in bytes
-     * @param callback  The event callback function
-     * @param event     The logical OR of events to modify. Look at spi hal header file for SPI events.
-     * @return Zero if the transfer has started, or -1 if SPI peripheral is busy
-     */
-    template<typename Type>
-    int transfer(const Type *tx_buffer, int tx_length, Type *rx_buffer, int rx_length, const event_callback_t& callback, int event = SPI_EVENT_COMPLETE) {
-        if (spi_active(&_spi)) {
-            return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
-        }
-        start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
-        return 0;
-    }
-
-    /** Abort the on-going SPI transfer, and continue with transfer's in the queue if any.
-     */
-    void abort_transfer();
-
-    /** Clear the transaction buffer
-     */
-    void clear_transfer_buffer();
-
-    /** Clear the transaction buffer and abort on-going transfer.
-     */
-    void abort_all_transfers();
-
-    /** Configure DMA usage suggestion for non-blocking transfers
-     *
-     *  @param usage The usage DMA hint for peripheral
-     *  @return Zero if the usage was set, -1 if a transaction is on-going
-    */
-    int set_dma_usage(DMAUsage usage);
-
-protected:
-    /** SPI IRQ handler
-     *
-    */
-    void irq_handler_asynch(void);
-
-    /** Common transfer method
-     *
-     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
-     *                  the default SPI value is sent
-     * @param tx_length The length of TX buffer in bytes
-     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
-     *                  received data are ignored
-     * @param rx_length The length of RX buffer in bytes
-     * @param bit_width The buffers element width
-     * @param callback  The event callback function
-     * @param event     The logical OR of events to modify
-     * @return Zero if the transfer has started or was added to the queue, or -1 if SPI peripheral is busy/buffer is full
-    */
-    int transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
-
-    /**
-     *
-     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
-     *                  the default SPI value is sent
-     * @param tx_length The length of TX buffer in bytes
-     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
-     *                  received data are ignored
-     * @param rx_length The length of RX buffer in bytes
-     * @param bit_width The buffers element width
-     * @param callback  The event callback function
-     * @param event     The logical OR of events to modify
-     * @return Zero if a transfer was added to the queue, or -1 if the queue is full
-    */
-    int queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
-
-    /** Configures a callback, spi peripheral and initiate a new transfer
-     *
-     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
-     *                  the default SPI value is sent
-     * @param tx_length The length of TX buffer in bytes
-     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
-     *                  received data are ignored
-     * @param rx_length The length of RX buffer in bytes
-     * @param bit_width The buffers element width
-     * @param callback  The event callback function
-     * @param event     The logical OR of events to modify
-    */
-    void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
-
-#if TRANSACTION_QUEUE_SIZE_SPI
-
-    /** Start a new transaction
-     *
-     *  @param data Transaction data
-    */
-    void start_transaction(transaction_t *data);
-
-    /** Dequeue a transaction
-     *
-    */
-    void dequeue_transaction();
-    static CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> _transaction_buffer;
-#endif
-
-#endif
-
-public:
-    virtual ~SPI() {
-    }
-
-protected:
-    spi_t _spi;
-
-#if DEVICE_SPI_ASYNCH
-    CThunk<SPI> _irq;
-    event_callback_t _callback;
-    DMAUsage _usage;
-#endif
-
-    void aquire(void);
-    static SPI *_owner;
-    static SingletonPtr<PlatformMutex> _mutex;
-    int _bits;
-    int _mode;
-    int _hz;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/SPISlave.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,124 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SPISLAVE_H
-#define MBED_SPISLAVE_H
-
-#include "platform.h"
-
-#if DEVICE_SPISLAVE
-
-#include "spi_api.h"
-
-namespace mbed {
-
-/** A SPI slave, used for communicating with a SPI Master device
- *
- * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
- *
- * @Note Synchronization level: Not protected
- *
- * Example:
- * @code
- * // Reply to a SPI master as slave
- *
- * #include "mbed.h"
- *
- * SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
- *
- * int main() {
- *     device.reply(0x00);              // Prime SPI with first reply
- *     while(1) {
- *         if(device.receive()) {
- *             int v = device.read();   // Read byte from master
- *             v = (v + 1) % 0x100;     // Add one to it, modulo 256
- *             device.reply(v);         // Make this the next reply
- *         }
- *     }
- * }
- * @endcode
- */
-class SPISlave {
-
-public:
-
-    /** Create a SPI slave connected to the specified pins
-     *
-     *  mosi or miso can be specfied as NC if not used
-     *
-     *  @param mosi SPI Master Out, Slave In pin
-     *  @param miso SPI Master In, Slave Out pin
-     *  @param sclk SPI Clock pin
-     *  @param ssel SPI chip select pin
-     */
-    SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel);
-
-    /** Configure the data transmission format
-     *
-     *  @param bits Number of bits per SPI frame (4 - 16)
-     *  @param mode Clock polarity and phase mode (0 - 3)
-     *
-     * @code
-     * mode | POL PHA
-     * -----+--------
-     *   0  |  0   0
-     *   1  |  0   1
-     *   2  |  1   0
-     *   3  |  1   1
-     * @endcode
-     */
-    void format(int bits, int mode = 0);
-
-    /** Set the spi bus clock frequency
-     *
-     *  @param hz SCLK frequency in hz (default = 1MHz)
-     */
-    void frequency(int hz = 1000000);
-
-    /** Polls the SPI to see if data has been received
-     *
-     *  @returns
-     *    0 if no data,
-     *    1 otherwise
-     */
-    int receive(void);
-
-    /** Retrieve  data from receive buffer as slave
-     *
-     *  @returns
-     *    the data in the receive buffer
-     */
-    int read(void);
-
-    /** Fill the transmission buffer with the value to be written out
-     *  as slave on the next received message from the master.
-     *
-     *  @param value the data to be transmitted next
-     */
-    void reply(int value);
-
-protected:
-    spi_t _spi;
-
-    int _bits;
-    int _mode;
-    int _hz;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/Serial.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,81 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SERIAL_H
-#define MBED_SERIAL_H
-
-#include "platform.h"
-
-#if DEVICE_SERIAL
-
-#include "Stream.h"
-#include "SerialBase.h"
-#include "PlatformMutex.h"
-#include "serial_api.h"
-
-namespace mbed {
-
-/** A serial port (UART) for communication with other serial devices
- *
- * Can be used for Full Duplex communication, or Simplex by specifying
- * one pin as NC (Not Connected)
- *
- * @Note Synchronization level: Thread safe
- *
- * Example:
- * @code
- * // Print "Hello World" to the PC
- *
- * #include "mbed.h"
- *
- * Serial pc(USBTX, USBRX);
- *
- * int main() {
- *     pc.printf("Hello World\n");
- * }
- * @endcode
- */
-class Serial : public SerialBase, public Stream {
-
-public:
-#if DEVICE_SERIAL_ASYNCH
-    using SerialBase::read;
-    using SerialBase::write;
-#endif
-
-    /** Create a Serial port, connected to the specified transmit and receive pins
-     *
-     *  @param tx Transmit pin
-     *  @param rx Receive pin
-     *
-     *  @note
-     *    Either tx or rx may be specified as NC if unused
-     */
-    Serial(PinName tx, PinName rx, const char *name=NULL);
-
-protected:
-    virtual int _getc();
-    virtual int _putc(int c);
-    virtual void lock();
-    virtual void unlock();
-
-    PlatformMutex _mutex;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/SerialBase.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,243 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SERIALBASE_H
-#define MBED_SERIALBASE_H
-
-#include "platform.h"
-
-#if DEVICE_SERIAL
-
-#include "Stream.h"
-#include "Callback.h"
-#include "serial_api.h"
-
-#if DEVICE_SERIAL_ASYNCH
-#include "CThunk.h"
-#include "dma_api.h"
-#endif
-
-namespace mbed {
-
-/** A base class for serial port implementations
- * Can't be instantiated directly (use Serial or RawSerial)
- *
- * @Note Synchronization level: Set by subclass
- */
-class SerialBase {
-
-public:
-    /** Set the baud rate of the serial port
-     *
-     *  @param baudrate The baudrate of the serial port (default = 9600).
-     */
-    void baud(int baudrate);
-
-    enum Parity {
-        None = 0,
-        Odd,
-        Even,
-        Forced1,
-        Forced0
-    };
-
-    enum IrqType {
-        RxIrq = 0,
-        TxIrq
-    };
-
-    enum Flow {
-        Disabled = 0,
-        RTS,
-        CTS,
-        RTSCTS
-    };
-
-    /** Set the transmission format used by the serial port
-     *
-     *  @param bits The number of bits in a word (5-8; default = 8)
-     *  @param parity The parity used (SerialBase::None, SerialBase::Odd, SerialBase::Even, SerialBase::Forced1, SerialBase::Forced0; default = SerialBase::None)
-     *  @param stop The number of stop bits (1 or 2; default = 1)
-     */
-    void format(int bits=8, Parity parity=SerialBase::None, int stop_bits=1);
-
-    /** Determine if there is a character available to read
-     *
-     *  @returns
-     *    1 if there is a character available to read,
-     *    0 otherwise
-     */
-    int readable();
-
-    /** Determine if there is space available to write a character
-     *
-     *  @returns
-     *    1 if there is space to write a character,
-     *    0 otherwise
-     */
-    int writeable();
-
-    /** Attach a function to call whenever a serial interrupt is generated
-     *
-     *  @param func A pointer to a void function, or 0 to set as none
-     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
-     */
-    void attach(Callback<void()> func, IrqType type=RxIrq);
-
-    /** Attach a member function to call whenever a serial interrupt is generated
-     *
-     *  @param obj pointer to the object to call the member function on
-     *  @param method pointer to the member function to be called
-     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
-     */
-    template<typename T>
-    void attach(T *obj, void (T::*method)(), IrqType type=RxIrq) {
-        attach(Callback<void()>(obj, method), type);
-    }
-
-    /** Attach a member function to call whenever a serial interrupt is generated
-     *
-     *  @param obj pointer to the object to call the member function on
-     *  @param method pointer to the member function to be called
-     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
-     */
-    template<typename T>
-    void attach(T *obj, void (*method)(T*), IrqType type=RxIrq) {
-        attach(Callback<void()>(obj, method), type);
-    }
-
-    /** Generate a break condition on the serial line
-     */
-    void send_break();
-
-protected:
-
-    /** Acquire exclusive access to this serial port
-     */
-    virtual void lock(void);
-
-    /** Release exclusive access to this serial port
-     */
-    virtual void unlock(void);
-
-public:
-
-#if DEVICE_SERIAL_FC
-    /** Set the flow control type on the serial port
-     *
-     *  @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
-     *  @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
-     *  @param flow2 the second flow control pin (CTS for RTSCTS)
-     */
-    void set_flow_control(Flow type, PinName flow1=NC, PinName flow2=NC);
-#endif
-
-    static void _irq_handler(uint32_t id, SerialIrq irq_type);
-
-#if DEVICE_SERIAL_ASYNCH
-
-    /** Begin asynchronous write using 8bit buffer. The completition invokes registered TX event callback
-     *
-     *  @param buffer   The buffer where received data will be stored
-     *  @param length   The buffer length in bytes
-     *  @param callback The event callback function
-     *  @param event    The logical OR of TX events
-     */
-    int write(const uint8_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_TX_COMPLETE);
-
-    /** Begin asynchronous write using 16bit buffer. The completition invokes registered TX event callback
-     *
-     *  @param buffer   The buffer where received data will be stored
-     *  @param length   The buffer length in bytes
-     *  @param callback The event callback function
-     *  @param event    The logical OR of TX events
-     */
-    int write(const uint16_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_TX_COMPLETE);
-
-    /** Abort the on-going write transfer
-     */
-    void abort_write();
-
-    /** Begin asynchronous reading using 8bit buffer. The completition invokes registred RX event callback.
-     *
-     *  @param buffer     The buffer where received data will be stored
-     *  @param length     The buffer length in bytes
-     *  @param callback   The event callback function
-     *  @param event      The logical OR of RX events
-     *  @param char_match The matching character
-     */
-    int read(uint8_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
-
-    /** Begin asynchronous reading using 16bit buffer. The completition invokes registred RX event callback.
-     *
-     *  @param buffer     The buffer where received data will be stored
-     *  @param length     The buffer length in bytes
-     *  @param callback   The event callback function
-     *  @param event      The logical OR of RX events
-     *  @param char_match The matching character
-     */
-    int read(uint16_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
-
-    /** Abort the on-going read transfer
-     */
-    void abort_read();
-
-    /** Configure DMA usage suggestion for non-blocking TX transfers
-     *
-     *  @param usage The usage DMA hint for peripheral
-     *  @return Zero if the usage was set, -1 if a transaction is on-going
-     */
-    int set_dma_usage_tx(DMAUsage usage);
-
-    /** Configure DMA usage suggestion for non-blocking RX transfers
-     *
-     *  @param usage The usage DMA hint for peripheral
-     *  @return Zero if the usage was set, -1 if a transaction is on-going
-     */
-    int set_dma_usage_rx(DMAUsage usage);
-
-protected:
-    void start_read(void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event, unsigned char char_match);
-    void start_write(const void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event);
-    void interrupt_handler_asynch(void);
-#endif
-
-protected:
-    SerialBase(PinName tx, PinName rx);
-    virtual ~SerialBase() {
-    }
-
-    int _base_getc();
-    int _base_putc(int c);
-
-#if DEVICE_SERIAL_ASYNCH
-    CThunk<SerialBase> _thunk_irq;
-    event_callback_t _tx_callback;
-    event_callback_t _rx_callback;
-    DMAUsage _tx_usage;
-    DMAUsage _rx_usage;
-#endif
-
-    serial_t         _serial;
-    Callback<void()> _irq[2];
-    int              _baud;
-
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/SingletonPtr.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,105 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef SINGLETONPTR_H
-#define SINGLETONPTR_H
-
-#include <stdint.h>
-#include <new>
-#include "mbed_assert.h"
-#ifdef MBED_CONF_RTOS_PRESENT
-#include "cmsis_os.h"
-#endif
-
-#ifdef MBED_CONF_RTOS_PRESENT
-extern osMutexId singleton_mutex_id;
-#endif
-
-/** Lock the singleton mutex
- *
- * This function is typically used to provide
- * exclusive access when initializing a
- * global object.
- */
-inline static void singleton_lock(void)
-{
-#ifdef MBED_CONF_RTOS_PRESENT
-    osMutexWait(singleton_mutex_id, osWaitForever);
-#endif
-}
-
-/** Unlock the singleton mutex
- *
- * This function is typically used to provide
- * exclusive access when initializing a
- * global object.
- */
-inline static void singleton_unlock(void)
-{
-#ifdef MBED_CONF_RTOS_PRESENT
-    osMutexRelease (singleton_mutex_id);
-#endif
-}
-
-/** Utility class for creating an using a singleton
- *
- * @Note Synchronization level: Thread safe
- *
- * @Note: This class must only be used in a static context -
- * this class must never be allocated or created on the
- * stack.
- *
- * @Note: This class is lazily initialized on first use.
- * This class is a POD type so if it is not used it will
- * be garbage collected.
- */
-template <class T>
-struct SingletonPtr {
-
-    /** Get a pointer to the underlying singleton
-     *
-     * @returns
-     *   A pointer to the singleton
-     */
-    T* get() {
-        if (NULL == _ptr) {
-            singleton_lock();
-            if (NULL == _ptr) {
-                _ptr = new (_data) T();
-            }
-            singleton_unlock();
-        }
-        // _ptr was not zero initialized or was
-        // corrupted if this assert is hit
-        MBED_ASSERT(_ptr == (T *)&_data);
-        return _ptr;
-    }
-
-    /** Get a pointer to the underlying singleton
-     *
-     * @returns
-     *   A pointer to the singleton
-     */
-    T* operator->() {
-        return get();
-    }
-
-    // This is zero initialized when in global scope
-    T *_ptr;
-    // Force data to be 4 byte aligned
-    uint32_t _data[(sizeof(T) + sizeof(uint32_t) - 1) / sizeof(uint32_t)];
-};
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/Stream.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,72 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_STREAM_H
-#define MBED_STREAM_H
-
-#include "platform.h"
-#include "FileLike.h"
-#include <cstdarg>
-
-namespace mbed {
-
-extern void mbed_set_unbuffered_stream(FILE *_file);
-extern int mbed_getc(FILE *_file);
-extern char* mbed_gets(char *s, int size, FILE *_file);
-
-/** File stream
- *
- * @Note Synchronization level: Set by subclass
- */
-class Stream : public FileLike {
-
-public:
-    Stream(const char *name=NULL);
-    virtual ~Stream();
-
-    int putc(int c);
-    int puts(const char *s);
-    int getc();
-    char *gets(char *s, int size);
-    int printf(const char* format, ...);
-    int scanf(const char* format, ...);
-    int vprintf(const char* format, std::va_list args);
-    int vscanf(const char* format, std::va_list args);
-
-    operator std::FILE*() {return _file;}
-
-protected:
-    virtual int close();
-    virtual ssize_t write(const void* buffer, size_t length);
-    virtual ssize_t read(void* buffer, size_t length);
-    virtual off_t lseek(off_t offset, int whence);
-    virtual int isatty();
-    virtual int fsync();
-    virtual off_t flen();
-
-    virtual int _putc(int c) = 0;
-    virtual int _getc() = 0;
-
-    std::FILE *_file;
-
-    /* disallow copy constructor and assignment operators */
-private:
-    Stream(const Stream&);
-    Stream & operator = (const Stream&);
-};
-
-} // namespace mbed
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/TARGET_STM/TARGET_STM32F1/PeripheralPins.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,67 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_PERIPHERALPINS_H
-#define MBED_PERIPHERALPINS_H
-
-#include "pinmap.h"
-#include "PeripheralNames.h"
-
-//*** ADC ***
-
-extern const PinMap PinMap_ADC[];
-
-//*** I2C ***
-
-extern const PinMap PinMap_I2C_SDA[];
-extern const PinMap PinMap_I2C_SCL[];
-
-//*** PWM ***
-
-extern const PinMap PinMap_PWM[];
-
-//*** SERIAL ***
-
-extern const PinMap PinMap_UART_TX[];
-extern const PinMap PinMap_UART_RX[];
-
-//*** SPI ***
-
-extern const PinMap PinMap_SPI_MOSI[];
-extern const PinMap PinMap_SPI_MISO[];
-extern const PinMap PinMap_SPI_SCLK[];
-extern const PinMap PinMap_SPI_SSEL[];
-
-//*** CAN ***
-
-extern const PinMap PinMap_CAN_RD[];
-extern const PinMap PinMap_CAN_TD[];
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralNames.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,78 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    ADC_1 = (int)ADC1_BASE
-} ADCName;
-
-typedef enum {
-    UART_1 = (int)USART1_BASE,
-    UART_2 = (int)USART2_BASE,
-    UART_3 = (int)USART3_BASE
-} UARTName;
-
-#define STDIO_UART_TX  PA_2
-#define STDIO_UART_RX  PA_3
-#define STDIO_UART     UART_2
-
-typedef enum {
-    SPI_1 = (int)SPI1_BASE,
-    SPI_2 = (int)SPI2_BASE
-} SPIName;
-
-typedef enum {
-    I2C_1 = (int)I2C1_BASE,
-    I2C_2 = (int)I2C2_BASE
-} I2CName;
-
-typedef enum {
-    PWM_1 = (int)TIM1_BASE,
-    PWM_2 = (int)TIM2_BASE,
-    PWM_3 = (int)TIM3_BASE,
-    PWM_4 = (int)TIM4_BASE
-} PWMName;
-
-typedef enum {
-    CAN_1 = (int)CAN1_BASE
-} CANName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,191 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((MODE  & 0x0F) << 0) |\
-                                                ((PUPD  & 0x07) << 4) |\
-                                                ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((MODE     & 0x0F) <<  0) |\
-                                                                       ((PUPD     & 0x07) <<  4) |\
-                                                                       ((AFNUM    & 0x0F) <<  7) |\
-                                                                       ((CHANNEL  & 0x0F) << 11) |\
-                                                                       ((INVERTED & 0x01) << 15)))
-
-#define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
-
-#define STM_MODE_INPUT              (0)
-#define STM_MODE_OUTPUT_PP          (1)
-#define STM_MODE_OUTPUT_OD          (2)
-#define STM_MODE_AF_PP              (3)
-#define STM_MODE_AF_OD              (4)
-#define STM_MODE_ANALOG             (5)
-#define STM_MODE_IT_RISING          (6)
-#define STM_MODE_IT_FALLING         (7)
-#define STM_MODE_IT_RISING_FALLING  (8)
-#define STM_MODE_EVT_RISING         (9)
-#define STM_MODE_EVT_FALLING        (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET       (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble  = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X)  ((uint32_t)(X) & 0xF)
-
-typedef enum {
-    PIN_INPUT,
-    PIN_OUTPUT
-} PinDirection;
-
-typedef enum {
-    PA_0  = 0x00,
-    PA_1  = 0x01,
-    PA_2  = 0x02,
-    PA_3  = 0x03,
-    PA_4  = 0x04,
-    PA_5  = 0x05,
-    PA_6  = 0x06,
-    PA_7  = 0x07,
-    PA_8  = 0x08,
-    PA_9  = 0x09,
-    PA_10 = 0x0A,
-    PA_11 = 0x0B,
-    PA_12 = 0x0C,
-    PA_13 = 0x0D,
-    PA_14 = 0x0E,
-    PA_15 = 0x0F,
-
-    PB_0  = 0x10,
-    PB_1  = 0x11,
-    PB_2  = 0x12,
-    PB_3  = 0x13,
-    PB_4  = 0x14,
-    PB_5  = 0x15,
-    PB_6  = 0x16,
-    PB_7  = 0x17,
-    PB_8  = 0x18,
-    PB_9  = 0x19,
-    PB_10 = 0x1A,
-    PB_11 = 0x1B,
-    PB_12 = 0x1C,
-    PB_13 = 0x1D,
-    PB_14 = 0x1E,
-    PB_15 = 0x1F,
-
-    PC_0  = 0x20,
-    PC_1  = 0x21,
-    PC_2  = 0x22,
-    PC_3  = 0x23,
-    PC_4  = 0x24,
-    PC_5  = 0x25,
-    PC_6  = 0x26,
-    PC_7  = 0x27,
-    PC_8  = 0x28,
-    PC_9  = 0x29,
-    PC_10 = 0x2A,
-    PC_11 = 0x2B,
-    PC_12 = 0x2C,
-    PC_13 = 0x2D,
-    PC_14 = 0x2E,
-    PC_15 = 0x2F,
-
-    PD_2  = 0x32,
-
-    // Arduino connector namings
-    A0          = PA_0,
-    A1          = PA_1,
-    A2          = PA_4,
-    A3          = PB_0,
-    A4          = PC_1,
-    A5          = PC_0,
-    D0          = PA_3,
-    D1          = PA_2,
-    D2          = PA_10,
-    D3          = PB_3,
-    D4          = PB_5,
-    D5          = PB_4,
-    D6          = PB_10,
-    D7          = PA_8,
-    D8          = PA_9,
-    D9          = PC_7,
-    D10         = PB_6,
-    D11         = PA_7,
-    D12         = PA_6,
-    D13         = PA_5,
-    D14         = PB_9,
-    D15         = PB_8,
-
-    // Generic signals namings
-    LED1        = PA_5,
-    LED2        = PA_5,
-    LED3        = PA_5,
-    LED4        = PA_5,
-    USER_BUTTON = PC_13,
-    SERIAL_TX   = PA_2,
-    SERIAL_RX   = PA_3,
-    USBTX       = PA_2,
-    USBRX       = PA_3,
-    I2C_SCL     = PB_8,
-    I2C_SDA     = PB_9,
-    SPI_MOSI    = PA_7,
-    SPI_MISO    = PA_6,
-    SPI_SCK     = PA_5,
-    SPI_CS      = PB_6,
-    PWM_OUT     = PB_3,
-
-    // Not connected
-    NC = (int)0xFFFFFFFF
-} PinName;
-
-typedef enum {
-    PullNone  = 0,
-    PullUp    = 1,
-    PullDown  = 2,
-    OpenDrain = 3,
-    PullDefault = PullNone
-} PinMode;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PortNames.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    PortA = 0,
-    PortB = 1,
-    PortC = 2,
-    PortD = 3,
-    PortE = 4
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,105 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
-    IRQn_Type irq_n;
-    uint32_t irq_index;
-    uint32_t event;
-    PinName pin;
-};
-
-struct port_s {
-    PortName port;
-    uint32_t mask;
-    PinDirection direction;
-    __IO uint32_t *reg_in;
-    __IO uint32_t *reg_out;
-};
-
-struct analogin_s {
-    ADCName adc;
-    PinName pin;
-    uint8_t channel;
-};
-
-struct serial_s {
-    UARTName uart;
-    int index; // Used by irq
-    uint32_t baudrate;
-    uint32_t databits;
-    uint32_t stopbits;
-    uint32_t parity;
-    PinName pin_tx;
-    PinName pin_rx;
-};
-
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
-struct i2c_s {
-    I2CName  i2c;
-    uint32_t slave;
-};
-
-struct can_s {
-    CANName can;
-    int index;
-};
-
-#include "common_objects.h"
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/TARGET_STM/TARGET_STM32F1/common_objects.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,59 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_COMMON_OBJECTS_H
-#define MBED_COMMON_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct pwmout_s {
-    PWMName pwm;
-    PinName pin;
-    uint32_t prescaler;
-    uint32_t period;
-    uint32_t pulse;
-    uint8_t channel;
-    uint8_t inverted;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/TARGET_STM/TARGET_STM32F1/gpio_object.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,75 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-    PinName  pin;
-    uint32_t mask;
-    __IO uint32_t *reg_in;
-    __IO uint32_t *reg_set;
-    __IO uint32_t *reg_clr;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value)
-{
-    MBED_ASSERT(obj->pin != (PinName)NC);
-    if (value) {
-        *obj->reg_set = obj->mask;
-    } else {
-        *obj->reg_clr = obj->mask;
-    }
-}
-
-static inline int gpio_read(gpio_t *obj)
-{
-    MBED_ASSERT(obj->pin != (PinName)NC);
-    return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-static inline int gpio_is_connected(const gpio_t *obj) {
-    return obj->pin != (PinName)NC;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/STM32F103XB.ld	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,154 +0,0 @@
-/* Linker script to configure memory regions. */
-MEMORY
-{ 
-  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
-  RAM (rwx) : ORIGIN = 0x200000EC, LENGTH = 20K - 0xEC
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- * 
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   _estack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-    .text :
-    {
-        KEEP(*(.isr_vector))
-        *(.text*)
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        *(.rodata*)
-
-        KEEP(*(.eh_frame*))
-    } > FLASH
-
-    .ARM.extab : 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > FLASH
-
-    __exidx_start = .;
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > FLASH
-    __exidx_end = .;
-
-    __etext = .;
-    _sidata = .;
-
-    .data : AT (__etext)
-    {
-        __data_start__ = .;
-        _sdata = .;
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        KEEP(*(.jcr*))
-        . = ALIGN(4);
-        /* All data end */
-        __data_end__ = .;
-        _edata = .;
-
-    } > RAM
-
-    .bss :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        _sbss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-        _ebss = .;
-    } > RAM
-    
-    .heap (COPY):
-    {
-        __end__ = .;
-        end = __end__;
-        *(.heap*)
-        __HeapLimit = .;
-    } > RAM
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (COPY):
-    {
-        *(.stack*)
-    } > RAM
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    _estack = __StackTop;
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    PROVIDE(__stack = __StackTop);
-    
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}
-

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--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/arm_common_tables.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,136 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
-*
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*
-* Project: 	    CMSIS DSP Library
-* Title:	    arm_common_tables.h
-*
-* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
-*
-* Target Processor: Cortex-M4/Cortex-M3
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-#ifndef _ARM_COMMON_TABLES_H
-#define _ARM_COMMON_TABLES_H
-
-#include "arm_math.h"
-
-extern const uint16_t armBitRevTable[1024];
-extern const q15_t armRecipTableQ15[64];
-extern const q31_t armRecipTableQ31[64];
-//extern const q31_t realCoefAQ31[1024];
-//extern const q31_t realCoefBQ31[1024];
-extern const float32_t twiddleCoef_16[32];
-extern const float32_t twiddleCoef_32[64];
-extern const float32_t twiddleCoef_64[128];
-extern const float32_t twiddleCoef_128[256];
-extern const float32_t twiddleCoef_256[512];
-extern const float32_t twiddleCoef_512[1024];
-extern const float32_t twiddleCoef_1024[2048];
-extern const float32_t twiddleCoef_2048[4096];
-extern const float32_t twiddleCoef_4096[8192];
-#define twiddleCoef twiddleCoef_4096
-extern const q31_t twiddleCoef_16_q31[24];
-extern const q31_t twiddleCoef_32_q31[48];
-extern const q31_t twiddleCoef_64_q31[96];
-extern const q31_t twiddleCoef_128_q31[192];
-extern const q31_t twiddleCoef_256_q31[384];
-extern const q31_t twiddleCoef_512_q31[768];
-extern const q31_t twiddleCoef_1024_q31[1536];
-extern const q31_t twiddleCoef_2048_q31[3072];
-extern const q31_t twiddleCoef_4096_q31[6144];
-extern const q15_t twiddleCoef_16_q15[24];
-extern const q15_t twiddleCoef_32_q15[48];
-extern const q15_t twiddleCoef_64_q15[96];
-extern const q15_t twiddleCoef_128_q15[192];
-extern const q15_t twiddleCoef_256_q15[384];
-extern const q15_t twiddleCoef_512_q15[768];
-extern const q15_t twiddleCoef_1024_q15[1536];
-extern const q15_t twiddleCoef_2048_q15[3072];
-extern const q15_t twiddleCoef_4096_q15[6144];
-extern const float32_t twiddleCoef_rfft_32[32];
-extern const float32_t twiddleCoef_rfft_64[64];
-extern const float32_t twiddleCoef_rfft_128[128];
-extern const float32_t twiddleCoef_rfft_256[256];
-extern const float32_t twiddleCoef_rfft_512[512];
-extern const float32_t twiddleCoef_rfft_1024[1024];
-extern const float32_t twiddleCoef_rfft_2048[2048];
-extern const float32_t twiddleCoef_rfft_4096[4096];
-
-
-/* floating-point bit reversal tables */
-#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
-#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
-#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
-#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
-#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
-#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
-#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
-#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
-#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
-
-/* fixed-point bit reversal tables */
-#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
-#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
-#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
-#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
-#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
-#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
-#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
-#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
-#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
-
-/* Tables for Fast Math Sine and Cosine */
-extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
-extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
-extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
-
-#endif /*  ARM_COMMON_TABLES_H */

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/arm_const_structs.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,79 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
-*
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*
-* Project: 	    CMSIS DSP Library
-* Title:	    arm_const_structs.h
-*
-* Description:	This file has constant structs that are initialized for
-*              user convenience.  For example, some can be given as
-*              arguments to the arm_cfft_f32() function.
-*
-* Target Processor: Cortex-M4/Cortex-M3
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-#ifndef _ARM_CONST_STRUCTS_H
-#define _ARM_CONST_STRUCTS_H
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
-
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
-
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/arm_math.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,7556 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
-*
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*
-* Project: 	    CMSIS DSP Library
-* Title:	    arm_math.h
-*
-* Description:	Public header file for CMSIS DSP Library
-*
-* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
- * -------------------------------------------------------------------- */
-
-/**
-   \mainpage CMSIS DSP Software Library
-   *
-   * Introduction
-   * ------------
-   *
-   * This user manual describes the CMSIS DSP software library,
-   * a suite of common signal processing functions for use on Cortex-M processor based devices.
-   *
-   * The library is divided into a number of functions each covering a specific category:
-   * - Basic math functions
-   * - Fast math functions
-   * - Complex math functions
-   * - Filters
-   * - Matrix functions
-   * - Transforms
-   * - Motor control functions
-   * - Statistical functions
-   * - Support functions
-   * - Interpolation functions
-   *
-   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
-   * 32-bit integer and 32-bit floating-point values.
-   *
-   * Using the Library
-   * ------------
-   *
-   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
-   * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
-   * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
-   * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
-   * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
-   * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
-   * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
-   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
-   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
-   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
-   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
-   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
-   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
-   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
-   * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
-   *
-   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
-   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
-   * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
-   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
-   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
-   *
-   * Examples
-   * --------
-   *
-   * The library ships with a number of examples which demonstrate how to use the library functions.
-   *
-   * Toolchain Support
-   * ------------
-   *
-   * The library has been developed and tested with MDK-ARM version 5.14.0.0
-   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
-   *
-   * Building the Library
-   * ------------
-   *
-   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
-   * - arm_cortexM_math.uvprojx
-   *
-   *
-   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
-   *
-   * Pre-processor Macros
-   * ------------
-   *
-   * Each library project have differant pre-processor macros.
-   *
-   * - UNALIGNED_SUPPORT_DISABLE:
-   *
-   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
-   *
-   * - ARM_MATH_BIG_ENDIAN:
-   *
-   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
-   *
-   * - ARM_MATH_MATRIX_CHECK:
-   *
-   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
-   *
-   * - ARM_MATH_ROUNDING:
-   *
-   * Define macro ARM_MATH_ROUNDING for rounding on support functions
-   *
-   * - ARM_MATH_CMx:
-   *
-   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
-   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
-   * ARM_MATH_CM7 for building the library on cortex-M7.
-   *
-   * - __FPU_PRESENT:
-   *
-   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
-   *
-   * <hr>
-   * CMSIS-DSP in ARM::CMSIS Pack
-   * -----------------------------
-   * 
-   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
-   * |File/Folder                   |Content                                                                 |
-   * |------------------------------|------------------------------------------------------------------------|
-   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
-   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
-   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
-   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
-   * 
-   * <hr>
-   * Revision History of CMSIS-DSP
-   * ------------
-   * Please refer to \ref ChangeLog_pg.
-   *
-   * Copyright Notice
-   * ------------
-   *
-   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
-   */
-
-
-/**
- * @defgroup groupMath Basic Math Functions
- */
-
-/**
- * @defgroup groupFastMath Fast Math Functions
- * This set of functions provides a fast approximation to sine, cosine, and square root.
- * As compared to most of the other functions in the CMSIS math library, the fast math functions
- * operate on individual values and not arrays.
- * There are separate functions for Q15, Q31, and floating-point data.
- *
- */
-
-/**
- * @defgroup groupCmplxMath Complex Math Functions
- * This set of functions operates on complex data vectors.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * In the API functions, the number of samples in a complex array refers
- * to the number of complex values; the array contains twice this number of
- * real values.
- */
-
-/**
- * @defgroup groupFilters Filtering Functions
- */
-
-/**
- * @defgroup groupMatrix Matrix Functions
- *
- * This set of functions provides basic matrix math operations.
- * The functions operate on matrix data structures.  For example,
- * the type
- * definition for the floating-point matrix structure is shown
- * below:
- * <pre>
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- * </pre>
- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data.  The array is of size <code>numRows X numCols</code>
- * and the values are arranged in row order.  That is, the
- * matrix element (i, j) is stored at:
- * <pre>
- *     pData[i*numCols + j]
- * </pre>
- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure.  For example:
- * <pre>
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
- * </pre>
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
- * specifies the number of columns, and <code>pData</code> points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices.  For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns.  If the size check fails the functions return:
- * <pre>
- *     ARM_MATH_SIZE_MISMATCH
- * </pre>
- * Otherwise the functions return
- * <pre>
- *     ARM_MATH_SUCCESS
- * </pre>
- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the \#define
- * <pre>
- *     ARM_MATH_MATRIX_CHECK
- * </pre>
- * within the library project settings.  By default this macro is defined
- * and size checking is enabled.  By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster.  With size checking disabled the functions always
- * return <code>ARM_MATH_SUCCESS</code>.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- */
-/**
- * @defgroup groupSupport Support Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- */
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
-
-#if defined(ARM_MATH_CM7)
-  #include "core_cm7.h"
-#elif defined (ARM_MATH_CM4)
-  #include "core_cm4.h"
-#elif defined (ARM_MATH_CM3)
-  #include "core_cm3.h"
-#elif defined (ARM_MATH_CM0)
-  #include "core_cm0.h"
-#define ARM_MATH_CM0_FAMILY
-  #elif defined (ARM_MATH_CM0PLUS)
-#include "core_cm0plus.h"
-  #define ARM_MATH_CM0_FAMILY
-#else
-  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
-#endif
-
-#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
-#include "string.h"
-#include "math.h"
-#ifdef	__cplusplus
-extern "C"
-{
-#endif
-
-
-  /**
-   * @brief Macros required for reciprocal calculation in Normalized LMS
-   */
-
-#define DELTA_Q31 			(0x100)
-#define DELTA_Q15 			0x5
-#define INDEX_MASK 			0x0000003F
-#ifndef PI
-#define PI					3.14159265358979f
-#endif
-
-  /**
-   * @brief Macros required for SINE and COSINE Fast math approximations
-   */
-
-#define FAST_MATH_TABLE_SIZE  512
-#define FAST_MATH_Q31_SHIFT   (32 - 10)
-#define FAST_MATH_Q15_SHIFT   (16 - 10)
-#define CONTROLLER_Q31_SHIFT  (32 - 9)
-#define TABLE_SIZE  256
-#define TABLE_SPACING_Q31	   0x400000
-#define TABLE_SPACING_Q15	   0x80
-
-  /**
-   * @brief Macros required for SINE and COSINE Controller functions
-   */
-  /* 1.31(q31) Fixed value of 2/360 */
-  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING			0xB60B61
-
-  /**
-   * @brief Macro for Unaligned Support
-   */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-    #define ALIGN4
-#else
-  #if defined  (__GNUC__)
-    #define ALIGN4 __attribute__((aligned(4)))
-  #else
-    #define ALIGN4 __align(4)
-  #endif
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /**
-   * @brief Error status returned by some functions in the library.
-   */
-
-  typedef enum
-  {
-    ARM_MATH_SUCCESS = 0,                /**< No error */
-    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
-    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
-    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
-    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
-    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
-    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
-  } arm_status;
-
-  /**
-   * @brief 8-bit fractional data type in 1.7 format.
-   */
-  typedef int8_t q7_t;
-
-  /**
-   * @brief 16-bit fractional data type in 1.15 format.
-   */
-  typedef int16_t q15_t;
-
-  /**
-   * @brief 32-bit fractional data type in 1.31 format.
-   */
-  typedef int32_t q31_t;
-
-  /**
-   * @brief 64-bit fractional data type in 1.63 format.
-   */
-  typedef int64_t q63_t;
-
-  /**
-   * @brief 32-bit floating-point type definition.
-   */
-  typedef float float32_t;
-
-  /**
-   * @brief 64-bit floating-point type definition.
-   */
-  typedef double float64_t;
-
-  /**
-   * @brief definition to read/write two 16 bit values.
-   */
-#if defined __CC_ARM
-  #define __SIMD32_TYPE int32_t __packed
-  #define CMSIS_UNUSED __attribute__((unused))
-#elif defined __ICCARM__
-  #define __SIMD32_TYPE int32_t __packed
-  #define CMSIS_UNUSED
-#elif defined __GNUC__
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED __attribute__((unused))
-#elif defined __CSMC__			/* Cosmic */
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED
-#elif defined __TASKING__
-  #define __SIMD32_TYPE __unaligned int32_t
-  #define CMSIS_UNUSED
-#else
-  #error Unknown compiler
-#endif
-
-#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
-#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
-
-#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
-
-#define __SIMD64(addr)  (*(int64_t **) & (addr))
-
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
-  /**
-   * @brief definition to pack two 16 bit values.
-   */
-#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
-                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
-#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
-                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
-
-#endif
-
-
-   /**
-   * @brief definition to pack four 8 bit values.
-   */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
-                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
-							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
-							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
-#else
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
-                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
-							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
-							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
-
-#endif
-
-
-  /**
-   * @brief Clips Q63 to Q31 values.
-   */
-  static __INLINE q31_t clip_q63_to_q31(
-  q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
-  }
-
-  /**
-   * @brief Clips Q63 to Q15 values.
-   */
-  static __INLINE q15_t clip_q63_to_q15(
-  q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
-  }
-
-  /**
-   * @brief Clips Q31 to Q7 values.
-   */
-  static __INLINE q7_t clip_q31_to_q7(
-  q31_t x)
-  {
-    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
-      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
-  }
-
-  /**
-   * @brief Clips Q31 to Q15 values.
-   */
-  static __INLINE q15_t clip_q31_to_q15(
-  q31_t x)
-  {
-    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
-  }
-
-  /**
-   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
-   */
-
-  static __INLINE q63_t mult32x64(
-  q63_t x,
-  q31_t y)
-  {
-    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
-            (((q63_t) (x >> 32) * y)));
-  }
-
-
-//#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
-//#define __CLZ __clz
-//#endif
-
-//note: function can be removed when all toolchain support __CLZ for Cortex-M0
-#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )
-
-  static __INLINE uint32_t __CLZ(
-  q31_t data);
-
-
-  static __INLINE uint32_t __CLZ(
-  q31_t data)
-  {
-    uint32_t count = 0;
-    uint32_t mask = 0x80000000;
-
-    while((data & mask) == 0)
-    {
-      count += 1u;
-      mask = mask >> 1u;
-    }
-
-    return (count);
-
-  }
-
-#endif
-
-  /**
-   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
-   */
-
-  static __INLINE uint32_t arm_recip_q31(
-  q31_t in,
-  q31_t * dst,
-  q31_t * pRecipTable)
-  {
-
-    uint32_t out, tempVal;
-    uint32_t index, i;
-    uint32_t signBits;
-
-    if(in > 0)
-    {
-      signBits = __CLZ(in) - 1;
-    }
-    else
-    {
-      signBits = __CLZ(-in) - 1;
-    }
-
-    /* Convert input sample to 1.31 format */
-    in = in << signBits;
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t) (in >> 24u);
-    index = (index & INDEX_MASK);
-
-    /* 1.31 with exp 1 */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0u; i < 2u; i++)
-    {
-      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
-      tempVal = 0x7FFFFFFF - tempVal;
-      /*      1.31 with exp 1 */
-      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
-      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1u);
-
-  }
-
-  /**
-   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
-   */
-  static __INLINE uint32_t arm_recip_q15(
-  q15_t in,
-  q15_t * dst,
-  q15_t * pRecipTable)
-  {
-
-    uint32_t out = 0, tempVal = 0;
-    uint32_t index = 0, i = 0;
-    uint32_t signBits = 0;
-
-    if(in > 0)
-    {
-      signBits = __CLZ(in) - 17;
-    }
-    else
-    {
-      signBits = __CLZ(-in) - 17;
-    }
-
-    /* Convert input sample to 1.15 format */
-    in = in << signBits;
-
-    /* calculation of index for initial approximated Val */
-    index = in >> 8;
-    index = (index & INDEX_MASK);
-
-    /*      1.15 with exp 1  */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0; i < 2; i++)
-    {
-      tempVal = (q15_t) (((q31_t) in * out) >> 15);
-      tempVal = 0x7FFF - tempVal;
-      /*      1.15 with exp 1 */
-      out = (q15_t) (((q31_t) out * tempVal) >> 14);
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1);
-
-  }
-
-
-  /*
-   * @brief C custom defined intrinisic function for only M0 processors
-   */
-#if defined(ARM_MATH_CM0_FAMILY)
-
-  static __INLINE q31_t __SSAT(
-  q31_t x,
-  uint32_t y)
-  {
-    int32_t posMax, negMin;
-    uint32_t i;
-
-    posMax = 1;
-    for (i = 0; i < (y - 1); i++)
-    {
-      posMax = posMax * 2;
-    }
-
-    if(x > 0)
-    {
-      posMax = (posMax - 1);
-
-      if(x > posMax)
-      {
-        x = posMax;
-      }
-    }
-    else
-    {
-      negMin = -posMax;
-
-      if(x < negMin)
-      {
-        x = negMin;
-      }
-    }
-    return (x);
-
-
-  }
-
-#endif /* end of ARM_MATH_CM0_FAMILY */
-
-
-
-  /*
-   * @brief C custom defined intrinsic function for M3 and M0 processors
-   */
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
-
-  /*
-   * @brief C custom defined QADD8 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QADD8(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q7_t r, s, t, u;
-
-    r = (q7_t) x;
-    s = (q7_t) y;
-
-    r = __SSAT((q31_t) (r + s), 8);
-    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
-    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
-    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
-
-    sum =
-      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
-      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
-
-    return sum;
-
-  }
-
-  /*
-   * @brief C custom defined QSUB8 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSUB8(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s, t, u;
-
-    r = (q7_t) x;
-    s = (q7_t) y;
-
-    r = __SSAT((r - s), 8);
-    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
-    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
-    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
-
-    sum =
-      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
-                                                                0x000000FF);
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined QADD16 for M3 and M0 processors
-   */
-
-  /*
-   * @brief C custom defined QADD16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QADD16(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (q15_t) x;
-    s = (q15_t) y;
-
-    r = __SSAT(r + s, 16);
-    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-
-  }
-
-  /*
-   * @brief C custom defined SHADD16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHADD16(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (q15_t) x;
-    s = (q15_t) y;
-
-    r = ((r >> 1) + (s >> 1));
-    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-
-  }
-
-  /*
-   * @brief C custom defined QSUB16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSUB16(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (q15_t) x;
-    s = (q15_t) y;
-
-    r = __SSAT(r - s, 16);
-    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SHSUB16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHSUB16(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t diff;
-    q31_t r, s;
-
-    r = (q15_t) x;
-    s = (q15_t) y;
-
-    r = ((r >> 1) - (s >> 1));
-    s = (((x >> 17) - (y >> 17)) << 16);
-
-    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return diff;
-  }
-
-  /*
-   * @brief C custom defined QASX for M3 and M0 processors
-   */
-  static __INLINE q31_t __QASX(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum = 0;
-
-    sum =
-      ((sum +
-        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +
-      clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SHASX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHASX(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (q15_t) x;
-    s = (q15_t) y;
-
-    r = ((r >> 1) - (y >> 17));
-    s = (((x >> 17) + (s >> 1)) << 16);
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-  }
-
-
-  /*
-   * @brief C custom defined QSAX for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSAX(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum = 0;
-
-    sum =
-      ((sum +
-        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +
-      clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SHSAX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHSAX(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (q15_t) x;
-    s = (q15_t) y;
-
-    r = ((r >> 1) + (y >> 17));
-    s = (((x >> 17) - (s >> 1)) << 16);
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SMUSDX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUSDX(
-  q31_t x,
-  q31_t y)
-  {
-
-    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -
-                     ((q15_t) (x >> 16) * (q15_t) y)));
-  }
-
-  /*
-   * @brief C custom defined SMUADX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUADX(
-  q31_t x,
-  q31_t y)
-  {
-
-    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +
-                     ((q15_t) (x >> 16) * (q15_t) y)));
-  }
-
-  /*
-   * @brief C custom defined QADD for M3 and M0 processors
-   */
-  static __INLINE q31_t __QADD(
-  q31_t x,
-  q31_t y)
-  {
-    return clip_q63_to_q31((q63_t) x + y);
-  }
-
-  /*
-   * @brief C custom defined QSUB for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSUB(
-  q31_t x,
-  q31_t y)
-  {
-    return clip_q63_to_q31((q63_t) x - y);
-  }
-
-  /*
-   * @brief C custom defined SMLAD for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMLAD(
-  q31_t x,
-  q31_t y,
-  q31_t sum)
-  {
-
-    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
-            ((q15_t) x * (q15_t) y));
-  }
-
-  /*
-   * @brief C custom defined SMLADX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMLADX(
-  q31_t x,
-  q31_t y,
-  q31_t sum)
-  {
-
-    return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +
-            ((q15_t) x * (q15_t) (y >> 16)));
-  }
-
-  /*
-   * @brief C custom defined SMLSDX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMLSDX(
-  q31_t x,
-  q31_t y,
-  q31_t sum)
-  {
-
-    return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +
-            ((q15_t) x * (q15_t) (y >> 16)));
-  }
-
-  /*
-   * @brief C custom defined SMLALD for M3 and M0 processors
-   */
-  static __INLINE q63_t __SMLALD(
-  q31_t x,
-  q31_t y,
-  q63_t sum)
-  {
-
-    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
-            ((q15_t) x * (q15_t) y));
-  }
-
-  /*
-   * @brief C custom defined SMLALDX for M3 and M0 processors
-   */
-  static __INLINE q63_t __SMLALDX(
-  q31_t x,
-  q31_t y,
-  q63_t sum)
-  {
-
-    return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +
-      ((q15_t) x * (q15_t) (y >> 16));
-  }
-
-  /*
-   * @brief C custom defined SMUAD for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUAD(
-  q31_t x,
-  q31_t y)
-  {
-
-    return (((x >> 16) * (y >> 16)) +
-            (((x << 16) >> 16) * ((y << 16) >> 16)));
-  }
-
-  /*
-   * @brief C custom defined SMUSD for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUSD(
-  q31_t x,
-  q31_t y)
-  {
-
-    return (-((x >> 16) * (y >> 16)) +
-            (((x << 16) >> 16) * ((y << 16) >> 16)));
-  }
-
-
-  /*
-   * @brief C custom defined SXTB16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __SXTB16(
-  q31_t x)
-  {
-
-    return ((((x << 24) >> 24) & 0x0000FFFF) |
-            (((x << 8) >> 8) & 0xFFFF0000));
-  }
-
-
-#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-
-
-  /**
-   * @brief Instance structure for the Q7 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
-    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q7;
-
-  /**
-   * @brief Instance structure for the Q15 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q7 FIR filter.
-   * @param[in] *S points to an instance of the Q7 FIR filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_q7(
-  const arm_fir_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q7 FIR filter.
-   * @param[in,out] *S points to an instance of the Q7 FIR structure.
-   * @param[in] numTaps  Number of filter coefficients in the filter.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of samples that are processed.
-   * @return none
-   */
-  void arm_fir_init_q7(
-  arm_fir_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR filter.
-   * @param[in] *S points to an instance of the Q15 FIR structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q15 FIR filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_fast_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q15 FIR filter.
-   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
-   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of samples that are processed at a time.
-   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
-   * <code>numTaps</code> is not a supported value.
-   */
-
-  arm_status arm_fir_init_q15(
-  arm_fir_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR filter.
-   * @param[in] *S points to an instance of the Q31 FIR filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q31 FIR structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_fast_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 FIR filter.
-   * @param[in,out] *S points to an instance of the Q31 FIR structure.
-   * @param[in] 	numTaps  Number of filter coefficients in the filter.
-   * @param[in] 	*pCoeffs points to the filter coefficients.
-   * @param[in] 	*pState points to the state buffer.
-   * @param[in] 	blockSize number of samples that are processed at a time.
-   * @return 		none.
-   */
-  void arm_fir_init_q31(
-  arm_fir_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the floating-point FIR filter.
-   * @param[in] *S points to an instance of the floating-point FIR structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_f32(
-  const arm_fir_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point FIR filter.
-   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
-   * @param[in] 	numTaps  Number of filter coefficients in the filter.
-   * @param[in] 	*pCoeffs points to the filter coefficients.
-   * @param[in] 	*pState points to the state buffer.
-   * @param[in] 	blockSize number of samples that are processed at a time.
-   * @return    	none.
-   */
-  void arm_fir_init_f32(
-  arm_fir_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
-
-  } arm_biquad_casd_df1_inst_q15;
-
-
-  /**
-   * @brief Instance structure for the Q31 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
-
-  } arm_biquad_casd_df1_inst_q31;
-
-  /**
-   * @brief Instance structure for the floating-point Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-
-
-  } arm_biquad_casd_df1_inst_f32;
-
-
-
-  /**
-   * @brief Processing function for the Q15 Biquad cascade filter.
-   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q15 Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df1_init_q15(
-  arm_biquad_casd_df1_inst_q15 * S,
-  uint8_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int8_t postShift);
-
-
-  /**
-   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_fast_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 Biquad cascade filter
-   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  *pSrc      points to the block of input data.
-   * @param[out] *pDst      points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  *pSrc      points to the block of input data.
-   * @param[out] *pDst      points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_fast_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]     numStages      number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df1_init_q31(
-  arm_biquad_casd_df1_inst_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int8_t postShift);
-
-  /**
-   * @brief Processing function for the floating-point Biquad cascade filter.
-   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]  *pSrc      points to the block of input data.
-   * @param[out] *pDst      points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_f32(
-  const arm_biquad_casd_df1_inst_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df1_init_f32(
-  arm_biquad_casd_df1_inst_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief Instance structure for the floating-point matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float32_t *pData;     /**< points to the data of the matrix. */
-  } arm_matrix_instance_f32;
-
-
-  /**
-   * @brief Instance structure for the floating-point matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float64_t *pData;     /**< points to the data of the matrix. */
-  } arm_matrix_instance_f64;
-
-  /**
-   * @brief Instance structure for the Q15 matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q15_t *pData;         /**< points to the data of the matrix. */
-
-  } arm_matrix_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q31_t *pData;         /**< points to the data of the matrix. */
-
-  } arm_matrix_instance_q31;
-
-
-
-  /**
-   * @brief Floating-point matrix addition.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_add_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix addition.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_add_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix addition.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_add_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Floating-point, complex, matrix multiplication.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_cmplx_mult_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15, complex,  matrix multiplication.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_cmplx_mult_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pScratch);
-
-  /**
-   * @brief Q31, complex, matrix multiplication.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_cmplx_mult_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix transpose.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_trans_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix transpose.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_trans_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix transpose.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_trans_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix multiplication
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix multiplication
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @param[in]		 *pState points to the array for storing intermediate results
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState);
-
-  /**
-   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA  points to the first input matrix structure
-   * @param[in]       *pSrcB  points to the second input matrix structure
-   * @param[out]      *pDst   points to output matrix structure
-   * @param[in]		  *pState points to the array for storing intermediate results
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_fast_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState);
-
-  /**
-   * @brief Q31 matrix multiplication
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_fast_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix subtraction
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_sub_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix subtraction
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_sub_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix subtraction
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_sub_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Floating-point matrix scaling.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[in]  scale scale factor
-   * @param[out] *pDst points to the output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_scale_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  float32_t scale,
-  arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix scaling.
-   * @param[in]       *pSrc points to input matrix
-   * @param[in]       scaleFract fractional portion of the scale factor
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_scale_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  q15_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix scaling.
-   * @param[in]       *pSrc points to input matrix
-   * @param[in]       scaleFract fractional portion of the scale factor
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_scale_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  q31_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief  Q31 matrix initialization.
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows          number of rows in the matrix.
-   * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
-   * @return        none
-   */
-
-  void arm_mat_init_q31(
-  arm_matrix_instance_q31 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q31_t * pData);
-
-  /**
-   * @brief  Q15 matrix initialization.
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows          number of rows in the matrix.
-   * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
-   * @return        none
-   */
-
-  void arm_mat_init_q15(
-  arm_matrix_instance_q15 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q15_t * pData);
-
-  /**
-   * @brief  Floating-point matrix initialization.
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows          number of rows in the matrix.
-   * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
-   * @return        none
-   */
-
-  void arm_mat_init_f32(
-  arm_matrix_instance_f32 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  float32_t * pData);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 PID Control.
-   */
-  typedef struct
-  {
-    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
-#ifdef ARM_MATH_CM0_FAMILY
-    q15_t A1;
-    q15_t A2;
-#else
-    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
-#endif
-    q15_t state[3];       /**< The state array of length 3. */
-    q15_t Kp;           /**< The proportional gain. */
-    q15_t Ki;           /**< The integral gain. */
-    q15_t Kd;           /**< The derivative gain. */
-  } arm_pid_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 PID Control.
-   */
-  typedef struct
-  {
-    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
-    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
-    q31_t A2;            /**< The derived gain, A2 = Kd . */
-    q31_t state[3];      /**< The state array of length 3. */
-    q31_t Kp;            /**< The proportional gain. */
-    q31_t Ki;            /**< The integral gain. */
-    q31_t Kd;            /**< The derivative gain. */
-
-  } arm_pid_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point PID Control.
-   */
-  typedef struct
-  {
-    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
-    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
-    float32_t A2;          /**< The derived gain, A2 = Kd . */
-    float32_t state[3];    /**< The state array of length 3. */
-    float32_t Kp;               /**< The proportional gain. */
-    float32_t Ki;               /**< The integral gain. */
-    float32_t Kd;               /**< The derivative gain. */
-  } arm_pid_instance_f32;
-
-
-
-  /**
-   * @brief  Initialization function for the floating-point PID Control.
-   * @param[in,out] *S      points to an instance of the PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   * @return none.
-   */
-  void arm_pid_init_f32(
-  arm_pid_instance_f32 * S,
-  int32_t resetStateFlag);
-
-  /**
-   * @brief  Reset function for the floating-point PID Control.
-   * @param[in,out] *S is an instance of the floating-point PID Control structure
-   * @return none
-   */
-  void arm_pid_reset_f32(
-  arm_pid_instance_f32 * S);
-
-
-  /**
-   * @brief  Initialization function for the Q31 PID Control.
-   * @param[in,out] *S points to an instance of the Q15 PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   * @return none.
-   */
-  void arm_pid_init_q31(
-  arm_pid_instance_q31 * S,
-  int32_t resetStateFlag);
-
-
-  /**
-   * @brief  Reset function for the Q31 PID Control.
-   * @param[in,out] *S points to an instance of the Q31 PID Control structure
-   * @return none
-   */
-
-  void arm_pid_reset_q31(
-  arm_pid_instance_q31 * S);
-
-  /**
-   * @brief  Initialization function for the Q15 PID Control.
-   * @param[in,out] *S points to an instance of the Q15 PID structure.
-   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   * @return none.
-   */
-  void arm_pid_init_q15(
-  arm_pid_instance_q15 * S,
-  int32_t resetStateFlag);
-
-  /**
-   * @brief  Reset function for the Q15 PID Control.
-   * @param[in,out] *S points to an instance of the q15 PID Control structure
-   * @return none
-   */
-  void arm_pid_reset_q15(
-  arm_pid_instance_q15 * S);
-
-
-  /**
-   * @brief Instance structure for the floating-point Linear Interpolate function.
-   */
-  typedef struct
-  {
-    uint32_t nValues;           /**< nValues */
-    float32_t x1;               /**< x1 */
-    float32_t xSpacing;         /**< xSpacing */
-    float32_t *pYData;          /**< pointer to the table of Y values */
-  } arm_linear_interp_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    float32_t *pData;   /**< points to the data table. */
-  } arm_bilinear_interp_instance_f32;
-
-   /**
-   * @brief Instance structure for the Q31 bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q31_t *pData;       /**< points to the data table. */
-  } arm_bilinear_interp_instance_q31;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q15_t *pData;       /**< points to the data table. */
-  } arm_bilinear_interp_instance_q15;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q7_t *pData;                /**< points to the data table. */
-  } arm_bilinear_interp_instance_q7;
-
-
-  /**
-   * @brief Q7 vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst  points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst  points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Floating-point vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-
-
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix2_instance_q15;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_q15(
-  arm_cfft_radix2_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_q15(
-  const arm_cfft_radix2_instance_q15 * S,
-  q15_t * pSrc);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q15;
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_q15(
-  arm_cfft_radix4_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix4_q15(
-  const arm_cfft_radix4_instance_q15 * S,
-  q15_t * pSrc);
-
-  /**
-   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix2_instance_q31;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_q31(
-  arm_cfft_radix2_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_q31(
-  const arm_cfft_radix2_instance_q31 * S,
-  q31_t * pSrc);
-
-  /**
-   * @brief Instance structure for the Q31 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q31;
-
-/* Deprecated */
-  void arm_cfft_radix4_q31(
-  const arm_cfft_radix4_instance_q31 * S,
-  q31_t * pSrc);
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_q31(
-  arm_cfft_radix4_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
-  } arm_cfft_radix2_instance_f32;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_f32(
-  arm_cfft_radix2_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_f32(
-  const arm_cfft_radix2_instance_f32 * S,
-  float32_t * pSrc);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
-  } arm_cfft_radix4_instance_f32;
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_f32(
-  arm_cfft_radix4_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix4_f32(
-  const arm_cfft_radix4_instance_f32 * S,
-  float32_t * pSrc);
-
-  /**
-   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_q15;
-
-void arm_cfft_q15( 
-    const arm_cfft_instance_q15 * S, 
-    q15_t * p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);  
-
-  /**
-   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_q31;
-
-void arm_cfft_q31( 
-    const arm_cfft_instance_q31 * S, 
-    q31_t * p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);  
-  
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_f32;
-
-  void arm_cfft_f32(
-  const arm_cfft_instance_f32 * S,
-  float32_t * p1,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the Q15 RFFT/RIFFT function.
-   */
-
-  typedef struct
-  {
-    uint32_t fftLenReal;                      /**< length of the real FFT. */
-    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
-    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
-    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q15;
-
-  arm_status arm_rfft_init_q15(
-  arm_rfft_instance_q15 * S,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_q15(
-  const arm_rfft_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst);
-
-  /**
-   * @brief Instance structure for the Q31 RFFT/RIFFT function.
-   */
-
-  typedef struct
-  {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
-    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
-    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q31;
-
-  arm_status arm_rfft_init_q31(
-  arm_rfft_instance_q31 * S,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_q31(
-  const arm_rfft_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point RFFT/RIFFT function.
-   */
-
-  typedef struct
-  {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
-    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
-  } arm_rfft_instance_f32;
-
-  arm_status arm_rfft_init_f32(
-  arm_rfft_instance_f32 * S,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_f32(
-  const arm_rfft_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point RFFT/RIFFT function.
-   */
-
-typedef struct
-  {
-    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
-    uint16_t fftLenRFFT;                        /**< length of the real sequence */
-	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
-  } arm_rfft_fast_instance_f32 ;
-
-arm_status arm_rfft_fast_init_f32 (
-	arm_rfft_fast_instance_f32 * S,
-	uint16_t fftLen);
-
-void arm_rfft_fast_f32(
-  arm_rfft_fast_instance_f32 * S,
-  float32_t * p, float32_t * pOut,
-  uint8_t ifftFlag);
-
-  /**
-   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
-   */
-
-  typedef struct
-  {
-    uint16_t N;                         /**< length of the DCT4. */
-    uint16_t Nby2;                      /**< half of the length of the DCT4. */
-    float32_t normalize;                /**< normalizing factor. */
-    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
-    float32_t *pCosFactor;              /**< points to the cosFactor table. */
-    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_f32;
-
-  /**
-   * @brief  Initialization function for the floating-point DCT4/IDCT4.
-   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
-   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
-   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
-   */
-
-  arm_status arm_dct4_init_f32(
-  arm_dct4_instance_f32 * S,
-  arm_rfft_instance_f32 * S_RFFT,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  float32_t normalize);
-
-  /**
-   * @brief Processing function for the floating-point DCT4/IDCT4.
-   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
-   * @param[in]       *pState        points to state buffer.
-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
-   * @return none.
-   */
-
-  void arm_dct4_f32(
-  const arm_dct4_instance_f32 * S,
-  float32_t * pState,
-  float32_t * pInlineBuffer);
-
-  /**
-   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
-   */
-
-  typedef struct
-  {
-    uint16_t N;                         /**< length of the DCT4. */
-    uint16_t Nby2;                      /**< half of the length of the DCT4. */
-    q31_t normalize;                    /**< normalizing factor. */
-    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
-    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
-    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q31;
-
-  /**
-   * @brief  Initialization function for the Q31 DCT4/IDCT4.
-   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
-   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
-   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-
-  arm_status arm_dct4_init_q31(
-  arm_dct4_instance_q31 * S,
-  arm_rfft_instance_q31 * S_RFFT,
-  arm_cfft_radix4_instance_q31 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q31_t normalize);
-
-  /**
-   * @brief Processing function for the Q31 DCT4/IDCT4.
-   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
-   * @param[in]       *pState        points to state buffer.
-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
-   * @return none.
-   */
-
-  void arm_dct4_q31(
-  const arm_dct4_instance_q31 * S,
-  q31_t * pState,
-  q31_t * pInlineBuffer);
-
-  /**
-   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
-   */
-
-  typedef struct
-  {
-    uint16_t N;                         /**< length of the DCT4. */
-    uint16_t Nby2;                      /**< half of the length of the DCT4. */
-    q15_t normalize;                    /**< normalizing factor. */
-    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
-    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
-    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q15;
-
-  /**
-   * @brief  Initialization function for the Q15 DCT4/IDCT4.
-   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
-   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
-   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-
-  arm_status arm_dct4_init_q15(
-  arm_dct4_instance_q15 * S,
-  arm_rfft_instance_q15 * S_RFFT,
-  arm_cfft_radix4_instance_q15 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q15_t normalize);
-
-  /**
-   * @brief Processing function for the Q15 DCT4/IDCT4.
-   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
-   * @param[in]       *pState        points to state buffer.
-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
-   * @return none.
-   */
-
-  void arm_dct4_q15(
-  const arm_dct4_instance_q15 * S,
-  q15_t * pState,
-  q15_t * pInlineBuffer);
-
-  /**
-   * @brief Floating-point vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q7 vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Floating-point vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q7 vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a floating-point vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scale scale factor to be applied
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_f32(
-  float32_t * pSrc,
-  float32_t scale,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a Q7 vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scaleFract fractional portion of the scale value
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_q7(
-  q7_t * pSrc,
-  q7_t scaleFract,
-  int8_t shift,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a Q15 vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scaleFract fractional portion of the scale value
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_q15(
-  q15_t * pSrc,
-  q15_t scaleFract,
-  int8_t shift,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a Q31 vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scaleFract fractional portion of the scale value
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_q31(
-  q31_t * pSrc,
-  q31_t scaleFract,
-  int8_t shift,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q7 vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Floating-point vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Dot product of floating-point vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  uint32_t blockSize,
-  float32_t * result);
-
-  /**
-   * @brief Dot product of Q7 vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  uint32_t blockSize,
-  q31_t * result);
-
-  /**
-   * @brief Dot product of Q15 vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  uint32_t blockSize,
-  q63_t * result);
-
-  /**
-   * @brief Dot product of Q31 vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  uint32_t blockSize,
-  q63_t * result);
-
-  /**
-   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_shift_q7(
-  q7_t * pSrc,
-  int8_t shiftBits,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_shift_q15(
-  q15_t * pSrc,
-  int8_t shiftBits,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_shift_q31(
-  q31_t * pSrc,
-  int8_t shiftBits,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a floating-point vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_f32(
-  float32_t * pSrc,
-  float32_t offset,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a Q7 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_q7(
-  q7_t * pSrc,
-  q7_t offset,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a Q15 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_q15(
-  q15_t * pSrc,
-  q15_t offset,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a Q31 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_q31(
-  q31_t * pSrc,
-  q31_t offset,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a floating-point vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a Q7 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a Q15 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a Q31 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-  /**
-   * @brief  Copies the elements of a floating-point vector.
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Copies the elements of a Q7 vector.
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Copies the elements of a Q15 vector.
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Copies the elements of a Q31 vector.
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-  /**
-   * @brief  Fills a constant value into a floating-point vector.
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_f32(
-  float32_t value,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Fills a constant value into a Q7 vector.
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_q7(
-  q7_t value,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Fills a constant value into a Q15 vector.
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_q15(
-  q15_t value,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Fills a constant value into a Q31 vector.
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_q31(
-  q31_t value,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-/**
- * @brief Convolution of floating-point sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
- * @return none.
- */
-
-  void arm_conv_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q15 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
-   * @return none.
-   */
-
-
-  void arm_conv_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
- * @return none.
- */
-
-  void arm_conv_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_fast_q15(
-			  q15_t * pSrcA,
-			 uint32_t srcALen,
-			  q15_t * pSrcB,
-			 uint32_t srcBLen,
-			 q15_t * pDst);
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
-   * @return none.
-   */
-
-  void arm_conv_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-
-  /**
-   * @brief Convolution of Q31 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-  /**
-   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-    /**
-   * @brief Convolution of Q7 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   * @return none.
-   */
-
-  void arm_conv_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-
-  /**
-   * @brief Convolution of Q7 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst);
-
-
-  /**
-   * @brief Partial convolution of floating-point sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-    /**
-   * @brief Partial convolution of Q15 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**
-   * @brief Partial convolution of Q15 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_fast_q15(
-				        q15_t * pSrcA,
-				       uint32_t srcALen,
-				        q15_t * pSrcB,
-				       uint32_t srcBLen,
-				       q15_t * pDst,
-				       uint32_t firstIndex,
-				       uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q7 sequences
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**
-   * @brief Partial convolution of Q7 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR decimator.
-   */
-
-  typedef struct
-  {
-    uint8_t M;                      /**< decimation factor. */
-    uint16_t numTaps;               /**< number of coefficients in the filter. */
-    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
-    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR decimator.
-   */
-
-  typedef struct
-  {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
-    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-
-  } arm_fir_decimate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR decimator.
-   */
-
-  typedef struct
-  {
-    uint8_t M;                          /**< decimation factor. */
-    uint16_t numTaps;                   /**< number of coefficients in the filter. */
-    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-
-  } arm_fir_decimate_instance_f32;
-
-
-
-  /**
-   * @brief Processing function for the floating-point FIR decimator.
-   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_f32(
-  const arm_fir_decimate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point FIR decimator.
-   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
-   * @param[in] numTaps  number of coefficients in the filter.
-   * @param[in] M  decimation factor.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-
-  arm_status arm_fir_decimate_init_f32(
-  arm_fir_decimate_instance_f32 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator.
-   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_fast_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR decimator.
-   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
-   * @param[in] numTaps  number of coefficients in the filter.
-   * @param[in] M  decimation factor.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-
-  arm_status arm_fir_decimate_init_q15(
-  arm_fir_decimate_instance_q15 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator.
-   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_q31(
-  const arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_fast_q31(
-  arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR decimator.
-   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
-   * @param[in] numTaps  number of coefficients in the filter.
-   * @param[in] M  decimation factor.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-
-  arm_status arm_fir_decimate_init_q31(
-  arm_fir_decimate_instance_q31 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR interpolator.
-   */
-
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR interpolator.
-   */
-
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR interpolator.
-   */
-
-  typedef struct
-  {
-    uint8_t L;                     /**< upsample factor. */
-    uint16_t phaseLength;          /**< length of each polyphase filter component. */
-    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
-    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
-  } arm_fir_interpolate_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q15 FIR interpolator.
-   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
-   * @param[in] *pSrc     points to the block of input data.
-   * @param[out] *pDst    points to the block of output data.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_interpolate_q15(
-  const arm_fir_interpolate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR interpolator.
-   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]     L         upsample factor.
-   * @param[in]     numTaps   number of filter coefficients in the filter.
-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
-   * @param[in]     *pState   points to the state buffer.
-   * @param[in]     blockSize number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-
-  arm_status arm_fir_interpolate_init_q15(
-  arm_fir_interpolate_instance_q15 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR interpolator.
-   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
-   * @param[in] *pSrc     points to the block of input data.
-   * @param[out] *pDst    points to the block of output data.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_interpolate_q31(
-  const arm_fir_interpolate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 FIR interpolator.
-   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
-   * @param[in]     L         upsample factor.
-   * @param[in]     numTaps   number of filter coefficients in the filter.
-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
-   * @param[in]     *pState   points to the state buffer.
-   * @param[in]     blockSize number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-
-  arm_status arm_fir_interpolate_init_q31(
-  arm_fir_interpolate_instance_q31 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR interpolator.
-   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
-   * @param[in] *pSrc     points to the block of input data.
-   * @param[out] *pDst    points to the block of output data.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_interpolate_f32(
-  const arm_fir_interpolate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point FIR interpolator.
-   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
-   * @param[in]     L         upsample factor.
-   * @param[in]     numTaps   number of filter coefficients in the filter.
-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
-   * @param[in]     *pState   points to the state buffer.
-   * @param[in]     blockSize number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-
-  arm_status arm_fir_interpolate_init_f32(
-  arm_fir_interpolate_instance_f32 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
-   */
-
-  typedef struct
-  {
-    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
-
-  } arm_biquad_cas_df1_32x64_ins_q31;
-
-
-  /**
-   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_biquad_cas_df1_32x64_q31(
-  const arm_biquad_cas_df1_32x64_ins_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
-   * @return        none
-   */
-
-  void arm_biquad_cas_df1_32x64_init_q31(
-  arm_biquad_cas_df1_32x64_ins_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q63_t * pState,
-  uint8_t postShift);
-
-
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_df2T_instance_f32;
-
-
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_stereo_df2T_instance_f32;
-
-
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_df2T_instance_f64;
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in]  *S        points to an instance of the filter data structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_biquad_cascade_df2T_f32(
-  const arm_biquad_cascade_df2T_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
-   * @param[in]  *S        points to an instance of the filter data structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_biquad_cascade_stereo_df2T_f32(
-  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in]  *S        points to an instance of the filter data structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_biquad_cascade_df2T_f64(
-  const arm_biquad_cascade_df2T_instance_f64 * S,
-  float64_t * pSrc,
-  float64_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the filter data structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df2T_init_f32(
-  arm_biquad_cascade_df2T_instance_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the filter data structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @return        none
-   */
-
-  void arm_biquad_cascade_stereo_df2T_init_f32(
-  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the filter data structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df2T_init_f64(
-  arm_biquad_cascade_df2T_instance_f64 * S,
-  uint8_t numStages,
-  float64_t * pCoeffs,
-  float64_t * pState);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR lattice filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numStages;                          /**< number of filter stages. */
-    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
-    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR lattice filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numStages;                          /**< number of filter stages. */
-    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
-    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR lattice filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of filter stages. */
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
-    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_f32;
-
-  /**
-   * @brief Initialization function for the Q15 FIR lattice filter.
-   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
-   * @param[in] *pState points to the state buffer.  The array is of length numStages.
-   * @return none.
-   */
-
-  void arm_fir_lattice_init_q15(
-  arm_fir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR lattice filter.
-   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_lattice_q15(
-  const arm_fir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for the Q31 FIR lattice filter.
-   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
-   * @param[in] *pState points to the state buffer.   The array is of length numStages.
-   * @return none.
-   */
-
-  void arm_fir_lattice_init_q31(
-  arm_fir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR lattice filter.
-   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_fir_lattice_q31(
-  const arm_fir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] *S points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages  number of filter stages.
- * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
- * @param[in] *pState points to the state buffer.  The array is of length numStages.
- * @return none.
- */
-
-  void arm_fir_lattice_init_f32(
-  arm_fir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-  /**
-   * @brief Processing function for the floating-point FIR lattice filter.
-   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_fir_lattice_f32(
-  const arm_fir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the Q15 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                         /**< number of stages in the filter. */
-    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
-    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                         /**< number of stages in the filter. */
-    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
-    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                         /**< number of stages in the filter. */
-    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
-    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
-    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_f32;
-
-  /**
-   * @brief Processing function for the floating-point IIR lattice filter.
-   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_f32(
-  const arm_iir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for the floating-point IIR lattice filter.
-   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
-   * @param[in] numStages number of stages in the filter.
-   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_init_f32(
-  arm_iir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pkCoeffs,
-  float32_t * pvCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 IIR lattice filter.
-   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_q31(
-  const arm_iir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the Q31 IIR lattice filter.
-   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
-   * @param[in] numStages number of stages in the filter.
-   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_init_q31(
-  arm_iir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pkCoeffs,
-  q31_t * pvCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 IIR lattice filter.
-   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_q15(
-  const arm_iir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages  number of stages in the filter.
- * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
- * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
- * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- */
-
-  void arm_iir_lattice_init_q15(
-  arm_iir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pkCoeffs,
-  q15_t * pvCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the floating-point LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;        /**< step size that controls filter coefficient updates. */
-  } arm_lms_instance_f32;
-
-  /**
-   * @brief Processing function for floating-point LMS filter.
-   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[in]  *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_lms_f32(
-  const arm_lms_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for floating-point LMS filter.
-   * @param[in] *S points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to the coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_init_f32(
-  arm_lms_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the Q15 LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-  } arm_lms_instance_q15;
-
-
-  /**
-   * @brief Initialization function for the Q15 LMS filter.
-   * @param[in] *S points to an instance of the Q15 LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to the coefficient buffer.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return    none.
-   */
-
-  void arm_lms_init_q15(
-  arm_lms_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint32_t postShift);
-
-  /**
-   * @brief Processing function for Q15 LMS filter.
-   * @param[in] *S points to an instance of the Q15 LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_q15(
-  const arm_lms_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-
-  } arm_lms_instance_q31;
-
-  /**
-   * @brief Processing function for Q31 LMS filter.
-   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[in]  *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_lms_q31(
-  const arm_lms_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for Q31 LMS filter.
-   * @param[in] *S points to an instance of the Q31 LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return none.
-   */
-
-  void arm_lms_init_q31(
-  arm_lms_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint32_t postShift);
-
-  /**
-   * @brief Instance structure for the floating-point normalized LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;        /**< step size that control filter coefficient updates. */
-    float32_t energy;    /**< saves previous frame energy. */
-    float32_t x0;        /**< saves previous input sample. */
-  } arm_lms_norm_instance_f32;
-
-  /**
-   * @brief Processing function for floating-point normalized LMS filter.
-   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_f32(
-  arm_lms_norm_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for floating-point normalized LMS filter.
-   * @param[in] *S points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_init_f32(
-  arm_lms_norm_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 normalized LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;             /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;    /**< bit shift applied to coefficients. */
-    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
-    q31_t energy;         /**< saves previous frame energy. */
-    q31_t x0;             /**< saves previous input sample. */
-  } arm_lms_norm_instance_q31;
-
-  /**
-   * @brief Processing function for Q31 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_q31(
-  arm_lms_norm_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for Q31 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return none.
-   */
-
-  void arm_lms_norm_init_q31(
-  arm_lms_norm_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint8_t postShift);
-
-  /**
-   * @brief Instance structure for the Q15 normalized LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< Number of coefficients in the filter. */
-    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;            /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;   /**< bit shift applied to coefficients. */
-    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
-    q15_t energy;        /**< saves previous frame energy. */
-    q15_t x0;            /**< saves previous input sample. */
-  } arm_lms_norm_instance_q15;
-
-  /**
-   * @brief Processing function for Q15 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_q15(
-  arm_lms_norm_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q15 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return none.
-   */
-
-  void arm_lms_norm_init_q15(
-  arm_lms_norm_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint8_t postShift);
-
-  /**
-   * @brief Correlation of floating-point sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst);
-
-
-   /**
-   * @brief Correlation of Q15 sequences
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @return none.
-   */
-  void arm_correlate_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch);
-
-
-  /**
-   * @brief Correlation of Q15 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-  /**
-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_fast_q15(
-			       q15_t * pSrcA,
-			      uint32_t srcALen,
-			       q15_t * pSrcB,
-			      uint32_t srcBLen,
-			      q15_t * pDst);
-
-
-
-  /**
-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @return none.
-   */
-
-  void arm_correlate_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch);
-
-  /**
-   * @brief Correlation of Q31 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-  /**
-   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-
- /**
-   * @brief Correlation of Q7 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   * @return none.
-   */
-
-  void arm_correlate_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Correlation of Q7 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst);
-
-
-  /**
-   * @brief Instance structure for the floating-point sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_f32;
-
-  /**
-   * @brief Instance structure for the Q31 sparse FIR filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q31;
-
-  /**
-   * @brief Instance structure for the Q15 sparse FIR filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q7 sparse FIR filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q7;
-
-  /**
-   * @brief Processing function for the floating-point sparse FIR filter.
-   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
-   * @param[in]  *pSrc       points to the block of input data.
-   * @param[out] *pDst       points to the block of output data
-   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_f32(
-  arm_fir_sparse_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  float32_t * pScratchIn,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_f32(
-  arm_fir_sparse_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 sparse FIR filter.
-   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
-   * @param[in]  *pSrc       points to the block of input data.
-   * @param[out] *pDst       points to the block of output data
-   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_q31(
-  arm_fir_sparse_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  q31_t * pScratchIn,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_q31(
-  arm_fir_sparse_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q15 sparse FIR filter.
-   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
-   * @param[in]  *pSrc        points to the block of input data.
-   * @param[out] *pDst        points to the block of output data
-   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_q15(
-  arm_fir_sparse_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  q15_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_q15(
-  arm_fir_sparse_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q7 sparse FIR filter.
-   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
-   * @param[in]  *pSrc        points to the block of input data.
-   * @param[out] *pDst        points to the block of output data
-   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_q7(
-  arm_fir_sparse_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  q7_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q7 sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_q7(
-  arm_fir_sparse_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /*
-   * @brief  Floating-point sin_cos function.
-   * @param[in]  theta    input value in degrees
-   * @param[out] *pSinVal points to the processed sine output.
-   * @param[out] *pCosVal points to the processed cos output.
-   * @return none.
-   */
-
-  void arm_sin_cos_f32(
-  float32_t theta,
-  float32_t * pSinVal,
-  float32_t * pCcosVal);
-
-  /*
-   * @brief  Q31 sin_cos function.
-   * @param[in]  theta    scaled input value in degrees
-   * @param[out] *pSinVal points to the processed sine output.
-   * @param[out] *pCosVal points to the processed cosine output.
-   * @return none.
-   */
-
-  void arm_sin_cos_q31(
-  q31_t theta,
-  q31_t * pSinVal,
-  q31_t * pCosVal);
-
-
-  /**
-   * @brief  Floating-point complex conjugate.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_conj_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex conjugate.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_conj_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex conjugate.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_conj_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
-
-  /**
-   * @brief  Floating-point complex magnitude squared
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_squared_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex magnitude squared
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_squared_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex magnitude squared
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_squared_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
- /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup PID PID Motor Control
-   *
-   * A Proportional Integral Derivative (PID) controller is a generic feedback control
-   * loop mechanism widely used in industrial control systems.
-   * A PID controller is the most commonly used type of feedback controller.
-   *
-   * This set of functions implements (PID) controllers
-   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
-   * of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
-   * is the input sample value. The functions return the output value.
-   *
-   * \par Algorithm:
-   * <pre>
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd  </pre>
-   *
-   * \par
-   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
-   *
-   * \par
-   * \image html PID.gif "Proportional Integral Derivative Controller"
-   *
-   * \par
-   * The PID controller calculates an "error" value as the difference between
-   * the measured output and the reference input.
-   * The controller attempts to minimize the error by adjusting the process control inputs.
-   * The proportional value determines the reaction to the current error,
-   * the integral value determines the reaction based on the sum of recent errors,
-   * and the derivative value determines the reaction based on the rate at which the error has been changing.
-   *
-   * \par Instance Structure
-   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
-   * A separate instance structure must be defined for each PID Controller.
-   * There are separate instance structure declarations for each of the 3 supported data types.
-   *
-   * \par Reset Functions
-   * There is also an associated reset function for each data type which clears the state array.
-   *
-   * \par Initialization Functions
-   * There is also an associated initialization function for each data type.
-   * The initialization function performs the following operations:
-   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
-   * - Zeros out the values in the state buffer.
-   *
-   * \par
-   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
-   *
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the fixed-point versions of the PID Controller functions.
-   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup PID
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point PID Control.
-   * @param[in,out] *S is an instance of the floating-point PID Control structure
-   * @param[in] in input sample to process
-   * @return out processed output sample.
-   */
-
-
-  static __INLINE float32_t arm_pid_f32(
-  arm_pid_instance_f32 * S,
-  float32_t in)
-  {
-    float32_t out;
-
-    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
-    out = (S->A0 * in) +
-      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @brief  Process function for the Q31 PID Control.
-   * @param[in,out] *S points to an instance of the Q31 PID Control structure
-   * @param[in] in input sample to process
-   * @return out processed output sample.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 64-bit accumulator.
-   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
-   * Thus, if the accumulator result overflows it wraps around rather than clip.
-   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
-   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
-   */
-
-  static __INLINE q31_t arm_pid_q31(
-  arm_pid_instance_q31 * S,
-  q31_t in)
-  {
-    q63_t acc;
-    q31_t out;
-
-    /* acc = A0 * x[n]  */
-    acc = (q63_t) S->A0 * in;
-
-    /* acc += A1 * x[n-1] */
-    acc += (q63_t) S->A1 * S->state[0];
-
-    /* acc += A2 * x[n-2]  */
-    acc += (q63_t) S->A2 * S->state[1];
-
-    /* convert output to 1.31 format to add y[n-1] */
-    out = (q31_t) (acc >> 31u);
-
-    /* out += y[n-1] */
-    out += S->state[2];
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @brief  Process function for the Q15 PID Control.
-   * @param[in,out] *S points to an instance of the Q15 PID Control structure
-   * @param[in] in input sample to process
-   * @return out processed output sample.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using a 64-bit internal accumulator.
-   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
-   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
-   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
-   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
-   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
-   */
-
-  static __INLINE q15_t arm_pid_q15(
-  arm_pid_instance_q15 * S,
-  q15_t in)
-  {
-    q63_t acc;
-    q15_t out;
-
-#ifndef ARM_MATH_CM0_FAMILY
-    __SIMD32_TYPE *vstate;
-
-    /* Implementation of PID controller */
-
-    /* acc = A0 * x[n]  */
-    acc = (q31_t) __SMUAD(S->A0, in);
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    vstate = __SIMD32_CONST(S->state);
-    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
-
-#else
-    /* acc = A0 * x[n]  */
-    acc = ((q31_t) S->A0) * in;
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    acc += (q31_t) S->A1 * S->state[0];
-    acc += (q31_t) S->A2 * S->state[1];
-
-#endif
-
-    /* acc += y[n-1] */
-    acc += (q31_t) S->state[2] << 15;
-
-    /* saturate the output */
-    out = (q15_t) (__SSAT((acc >> 15), 16));
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @} end of PID group
-   */
-
-
-  /**
-   * @brief Floating-point matrix inverse.
-   * @param[in]  *src points to the instance of the input floating-point matrix structure.
-   * @param[out] *dst points to the instance of the output floating-point matrix structure.
-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
-   */
-
-  arm_status arm_mat_inverse_f32(
-  const arm_matrix_instance_f32 * src,
-  arm_matrix_instance_f32 * dst);
-
-
-  /**
-   * @brief Floating-point matrix inverse.
-   * @param[in]  *src points to the instance of the input floating-point matrix structure.
-   * @param[out] *dst points to the instance of the output floating-point matrix structure.
-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
-   */
-
-  arm_status arm_mat_inverse_f64(
-  const arm_matrix_instance_f64 * src,
-  arm_matrix_instance_f64 * dst);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-
-  /**
-   * @defgroup clarke Vector Clarke Transform
-   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
-   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
-   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
-   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
-   * \image html clarke.gif Stator current space vector and its components in (a,b).
-   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
-   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeFormula.gif
-   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
-   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup clarke
-   * @{
-   */
-
-  /**
-   *
-   * @brief  Floating-point Clarke transform
-   * @param[in]       Ia       input three-phase coordinate <code>a</code>
-   * @param[in]       Ib       input three-phase coordinate <code>b</code>
-   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
-   * @return none.
-   */
-
-  static __INLINE void arm_clarke_f32(
-  float32_t Ia,
-  float32_t Ib,
-  float32_t * pIalpha,
-  float32_t * pIbeta)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
-    *pIbeta =
-      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
-
-  }
-
-  /**
-   * @brief  Clarke transform for Q31 version
-   * @param[in]       Ia       input three-phase coordinate <code>a</code>
-   * @param[in]       Ib       input three-phase coordinate <code>b</code>
-   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-
-  static __INLINE void arm_clarke_q31(
-  q31_t Ia,
-  q31_t Ib,
-  q31_t * pIalpha,
-  q31_t * pIbeta)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
-    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
-    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
-    /* pIbeta is calculated by adding the intermediate products */
-    *pIbeta = __QADD(product1, product2);
-  }
-
-  /**
-   * @} end of clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q31 vector.
-   * @param[in]  *pSrc     input pointer
-   * @param[out]  *pDst    output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_q7_to_q31(
-  q7_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_clarke Vector Inverse Clarke Transform
-   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeInvFormula.gif
-   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
-   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_clarke
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Clarke transform
-   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
-   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
-   * @return none.
-   */
-
-
-  static __INLINE void arm_inv_clarke_f32(
-  float32_t Ialpha,
-  float32_t Ibeta,
-  float32_t * pIa,
-  float32_t * pIb)
-  {
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
-    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
-
-  }
-
-  /**
-   * @brief  Inverse Clarke transform for Q31 version
-   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
-   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the subtraction, hence there is no risk of overflow.
-   */
-
-  static __INLINE void arm_inv_clarke_q31(
-  q31_t Ialpha,
-  q31_t Ibeta,
-  q31_t * pIa,
-  q31_t * pIb)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
-    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
-    /* pIb is calculated by subtracting the products */
-    *pIb = __QSUB(product2, product1);
-
-  }
-
-  /**
-   * @} end of inv_clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q15 vector.
-   * @param[in]  *pSrc     input pointer
-   * @param[out] *pDst     output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_q7_to_q15(
-  q7_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup park Vector Park Transform
-   *
-   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
-   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
-   * from the stationary to the moving reference frame and control the spatial relationship between
-   * the stator vector current and rotor flux vector.
-   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
-   * current vector and the relationship from the two reference frames:
-   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkFormula.gif
-   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
-   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup park
-   * @{
-   */
-
-  /**
-   * @brief Floating-point Park transform
-   * @param[in]       Ialpha input two-phase vector coordinate alpha
-   * @param[in]       Ibeta  input two-phase vector coordinate beta
-   * @param[out]      *pId   points to output	rotor reference frame d
-   * @param[out]      *pIq   points to output	rotor reference frame q
-   * @param[in]       sinVal sine value of rotation angle theta
-   * @param[in]       cosVal cosine value of rotation angle theta
-   * @return none.
-   *
-   * The function implements the forward Park transform.
-   *
-   */
-
-  static __INLINE void arm_park_f32(
-  float32_t Ialpha,
-  float32_t Ibeta,
-  float32_t * pId,
-  float32_t * pIq,
-  float32_t sinVal,
-  float32_t cosVal)
-  {
-    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
-    *pId = Ialpha * cosVal + Ibeta * sinVal;
-
-    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
-    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
-
-  }
-
-  /**
-   * @brief  Park transform for Q31 version
-   * @param[in]       Ialpha input two-phase vector coordinate alpha
-   * @param[in]       Ibeta  input two-phase vector coordinate beta
-   * @param[out]      *pId   points to output rotor reference frame d
-   * @param[out]      *pIq   points to output rotor reference frame q
-   * @param[in]       sinVal sine value of rotation angle theta
-   * @param[in]       cosVal cosine value of rotation angle theta
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
-   */
-
-
-  static __INLINE void arm_park_q31(
-  q31_t Ialpha,
-  q31_t Ibeta,
-  q31_t * pId,
-  q31_t * pIq,
-  q31_t sinVal,
-  q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Ialpha * cosVal) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * sinVal) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Ialpha * sinVal) */
-    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * cosVal) */
-    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
-    /* Calculate pId by adding the two intermediate products 1 and 2 */
-    *pId = __QADD(product1, product2);
-
-    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
-    *pIq = __QSUB(product4, product3);
-  }
-
-  /**
-   * @} end of park group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q7_to_float(
-  q7_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_park Vector Inverse Park transform
-   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkInvFormula.gif
-   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
-   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_park
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Park transform
-   * @param[in]       Id        input coordinate of rotor reference frame d
-   * @param[in]       Iq        input coordinate of rotor reference frame q
-   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]       sinVal    sine value of rotation angle theta
-   * @param[in]       cosVal    cosine value of rotation angle theta
-   * @return none.
-   */
-
-  static __INLINE void arm_inv_park_f32(
-  float32_t Id,
-  float32_t Iq,
-  float32_t * pIalpha,
-  float32_t * pIbeta,
-  float32_t sinVal,
-  float32_t cosVal)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
-    *pIalpha = Id * cosVal - Iq * sinVal;
-
-    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
-    *pIbeta = Id * sinVal + Iq * cosVal;
-
-  }
-
-
-  /**
-   * @brief  Inverse Park transform for	Q31 version
-   * @param[in]       Id        input coordinate of rotor reference frame d
-   * @param[in]       Iq        input coordinate of rotor reference frame q
-   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]       sinVal    sine value of rotation angle theta
-   * @param[in]       cosVal    cosine value of rotation angle theta
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-
-
-  static __INLINE void arm_inv_park_q31(
-  q31_t Id,
-  q31_t Iq,
-  q31_t * pIalpha,
-  q31_t * pIbeta,
-  q31_t sinVal,
-  q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Id * cosVal) */
-    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * sinVal) */
-    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Id * sinVal) */
-    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * cosVal) */
-    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
-    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
-    *pIalpha = __QSUB(product1, product2);
-
-    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
-    *pIbeta = __QADD(product4, product3);
-
-  }
-
-  /**
-   * @} end of Inverse park group
-   */
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q31_to_float(
-  q31_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup LinearInterpolate Linear Interpolation
-   *
-   * Linear interpolation is a method of curve fitting using linear polynomials.
-   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
-   *
-   * \par
-   * \image html LinearInterp.gif "Linear interpolation"
-   *
-   * \par
-   * A  Linear Interpolate function calculates an output value(y), for the input(x)
-   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
-   *
-   * \par Algorithm:
-   * <pre>
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   * </pre>
-   *
-   * \par
-   * This set of functions implements Linear interpolation process
-   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
-   * sample of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
-   * <code>x</code> is the input sample value. The functions returns the output value.
-   *
-   * \par
-   * if x is outside of the table boundary, Linear interpolation returns first value of the table
-   * if x is below input range and returns last value of table if x is above range.
-   */
-
-  /**
-   * @addtogroup LinearInterpolate
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point Linear Interpolation Function.
-   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
-   * @param[in] x input sample to process
-   * @return y processed output sample.
-   *
-   */
-
-  static __INLINE float32_t arm_linear_interp_f32(
-  arm_linear_interp_instance_f32 * S,
-  float32_t x)
-  {
-
-    float32_t y;
-    float32_t x0, x1;                            /* Nearest input values */
-    float32_t y0, y1;                            /* Nearest output values */
-    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
-    int32_t i;                                   /* Index variable */
-    float32_t *pYData = S->pYData;               /* pointer to output table */
-
-    /* Calculation of index */
-    i = (int32_t) ((x - S->x1) / xSpacing);
-
-    if(i < 0)
-    {
-      /* Iniatilize output for below specified range as least output value of table */
-      y = pYData[0];
-    }
-    else if((uint32_t)i >= S->nValues)
-    {
-      /* Iniatilize output for above specified range as last output value of table */
-      y = pYData[S->nValues - 1];
-    }
-    else
-    {
-      /* Calculation of nearest input values */
-      x0 = S->x1 + i * xSpacing;
-      x1 = S->x1 + (i + 1) * xSpacing;
-
-      /* Read of nearest output values */
-      y0 = pYData[i];
-      y1 = pYData[i + 1];
-
-      /* Calculation of output */
-      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
-
-    }
-
-    /* returns output value */
-    return (y);
-  }
-
-   /**
-   *
-   * @brief  Process function for the Q31 Linear Interpolation Function.
-   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
-   * @param[in] x input sample to process
-   * @param[in] nValues number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   *
-   */
-
-
-  static __INLINE q31_t arm_linear_interp_q31(
-  q31_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q31_t y;                                     /* output */
-    q31_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & 0xFFF00000) >> 20);
-
-    if(index >= (int32_t)(nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else if(index < 0)
-    {
-      return (pYData[0]);
-    }
-    else
-    {
-
-      /* 20 bits for the fractional part */
-      /* shift left by 11 to keep fract in 1.31 format */
-      fract = (x & 0x000FFFFF) << 11;
-
-      /* Read two nearest output values from the index in 1.31(q31) format */
-      y0 = pYData[index];
-      y1 = pYData[index + 1u];
-
-      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
-      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-
-      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
-      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-
-      /* Convert y to 1.31 format */
-      return (y << 1u);
-
-    }
-
-  }
-
-  /**
-   *
-   * @brief  Process function for the Q15 Linear Interpolation Function.
-   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
-   * @param[in] x input sample to process
-   * @param[in] nValues number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   *
-   */
-
-
-  static __INLINE q15_t arm_linear_interp_q15(
-  q15_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q63_t y;                                     /* output */
-    q15_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & 0xFFF00000) >> 20u);
-
-    if(index >= (int32_t)(nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else if(index < 0)
-    {
-      return (pYData[0]);
-    }
-    else
-    {
-      /* 20 bits for the fractional part */
-      /* fract is in 12.20 format */
-      fract = (x & 0x000FFFFF);
-
-      /* Read two nearest output values from the index */
-      y0 = pYData[index];
-      y1 = pYData[index + 1u];
-
-      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
-      y = ((q63_t) y0 * (0xFFFFF - fract));
-
-      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
-      y += ((q63_t) y1 * (fract));
-
-      /* convert y to 1.15 format */
-      return (y >> 20);
-    }
-
-
-  }
-
-  /**
-   *
-   * @brief  Process function for the Q7 Linear Interpolation Function.
-   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
-   * @param[in] x input sample to process
-   * @param[in] nValues number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   */
-
-
-  static __INLINE q7_t arm_linear_interp_q7(
-  q7_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q31_t y;                                     /* output */
-    q7_t y0, y1;                                 /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    uint32_t index;                              /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    if (x < 0)
-    {
-      return (pYData[0]);
-    }
-    index = (x >> 20) & 0xfff;
-
-
-    if(index >= (nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else
-    {
-
-      /* 20 bits for the fractional part */
-      /* fract is in 12.20 format */
-      fract = (x & 0x000FFFFF);
-
-      /* Read two nearest output values from the index and are in 1.7(q7) format */
-      y0 = pYData[index];
-      y1 = pYData[index + 1u];
-
-      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
-      y = ((y0 * (0xFFFFF - fract)));
-
-      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
-      y += (y1 * fract);
-
-      /* convert y to 1.7(q7) format */
-      return (y >> 20u);
-
-    }
-
-  }
-  /**
-   * @} end of LinearInterpolate group
-   */
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
-   * @param[in] x input value in radians.
-   * @return  sin(x).
-   */
-
-  float32_t arm_sin_f32(
-  float32_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  sin(x).
-   */
-
-  q31_t arm_sin_q31(
-  q31_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  sin(x).
-   */
-
-  q15_t arm_sin_q15(
-  q15_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
-   * @param[in] x input value in radians.
-   * @return  cos(x).
-   */
-
-  float32_t arm_cos_f32(
-  float32_t x);
-
-  /**
-   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  cos(x).
-   */
-
-  q31_t arm_cos_q31(
-  q31_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  cos(x).
-   */
-
-  q15_t arm_cos_q15(
-  q15_t x);
-
-
-  /**
-   * @ingroup groupFastMath
-   */
-
-
-  /**
-   * @defgroup SQRT Square Root
-   *
-   * Computes the square root of a number.
-   * There are separate functions for Q15, Q31, and floating-point data types.
-   * The square root function is computed using the Newton-Raphson algorithm.
-   * This is an iterative algorithm of the form:
-   * <pre>
-   *      x1 = x0 - f(x0)/f'(x0)
-   * </pre>
-   * where <code>x1</code> is the current estimate,
-   * <code>x0</code> is the previous estimate, and
-   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
-   * For the square root function, the algorithm reduces to:
-   * <pre>
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   * </pre>
-   */
-
-
-  /**
-   * @addtogroup SQRT
-   * @{
-   */
-
-  /**
-   * @brief  Floating-point square root function.
-   * @param[in]  in     input value.
-   * @param[out] *pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-
-  static __INLINE arm_status arm_sqrt_f32(
-  float32_t in,
-  float32_t * pOut)
-  {
-    if(in >= 0.0f)
-    {
-
-//      #if __FPU_USED
-#if (__FPU_USED == 1) && defined ( __CC_ARM   )
-      *pOut = __sqrtf(in);
-#else
-      *pOut = sqrtf(in);
-#endif
-
-      return (ARM_MATH_SUCCESS);
-    }
-    else
-    {
-      *pOut = 0.0f;
-      return (ARM_MATH_ARGUMENT_ERROR);
-    }
-
-  }
-
-
-  /**
-   * @brief Q31 square root function.
-   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
-   * @param[out]  *pOut square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q31(
-  q31_t in,
-  q31_t * pOut);
-
-  /**
-   * @brief  Q15 square root function.
-   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
-   * @param[out]  *pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q15(
-  q15_t in,
-  q15_t * pOut);
-
-  /**
-   * @} end of SQRT group
-   */
-
-
-
-
-
-
-  /**
-   * @brief floating-point Circular write function.
-   */
-
-  static __INLINE void arm_circularWrite_f32(
-  int32_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const int32_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if(wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = wOffset;
-  }
-
-
-
-  /**
-   * @brief floating-point Circular Read function.
-   */
-  static __INLINE void arm_circularRead_f32(
-  int32_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  int32_t * dst,
-  int32_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if(dst == (int32_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update rOffset.  Watch out for positive and negative value  */
-      rOffset += bufferInc;
-
-      if(rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-  /**
-   * @brief Q15 Circular write function.
-   */
-
-  static __INLINE void arm_circularWrite_q15(
-  q15_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const q15_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if(wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = wOffset;
-  }
-
-
-
-  /**
-   * @brief Q15 Circular Read function.
-   */
-  static __INLINE void arm_circularRead_q15(
-  q15_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  q15_t * dst,
-  q15_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if(dst == (q15_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      rOffset += bufferInc;
-
-      if(rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief Q7 Circular write function.
-   */
-
-  static __INLINE void arm_circularWrite_q7(
-  q7_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const q7_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if(wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = wOffset;
-  }
-
-
-
-  /**
-   * @brief Q7 Circular Read function.
-   */
-  static __INLINE void arm_circularRead_q7(
-  q7_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  q7_t * dst,
-  q7_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if(dst == (q7_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update rOffset.  Watch out for positive and negative value */
-      rOffset += bufferInc;
-
-      if(rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult);
-
-  /**
-   * @brief  Sum of the squares of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult);
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Mean value of a Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_mean_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult);
-
-  /**
-   * @brief  Mean value of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-  void arm_mean_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-  /**
-   * @brief  Mean value of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-  void arm_mean_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Mean value of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-  void arm_mean_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Variance of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_var_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Variance of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_var_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Variance of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_var_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-  /**
-   * @brief  Root Mean Square of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_rms_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_rms_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_rms_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-  /**
-   * @brief  Standard deviation of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_std_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Standard deviation of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_std_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Standard deviation of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_std_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-  /**
-   * @brief  Floating-point complex magnitude
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex magnitude
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex magnitude
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex dot product
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @param[out]  *realResult real part of the result returned here
-   * @param[out]  *imagResult imaginary part of the result returned here
-   * @return none.
-   */
-
-  void arm_cmplx_dot_prod_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  uint32_t numSamples,
-  q31_t * realResult,
-  q31_t * imagResult);
-
-  /**
-   * @brief  Q31 complex dot product
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @param[out]  *realResult real part of the result returned here
-   * @param[out]  *imagResult imaginary part of the result returned here
-   * @return none.
-   */
-
-  void arm_cmplx_dot_prod_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  uint32_t numSamples,
-  q63_t * realResult,
-  q63_t * imagResult);
-
-  /**
-   * @brief  Floating-point complex dot product
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @param[out]  *realResult real part of the result returned here
-   * @param[out]  *imagResult imaginary part of the result returned here
-   * @return none.
-   */
-
-  void arm_cmplx_dot_prod_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  uint32_t numSamples,
-  float32_t * realResult,
-  float32_t * imagResult);
-
-  /**
-   * @brief  Q15 complex-by-real multiplication
-   * @param[in]  *pSrcCmplx points to the complex input vector
-   * @param[in]  *pSrcReal points to the real input vector
-   * @param[out]  *pCmplxDst points to the complex output vector
-   * @param[in]  numSamples number of samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_real_q15(
-  q15_t * pSrcCmplx,
-  q15_t * pSrcReal,
-  q15_t * pCmplxDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex-by-real multiplication
-   * @param[in]  *pSrcCmplx points to the complex input vector
-   * @param[in]  *pSrcReal points to the real input vector
-   * @param[out]  *pCmplxDst points to the complex output vector
-   * @param[in]  numSamples number of samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_real_q31(
-  q31_t * pSrcCmplx,
-  q31_t * pSrcReal,
-  q31_t * pCmplxDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Floating-point complex-by-real multiplication
-   * @param[in]  *pSrcCmplx points to the complex input vector
-   * @param[in]  *pSrcReal points to the real input vector
-   * @param[out]  *pCmplxDst points to the complex output vector
-   * @param[in]  numSamples number of samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_real_f32(
-  float32_t * pSrcCmplx,
-  float32_t * pSrcReal,
-  float32_t * pCmplxDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Minimum value of a Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *result is output pointer
-   * @param[in]  index is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-
-  void arm_min_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * result,
-  uint32_t * index);
-
-  /**
-   * @brief  Minimum value of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output pointer
-   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-
-  void arm_min_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex);
-
-  /**
-   * @brief  Minimum value of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output pointer
-   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-  void arm_min_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex);
-
-  /**
-   * @brief  Minimum value of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output pointer
-   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-
-  void arm_min_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult,
-  uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex);
-
-  /**
-   * @brief  Q15 complex-by-complex multiplication
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[out]  *pDst  points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_cmplx_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex-by-complex multiplication
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[out]  *pDst  points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_cmplx_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Floating-point complex-by-complex multiplication
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[out]  *pDst  points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_cmplx_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q31 vector.
-   * @param[in]       *pSrc points to the floating-point input vector
-   * @param[out]      *pDst points to the Q31 output vector
-   * @param[in]       blockSize length of the input vector
-   * @return none.
-   */
-  void arm_float_to_q31(
-  float32_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q15 vector.
-   * @param[in]       *pSrc points to the floating-point input vector
-   * @param[out]      *pDst points to the Q15 output vector
-   * @param[in]       blockSize length of the input vector
-   * @return          none
-   */
-  void arm_float_to_q15(
-  float32_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q7 vector.
-   * @param[in]       *pSrc points to the floating-point input vector
-   * @param[out]      *pDst points to the Q7 output vector
-   * @param[in]       blockSize length of the input vector
-   * @return          none
-   */
-  void arm_float_to_q7(
-  float32_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q31_to_q15(
-  q31_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q31_to_q7(
-  q31_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q15_to_float(
-  q15_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q15_to_q31(
-  q15_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q15_to_q7(
-  q15_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup BilinearInterpolate Bilinear Interpolation
-   *
-   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
-   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
-   * determines values between the grid points.
-   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
-   * Bilinear interpolation is often used in image processing to rescale images.
-   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
-   *
-   * <b>Algorithm</b>
-   * \par
-   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
-   * For floating-point, the instance structure is defined as:
-   * <pre>
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   * </pre>
-   *
-   * \par
-   * where <code>numRows</code> specifies the number of rows in the table;
-   * <code>numCols</code> specifies the number of columns in the table;
-   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
-   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
-   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
-   *
-   * \par
-   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
-   * <pre>
-   *     XF = floor(x)
-   *     YF = floor(y)
-   * </pre>
-   * \par
-   * The interpolated output point is computed as:
-   * <pre>
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   * </pre>
-   * Note that the coordinates (x, y) contain integer and fractional components.
-   * The integer components specify which portion of the table to use while the
-   * fractional components control the interpolation processor.
-   *
-   * \par
-   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
-   */
-
-  /**
-   * @addtogroup BilinearInterpolate
-   * @{
-   */
-
-  /**
-  *
-  * @brief  Floating-point bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate.
-  * @param[in] Y interpolation coordinate.
-  * @return out interpolated value.
-  */
-
-
-  static __INLINE float32_t arm_bilinear_interp_f32(
-  const arm_bilinear_interp_instance_f32 * S,
-  float32_t X,
-  float32_t Y)
-  {
-    float32_t out;
-    float32_t f00, f01, f10, f11;
-    float32_t *pData = S->pData;
-    int32_t xIndex, yIndex, index;
-    float32_t xdiff, ydiff;
-    float32_t b1, b2, b3, b4;
-
-    xIndex = (int32_t) X;
-    yIndex = (int32_t) Y;
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
-       || yIndex > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* Calculation of index for two nearest points in X-direction */
-    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
-
-
-    /* Read two nearest points in X-direction */
-    f00 = pData[index];
-    f01 = pData[index + 1];
-
-    /* Calculation of index for two nearest points in Y-direction */
-    index = (xIndex - 1) + (yIndex) * S->numCols;
-
-
-    /* Read two nearest points in Y-direction */
-    f10 = pData[index];
-    f11 = pData[index + 1];
-
-    /* Calculation of intermediate values */
-    b1 = f00;
-    b2 = f01 - f00;
-    b3 = f10 - f00;
-    b4 = f00 - f01 - f10 + f11;
-
-    /* Calculation of fractional part in X */
-    xdiff = X - xIndex;
-
-    /* Calculation of fractional part in Y */
-    ydiff = Y - yIndex;
-
-    /* Calculation of bi-linear interpolated output */
-    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-  *
-  * @brief  Q31 bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate in 12.20 format.
-  * @param[in] Y interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-
-  static __INLINE q31_t arm_bilinear_interp_q31(
-  arm_bilinear_interp_instance_q31 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q31_t out;                                   /* Temporary output */
-    q31_t acc = 0;                               /* output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q31_t x1, x2, y1, y2;                        /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q31_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & 0xFFF00000) >> 20u);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & 0xFFF00000) >> 20u);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* shift left xfract by 11 to keep 1.31 format */
-    xfract = (X & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + nCols * (cI)];
-    x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-    /* 20 bits for the fractional part */
-    /* shift left yfract by 11 to keep 1.31 format */
-    yfract = (Y & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + nCols * (cI + 1)];
-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
-    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
-    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
-    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
-    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* Convert acc to 1.31(q31) format */
-    return (acc << 2u);
-
-  }
-
-  /**
-  * @brief  Q15 bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate in 12.20 format.
-  * @param[in] Y interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-
-  static __INLINE q15_t arm_bilinear_interp_q15(
-  arm_bilinear_interp_instance_q15 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q15_t x1, x2, y1, y2;                        /* Nearest output values */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    int32_t rI, cI;                              /* Row and column indices */
-    q15_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & 0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & 0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + nCols * (cI)];
-    x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + nCols * (cI + 1)];
-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
-    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
-    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
-    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
-    acc = ((q63_t) out * (0xFFFFF - yfract));
-
-    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
-    acc += ((q63_t) out * (xfract));
-
-    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* acc is in 13.51 format and down shift acc by 36 times */
-    /* Convert out to 1.15 format */
-    return (acc >> 36);
-
-  }
-
-  /**
-  * @brief  Q7 bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate in 12.20 format.
-  * @param[in] Y interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-
-  static __INLINE q7_t arm_bilinear_interp_q7(
-  arm_bilinear_interp_instance_q7 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q7_t x1, x2, y1, y2;                         /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q7_t *pYData = S->pData;                     /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & 0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & 0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + nCols * (cI)];
-    x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + nCols * (cI + 1)];
-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
-    out = ((x1 * (0xFFFFF - xfract)));
-    acc = (((q63_t) out * (0xFFFFF - yfract)));
-
-    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
-    out = ((x2 * (0xFFFFF - yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y1 * (0xFFFFF - xfract)));
-    acc += (((q63_t) out * (yfract)));
-
-    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y2 * (yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
-    return (acc >> 40);
-
-  }
-
-  /**
-   * @} end of BilinearInterpolate group
-   */
-   
-
-//SMMLAR
-#define multAcc_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-//SMMLSR
-#define multSub_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-//SMMULR
-#define mult_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
-
-//SMMLA
-#define multAcc_32x32_keep32(a, x, y) \
-    a += (q31_t) (((q63_t) x * y) >> 32)
-
-//SMMLS
-#define multSub_32x32_keep32(a, x, y) \
-    a -= (q31_t) (((q63_t) x * y) >> 32)
-
-//SMMUL
-#define mult_32x32_keep32(a, x, y) \
-    a = (q31_t) (((q63_t) x * y ) >> 32)
-
-
-#if defined ( __CC_ARM ) //Keil
-
-//Enter low optimization region - place directly above function definition
-    #ifdef ARM_MATH_CM4
-      #define LOW_OPTIMIZATION_ENTER \
-         _Pragma ("push")         \
-         _Pragma ("O1")
-    #else
-      #define LOW_OPTIMIZATION_ENTER 
-    #endif
-
-//Exit low optimization region - place directly after end of function definition
-    #ifdef ARM_MATH_CM4
-      #define LOW_OPTIMIZATION_EXIT \
-         _Pragma ("pop")
-    #else
-      #define LOW_OPTIMIZATION_EXIT  
-    #endif
-
-//Enter low optimization region - place directly above function definition
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
-//Exit low optimization region - place directly after end of function definition
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__ICCARM__) //IAR
-
-//Enter low optimization region - place directly above function definition
-    #ifdef ARM_MATH_CM4
-      #define LOW_OPTIMIZATION_ENTER \
-         _Pragma ("optimize=low")
-    #else
-      #define LOW_OPTIMIZATION_ENTER   
-    #endif
-
-//Exit low optimization region - place directly after end of function definition
-  #define LOW_OPTIMIZATION_EXIT
-
-//Enter low optimization region - place directly above function definition
-    #ifdef ARM_MATH_CM4
-      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
-         _Pragma ("optimize=low")
-    #else
-      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER   
-    #endif
-
-//Exit low optimization region - place directly after end of function definition
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__GNUC__)
-
-  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
-
-  #define LOW_OPTIMIZATION_EXIT
-
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__CSMC__)		// Cosmic
-
-#define LOW_OPTIMIZATION_ENTER
-#define LOW_OPTIMIZATION_EXIT
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__TASKING__)		// TASKING
-
-#define LOW_OPTIMIZATION_ENTER
-#define LOW_OPTIMIZATION_EXIT
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#endif
-
-
-#ifdef	__cplusplus
-}
-#endif
-
-
-#endif /* _ARM_MATH_H */
-
-/**
- *
- * End of file.
- */

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/cmsis.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,38 +0,0 @@
-/* mbed Microcontroller Library
- * A generic CMSIS include header
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "stm32f1xx.h"
-#include "cmsis_nvic.h"
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/cmsis_nvic.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */ 
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-// CORE: 16 vectors (= 64 bytes from 0x00 to 0x3F)
-// MCU Peripherals: 43 vectors (= 172 bytes from 0x40 to 0xEB)
-// Total:  236 bytes to be reserved in RAM (see scatter file)
-#define NVIC_NUM_VECTORS      (16 + 43)
-#define NVIC_USER_IRQ_OFFSET  16
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/core_ca9.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,276 +0,0 @@
-/**************************************************************************//**
- * @file     core_ca9.h
- * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File
- * @version
- * @date     25 March 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2012 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CA9_H_GENERIC
-#define __CORE_CA9_H_GENERIC
-
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_A9
-  @{
- */
-
-/*  CMSIS CA9 definitions */
-#define __CA9_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CA9_CMSIS_VERSION_SUB   (0x10)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CA9_CMSIS_VERSION       ((__CA9_CMSIS_VERSION_MAIN << 16) | \
-                                    __CA9_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_A                (0x09)                                   /*!< Cortex-A Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-  #define __STATIC_ASM     static __asm
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-  #define __STATIC_ASM     static __asm
-
-#include <stdint.h>
-inline uint32_t __get_PSR(void) {
-	__ASM("mrs r0, cpsr");
-}
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-  #define __STATIC_ASM     static __asm
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-  #define __STATIC_ASM     static __asm
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-  #define __STATIC_ASM     static __asm
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-#endif
-
-#include <stdint.h>                      /*!< standard types definitions                      */
-#include "core_caInstr.h"                /*!< Core Instruction Access                         */
-#include "core_caFunc.h"                 /*!< Core Function Access                            */
-#include "core_cm4_simd.h"               /*!< Compiler specific SIMD Intrinsics               */
-
-#endif /* __CORE_CA9_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CA9_H_DEPENDANT
-#define __CORE_CA9_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CA9_REV
-    #define __CA9_REV               0x0000
-    #warning "__CA9_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             1
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    1
-  #endif
-
-  #if __Vendor_SysTickConfig == 0
-    #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_A9 */
-
-
-/*******************************************************************************
- *                 Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-A processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t reserved1:7;                /*!< bit: 20..23  Reserved                           */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */ 
-} APSR_Type;
-
-
-/*@} end of group CMSIS_CORE */
-
-/*@} end of CMSIS_Core_FPUFunctions */
-
-
-#endif /* __CORE_CA9_H_GENERIC */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/core_caFunc.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1427 +0,0 @@
-/**************************************************************************//**
- * @file     core_caFunc.h
- * @brief    CMSIS Cortex-A Core Function Access Header File
- * @version  V3.10
- * @date     30 Oct 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CAFUNC_H__
-#define __CORE_CAFUNC_H__
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-#define MODE_USR 0x10
-#define MODE_FIQ 0x11
-#define MODE_IRQ 0x12
-#define MODE_SVC 0x13
-#define MODE_MON 0x16
-#define MODE_ABT 0x17
-#define MODE_HYP 0x1A
-#define MODE_UND 0x1B
-#define MODE_SYS 0x1F
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/** \brief  Get CPSR Register
-
-    This function returns the content of the CPSR Register.
-
-    \return               CPSR Register value
- */
-__STATIC_INLINE uint32_t __get_CPSR(void)
-{
-  register uint32_t __regCPSR          __ASM("cpsr");
-  return(__regCPSR);
-}
-
-/** \brief  Set Stack Pointer
-
-    This function assigns the given value to the current stack pointer.
-
-    \param [in]    topOfStack  Stack Pointer value to set
- */
-register uint32_t __regSP              __ASM("sp");
-__STATIC_INLINE void __set_SP(uint32_t topOfStack)
-{
-    __regSP = topOfStack;
-}
-
-
-/** \brief  Get link register
-
-    This function returns the value of the link register
-
-    \return    Value of link register
- */
-register uint32_t __reglr         __ASM("lr");
-__STATIC_INLINE uint32_t __get_LR(void)
-{
-  return(__reglr);
-}
-
-/** \brief  Set link register
-
-    This function sets the value of the link register
-
-    \param [in]    lr  LR value to set
- */
-__STATIC_INLINE void __set_LR(uint32_t lr)
-{
-  __reglr = lr;
-}
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the USR/SYS Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
- */
-__STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
-{
-    ARM
-    PRESERVE8
-
-    BIC     R0, R0, #7  ;ensure stack is 8-byte aligned
-    MRS     R1, CPSR
-    CPS     #MODE_SYS   ;no effect in USR mode
-    MOV     SP, R0
-    MSR     CPSR_c, R1  ;no effect in USR mode
-    ISB
-    BX      LR
-
-}
-
-/** \brief  Set User Mode
-
-    This function changes the processor state to User Mode
- */
-__STATIC_ASM void __set_CPS_USR(void)
-{
-    ARM 
-
-    CPS  #MODE_USR  
-    BX   LR
-}
-
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-/** \brief  Get FPEXC
-
-    This function returns the current value of the Floating Point Exception Control register.
-
-    \return               Floating Point Exception Control register value
- */
-__STATIC_INLINE uint32_t __get_FPEXC(void)
-{
-#if (__FPU_PRESENT == 1)
-  register uint32_t __regfpexc         __ASM("fpexc");
-  return(__regfpexc);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPEXC
-
-    This function assigns the given value to the Floating Point Exception Control register.
-
-    \param [in]    fpscr  Floating Point Exception Control value to set
- */
-__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
-{
-#if (__FPU_PRESENT == 1)
-  register uint32_t __regfpexc         __ASM("fpexc");
-  __regfpexc = (fpexc);
-#endif
-}
-
-/** \brief  Get CPACR
-
-    This function returns the current value of the Coprocessor Access Control register.
-
-    \return               Coprocessor Access Control register value
- */
-__STATIC_INLINE uint32_t __get_CPACR(void)
-{
-    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
-    return __regCPACR;
-}
-
-/** \brief  Set CPACR
-
-    This function assigns the given value to the Coprocessor Access Control register.
-
-    \param [in]    cpacr  Coprocessor Acccess Control value to set
- */
-__STATIC_INLINE void __set_CPACR(uint32_t cpacr)
-{
-    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
-    __regCPACR = cpacr;
-    __ISB();
-}
-
-/** \brief  Get CBAR
-
-    This function returns the value of the Configuration Base Address register.
-
-    \return               Configuration Base Address register value
- */
-__STATIC_INLINE uint32_t __get_CBAR() {
-    register uint32_t __regCBAR         __ASM("cp15:4:c15:c0:0");
-    return(__regCBAR);
-}
-
-/** \brief  Get TTBR0
-
-    This function returns the value of the Translation Table Base Register 0.
-
-    \return               Translation Table Base Register 0 value
- */
-__STATIC_INLINE uint32_t __get_TTBR0() {
-    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
-    return(__regTTBR0);
-}
-
-/** \brief  Set TTBR0
-
-    This function assigns the given value to the Translation Table Base Register 0.
-
-    \param [in]    ttbr0  Translation Table Base Register 0 value to set
- */
-__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
-    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
-    __regTTBR0 = ttbr0;
-    __ISB();
-}
-
-/** \brief  Get DACR
-
-    This function returns the value of the Domain Access Control Register.
-
-    \return               Domain Access Control Register value
- */
-__STATIC_INLINE uint32_t __get_DACR() {
-    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
-    return(__regDACR);
-}
-
-/** \brief  Set DACR
-
-    This function assigns the given value to the Domain Access Control Register.
-
-    \param [in]    dacr   Domain Access Control Register value to set
- */
-__STATIC_INLINE void __set_DACR(uint32_t dacr) {
-    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
-    __regDACR = dacr;
-    __ISB();
-}
-
-/******************************** Cache and BTAC enable  ****************************************************/
-
-/** \brief  Set SCTLR
-
-    This function assigns the given value to the System Control Register.
-
-    \param [in]    sctlr  System Control Register value to set
- */
-__STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
-{
-    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
-    __regSCTLR = sctlr;
-}
-
-/** \brief  Get SCTLR
-
-    This function returns the value of the System Control Register.
-
-    \return               System Control Register value
- */
-__STATIC_INLINE uint32_t __get_SCTLR() {
-    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
-    return(__regSCTLR);
-}
-
-/** \brief  Enable Caches
-
-    Enable Caches
- */
-__STATIC_INLINE void __enable_caches(void) {
-    // Set I bit 12 to enable I Cache
-    // Set C bit  2 to enable D Cache
-    __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
-}
-
-/** \brief  Disable Caches
-
-    Disable Caches
- */
-__STATIC_INLINE void __disable_caches(void) {
-    // Clear I bit 12 to disable I Cache
-    // Clear C bit  2 to disable D Cache
-    __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
-    __ISB();
-}
-
-/** \brief  Enable BTAC
-
-    Enable BTAC
- */
-__STATIC_INLINE void __enable_btac(void) {
-    // Set Z bit 11 to enable branch prediction
-    __set_SCTLR( __get_SCTLR() | (1 << 11));
-    __ISB();
-}
-
-/** \brief  Disable BTAC
-
-    Disable BTAC
- */
-__STATIC_INLINE void __disable_btac(void) {
-    // Clear Z bit 11 to disable branch prediction
-    __set_SCTLR( __get_SCTLR() & ~(1 << 11));
-}
-
-
-/** \brief  Enable MMU
-
-    Enable MMU
- */
-__STATIC_INLINE void __enable_mmu(void) {
-    // Set M bit 0 to enable the MMU
-    // Set AFE bit to enable simplified access permissions model
-    // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
-    __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
-    __ISB();
-}
-
-/** \brief  Disable MMU
-
-    Disable MMU
- */
-__STATIC_INLINE void __disable_mmu(void) {
-    // Clear M bit 0 to disable the MMU
-    __set_SCTLR( __get_SCTLR() & ~1);
-    __ISB();
-}
-
-/******************************** TLB maintenance operations ************************************************/
-/** \brief  Invalidate the whole tlb
-
-    TLBIALL. Invalidate the whole tlb
- */
-
-__STATIC_INLINE void __ca9u_inv_tlb_all(void) {
-    register uint32_t __TLBIALL         __ASM("cp15:0:c8:c7:0");
-    __TLBIALL = 0;
-    __DSB();
-    __ISB();
-}
-
-/******************************** BTB maintenance operations ************************************************/
-/** \brief  Invalidate entire branch predictor array
-
-    BPIALL. Branch Predictor Invalidate All.
- */
-
-__STATIC_INLINE void __v7_inv_btac(void) {
-    register uint32_t __BPIALL          __ASM("cp15:0:c7:c5:6");
-    __BPIALL  = 0;
-    __DSB();     //ensure completion of the invalidation
-    __ISB();     //ensure instruction fetch path sees new state
-}
-
-
-/******************************** L1 cache operations ******************************************************/
-
-/** \brief  Invalidate the whole I$
-
-    ICIALLU. Instruction Cache Invalidate All to PoU
- */
-__STATIC_INLINE void __v7_inv_icache_all(void) {
-    register uint32_t __ICIALLU         __ASM("cp15:0:c7:c5:0");
-    __ICIALLU = 0;
-    __DSB();     //ensure completion of the invalidation
-    __ISB();     //ensure instruction fetch path sees new I cache state
-}
-
-/** \brief  Clean D$ by MVA
-
-    DCCMVAC. Data cache clean by MVA to PoC
- */
-__STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
-    register uint32_t __DCCMVAC         __ASM("cp15:0:c7:c10:1");
-    __DCCMVAC = (uint32_t)va;
-    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Invalidate D$ by MVA
-
-    DCIMVAC. Data cache invalidate by MVA to PoC
- */
-__STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
-    register uint32_t __DCIMVAC         __ASM("cp15:0:c7:c6:1");
-    __DCIMVAC = (uint32_t)va;
-    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Clean and Invalidate D$ by MVA
-
-    DCCIMVAC. Data cache clean and invalidate by MVA to PoC
- */
-__STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
-    register uint32_t __DCCIMVAC        __ASM("cp15:0:c7:c14:1");
-    __DCCIMVAC = (uint32_t)va;
-    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Clean and Invalidate the entire data or unified cache
-
-    Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
- */
-#pragma push
-#pragma arm
-__STATIC_ASM void __v7_all_cache(uint32_t op) {
-        ARM 
-
-        PUSH    {R4-R11}
-
-        MRC     p15, 1, R6, c0, c0, 1      // Read CLIDR
-        ANDS    R3, R6, #0x07000000        // Extract coherency level
-        MOV     R3, R3, LSR #23            // Total cache levels << 1
-        BEQ     Finished                   // If 0, no need to clean
-
-        MOV     R10, #0                    // R10 holds current cache level << 1
-Loop1   ADD     R2, R10, R10, LSR #1       // R2 holds cache "Set" position
-        MOV     R1, R6, LSR R2             // Bottom 3 bits are the Cache-type for this level
-        AND     R1, R1, #7                 // Isolate those lower 3 bits
-        CMP     R1, #2
-        BLT     Skip                       // No cache or only instruction cache at this level
-
-        MCR     p15, 2, R10, c0, c0, 0     // Write the Cache Size selection register
-        ISB                                // ISB to sync the change to the CacheSizeID reg
-        MRC     p15, 1, R1, c0, c0, 0      // Reads current Cache Size ID register
-        AND     R2, R1, #7                 // Extract the line length field
-        ADD     R2, R2, #4                 // Add 4 for the line length offset (log2 16 bytes)
-        LDR     R4, =0x3FF
-        ANDS    R4, R4, R1, LSR #3         // R4 is the max number on the way size (right aligned)
-        CLZ     R5, R4                     // R5 is the bit position of the way size increment
-        LDR     R7, =0x7FFF
-        ANDS    R7, R7, R1, LSR #13        // R7 is the max number of the index size (right aligned)
-
-Loop2   MOV     R9, R4                     // R9 working copy of the max way size (right aligned)
-
-Loop3   ORR     R11, R10, R9, LSL R5       // Factor in the Way number and cache number into R11
-        ORR     R11, R11, R7, LSL R2       // Factor in the Set number
-        CMP     R0, #0
-        BNE     Dccsw
-        MCR     p15, 0, R11, c7, c6, 2     // DCISW. Invalidate by Set/Way
-        B       cont
-Dccsw   CMP     R0, #1
-        BNE     Dccisw
-        MCR     p15, 0, R11, c7, c10, 2    // DCCSW. Clean by Set/Way
-        B       cont
-Dccisw  MCR     p15, 0, R11, c7, c14, 2    // DCCISW. Clean and Invalidate by Set/Way
-cont    SUBS    R9, R9, #1                 // Decrement the Way number
-        BGE     Loop3
-        SUBS    R7, R7, #1                 // Decrement the Set number
-        BGE     Loop2
-Skip    ADD     R10, R10, #2               // Increment the cache number
-        CMP     R3, R10
-        BGT     Loop1
-
-Finished
-        DSB
-        POP    {R4-R11}
-        BX     lr
-
-}
-#pragma pop
-
-
-/** \brief  Invalidate the whole D$
-
-    DCISW. Invalidate by Set/Way
- */
-
-__STATIC_INLINE void __v7_inv_dcache_all(void) {
-    __v7_all_cache(0);
-}
-
-/** \brief  Clean the whole D$
-
-    DCCSW. Clean by Set/Way
- */
-
-__STATIC_INLINE void __v7_clean_dcache_all(void) {
-    __v7_all_cache(1);
-}
-
-/** \brief  Clean and invalidate the whole D$
-
-    DCCISW. Clean and Invalidate by Set/Way
- */
-
-__STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
-    __v7_all_cache(2);
-}
-
-#include "core_ca_mmu.h"
-
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-
-#define __inline inline
-
-inline static uint32_t __disable_irq_iar() {
-  int irq_dis = __get_CPSR() & 0x80;      // 7bit CPSR.I
-  __disable_irq();
-  return irq_dis;
-}
-
-#define MODE_USR 0x10
-#define MODE_FIQ 0x11
-#define MODE_IRQ 0x12
-#define MODE_SVC 0x13
-#define MODE_MON 0x16
-#define MODE_ABT 0x17
-#define MODE_HYP 0x1A
-#define MODE_UND 0x1B
-#define MODE_SYS 0x1F
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the USR/SYS Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
- */
-// from rt_CMSIS.c
-__arm static inline void __set_PSP(uint32_t topOfProcStack) {
-__asm(
-  "    ARM\n"
-//  "    PRESERVE8\n"
-
-  "    BIC     R0, R0, #7  ;ensure stack is 8-byte aligned \n"
-  "    MRS     R1, CPSR \n"
-  "    CPS     #0x1F   ;no effect in USR mode \n"        // MODE_SYS
-  "    MOV     SP, R0 \n"
-  "    MSR     CPSR_c, R1  ;no effect in USR mode \n"
-  "    ISB \n"
-  "    BX      LR \n");
-}
-
-/** \brief  Set User Mode
-
-    This function changes the processor state to User Mode
- */
-// from rt_CMSIS.c
-__arm static inline void __set_CPS_USR(void) {
-__asm(
-  "    ARM \n"
-
-  "    CPS  #0x10  \n"                  // MODE_USR
-  "    BX   LR\n");
-}
-
-/** \brief  Set TTBR0
-
-    This function assigns the given value to the Translation Table Base Register 0.
-
-    \param [in]    ttbr0  Translation Table Base Register 0 value to set
- */
-// from mmu_Renesas_RZ_A1.c
-__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
-    __MCR(15, 0, ttbr0, 2, 0, 0);      // reg to cp15
-    __ISB();
-}
-
-/** \brief  Set DACR
-
-    This function assigns the given value to the Domain Access Control Register.
-
-    \param [in]    dacr   Domain Access Control Register value to set
- */
-// from mmu_Renesas_RZ_A1.c
-__STATIC_INLINE void __set_DACR(uint32_t dacr) {
-    __MCR(15, 0, dacr, 3, 0, 0);      // reg to cp15
-    __ISB();
-}
-
-
-/******************************** Cache and BTAC enable  ****************************************************/
-/** \brief  Set SCTLR
-
-    This function assigns the given value to the System Control Register.
-
-    \param [in]    sctlr  System Control Register value to set
- */
-// from __enable_mmu()
-__STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
-    __MCR(15, 0, sctlr, 1, 0, 0);      // reg to cp15
-}
-
-/** \brief  Get SCTLR
-
-    This function returns the value of the System Control Register.
-
-    \return               System Control Register value
- */
-// from __enable_mmu()
-__STATIC_INLINE uint32_t __get_SCTLR() {
-	uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
-	return __regSCTLR;
-}
-
-/** \brief  Enable Caches
-
-    Enable Caches
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __enable_caches(void) {
-    __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
-}
-
-/** \brief  Enable BTAC
-
-    Enable BTAC
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __enable_btac(void) {
-    __set_SCTLR( __get_SCTLR() | (1 << 11));
-    __ISB();
-}
-
-/** \brief  Enable MMU
-
-    Enable MMU
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __enable_mmu(void) {
-    // Set M bit 0 to enable the MMU
-    // Set AFE bit to enable simplified access permissions model
-    // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
-    __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
-    __ISB();
-}
-
-/******************************** TLB maintenance operations ************************************************/
-/** \brief  Invalidate the whole tlb
-
-    TLBIALL. Invalidate the whole tlb
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __ca9u_inv_tlb_all(void) {
-	uint32_t val = 0;
-    __MCR(15, 0, val, 8, 7, 0);      // reg to cp15
-    __MCR(15, 0, val, 8, 6, 0);      // reg to cp15
-    __MCR(15, 0, val, 8, 5, 0);      // reg to cp15
-    __DSB();
-    __ISB();
-}
-
-/******************************** BTB maintenance operations ************************************************/
-/** \brief  Invalidate entire branch predictor array
-
-    BPIALL. Branch Predictor Invalidate All.
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __v7_inv_btac(void) {
-	uint32_t val = 0;
-    __MCR(15, 0, val, 7, 5, 6);      // reg to cp15
-    __DSB();     //ensure completion of the invalidation
-    __ISB();     //ensure instruction fetch path sees new state
-}
-
-
-/******************************** L1 cache operations ******************************************************/
-
-/** \brief  Invalidate the whole I$
-
-    ICIALLU. Instruction Cache Invalidate All to PoU
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __v7_inv_icache_all(void) {
-	uint32_t val = 0;
-    __MCR(15, 0, val, 7, 5, 0);      // reg to cp15
-    __DSB();     //ensure completion of the invalidation
-    __ISB();     //ensure instruction fetch path sees new I cache state
-}
-
-// from __v7_inv_dcache_all()
-__arm static inline void __v7_all_cache(uint32_t op) {
-__asm(
-	"        ARM \n"
-
-	"        PUSH    {R4-R11} \n"
-
-	"        MRC     p15, 1, R6, c0, c0, 1\n"      // Read CLIDR
-	"        ANDS    R3, R6, #0x07000000\n"        // Extract coherency level
-	"        MOV     R3, R3, LSR #23\n"            // Total cache levels << 1
-	"        BEQ     Finished\n"                   // If 0, no need to clean
-
-	"        MOV     R10, #0\n"                    // R10 holds current cache level << 1
-    "Loop1:   ADD     R2, R10, R10, LSR #1\n"       // R2 holds cache "Set" position
-	"        MOV     R1, R6, LSR R2 \n"            // Bottom 3 bits are the Cache-type for this level
-	"        AND     R1, R1, #7 \n"                // Isolate those lower 3 bits
-	"        CMP     R1, #2 \n"
-	"        BLT     Skip \n"                      // No cache or only instruction cache at this level
-
-	"        MCR     p15, 2, R10, c0, c0, 0 \n"    // Write the Cache Size selection register
-	"        ISB \n"                               // ISB to sync the change to the CacheSizeID reg
-	"        MRC     p15, 1, R1, c0, c0, 0 \n"     // Reads current Cache Size ID register
-	"        AND     R2, R1, #7 \n"                // Extract the line length field
-	"        ADD     R2, R2, #4 \n"                // Add 4 for the line length offset (log2 16 bytes)
-	"        movw    R4, #0x3FF \n"
-	"        ANDS    R4, R4, R1, LSR #3 \n"        // R4 is the max number on the way size (right aligned)
-	"        CLZ     R5, R4 \n"                    // R5 is the bit position of the way size increment
-	"        movw    R7, #0x7FFF \n"
-	"        ANDS    R7, R7, R1, LSR #13 \n"       // R7 is the max number of the index size (right aligned)
-
-	"Loop2:   MOV     R9, R4 \n"                    // R9 working copy of the max way size (right aligned)
-
-	"Loop3:   ORR     R11, R10, R9, LSL R5 \n"      // Factor in the Way number and cache number into R11
-	"        ORR     R11, R11, R7, LSL R2 \n"      // Factor in the Set number
-	"        CMP     R0, #0 \n"
-	"        BNE     Dccsw \n"
-	"        MCR     p15, 0, R11, c7, c6, 2 \n"    // DCISW. Invalidate by Set/Way
-	"        B       cont \n"
-	"Dccsw:   CMP     R0, #1 \n"
-	"        BNE     Dccisw \n"
-	"        MCR     p15, 0, R11, c7, c10, 2 \n"   // DCCSW. Clean by Set/Way
-	"        B       cont \n"
-	"Dccisw:  MCR     p15, 0, R11, c7, c14, 2 \n"   // DCCISW, Clean and Invalidate by Set/Way
-	"cont:    SUBS    R9, R9, #1 \n"                // Decrement the Way number
-	"        BGE     Loop3 \n"
-	"        SUBS    R7, R7, #1 \n"                // Decrement the Set number
-	"        BGE     Loop2 \n"
-	"Skip:    ADD     R10, R10, #2 \n"              // increment the cache number
-	"        CMP     R3, R10 \n"
-	"        BGT     Loop1 \n"
-
-	"Finished: \n"
-	"        DSB \n"
-	"        POP    {R4-R11} \n"
-	"        BX     lr \n" );
-}
-
-/** \brief  Invalidate the whole D$
-
-    DCISW. Invalidate by Set/Way
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __v7_inv_dcache_all(void) {
-    __v7_all_cache(0);
-}
-/** \brief  Clean and Invalidate D$ by MVA
-
-    DCCIMVAC. Data cache clean and invalidate by MVA to PoC
- */
-__STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
-    __MCR(15, 0, (uint32_t)va, 7, 14, 1);
-    __DMB();
-}
-
-#include "core_ca_mmu.h"
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-#define MODE_USR 0x10
-#define MODE_FIQ 0x11
-#define MODE_IRQ 0x12
-#define MODE_SVC 0x13
-#define MODE_MON 0x16
-#define MODE_ABT 0x17
-#define MODE_HYP 0x1A
-#define MODE_UND 0x1B
-#define MODE_SYS 0x1F
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
-    __ASM volatile ("cpsie i");
-}
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("mrs %0, cpsr" : "=r" (result));
-    __ASM volatile ("cpsid i");
-    return(result & 0x80);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-#if 1
-  register uint32_t __regAPSR;
-  __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
-#else
-  register uint32_t __regAPSR          __ASM("apsr");
-#endif
-  return(__regAPSR);
-}
-
-
-/** \brief  Get CPSR Register
-
-    This function returns the content of the CPSR Register.
-
-    \return               CPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
-{
-#if 1
-  register uint32_t __regCPSR;
-  __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
-#else
-  register uint32_t __regCPSR          __ASM("cpsr");
-#endif
-  return(__regCPSR);
-}
-
-#if 0
-/** \brief  Set Stack Pointer
-
-    This function assigns the given value to the current stack pointer.
-
-    \param [in]    topOfStack  Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
-{
-    register uint32_t __regSP       __ASM("sp");
-    __regSP = topOfStack;
-}
-#endif
-
-/** \brief  Get link register
-
-    This function returns the value of the link register
-
-    \return    Value of link register
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
-{
-  register uint32_t __reglr         __ASM("lr");
-  return(__reglr);
-}
-
-#if 0
-/** \brief  Set link register
-
-    This function sets the value of the link register
-
-    \param [in]    lr  LR value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
-{
-  register uint32_t __reglr         __ASM("lr");
-  __reglr = lr;
-}
-#endif
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the USR/SYS Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-    __asm__ volatile (
-    ".ARM;"
-    ".eabi_attribute Tag_ABI_align8_preserved,1;"
-
-    "BIC     R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
-    "MRS     R1, CPSR;"
-    "CPS     %0;"         /* ;no effect in USR mode */
-    "MOV     SP, R0;"
-    "MSR     CPSR_c, R1;" /* ;no effect in USR mode */
-    "ISB;"
-    //"BX      LR;"
-    :
-    : "i"(MODE_SYS)
-    : "r0", "r1");
-    return;
-}
-
-/** \brief  Set User Mode
-
-    This function changes the processor state to User Mode
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
-{
-    __asm__ volatile (
-    ".ARM;"
-
-    "CPS  %0;"
-    //"BX   LR;"
-    :
-    : "i"(MODE_USR)
-    : );
-    return;
-}
-
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq()                __asm__ volatile ("cpsie f")
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq()               __asm__ volatile ("cpsid f")
-
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-#if 1
-    uint32_t result;
-
-    __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
-    return (result);
-#else
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#endif
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-#if 1
-    __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
-#else
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-#endif
-}
-
-/** \brief  Get FPEXC
-
-    This function returns the current value of the Floating Point Exception Control register.
-
-    \return               Floating Point Exception Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
-{
-#if (__FPU_PRESENT == 1)
-#if 1
-    uint32_t result;
-
-    __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
-    return (result);
-#else
-  register uint32_t __regfpexc         __ASM("fpexc");
-  return(__regfpexc);
-#endif
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPEXC
-
-    This function assigns the given value to the Floating Point Exception Control register.
-
-    \param [in]    fpscr  Floating Point Exception Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
-{
-#if (__FPU_PRESENT == 1)
-#if 1
-    __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
-#else
-  register uint32_t __regfpexc         __ASM("fpexc");
-  __regfpexc = (fpexc);
-#endif
-#endif
-}
-
-/** \brief  Get CPACR
-
-    This function returns the current value of the Coprocessor Access Control register.
-
-    \return               Coprocessor Access Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
-{
-#if 1
-    register uint32_t __regCPACR;
-    __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
-#else
-    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
-#endif
-    return __regCPACR;
-}
-
-/** \brief  Set CPACR
-
-    This function assigns the given value to the Coprocessor Access Control register.
-
-    \param [in]    cpacr  Coprocessor Acccess Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
-{
-#if 1
-    __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
-#else
-    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
-    __regCPACR = cpacr;
-#endif
-    __ISB();
-}
-
-/** \brief  Get CBAR
-
-    This function returns the value of the Configuration Base Address register.
-
-    \return               Configuration Base Address register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
-#if 1
-    register uint32_t __regCBAR;
-    __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
-#else
-    register uint32_t __regCBAR         __ASM("cp15:4:c15:c0:0");
-#endif
-    return(__regCBAR);
-}
-
-/** \brief  Get TTBR0
-
-    This function returns the value of the Translation Table Base Register 0.
-
-    \return               Translation Table Base Register 0 value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
-#if 1
-    register uint32_t __regTTBR0;
-    __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
-#else
-    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
-#endif
-    return(__regTTBR0);
-}
-
-/** \brief  Set TTBR0
-
-    This function assigns the given value to the Translation Table Base Register 0.
-
-    \param [in]    ttbr0  Translation Table Base Register 0 value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
-#if 1
-	__ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
-#else
-    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
-    __regTTBR0 = ttbr0;
-#endif
-    __ISB();
-}
-
-/** \brief  Get DACR
-
-    This function returns the value of the Domain Access Control Register.
-
-    \return               Domain Access Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
-#if 1
-    register uint32_t __regDACR;
-    __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
-#else
-    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
-#endif
-    return(__regDACR);
-}
-
-/** \brief  Set DACR
-
-    This function assigns the given value to the Domain Access Control Register.
-
-    \param [in]    dacr   Domain Access Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
-#if 1
-	__ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
-#else
-    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
-    __regDACR = dacr;
-#endif
-    __ISB();
-}
-
-/******************************** Cache and BTAC enable  ****************************************************/
-
-/** \brief  Set SCTLR
-
-    This function assigns the given value to the System Control Register.
-
-    \param [in]    sctlr  System Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
-{
-#if 1
-	__ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
-#else
-    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
-    __regSCTLR = sctlr;
-#endif
-}
-
-/** \brief  Get SCTLR
-
-    This function returns the value of the System Control Register.
-
-    \return               System Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
-#if 1
-	register uint32_t __regSCTLR;
-	__ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
-#else
-    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
-#endif
-    return(__regSCTLR);
-}
-
-/** \brief  Enable Caches
-
-    Enable Caches
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
-    // Set I bit 12 to enable I Cache
-    // Set C bit  2 to enable D Cache
-    __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
-}
-
-/** \brief  Disable Caches
-
-    Disable Caches
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
-    // Clear I bit 12 to disable I Cache
-    // Clear C bit  2 to disable D Cache
-    __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
-    __ISB();
-}
-
-/** \brief  Enable BTAC
-
-    Enable BTAC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
-    // Set Z bit 11 to enable branch prediction
-    __set_SCTLR( __get_SCTLR() | (1 << 11));
-    __ISB();
-}
-
-/** \brief  Disable BTAC
-
-    Disable BTAC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
-    // Clear Z bit 11 to disable branch prediction
-    __set_SCTLR( __get_SCTLR() & ~(1 << 11));
-}
-
-
-/** \brief  Enable MMU
-
-    Enable MMU
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
-    // Set M bit 0 to enable the MMU
-    // Set AFE bit to enable simplified access permissions model
-    // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
-    __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
-    __ISB();
-}
-
-/** \brief  Disable MMU
-
-    Disable MMU
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
-    // Clear M bit 0 to disable the MMU
-    __set_SCTLR( __get_SCTLR() & ~1);
-    __ISB();
-}
-
-/******************************** TLB maintenance operations ************************************************/
-/** \brief  Invalidate the whole tlb
-
-    TLBIALL. Invalidate the whole tlb
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
-#if 1
-	__ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
-#else
-    register uint32_t __TLBIALL         __ASM("cp15:0:c8:c7:0");
-    __TLBIALL = 0;
-#endif
-    __DSB();
-    __ISB();
-}
-
-/******************************** BTB maintenance operations ************************************************/
-/** \brief  Invalidate entire branch predictor array
-
-    BPIALL. Branch Predictor Invalidate All.
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
-#if 1
-	__ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
-#else
-    register uint32_t __BPIALL          __ASM("cp15:0:c7:c5:6");
-    __BPIALL  = 0;
-#endif
-    __DSB();     //ensure completion of the invalidation
-    __ISB();     //ensure instruction fetch path sees new state
-}
-
-
-/******************************** L1 cache operations ******************************************************/
-
-/** \brief  Invalidate the whole I$
-
-    ICIALLU. Instruction Cache Invalidate All to PoU
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
-#if 1
-	__ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
-#else
-    register uint32_t __ICIALLU         __ASM("cp15:0:c7:c5:0");
-    __ICIALLU = 0;
-#endif
-    __DSB();     //ensure completion of the invalidation
-    __ISB();     //ensure instruction fetch path sees new I cache state
-}
-
-/** \brief  Clean D$ by MVA
-
-    DCCMVAC. Data cache clean by MVA to PoC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
-#if 1
-    __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
-#else
-    register uint32_t __DCCMVAC         __ASM("cp15:0:c7:c10:1");
-    __DCCMVAC = (uint32_t)va;
-#endif
-    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Invalidate D$ by MVA
-
-    DCIMVAC. Data cache invalidate by MVA to PoC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
-#if 1
-    __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
-#else
-    register uint32_t __DCIMVAC         __ASM("cp15:0:c7:c6:1");
-    __DCIMVAC = (uint32_t)va;
-#endif
-    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Clean and Invalidate D$ by MVA
-
-    DCCIMVAC. Data cache clean and invalidate by MVA to PoC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
-#if 1
-    __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
-#else
-    register uint32_t __DCCIMVAC        __ASM("cp15:0:c7:c14:1");
-    __DCCIMVAC = (uint32_t)va;
-#endif
-    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Clean and Invalidate the entire data or unified cache
-
-    Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
- */
-extern void __v7_all_cache(uint32_t op);
-
-
-/** \brief  Invalidate the whole D$
-
-    DCISW. Invalidate by Set/Way
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
-    __v7_all_cache(0);
-}
-
-/** \brief  Clean the whole D$
-
-    DCCSW. Clean by Set/Way
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
-    __v7_all_cache(1);
-}
-
-/** \brief  Clean and invalidate the whole D$
-
-    DCCISW. Clean and Invalidate by Set/Way
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
-    __v7_all_cache(2);
-}
-
-#include "core_ca_mmu.h"
-
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-
-#error TASKING Compiler support not implemented for Cortex-A
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CAFUNC_H__ */

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/core_caInstr.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-/**************************************************************************//**
- * @file     core_caInstr.h
- * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File
- * @version
- * @date     04. December 2012
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2012 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-#ifndef __CORE_CAINSTR_H__
-#define __CORE_CAINSTR_H__
-
-#define __CORTEX_M 0x3
-#include "core_cmInstr.h"
-#undef  __CORTEX_M
-
-#endif
-

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/core_ca_mmu.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,847 +0,0 @@
-;/**************************************************************************//**
-; * @file     core_ca_mmu.h
-; * @brief    MMU Startup File for A9_MP Device Series
-; * @version  V1.01
-; * @date     10 Sept 2014
-; *
-; * @note
-; *
-; ******************************************************************************/
-;/* Copyright (c) 2012-2014 ARM LIMITED
-;
-;   All rights reserved.
-;   Redistribution and use in source and binary forms, with or without
-;   modification, are permitted provided that the following conditions are met:
-;   - Redistributions of source code must retain the above copyright
-;     notice, this list of conditions and the following disclaimer.
-;   - Redistributions in binary form must reproduce the above copyright
-;     notice, this list of conditions and the following disclaimer in the
-;     documentation and/or other materials provided with the distribution.
-;   - Neither the name of ARM nor the names of its contributors may be used
-;     to endorse or promote products derived from this software without
-;     specific prior written permission.
-;   *
-;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-;   POSSIBILITY OF SUCH DAMAGE.
-;   ---------------------------------------------------------------------------*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef _MMU_FUNC_H
-#define _MMU_FUNC_H
-
-#define SECTION_DESCRIPTOR      (0x2)
-#define SECTION_MASK            (0xFFFFFFFC)
-
-#define SECTION_TEXCB_MASK      (0xFFFF8FF3)
-#define SECTION_B_SHIFT         (2)
-#define SECTION_C_SHIFT         (3)
-#define SECTION_TEX0_SHIFT      (12)
-#define SECTION_TEX1_SHIFT      (13)
-#define SECTION_TEX2_SHIFT      (14)
-
-#define SECTION_XN_MASK         (0xFFFFFFEF)
-#define SECTION_XN_SHIFT        (4)
-
-#define SECTION_DOMAIN_MASK     (0xFFFFFE1F)
-#define SECTION_DOMAIN_SHIFT    (5)
-
-#define SECTION_P_MASK          (0xFFFFFDFF)
-#define SECTION_P_SHIFT         (9)
-
-#define SECTION_AP_MASK         (0xFFFF73FF)
-#define SECTION_AP_SHIFT        (10)
-#define SECTION_AP2_SHIFT       (15)
-
-#define SECTION_S_MASK          (0xFFFEFFFF)
-#define SECTION_S_SHIFT         (16)
-
-#define SECTION_NG_MASK         (0xFFFDFFFF)
-#define SECTION_NG_SHIFT        (17)
-
-#define SECTION_NS_MASK         (0xFFF7FFFF)
-#define SECTION_NS_SHIFT        (19)
-
-
-#define PAGE_L1_DESCRIPTOR      (0x1)
-#define PAGE_L1_MASK            (0xFFFFFFFC)
-
-#define PAGE_L2_4K_DESC         (0x2)
-#define PAGE_L2_4K_MASK         (0xFFFFFFFD)
-
-#define PAGE_L2_64K_DESC        (0x1)
-#define PAGE_L2_64K_MASK        (0xFFFFFFFC)
-
-#define PAGE_4K_TEXCB_MASK      (0xFFFFFE33)
-#define PAGE_4K_B_SHIFT         (2)
-#define PAGE_4K_C_SHIFT         (3)
-#define PAGE_4K_TEX0_SHIFT      (6)
-#define PAGE_4K_TEX1_SHIFT      (7)
-#define PAGE_4K_TEX2_SHIFT      (8)
-
-#define PAGE_64K_TEXCB_MASK     (0xFFFF8FF3)
-#define PAGE_64K_B_SHIFT        (2)
-#define PAGE_64K_C_SHIFT        (3)
-#define PAGE_64K_TEX0_SHIFT     (12)
-#define PAGE_64K_TEX1_SHIFT     (13)
-#define PAGE_64K_TEX2_SHIFT     (14)
-
-#define PAGE_TEXCB_MASK         (0xFFFF8FF3)
-#define PAGE_B_SHIFT            (2)
-#define PAGE_C_SHIFT            (3)
-#define PAGE_TEX_SHIFT          (12)
-
-#define PAGE_XN_4K_MASK         (0xFFFFFFFE)
-#define PAGE_XN_4K_SHIFT        (0)
-#define PAGE_XN_64K_MASK        (0xFFFF7FFF)
-#define PAGE_XN_64K_SHIFT       (15)
-
-
-#define PAGE_DOMAIN_MASK        (0xFFFFFE1F)
-#define PAGE_DOMAIN_SHIFT       (5)
-
-#define PAGE_P_MASK             (0xFFFFFDFF)
-#define PAGE_P_SHIFT            (9)
-
-#define PAGE_AP_MASK            (0xFFFFFDCF)
-#define PAGE_AP_SHIFT           (4)
-#define PAGE_AP2_SHIFT          (9)
-
-#define PAGE_S_MASK             (0xFFFFFBFF)
-#define PAGE_S_SHIFT            (10)
-
-#define PAGE_NG_MASK            (0xFFFFF7FF)
-#define PAGE_NG_SHIFT           (11)
-
-#define PAGE_NS_MASK            (0xFFFFFFF7)
-#define PAGE_NS_SHIFT           (3)
-
-#define OFFSET_1M               (0x00100000)
-#define OFFSET_64K              (0x00010000)
-#define OFFSET_4K               (0x00001000)
-
-#define DESCRIPTOR_FAULT        (0x00000000)
-
-/* ###########################  MMU Function Access  ########################### */
-/** \ingroup  MMU_FunctionInterface
-    \defgroup MMU_Functions MMU Functions Interface
-  @{
- */
-
-/* Attributes enumerations */
-
-/* Region size attributes */
-typedef enum
-{
-   SECTION,
-   PAGE_4k,
-   PAGE_64k,
-} mmu_region_size_Type;
-
-/* Region type attributes */
-typedef enum
-{
-   NORMAL,
-   DEVICE,
-   SHARED_DEVICE,
-   NON_SHARED_DEVICE,
-   STRONGLY_ORDERED
-} mmu_memory_Type;
-
-/* Region cacheability attributes */
-typedef enum
-{
-   NON_CACHEABLE,
-   WB_WA,
-   WT,
-   WB_NO_WA,
-} mmu_cacheability_Type;
-
-/* Region parity check attributes */
-typedef enum
-{
-   ECC_DISABLED,
-   ECC_ENABLED,
-} mmu_ecc_check_Type;
-
-/* Region execution attributes */
-typedef enum
-{
-   EXECUTE,
-   NON_EXECUTE,
-} mmu_execute_Type;
-
-/* Region global attributes */
-typedef enum
-{
-   GLOBAL,
-   NON_GLOBAL,
-} mmu_global_Type;
-
-/* Region shareability attributes */
-typedef enum
-{
-   NON_SHARED,
-   SHARED,
-} mmu_shared_Type;
-
-/* Region security attributes */
-typedef enum
-{
-   SECURE,
-   NON_SECURE,
-} mmu_secure_Type;
-
-/* Region access attributes */
-typedef enum
-{
-   NO_ACCESS,
-   RW,
-   READ,
-} mmu_access_Type;
-
-/* Memory Region definition */
-typedef struct RegionStruct {
-    mmu_region_size_Type rg_t;
-    mmu_memory_Type mem_t;
-    uint8_t domain;
-    mmu_cacheability_Type inner_norm_t;
-    mmu_cacheability_Type outer_norm_t;
-    mmu_ecc_check_Type e_t;
-    mmu_execute_Type xn_t;
-    mmu_global_Type g_t;
-    mmu_secure_Type sec_t;
-    mmu_access_Type priv_t;
-    mmu_access_Type user_t;
-    mmu_shared_Type sh_t;
-
-} mmu_region_attributes_Type;
-
-/** \brief  Set section execution-never attribute
-
-    The function sets section execution-never attribute
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]                xn  Section execution-never attribute : EXECUTE , NON_EXECUTE.
-
-    \return          0  
- */
-__STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
-{
-    *descriptor_l1 &= SECTION_XN_MASK;
-    *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
-    return 0;
-}
-
-/** \brief  Set section domain
-
-    The function sets section domain
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]            domain  Section domain
-
-    \return          0  
- */
-__STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
-{
-    *descriptor_l1 &= SECTION_DOMAIN_MASK;
-    *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
-    return 0;
-}
-
-/** \brief  Set section parity check
-
-    The function sets section parity check
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
-
-    \return          0  
- */
-__STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
-{
-    *descriptor_l1 &= SECTION_P_MASK;
-    *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
-    return 0;
-}
-
-/** \brief  Set section access privileges
-
-    The function sets section access privileges
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]              user  User Level Access: NO_ACCESS, RW, READ
-    \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
-    \param [in]               afe  Access flag enable
-
-    \return          0  
- */
-__STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv,  uint32_t afe)
-{
-    uint32_t ap = 0;
-
-    if (afe == 0) { //full access
-        if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
-        else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
-        else if ((priv == RW) && (user == READ))        { ap = 0x2; }
-        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
-        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
-        else if ((priv == READ) && (user == READ))      { ap = 0x7; }
-    }
-
-    else { //Simplified access
-        if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
-        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
-        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
-        else if ((priv == READ) && (user == READ))      { ap = 0x7; }
-    }
-
-    *descriptor_l1 &= SECTION_AP_MASK;
-    *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
-    *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
-
-    return 0;
-}
-
-/** \brief  Set section shareability
-
-    The function sets section shareability
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]             s_bit  Section shareability: NON_SHARED, SHARED
-
-    \return          0  
- */
-__STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
-{
-    *descriptor_l1 &= SECTION_S_MASK;
-    *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
-    return 0;
-}
-
-/** \brief  Set section Global attribute
-
-    The function sets section Global attribute
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]             g_bit  Section attribute: GLOBAL, NON_GLOBAL
-
-    \return          0  
- */
-__STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
-{
-    *descriptor_l1 &= SECTION_NG_MASK;
-    *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
-    return 0;
-}
-
-/** \brief  Set section Security attribute
-
-    The function sets section Global attribute
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]             s_bit  Section Security attribute: SECURE, NON_SECURE
-
-    \return          0  
- */
-__STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
-{
-    *descriptor_l1 &= SECTION_NS_MASK;
-    *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
-    return 0;
-}
-
-/* Page 4k or 64k */
-/** \brief  Set 4k/64k page execution-never attribute
-
-    The function sets 4k/64k page execution-never attribute
-
-    \param [out]    descriptor_l2  L2 descriptor.
-    \param [in]                xn  Page execution-never attribute : EXECUTE , NON_EXECUTE.
-    \param [in]              page  Page size: PAGE_4k, PAGE_64k,
-   
-    \return          0  
- */
-__STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
-{
-    if (page == PAGE_4k)
-    {
-        *descriptor_l2 &= PAGE_XN_4K_MASK;
-        *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
-    }
-    else
-    {
-        *descriptor_l2 &= PAGE_XN_64K_MASK;
-        *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
-    }
-    return 0;
-}
-
-/** \brief  Set 4k/64k page domain
-
-    The function sets 4k/64k page domain
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]            domain  Page domain
-
-    \return          0  
- */
-__STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
-{
-    *descriptor_l1 &= PAGE_DOMAIN_MASK;
-    *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
-    return 0;
-}
-
-/** \brief  Set 4k/64k page parity check
-
-    The function sets 4k/64k page parity check
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
-
-    \return          0  
- */
-__STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
-{
-    *descriptor_l1 &= SECTION_P_MASK;
-    *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
-    return 0;
-}
-
-/** \brief  Set 4k/64k page access privileges
-
-    The function sets 4k/64k page access privileges
-
-    \param [out]    descriptor_l2  L2 descriptor.
-    \param [in]              user  User Level Access: NO_ACCESS, RW, READ
-    \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
-    \param [in]               afe  Access flag enable
-
-    \return          0  
- */
-__STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv,  uint32_t afe)
-{
-    uint32_t ap = 0;
-
-    if (afe == 0) { //full access
-        if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
-        else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
-        else if ((priv == RW) && (user == READ))        { ap = 0x2; }
-        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
-        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
-        else if ((priv == READ) && (user == READ))      { ap = 0x6; }
-    }
-
-    else { //Simplified access
-        if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
-        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
-        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
-        else if ((priv == READ) && (user == READ))      { ap = 0x7; }
-    }
-
-    *descriptor_l2 &= PAGE_AP_MASK;
-    *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
-    *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
-
-    return 0;
-}
-
-/** \brief  Set 4k/64k page shareability
-
-    The function sets 4k/64k page shareability
-
-    \param [out]    descriptor_l2  L2 descriptor.
-    \param [in]             s_bit  4k/64k page shareability: NON_SHARED, SHARED
-
-    \return          0  
- */
-__STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
-{
-    *descriptor_l2 &= PAGE_S_MASK;
-    *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
-    return 0;
-}
-
-/** \brief  Set 4k/64k page Global attribute
-
-    The function sets 4k/64k page Global attribute
-
-    \param [out]    descriptor_l2  L2 descriptor.
-    \param [in]             g_bit  4k/64k page attribute: GLOBAL, NON_GLOBAL
-
-    \return          0  
- */
-__STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
-{
-    *descriptor_l2 &= PAGE_NG_MASK;
-    *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
-    return 0;
-}
-
-/** \brief  Set 4k/64k page Security attribute
-
-    The function sets 4k/64k page Global attribute
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]             s_bit  4k/64k page Security attribute: SECURE, NON_SECURE
-
-    \return          0  
- */
-__STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
-{
-    *descriptor_l1 &= PAGE_NS_MASK;
-    *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
-    return 0;
-}
-
-
-/** \brief  Set Section memory attributes
-
-    The function sets section memory attributes
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]               mem  Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
-    \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-    \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-
-    \return          0  
- */
-__STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
-{
-    *descriptor_l1 &= SECTION_TEXCB_MASK;
-
-    if (STRONGLY_ORDERED == mem)
-    {
-        return 0;
-    }
-    else if (SHARED_DEVICE == mem)
-    {
-        *descriptor_l1 |= (1 << SECTION_B_SHIFT);
-    }
-    else if (NON_SHARED_DEVICE == mem)
-    {
-        *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
-    }
-    else if (NORMAL == mem)
-    {
-           *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
-           switch(inner)
-           {
-            case NON_CACHEABLE:
-            break;
-            case WB_WA:
-                *descriptor_l1 |= (1 << SECTION_B_SHIFT);
-                break;
-            case WT:
-                *descriptor_l1 |= 1 << SECTION_C_SHIFT;
-                break;
-            case WB_NO_WA:
-                *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
-                break;
-        }
-        switch(outer)
-        {
-            case NON_CACHEABLE:
-             break;
-            case WB_WA:
-                *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
-                break;
-            case WT:
-                *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
-                break;
-            case WB_NO_WA:
-                *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
-                break;
-        }
-    }
-
-    return 0;
-}
-
-/** \brief  Set 4k/64k page memory attributes
-
-    The function sets 4k/64k page memory attributes
-
-    \param [out]    descriptor_l2  L2 descriptor.
-    \param [in]               mem  4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
-    \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-    \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-
-    \return          0  
- */
-__STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
-{
-    *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
-
-    if (page == PAGE_64k)
-    {
-        //same as section
-        __memory_section(descriptor_l2, mem, outer, inner);
-    }
-    else
-    {
-        if (STRONGLY_ORDERED == mem)
-        {
-            return 0;
-        }
-        else if (SHARED_DEVICE == mem)
-        {
-            *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
-        }
-        else if (NON_SHARED_DEVICE == mem)
-        {
-             *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
-        }
-        else if (NORMAL == mem)
-        {
-            *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
-            switch(inner)
-            {
-                case NON_CACHEABLE:
-                break;
-                case WB_WA:
-                     *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
-                     break;
-                case WT:
-                    *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
-                     break;
-                case WB_NO_WA:
-                    *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
-                    break;
-            }
-            switch(outer)
-            {
-                case NON_CACHEABLE:
-                break;
-                case WB_WA:
-                      *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
-                    break;
-                case WT:
-                     *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
-                    break;
-                case WB_NO_WA:
-                    *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
-                    break;
-            }
-        }
-    }
-
-    return 0;
-}
-
-/** \brief  Create a L1 section descriptor
-
-    The function creates a section descriptor.
-    
-    Assumptions:
-    - 16MB super sections not supported
-    - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
-    - Functions always return 0
-
-    \param [out]       descriptor  L1 descriptor
-    \param [out]      descriptor2  L2 descriptor
-    \param [in]               reg  Section attributes
-
-    \return          0  
- */
-__STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
-{
-    *descriptor  = 0;
-
-   __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
-   __xn_section(descriptor,reg.xn_t);
-   __domain_section(descriptor, reg.domain);
-   __p_section(descriptor, reg.e_t);
-   __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
-   __shared_section(descriptor,reg.sh_t);
-   __global_section(descriptor,reg.g_t);
-   __secure_section(descriptor,reg.sec_t);
-   *descriptor &= SECTION_MASK;
-   *descriptor |= SECTION_DESCRIPTOR;
-
-   return 0;
-
-}
-
-
-/** \brief  Create a L1 and L2 4k/64k page descriptor
-
-    The function creates a 4k/64k page descriptor.
-    Assumptions:
-    - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
-    - Functions always return 0
-
-    \param [out]       descriptor  L1 descriptor
-    \param [out]      descriptor2  L2 descriptor
-    \param [in]               reg  4k/64k page attributes
-
-    \return          0  
- */
-__STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
-{
-    *descriptor  = 0;
-    *descriptor2 = 0;
-
-    switch (reg.rg_t)
-    {
-        case PAGE_4k:
-            __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
-            __xn_page(descriptor2, reg.xn_t, PAGE_4k);
-            __domain_page(descriptor, reg.domain);
-            __p_page(descriptor, reg.e_t);
-            __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
-            __shared_page(descriptor2,reg.sh_t);
-            __global_page(descriptor2,reg.g_t);
-            __secure_page(descriptor,reg.sec_t);
-            *descriptor &= PAGE_L1_MASK;
-            *descriptor |= PAGE_L1_DESCRIPTOR;
-            *descriptor2 &= PAGE_L2_4K_MASK;
-            *descriptor2 |= PAGE_L2_4K_DESC;
-            break;
-
-        case PAGE_64k:
-            __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
-            __xn_page(descriptor2, reg.xn_t, PAGE_64k);
-            __domain_page(descriptor, reg.domain);
-            __p_page(descriptor, reg.e_t);
-            __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
-            __shared_page(descriptor2,reg.sh_t);
-            __global_page(descriptor2,reg.g_t);
-            __secure_page(descriptor,reg.sec_t);
-            *descriptor &= PAGE_L1_MASK;
-            *descriptor |= PAGE_L1_DESCRIPTOR;
-            *descriptor2 &= PAGE_L2_64K_MASK;
-            *descriptor2 |= PAGE_L2_64K_DESC;
-            break;
-
-        case SECTION:
-            //error
-            break;    
-
-    }
-
-   return 0;
-
-}
-
-/** \brief  Create a 1MB Section
-
-    \param [in]               ttb  Translation table base address
-    \param [in]      base_address  Section base address
-    \param [in]             count  Number of sections to create
-    \param [in]     descriptor_l1  L1 descriptor (region attributes) 
-
- */
-__STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
-{
-    uint32_t offset;
-    uint32_t entry;
-    uint32_t i;
-
-    offset = base_address >> 20;
-    entry  = (base_address & 0xFFF00000) | descriptor_l1;
-
-    //4 bytes aligned
-    ttb = ttb + offset;
-
-    for (i = 0; i < count; i++ )
-    {
-        //4 bytes aligned
-       *ttb++ = entry;
-       entry += OFFSET_1M;
-    }
-}
-
-/** \brief  Create a 4k page entry
-
-    \param [in]               ttb  L1 table base address
-    \param [in]      base_address  4k base address
-    \param [in]             count  Number of 4k pages to create
-    \param [in]     descriptor_l1  L1 descriptor (region attributes) 
-    \param [in]            ttb_l2  L2 table base address
-    \param [in]     descriptor_l2  L2 descriptor (region attributes) 
-
- */
-__STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
-{
-
-    uint32_t offset, offset2;
-    uint32_t entry, entry2;
-    uint32_t i;
-
-
-    offset = base_address >> 20;
-    entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
-
-    //4 bytes aligned
-    ttb += offset;
-    //create l1_entry
-    *ttb = entry;
-
-    offset2 = (base_address & 0xff000) >> 12;
-    ttb_l2 += offset2;
-    entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
-    for (i = 0; i < count; i++ )
-    {
-        //4 bytes aligned
-       *ttb_l2++ = entry2;
-       entry2 += OFFSET_4K;
-    }
-}
-
-/** \brief  Create a 64k page entry
-
-    \param [in]               ttb  L1 table base address
-    \param [in]      base_address  64k base address
-    \param [in]             count  Number of 64k pages to create
-    \param [in]     descriptor_l1  L1 descriptor (region attributes) 
-    \param [in]            ttb_l2  L2 table base address
-    \param [in]     descriptor_l2  L2 descriptor (region attributes) 
-
- */
-__STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
-{
-    uint32_t offset, offset2;
-    uint32_t entry, entry2;
-    uint32_t i,j;
-
-
-    offset = base_address >> 20;
-    entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
-
-    //4 bytes aligned
-    ttb += offset;
-    //create l1_entry
-    *ttb = entry;
-
-    offset2 = (base_address & 0xff000) >> 12;
-    ttb_l2 += offset2;
-    entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
-    for (i = 0; i < count; i++ )
-    {
-        //create 16 entries
-        for (j = 0; j < 16; j++)
-            //4 bytes aligned
-            *ttb_l2++ = entry2;
-        entry2 += OFFSET_64K;
-    }
-}
-
-/*@} end of MMU_Functions */
-#endif
-
-#ifdef __cplusplus
-}
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/core_cm0.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,740 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0.h
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M0
-  @{
- */
-
-/*  CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM0_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI__VFP_SUPPORT____
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0_REV
-    #define __CM0_REV               0x0000
-    #warning "__CM0_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_M0 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved                           */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-       uint32_t RESERVED0;
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED1;
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
-                are only accessible over DAP and not via processor. Therefore
-                they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if((int32_t)(IRQn) < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if((int32_t)(IRQn) < 0) {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
-  }
-  else {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1) { __NOP(); }                                        /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/core_cm0plus.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,854 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0plus.h
- * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CM0PLUS_H_GENERIC
-#define __CORE_CM0PLUS_H_GENERIC
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex-M0+
-  @{
- */
-
-/*  CMSIS CM0P definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04)                                /*!< [31:16] CMSIS HAL main version   */
-#define __CM0PLUS_CMSIS_VERSION_SUB  (0x00)                                /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
-                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI__VFP_SUPPORT____
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0PLUS_H_DEPENDANT
-#define __CORE_CM0PLUS_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0PLUS_REV
-    #define __CM0PLUS_REV             0x0000
-    #warning "__CM0PLUS_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __VTOR_PRESENT
-    #define __VTOR_PRESENT            0
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex-M0+ */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-#if (__VTOR_PRESENT == 1)
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-#else
-       uint32_t RESERVED0;
-#endif
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED1;
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if (__VTOR_PRESENT == 1)
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
-                are only accessible over DAP and not via processor. Therefore
-                they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M0+ Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if((int32_t)(IRQn) < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if((int32_t)(IRQn) < 0) {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
-  }
-  else {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1) { __NOP(); }                                        /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);}      /* Reload value impossible */
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/core_cm3.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1693 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm3.h
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M3
-  @{
- */
-
-/*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM3_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI__VFP_SUPPORT____
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM3_REV
-    #define __CM3_REV               0x0200
-    #warning "__CM3_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_M3 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[5];
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#if (__CM3_REV < 0x0201)                   /* core r2p1 */
-#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-#else
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
-#else
-       uint32_t RESERVED1[1];
-#endif
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __O  union
-  {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];
-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];
-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-       uint32_t RESERVED0[1];
-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-       uint32_t RESERVED1[1];
-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-       uint32_t RESERVED2[1];
-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/** \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-       uint32_t RESERVED1[55];
-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-       uint32_t RESERVED2[131];
-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-       uint32_t RESERVED3[759];
-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-       uint32_t RESERVED4[1];
-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-       uint32_t RESERVED5[39];
-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-       uint32_t RESERVED7[8];
-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/** \brief  Set Priority Grouping
-
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if((int32_t)IRQn < 0) {
-    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if((int32_t)IRQn < 0) {
-    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
-  }
-  else {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-  while(1) { __NOP(); }                                             /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief  ITM Send Character
-
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
-    \param [in]     ch  Character to transmit.
-
-    \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
-    ITM->PORT[0].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/core_cm4.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1887 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm4.h
- * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M4
-  @{
- */
-
-/*  CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM4_REV
-    #define __CM4_REV               0x0000
-    #warning "__CM4_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16                                             /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16                                             /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos                    2                                             /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[5];
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __O  union
-  {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];
-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];
-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-       uint32_t RESERVED0[1];
-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-       uint32_t RESERVED1[1];
-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-       uint32_t RESERVED2[1];
-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/** \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-       uint32_t RESERVED1[55];
-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-       uint32_t RESERVED2[131];
-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-       uint32_t RESERVED3[759];
-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-       uint32_t RESERVED4[1];
-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-       uint32_t RESERVED5[39];
-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-       uint32_t RESERVED7[8];
-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-    \brief      Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/** \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
-  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
-  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
-  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
-  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
-} FPU_Type;
-
-/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-#if (__FPU_PRESENT == 1)
-  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
-  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* CMSIS_VECTAB_VIRTUAL */
-
-
-/** \brief  Set Priority Grouping
-
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if((int32_t)IRQn < 0) {
-    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if((int32_t)IRQn < 0) {
-    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
-  }
-  else {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-  while(1) { __NOP(); }                                             /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief  ITM Send Character
-
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
-    \param [in]     ch  Character to transmit.
-
-    \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
-    ITM->PORT[0].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/core_cm4_simd.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,673 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm4_simd.h
- * @brief    CMSIS Cortex-M4 SIMD Header File
- * @version  V3.20
- * @date     25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM4_SIMD_H
-#define __CORE_CM4_SIMD_H
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
-                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#include <cmsis_iar.h>
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#include <cmsis_ccs.h>
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SMLALD(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLALDX(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SMLSLD(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLSLDX(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else \
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-/* not yet supported */
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CORE_CM4_SIMD_H */
-
-#ifdef __cplusplus
-}
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/core_cm7.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,2397 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm7.h
- * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CM7_H_GENERIC
-#define __CORE_CM7_H_GENERIC
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M7
-  @{
- */
-
-/*  CMSIS CM7 definitions */
-#define __CM7_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM7_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM7_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x07)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM7_H_DEPENDANT
-#define __CORE_CM7_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM7_REV
-    #define __CM7_REV               0x0000
-    #warning "__CM7_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __ICACHE_PRESENT
-    #define __ICACHE_PRESENT          0
-    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __DCACHE_PRESENT
-    #define __DCACHE_PRESENT          0
-    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __DTCM_PRESENT
-    #define __DTCM_PRESENT            0
-    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_M7 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16                                             /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16                                             /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos                    2                                             /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHPR[12];                /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t ID_PFR[2];               /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t ID_DFR;                  /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ID_AFR;                  /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t ID_MFR[4];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ID_ISAR[5];              /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[1];
-  __I  uint32_t CLIDR;                   /*!< Offset: 0x078 (R/ )  Cache Level ID register                               */
-  __I  uint32_t CTR;                     /*!< Offset: 0x07C (R/ )  Cache Type register                                   */
-  __I  uint32_t CCSIDR;                  /*!< Offset: 0x080 (R/ )  Cache Size ID Register                                */
-  __IO uint32_t CSSELR;                  /*!< Offset: 0x084 (R/W)  Cache Size Selection Register                         */
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-       uint32_t RESERVED3[93];
-  __O  uint32_t STIR;                    /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register                 */
-       uint32_t RESERVED4[15];
-  __I  uint32_t MVFR0;                   /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0                      */
-  __I  uint32_t MVFR1;                   /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1                      */
-  __I  uint32_t MVFR2;                   /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1                      */
-       uint32_t RESERVED5[1];
-  __O  uint32_t ICIALLU;                 /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU                         */
-       uint32_t RESERVED6[1];
-  __O  uint32_t ICIMVAU;                 /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU                      */
-  __O  uint32_t DCIMVAC;                 /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC                      */
-  __O  uint32_t DCISW;                   /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way                         */
-  __O  uint32_t DCCMVAU;                 /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU                           */
-  __O  uint32_t DCCMVAC;                 /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC                           */
-  __O  uint32_t DCCSW;                   /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way                              */
-  __O  uint32_t DCCIMVAC;                /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC            */
-  __O  uint32_t DCCISW;                  /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way               */
-       uint32_t RESERVED7[6];
-  __IO uint32_t ITCMCR;                  /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register   */
-  __IO uint32_t DTCMCR;                  /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers         */
-  __IO uint32_t AHBPCR;                  /*!< Offset: 0x298 (R/W)  AHBP Control Register                                 */
-  __IO uint32_t CACR;                    /*!< Offset: 0x29C (R/W)  L1 Cache Control Register                             */
-  __IO uint32_t AHBSCR;                  /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register                            */
-       uint32_t RESERVED8[1];
-  __IO uint32_t ABFSR;                   /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register                   */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                      18                                            /*!< SCB CCR: Branch prediction enable bit Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
-
-#define SCB_CCR_IC_Pos                      17                                            /*!< SCB CCR: Instruction cache enable bit Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
-
-#define SCB_CCR_DC_Pos                      16                                            /*!< SCB CCR: Cache enable bit Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
-
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/* Cache Level ID register */
-#define SCB_CLIDR_LOUU_Pos                 27                                             /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos                  24                                             /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_FORMAT_Pos)                  /*!< SCB CLIDR: LoC Mask */
-
-/* Cache Type register */
-#define SCB_CTR_FORMAT_Pos                 29                                             /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos                    24                                             /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos                    20                                             /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos               16                                             /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos                0                                             /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
-
-/* Cache Size ID Register */
-#define SCB_CCSIDR_WT_Pos                  31                                             /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk                  (7UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos                  30                                             /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk                  (7UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos                  29                                             /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk                  (7UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos                  28                                             /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk                  (7UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos             13                                             /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3                                             /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos             0                                             /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
-
-/* Cache Size Selection Register */
-#define SCB_CSSELR_LEVEL_Pos                1                                             /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos                  0                                             /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register */
-#define SCB_STIR_INTID_Pos                  0                                             /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register*/
-#define SCB_ITCMCR_SZ_Pos                   3                                             /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos                2                                             /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos                  1                                             /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos                   0                                             /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Registers */
-#define SCB_DTCMCR_SZ_Pos                   3                                             /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos                2                                             /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos                  1                                             /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos                   0                                             /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register */
-#define SCB_AHBPCR_SZ_Pos                   1                                             /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos                   0                                             /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register */
-#define SCB_CACR_FORCEWT_Pos                2                                             /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos                  1                                             /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos                   0                                             /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
-
-/* AHBS control register */
-#define SCB_AHBSCR_INITCOUNT_Pos           11                                             /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos                 2                                             /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos                  0                                             /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register */
-#define SCB_ABFSR_AXIMTYPE_Pos              8                                             /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos                  4                                             /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos                  3                                             /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos                  2                                             /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos                  1                                             /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos                  0                                             /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12                                          /*!< ACTLR: DISITMATBFLUSH Position */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
-
-#define SCnSCB_ACTLR_DISRAMODE_Pos         11                                          /*!< ACTLR: DISRAMODE Position */
-#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
-
-#define SCnSCB_ACTLR_FPEXCODIS_Pos         10                                          /*!< ACTLR: FPEXCODIS Position */
-#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __O  union
-  {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];
-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];
-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-       uint32_t RESERVED0[1];
-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-       uint32_t RESERVED1[1];
-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-       uint32_t RESERVED2[1];
-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
-       uint32_t RESERVED3[981];
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 (  W)  Lock Access Register                      */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R  )  Lock Status Register                      */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/** \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-       uint32_t RESERVED1[55];
-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-       uint32_t RESERVED2[131];
-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-       uint32_t RESERVED3[759];
-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-       uint32_t RESERVED4[1];
-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-       uint32_t RESERVED5[39];
-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-       uint32_t RESERVED7[8];
-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-    \brief      Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/** \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
-  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
-  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
-  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
-  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
-  __I  uint32_t MVFR2;                   /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2                       */
-} FPU_Type;
-
-/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/* Media and FP Feature Register 2 */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-#if (__FPU_PRESENT == 1)
-  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
-  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/** \brief  Set Priority Grouping
-
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if((int32_t)IRQn < 0) {
-    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if((int32_t)IRQn < 0) {
-    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
-  }
-  else {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-  while(1) { __NOP(); }                                             /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_FpuFunctions FPU Functions
-    \brief      Function that provides FPU type.
-    @{
- */
-
-/**
-  \fn          uint32_t SCB_GetFPUType(void)
-  \brief       get FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-  uint32_t mvfr0;
-
-  mvfr0 = SCB->MVFR0;
-  if        ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
-    return 2UL;           // Double + Single precision FPU
-  } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
-    return 1UL;           // Single precision FPU
-  } else {
-    return 0UL;           // No FPU
-  }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################  Cache functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_CacheFunctions Cache Functions
-    \brief      Functions that configure Instruction and Data cache.
-    @{
- */
-
-/* Cache Size ID Register Macros */
-#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
-#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
-#define CCSIDR_LSSHIFT(x)      (((x) & SCB_CCSIDR_LINESIZE_Msk     ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )
-
-
-/** \brief Enable I-Cache
-
-    The function turns on I-Cache
-  */
-__STATIC_INLINE void SCB_EnableICache (void)
-{
-  #if (__ICACHE_PRESENT == 1)
-    __DSB();
-    __ISB();
-    SCB->ICIALLU = 0UL;                     // invalidate I-Cache
-    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  // enable I-Cache
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/** \brief Disable I-Cache
-
-    The function turns off I-Cache
-  */
-__STATIC_INLINE void SCB_DisableICache (void)
-{
-  #if (__ICACHE_PRESENT == 1)
-    __DSB();
-    __ISB();
-    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  // disable I-Cache
-    SCB->ICIALLU = 0UL;                     // invalidate I-Cache
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/** \brief Invalidate I-Cache
-
-    The function invalidates I-Cache
-  */
-__STATIC_INLINE void SCB_InvalidateICache (void)
-{
-  #if (__ICACHE_PRESENT == 1)
-    __DSB();
-    __ISB();
-    SCB->ICIALLU = 0UL;
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/** \brief Enable D-Cache
-
-    The function turns on D-Cache
-  */
-__STATIC_INLINE void SCB_EnableDCache (void)
-{
-  #if (__DCACHE_PRESENT == 1)
-    uint32_t ccsidr, sshift, wshift, sw;
-    uint32_t sets, ways;
-
-    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
-    ccsidr  = SCB->CCSIDR;
-    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
-    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
-    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
-    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
-
-    __DSB();
-
-    do {                                   // invalidate D-Cache
-         uint32_t tmpways = ways;
-         do {
-              sw = ((tmpways << wshift) | (sets << sshift));
-              SCB->DCISW = sw;
-            } while(tmpways--);
-        } while(sets--);
-    __DSB();
-
-    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;   // enable D-Cache
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/** \brief Disable D-Cache
-
-    The function turns off D-Cache
-  */
-__STATIC_INLINE void SCB_DisableDCache (void)
-{
-  #if (__DCACHE_PRESENT == 1)
-    uint32_t ccsidr, sshift, wshift, sw;
-    uint32_t sets, ways;
-
-    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
-    ccsidr  = SCB->CCSIDR;
-    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
-    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
-    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
-    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
-
-    __DSB();
-
-    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  // disable D-Cache
-
-    do {                                    // clean & invalidate D-Cache
-         uint32_t tmpways = ways;
-         do {
-              sw = ((tmpways << wshift) | (sets << sshift));
-              SCB->DCCISW = sw;
-            } while(tmpways--);
-        } while(sets--);
-
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/** \brief Invalidate D-Cache
-
-    The function invalidates D-Cache
-  */
-__STATIC_INLINE void SCB_InvalidateDCache (void)
-{
-  #if (__DCACHE_PRESENT == 1)
-    uint32_t ccsidr, sshift, wshift, sw;
-    uint32_t sets, ways;
-
-    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
-    ccsidr  = SCB->CCSIDR;
-    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
-    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
-    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
-    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
-
-    __DSB();
-
-    do {                                    // invalidate D-Cache
-         uint32_t tmpways = ways;
-         do {
-              sw = ((tmpways << wshift) | (sets << sshift));
-              SCB->DCISW = sw;
-            } while(tmpways--);
-        } while(sets--);
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/** \brief Clean D-Cache
-
-    The function cleans D-Cache
-  */
-__STATIC_INLINE void SCB_CleanDCache (void)
-{
-  #if (__DCACHE_PRESENT == 1)
-    uint32_t ccsidr, sshift, wshift, sw;
-    uint32_t sets, ways;
-
-    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
-    ccsidr  = SCB->CCSIDR;
-    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
-    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
-    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
-    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
-
-    __DSB();
-
-    do {                                    // clean D-Cache
-         uint32_t tmpways = ways;
-         do {
-              sw = ((tmpways << wshift) | (sets << sshift));
-              SCB->DCCSW = sw;
-            } while(tmpways--);
-        } while(sets--);
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/** \brief Clean & Invalidate D-Cache
-
-    The function cleans and Invalidates D-Cache
-  */
-__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
-{
-  #if (__DCACHE_PRESENT == 1)
-    uint32_t ccsidr, sshift, wshift, sw;
-    uint32_t sets, ways;
-
-    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
-    ccsidr  = SCB->CCSIDR;
-    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
-    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
-    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
-    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
-
-    __DSB();
-
-    do {                                    // clean & invalidate D-Cache
-         uint32_t tmpways = ways;
-         do {
-              sw = ((tmpways << wshift) | (sets << sshift));
-              SCB->DCCISW = sw;
-            } while(tmpways--);
-        } while(sets--);
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \fn          void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
-  \brief       D-Cache Invalidate by address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
-  #if (__DCACHE_PRESENT == 1)
-    int32_t  op_size = dsize;
-    uint32_t op_addr = (uint32_t)addr;
-    uint32_t linesize = 32UL;               // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
-
-    __DSB();
-
-    while (op_size > 0) {
-      SCB->DCIMVAC = op_addr;
-      op_addr +=          linesize;
-      op_size -= (int32_t)linesize;
-    }
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \fn          void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
-  \brief       D-Cache Clean by address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
-  #if (__DCACHE_PRESENT == 1)
-    int32_t  op_size = dsize;
-    uint32_t op_addr = (uint32_t) addr;
-    uint32_t linesize = 32UL;               // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
-
-    __DSB();
-
-    while (op_size > 0) {
-      SCB->DCCMVAC = op_addr;
-      op_addr +=          linesize;
-      op_size -= (int32_t)linesize;
-    }
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \fn          void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
-  \brief       D-Cache Clean and Invalidate by address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
-  #if (__DCACHE_PRESENT == 1)
-    int32_t  op_size = dsize;
-    uint32_t op_addr = (uint32_t) addr;
-    uint32_t linesize = 32UL;               // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
-
-    __DSB();
-
-    while (op_size > 0) {
-      SCB->DCCIMVAC = op_addr;
-      op_addr +=          linesize;
-      op_size -= (int32_t)linesize;
-    }
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/*@} end of CMSIS_Core_CacheFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief  ITM Send Character
-
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
-    \param [in]     ch  Character to transmit.
-
-    \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
-    ITM->PORT[0].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/core_cmFunc.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,664 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmFunc.h
- * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief  Set Base Priority with condition
-
-    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-    or the new value increases the BASEPRI priority level.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  register uint32_t __regBasePriMax      __ASM("basepri_max");
-  __regBasePriMax = (basePri & 0xff);
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
-}
-
-
-/** \brief  Set Base Priority with condition
-
-    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-	or the new value increases the BASEPRI priority level.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
-{
-  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  uint32_t result;
-
-  /* Empty asm statement works as a scheduling barrier */
-  __ASM volatile ("");
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  __ASM volatile ("");
-  return(result);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  /* Empty asm statement works as a scheduling barrier */
-  __ASM volatile ("");
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
-  __ASM volatile ("");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include <cmsis_csm.h>
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-#endif /* __CORE_CMFUNC_H */

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/core_cmInstr.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,916 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmInstr.h
- * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-#define __ISB() do {\
-                   __schedule_barrier();\
-                   __isb(0xF);\
-                   __schedule_barrier();\
-                } while (0)
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() do {\
-                   __schedule_barrier();\
-                   __dsb(0xF);\
-                   __schedule_barrier();\
-                } while (0)
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-#define __DMB() do {\
-                   __schedule_barrier();\
-                   __dmb(0xF);\
-                   __schedule_barrier();\
-                } while (0)
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-#define __ROR                             __ror
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __breakpoint(value)
-
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-  #define __RBIT                          __rbit
-#else
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
-
-  result = value;                      // r will be reversed bits of v; first get LSB of v
-  for (value >>= 1; value; value >>= 1)
-  {
-    result <<= 1;
-    result |= value & 1;
-    s--;
-  }
-  result <<= s;                       // shift when v's highest bits are zero
-  return(result);
-}
-#endif
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function executes a exclusive LDR instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function executes a exclusive LDR instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function executes a exclusive LDR instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function executes a exclusive STR instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXB(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function executes a exclusive STR instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXH(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function executes a exclusive STR instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX                           __clrex
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/** \brief  Rotate Right with Extend (32 bit)
-
-    This function moves each bit of a bitstring right by one bit.
-    The carry input is shifted in at the left end of the bitstring.
-
-    \param [in]    value  Value to rotate
-    \return               Rotated value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
-{
-  rrx r0, r0
-  bx lr
-}
-#endif
-
-
-/** \brief  LDRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged LDRT instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
-
-
-/** \brief  LDRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged LDRT instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
-
-
-/** \brief  LDRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged LDRT instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
-
-
-/** \brief  STRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged STRT instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-#define __STRBT(value, ptr)               __strt(value, ptr)
-
-
-/** \brief  STRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged STRT instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-#define __STRHT(value, ptr)               __strt(value, ptr)
-
-
-/** \brief  STRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged STRT instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-#define __STRT(value, ptr)                __strt(value, ptr)
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constrant "l"
- * Otherwise, use general registers, specified by constrant "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
-{
-  __ASM volatile ("nop");
-}
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
-{
-  __ASM volatile ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
-{
-  __ASM volatile ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
-{
-  __ASM volatile ("sev");
-}
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
-{
-  __ASM volatile ("isb 0xF":::"memory");
-}
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
-{
-  __ASM volatile ("dsb 0xF":::"memory");
-}
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
-{
-  __ASM volatile ("dmb 0xF":::"memory");
-}
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
-  return __builtin_bswap32(value);
-#else
-  uint32_t result;
-
-  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-#endif
-}
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-  return (short)__builtin_bswap16(value);
-#else
-  uint32_t result;
-
-  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-#endif
-}
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-  return (op1 >> op2) | (op1 << (32 - op2));
-}
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
-  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
-
-  result = value;                      // r will be reversed bits of v; first get LSB of v
-  for (value >>= 1; value; value >>= 1)
-  {
-    result <<= 1;
-    result |= value & 1;
-    s--;
-  }
-  result <<= s;                       // shift when v's highest bits are zero
-#endif
-  return(result);
-}
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ             __builtin_clz
-
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function executes a exclusive LDR instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function executes a exclusive LDR instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function executes a exclusive LDR instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function executes a exclusive STR instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function executes a exclusive STR instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function executes a exclusive STR instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex" ::: "memory");
-}
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Rotate Right with Extend (32 bit)
-
-    This function moves each bit of a bitstring right by one bit.
-    The carry input is shifted in at the left end of the bitstring.
-
-    \param [in]    value  Value to rotate
-    \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/** \brief  LDRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged LDRT instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged LDRT instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged LDRT instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
-}
-
-
-/** \brief  STRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged STRT instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
-{
-   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/** \brief  STRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged STRT instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
-{
-   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/** \brief  STRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged STRT instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
-{
-   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include <cmsis_csm.h>
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/core_cmSecureAccess.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,201 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmSecureAccess.h
- * @brief    CMSIS Cortex-M Core Secure Access Header File
- * @version  XXX
- * @date     10. June 2016
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2016 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CM_SECURE_ACCESS_H
-#define __CORE_CM_SECURE_ACCESS_H
-
-
-/* ###########################  Core Secure Access  ########################### */
-
-#ifdef FEATURE_UVISOR
-#include "uvisor-lib.h"
-
-/* Secure uVisor implementation. */
-
-/** Set the value at the target address.
- *
- * Equivalent to: `*address = value`.
- * @param address[in]  Target address
- * @param value[in]    Value to write at the address location.
- */
-#define SECURE_WRITE(address, value) \
-    uvisor_write(main, UVISOR_RGW_SHARED, address, value, UVISOR_RGW_OP_WRITE, 0xFFFFFFFFUL)
-
-/** Get the value at the target address.
- *
- * @param address[in]  Target address
- * @returns The value `*address`.
- */
-#define SECURE_READ(address) \
-    uvisor_read(main, UVISOR_RGW_SHARED, address, UVISOR_RGW_OP_READ, 0xFFFFFFFFUL)
-
-/** Get the selected bits at the target address.
- *
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- * @returns The value `*address & mask`.
- */
-#define SECURE_BITS_GET(address, mask) \
-    UVISOR_BITS_GET(main, UVISOR_RGW_SHARED, address, mask)
-
-/** Check the selected bits at the target address.
- *
- * @param address[in]  Address at which to check the bits
- * @param mask[in]     Bits to select out of the target address
- * @returns The value `((*address & mask) == mask)`.
- */
-#define SECURE_BITS_CHECK(address, mask) \
-    UVISOR_BITS_CHECK(main, UVISOR_RGW_SHARED, address, mask)
-
-/** Set the selected bits to 1 at the target address.
- *
- * Equivalent to: `*address |= mask`.
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- */
-#define SECURE_BITS_SET(address, mask) \
-    UVISOR_BITS_SET(main, UVISOR_RGW_SHARED, address, mask)
-
-/** Clear the selected bits at the target address.
- *
- * Equivalent to: `*address &= ~mask`.
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- */
-#define SECURE_BITS_CLEAR(address, mask) \
-    UVISOR_BITS_CLEAR(main, UVISOR_RGW_SHARED, address, mask)
-
-/** Set the selected bits at the target address to the given value.
- *
- * Equivalent to: `*address = (*address & ~mask) | (value & mask)`.
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- * @param value[in]    Value to write at the address location. Note: The value
- *                     must be already shifted to the correct bit position
- */
-#define SECURE_BITS_SET_VALUE(address, mask, value) \
-    UVISOR_BITS_SET_VALUE(main, UVISOR_RGW_SHARED, address, mask, value)
-
-/** Toggle the selected bits at the target address.
- *
- * Equivalent to: `*address ^= mask`.
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- */
-#define SECURE_BITS_TOGGLE(address, mask) \
-    UVISOR_BITS_TOGGLE(main, UVISOR_RGW_SHARED, address, mask)
-
-#else
-
-/* Insecure fallback implementation. */
-
-/** Set the value at the target address.
- *
- * Equivalent to: `*address = value`.
- * @param address[in]  Target address
- * @param value[in]    Value to write at the address location.
- */
-#define SECURE_WRITE(address, value) \
-    *(address) = (value)
-
-/** Get the value at the target address.
- *
- * @param address[in]  Target address
- * @returns The value `*address`.
- */
-#define SECURE_READ(address) \
-    (*(address))
-
-/** Get the selected bits at the target address.
- *
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- * @returns The value `*address & mask`.
- */
-#define SECURE_BITS_GET(address, mask) \
-    (*(address) & (mask))
-
-/** Check the selected bits at the target address.
- *
- * @param address[in]  Address at which to check the bits
- * @param mask[in]     Bits to select out of the target address
- * @returns The value `((*address & mask) == mask)`.
- */
-#define SECURE_BITS_CHECK(address, mask) \
-    ((*(address) & (mask)) == (mask))
-
-/** Set the selected bits to 1 at the target address.
- *
- * Equivalent to: `*address |= mask`.
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- */
-#define SECURE_BITS_SET(address, mask) \
-    *(address) |= (mask)
-
-/** Clear the selected bits at the target address.
- *
- * Equivalent to: `*address &= ~mask`.
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- */
-#define SECURE_BITS_CLEAR(address, mask) \
-    *(address) &= ~(mask)
-
-/** Set the selected bits at the target address to the given value.
- *
- * Equivalent to: `*address = (*address & ~mask) | (value & mask)`.
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- * @param value[in]    Value to write at the address location. Note: The value
- *                     must be already shifted to the correct bit position
- */
-#define SECURE_BITS_SET_VALUE(address, mask, value) \
-    *(address) = (*(address) & ~(mask)) | ((value) & (mask))
-
-/** Toggle the selected bits at the target address.
- *
- * Equivalent to: `*address ^= mask`.
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- */
-#define SECURE_BITS_TOGGLE(address, mask) \
-    *(address) ^= (mask)
-
-#endif
-
-#endif /* __CORE_CM_SECURE_ACCESS_H */

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/core_cmSimd.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,697 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmSimd.h
- * @brief    CMSIS Cortex-M SIMD Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CMSIMD_H
-#define __CORE_CMSIMD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
-                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else \
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/* not yet supported */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include <cmsis_csm.h>
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CMSIMD_H */

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/core_sc000.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,864 +0,0 @@
-/**************************************************************************//**
- * @file     core_sc000.h
- * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_SC000_H_GENERIC
-#define __CORE_SC000_H_GENERIC
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup SC000
-  @{
- */
-
-/*  CMSIS SC000 definitions */
-#define __SC000_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */
-#define __SC000_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */
-#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
-                                      __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
-
-#define __CORTEX_SC                 (000)                                       /*!< Cortex secure core             */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI__VFP_SUPPORT____
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC000_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC000_H_DEPENDANT
-#define __CORE_SC000_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __SC000_REV
-    #define __SC000_REV             0x0000
-    #warning "__SC000_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group SC000 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved                           */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED0[1];
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-       uint32_t RESERVED1[154];
-  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Control Register                    */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
-} SCnSCB_Type;
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
-                are only accessible over DAP and not via processor. Therefore
-                they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of SC000 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if((int32_t)(IRQn) < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if((int32_t)(IRQn) < 0) {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
-  }
-  else {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1) { __NOP(); }                                        /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);}      /* Reload value impossible */
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC000_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/core_sc300.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1675 +0,0 @@
-/**************************************************************************//**
- * @file     core_sc300.h
- * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_SC300_H_GENERIC
-#define __CORE_SC300_H_GENERIC
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup SC3000
-  @{
- */
-
-/*  CMSIS SC300 definitions */
-#define __SC300_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */
-#define __SC300_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */
-#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \
-                                      __SC300_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
-
-#define __CORTEX_SC                 (300)                                     /*!< Cortex secure core             */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI__VFP_SUPPORT____
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC300_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC300_H_DEPENDANT
-#define __CORE_SC300_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __SC300_REV
-    #define __SC300_REV               0x0000
-    #warning "__SC300_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group SC300 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[5];
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-       uint32_t RESERVED1[129];
-  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Control Register                    */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-       uint32_t RESERVED1[1];
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __O  union
-  {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];
-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];
-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-       uint32_t RESERVED0[1];
-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-       uint32_t RESERVED1[1];
-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-       uint32_t RESERVED2[1];
-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/** \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-       uint32_t RESERVED1[55];
-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-       uint32_t RESERVED2[131];
-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-       uint32_t RESERVED3[759];
-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-       uint32_t RESERVED4[1];
-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-       uint32_t RESERVED5[39];
-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-       uint32_t RESERVED7[8];
-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/** \brief  Set Priority Grouping
-
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if((int32_t)IRQn < 0) {
-    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if((int32_t)IRQn < 0) {
-    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
-  }
-  else {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-  while(1) { __NOP(); }                                             /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief  ITM Send Character
-
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
-    \param [in]     ch  Character to transmit.
-
-    \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
-    ITM->PORT[0].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC300_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/hal_tick.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,60 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    hal_tick.h
-  * @author  MCD Application Team
-  * @brief   Initialization of HAL tick
-  ******************************************************************************  
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
-#ifndef __HAL_TICK_H
-#define __HAL_TICK_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "stm32f1xx.h"
-#include "cmsis_nvic.h"
-   
-#define TIM_MST      TIM4
-#define TIM_MST_IRQ  TIM4_IRQn
-#define TIM_MST_RCC  __TIM4_CLK_ENABLE()
-
-#define TIM_MST_RESET_ON   __TIM4_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM4_RELEASE_RESET()
-
-#define HAL_TICK_DELAY (1000) // 1 ms
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __HAL_TICK_H
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32_hal_legacy.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,3123 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_hal_legacy.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   This file contains aliases definition for the STM32Cube HAL constants 
-  *          macros and functions maintained for legacy purpose.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_HAL_LEGACY
-#define __STM32_HAL_LEGACY
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
-#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
-#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
-#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
-#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
-#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
-#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
-#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
-#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
-#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
-#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
-#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
-#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
-#define REGULAR_GROUP                   ADC_REGULAR_GROUP
-#define INJECTED_GROUP                  ADC_INJECTED_GROUP
-#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
-#define AWD_EVENT                       ADC_AWD_EVENT
-#define AWD1_EVENT                      ADC_AWD1_EVENT
-#define AWD2_EVENT                      ADC_AWD2_EVENT
-#define AWD3_EVENT                      ADC_AWD3_EVENT
-#define OVR_EVENT                       ADC_OVR_EVENT
-#define JQOVF_EVENT                     ADC_JQOVF_EVENT
-#define ALL_CHANNELS                    ADC_ALL_CHANNELS
-#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
-#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
-#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
-#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
-#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
-#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
-#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
-#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
-#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
-#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO 
-#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2 
-#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO 
-#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4  
-#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
-#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
-#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
-#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
-#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
-#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
-#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
-#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
-
-#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
-#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
-#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
-#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
-#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
-#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
-#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1 
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
-  * @{
-  */ 
-  
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 
-
-/**
-  * @}
-  */   
-   
-/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
-#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
-#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
-#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
-#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
-#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
-#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
-#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
-#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
-#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
-#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32L0) || defined(STM32L4)
-#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
-
-#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
-#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
-#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
- 
-#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
-#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
-#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
-#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
-#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
-#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
-#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
-#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
-#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
-
-#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
-#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
-
-/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
-/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
-#if defined(COMP_CSR_LOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
-#elif defined(COMP_CSR_COMP1LOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
-#elif defined(COMP_CSR_COMPxLOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
-#endif
-
-#if defined(STM32L4)
-#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
-#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
-#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
-#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
-#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
-#endif
-
-#if defined(STM32L0)
-#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
-#else
-#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
-#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
-#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
-#endif
-
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-  
-#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
-#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
-#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
-#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
-#define DAC_WAVE_NONE                                   ((uint32_t)0x00000000U)
-#define DAC_WAVE_NOISE                                  ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVE_TRIANGLE                               ((uint32_t)DAC_CR_WAVE1_1)                           
-#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
-#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
-#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2       
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4 
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5   
-#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4       
-#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2       
-#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
-#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7      
-#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67  
-#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67 
-#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32  
-#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76   
-#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6     
-#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7      
-#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6    
-  
-#define IS_HAL_REMAPDMA                          IS_DMA_REMAP  
-#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
-#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
-  
-  
-  
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
-  * @{
-  */
-  
-#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
-#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
-#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
-#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
-#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
-#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
-#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
-#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
-#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
-#define OBEX_PCROP                    OPTIONBYTE_PCROP
-#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
-#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
-#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
-#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
-#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
-#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
-#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
-#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
-#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
-#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
-#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
-#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
-#define PAGESIZE                      FLASH_PAGE_SIZE
-#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
-#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
-#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
-#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
-#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
-#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
-#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
-#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
-#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
-#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
-#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
-#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
-#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
-#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
-#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
-#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
-#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
-#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
-#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
-#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
-#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
-#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
-#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
-#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
-#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
-#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
-#define OB_WDG_SW                     OB_IWDG_SW
-#define OB_WDG_HW                     OB_IWDG_HW
-#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
-#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
-#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
-#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
-#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
-#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
-#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
-#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-  
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
-#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
-#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
-/**
-  * @}
-  */
-  
-
-/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
-  * @{
-  */
-#if defined(STM32L4) || defined(STM32F7)
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
-#else
-#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
-#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
-#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
-#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-  
-#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
-/**
-  * @}
-  */
-
-/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
-#define GET_GPIO_INDEX                            GPIO_GET_INDEX
-
-#if defined(STM32F4)
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
-#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
-#endif
-
-#if defined(STM32F7)
-#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32L4)
-#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
-#endif
-
-#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
-#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
-#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
-
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
-#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW     
-#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM     
-#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH     
-#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH       
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
-
-#if defined(STM32L1) 
- #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW     
- #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM     
- #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH     
- #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH     
-#endif /* STM32L1 */
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
- #define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
- #define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
- #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
-#endif /* STM32F0 || STM32F3 || STM32F1 */
-
-#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
-/**
-  * @}
-  */
-
-/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
-   
-#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
-#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
-#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
-#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
-#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
-#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
-#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
-#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
-#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
-#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
-#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
-#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
-#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
-#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
-#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
-#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
-#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
-#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
-#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
-#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
-
-#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
-#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
-#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
-
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS        
-
-/* The following 3 definition have also been present in a temporary version of lptim.h */
-/* They need to be renamed also to the right name, just in case */
-#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
-#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
-#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
-#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
-
-#define NAND_AddressTypedef             NAND_AddressTypeDef
-
-#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
-#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
-#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
-#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
-#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
-/**
-  * @}
-  */
-   
-/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
-#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
-#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
-#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
-#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
-
-#define __NOR_WRITE                    NOR_WRITE
-#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
-/**
-  * @}
-  */
-
-/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
-#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
-#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
-#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
-                                              
-#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
-#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
-#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3   
-
-#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
-#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
-
-#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
-#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
-
-#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
-#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1    
-
-#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
-                                                                      
-#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO             
-#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0            
-#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1          
-                                                        
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
-#if defined(STM32F7) 
-  #define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-/* Compact Flash-ATA registers description */
-#define CF_DATA                       ATA_DATA                
-#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT        
-#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER       
-#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW        
-#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH       
-#define CF_CARD_HEAD                  ATA_CARD_HEAD           
-#define CF_STATUS_CMD                 ATA_STATUS_CMD          
-#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
-#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA    
-
-/* Compact Flash-ATA commands */
-#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD 
-#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
-#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
-#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
-
-#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
-#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
-#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
-#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
-#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-  
-#define FORMAT_BIN                  RTC_FORMAT_BIN
-#define FORMAT_BCD                  RTC_FORMAT_BCD
-
-#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
-#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
-
-#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE 
-#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE 
-#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE 
-#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE 
-#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT 
-#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT 
-
-#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
-
-#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
-#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
-#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
-
-#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 
-#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1 
-#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
-
-/**
-  * @}
-  */
-
-  
-/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
-#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
-
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-
-#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
-#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
-
-#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
-#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
-/**
-  * @}
-  */
-
-  
-/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
-#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
-#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
-#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
-#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
-#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
-#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
-#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
-#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
-#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
-#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
-#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
-
-#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
-#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
-
-#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
-#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
-#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
-  
-#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
-#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
-#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
-#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
-#define TIM_DMABase_SR                   TIM_DMABASE_SR
-#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
-#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
-#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
-#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
-#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
-#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
-#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
-#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
-#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
-#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
-#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
-#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
-#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
-#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
-#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
-#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
-#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
-#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
-#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
-#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
-#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
-#define TIM_DMABase_OR                   TIM_DMABASE_OR
-
-#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
-#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
-#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
-#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
-#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
-#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
-#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
-#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
-#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
-
-#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
-#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
-#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
-#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
-#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
-#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
-#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
-#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
-#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
-#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
-#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
-#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
-#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
-#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
-#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
-#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
-#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
-#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
-#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
-/**
-  * @}
-  */
-
-/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
-#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
-
-#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
-#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
-
-#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
-#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
-#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
-#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
-
-#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
-#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
-#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
-#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
-
-#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
-#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
-
-/**
-  * @}
-  */
-
-  
-/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
-#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
-
-#define USARTNACK_ENABLED               USART_NACK_ENABLE
-#define USARTNACK_DISABLED              USART_NACK_DISABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CFR_BASE                    WWDG_CFR_BASE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
-#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
-#define CAN_IT_RQCP0                CAN_IT_TME
-#define CAN_IT_RQCP1                CAN_IT_TME
-#define CAN_IT_RQCP2                CAN_IT_TME
-#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
-#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
-#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
-#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
-#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define VLAN_TAG                ETH_VLAN_TAG
-#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
-#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
-#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
-#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
-#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
-#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
-#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
-
-#define ETH_MMCCR              ((uint32_t)0x00000100U)  
-#define ETH_MMCRIR             ((uint32_t)0x00000104U)  
-#define ETH_MMCTIR             ((uint32_t)0x00000108U)  
-#define ETH_MMCRIMR            ((uint32_t)0x0000010CU)  
-#define ETH_MMCTIMR            ((uint32_t)0x00000110U)  
-#define ETH_MMCTGFSCCR         ((uint32_t)0x0000014CU)  
-#define ETH_MMCTGFMSCCR        ((uint32_t)0x00000150U)  
-#define ETH_MMCTGFCR           ((uint32_t)0x00000168U)  
-#define ETH_MMCRFCECR          ((uint32_t)0x00000194U)  
-#define ETH_MMCRFAECR          ((uint32_t)0x00000198U)  
-#define ETH_MMCRGUFCR          ((uint32_t)0x000001C4U)
- 
-#define ETH_MAC_TXFIFO_FULL          ((uint32_t)0x02000000)  /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY      ((uint32_t)0x01000000)  /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE  ((uint32_t)0x00400000)  /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE     ((uint32_t)0x00000000)  /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ     ((uint32_t)0x00100000)  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING  ((uint32_t)0x00200000)  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING  ((uint32_t)0x00300000)  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE     ((uint32_t)0x00080000)  /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            ((uint32_t)0x00000000)  /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         ((uint32_t)0x00020000)  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   ((uint32_t)0x00040000)  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    ((uint32_t)0x00060000)  /* MAC transmit frame controller: Transferring input frame for transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE      ((uint32_t)0x00010000)  /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY             ((uint32_t)0x00000000)  /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD   ((uint32_t)0x00000100)  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD   ((uint32_t)0x00000200)  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
-#define ETH_MAC_RXFIFO_FULL              ((uint32_t)0x00000300)  /* Rx FIFO fill level: full */
-#if defined(STM32F1)
-#else
-#define ETH_MAC_READCONTROLLER_IDLE               ((uint32_t)0x00000000)  /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA       ((uint32_t)0x00000020)  /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS     ((uint32_t)0x00000040)  /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#endif
-#define ETH_MAC_READCONTROLLER_FLUSHING           ((uint32_t)0x00000060)  /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE     ((uint32_t)0x00000010)  /* Rx FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE    ((uint32_t)0x00000000)  /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE  ((uint32_t)0x00000002)  /* MAC small FIFO read controller active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004)  /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE    ((uint32_t)0x00000006)  /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   ((uint32_t)0x00000001)  /* MAC MII receive protocol engine active */
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
-#define DCMI_IT_OVF             DCMI_IT_OVR
-#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
-#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
-
-#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
-#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
-#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
-
-/**
-  * @}
-  */  
-  
-#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
-    defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
-#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888  
-#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565  
-#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
-#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
-
-#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
-#define CM_RGB888               DMA2D_INPUT_RGB888  
-#define CM_RGB565               DMA2D_INPUT_RGB565  
-#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
-#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
-#define CM_L8                   DMA2D_INPUT_L8      
-#define CM_AL44                 DMA2D_INPUT_AL44    
-#define CM_AL88                 DMA2D_INPUT_AL88    
-#define CM_L4                   DMA2D_INPUT_L4      
-#define CM_A8                   DMA2D_INPUT_A8      
-#define CM_A4                   DMA2D_INPUT_A4      
-/**
-  * @}
-  */    
-#endif  /* STM32L4xx ||  STM32F7*/
-
-/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-  
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
-/**
-  * @}
-  */  
-
-/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
-  * @{
-  */ 
-#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
-#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
-#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
-#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
-#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
-#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
-
-/*HASH Algorithm Selection*/
-
-#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1 
-#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
-#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
-#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
-
-#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH 
-#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
-
-#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
-#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
-#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
-#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
-#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
-#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
-#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
-#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
-#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
-#if defined(STM32L0)
-#else
-#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
-#endif
-#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
-#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
-#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
-#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
-#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
-#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
-#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
-
- /**
-  * @}
-  */
-
-/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
-#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
-#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
-#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
-
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
- /**
-  * @}
-  */
-
-/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
-  * @{
-  */
-#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
-#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
-#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
-#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
-#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
-#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
-#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
-#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
-#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
-#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
-#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
-#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
-#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
-#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
-#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
-#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
-
-#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
-#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
-#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
-#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
-#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
-#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
-#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
-
-#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
-#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
-
-#define DBP_BitNumber                                 DBP_BIT_NUMBER
-#define PVDE_BitNumber                                PVDE_BIT_NUMBER
-#define PMODE_BitNumber                               PMODE_BIT_NUMBER
-#define EWUP_BitNumber                                EWUP_BIT_NUMBER
-#define FPDS_BitNumber                                FPDS_BIT_NUMBER
-#define ODEN_BitNumber                                ODEN_BIT_NUMBER
-#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
-#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
-#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
-#define BRE_BitNumber                                 BRE_BIT_NUMBER
-
-#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
- 
- /**
-  * @}
-  */  
-  
-/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
-#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback         
-#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback   
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
-/**
-  * @}
-  */  
-
-/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
-#define HAL_TIM_DMAError                                TIM_DMAError
-#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
-#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
-/**
-  * @}
-  */
-   
-/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
-  * @{
-  */ 
-#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
-  * @{
-  */ 
-#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
-/**
-  * @}
-  */  
-   
-  
-/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-  
-/**
-  * @}
-  */
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define AES_IT_CC                      CRYP_IT_CC
-#define AES_IT_ERR                     CRYP_IT_ERR
-#define AES_FLAG_CCF                   CRYP_FLAG_CCF
-/**
-  * @}
-  */  
-  
-/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
-#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
-#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
-#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
-#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
-#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 
-#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
-#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
-#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
-#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
-#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
-#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
-#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
-
-#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
-#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
-#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
-#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
-#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
-
-/**
-  * @}
-  */
-
-   
-/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
-#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
-#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
-#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
-#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
-#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
-#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
-#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
-#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
-#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
-
-#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
-#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
-#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
-#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
-#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
-#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
-#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
-#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
-#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
-#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
-#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
-#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
-#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
-#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
-#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
-#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
-#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
-
-#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
-#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
-#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
-#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
-#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
-#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
-#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
-
-#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
-#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
-#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
-#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
-#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
-#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
-#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
-#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
-
-#define __HAL_ADC_SQR1                                   ADC_SQR1
-#define __HAL_ADC_SMPR1                                  ADC_SMPR1
-#define __HAL_ADC_SMPR2                                  ADC_SMPR2
-#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
-#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
-#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
-#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
-#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
-#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
-#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
-#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
-#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR                                   ADC_JSQR
-
-#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
-#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
-#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
-#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
-#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
-#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
-#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
-#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
-#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
-#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
-
-/**
-  * @}
-  */
-   
-/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
-#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
-#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
-#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
-#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
-#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
-#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
-#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
-#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
-#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
-#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
-#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
-#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
-#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
-#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
-#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
-
-#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
-#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
-#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
-#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
-#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
-#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
-#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
-#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
-#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
-#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
-#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
-#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
-#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
-#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
-
-
-#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
-#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
-#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
-#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
-#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
-#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
-#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
-#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
-#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
-#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
-#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
-#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
-#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
-#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
-#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
-#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined(STM32F3)
-#define COMP_START                                       __HAL_COMP_ENABLE
-#define COMP_STOP                                        __HAL_COMP_DISABLE
-#define COMP_LOCK                                        __HAL_COMP_LOCK
-   
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F302xE) || defined(STM32F302xC)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F373xC) ||defined(STM32F378xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-# endif
-#else
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-#endif
-
-#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
-
-#if defined(STM32L0) || defined(STM32L4)
-/* Note: On these STM32 families, the only argument of this macro             */
-/*       is COMP_FLAG_LOCK.                                                   */
-/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
-/*       argument.                                                            */
-#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
-#endif
-/**
-  * @}
-  */
-
-#if defined(STM32L0) || defined(STM32L4)
-/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-/**
-  * @}
-  */
-#endif
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
-                          ((WAVE) == DAC_WAVE_NOISE)|| \
-                          ((WAVE) == DAC_WAVE_TRIANGLE))
-  
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_WRPAREA          IS_OB_WRPAREA
-#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
-#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
-#define IS_TYPEERASE        IS_FLASH_TYPEERASE
-#define IS_NBSECTORS        IS_FLASH_NBSECTORS
-#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
-  * @{
-  */
-  
-#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
-#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
-#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
-#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
-#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
-#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
-#define __HAL_I2C_SPEED                 I2C_SPEED
-#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
-#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
-#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
-#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
-#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
-#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
-#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
-#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
-  * @{
-  */
-  
-#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
-#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
-  * @{
-  */
-  
-#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
-#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
-
-#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
-#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
-#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
-#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
-
-#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE                  
-
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
-#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
-#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
-
-/**
-  * @}
-  */
-  
-  
-/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
-#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
-#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
-#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
-#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
-#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
-#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
-#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
-#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
-#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
-#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
-#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
-#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
-#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
-#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
-#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
-#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
-#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
-#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
-#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
-#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
-#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
-
-#if defined (STM32F4)
-#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
-#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()   
-#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
-#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
-#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
-#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
-#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
-#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG 
-#endif /* STM32F4 */
-/**   
-  * @}
-  */  
-  
-  
-/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
-  * @{
-  */
-  
-#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
-#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
-
-#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
-
-#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
-#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
-#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
-#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
-#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
-#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE        __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE         __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET        __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET      __HAL_RCC_ADC1_RELEASE_RESET
-#define __ADC1_CLK_SLEEP_ENABLE   __HAL_RCC_ADC1_CLK_SLEEP_ENABLE  
-#define __ADC1_CLK_SLEEP_DISABLE  __HAL_RCC_ADC1_CLK_SLEEP_DISABLE  
-#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
-#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
-#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
-#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
-#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
-#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
-#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
-#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
-#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
-#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
-#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
-#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
-#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
-#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
-#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
-#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
-#define __CRYP_FORCE_RESET  __HAL_RCC_CRYP_FORCE_RESET
-#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
-#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
-#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
-#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
-#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
-#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
-#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
-#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
-#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
-#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
-#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
-#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
-#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
-#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
-#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
-#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
-#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
-#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
-#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
-#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
-#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
-#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
-#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
-#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
-#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
-#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
-#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
-#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
-#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
-#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
-#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
-#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
-#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
-#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
-#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
-#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
-#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
-#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
-#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
-#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
-#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
-#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
-#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
-#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
-#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
-#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
-#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
-#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
-#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
-#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
-#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
-#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
-#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
-#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
-#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
-#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
-#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
-#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
-#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
-#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
-#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
-#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
-#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
-#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
-#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
-#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
-#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
-#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
-#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
-#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
-#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
-#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
-#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
-#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
-#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
-#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
-#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
-#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
-#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
-#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
-#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
-#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
-#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
-#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
-#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
-#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
-#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
-#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
-#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
-#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
-#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
-#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
-#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
-#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
-#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
-#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
-#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
-#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
-#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
-#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
-#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
-#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
-#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
-#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
-#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
-#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
-#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
-#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
-#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
-#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
-#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
-#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
-#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
-#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
-#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
-#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
-#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
-#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
-#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
-#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
-#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
-#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
-#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
-#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
-#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
-#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
-#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
-#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
-#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
-#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
-#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
-#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
-#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
-#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
-#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
-#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
-#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
-#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
-#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
-#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
-#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
-#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
-#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
-#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
-#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
-#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
-#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
-#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
-#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
-#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
-#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
-#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
-#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
-#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
-#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
-#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
-#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
-#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
-#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
-#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
-#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
-#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
-#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
-#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
-#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
-#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
-#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
-#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
-#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
-#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
-#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
-#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
-#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
-#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
-#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
-#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
-#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
-#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
-#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
-#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
-#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
-#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
-#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
-#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
-#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
-#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
-#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
-#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
-#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
-#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
-#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
-#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
-#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
-#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
-#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
-#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
-#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
-#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
-#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
-#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
-#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
-#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
-#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
-#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
-#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
-#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
-#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
-#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
-#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
-#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
-#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
-#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
-#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
-#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
-#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
-#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
-#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
-#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
-#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
-#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
-#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
-#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
-#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
-#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
-#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
-#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
-#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
-#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
-#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
-#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
-#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
-#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
-#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
-#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
-#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
-#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
-#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
-#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
-#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
-#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
-#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
-#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
-#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
-#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
-#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
-#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
-#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
-#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
-#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
-#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
-#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
-#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
-#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
-#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
-#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
-#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
-#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
-#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
-#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
-#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
-#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
-#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
-#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
-#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
-#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
-#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
-#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
-#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
-#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
-#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
-#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
-#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
-#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
-#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
-#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
-#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
-#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
-#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
-#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
-#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
-#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
-#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
-#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
-#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
-#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
-#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
-#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
-#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
-#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
-#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
-#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
-#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
-#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
-#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
-#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
-#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
-#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
-#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
-#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
-#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
-#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
-#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
-#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
-#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
-#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
-#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
-#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
-#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
-#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
-#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
-#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
-#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
-#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
-#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
-#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
-#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
-#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
-#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
-#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
-#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
-#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
-#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
-#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
-#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
-#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
-#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
-#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
-#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
-#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
-#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
-#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
-#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
-#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
-#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
-#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
-#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
-#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
-#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
-#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
-#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
-#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
-#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
-#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
-#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
-#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
-#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
-#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
-#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
-#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
-#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
-#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
-#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
-#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
-#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
-#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
-#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
-#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
-#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
-#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
-#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
-#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
-#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
-#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
-#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
-#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
-#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
-#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
-#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
-#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
-#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
-#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
-#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
-#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
-#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
-#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
-#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
-#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
-#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
-#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
-#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
-#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
-#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
-#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
-#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
-#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
-#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
-#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
-#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
-#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
-#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
-#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
-#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
-#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USART4_CLK_DISABLE        __HAL_RCC_USART4_CLK_DISABLE
-#define __USART4_CLK_ENABLE         __HAL_RCC_USART4_CLK_ENABLE
-#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_USART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_USART4_CLK_SLEEP_DISABLE 
-#define __USART4_FORCE_RESET        __HAL_RCC_USART4_FORCE_RESET
-#define __USART4_RELEASE_RESET      __HAL_RCC_USART4_RELEASE_RESET
-#define __USART5_CLK_DISABLE        __HAL_RCC_USART5_CLK_DISABLE
-#define __USART5_CLK_ENABLE         __HAL_RCC_USART5_CLK_ENABLE
-#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_USART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_USART5_CLK_SLEEP_DISABLE 
-#define __USART5_FORCE_RESET        __HAL_RCC_USART5_FORCE_RESET
-#define __USART5_RELEASE_RESET      __HAL_RCC_USART5_RELEASE_RESET
-#define __USART7_CLK_DISABLE        __HAL_RCC_USART7_CLK_DISABLE
-#define __USART7_CLK_ENABLE         __HAL_RCC_USART7_CLK_ENABLE
-#define __USART7_FORCE_RESET        __HAL_RCC_USART7_FORCE_RESET
-#define __USART7_RELEASE_RESET      __HAL_RCC_USART7_RELEASE_RESET
-#define __USART8_CLK_DISABLE        __HAL_RCC_USART8_CLK_DISABLE
-#define __USART8_CLK_ENABLE         __HAL_RCC_USART8_CLK_ENABLE
-#define __USART8_FORCE_RESET        __HAL_RCC_USART8_FORCE_RESET
-#define __USART8_RELEASE_RESET      __HAL_RCC_USART8_RELEASE_RESET
-#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
-#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
-#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
-#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
-#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
-#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
-#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
-#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
-#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
-#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
-#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
-#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
-#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
-#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
-#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
-#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
-#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
-#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
-#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
-#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
-#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
-#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
-#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
-#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
-#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
-#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
-#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
-#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
-#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
-#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
-#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
-#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
-#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
-#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
-
-#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
-#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
-#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
-#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE  
-#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
-#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE  
-#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
-#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE  
-#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
-#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE  
-#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
-#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
-#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE  
-#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
-#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
-#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
-#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
-#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
-#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE  
-#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
-#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
-#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
-#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
-#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
-#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE  
-#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
-#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
-#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
-#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
-#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
-#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE  
-#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
-#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
-#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
-#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
-#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE  
-#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE  
-#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
-#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE  
-#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
-#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE  
-#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
-#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE  
-#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
-#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE  
-#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
-#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE  
-#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
-#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
-#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
-#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE  
-#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
-#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE  
-#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
-#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
-#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
-#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
-#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
-#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE  
-#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
-#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
-#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
-#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
-#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
-#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE  
-#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
-#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
-#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
-#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
-#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
-#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE  
-#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
-#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
-#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
-#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
-#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
-#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE  
-#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
-#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
-#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
-#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
-#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE  
-#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
-#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE  
-#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
-#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
-#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
-#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
-#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
-#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE  
-#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
-#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
-#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
-#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
-#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
-#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE  
-#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
-#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
-#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
-#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
-#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
-#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE  
-#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET  
-#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
-#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET  
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED   
-#define __CRYP_FORCE_RESET             __HAL_RCC_CRYP_FORCE_RESET  
-#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE  
-#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE  
-#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE  
-#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE  
-#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE  
-#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
-#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
-#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE  
-#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
-#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
-#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE  
-#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
-#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
-#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
-#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
-#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
-
-/* alias define maintained for legacy */
-#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-
-#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
-#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
-#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
-#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
-#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
-#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
-#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
-#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
-#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
-#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
-#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
-#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
-#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
-#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
-#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
-#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
-#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
-#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
-#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
-#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
-
-#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
-#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
-#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
-#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
-#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
-#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
-#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
-#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
-#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
-#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
-#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
-#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
-#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
-#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
-#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
-#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
-#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
-#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
-#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
-#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
-
-#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
-#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
-#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
-#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
-#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
-#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
-#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
-#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
-#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
-#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
-#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
-#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
-#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
-#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
-#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
-#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
-#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
-#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
-#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
-#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
-#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
-#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
-#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
-#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
-#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
-#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
-#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
-#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
-#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
-#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
-#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
-#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
-#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
-#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
-#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
-#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
-#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
-#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
-#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
-#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
-#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
-#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
-#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
-#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
-#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
-#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
-#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
-#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
-#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
-#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
-#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
-#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
-#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
-#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
-#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
-#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
-#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
-#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
-#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
-#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
-#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
-#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
-#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
-#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
-#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
-#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
-#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
-#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
-#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
-#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
-#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
-#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
-#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
-#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
-#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
-#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
-#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
-#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
-#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
-#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
-#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
-#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
-#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
-#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
-#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
-#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
-#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
-#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
-#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
-#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
-#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
-#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
-#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
-#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
-#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
-#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
-#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
-#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
-#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
-#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
-#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
-#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
-#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
-#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
-#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
-#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
-#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
-#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
-#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
-#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
-#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
-#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
-#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
-#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
-#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
-#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
-
-#if defined(STM32F4)
-#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
-#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
-#define Sdmmc1ClockSelection               SdioClockSelection
-#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
-#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
-#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
-#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
-#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
-#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
-#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
-#define SdioClockSelection                 Sdmmc1ClockSelection
-#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
-#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
-#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE	
-#endif
-
-#if defined(STM32F7)
-#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
-#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
-#endif
-
-#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
-#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
-
-#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
-
-#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
-#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
-#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
-#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
-#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
-
-#define RCC_IT_HSI14                RCC_IT_HSI14RDY
-
-#if defined(STM32L0)
-#define RCC_IT_LSECSS              RCC_IT_CSSLSE 
-#define RCC_IT_CSS                 RCC_IT_CSSHSE
-#endif
-
-#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
-#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
-#define RCC_MCO_NODIV               RCC_MCODIV_1
-#define RCC_MCO_DIV1                RCC_MCODIV_1
-#define RCC_MCO_DIV2                RCC_MCODIV_2
-#define RCC_MCO_DIV4                RCC_MCODIV_4
-#define RCC_MCO_DIV8                RCC_MCODIV_8
-#define RCC_MCO_DIV16               RCC_MCODIV_16
-#define RCC_MCO_DIV32               RCC_MCODIV_32
-#define RCC_MCO_DIV64               RCC_MCODIV_64
-#define RCC_MCO_DIV128              RCC_MCODIV_128
-#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
-#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
-#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
-#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
-#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
-#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
-#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
-#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
-#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
-
-#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
-
-#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
-#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
-#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
-#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
-#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
-#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
-
-#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
-#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
-#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
-#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
-#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
-#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
-#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
-#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
-#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
-#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
-#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
-#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
-#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
-#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
-#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
-#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
-#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
-#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
-#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
-#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
-#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
-#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
-#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
-#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
-#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
-#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
-#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
-#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
-#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
-#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
-#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
-#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
-
-#define CR_HSION_BB            RCC_CR_HSION_BB
-#define CR_CSSON_BB            RCC_CR_CSSON_BB
-#define CR_PLLON_BB            RCC_CR_PLLON_BB
-#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
-#define CR_MSION_BB            RCC_CR_MSION_BB
-#define CSR_LSION_BB           RCC_CSR_LSION_BB
-#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
-#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
-#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
-#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
-#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
-#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
-#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
-#define CR_HSEON_BB            RCC_CR_HSEON_BB
-#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
-#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
-#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
-
-#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
-#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
-#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
-#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
-#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
-
-#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
-
-#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
-#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
-
-#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
-#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
-#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
-#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
-#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
-#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
-
-#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
-#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
-#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
-#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
-#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
-#define DfsdmClockSelection         Dfsdm1ClockSelection
-#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
-#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK
-#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
-#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
-#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)                                       
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-  
-#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
-#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
-#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
-
-#if defined (STM32F1)
-#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
-
-#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
-
-#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
-
-#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
-
-#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
-                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
-                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
-                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
-                                                      (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
-                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
-#endif   /* STM32F1 */
-
-#define IS_ALARM                                  IS_RTC_ALARM
-#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
-#define IS_TAMPER                                 IS_RTC_TAMPER
-#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
-#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER 
-#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
-#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
-#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
-#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
-#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
-#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
-#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
-#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
-
-#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
-#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
-#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
-
-#if defined(STM32F4)
-#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
-#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY     
-#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED   
-#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION  
-#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND   
-#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT     
-#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED   
-#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE      
-#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE     
-#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE  
-#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL  
-#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT   
-#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT  
-#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG    
-#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG  
-#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT      
-#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT    
-#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS	       
-#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT	       
-#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
-/* alias CMSIS */
-#define  SDMMC1_IRQn                SDIO_IRQn
-#define  SDMMC1_IRQHandler          SDIO_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
-#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY    
-#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED  
-#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
-#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
-#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
-#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
-#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
-#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
-#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
-#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
-#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
-#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
-#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
-#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
-#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
-#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
-#define  SDIO_STATIC_FLAGS	        SDMMC_STATIC_FLAGS
-#define  SDIO_CMD0TIMEOUT	          SDMMC_CMD0TIMEOUT
-#define  SD_SDIO_SEND_IF_COND	      SD_SDMMC_SEND_IF_COND
-/* alias CMSIS for compatibilities */
-#define  SDIO_IRQn                  SDMMC1_IRQn
-#define  SDIO_IRQHandler            SDMMC1_IRQHandler
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
-#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
-#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
-#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
-#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
-#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
-
-#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
-#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
-
-#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE                  
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
-#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
-#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
-#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
-#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
-#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
-#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
-#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
-#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
-#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
-#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
-#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
-#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
-
-#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
-
-#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE                  
-#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE                  
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
-#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
-#define __USART_ENABLE                  __HAL_USART_ENABLE
-#define __USART_DISABLE                 __HAL_USART_DISABLE
-
-#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
-#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
-
-#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
-#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
-#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-
-#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
-#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
-
-#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
-#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
-#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
-
-#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
-#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
-
-#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
-
-#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
-#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
-#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
-#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
-#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
-#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
-#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
-#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
-#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
-#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
-#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
-#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
-
-#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
-/**
-  * @}
-  */
-
-/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
-  * @{
-  */
-  
-#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
-#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
-
-#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE 
-#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
-#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_LTDC_LAYER LTDC_LAYER
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
-#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
-#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
-#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
-#define SAI_STREOMODE                     SAI_STEREOMODE
-#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
-#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
-#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
-#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
-#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
-#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
-#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
-#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
-#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-  
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32_HAL_LEGACY */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f103xb.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,11073 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f103xb.h
-  * @author  MCD Application Team
-  * @version V4.1.0
-  * @date    29-April-2016
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32F1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f103xb
-  * @{
-  */
-    
-#ifndef __STM32F103xB_H
-#define __STM32F103xB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
- #define __MPU_PRESENT             0      /*!< Other STM32 devices does not provide an MPU  */
-#define __CM3_REV                 0x0200  /*!< Core Revision r2p0                           */
-#define __NVIC_PRIO_BITS          4       /*!< STM32 uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used */
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F10x Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                     */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */
-
-/******  STM32 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */
-  TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */
-  RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */
-  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
-  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
-  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
-  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
-  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
-  USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
-} IRQn_Type;
-
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32f1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;
-  __IO uint32_t CR1;
-  __IO uint32_t CR2;
-  __IO uint32_t SMPR1;
-  __IO uint32_t SMPR2;
-  __IO uint32_t JOFR1;
-  __IO uint32_t JOFR2;
-  __IO uint32_t JOFR3;
-  __IO uint32_t JOFR4;
-  __IO uint32_t HTR;
-  __IO uint32_t LTR;
-  __IO uint32_t SQR1;
-  __IO uint32_t SQR2;
-  __IO uint32_t SQR3;
-  __IO uint32_t JSQR;
-  __IO uint32_t JDR1;
-  __IO uint32_t JDR2;
-  __IO uint32_t JDR3;
-  __IO uint32_t JDR4;
-  __IO uint32_t DR;
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t SR;               /*!< ADC status register,    used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address         */
-  __IO uint32_t CR1;              /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04  */
-  __IO uint32_t CR2;              /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08  */
-  uint32_t  RESERVED[16];
-  __IO uint32_t DR;               /*!< ADC data register,      used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C  */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Backup Registers  
-  */
-
-typedef struct
-{
-  uint32_t  RESERVED0;
-  __IO uint32_t DR1;
-  __IO uint32_t DR2;
-  __IO uint32_t DR3;
-  __IO uint32_t DR4;
-  __IO uint32_t DR5;
-  __IO uint32_t DR6;
-  __IO uint32_t DR7;
-  __IO uint32_t DR8;
-  __IO uint32_t DR9;
-  __IO uint32_t DR10;
-  __IO uint32_t RTCCR;
-  __IO uint32_t CR;
-  __IO uint32_t CSR;
-} BKP_TypeDef;
-  
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;
-  __IO uint32_t TDTR;
-  __IO uint32_t TDLR;
-  __IO uint32_t TDHR;
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;
-  __IO uint32_t RDTR;
-  __IO uint32_t RDLR;
-  __IO uint32_t RDHR;
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1;
-  __IO uint32_t FR2;
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-  
-typedef struct
-{
-  __IO uint32_t MCR;
-  __IO uint32_t MSR;
-  __IO uint32_t TSR;
-  __IO uint32_t RF0R;
-  __IO uint32_t RF1R;
-  __IO uint32_t IER;
-  __IO uint32_t ESR;
-  __IO uint32_t BTR;
-  uint32_t  RESERVED0[88];
-  CAN_TxMailBox_TypeDef sTxMailBox[3];
-  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
-  uint32_t  RESERVED1[12];
-  __IO uint32_t FMR;
-  __IO uint32_t FM1R;
-  uint32_t  RESERVED2;
-  __IO uint32_t FS1R;
-  uint32_t  RESERVED3;
-  __IO uint32_t FFA1R;
-  uint32_t  RESERVED4;
-  __IO uint32_t FA1R;
-  uint32_t  RESERVED5[8];
-  CAN_FilterRegister_TypeDef sFilterRegister[14];
-} CAN_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */  
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;
-  __IO uint32_t CR;
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;
-  __IO uint32_t CNDTR;
-  __IO uint32_t CPAR;
-  __IO uint32_t CMAR;
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;
-  __IO uint32_t IFCR;
-} DMA_TypeDef;
-
-
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;
-  __IO uint32_t EMR;
-  __IO uint32_t RTSR;
-  __IO uint32_t FTSR;
-  __IO uint32_t SWIER;
-  __IO uint32_t PR;
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;
-  __IO uint32_t KEYR;
-  __IO uint32_t OPTKEYR;
-  __IO uint32_t SR;
-  __IO uint32_t CR;
-  __IO uint32_t AR;
-  __IO uint32_t RESERVED;
-  __IO uint32_t OBR;
-  __IO uint32_t WRPR;
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-  
-typedef struct
-{
-  __IO uint16_t RDP;
-  __IO uint16_t USER;
-  __IO uint16_t Data0;
-  __IO uint16_t Data1;
-  __IO uint16_t WRP0;
-  __IO uint16_t WRP1;
-  __IO uint16_t WRP2;
-  __IO uint16_t WRP3;
-} OB_TypeDef;
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t CRL;
-  __IO uint32_t CRH;
-  __IO uint32_t IDR;
-  __IO uint32_t ODR;
-  __IO uint32_t BSRR;
-  __IO uint32_t BRR;
-  __IO uint32_t LCKR;
-} GPIO_TypeDef;
-
-/** 
-  * @brief Alternate Function I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t EVCR;
-  __IO uint32_t MAPR;
-  __IO uint32_t EXTICR[4];
-  uint32_t RESERVED0;
-  __IO uint32_t MAPR2;  
-} AFIO_TypeDef;
-/** 
-  * @brief Inter Integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;
-  __IO uint32_t CR2;
-  __IO uint32_t OAR1;
-  __IO uint32_t OAR2;
-  __IO uint32_t DR;
-  __IO uint32_t SR1;
-  __IO uint32_t SR2;
-  __IO uint32_t CCR;
-  __IO uint32_t TRISE;
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;
-  __IO uint32_t CSR;
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;
-  __IO uint32_t CFGR;
-  __IO uint32_t CIR;
-  __IO uint32_t APB2RSTR;
-  __IO uint32_t APB1RSTR;
-  __IO uint32_t AHBENR;
-  __IO uint32_t APB2ENR;
-  __IO uint32_t APB1ENR;
-  __IO uint32_t BDCR;
-  __IO uint32_t CSR;
-
-
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t CRH;
-  __IO uint32_t CRL;
-  __IO uint32_t PRLH;
-  __IO uint32_t PRLL;
-  __IO uint32_t DIVH;
-  __IO uint32_t DIVL;
-  __IO uint32_t CNTH;
-  __IO uint32_t CNTL;
-  __IO uint32_t ALRH;
-  __IO uint32_t ALRL;
-} RTC_TypeDef;
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;
-  __IO uint32_t CLKCR;
-  __IO uint32_t ARG;
-  __IO uint32_t CMD;
-  __I uint32_t RESPCMD;
-  __I uint32_t RESP1;
-  __I uint32_t RESP2;
-  __I uint32_t RESP3;
-  __I uint32_t RESP4;
-  __IO uint32_t DTIMER;
-  __IO uint32_t DLEN;
-  __IO uint32_t DCTRL;
-  __I uint32_t DCOUNT;
-  __I uint32_t STA;
-  __IO uint32_t ICR;
-  __IO uint32_t MASK;
-  uint32_t  RESERVED0[2];
-  __I uint32_t FIFOCNT;
-  uint32_t  RESERVED1[13];
-  __IO uint32_t FIFO;
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;
-  __IO uint32_t CR2;
-  __IO uint32_t SR;
-  __IO uint32_t DR;
-  __IO uint32_t CRCPR;
-  __IO uint32_t RXCRCR;
-  __IO uint32_t TXCRCR;
-  __IO uint32_t I2SCFGR;
-} SPI_TypeDef;
-
-/**
-  * @brief TIM Timers
-  */
-typedef struct
-{
-  __IO uint32_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */
-  __IO uint32_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */
-  __IO uint32_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */
-  __IO uint32_t SR;              /*!< TIM status register,                         Address offset: 0x10 */
-  __IO uint32_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */
-  __IO uint32_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */
-  __IO uint32_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */
-  __IO uint32_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */
-  __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */
-  __IO uint32_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
-  __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
-  __IO uint32_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
-  __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
-  __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
-  __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
-  __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
-  __IO uint32_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
-  __IO uint32_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
-  __IO uint32_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
-  __IO uint32_t OR;              /*!< TIM option register,                         Address offset: 0x50 */
-}TIM_TypeDef;
-
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;                 /*!< USB Endpoint 0 register,                   Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;            /*!< Reserved */     
-  __IO uint16_t EP1R;                 /*!< USB Endpoint 1 register,                   Address offset: 0x04 */
-  __IO uint16_t RESERVED1;            /*!< Reserved */       
-  __IO uint16_t EP2R;                 /*!< USB Endpoint 2 register,                   Address offset: 0x08 */
-  __IO uint16_t RESERVED2;            /*!< Reserved */       
-  __IO uint16_t EP3R;                 /*!< USB Endpoint 3 register,                   Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;            /*!< Reserved */       
-  __IO uint16_t EP4R;                 /*!< USB Endpoint 4 register,                   Address offset: 0x10 */
-  __IO uint16_t RESERVED4;            /*!< Reserved */       
-  __IO uint16_t EP5R;                 /*!< USB Endpoint 5 register,                   Address offset: 0x14 */
-  __IO uint16_t RESERVED5;            /*!< Reserved */       
-  __IO uint16_t EP6R;                 /*!< USB Endpoint 6 register,                   Address offset: 0x18 */
-  __IO uint16_t RESERVED6;            /*!< Reserved */       
-  __IO uint16_t EP7R;                 /*!< USB Endpoint 7 register,                   Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];        /*!< Reserved */     
-  __IO uint16_t CNTR;                 /*!< Control register,                          Address offset: 0x40 */
-  __IO uint16_t RESERVED8;            /*!< Reserved */       
-  __IO uint16_t ISTR;                 /*!< Interrupt status register,                 Address offset: 0x44 */
-  __IO uint16_t RESERVED9;            /*!< Reserved */       
-  __IO uint16_t FNR;                  /*!< Frame number register,                     Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;            /*!< Reserved */       
-  __IO uint16_t DADDR;                /*!< Device address register,                   Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;            /*!< Reserved */       
-  __IO uint16_t BTABLE;               /*!< Buffer Table address register,             Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;            /*!< Reserved */       
-} USB_TypeDef;
-
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-
-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_BANK1_END       ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
-
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
-#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
-#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
-#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
-
-#define SDIO_BASE             (PERIPH_BASE + 0x18000)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)
-
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define FLASHSIZE_BASE        ((uint32_t)0x1FFFF7E0)    /*!< FLASH Size register base address */
-#define UID_BASE              ((uint32_t)0x1FFFF7E8)    /*!< Unique device ID register base address */
-#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */
-
-
-
-#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
-
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define USB                 ((USB_TypeDef *) USB_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define BKP                 ((BKP_TypeDef *) BKP_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC1_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFU << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFU << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1U << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPDS_Pos                     (0U)                               
-#define PWR_CR_LPDS_Msk                     (0x1U << PWR_CR_LPDS_Pos)          /*!< 0x00000001 */
-#define PWR_CR_LPDS                         PWR_CR_LPDS_Msk                    /*!< Low-Power Deepsleep */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1U << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1U << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1U << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1U << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7U << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1U << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2U << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4U << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_2V2                      ((uint32_t)0x00000000)             /*!< PVD level 2.2V */
-#define PWR_CR_PLS_2V3                      ((uint32_t)0x00000020)             /*!< PVD level 2.3V */
-#define PWR_CR_PLS_2V4                      ((uint32_t)0x00000040)             /*!< PVD level 2.4V */
-#define PWR_CR_PLS_2V5                      ((uint32_t)0x00000060)             /*!< PVD level 2.5V */
-#define PWR_CR_PLS_2V6                      ((uint32_t)0x00000080)             /*!< PVD level 2.6V */
-#define PWR_CR_PLS_2V7                      ((uint32_t)0x000000A0)             /*!< PVD level 2.7V */
-#define PWR_CR_PLS_2V8                      ((uint32_t)0x000000C0)             /*!< PVD level 2.8V */
-#define PWR_CR_PLS_2V9                      ((uint32_t)0x000000E0)             /*!< PVD level 2.9V */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1U << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1U << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1U << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1U << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_EWUP_Pos                    (8U)                               
-#define PWR_CSR_EWUP_Msk                    (0x1U << PWR_CSR_EWUP_Pos)         /*!< 0x00000100 */
-#define PWR_CSR_EWUP                        PWR_CSR_EWUP_Msk                   /*!< Enable WKUP pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Backup registers                                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for BKP_DR1 register  ********************/
-#define BKP_DR1_D_Pos                       (0U)                               
-#define BKP_DR1_D_Msk                       (0xFFFFU << BKP_DR1_D_Pos)         /*!< 0x0000FFFF */
-#define BKP_DR1_D                           BKP_DR1_D_Msk                      /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR2 register  ********************/
-#define BKP_DR2_D_Pos                       (0U)                               
-#define BKP_DR2_D_Msk                       (0xFFFFU << BKP_DR2_D_Pos)         /*!< 0x0000FFFF */
-#define BKP_DR2_D                           BKP_DR2_D_Msk                      /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR3 register  ********************/
-#define BKP_DR3_D_Pos                       (0U)                               
-#define BKP_DR3_D_Msk                       (0xFFFFU << BKP_DR3_D_Pos)         /*!< 0x0000FFFF */
-#define BKP_DR3_D                           BKP_DR3_D_Msk                      /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR4 register  ********************/
-#define BKP_DR4_D_Pos                       (0U)                               
-#define BKP_DR4_D_Msk                       (0xFFFFU << BKP_DR4_D_Pos)         /*!< 0x0000FFFF */
-#define BKP_DR4_D                           BKP_DR4_D_Msk                      /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR5 register  ********************/
-#define BKP_DR5_D_Pos                       (0U)                               
-#define BKP_DR5_D_Msk                       (0xFFFFU << BKP_DR5_D_Pos)         /*!< 0x0000FFFF */
-#define BKP_DR5_D                           BKP_DR5_D_Msk                      /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR6 register  ********************/
-#define BKP_DR6_D_Pos                       (0U)                               
-#define BKP_DR6_D_Msk                       (0xFFFFU << BKP_DR6_D_Pos)         /*!< 0x0000FFFF */
-#define BKP_DR6_D                           BKP_DR6_D_Msk                      /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR7 register  ********************/
-#define BKP_DR7_D_Pos                       (0U)                               
-#define BKP_DR7_D_Msk                       (0xFFFFU << BKP_DR7_D_Pos)         /*!< 0x0000FFFF */
-#define BKP_DR7_D                           BKP_DR7_D_Msk                      /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR8 register  ********************/
-#define BKP_DR8_D_Pos                       (0U)                               
-#define BKP_DR8_D_Msk                       (0xFFFFU << BKP_DR8_D_Pos)         /*!< 0x0000FFFF */
-#define BKP_DR8_D                           BKP_DR8_D_Msk                      /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR9 register  ********************/
-#define BKP_DR9_D_Pos                       (0U)                               
-#define BKP_DR9_D_Msk                       (0xFFFFU << BKP_DR9_D_Pos)         /*!< 0x0000FFFF */
-#define BKP_DR9_D                           BKP_DR9_D_Msk                      /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR10 register  *******************/
-#define BKP_DR10_D_Pos                      (0U)                               
-#define BKP_DR10_D_Msk                      (0xFFFFU << BKP_DR10_D_Pos)        /*!< 0x0000FFFF */
-#define BKP_DR10_D                          BKP_DR10_D_Msk                     /*!< Backup data */
-
-#define RTC_BKP_NUMBER 10
-
-/******************  Bit definition for BKP_RTCCR register  *******************/
-#define BKP_RTCCR_CAL_Pos                   (0U)                               
-#define BKP_RTCCR_CAL_Msk                   (0x7FU << BKP_RTCCR_CAL_Pos)       /*!< 0x0000007F */
-#define BKP_RTCCR_CAL                       BKP_RTCCR_CAL_Msk                  /*!< Calibration value */
-#define BKP_RTCCR_CCO_Pos                   (7U)                               
-#define BKP_RTCCR_CCO_Msk                   (0x1U << BKP_RTCCR_CCO_Pos)        /*!< 0x00000080 */
-#define BKP_RTCCR_CCO                       BKP_RTCCR_CCO_Msk                  /*!< Calibration Clock Output */
-#define BKP_RTCCR_ASOE_Pos                  (8U)                               
-#define BKP_RTCCR_ASOE_Msk                  (0x1U << BKP_RTCCR_ASOE_Pos)       /*!< 0x00000100 */
-#define BKP_RTCCR_ASOE                      BKP_RTCCR_ASOE_Msk                 /*!< Alarm or Second Output Enable */
-#define BKP_RTCCR_ASOS_Pos                  (9U)                               
-#define BKP_RTCCR_ASOS_Msk                  (0x1U << BKP_RTCCR_ASOS_Pos)       /*!< 0x00000200 */
-#define BKP_RTCCR_ASOS                      BKP_RTCCR_ASOS_Msk                 /*!< Alarm or Second Output Selection */
-
-/********************  Bit definition for BKP_CR register  ********************/
-#define BKP_CR_TPE_Pos                      (0U)                               
-#define BKP_CR_TPE_Msk                      (0x1U << BKP_CR_TPE_Pos)           /*!< 0x00000001 */
-#define BKP_CR_TPE                          BKP_CR_TPE_Msk                     /*!< TAMPER pin enable */
-#define BKP_CR_TPAL_Pos                     (1U)                               
-#define BKP_CR_TPAL_Msk                     (0x1U << BKP_CR_TPAL_Pos)          /*!< 0x00000002 */
-#define BKP_CR_TPAL                         BKP_CR_TPAL_Msk                    /*!< TAMPER pin active level */
-
-/*******************  Bit definition for BKP_CSR register  ********************/
-#define BKP_CSR_CTE_Pos                     (0U)                               
-#define BKP_CSR_CTE_Msk                     (0x1U << BKP_CSR_CTE_Pos)          /*!< 0x00000001 */
-#define BKP_CSR_CTE                         BKP_CSR_CTE_Msk                    /*!< Clear Tamper event */
-#define BKP_CSR_CTI_Pos                     (1U)                               
-#define BKP_CSR_CTI_Msk                     (0x1U << BKP_CSR_CTI_Pos)          /*!< 0x00000002 */
-#define BKP_CSR_CTI                         BKP_CSR_CTI_Msk                    /*!< Clear Tamper Interrupt */
-#define BKP_CSR_TPIE_Pos                    (2U)                               
-#define BKP_CSR_TPIE_Msk                    (0x1U << BKP_CSR_TPIE_Pos)         /*!< 0x00000004 */
-#define BKP_CSR_TPIE                        BKP_CSR_TPIE_Msk                   /*!< TAMPER Pin interrupt enable */
-#define BKP_CSR_TEF_Pos                     (8U)                               
-#define BKP_CSR_TEF_Msk                     (0x1U << BKP_CSR_TEF_Pos)          /*!< 0x00000100 */
-#define BKP_CSR_TEF                         BKP_CSR_TEF_Msk                    /*!< Tamper Event Flag */
-#define BKP_CSR_TIF_Pos                     (9U)                               
-#define BKP_CSR_TIF_Msk                     (0x1U << BKP_CSR_TIF_Pos)          /*!< 0x00000200 */
-#define BKP_CSR_TIF                         BKP_CSR_TIF_Msk                    /*!< Tamper Interrupt Flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                     (0U)                              
-#define RCC_CR_HSION_Msk                     (0x1U << RCC_CR_HSION_Pos)        /*!< 0x00000001 */
-#define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                    (1U)                              
-#define RCC_CR_HSIRDY_Msk                    (0x1U << RCC_CR_HSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSITRIM_Pos                   (3U)                              
-#define RCC_CR_HSITRIM_Msk                   (0x1FU << RCC_CR_HSITRIM_Pos)     /*!< 0x000000F8 */
-#define RCC_CR_HSITRIM                       RCC_CR_HSITRIM_Msk                /*!< Internal High Speed clock trimming */
-#define RCC_CR_HSICAL_Pos                    (8U)                              
-#define RCC_CR_HSICAL_Msk                    (0xFFU << RCC_CR_HSICAL_Pos)      /*!< 0x0000FF00 */
-#define RCC_CR_HSICAL                        RCC_CR_HSICAL_Msk                 /*!< Internal High Speed clock Calibration */
-#define RCC_CR_HSEON_Pos                     (16U)                             
-#define RCC_CR_HSEON_Msk                     (0x1U << RCC_CR_HSEON_Pos)        /*!< 0x00010000 */
-#define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                    (17U)                             
-#define RCC_CR_HSERDY_Msk                    (0x1U << RCC_CR_HSERDY_Pos)       /*!< 0x00020000 */
-#define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                    (18U)                             
-#define RCC_CR_HSEBYP_Msk                    (0x1U << RCC_CR_HSEBYP_Pos)       /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSON_Pos                     (19U)                             
-#define RCC_CR_CSSON_Msk                     (0x1U << RCC_CR_CSSON_Pos)        /*!< 0x00080000 */
-#define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< Clock Security System enable */
-#define RCC_CR_PLLON_Pos                     (24U)                             
-#define RCC_CR_PLLON_Msk                     (0x1U << RCC_CR_PLLON_Pos)        /*!< 0x01000000 */
-#define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                    (25U)                             
-#define RCC_CR_PLLRDY_Msk                    (0x1U << RCC_CR_PLLRDY_Pos)       /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< PLL clock ready flag */
-
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3U << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_HSI                      ((uint32_t)0x00000000)            /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      ((uint32_t)0x00000001)            /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      ((uint32_t)0x00000002)            /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3U << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_HSI                     ((uint32_t)0x00000000)            /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     ((uint32_t)0x00000004)            /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     ((uint32_t)0x00000008)            /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFU << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)            /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   ((uint32_t)0x00000080)            /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   ((uint32_t)0x00000090)            /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   ((uint32_t)0x000000A0)            /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  ((uint32_t)0x000000B0)            /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  ((uint32_t)0x000000C0)            /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 ((uint32_t)0x000000D0)            /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 ((uint32_t)0x000000E0)            /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 ((uint32_t)0x000000F0)            /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  ((uint32_t)0x00000400)            /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  ((uint32_t)0x00000500)            /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  ((uint32_t)0x00000600)            /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 ((uint32_t)0x00000700)            /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  ((uint32_t)0x00002000)            /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  ((uint32_t)0x00002800)            /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  ((uint32_t)0x00003000)            /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 ((uint32_t)0x00003800)            /*!< HCLK divided by 16 */
-
-/*!< ADCPPRE configuration */
-#define RCC_CFGR_ADCPRE_Pos                  (14U)                             
-#define RCC_CFGR_ADCPRE_Msk                  (0x3U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x0000C000 */
-#define RCC_CFGR_ADCPRE                      RCC_CFGR_ADCPRE_Msk               /*!< ADCPRE[1:0] bits (ADC prescaler) */
-#define RCC_CFGR_ADCPRE_0                    (0x1U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00004000 */
-#define RCC_CFGR_ADCPRE_1                    (0x2U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00008000 */
-
-#define RCC_CFGR_ADCPRE_DIV2                 ((uint32_t)0x00000000)            /*!< PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4                 ((uint32_t)0x00004000)            /*!< PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6                 ((uint32_t)0x00008000)            /*!< PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8                 ((uint32_t)0x0000C000)            /*!< PCLK2 divided by 8 */
-
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1U << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLXTPRE_Pos                (17U)                             
-#define RCC_CFGR_PLLXTPRE_Msk                (0x1U << RCC_CFGR_PLLXTPRE_Pos)   /*!< 0x00020000 */
-#define RCC_CFGR_PLLXTPRE                    RCC_CFGR_PLLXTPRE_Msk             /*!< HSE divider for PLL entry */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMULL_Pos                 (18U)                             
-#define RCC_CFGR_PLLMULL_Msk                 (0xFU << RCC_CFGR_PLLMULL_Pos)    /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMULL                     RCC_CFGR_PLLMULL_Msk              /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMULL_0                   (0x1U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00040000 */
-#define RCC_CFGR_PLLMULL_1                   (0x2U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00080000 */
-#define RCC_CFGR_PLLMULL_2                   (0x4U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00100000 */
-#define RCC_CFGR_PLLMULL_3                   (0x8U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLXTPRE_HSE                ((uint32_t)0x00000000)            /*!< HSE clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_HSE_DIV2           ((uint32_t)0x00020000)            /*!< HSE clock divided by 2 for PLL entry */
-
-#define RCC_CFGR_PLLMULL2                    ((uint32_t)0x00000000)            /*!< PLL input clock*2 */
-#define RCC_CFGR_PLLMULL3_Pos                (18U)                             
-#define RCC_CFGR_PLLMULL3_Msk                (0x1U << RCC_CFGR_PLLMULL3_Pos)   /*!< 0x00040000 */
-#define RCC_CFGR_PLLMULL3                    RCC_CFGR_PLLMULL3_Msk             /*!< PLL input clock*3 */
-#define RCC_CFGR_PLLMULL4_Pos                (19U)                             
-#define RCC_CFGR_PLLMULL4_Msk                (0x1U << RCC_CFGR_PLLMULL4_Pos)   /*!< 0x00080000 */
-#define RCC_CFGR_PLLMULL4                    RCC_CFGR_PLLMULL4_Msk             /*!< PLL input clock*4 */
-#define RCC_CFGR_PLLMULL5_Pos                (18U)                             
-#define RCC_CFGR_PLLMULL5_Msk                (0x3U << RCC_CFGR_PLLMULL5_Pos)   /*!< 0x000C0000 */
-#define RCC_CFGR_PLLMULL5                    RCC_CFGR_PLLMULL5_Msk             /*!< PLL input clock*5 */
-#define RCC_CFGR_PLLMULL6_Pos                (20U)                             
-#define RCC_CFGR_PLLMULL6_Msk                (0x1U << RCC_CFGR_PLLMULL6_Pos)   /*!< 0x00100000 */
-#define RCC_CFGR_PLLMULL6                    RCC_CFGR_PLLMULL6_Msk             /*!< PLL input clock*6 */
-#define RCC_CFGR_PLLMULL7_Pos                (18U)                             
-#define RCC_CFGR_PLLMULL7_Msk                (0x5U << RCC_CFGR_PLLMULL7_Pos)   /*!< 0x00140000 */
-#define RCC_CFGR_PLLMULL7                    RCC_CFGR_PLLMULL7_Msk             /*!< PLL input clock*7 */
-#define RCC_CFGR_PLLMULL8_Pos                (19U)                             
-#define RCC_CFGR_PLLMULL8_Msk                (0x3U << RCC_CFGR_PLLMULL8_Pos)   /*!< 0x00180000 */
-#define RCC_CFGR_PLLMULL8                    RCC_CFGR_PLLMULL8_Msk             /*!< PLL input clock*8 */
-#define RCC_CFGR_PLLMULL9_Pos                (18U)                             
-#define RCC_CFGR_PLLMULL9_Msk                (0x7U << RCC_CFGR_PLLMULL9_Pos)   /*!< 0x001C0000 */
-#define RCC_CFGR_PLLMULL9                    RCC_CFGR_PLLMULL9_Msk             /*!< PLL input clock*9 */
-#define RCC_CFGR_PLLMULL10_Pos               (21U)                             
-#define RCC_CFGR_PLLMULL10_Msk               (0x1U << RCC_CFGR_PLLMULL10_Pos)  /*!< 0x00200000 */
-#define RCC_CFGR_PLLMULL10                   RCC_CFGR_PLLMULL10_Msk            /*!< PLL input clock10 */
-#define RCC_CFGR_PLLMULL11_Pos               (18U)                             
-#define RCC_CFGR_PLLMULL11_Msk               (0x9U << RCC_CFGR_PLLMULL11_Pos)  /*!< 0x00240000 */
-#define RCC_CFGR_PLLMULL11                   RCC_CFGR_PLLMULL11_Msk            /*!< PLL input clock*11 */
-#define RCC_CFGR_PLLMULL12_Pos               (19U)                             
-#define RCC_CFGR_PLLMULL12_Msk               (0x5U << RCC_CFGR_PLLMULL12_Pos)  /*!< 0x00280000 */
-#define RCC_CFGR_PLLMULL12                   RCC_CFGR_PLLMULL12_Msk            /*!< PLL input clock*12 */
-#define RCC_CFGR_PLLMULL13_Pos               (18U)                             
-#define RCC_CFGR_PLLMULL13_Msk               (0xBU << RCC_CFGR_PLLMULL13_Pos)  /*!< 0x002C0000 */
-#define RCC_CFGR_PLLMULL13                   RCC_CFGR_PLLMULL13_Msk            /*!< PLL input clock*13 */
-#define RCC_CFGR_PLLMULL14_Pos               (20U)                             
-#define RCC_CFGR_PLLMULL14_Msk               (0x3U << RCC_CFGR_PLLMULL14_Pos)  /*!< 0x00300000 */
-#define RCC_CFGR_PLLMULL14                   RCC_CFGR_PLLMULL14_Msk            /*!< PLL input clock*14 */
-#define RCC_CFGR_PLLMULL15_Pos               (18U)                             
-#define RCC_CFGR_PLLMULL15_Msk               (0xDU << RCC_CFGR_PLLMULL15_Pos)  /*!< 0x00340000 */
-#define RCC_CFGR_PLLMULL15                   RCC_CFGR_PLLMULL15_Msk            /*!< PLL input clock*15 */
-#define RCC_CFGR_PLLMULL16_Pos               (19U)                             
-#define RCC_CFGR_PLLMULL16_Msk               (0x7U << RCC_CFGR_PLLMULL16_Pos)  /*!< 0x00380000 */
-#define RCC_CFGR_PLLMULL16                   RCC_CFGR_PLLMULL16_Msk            /*!< PLL input clock*16 */
-#define RCC_CFGR_USBPRE_Pos                  (22U)                             
-#define RCC_CFGR_USBPRE_Msk                  (0x1U << RCC_CFGR_USBPRE_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_USBPRE                      RCC_CFGR_USBPRE_Msk               /*!< USB Device prescaler */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCO_Pos                     (24U)                             
-#define RCC_CFGR_MCO_Msk                     (0x7U << RCC_CFGR_MCO_Pos)        /*!< 0x07000000 */
-#define RCC_CFGR_MCO                         RCC_CFGR_MCO_Msk                  /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCO_0                       (0x1U << RCC_CFGR_MCO_Pos)        /*!< 0x01000000 */
-#define RCC_CFGR_MCO_1                       (0x2U << RCC_CFGR_MCO_Pos)        /*!< 0x02000000 */
-#define RCC_CFGR_MCO_2                       (0x4U << RCC_CFGR_MCO_Pos)        /*!< 0x04000000 */
-
-#define RCC_CFGR_MCO_NOCLOCK                 ((uint32_t)0x00000000)            /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK                  ((uint32_t)0x04000000)            /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI                     ((uint32_t)0x05000000)            /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE                     ((uint32_t)0x06000000)            /*!< HSE clock selected as MCO source  */
-#define RCC_CFGR_MCO_PLLCLK_DIV2             ((uint32_t)0x07000000)            /*!< PLL clock divided by 2 selected as MCO source */
-
- /* Reference defines */
- #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO
- #define RCC_CFGR_MCOSEL_0                    RCC_CFGR_MCO_0
- #define RCC_CFGR_MCOSEL_1                    RCC_CFGR_MCO_1
- #define RCC_CFGR_MCOSEL_2                    RCC_CFGR_MCO_2
- #define RCC_CFGR_MCOSEL_NOCLOCK              RCC_CFGR_MCO_NOCLOCK
- #define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCO_SYSCLK
- #define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCO_HSI
- #define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCO_HSE
- #define RCC_CFGR_MCOSEL_PLL_DIV2             RCC_CFGR_MCO_PLLCLK_DIV2
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                  (0U)                              
-#define RCC_CIR_LSIRDYF_Msk                  (0x1U << RCC_CIR_LSIRDYF_Pos)     /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                      RCC_CIR_LSIRDYF_Msk               /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                  (1U)                              
-#define RCC_CIR_LSERDYF_Msk                  (0x1U << RCC_CIR_LSERDYF_Pos)     /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                      RCC_CIR_LSERDYF_Msk               /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                  (2U)                              
-#define RCC_CIR_HSIRDYF_Msk                  (0x1U << RCC_CIR_HSIRDYF_Pos)     /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                      RCC_CIR_HSIRDYF_Msk               /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                  (3U)                              
-#define RCC_CIR_HSERDYF_Msk                  (0x1U << RCC_CIR_HSERDYF_Pos)     /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                      RCC_CIR_HSERDYF_Msk               /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                  (4U)                              
-#define RCC_CIR_PLLRDYF_Msk                  (0x1U << RCC_CIR_PLLRDYF_Pos)     /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                      RCC_CIR_PLLRDYF_Msk               /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_CSSF_Pos                     (7U)                              
-#define RCC_CIR_CSSF_Msk                     (0x1U << RCC_CIR_CSSF_Pos)        /*!< 0x00000080 */
-#define RCC_CIR_CSSF                         RCC_CIR_CSSF_Msk                  /*!< Clock Security System Interrupt flag */
-#define RCC_CIR_LSIRDYIE_Pos                 (8U)                              
-#define RCC_CIR_LSIRDYIE_Msk                 (0x1U << RCC_CIR_LSIRDYIE_Pos)    /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                     RCC_CIR_LSIRDYIE_Msk              /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                 (9U)                              
-#define RCC_CIR_LSERDYIE_Msk                 (0x1U << RCC_CIR_LSERDYIE_Pos)    /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                     RCC_CIR_LSERDYIE_Msk              /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                 (10U)                             
-#define RCC_CIR_HSIRDYIE_Msk                 (0x1U << RCC_CIR_HSIRDYIE_Pos)    /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                     RCC_CIR_HSIRDYIE_Msk              /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                 (11U)                             
-#define RCC_CIR_HSERDYIE_Msk                 (0x1U << RCC_CIR_HSERDYIE_Pos)    /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                     RCC_CIR_HSERDYIE_Msk              /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                 (12U)                             
-#define RCC_CIR_PLLRDYIE_Msk                 (0x1U << RCC_CIR_PLLRDYIE_Pos)    /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                     RCC_CIR_PLLRDYIE_Msk              /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_LSIRDYC_Pos                  (16U)                             
-#define RCC_CIR_LSIRDYC_Msk                  (0x1U << RCC_CIR_LSIRDYC_Pos)     /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                      RCC_CIR_LSIRDYC_Msk               /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                  (17U)                             
-#define RCC_CIR_LSERDYC_Msk                  (0x1U << RCC_CIR_LSERDYC_Pos)     /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                      RCC_CIR_LSERDYC_Msk               /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                  (18U)                             
-#define RCC_CIR_HSIRDYC_Msk                  (0x1U << RCC_CIR_HSIRDYC_Pos)     /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                      RCC_CIR_HSIRDYC_Msk               /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                  (19U)                             
-#define RCC_CIR_HSERDYC_Msk                  (0x1U << RCC_CIR_HSERDYC_Pos)     /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                      RCC_CIR_HSERDYC_Msk               /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                  (20U)                             
-#define RCC_CIR_PLLRDYC_Msk                  (0x1U << RCC_CIR_PLLRDYC_Pos)     /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                      RCC_CIR_PLLRDYC_Msk               /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                     (23U)                             
-#define RCC_CIR_CSSC_Msk                     (0x1U << RCC_CIR_CSSC_Pos)        /*!< 0x00800000 */
-#define RCC_CIR_CSSC                         RCC_CIR_CSSC_Msk                  /*!< Clock Security System Interrupt Clear */
-
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_AFIORST_Pos             (0U)                              
-#define RCC_APB2RSTR_AFIORST_Msk             (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_AFIORST                 RCC_APB2RSTR_AFIORST_Msk          /*!< Alternate Function I/O reset */
-#define RCC_APB2RSTR_IOPARST_Pos             (2U)                              
-#define RCC_APB2RSTR_IOPARST_Msk             (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_IOPARST                 RCC_APB2RSTR_IOPARST_Msk          /*!< I/O port A reset */
-#define RCC_APB2RSTR_IOPBRST_Pos             (3U)                              
-#define RCC_APB2RSTR_IOPBRST_Msk             (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_IOPBRST                 RCC_APB2RSTR_IOPBRST_Msk          /*!< I/O port B reset */
-#define RCC_APB2RSTR_IOPCRST_Pos             (4U)                              
-#define RCC_APB2RSTR_IOPCRST_Msk             (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_IOPCRST                 RCC_APB2RSTR_IOPCRST_Msk          /*!< I/O port C reset */
-#define RCC_APB2RSTR_IOPDRST_Pos             (5U)                              
-#define RCC_APB2RSTR_IOPDRST_Msk             (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
-#define RCC_APB2RSTR_IOPDRST                 RCC_APB2RSTR_IOPDRST_Msk          /*!< I/O port D reset */
-#define RCC_APB2RSTR_ADC1RST_Pos             (9U)                              
-#define RCC_APB2RSTR_ADC1RST_Msk             (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                 RCC_APB2RSTR_ADC1RST_Msk          /*!< ADC 1 interface reset */
-
-#define RCC_APB2RSTR_ADC2RST_Pos             (10U)                             
-#define RCC_APB2RSTR_ADC2RST_Msk             (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
-#define RCC_APB2RSTR_ADC2RST                 RCC_APB2RSTR_ADC2RST_Msk          /*!< ADC 2 interface reset */
-
-#define RCC_APB2RSTR_TIM1RST_Pos             (11U)                             
-#define RCC_APB2RSTR_TIM1RST_Msk             (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
-#define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk          /*!< TIM1 Timer reset */
-#define RCC_APB2RSTR_SPI1RST_Pos             (12U)                             
-#define RCC_APB2RSTR_SPI1RST_Msk             (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk          /*!< SPI 1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos           (14U)                             
-#define RCC_APB2RSTR_USART1RST_Msk           (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk        /*!< USART1 reset */
-
-
-#define RCC_APB2RSTR_IOPERST_Pos             (6U)                              
-#define RCC_APB2RSTR_IOPERST_Msk             (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
-#define RCC_APB2RSTR_IOPERST                 RCC_APB2RSTR_IOPERST_Msk          /*!< I/O port E reset */
-
-
-
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos             (0U)                              
-#define RCC_APB1RSTR_TIM2RST_Msk             (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                 RCC_APB1RSTR_TIM2RST_Msk          /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos             (1U)                              
-#define RCC_APB1RSTR_TIM3RST_Msk             (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                 RCC_APB1RSTR_TIM3RST_Msk          /*!< Timer 3 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos             (11U)                             
-#define RCC_APB1RSTR_WWDGRST_Msk             (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                 RCC_APB1RSTR_WWDGRST_Msk          /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_USART2RST_Pos           (17U)                             
-#define RCC_APB1RSTR_USART2RST_Msk           (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST               RCC_APB1RSTR_USART2RST_Msk        /*!< USART 2 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos             (21U)                             
-#define RCC_APB1RSTR_I2C1RST_Msk             (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                 RCC_APB1RSTR_I2C1RST_Msk          /*!< I2C 1 reset */
-
-#define RCC_APB1RSTR_CAN1RST_Pos             (25U)                             
-#define RCC_APB1RSTR_CAN1RST_Msk             (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
-#define RCC_APB1RSTR_CAN1RST                 RCC_APB1RSTR_CAN1RST_Msk          /*!< CAN1 reset */
-
-#define RCC_APB1RSTR_BKPRST_Pos              (27U)                             
-#define RCC_APB1RSTR_BKPRST_Msk              (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
-#define RCC_APB1RSTR_BKPRST                  RCC_APB1RSTR_BKPRST_Msk           /*!< Backup interface reset */
-#define RCC_APB1RSTR_PWRRST_Pos              (28U)                             
-#define RCC_APB1RSTR_PWRRST_Msk              (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                  RCC_APB1RSTR_PWRRST_Msk           /*!< Power interface reset */
-
-#define RCC_APB1RSTR_TIM4RST_Pos             (2U)                              
-#define RCC_APB1RSTR_TIM4RST_Msk             (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                 RCC_APB1RSTR_TIM4RST_Msk          /*!< Timer 4 reset */
-#define RCC_APB1RSTR_SPI2RST_Pos             (14U)                             
-#define RCC_APB1RSTR_SPI2RST_Msk             (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                 RCC_APB1RSTR_SPI2RST_Msk          /*!< SPI 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos           (18U)                             
-#define RCC_APB1RSTR_USART3RST_Msk           (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST               RCC_APB1RSTR_USART3RST_Msk        /*!< USART 3 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos             (22U)                             
-#define RCC_APB1RSTR_I2C2RST_Msk             (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                 RCC_APB1RSTR_I2C2RST_Msk          /*!< I2C 2 reset */
-
-#define RCC_APB1RSTR_USBRST_Pos              (23U)                             
-#define RCC_APB1RSTR_USBRST_Msk              (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                  RCC_APB1RSTR_USBRST_Msk           /*!< USB Device reset */
-
-
-
-
-
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMA1EN_Pos                (0U)                              
-#define RCC_AHBENR_DMA1EN_Msk                (0x1U << RCC_AHBENR_DMA1EN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_DMA1EN                    RCC_AHBENR_DMA1EN_Msk             /*!< DMA1 clock enable */
-#define RCC_AHBENR_SRAMEN_Pos                (2U)                              
-#define RCC_AHBENR_SRAMEN_Msk                (0x1U << RCC_AHBENR_SRAMEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_SRAMEN                    RCC_AHBENR_SRAMEN_Msk             /*!< SRAM interface clock enable */
-#define RCC_AHBENR_FLITFEN_Pos               (4U)                              
-#define RCC_AHBENR_FLITFEN_Msk               (0x1U << RCC_AHBENR_FLITFEN_Pos)  /*!< 0x00000010 */
-#define RCC_AHBENR_FLITFEN                   RCC_AHBENR_FLITFEN_Msk            /*!< FLITF clock enable */
-#define RCC_AHBENR_CRCEN_Pos                 (6U)                              
-#define RCC_AHBENR_CRCEN_Msk                 (0x1U << RCC_AHBENR_CRCEN_Pos)    /*!< 0x00000040 */
-#define RCC_AHBENR_CRCEN                     RCC_AHBENR_CRCEN_Msk              /*!< CRC clock enable */
-
-
-
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_AFIOEN_Pos               (0U)                              
-#define RCC_APB2ENR_AFIOEN_Msk               (0x1U << RCC_APB2ENR_AFIOEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB2ENR_AFIOEN                   RCC_APB2ENR_AFIOEN_Msk            /*!< Alternate Function I/O clock enable */
-#define RCC_APB2ENR_IOPAEN_Pos               (2U)                              
-#define RCC_APB2ENR_IOPAEN_Msk               (0x1U << RCC_APB2ENR_IOPAEN_Pos)  /*!< 0x00000004 */
-#define RCC_APB2ENR_IOPAEN                   RCC_APB2ENR_IOPAEN_Msk            /*!< I/O port A clock enable */
-#define RCC_APB2ENR_IOPBEN_Pos               (3U)                              
-#define RCC_APB2ENR_IOPBEN_Msk               (0x1U << RCC_APB2ENR_IOPBEN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_IOPBEN                   RCC_APB2ENR_IOPBEN_Msk            /*!< I/O port B clock enable */
-#define RCC_APB2ENR_IOPCEN_Pos               (4U)                              
-#define RCC_APB2ENR_IOPCEN_Msk               (0x1U << RCC_APB2ENR_IOPCEN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_IOPCEN                   RCC_APB2ENR_IOPCEN_Msk            /*!< I/O port C clock enable */
-#define RCC_APB2ENR_IOPDEN_Pos               (5U)                              
-#define RCC_APB2ENR_IOPDEN_Msk               (0x1U << RCC_APB2ENR_IOPDEN_Pos)  /*!< 0x00000020 */
-#define RCC_APB2ENR_IOPDEN                   RCC_APB2ENR_IOPDEN_Msk            /*!< I/O port D clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos               (9U)                              
-#define RCC_APB2ENR_ADC1EN_Msk               (0x1U << RCC_APB2ENR_ADC1EN_Pos)  /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                   RCC_APB2ENR_ADC1EN_Msk            /*!< ADC 1 interface clock enable */
-
-#define RCC_APB2ENR_ADC2EN_Pos               (10U)                             
-#define RCC_APB2ENR_ADC2EN_Msk               (0x1U << RCC_APB2ENR_ADC2EN_Pos)  /*!< 0x00000400 */
-#define RCC_APB2ENR_ADC2EN                   RCC_APB2ENR_ADC2EN_Msk            /*!< ADC 2 interface clock enable */
-
-#define RCC_APB2ENR_TIM1EN_Pos               (11U)                             
-#define RCC_APB2ENR_TIM1EN_Msk               (0x1U << RCC_APB2ENR_TIM1EN_Pos)  /*!< 0x00000800 */
-#define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk            /*!< TIM1 Timer clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos               (12U)                             
-#define RCC_APB2ENR_SPI1EN_Msk               (0x1U << RCC_APB2ENR_SPI1EN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk            /*!< SPI 1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos             (14U)                             
-#define RCC_APB2ENR_USART1EN_Msk             (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk          /*!< USART1 clock enable */
-
-
-#define RCC_APB2ENR_IOPEEN_Pos               (6U)                              
-#define RCC_APB2ENR_IOPEEN_Msk               (0x1U << RCC_APB2ENR_IOPEEN_Pos)  /*!< 0x00000040 */
-#define RCC_APB2ENR_IOPEEN                   RCC_APB2ENR_IOPEEN_Msk            /*!< I/O port E clock enable */
-
-
-
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos               (0U)                              
-#define RCC_APB1ENR_TIM2EN_Msk               (0x1U << RCC_APB1ENR_TIM2EN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                   RCC_APB1ENR_TIM2EN_Msk            /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos               (1U)                              
-#define RCC_APB1ENR_TIM3EN_Msk               (0x1U << RCC_APB1ENR_TIM3EN_Pos)  /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                   RCC_APB1ENR_TIM3EN_Msk            /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos               (11U)                             
-#define RCC_APB1ENR_WWDGEN_Msk               (0x1U << RCC_APB1ENR_WWDGEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                   RCC_APB1ENR_WWDGEN_Msk            /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_USART2EN_Pos             (17U)                             
-#define RCC_APB1ENR_USART2EN_Msk             (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                 RCC_APB1ENR_USART2EN_Msk          /*!< USART 2 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos               (21U)                             
-#define RCC_APB1ENR_I2C1EN_Msk               (0x1U << RCC_APB1ENR_I2C1EN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                   RCC_APB1ENR_I2C1EN_Msk            /*!< I2C 1 clock enable */
-
-#define RCC_APB1ENR_CAN1EN_Pos               (25U)                             
-#define RCC_APB1ENR_CAN1EN_Msk               (0x1U << RCC_APB1ENR_CAN1EN_Pos)  /*!< 0x02000000 */
-#define RCC_APB1ENR_CAN1EN                   RCC_APB1ENR_CAN1EN_Msk            /*!< CAN1 clock enable */
-
-#define RCC_APB1ENR_BKPEN_Pos                (27U)                             
-#define RCC_APB1ENR_BKPEN_Msk                (0x1U << RCC_APB1ENR_BKPEN_Pos)   /*!< 0x08000000 */
-#define RCC_APB1ENR_BKPEN                    RCC_APB1ENR_BKPEN_Msk             /*!< Backup interface clock enable */
-#define RCC_APB1ENR_PWREN_Pos                (28U)                             
-#define RCC_APB1ENR_PWREN_Msk                (0x1U << RCC_APB1ENR_PWREN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                    RCC_APB1ENR_PWREN_Msk             /*!< Power interface clock enable */
-
-#define RCC_APB1ENR_TIM4EN_Pos               (2U)                              
-#define RCC_APB1ENR_TIM4EN_Msk               (0x1U << RCC_APB1ENR_TIM4EN_Pos)  /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                   RCC_APB1ENR_TIM4EN_Msk            /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos               (14U)                             
-#define RCC_APB1ENR_SPI2EN_Msk               (0x1U << RCC_APB1ENR_SPI2EN_Pos)  /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                   RCC_APB1ENR_SPI2EN_Msk            /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos             (18U)                             
-#define RCC_APB1ENR_USART3EN_Msk             (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                 RCC_APB1ENR_USART3EN_Msk          /*!< USART 3 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos               (22U)                             
-#define RCC_APB1ENR_I2C2EN_Msk               (0x1U << RCC_APB1ENR_I2C2EN_Pos)  /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                   RCC_APB1ENR_I2C2EN_Msk            /*!< I2C 2 clock enable */
-
-#define RCC_APB1ENR_USBEN_Pos                (23U)                             
-#define RCC_APB1ENR_USBEN_Msk                (0x1U << RCC_APB1ENR_USBEN_Pos)   /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                    RCC_APB1ENR_USBEN_Msk             /*!< USB Device clock enable */
-
-
-
-
-
-
-/*******************  Bit definition for RCC_BDCR register  *******************/
-#define RCC_BDCR_LSEON_Pos                   (0U)                              
-#define RCC_BDCR_LSEON_Msk                   (0x1U << RCC_BDCR_LSEON_Pos)      /*!< 0x00000001 */
-#define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk                /*!< External Low Speed oscillator enable */
-#define RCC_BDCR_LSERDY_Pos                  (1U)                              
-#define RCC_BDCR_LSERDY_Msk                  (0x1U << RCC_BDCR_LSERDY_Pos)     /*!< 0x00000002 */
-#define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk               /*!< External Low Speed oscillator Ready */
-#define RCC_BDCR_LSEBYP_Pos                  (2U)                              
-#define RCC_BDCR_LSEBYP_Msk                  (0x1U << RCC_BDCR_LSEBYP_Pos)     /*!< 0x00000004 */
-#define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk               /*!< External Low Speed oscillator Bypass */
-
-#define RCC_BDCR_RTCSEL_Pos                  (8U)                              
-#define RCC_BDCR_RTCSEL_Msk                  (0x3U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000300 */
-#define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk               /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_BDCR_RTCSEL_0                    (0x1U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000100 */
-#define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */
-
-/*!< RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK              ((uint32_t)0x00000000)            /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE                  ((uint32_t)0x00000100)            /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI                  ((uint32_t)0x00000200)            /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE                  ((uint32_t)0x00000300)            /*!< HSE oscillator clock divided by 128 used as RTC clock */
-
-#define RCC_BDCR_RTCEN_Pos                   (15U)                             
-#define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */
-#define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk                /*!< RTC clock enable */
-#define RCC_BDCR_BDRST_Pos                   (16U)                             
-#define RCC_BDCR_BDRST_Msk                   (0x1U << RCC_BDCR_BDRST_Pos)      /*!< 0x00010000 */
-#define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk                /*!< Backup domain software reset  */
-
-/*******************  Bit definition for RCC_CSR register  ********************/  
-#define RCC_CSR_LSION_Pos                    (0U)                              
-#define RCC_CSR_LSION_Msk                    (0x1U << RCC_CSR_LSION_Pos)       /*!< 0x00000001 */
-#define RCC_CSR_LSION                        RCC_CSR_LSION_Msk                 /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                   (1U)                              
-#define RCC_CSR_LSIRDY_Msk                   (0x1U << RCC_CSR_LSIRDY_Pos)      /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk                /*!< Internal Low Speed oscillator Ready */
-#define RCC_CSR_RMVF_Pos                     (24U)                             
-#define RCC_CSR_RMVF_Msk                     (0x1U << RCC_CSR_RMVF_Pos)        /*!< 0x01000000 */
-#define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk                  /*!< Remove reset flag */
-#define RCC_CSR_PINRSTF_Pos                  (26U)                             
-#define RCC_CSR_PINRSTF_Msk                  (0x1U << RCC_CSR_PINRSTF_Pos)     /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk               /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                  (27U)                             
-#define RCC_CSR_PORRSTF_Msk                  (0x1U << RCC_CSR_PORRSTF_Pos)     /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                      RCC_CSR_PORRSTF_Msk               /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                  (28U)                             
-#define RCC_CSR_SFTRSTF_Msk                  (0x1U << RCC_CSR_SFTRSTF_Pos)     /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk               /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                 (29U)                             
-#define RCC_CSR_IWDGRSTF_Msk                 (0x1U << RCC_CSR_IWDGRSTF_Pos)    /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk              /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                 (30U)                             
-#define RCC_CSR_WWDGRSTF_Msk                 (0x1U << RCC_CSR_WWDGRSTF_Pos)    /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk              /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                 (31U)                             
-#define RCC_CSR_LPWRRSTF_Msk                 (0x1U << RCC_CSR_LPWRRSTF_Pos)    /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk              /*!< Low-Power reset flag */
-
-
- 
-/******************************************************************************/
-/*                                                                            */
-/*                General Purpose and Alternate Function I/O                  */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for GPIO_CRL register  *******************/
-#define GPIO_CRL_MODE_Pos                    (0U)                              
-#define GPIO_CRL_MODE_Msk                    (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
-#define GPIO_CRL_MODE                        GPIO_CRL_MODE_Msk                 /*!< Port x mode bits */
-
-#define GPIO_CRL_MODE0_Pos                   (0U)                              
-#define GPIO_CRL_MODE0_Msk                   (0x3U << GPIO_CRL_MODE0_Pos)      /*!< 0x00000003 */
-#define GPIO_CRL_MODE0                       GPIO_CRL_MODE0_Msk                /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
-#define GPIO_CRL_MODE0_0                     (0x1U << GPIO_CRL_MODE0_Pos)      /*!< 0x00000001 */
-#define GPIO_CRL_MODE0_1                     (0x2U << GPIO_CRL_MODE0_Pos)      /*!< 0x00000002 */
-
-#define GPIO_CRL_MODE1_Pos                   (4U)                              
-#define GPIO_CRL_MODE1_Msk                   (0x3U << GPIO_CRL_MODE1_Pos)      /*!< 0x00000030 */
-#define GPIO_CRL_MODE1                       GPIO_CRL_MODE1_Msk                /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
-#define GPIO_CRL_MODE1_0                     (0x1U << GPIO_CRL_MODE1_Pos)      /*!< 0x00000010 */
-#define GPIO_CRL_MODE1_1                     (0x2U << GPIO_CRL_MODE1_Pos)      /*!< 0x00000020 */
-
-#define GPIO_CRL_MODE2_Pos                   (8U)                              
-#define GPIO_CRL_MODE2_Msk                   (0x3U << GPIO_CRL_MODE2_Pos)      /*!< 0x00000300 */
-#define GPIO_CRL_MODE2                       GPIO_CRL_MODE2_Msk                /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
-#define GPIO_CRL_MODE2_0                     (0x1U << GPIO_CRL_MODE2_Pos)      /*!< 0x00000100 */
-#define GPIO_CRL_MODE2_1                     (0x2U << GPIO_CRL_MODE2_Pos)      /*!< 0x00000200 */
-
-#define GPIO_CRL_MODE3_Pos                   (12U)                             
-#define GPIO_CRL_MODE3_Msk                   (0x3U << GPIO_CRL_MODE3_Pos)      /*!< 0x00003000 */
-#define GPIO_CRL_MODE3                       GPIO_CRL_MODE3_Msk                /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
-#define GPIO_CRL_MODE3_0                     (0x1U << GPIO_CRL_MODE3_Pos)      /*!< 0x00001000 */
-#define GPIO_CRL_MODE3_1                     (0x2U << GPIO_CRL_MODE3_Pos)      /*!< 0x00002000 */
-
-#define GPIO_CRL_MODE4_Pos                   (16U)                             
-#define GPIO_CRL_MODE4_Msk                   (0x3U << GPIO_CRL_MODE4_Pos)      /*!< 0x00030000 */
-#define GPIO_CRL_MODE4                       GPIO_CRL_MODE4_Msk                /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
-#define GPIO_CRL_MODE4_0                     (0x1U << GPIO_CRL_MODE4_Pos)      /*!< 0x00010000 */
-#define GPIO_CRL_MODE4_1                     (0x2U << GPIO_CRL_MODE4_Pos)      /*!< 0x00020000 */
-
-#define GPIO_CRL_MODE5_Pos                   (20U)                             
-#define GPIO_CRL_MODE5_Msk                   (0x3U << GPIO_CRL_MODE5_Pos)      /*!< 0x00300000 */
-#define GPIO_CRL_MODE5                       GPIO_CRL_MODE5_Msk                /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
-#define GPIO_CRL_MODE5_0                     (0x1U << GPIO_CRL_MODE5_Pos)      /*!< 0x00100000 */
-#define GPIO_CRL_MODE5_1                     (0x2U << GPIO_CRL_MODE5_Pos)      /*!< 0x00200000 */
-
-#define GPIO_CRL_MODE6_Pos                   (24U)                             
-#define GPIO_CRL_MODE6_Msk                   (0x3U << GPIO_CRL_MODE6_Pos)      /*!< 0x03000000 */
-#define GPIO_CRL_MODE6                       GPIO_CRL_MODE6_Msk                /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
-#define GPIO_CRL_MODE6_0                     (0x1U << GPIO_CRL_MODE6_Pos)      /*!< 0x01000000 */
-#define GPIO_CRL_MODE6_1                     (0x2U << GPIO_CRL_MODE6_Pos)      /*!< 0x02000000 */
-
-#define GPIO_CRL_MODE7_Pos                   (28U)                             
-#define GPIO_CRL_MODE7_Msk                   (0x3U << GPIO_CRL_MODE7_Pos)      /*!< 0x30000000 */
-#define GPIO_CRL_MODE7                       GPIO_CRL_MODE7_Msk                /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
-#define GPIO_CRL_MODE7_0                     (0x1U << GPIO_CRL_MODE7_Pos)      /*!< 0x10000000 */
-#define GPIO_CRL_MODE7_1                     (0x2U << GPIO_CRL_MODE7_Pos)      /*!< 0x20000000 */
-
-#define GPIO_CRL_CNF_Pos                     (2U)                              
-#define GPIO_CRL_CNF_Msk                     (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
-#define GPIO_CRL_CNF                         GPIO_CRL_CNF_Msk                  /*!< Port x configuration bits */
-
-#define GPIO_CRL_CNF0_Pos                    (2U)                              
-#define GPIO_CRL_CNF0_Msk                    (0x3U << GPIO_CRL_CNF0_Pos)       /*!< 0x0000000C */
-#define GPIO_CRL_CNF0                        GPIO_CRL_CNF0_Msk                 /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
-#define GPIO_CRL_CNF0_0                      (0x1U << GPIO_CRL_CNF0_Pos)       /*!< 0x00000004 */
-#define GPIO_CRL_CNF0_1                      (0x2U << GPIO_CRL_CNF0_Pos)       /*!< 0x00000008 */
-
-#define GPIO_CRL_CNF1_Pos                    (6U)                              
-#define GPIO_CRL_CNF1_Msk                    (0x3U << GPIO_CRL_CNF1_Pos)       /*!< 0x000000C0 */
-#define GPIO_CRL_CNF1                        GPIO_CRL_CNF1_Msk                 /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
-#define GPIO_CRL_CNF1_0                      (0x1U << GPIO_CRL_CNF1_Pos)       /*!< 0x00000040 */
-#define GPIO_CRL_CNF1_1                      (0x2U << GPIO_CRL_CNF1_Pos)       /*!< 0x00000080 */
-
-#define GPIO_CRL_CNF2_Pos                    (10U)                             
-#define GPIO_CRL_CNF2_Msk                    (0x3U << GPIO_CRL_CNF2_Pos)       /*!< 0x00000C00 */
-#define GPIO_CRL_CNF2                        GPIO_CRL_CNF2_Msk                 /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
-#define GPIO_CRL_CNF2_0                      (0x1U << GPIO_CRL_CNF2_Pos)       /*!< 0x00000400 */
-#define GPIO_CRL_CNF2_1                      (0x2U << GPIO_CRL_CNF2_Pos)       /*!< 0x00000800 */
-
-#define GPIO_CRL_CNF3_Pos                    (14U)                             
-#define GPIO_CRL_CNF3_Msk                    (0x3U << GPIO_CRL_CNF3_Pos)       /*!< 0x0000C000 */
-#define GPIO_CRL_CNF3                        GPIO_CRL_CNF3_Msk                 /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
-#define GPIO_CRL_CNF3_0                      (0x1U << GPIO_CRL_CNF3_Pos)       /*!< 0x00004000 */
-#define GPIO_CRL_CNF3_1                      (0x2U << GPIO_CRL_CNF3_Pos)       /*!< 0x00008000 */
-
-#define GPIO_CRL_CNF4_Pos                    (18U)                             
-#define GPIO_CRL_CNF4_Msk                    (0x3U << GPIO_CRL_CNF4_Pos)       /*!< 0x000C0000 */
-#define GPIO_CRL_CNF4                        GPIO_CRL_CNF4_Msk                 /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
-#define GPIO_CRL_CNF4_0                      (0x1U << GPIO_CRL_CNF4_Pos)       /*!< 0x00040000 */
-#define GPIO_CRL_CNF4_1                      (0x2U << GPIO_CRL_CNF4_Pos)       /*!< 0x00080000 */
-
-#define GPIO_CRL_CNF5_Pos                    (22U)                             
-#define GPIO_CRL_CNF5_Msk                    (0x3U << GPIO_CRL_CNF5_Pos)       /*!< 0x00C00000 */
-#define GPIO_CRL_CNF5                        GPIO_CRL_CNF5_Msk                 /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
-#define GPIO_CRL_CNF5_0                      (0x1U << GPIO_CRL_CNF5_Pos)       /*!< 0x00400000 */
-#define GPIO_CRL_CNF5_1                      (0x2U << GPIO_CRL_CNF5_Pos)       /*!< 0x00800000 */
-
-#define GPIO_CRL_CNF6_Pos                    (26U)                             
-#define GPIO_CRL_CNF6_Msk                    (0x3U << GPIO_CRL_CNF6_Pos)       /*!< 0x0C000000 */
-#define GPIO_CRL_CNF6                        GPIO_CRL_CNF6_Msk                 /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
-#define GPIO_CRL_CNF6_0                      (0x1U << GPIO_CRL_CNF6_Pos)       /*!< 0x04000000 */
-#define GPIO_CRL_CNF6_1                      (0x2U << GPIO_CRL_CNF6_Pos)       /*!< 0x08000000 */
-
-#define GPIO_CRL_CNF7_Pos                    (30U)                             
-#define GPIO_CRL_CNF7_Msk                    (0x3U << GPIO_CRL_CNF7_Pos)       /*!< 0xC0000000 */
-#define GPIO_CRL_CNF7                        GPIO_CRL_CNF7_Msk                 /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
-#define GPIO_CRL_CNF7_0                      (0x1U << GPIO_CRL_CNF7_Pos)       /*!< 0x40000000 */
-#define GPIO_CRL_CNF7_1                      (0x2U << GPIO_CRL_CNF7_Pos)       /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_CRH register  *******************/
-#define GPIO_CRH_MODE_Pos                    (0U)                              
-#define GPIO_CRH_MODE_Msk                    (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
-#define GPIO_CRH_MODE                        GPIO_CRH_MODE_Msk                 /*!< Port x mode bits */
-
-#define GPIO_CRH_MODE8_Pos                   (0U)                              
-#define GPIO_CRH_MODE8_Msk                   (0x3U << GPIO_CRH_MODE8_Pos)      /*!< 0x00000003 */
-#define GPIO_CRH_MODE8                       GPIO_CRH_MODE8_Msk                /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
-#define GPIO_CRH_MODE8_0                     (0x1U << GPIO_CRH_MODE8_Pos)      /*!< 0x00000001 */
-#define GPIO_CRH_MODE8_1                     (0x2U << GPIO_CRH_MODE8_Pos)      /*!< 0x00000002 */
-
-#define GPIO_CRH_MODE9_Pos                   (4U)                              
-#define GPIO_CRH_MODE9_Msk                   (0x3U << GPIO_CRH_MODE9_Pos)      /*!< 0x00000030 */
-#define GPIO_CRH_MODE9                       GPIO_CRH_MODE9_Msk                /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
-#define GPIO_CRH_MODE9_0                     (0x1U << GPIO_CRH_MODE9_Pos)      /*!< 0x00000010 */
-#define GPIO_CRH_MODE9_1                     (0x2U << GPIO_CRH_MODE9_Pos)      /*!< 0x00000020 */
-
-#define GPIO_CRH_MODE10_Pos                  (8U)                              
-#define GPIO_CRH_MODE10_Msk                  (0x3U << GPIO_CRH_MODE10_Pos)     /*!< 0x00000300 */
-#define GPIO_CRH_MODE10                      GPIO_CRH_MODE10_Msk               /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
-#define GPIO_CRH_MODE10_0                    (0x1U << GPIO_CRH_MODE10_Pos)     /*!< 0x00000100 */
-#define GPIO_CRH_MODE10_1                    (0x2U << GPIO_CRH_MODE10_Pos)     /*!< 0x00000200 */
-
-#define GPIO_CRH_MODE11_Pos                  (12U)                             
-#define GPIO_CRH_MODE11_Msk                  (0x3U << GPIO_CRH_MODE11_Pos)     /*!< 0x00003000 */
-#define GPIO_CRH_MODE11                      GPIO_CRH_MODE11_Msk               /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
-#define GPIO_CRH_MODE11_0                    (0x1U << GPIO_CRH_MODE11_Pos)     /*!< 0x00001000 */
-#define GPIO_CRH_MODE11_1                    (0x2U << GPIO_CRH_MODE11_Pos)     /*!< 0x00002000 */
-
-#define GPIO_CRH_MODE12_Pos                  (16U)                             
-#define GPIO_CRH_MODE12_Msk                  (0x3U << GPIO_CRH_MODE12_Pos)     /*!< 0x00030000 */
-#define GPIO_CRH_MODE12                      GPIO_CRH_MODE12_Msk               /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
-#define GPIO_CRH_MODE12_0                    (0x1U << GPIO_CRH_MODE12_Pos)     /*!< 0x00010000 */
-#define GPIO_CRH_MODE12_1                    (0x2U << GPIO_CRH_MODE12_Pos)     /*!< 0x00020000 */
-
-#define GPIO_CRH_MODE13_Pos                  (20U)                             
-#define GPIO_CRH_MODE13_Msk                  (0x3U << GPIO_CRH_MODE13_Pos)     /*!< 0x00300000 */
-#define GPIO_CRH_MODE13                      GPIO_CRH_MODE13_Msk               /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
-#define GPIO_CRH_MODE13_0                    (0x1U << GPIO_CRH_MODE13_Pos)     /*!< 0x00100000 */
-#define GPIO_CRH_MODE13_1                    (0x2U << GPIO_CRH_MODE13_Pos)     /*!< 0x00200000 */
-
-#define GPIO_CRH_MODE14_Pos                  (24U)                             
-#define GPIO_CRH_MODE14_Msk                  (0x3U << GPIO_CRH_MODE14_Pos)     /*!< 0x03000000 */
-#define GPIO_CRH_MODE14                      GPIO_CRH_MODE14_Msk               /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
-#define GPIO_CRH_MODE14_0                    (0x1U << GPIO_CRH_MODE14_Pos)     /*!< 0x01000000 */
-#define GPIO_CRH_MODE14_1                    (0x2U << GPIO_CRH_MODE14_Pos)     /*!< 0x02000000 */
-
-#define GPIO_CRH_MODE15_Pos                  (28U)                             
-#define GPIO_CRH_MODE15_Msk                  (0x3U << GPIO_CRH_MODE15_Pos)     /*!< 0x30000000 */
-#define GPIO_CRH_MODE15                      GPIO_CRH_MODE15_Msk               /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
-#define GPIO_CRH_MODE15_0                    (0x1U << GPIO_CRH_MODE15_Pos)     /*!< 0x10000000 */
-#define GPIO_CRH_MODE15_1                    (0x2U << GPIO_CRH_MODE15_Pos)     /*!< 0x20000000 */
-
-#define GPIO_CRH_CNF_Pos                     (2U)                              
-#define GPIO_CRH_CNF_Msk                     (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
-#define GPIO_CRH_CNF                         GPIO_CRH_CNF_Msk                  /*!< Port x configuration bits */
-
-#define GPIO_CRH_CNF8_Pos                    (2U)                              
-#define GPIO_CRH_CNF8_Msk                    (0x3U << GPIO_CRH_CNF8_Pos)       /*!< 0x0000000C */
-#define GPIO_CRH_CNF8                        GPIO_CRH_CNF8_Msk                 /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
-#define GPIO_CRH_CNF8_0                      (0x1U << GPIO_CRH_CNF8_Pos)       /*!< 0x00000004 */
-#define GPIO_CRH_CNF8_1                      (0x2U << GPIO_CRH_CNF8_Pos)       /*!< 0x00000008 */
-
-#define GPIO_CRH_CNF9_Pos                    (6U)                              
-#define GPIO_CRH_CNF9_Msk                    (0x3U << GPIO_CRH_CNF9_Pos)       /*!< 0x000000C0 */
-#define GPIO_CRH_CNF9                        GPIO_CRH_CNF9_Msk                 /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
-#define GPIO_CRH_CNF9_0                      (0x1U << GPIO_CRH_CNF9_Pos)       /*!< 0x00000040 */
-#define GPIO_CRH_CNF9_1                      (0x2U << GPIO_CRH_CNF9_Pos)       /*!< 0x00000080 */
-
-#define GPIO_CRH_CNF10_Pos                   (10U)                             
-#define GPIO_CRH_CNF10_Msk                   (0x3U << GPIO_CRH_CNF10_Pos)      /*!< 0x00000C00 */
-#define GPIO_CRH_CNF10                       GPIO_CRH_CNF10_Msk                /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
-#define GPIO_CRH_CNF10_0                     (0x1U << GPIO_CRH_CNF10_Pos)      /*!< 0x00000400 */
-#define GPIO_CRH_CNF10_1                     (0x2U << GPIO_CRH_CNF10_Pos)      /*!< 0x00000800 */
-
-#define GPIO_CRH_CNF11_Pos                   (14U)                             
-#define GPIO_CRH_CNF11_Msk                   (0x3U << GPIO_CRH_CNF11_Pos)      /*!< 0x0000C000 */
-#define GPIO_CRH_CNF11                       GPIO_CRH_CNF11_Msk                /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
-#define GPIO_CRH_CNF11_0                     (0x1U << GPIO_CRH_CNF11_Pos)      /*!< 0x00004000 */
-#define GPIO_CRH_CNF11_1                     (0x2U << GPIO_CRH_CNF11_Pos)      /*!< 0x00008000 */
-
-#define GPIO_CRH_CNF12_Pos                   (18U)                             
-#define GPIO_CRH_CNF12_Msk                   (0x3U << GPIO_CRH_CNF12_Pos)      /*!< 0x000C0000 */
-#define GPIO_CRH_CNF12                       GPIO_CRH_CNF12_Msk                /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
-#define GPIO_CRH_CNF12_0                     (0x1U << GPIO_CRH_CNF12_Pos)      /*!< 0x00040000 */
-#define GPIO_CRH_CNF12_1                     (0x2U << GPIO_CRH_CNF12_Pos)      /*!< 0x00080000 */
-
-#define GPIO_CRH_CNF13_Pos                   (22U)                             
-#define GPIO_CRH_CNF13_Msk                   (0x3U << GPIO_CRH_CNF13_Pos)      /*!< 0x00C00000 */
-#define GPIO_CRH_CNF13                       GPIO_CRH_CNF13_Msk                /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
-#define GPIO_CRH_CNF13_0                     (0x1U << GPIO_CRH_CNF13_Pos)      /*!< 0x00400000 */
-#define GPIO_CRH_CNF13_1                     (0x2U << GPIO_CRH_CNF13_Pos)      /*!< 0x00800000 */
-
-#define GPIO_CRH_CNF14_Pos                   (26U)                             
-#define GPIO_CRH_CNF14_Msk                   (0x3U << GPIO_CRH_CNF14_Pos)      /*!< 0x0C000000 */
-#define GPIO_CRH_CNF14                       GPIO_CRH_CNF14_Msk                /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
-#define GPIO_CRH_CNF14_0                     (0x1U << GPIO_CRH_CNF14_Pos)      /*!< 0x04000000 */
-#define GPIO_CRH_CNF14_1                     (0x2U << GPIO_CRH_CNF14_Pos)      /*!< 0x08000000 */
-
-#define GPIO_CRH_CNF15_Pos                   (30U)                             
-#define GPIO_CRH_CNF15_Msk                   (0x3U << GPIO_CRH_CNF15_Pos)      /*!< 0xC0000000 */
-#define GPIO_CRH_CNF15                       GPIO_CRH_CNF15_Msk                /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
-#define GPIO_CRH_CNF15_0                     (0x1U << GPIO_CRH_CNF15_Pos)      /*!< 0x40000000 */
-#define GPIO_CRH_CNF15_1                     (0x2U << GPIO_CRH_CNF15_Pos)      /*!< 0x80000000 */
-
-/*!<******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR0_Pos                    (0U)                              
-#define GPIO_IDR_IDR0_Msk                    (0x1U << GPIO_IDR_IDR0_Pos)       /*!< 0x00000001 */
-#define GPIO_IDR_IDR0                        GPIO_IDR_IDR0_Msk                 /*!< Port input data, bit 0 */
-#define GPIO_IDR_IDR1_Pos                    (1U)                              
-#define GPIO_IDR_IDR1_Msk                    (0x1U << GPIO_IDR_IDR1_Pos)       /*!< 0x00000002 */
-#define GPIO_IDR_IDR1                        GPIO_IDR_IDR1_Msk                 /*!< Port input data, bit 1 */
-#define GPIO_IDR_IDR2_Pos                    (2U)                              
-#define GPIO_IDR_IDR2_Msk                    (0x1U << GPIO_IDR_IDR2_Pos)       /*!< 0x00000004 */
-#define GPIO_IDR_IDR2                        GPIO_IDR_IDR2_Msk                 /*!< Port input data, bit 2 */
-#define GPIO_IDR_IDR3_Pos                    (3U)                              
-#define GPIO_IDR_IDR3_Msk                    (0x1U << GPIO_IDR_IDR3_Pos)       /*!< 0x00000008 */
-#define GPIO_IDR_IDR3                        GPIO_IDR_IDR3_Msk                 /*!< Port input data, bit 3 */
-#define GPIO_IDR_IDR4_Pos                    (4U)                              
-#define GPIO_IDR_IDR4_Msk                    (0x1U << GPIO_IDR_IDR4_Pos)       /*!< 0x00000010 */
-#define GPIO_IDR_IDR4                        GPIO_IDR_IDR4_Msk                 /*!< Port input data, bit 4 */
-#define GPIO_IDR_IDR5_Pos                    (5U)                              
-#define GPIO_IDR_IDR5_Msk                    (0x1U << GPIO_IDR_IDR5_Pos)       /*!< 0x00000020 */
-#define GPIO_IDR_IDR5                        GPIO_IDR_IDR5_Msk                 /*!< Port input data, bit 5 */
-#define GPIO_IDR_IDR6_Pos                    (6U)                              
-#define GPIO_IDR_IDR6_Msk                    (0x1U << GPIO_IDR_IDR6_Pos)       /*!< 0x00000040 */
-#define GPIO_IDR_IDR6                        GPIO_IDR_IDR6_Msk                 /*!< Port input data, bit 6 */
-#define GPIO_IDR_IDR7_Pos                    (7U)                              
-#define GPIO_IDR_IDR7_Msk                    (0x1U << GPIO_IDR_IDR7_Pos)       /*!< 0x00000080 */
-#define GPIO_IDR_IDR7                        GPIO_IDR_IDR7_Msk                 /*!< Port input data, bit 7 */
-#define GPIO_IDR_IDR8_Pos                    (8U)                              
-#define GPIO_IDR_IDR8_Msk                    (0x1U << GPIO_IDR_IDR8_Pos)       /*!< 0x00000100 */
-#define GPIO_IDR_IDR8                        GPIO_IDR_IDR8_Msk                 /*!< Port input data, bit 8 */
-#define GPIO_IDR_IDR9_Pos                    (9U)                              
-#define GPIO_IDR_IDR9_Msk                    (0x1U << GPIO_IDR_IDR9_Pos)       /*!< 0x00000200 */
-#define GPIO_IDR_IDR9                        GPIO_IDR_IDR9_Msk                 /*!< Port input data, bit 9 */
-#define GPIO_IDR_IDR10_Pos                   (10U)                             
-#define GPIO_IDR_IDR10_Msk                   (0x1U << GPIO_IDR_IDR10_Pos)      /*!< 0x00000400 */
-#define GPIO_IDR_IDR10                       GPIO_IDR_IDR10_Msk                /*!< Port input data, bit 10 */
-#define GPIO_IDR_IDR11_Pos                   (11U)                             
-#define GPIO_IDR_IDR11_Msk                   (0x1U << GPIO_IDR_IDR11_Pos)      /*!< 0x00000800 */
-#define GPIO_IDR_IDR11                       GPIO_IDR_IDR11_Msk                /*!< Port input data, bit 11 */
-#define GPIO_IDR_IDR12_Pos                   (12U)                             
-#define GPIO_IDR_IDR12_Msk                   (0x1U << GPIO_IDR_IDR12_Pos)      /*!< 0x00001000 */
-#define GPIO_IDR_IDR12                       GPIO_IDR_IDR12_Msk                /*!< Port input data, bit 12 */
-#define GPIO_IDR_IDR13_Pos                   (13U)                             
-#define GPIO_IDR_IDR13_Msk                   (0x1U << GPIO_IDR_IDR13_Pos)      /*!< 0x00002000 */
-#define GPIO_IDR_IDR13                       GPIO_IDR_IDR13_Msk                /*!< Port input data, bit 13 */
-#define GPIO_IDR_IDR14_Pos                   (14U)                             
-#define GPIO_IDR_IDR14_Msk                   (0x1U << GPIO_IDR_IDR14_Pos)      /*!< 0x00004000 */
-#define GPIO_IDR_IDR14                       GPIO_IDR_IDR14_Msk                /*!< Port input data, bit 14 */
-#define GPIO_IDR_IDR15_Pos                   (15U)                             
-#define GPIO_IDR_IDR15_Msk                   (0x1U << GPIO_IDR_IDR15_Pos)      /*!< 0x00008000 */
-#define GPIO_IDR_IDR15                       GPIO_IDR_IDR15_Msk                /*!< Port input data, bit 15 */
-
-/*******************  Bit definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR0_Pos                    (0U)                              
-#define GPIO_ODR_ODR0_Msk                    (0x1U << GPIO_ODR_ODR0_Pos)       /*!< 0x00000001 */
-#define GPIO_ODR_ODR0                        GPIO_ODR_ODR0_Msk                 /*!< Port output data, bit 0 */
-#define GPIO_ODR_ODR1_Pos                    (1U)                              
-#define GPIO_ODR_ODR1_Msk                    (0x1U << GPIO_ODR_ODR1_Pos)       /*!< 0x00000002 */
-#define GPIO_ODR_ODR1                        GPIO_ODR_ODR1_Msk                 /*!< Port output data, bit 1 */
-#define GPIO_ODR_ODR2_Pos                    (2U)                              
-#define GPIO_ODR_ODR2_Msk                    (0x1U << GPIO_ODR_ODR2_Pos)       /*!< 0x00000004 */
-#define GPIO_ODR_ODR2                        GPIO_ODR_ODR2_Msk                 /*!< Port output data, bit 2 */
-#define GPIO_ODR_ODR3_Pos                    (3U)                              
-#define GPIO_ODR_ODR3_Msk                    (0x1U << GPIO_ODR_ODR3_Pos)       /*!< 0x00000008 */
-#define GPIO_ODR_ODR3                        GPIO_ODR_ODR3_Msk                 /*!< Port output data, bit 3 */
-#define GPIO_ODR_ODR4_Pos                    (4U)                              
-#define GPIO_ODR_ODR4_Msk                    (0x1U << GPIO_ODR_ODR4_Pos)       /*!< 0x00000010 */
-#define GPIO_ODR_ODR4                        GPIO_ODR_ODR4_Msk                 /*!< Port output data, bit 4 */
-#define GPIO_ODR_ODR5_Pos                    (5U)                              
-#define GPIO_ODR_ODR5_Msk                    (0x1U << GPIO_ODR_ODR5_Pos)       /*!< 0x00000020 */
-#define GPIO_ODR_ODR5                        GPIO_ODR_ODR5_Msk                 /*!< Port output data, bit 5 */
-#define GPIO_ODR_ODR6_Pos                    (6U)                              
-#define GPIO_ODR_ODR6_Msk                    (0x1U << GPIO_ODR_ODR6_Pos)       /*!< 0x00000040 */
-#define GPIO_ODR_ODR6                        GPIO_ODR_ODR6_Msk                 /*!< Port output data, bit 6 */
-#define GPIO_ODR_ODR7_Pos                    (7U)                              
-#define GPIO_ODR_ODR7_Msk                    (0x1U << GPIO_ODR_ODR7_Pos)       /*!< 0x00000080 */
-#define GPIO_ODR_ODR7                        GPIO_ODR_ODR7_Msk                 /*!< Port output data, bit 7 */
-#define GPIO_ODR_ODR8_Pos                    (8U)                              
-#define GPIO_ODR_ODR8_Msk                    (0x1U << GPIO_ODR_ODR8_Pos)       /*!< 0x00000100 */
-#define GPIO_ODR_ODR8                        GPIO_ODR_ODR8_Msk                 /*!< Port output data, bit 8 */
-#define GPIO_ODR_ODR9_Pos                    (9U)                              
-#define GPIO_ODR_ODR9_Msk                    (0x1U << GPIO_ODR_ODR9_Pos)       /*!< 0x00000200 */
-#define GPIO_ODR_ODR9                        GPIO_ODR_ODR9_Msk                 /*!< Port output data, bit 9 */
-#define GPIO_ODR_ODR10_Pos                   (10U)                             
-#define GPIO_ODR_ODR10_Msk                   (0x1U << GPIO_ODR_ODR10_Pos)      /*!< 0x00000400 */
-#define GPIO_ODR_ODR10                       GPIO_ODR_ODR10_Msk                /*!< Port output data, bit 10 */
-#define GPIO_ODR_ODR11_Pos                   (11U)                             
-#define GPIO_ODR_ODR11_Msk                   (0x1U << GPIO_ODR_ODR11_Pos)      /*!< 0x00000800 */
-#define GPIO_ODR_ODR11                       GPIO_ODR_ODR11_Msk                /*!< Port output data, bit 11 */
-#define GPIO_ODR_ODR12_Pos                   (12U)                             
-#define GPIO_ODR_ODR12_Msk                   (0x1U << GPIO_ODR_ODR12_Pos)      /*!< 0x00001000 */
-#define GPIO_ODR_ODR12                       GPIO_ODR_ODR12_Msk                /*!< Port output data, bit 12 */
-#define GPIO_ODR_ODR13_Pos                   (13U)                             
-#define GPIO_ODR_ODR13_Msk                   (0x1U << GPIO_ODR_ODR13_Pos)      /*!< 0x00002000 */
-#define GPIO_ODR_ODR13                       GPIO_ODR_ODR13_Msk                /*!< Port output data, bit 13 */
-#define GPIO_ODR_ODR14_Pos                   (14U)                             
-#define GPIO_ODR_ODR14_Msk                   (0x1U << GPIO_ODR_ODR14_Pos)      /*!< 0x00004000 */
-#define GPIO_ODR_ODR14                       GPIO_ODR_ODR14_Msk                /*!< Port output data, bit 14 */
-#define GPIO_ODR_ODR15_Pos                   (15U)                             
-#define GPIO_ODR_ODR15_Msk                   (0x1U << GPIO_ODR_ODR15_Pos)      /*!< 0x00008000 */
-#define GPIO_ODR_ODR15                       GPIO_ODR_ODR15_Msk                /*!< Port output data, bit 15 */
-
-/******************  Bit definition for GPIO_BSRR register  *******************/
-#define GPIO_BSRR_BS0_Pos                    (0U)                              
-#define GPIO_BSRR_BS0_Msk                    (0x1U << GPIO_BSRR_BS0_Pos)       /*!< 0x00000001 */
-#define GPIO_BSRR_BS0                        GPIO_BSRR_BS0_Msk                 /*!< Port x Set bit 0 */
-#define GPIO_BSRR_BS1_Pos                    (1U)                              
-#define GPIO_BSRR_BS1_Msk                    (0x1U << GPIO_BSRR_BS1_Pos)       /*!< 0x00000002 */
-#define GPIO_BSRR_BS1                        GPIO_BSRR_BS1_Msk                 /*!< Port x Set bit 1 */
-#define GPIO_BSRR_BS2_Pos                    (2U)                              
-#define GPIO_BSRR_BS2_Msk                    (0x1U << GPIO_BSRR_BS2_Pos)       /*!< 0x00000004 */
-#define GPIO_BSRR_BS2                        GPIO_BSRR_BS2_Msk                 /*!< Port x Set bit 2 */
-#define GPIO_BSRR_BS3_Pos                    (3U)                              
-#define GPIO_BSRR_BS3_Msk                    (0x1U << GPIO_BSRR_BS3_Pos)       /*!< 0x00000008 */
-#define GPIO_BSRR_BS3                        GPIO_BSRR_BS3_Msk                 /*!< Port x Set bit 3 */
-#define GPIO_BSRR_BS4_Pos                    (4U)                              
-#define GPIO_BSRR_BS4_Msk                    (0x1U << GPIO_BSRR_BS4_Pos)       /*!< 0x00000010 */
-#define GPIO_BSRR_BS4                        GPIO_BSRR_BS4_Msk                 /*!< Port x Set bit 4 */
-#define GPIO_BSRR_BS5_Pos                    (5U)                              
-#define GPIO_BSRR_BS5_Msk                    (0x1U << GPIO_BSRR_BS5_Pos)       /*!< 0x00000020 */
-#define GPIO_BSRR_BS5                        GPIO_BSRR_BS5_Msk                 /*!< Port x Set bit 5 */
-#define GPIO_BSRR_BS6_Pos                    (6U)                              
-#define GPIO_BSRR_BS6_Msk                    (0x1U << GPIO_BSRR_BS6_Pos)       /*!< 0x00000040 */
-#define GPIO_BSRR_BS6                        GPIO_BSRR_BS6_Msk                 /*!< Port x Set bit 6 */
-#define GPIO_BSRR_BS7_Pos                    (7U)                              
-#define GPIO_BSRR_BS7_Msk                    (0x1U << GPIO_BSRR_BS7_Pos)       /*!< 0x00000080 */
-#define GPIO_BSRR_BS7                        GPIO_BSRR_BS7_Msk                 /*!< Port x Set bit 7 */
-#define GPIO_BSRR_BS8_Pos                    (8U)                              
-#define GPIO_BSRR_BS8_Msk                    (0x1U << GPIO_BSRR_BS8_Pos)       /*!< 0x00000100 */
-#define GPIO_BSRR_BS8                        GPIO_BSRR_BS8_Msk                 /*!< Port x Set bit 8 */
-#define GPIO_BSRR_BS9_Pos                    (9U)                              
-#define GPIO_BSRR_BS9_Msk                    (0x1U << GPIO_BSRR_BS9_Pos)       /*!< 0x00000200 */
-#define GPIO_BSRR_BS9                        GPIO_BSRR_BS9_Msk                 /*!< Port x Set bit 9 */
-#define GPIO_BSRR_BS10_Pos                   (10U)                             
-#define GPIO_BSRR_BS10_Msk                   (0x1U << GPIO_BSRR_BS10_Pos)      /*!< 0x00000400 */
-#define GPIO_BSRR_BS10                       GPIO_BSRR_BS10_Msk                /*!< Port x Set bit 10 */
-#define GPIO_BSRR_BS11_Pos                   (11U)                             
-#define GPIO_BSRR_BS11_Msk                   (0x1U << GPIO_BSRR_BS11_Pos)      /*!< 0x00000800 */
-#define GPIO_BSRR_BS11                       GPIO_BSRR_BS11_Msk                /*!< Port x Set bit 11 */
-#define GPIO_BSRR_BS12_Pos                   (12U)                             
-#define GPIO_BSRR_BS12_Msk                   (0x1U << GPIO_BSRR_BS12_Pos)      /*!< 0x00001000 */
-#define GPIO_BSRR_BS12                       GPIO_BSRR_BS12_Msk                /*!< Port x Set bit 12 */
-#define GPIO_BSRR_BS13_Pos                   (13U)                             
-#define GPIO_BSRR_BS13_Msk                   (0x1U << GPIO_BSRR_BS13_Pos)      /*!< 0x00002000 */
-#define GPIO_BSRR_BS13                       GPIO_BSRR_BS13_Msk                /*!< Port x Set bit 13 */
-#define GPIO_BSRR_BS14_Pos                   (14U)                             
-#define GPIO_BSRR_BS14_Msk                   (0x1U << GPIO_BSRR_BS14_Pos)      /*!< 0x00004000 */
-#define GPIO_BSRR_BS14                       GPIO_BSRR_BS14_Msk                /*!< Port x Set bit 14 */
-#define GPIO_BSRR_BS15_Pos                   (15U)                             
-#define GPIO_BSRR_BS15_Msk                   (0x1U << GPIO_BSRR_BS15_Pos)      /*!< 0x00008000 */
-#define GPIO_BSRR_BS15                       GPIO_BSRR_BS15_Msk                /*!< Port x Set bit 15 */
-
-#define GPIO_BSRR_BR0_Pos                    (16U)                             
-#define GPIO_BSRR_BR0_Msk                    (0x1U << GPIO_BSRR_BR0_Pos)       /*!< 0x00010000 */
-#define GPIO_BSRR_BR0                        GPIO_BSRR_BR0_Msk                 /*!< Port x Reset bit 0 */
-#define GPIO_BSRR_BR1_Pos                    (17U)                             
-#define GPIO_BSRR_BR1_Msk                    (0x1U << GPIO_BSRR_BR1_Pos)       /*!< 0x00020000 */
-#define GPIO_BSRR_BR1                        GPIO_BSRR_BR1_Msk                 /*!< Port x Reset bit 1 */
-#define GPIO_BSRR_BR2_Pos                    (18U)                             
-#define GPIO_BSRR_BR2_Msk                    (0x1U << GPIO_BSRR_BR2_Pos)       /*!< 0x00040000 */
-#define GPIO_BSRR_BR2                        GPIO_BSRR_BR2_Msk                 /*!< Port x Reset bit 2 */
-#define GPIO_BSRR_BR3_Pos                    (19U)                             
-#define GPIO_BSRR_BR3_Msk                    (0x1U << GPIO_BSRR_BR3_Pos)       /*!< 0x00080000 */
-#define GPIO_BSRR_BR3                        GPIO_BSRR_BR3_Msk                 /*!< Port x Reset bit 3 */
-#define GPIO_BSRR_BR4_Pos                    (20U)                             
-#define GPIO_BSRR_BR4_Msk                    (0x1U << GPIO_BSRR_BR4_Pos)       /*!< 0x00100000 */
-#define GPIO_BSRR_BR4                        GPIO_BSRR_BR4_Msk                 /*!< Port x Reset bit 4 */
-#define GPIO_BSRR_BR5_Pos                    (21U)                             
-#define GPIO_BSRR_BR5_Msk                    (0x1U << GPIO_BSRR_BR5_Pos)       /*!< 0x00200000 */
-#define GPIO_BSRR_BR5                        GPIO_BSRR_BR5_Msk                 /*!< Port x Reset bit 5 */
-#define GPIO_BSRR_BR6_Pos                    (22U)                             
-#define GPIO_BSRR_BR6_Msk                    (0x1U << GPIO_BSRR_BR6_Pos)       /*!< 0x00400000 */
-#define GPIO_BSRR_BR6                        GPIO_BSRR_BR6_Msk                 /*!< Port x Reset bit 6 */
-#define GPIO_BSRR_BR7_Pos                    (23U)                             
-#define GPIO_BSRR_BR7_Msk                    (0x1U << GPIO_BSRR_BR7_Pos)       /*!< 0x00800000 */
-#define GPIO_BSRR_BR7                        GPIO_BSRR_BR7_Msk                 /*!< Port x Reset bit 7 */
-#define GPIO_BSRR_BR8_Pos                    (24U)                             
-#define GPIO_BSRR_BR8_Msk                    (0x1U << GPIO_BSRR_BR8_Pos)       /*!< 0x01000000 */
-#define GPIO_BSRR_BR8                        GPIO_BSRR_BR8_Msk                 /*!< Port x Reset bit 8 */
-#define GPIO_BSRR_BR9_Pos                    (25U)                             
-#define GPIO_BSRR_BR9_Msk                    (0x1U << GPIO_BSRR_BR9_Pos)       /*!< 0x02000000 */
-#define GPIO_BSRR_BR9                        GPIO_BSRR_BR9_Msk                 /*!< Port x Reset bit 9 */
-#define GPIO_BSRR_BR10_Pos                   (26U)                             
-#define GPIO_BSRR_BR10_Msk                   (0x1U << GPIO_BSRR_BR10_Pos)      /*!< 0x04000000 */
-#define GPIO_BSRR_BR10                       GPIO_BSRR_BR10_Msk                /*!< Port x Reset bit 10 */
-#define GPIO_BSRR_BR11_Pos                   (27U)                             
-#define GPIO_BSRR_BR11_Msk                   (0x1U << GPIO_BSRR_BR11_Pos)      /*!< 0x08000000 */
-#define GPIO_BSRR_BR11                       GPIO_BSRR_BR11_Msk                /*!< Port x Reset bit 11 */
-#define GPIO_BSRR_BR12_Pos                   (28U)                             
-#define GPIO_BSRR_BR12_Msk                   (0x1U << GPIO_BSRR_BR12_Pos)      /*!< 0x10000000 */
-#define GPIO_BSRR_BR12                       GPIO_BSRR_BR12_Msk                /*!< Port x Reset bit 12 */
-#define GPIO_BSRR_BR13_Pos                   (29U)                             
-#define GPIO_BSRR_BR13_Msk                   (0x1U << GPIO_BSRR_BR13_Pos)      /*!< 0x20000000 */
-#define GPIO_BSRR_BR13                       GPIO_BSRR_BR13_Msk                /*!< Port x Reset bit 13 */
-#define GPIO_BSRR_BR14_Pos                   (30U)                             
-#define GPIO_BSRR_BR14_Msk                   (0x1U << GPIO_BSRR_BR14_Pos)      /*!< 0x40000000 */
-#define GPIO_BSRR_BR14                       GPIO_BSRR_BR14_Msk                /*!< Port x Reset bit 14 */
-#define GPIO_BSRR_BR15_Pos                   (31U)                             
-#define GPIO_BSRR_BR15_Msk                   (0x1U << GPIO_BSRR_BR15_Pos)      /*!< 0x80000000 */
-#define GPIO_BSRR_BR15                       GPIO_BSRR_BR15_Msk                /*!< Port x Reset bit 15 */
-
-/*******************  Bit definition for GPIO_BRR register  *******************/
-#define GPIO_BRR_BR0_Pos                     (0U)                              
-#define GPIO_BRR_BR0_Msk                     (0x1U << GPIO_BRR_BR0_Pos)        /*!< 0x00000001 */
-#define GPIO_BRR_BR0                         GPIO_BRR_BR0_Msk                  /*!< Port x Reset bit 0 */
-#define GPIO_BRR_BR1_Pos                     (1U)                              
-#define GPIO_BRR_BR1_Msk                     (0x1U << GPIO_BRR_BR1_Pos)        /*!< 0x00000002 */
-#define GPIO_BRR_BR1                         GPIO_BRR_BR1_Msk                  /*!< Port x Reset bit 1 */
-#define GPIO_BRR_BR2_Pos                     (2U)                              
-#define GPIO_BRR_BR2_Msk                     (0x1U << GPIO_BRR_BR2_Pos)        /*!< 0x00000004 */
-#define GPIO_BRR_BR2                         GPIO_BRR_BR2_Msk                  /*!< Port x Reset bit 2 */
-#define GPIO_BRR_BR3_Pos                     (3U)                              
-#define GPIO_BRR_BR3_Msk                     (0x1U << GPIO_BRR_BR3_Pos)        /*!< 0x00000008 */
-#define GPIO_BRR_BR3                         GPIO_BRR_BR3_Msk                  /*!< Port x Reset bit 3 */
-#define GPIO_BRR_BR4_Pos                     (4U)                              
-#define GPIO_BRR_BR4_Msk                     (0x1U << GPIO_BRR_BR4_Pos)        /*!< 0x00000010 */
-#define GPIO_BRR_BR4                         GPIO_BRR_BR4_Msk                  /*!< Port x Reset bit 4 */
-#define GPIO_BRR_BR5_Pos                     (5U)                              
-#define GPIO_BRR_BR5_Msk                     (0x1U << GPIO_BRR_BR5_Pos)        /*!< 0x00000020 */
-#define GPIO_BRR_BR5                         GPIO_BRR_BR5_Msk                  /*!< Port x Reset bit 5 */
-#define GPIO_BRR_BR6_Pos                     (6U)                              
-#define GPIO_BRR_BR6_Msk                     (0x1U << GPIO_BRR_BR6_Pos)        /*!< 0x00000040 */
-#define GPIO_BRR_BR6                         GPIO_BRR_BR6_Msk                  /*!< Port x Reset bit 6 */
-#define GPIO_BRR_BR7_Pos                     (7U)                              
-#define GPIO_BRR_BR7_Msk                     (0x1U << GPIO_BRR_BR7_Pos)        /*!< 0x00000080 */
-#define GPIO_BRR_BR7                         GPIO_BRR_BR7_Msk                  /*!< Port x Reset bit 7 */
-#define GPIO_BRR_BR8_Pos                     (8U)                              
-#define GPIO_BRR_BR8_Msk                     (0x1U << GPIO_BRR_BR8_Pos)        /*!< 0x00000100 */
-#define GPIO_BRR_BR8                         GPIO_BRR_BR8_Msk                  /*!< Port x Reset bit 8 */
-#define GPIO_BRR_BR9_Pos                     (9U)                              
-#define GPIO_BRR_BR9_Msk                     (0x1U << GPIO_BRR_BR9_Pos)        /*!< 0x00000200 */
-#define GPIO_BRR_BR9                         GPIO_BRR_BR9_Msk                  /*!< Port x Reset bit 9 */
-#define GPIO_BRR_BR10_Pos                    (10U)                             
-#define GPIO_BRR_BR10_Msk                    (0x1U << GPIO_BRR_BR10_Pos)       /*!< 0x00000400 */
-#define GPIO_BRR_BR10                        GPIO_BRR_BR10_Msk                 /*!< Port x Reset bit 10 */
-#define GPIO_BRR_BR11_Pos                    (11U)                             
-#define GPIO_BRR_BR11_Msk                    (0x1U << GPIO_BRR_BR11_Pos)       /*!< 0x00000800 */
-#define GPIO_BRR_BR11                        GPIO_BRR_BR11_Msk                 /*!< Port x Reset bit 11 */
-#define GPIO_BRR_BR12_Pos                    (12U)                             
-#define GPIO_BRR_BR12_Msk                    (0x1U << GPIO_BRR_BR12_Pos)       /*!< 0x00001000 */
-#define GPIO_BRR_BR12                        GPIO_BRR_BR12_Msk                 /*!< Port x Reset bit 12 */
-#define GPIO_BRR_BR13_Pos                    (13U)                             
-#define GPIO_BRR_BR13_Msk                    (0x1U << GPIO_BRR_BR13_Pos)       /*!< 0x00002000 */
-#define GPIO_BRR_BR13                        GPIO_BRR_BR13_Msk                 /*!< Port x Reset bit 13 */
-#define GPIO_BRR_BR14_Pos                    (14U)                             
-#define GPIO_BRR_BR14_Msk                    (0x1U << GPIO_BRR_BR14_Pos)       /*!< 0x00004000 */
-#define GPIO_BRR_BR14                        GPIO_BRR_BR14_Msk                 /*!< Port x Reset bit 14 */
-#define GPIO_BRR_BR15_Pos                    (15U)                             
-#define GPIO_BRR_BR15_Msk                    (0x1U << GPIO_BRR_BR15_Pos)       /*!< 0x00008000 */
-#define GPIO_BRR_BR15                        GPIO_BRR_BR15_Msk                 /*!< Port x Reset bit 15 */
-
-/******************  Bit definition for GPIO_LCKR register  *******************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1U << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                /*!< Port x Lock bit 0 */
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1U << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                /*!< Port x Lock bit 1 */
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1U << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                /*!< Port x Lock bit 2 */
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1U << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                /*!< Port x Lock bit 3 */
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1U << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                /*!< Port x Lock bit 4 */
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1U << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                /*!< Port x Lock bit 5 */
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1U << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                /*!< Port x Lock bit 6 */
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1U << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                /*!< Port x Lock bit 7 */
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1U << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                /*!< Port x Lock bit 8 */
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1U << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                /*!< Port x Lock bit 9 */
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1U << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               /*!< Port x Lock bit 10 */
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1U << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               /*!< Port x Lock bit 11 */
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1U << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               /*!< Port x Lock bit 12 */
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1U << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               /*!< Port x Lock bit 13 */
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1U << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               /*!< Port x Lock bit 14 */
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1U << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               /*!< Port x Lock bit 15 */
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1U << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                /*!< Lock key */
-
-/*----------------------------------------------------------------------------*/
-
-/******************  Bit definition for AFIO_EVCR register  *******************/
-#define AFIO_EVCR_PIN_Pos                    (0U)                              
-#define AFIO_EVCR_PIN_Msk                    (0xFU << AFIO_EVCR_PIN_Pos)       /*!< 0x0000000F */
-#define AFIO_EVCR_PIN                        AFIO_EVCR_PIN_Msk                 /*!< PIN[3:0] bits (Pin selection) */
-#define AFIO_EVCR_PIN_0                      (0x1U << AFIO_EVCR_PIN_Pos)       /*!< 0x00000001 */
-#define AFIO_EVCR_PIN_1                      (0x2U << AFIO_EVCR_PIN_Pos)       /*!< 0x00000002 */
-#define AFIO_EVCR_PIN_2                      (0x4U << AFIO_EVCR_PIN_Pos)       /*!< 0x00000004 */
-#define AFIO_EVCR_PIN_3                      (0x8U << AFIO_EVCR_PIN_Pos)       /*!< 0x00000008 */
-
-/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0                    ((uint32_t)0x00000000)            /*!< Pin 0 selected */
-#define AFIO_EVCR_PIN_PX1_Pos                (0U)                              
-#define AFIO_EVCR_PIN_PX1_Msk                (0x1U << AFIO_EVCR_PIN_PX1_Pos)   /*!< 0x00000001 */
-#define AFIO_EVCR_PIN_PX1                    AFIO_EVCR_PIN_PX1_Msk             /*!< Pin 1 selected */
-#define AFIO_EVCR_PIN_PX2_Pos                (1U)                              
-#define AFIO_EVCR_PIN_PX2_Msk                (0x1U << AFIO_EVCR_PIN_PX2_Pos)   /*!< 0x00000002 */
-#define AFIO_EVCR_PIN_PX2                    AFIO_EVCR_PIN_PX2_Msk             /*!< Pin 2 selected */
-#define AFIO_EVCR_PIN_PX3_Pos                (0U)                              
-#define AFIO_EVCR_PIN_PX3_Msk                (0x3U << AFIO_EVCR_PIN_PX3_Pos)   /*!< 0x00000003 */
-#define AFIO_EVCR_PIN_PX3                    AFIO_EVCR_PIN_PX3_Msk             /*!< Pin 3 selected */
-#define AFIO_EVCR_PIN_PX4_Pos                (2U)                              
-#define AFIO_EVCR_PIN_PX4_Msk                (0x1U << AFIO_EVCR_PIN_PX4_Pos)   /*!< 0x00000004 */
-#define AFIO_EVCR_PIN_PX4                    AFIO_EVCR_PIN_PX4_Msk             /*!< Pin 4 selected */
-#define AFIO_EVCR_PIN_PX5_Pos                (0U)                              
-#define AFIO_EVCR_PIN_PX5_Msk                (0x5U << AFIO_EVCR_PIN_PX5_Pos)   /*!< 0x00000005 */
-#define AFIO_EVCR_PIN_PX5                    AFIO_EVCR_PIN_PX5_Msk             /*!< Pin 5 selected */
-#define AFIO_EVCR_PIN_PX6_Pos                (1U)                              
-#define AFIO_EVCR_PIN_PX6_Msk                (0x3U << AFIO_EVCR_PIN_PX6_Pos)   /*!< 0x00000006 */
-#define AFIO_EVCR_PIN_PX6                    AFIO_EVCR_PIN_PX6_Msk             /*!< Pin 6 selected */
-#define AFIO_EVCR_PIN_PX7_Pos                (0U)                              
-#define AFIO_EVCR_PIN_PX7_Msk                (0x7U << AFIO_EVCR_PIN_PX7_Pos)   /*!< 0x00000007 */
-#define AFIO_EVCR_PIN_PX7                    AFIO_EVCR_PIN_PX7_Msk             /*!< Pin 7 selected */
-#define AFIO_EVCR_PIN_PX8_Pos                (3U)                              
-#define AFIO_EVCR_PIN_PX8_Msk                (0x1U << AFIO_EVCR_PIN_PX8_Pos)   /*!< 0x00000008 */
-#define AFIO_EVCR_PIN_PX8                    AFIO_EVCR_PIN_PX8_Msk             /*!< Pin 8 selected */
-#define AFIO_EVCR_PIN_PX9_Pos                (0U)                              
-#define AFIO_EVCR_PIN_PX9_Msk                (0x9U << AFIO_EVCR_PIN_PX9_Pos)   /*!< 0x00000009 */
-#define AFIO_EVCR_PIN_PX9                    AFIO_EVCR_PIN_PX9_Msk             /*!< Pin 9 selected */
-#define AFIO_EVCR_PIN_PX10_Pos               (1U)                              
-#define AFIO_EVCR_PIN_PX10_Msk               (0x5U << AFIO_EVCR_PIN_PX10_Pos)  /*!< 0x0000000A */
-#define AFIO_EVCR_PIN_PX10                   AFIO_EVCR_PIN_PX10_Msk            /*!< Pin 10 selected */
-#define AFIO_EVCR_PIN_PX11_Pos               (0U)                              
-#define AFIO_EVCR_PIN_PX11_Msk               (0xBU << AFIO_EVCR_PIN_PX11_Pos)  /*!< 0x0000000B */
-#define AFIO_EVCR_PIN_PX11                   AFIO_EVCR_PIN_PX11_Msk            /*!< Pin 11 selected */
-#define AFIO_EVCR_PIN_PX12_Pos               (2U)                              
-#define AFIO_EVCR_PIN_PX12_Msk               (0x3U << AFIO_EVCR_PIN_PX12_Pos)  /*!< 0x0000000C */
-#define AFIO_EVCR_PIN_PX12                   AFIO_EVCR_PIN_PX12_Msk            /*!< Pin 12 selected */
-#define AFIO_EVCR_PIN_PX13_Pos               (0U)                              
-#define AFIO_EVCR_PIN_PX13_Msk               (0xDU << AFIO_EVCR_PIN_PX13_Pos)  /*!< 0x0000000D */
-#define AFIO_EVCR_PIN_PX13                   AFIO_EVCR_PIN_PX13_Msk            /*!< Pin 13 selected */
-#define AFIO_EVCR_PIN_PX14_Pos               (1U)                              
-#define AFIO_EVCR_PIN_PX14_Msk               (0x7U << AFIO_EVCR_PIN_PX14_Pos)  /*!< 0x0000000E */
-#define AFIO_EVCR_PIN_PX14                   AFIO_EVCR_PIN_PX14_Msk            /*!< Pin 14 selected */
-#define AFIO_EVCR_PIN_PX15_Pos               (0U)                              
-#define AFIO_EVCR_PIN_PX15_Msk               (0xFU << AFIO_EVCR_PIN_PX15_Pos)  /*!< 0x0000000F */
-#define AFIO_EVCR_PIN_PX15                   AFIO_EVCR_PIN_PX15_Msk            /*!< Pin 15 selected */
-
-#define AFIO_EVCR_PORT_Pos                   (4U)                              
-#define AFIO_EVCR_PORT_Msk                   (0x7U << AFIO_EVCR_PORT_Pos)      /*!< 0x00000070 */
-#define AFIO_EVCR_PORT                       AFIO_EVCR_PORT_Msk                /*!< PORT[2:0] bits (Port selection) */
-#define AFIO_EVCR_PORT_0                     (0x1U << AFIO_EVCR_PORT_Pos)      /*!< 0x00000010 */
-#define AFIO_EVCR_PORT_1                     (0x2U << AFIO_EVCR_PORT_Pos)      /*!< 0x00000020 */
-#define AFIO_EVCR_PORT_2                     (0x4U << AFIO_EVCR_PORT_Pos)      /*!< 0x00000040 */
-
-/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA                    ((uint32_t)0x00000000)            /*!< Port A selected */
-#define AFIO_EVCR_PORT_PB_Pos                (4U)                              
-#define AFIO_EVCR_PORT_PB_Msk                (0x1U << AFIO_EVCR_PORT_PB_Pos)   /*!< 0x00000010 */
-#define AFIO_EVCR_PORT_PB                    AFIO_EVCR_PORT_PB_Msk             /*!< Port B selected */
-#define AFIO_EVCR_PORT_PC_Pos                (5U)                              
-#define AFIO_EVCR_PORT_PC_Msk                (0x1U << AFIO_EVCR_PORT_PC_Pos)   /*!< 0x00000020 */
-#define AFIO_EVCR_PORT_PC                    AFIO_EVCR_PORT_PC_Msk             /*!< Port C selected */
-#define AFIO_EVCR_PORT_PD_Pos                (4U)                              
-#define AFIO_EVCR_PORT_PD_Msk                (0x3U << AFIO_EVCR_PORT_PD_Pos)   /*!< 0x00000030 */
-#define AFIO_EVCR_PORT_PD                    AFIO_EVCR_PORT_PD_Msk             /*!< Port D selected */
-#define AFIO_EVCR_PORT_PE_Pos                (6U)                              
-#define AFIO_EVCR_PORT_PE_Msk                (0x1U << AFIO_EVCR_PORT_PE_Pos)   /*!< 0x00000040 */
-#define AFIO_EVCR_PORT_PE                    AFIO_EVCR_PORT_PE_Msk             /*!< Port E selected */
-
-#define AFIO_EVCR_EVOE_Pos                   (7U)                              
-#define AFIO_EVCR_EVOE_Msk                   (0x1U << AFIO_EVCR_EVOE_Pos)      /*!< 0x00000080 */
-#define AFIO_EVCR_EVOE                       AFIO_EVCR_EVOE_Msk                /*!< Event Output Enable */
-
-/******************  Bit definition for AFIO_MAPR register  *******************/
-#define AFIO_MAPR_SPI1_REMAP_Pos             (0U)                              
-#define AFIO_MAPR_SPI1_REMAP_Msk             (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
-#define AFIO_MAPR_SPI1_REMAP                 AFIO_MAPR_SPI1_REMAP_Msk          /*!< SPI1 remapping */
-#define AFIO_MAPR_I2C1_REMAP_Pos             (1U)                              
-#define AFIO_MAPR_I2C1_REMAP_Msk             (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
-#define AFIO_MAPR_I2C1_REMAP                 AFIO_MAPR_I2C1_REMAP_Msk          /*!< I2C1 remapping */
-#define AFIO_MAPR_USART1_REMAP_Pos           (2U)                              
-#define AFIO_MAPR_USART1_REMAP_Msk           (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
-#define AFIO_MAPR_USART1_REMAP               AFIO_MAPR_USART1_REMAP_Msk        /*!< USART1 remapping */
-#define AFIO_MAPR_USART2_REMAP_Pos           (3U)                              
-#define AFIO_MAPR_USART2_REMAP_Msk           (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
-#define AFIO_MAPR_USART2_REMAP               AFIO_MAPR_USART2_REMAP_Msk        /*!< USART2 remapping */
-
-#define AFIO_MAPR_USART3_REMAP_Pos           (4U)                              
-#define AFIO_MAPR_USART3_REMAP_Msk           (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
-#define AFIO_MAPR_USART3_REMAP               AFIO_MAPR_USART3_REMAP_Msk        /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
-#define AFIO_MAPR_USART3_REMAP_0             (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
-#define AFIO_MAPR_USART3_REMAP_1             (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
-
-/* USART3_REMAP configuration */
-#define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)            /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
-#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)                           
-#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
-#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
-#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)                              
-#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
-#define AFIO_MAPR_USART3_REMAP_FULLREMAP     AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
-
-#define AFIO_MAPR_TIM1_REMAP_Pos             (6U)                              
-#define AFIO_MAPR_TIM1_REMAP_Msk             (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
-#define AFIO_MAPR_TIM1_REMAP                 AFIO_MAPR_TIM1_REMAP_Msk          /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
-#define AFIO_MAPR_TIM1_REMAP_0               (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
-#define AFIO_MAPR_TIM1_REMAP_1               (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
-
-/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
-#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)                             
-#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
-#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
-#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos   (6U)                              
-#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk   (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
-#define AFIO_MAPR_TIM1_REMAP_FULLREMAP       AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
-
-#define AFIO_MAPR_TIM2_REMAP_Pos             (8U)                              
-#define AFIO_MAPR_TIM2_REMAP_Msk             (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
-#define AFIO_MAPR_TIM2_REMAP                 AFIO_MAPR_TIM2_REMAP_Msk          /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
-#define AFIO_MAPR_TIM2_REMAP_0               (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
-#define AFIO_MAPR_TIM2_REMAP_1               (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
-
-/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)                            
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)                            
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
-#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos   (8U)                              
-#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk   (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
-#define AFIO_MAPR_TIM2_REMAP_FULLREMAP       AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
-
-#define AFIO_MAPR_TIM3_REMAP_Pos             (10U)                             
-#define AFIO_MAPR_TIM3_REMAP_Msk             (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
-#define AFIO_MAPR_TIM3_REMAP                 AFIO_MAPR_TIM3_REMAP_Msk          /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
-#define AFIO_MAPR_TIM3_REMAP_0               (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
-#define AFIO_MAPR_TIM3_REMAP_1               (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
-
-/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)                            
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
-#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos   (10U)                             
-#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk   (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
-#define AFIO_MAPR_TIM3_REMAP_FULLREMAP       AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
-
-#define AFIO_MAPR_TIM4_REMAP_Pos             (12U)                             
-#define AFIO_MAPR_TIM4_REMAP_Msk             (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
-#define AFIO_MAPR_TIM4_REMAP                 AFIO_MAPR_TIM4_REMAP_Msk          /*!< TIM4_REMAP bit (TIM4 remapping) */
-
-#define AFIO_MAPR_CAN_REMAP_Pos              (13U)                             
-#define AFIO_MAPR_CAN_REMAP_Msk              (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */
-#define AFIO_MAPR_CAN_REMAP                  AFIO_MAPR_CAN_REMAP_Msk           /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
-#define AFIO_MAPR_CAN_REMAP_0                (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */
-#define AFIO_MAPR_CAN_REMAP_1                (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
-
-/*!< CAN_REMAP configuration */
-#define AFIO_MAPR_CAN_REMAP_REMAP1           ((uint32_t)0x00000000)            /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
-#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos       (14U)                             
-#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk       (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
-#define AFIO_MAPR_CAN_REMAP_REMAP2           AFIO_MAPR_CAN_REMAP_REMAP2_Msk    /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
-#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos       (13U)                             
-#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk       (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */
-#define AFIO_MAPR_CAN_REMAP_REMAP3           AFIO_MAPR_CAN_REMAP_REMAP3_Msk    /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
-
-#define AFIO_MAPR_PD01_REMAP_Pos             (15U)                             
-#define AFIO_MAPR_PD01_REMAP_Msk             (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
-#define AFIO_MAPR_PD01_REMAP                 AFIO_MAPR_PD01_REMAP_Msk          /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
-
-/*!< SWJ_CFG configuration */
-#define AFIO_MAPR_SWJ_CFG_Pos                (24U)                             
-#define AFIO_MAPR_SWJ_CFG_Msk                (0x7U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x07000000 */
-#define AFIO_MAPR_SWJ_CFG                    AFIO_MAPR_SWJ_CFG_Msk             /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
-#define AFIO_MAPR_SWJ_CFG_0                  (0x1U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x01000000 */
-#define AFIO_MAPR_SWJ_CFG_1                  (0x2U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x02000000 */
-#define AFIO_MAPR_SWJ_CFG_2                  (0x4U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x04000000 */
-
-#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)            /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
-#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos       (24U)                             
-#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk       (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
-#define AFIO_MAPR_SWJ_CFG_NOJNTRST           AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos    (25U)                             
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk    (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE        AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
-#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos        (26U)                             
-#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk        (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
-#define AFIO_MAPR_SWJ_CFG_DISABLE            AFIO_MAPR_SWJ_CFG_DISABLE_Msk     /*!< JTAG-DP Disabled and SW-DP Disabled */
-
-
-/*****************  Bit definition for AFIO_EXTICR1 register  *****************/
-#define AFIO_EXTICR1_EXTI0_Pos               (0U)                              
-#define AFIO_EXTICR1_EXTI0_Msk               (0xFU << AFIO_EXTICR1_EXTI0_Pos)  /*!< 0x0000000F */
-#define AFIO_EXTICR1_EXTI0                   AFIO_EXTICR1_EXTI0_Msk            /*!< EXTI 0 configuration */
-#define AFIO_EXTICR1_EXTI1_Pos               (4U)                              
-#define AFIO_EXTICR1_EXTI1_Msk               (0xFU << AFIO_EXTICR1_EXTI1_Pos)  /*!< 0x000000F0 */
-#define AFIO_EXTICR1_EXTI1                   AFIO_EXTICR1_EXTI1_Msk            /*!< EXTI 1 configuration */
-#define AFIO_EXTICR1_EXTI2_Pos               (8U)                              
-#define AFIO_EXTICR1_EXTI2_Msk               (0xFU << AFIO_EXTICR1_EXTI2_Pos)  /*!< 0x00000F00 */
-#define AFIO_EXTICR1_EXTI2                   AFIO_EXTICR1_EXTI2_Msk            /*!< EXTI 2 configuration */
-#define AFIO_EXTICR1_EXTI3_Pos               (12U)                             
-#define AFIO_EXTICR1_EXTI3_Msk               (0xFU << AFIO_EXTICR1_EXTI3_Pos)  /*!< 0x0000F000 */
-#define AFIO_EXTICR1_EXTI3                   AFIO_EXTICR1_EXTI3_Msk            /*!< EXTI 3 configuration */
-
-/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA                ((uint32_t)0x00000000)            /*!< PA[0] pin */
-#define AFIO_EXTICR1_EXTI0_PB_Pos            (0U)                              
-#define AFIO_EXTICR1_EXTI0_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
-#define AFIO_EXTICR1_EXTI0_PB                AFIO_EXTICR1_EXTI0_PB_Msk         /*!< PB[0] pin */
-#define AFIO_EXTICR1_EXTI0_PC_Pos            (1U)                              
-#define AFIO_EXTICR1_EXTI0_PC_Msk            (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
-#define AFIO_EXTICR1_EXTI0_PC                AFIO_EXTICR1_EXTI0_PC_Msk         /*!< PC[0] pin */
-#define AFIO_EXTICR1_EXTI0_PD_Pos            (0U)                              
-#define AFIO_EXTICR1_EXTI0_PD_Msk            (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
-#define AFIO_EXTICR1_EXTI0_PD                AFIO_EXTICR1_EXTI0_PD_Msk         /*!< PD[0] pin */
-#define AFIO_EXTICR1_EXTI0_PE_Pos            (2U)                              
-#define AFIO_EXTICR1_EXTI0_PE_Msk            (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
-#define AFIO_EXTICR1_EXTI0_PE                AFIO_EXTICR1_EXTI0_PE_Msk         /*!< PE[0] pin */
-#define AFIO_EXTICR1_EXTI0_PF_Pos            (0U)                              
-#define AFIO_EXTICR1_EXTI0_PF_Msk            (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
-#define AFIO_EXTICR1_EXTI0_PF                AFIO_EXTICR1_EXTI0_PF_Msk         /*!< PF[0] pin */
-#define AFIO_EXTICR1_EXTI0_PG_Pos            (1U)                              
-#define AFIO_EXTICR1_EXTI0_PG_Msk            (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
-#define AFIO_EXTICR1_EXTI0_PG                AFIO_EXTICR1_EXTI0_PG_Msk         /*!< PG[0] pin */
-
-/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA                ((uint32_t)0x00000000)            /*!< PA[1] pin */
-#define AFIO_EXTICR1_EXTI1_PB_Pos            (4U)                              
-#define AFIO_EXTICR1_EXTI1_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
-#define AFIO_EXTICR1_EXTI1_PB                AFIO_EXTICR1_EXTI1_PB_Msk         /*!< PB[1] pin */
-#define AFIO_EXTICR1_EXTI1_PC_Pos            (5U)                              
-#define AFIO_EXTICR1_EXTI1_PC_Msk            (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
-#define AFIO_EXTICR1_EXTI1_PC                AFIO_EXTICR1_EXTI1_PC_Msk         /*!< PC[1] pin */
-#define AFIO_EXTICR1_EXTI1_PD_Pos            (4U)                              
-#define AFIO_EXTICR1_EXTI1_PD_Msk            (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
-#define AFIO_EXTICR1_EXTI1_PD                AFIO_EXTICR1_EXTI1_PD_Msk         /*!< PD[1] pin */
-#define AFIO_EXTICR1_EXTI1_PE_Pos            (6U)                              
-#define AFIO_EXTICR1_EXTI1_PE_Msk            (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
-#define AFIO_EXTICR1_EXTI1_PE                AFIO_EXTICR1_EXTI1_PE_Msk         /*!< PE[1] pin */
-#define AFIO_EXTICR1_EXTI1_PF_Pos            (4U)                              
-#define AFIO_EXTICR1_EXTI1_PF_Msk            (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
-#define AFIO_EXTICR1_EXTI1_PF                AFIO_EXTICR1_EXTI1_PF_Msk         /*!< PF[1] pin */
-#define AFIO_EXTICR1_EXTI1_PG_Pos            (5U)                              
-#define AFIO_EXTICR1_EXTI1_PG_Msk            (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
-#define AFIO_EXTICR1_EXTI1_PG                AFIO_EXTICR1_EXTI1_PG_Msk         /*!< PG[1] pin */
-
-/*!< EXTI2 configuration */  
-#define AFIO_EXTICR1_EXTI2_PA                ((uint32_t)0x00000000)            /*!< PA[2] pin */
-#define AFIO_EXTICR1_EXTI2_PB_Pos            (8U)                              
-#define AFIO_EXTICR1_EXTI2_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
-#define AFIO_EXTICR1_EXTI2_PB                AFIO_EXTICR1_EXTI2_PB_Msk         /*!< PB[2] pin */
-#define AFIO_EXTICR1_EXTI2_PC_Pos            (9U)                              
-#define AFIO_EXTICR1_EXTI2_PC_Msk            (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
-#define AFIO_EXTICR1_EXTI2_PC                AFIO_EXTICR1_EXTI2_PC_Msk         /*!< PC[2] pin */
-#define AFIO_EXTICR1_EXTI2_PD_Pos            (8U)                              
-#define AFIO_EXTICR1_EXTI2_PD_Msk            (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
-#define AFIO_EXTICR1_EXTI2_PD                AFIO_EXTICR1_EXTI2_PD_Msk         /*!< PD[2] pin */
-#define AFIO_EXTICR1_EXTI2_PE_Pos            (10U)                             
-#define AFIO_EXTICR1_EXTI2_PE_Msk            (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
-#define AFIO_EXTICR1_EXTI2_PE                AFIO_EXTICR1_EXTI2_PE_Msk         /*!< PE[2] pin */
-#define AFIO_EXTICR1_EXTI2_PF_Pos            (8U)                              
-#define AFIO_EXTICR1_EXTI2_PF_Msk            (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
-#define AFIO_EXTICR1_EXTI2_PF                AFIO_EXTICR1_EXTI2_PF_Msk         /*!< PF[2] pin */
-#define AFIO_EXTICR1_EXTI2_PG_Pos            (9U)                              
-#define AFIO_EXTICR1_EXTI2_PG_Msk            (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
-#define AFIO_EXTICR1_EXTI2_PG                AFIO_EXTICR1_EXTI2_PG_Msk         /*!< PG[2] pin */
-
-/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA                ((uint32_t)0x00000000)            /*!< PA[3] pin */
-#define AFIO_EXTICR1_EXTI3_PB_Pos            (12U)                             
-#define AFIO_EXTICR1_EXTI3_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
-#define AFIO_EXTICR1_EXTI3_PB                AFIO_EXTICR1_EXTI3_PB_Msk         /*!< PB[3] pin */
-#define AFIO_EXTICR1_EXTI3_PC_Pos            (13U)                             
-#define AFIO_EXTICR1_EXTI3_PC_Msk            (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
-#define AFIO_EXTICR1_EXTI3_PC                AFIO_EXTICR1_EXTI3_PC_Msk         /*!< PC[3] pin */
-#define AFIO_EXTICR1_EXTI3_PD_Pos            (12U)                             
-#define AFIO_EXTICR1_EXTI3_PD_Msk            (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
-#define AFIO_EXTICR1_EXTI3_PD                AFIO_EXTICR1_EXTI3_PD_Msk         /*!< PD[3] pin */
-#define AFIO_EXTICR1_EXTI3_PE_Pos            (14U)                             
-#define AFIO_EXTICR1_EXTI3_PE_Msk            (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
-#define AFIO_EXTICR1_EXTI3_PE                AFIO_EXTICR1_EXTI3_PE_Msk         /*!< PE[3] pin */
-#define AFIO_EXTICR1_EXTI3_PF_Pos            (12U)                             
-#define AFIO_EXTICR1_EXTI3_PF_Msk            (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
-#define AFIO_EXTICR1_EXTI3_PF                AFIO_EXTICR1_EXTI3_PF_Msk         /*!< PF[3] pin */
-#define AFIO_EXTICR1_EXTI3_PG_Pos            (13U)                             
-#define AFIO_EXTICR1_EXTI3_PG_Msk            (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
-#define AFIO_EXTICR1_EXTI3_PG                AFIO_EXTICR1_EXTI3_PG_Msk         /*!< PG[3] pin */
-
-/*****************  Bit definition for AFIO_EXTICR2 register  *****************/
-#define AFIO_EXTICR2_EXTI4_Pos               (0U)                              
-#define AFIO_EXTICR2_EXTI4_Msk               (0xFU << AFIO_EXTICR2_EXTI4_Pos)  /*!< 0x0000000F */
-#define AFIO_EXTICR2_EXTI4                   AFIO_EXTICR2_EXTI4_Msk            /*!< EXTI 4 configuration */
-#define AFIO_EXTICR2_EXTI5_Pos               (4U)                              
-#define AFIO_EXTICR2_EXTI5_Msk               (0xFU << AFIO_EXTICR2_EXTI5_Pos)  /*!< 0x000000F0 */
-#define AFIO_EXTICR2_EXTI5                   AFIO_EXTICR2_EXTI5_Msk            /*!< EXTI 5 configuration */
-#define AFIO_EXTICR2_EXTI6_Pos               (8U)                              
-#define AFIO_EXTICR2_EXTI6_Msk               (0xFU << AFIO_EXTICR2_EXTI6_Pos)  /*!< 0x00000F00 */
-#define AFIO_EXTICR2_EXTI6                   AFIO_EXTICR2_EXTI6_Msk            /*!< EXTI 6 configuration */
-#define AFIO_EXTICR2_EXTI7_Pos               (12U)                             
-#define AFIO_EXTICR2_EXTI7_Msk               (0xFU << AFIO_EXTICR2_EXTI7_Pos)  /*!< 0x0000F000 */
-#define AFIO_EXTICR2_EXTI7                   AFIO_EXTICR2_EXTI7_Msk            /*!< EXTI 7 configuration */
-
-/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA                ((uint32_t)0x00000000)            /*!< PA[4] pin */
-#define AFIO_EXTICR2_EXTI4_PB_Pos            (0U)                              
-#define AFIO_EXTICR2_EXTI4_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
-#define AFIO_EXTICR2_EXTI4_PB                AFIO_EXTICR2_EXTI4_PB_Msk         /*!< PB[4] pin */
-#define AFIO_EXTICR2_EXTI4_PC_Pos            (1U)                              
-#define AFIO_EXTICR2_EXTI4_PC_Msk            (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
-#define AFIO_EXTICR2_EXTI4_PC                AFIO_EXTICR2_EXTI4_PC_Msk         /*!< PC[4] pin */
-#define AFIO_EXTICR2_EXTI4_PD_Pos            (0U)                              
-#define AFIO_EXTICR2_EXTI4_PD_Msk            (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
-#define AFIO_EXTICR2_EXTI4_PD                AFIO_EXTICR2_EXTI4_PD_Msk         /*!< PD[4] pin */
-#define AFIO_EXTICR2_EXTI4_PE_Pos            (2U)                              
-#define AFIO_EXTICR2_EXTI4_PE_Msk            (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
-#define AFIO_EXTICR2_EXTI4_PE                AFIO_EXTICR2_EXTI4_PE_Msk         /*!< PE[4] pin */
-#define AFIO_EXTICR2_EXTI4_PF_Pos            (0U)                              
-#define AFIO_EXTICR2_EXTI4_PF_Msk            (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
-#define AFIO_EXTICR2_EXTI4_PF                AFIO_EXTICR2_EXTI4_PF_Msk         /*!< PF[4] pin */
-#define AFIO_EXTICR2_EXTI4_PG_Pos            (1U)                              
-#define AFIO_EXTICR2_EXTI4_PG_Msk            (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
-#define AFIO_EXTICR2_EXTI4_PG                AFIO_EXTICR2_EXTI4_PG_Msk         /*!< PG[4] pin */
-
-/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA                ((uint32_t)0x00000000)            /*!< PA[5] pin */
-#define AFIO_EXTICR2_EXTI5_PB_Pos            (4U)                              
-#define AFIO_EXTICR2_EXTI5_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
-#define AFIO_EXTICR2_EXTI5_PB                AFIO_EXTICR2_EXTI5_PB_Msk         /*!< PB[5] pin */
-#define AFIO_EXTICR2_EXTI5_PC_Pos            (5U)                              
-#define AFIO_EXTICR2_EXTI5_PC_Msk            (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
-#define AFIO_EXTICR2_EXTI5_PC                AFIO_EXTICR2_EXTI5_PC_Msk         /*!< PC[5] pin */
-#define AFIO_EXTICR2_EXTI5_PD_Pos            (4U)                              
-#define AFIO_EXTICR2_EXTI5_PD_Msk            (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
-#define AFIO_EXTICR2_EXTI5_PD                AFIO_EXTICR2_EXTI5_PD_Msk         /*!< PD[5] pin */
-#define AFIO_EXTICR2_EXTI5_PE_Pos            (6U)                              
-#define AFIO_EXTICR2_EXTI5_PE_Msk            (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
-#define AFIO_EXTICR2_EXTI5_PE                AFIO_EXTICR2_EXTI5_PE_Msk         /*!< PE[5] pin */
-#define AFIO_EXTICR2_EXTI5_PF_Pos            (4U)                              
-#define AFIO_EXTICR2_EXTI5_PF_Msk            (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
-#define AFIO_EXTICR2_EXTI5_PF                AFIO_EXTICR2_EXTI5_PF_Msk         /*!< PF[5] pin */
-#define AFIO_EXTICR2_EXTI5_PG_Pos            (5U)                              
-#define AFIO_EXTICR2_EXTI5_PG_Msk            (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
-#define AFIO_EXTICR2_EXTI5_PG                AFIO_EXTICR2_EXTI5_PG_Msk         /*!< PG[5] pin */
-
-/*!< EXTI6 configuration */  
-#define AFIO_EXTICR2_EXTI6_PA                ((uint32_t)0x00000000)            /*!< PA[6] pin */
-#define AFIO_EXTICR2_EXTI6_PB_Pos            (8U)                              
-#define AFIO_EXTICR2_EXTI6_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
-#define AFIO_EXTICR2_EXTI6_PB                AFIO_EXTICR2_EXTI6_PB_Msk         /*!< PB[6] pin */
-#define AFIO_EXTICR2_EXTI6_PC_Pos            (9U)                              
-#define AFIO_EXTICR2_EXTI6_PC_Msk            (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
-#define AFIO_EXTICR2_EXTI6_PC                AFIO_EXTICR2_EXTI6_PC_Msk         /*!< PC[6] pin */
-#define AFIO_EXTICR2_EXTI6_PD_Pos            (8U)                              
-#define AFIO_EXTICR2_EXTI6_PD_Msk            (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
-#define AFIO_EXTICR2_EXTI6_PD                AFIO_EXTICR2_EXTI6_PD_Msk         /*!< PD[6] pin */
-#define AFIO_EXTICR2_EXTI6_PE_Pos            (10U)                             
-#define AFIO_EXTICR2_EXTI6_PE_Msk            (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
-#define AFIO_EXTICR2_EXTI6_PE                AFIO_EXTICR2_EXTI6_PE_Msk         /*!< PE[6] pin */
-#define AFIO_EXTICR2_EXTI6_PF_Pos            (8U)                              
-#define AFIO_EXTICR2_EXTI6_PF_Msk            (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
-#define AFIO_EXTICR2_EXTI6_PF                AFIO_EXTICR2_EXTI6_PF_Msk         /*!< PF[6] pin */
-#define AFIO_EXTICR2_EXTI6_PG_Pos            (9U)                              
-#define AFIO_EXTICR2_EXTI6_PG_Msk            (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
-#define AFIO_EXTICR2_EXTI6_PG                AFIO_EXTICR2_EXTI6_PG_Msk         /*!< PG[6] pin */
-
-/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA                ((uint32_t)0x00000000)            /*!< PA[7] pin */
-#define AFIO_EXTICR2_EXTI7_PB_Pos            (12U)                             
-#define AFIO_EXTICR2_EXTI7_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
-#define AFIO_EXTICR2_EXTI7_PB                AFIO_EXTICR2_EXTI7_PB_Msk         /*!< PB[7] pin */
-#define AFIO_EXTICR2_EXTI7_PC_Pos            (13U)                             
-#define AFIO_EXTICR2_EXTI7_PC_Msk            (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
-#define AFIO_EXTICR2_EXTI7_PC                AFIO_EXTICR2_EXTI7_PC_Msk         /*!< PC[7] pin */
-#define AFIO_EXTICR2_EXTI7_PD_Pos            (12U)                             
-#define AFIO_EXTICR2_EXTI7_PD_Msk            (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
-#define AFIO_EXTICR2_EXTI7_PD                AFIO_EXTICR2_EXTI7_PD_Msk         /*!< PD[7] pin */
-#define AFIO_EXTICR2_EXTI7_PE_Pos            (14U)                             
-#define AFIO_EXTICR2_EXTI7_PE_Msk            (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
-#define AFIO_EXTICR2_EXTI7_PE                AFIO_EXTICR2_EXTI7_PE_Msk         /*!< PE[7] pin */
-#define AFIO_EXTICR2_EXTI7_PF_Pos            (12U)                             
-#define AFIO_EXTICR2_EXTI7_PF_Msk            (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
-#define AFIO_EXTICR2_EXTI7_PF                AFIO_EXTICR2_EXTI7_PF_Msk         /*!< PF[7] pin */
-#define AFIO_EXTICR2_EXTI7_PG_Pos            (13U)                             
-#define AFIO_EXTICR2_EXTI7_PG_Msk            (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
-#define AFIO_EXTICR2_EXTI7_PG                AFIO_EXTICR2_EXTI7_PG_Msk         /*!< PG[7] pin */
-
-/*****************  Bit definition for AFIO_EXTICR3 register  *****************/
-#define AFIO_EXTICR3_EXTI8_Pos               (0U)                              
-#define AFIO_EXTICR3_EXTI8_Msk               (0xFU << AFIO_EXTICR3_EXTI8_Pos)  /*!< 0x0000000F */
-#define AFIO_EXTICR3_EXTI8                   AFIO_EXTICR3_EXTI8_Msk            /*!< EXTI 8 configuration */
-#define AFIO_EXTICR3_EXTI9_Pos               (4U)                              
-#define AFIO_EXTICR3_EXTI9_Msk               (0xFU << AFIO_EXTICR3_EXTI9_Pos)  /*!< 0x000000F0 */
-#define AFIO_EXTICR3_EXTI9                   AFIO_EXTICR3_EXTI9_Msk            /*!< EXTI 9 configuration */
-#define AFIO_EXTICR3_EXTI10_Pos              (8U)                              
-#define AFIO_EXTICR3_EXTI10_Msk              (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define AFIO_EXTICR3_EXTI10                  AFIO_EXTICR3_EXTI10_Msk           /*!< EXTI 10 configuration */
-#define AFIO_EXTICR3_EXTI11_Pos              (12U)                             
-#define AFIO_EXTICR3_EXTI11_Msk              (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define AFIO_EXTICR3_EXTI11                  AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */
-
-/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA                ((uint32_t)0x00000000)            /*!< PA[8] pin */
-#define AFIO_EXTICR3_EXTI8_PB_Pos            (0U)                              
-#define AFIO_EXTICR3_EXTI8_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
-#define AFIO_EXTICR3_EXTI8_PB                AFIO_EXTICR3_EXTI8_PB_Msk         /*!< PB[8] pin */
-#define AFIO_EXTICR3_EXTI8_PC_Pos            (1U)                              
-#define AFIO_EXTICR3_EXTI8_PC_Msk            (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
-#define AFIO_EXTICR3_EXTI8_PC                AFIO_EXTICR3_EXTI8_PC_Msk         /*!< PC[8] pin */
-#define AFIO_EXTICR3_EXTI8_PD_Pos            (0U)                              
-#define AFIO_EXTICR3_EXTI8_PD_Msk            (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
-#define AFIO_EXTICR3_EXTI8_PD                AFIO_EXTICR3_EXTI8_PD_Msk         /*!< PD[8] pin */
-#define AFIO_EXTICR3_EXTI8_PE_Pos            (2U)                              
-#define AFIO_EXTICR3_EXTI8_PE_Msk            (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
-#define AFIO_EXTICR3_EXTI8_PE                AFIO_EXTICR3_EXTI8_PE_Msk         /*!< PE[8] pin */
-#define AFIO_EXTICR3_EXTI8_PF_Pos            (0U)                              
-#define AFIO_EXTICR3_EXTI8_PF_Msk            (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
-#define AFIO_EXTICR3_EXTI8_PF                AFIO_EXTICR3_EXTI8_PF_Msk         /*!< PF[8] pin */
-#define AFIO_EXTICR3_EXTI8_PG_Pos            (1U)                              
-#define AFIO_EXTICR3_EXTI8_PG_Msk            (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
-#define AFIO_EXTICR3_EXTI8_PG                AFIO_EXTICR3_EXTI8_PG_Msk         /*!< PG[8] pin */
-
-/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA                ((uint32_t)0x00000000)            /*!< PA[9] pin */
-#define AFIO_EXTICR3_EXTI9_PB_Pos            (4U)                              
-#define AFIO_EXTICR3_EXTI9_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
-#define AFIO_EXTICR3_EXTI9_PB                AFIO_EXTICR3_EXTI9_PB_Msk         /*!< PB[9] pin */
-#define AFIO_EXTICR3_EXTI9_PC_Pos            (5U)                              
-#define AFIO_EXTICR3_EXTI9_PC_Msk            (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
-#define AFIO_EXTICR3_EXTI9_PC                AFIO_EXTICR3_EXTI9_PC_Msk         /*!< PC[9] pin */
-#define AFIO_EXTICR3_EXTI9_PD_Pos            (4U)                              
-#define AFIO_EXTICR3_EXTI9_PD_Msk            (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
-#define AFIO_EXTICR3_EXTI9_PD                AFIO_EXTICR3_EXTI9_PD_Msk         /*!< PD[9] pin */
-#define AFIO_EXTICR3_EXTI9_PE_Pos            (6U)                              
-#define AFIO_EXTICR3_EXTI9_PE_Msk            (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
-#define AFIO_EXTICR3_EXTI9_PE                AFIO_EXTICR3_EXTI9_PE_Msk         /*!< PE[9] pin */
-#define AFIO_EXTICR3_EXTI9_PF_Pos            (4U)                              
-#define AFIO_EXTICR3_EXTI9_PF_Msk            (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
-#define AFIO_EXTICR3_EXTI9_PF                AFIO_EXTICR3_EXTI9_PF_Msk         /*!< PF[9] pin */
-#define AFIO_EXTICR3_EXTI9_PG_Pos            (5U)                              
-#define AFIO_EXTICR3_EXTI9_PG_Msk            (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
-#define AFIO_EXTICR3_EXTI9_PG                AFIO_EXTICR3_EXTI9_PG_Msk         /*!< PG[9] pin */
-
-/*!< EXTI10 configuration */  
-#define AFIO_EXTICR3_EXTI10_PA               ((uint32_t)0x00000000)            /*!< PA[10] pin */
-#define AFIO_EXTICR3_EXTI10_PB_Pos           (8U)                              
-#define AFIO_EXTICR3_EXTI10_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
-#define AFIO_EXTICR3_EXTI10_PB               AFIO_EXTICR3_EXTI10_PB_Msk        /*!< PB[10] pin */
-#define AFIO_EXTICR3_EXTI10_PC_Pos           (9U)                              
-#define AFIO_EXTICR3_EXTI10_PC_Msk           (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
-#define AFIO_EXTICR3_EXTI10_PC               AFIO_EXTICR3_EXTI10_PC_Msk        /*!< PC[10] pin */
-#define AFIO_EXTICR3_EXTI10_PD_Pos           (8U)                              
-#define AFIO_EXTICR3_EXTI10_PD_Msk           (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
-#define AFIO_EXTICR3_EXTI10_PD               AFIO_EXTICR3_EXTI10_PD_Msk        /*!< PD[10] pin */
-#define AFIO_EXTICR3_EXTI10_PE_Pos           (10U)                             
-#define AFIO_EXTICR3_EXTI10_PE_Msk           (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
-#define AFIO_EXTICR3_EXTI10_PE               AFIO_EXTICR3_EXTI10_PE_Msk        /*!< PE[10] pin */
-#define AFIO_EXTICR3_EXTI10_PF_Pos           (8U)                              
-#define AFIO_EXTICR3_EXTI10_PF_Msk           (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
-#define AFIO_EXTICR3_EXTI10_PF               AFIO_EXTICR3_EXTI10_PF_Msk        /*!< PF[10] pin */
-#define AFIO_EXTICR3_EXTI10_PG_Pos           (9U)                              
-#define AFIO_EXTICR3_EXTI10_PG_Msk           (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
-#define AFIO_EXTICR3_EXTI10_PG               AFIO_EXTICR3_EXTI10_PG_Msk        /*!< PG[10] pin */
-
-/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA               ((uint32_t)0x00000000)            /*!< PA[11] pin */
-#define AFIO_EXTICR3_EXTI11_PB_Pos           (12U)                             
-#define AFIO_EXTICR3_EXTI11_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
-#define AFIO_EXTICR3_EXTI11_PB               AFIO_EXTICR3_EXTI11_PB_Msk        /*!< PB[11] pin */
-#define AFIO_EXTICR3_EXTI11_PC_Pos           (13U)                             
-#define AFIO_EXTICR3_EXTI11_PC_Msk           (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
-#define AFIO_EXTICR3_EXTI11_PC               AFIO_EXTICR3_EXTI11_PC_Msk        /*!< PC[11] pin */
-#define AFIO_EXTICR3_EXTI11_PD_Pos           (12U)                             
-#define AFIO_EXTICR3_EXTI11_PD_Msk           (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
-#define AFIO_EXTICR3_EXTI11_PD               AFIO_EXTICR3_EXTI11_PD_Msk        /*!< PD[11] pin */
-#define AFIO_EXTICR3_EXTI11_PE_Pos           (14U)                             
-#define AFIO_EXTICR3_EXTI11_PE_Msk           (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
-#define AFIO_EXTICR3_EXTI11_PE               AFIO_EXTICR3_EXTI11_PE_Msk        /*!< PE[11] pin */
-#define AFIO_EXTICR3_EXTI11_PF_Pos           (12U)                             
-#define AFIO_EXTICR3_EXTI11_PF_Msk           (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
-#define AFIO_EXTICR3_EXTI11_PF               AFIO_EXTICR3_EXTI11_PF_Msk        /*!< PF[11] pin */
-#define AFIO_EXTICR3_EXTI11_PG_Pos           (13U)                             
-#define AFIO_EXTICR3_EXTI11_PG_Msk           (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
-#define AFIO_EXTICR3_EXTI11_PG               AFIO_EXTICR3_EXTI11_PG_Msk        /*!< PG[11] pin */
-
-/*****************  Bit definition for AFIO_EXTICR4 register  *****************/
-#define AFIO_EXTICR4_EXTI12_Pos              (0U)                              
-#define AFIO_EXTICR4_EXTI12_Msk              (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define AFIO_EXTICR4_EXTI12                  AFIO_EXTICR4_EXTI12_Msk           /*!< EXTI 12 configuration */
-#define AFIO_EXTICR4_EXTI13_Pos              (4U)                              
-#define AFIO_EXTICR4_EXTI13_Msk              (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define AFIO_EXTICR4_EXTI13                  AFIO_EXTICR4_EXTI13_Msk           /*!< EXTI 13 configuration */
-#define AFIO_EXTICR4_EXTI14_Pos              (8U)                              
-#define AFIO_EXTICR4_EXTI14_Msk              (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define AFIO_EXTICR4_EXTI14                  AFIO_EXTICR4_EXTI14_Msk           /*!< EXTI 14 configuration */
-#define AFIO_EXTICR4_EXTI15_Pos              (12U)                             
-#define AFIO_EXTICR4_EXTI15_Msk              (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define AFIO_EXTICR4_EXTI15                  AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */
-
-/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA               ((uint32_t)0x00000000)            /*!< PA[12] pin */
-#define AFIO_EXTICR4_EXTI12_PB_Pos           (0U)                              
-#define AFIO_EXTICR4_EXTI12_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
-#define AFIO_EXTICR4_EXTI12_PB               AFIO_EXTICR4_EXTI12_PB_Msk        /*!< PB[12] pin */
-#define AFIO_EXTICR4_EXTI12_PC_Pos           (1U)                              
-#define AFIO_EXTICR4_EXTI12_PC_Msk           (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
-#define AFIO_EXTICR4_EXTI12_PC               AFIO_EXTICR4_EXTI12_PC_Msk        /*!< PC[12] pin */
-#define AFIO_EXTICR4_EXTI12_PD_Pos           (0U)                              
-#define AFIO_EXTICR4_EXTI12_PD_Msk           (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
-#define AFIO_EXTICR4_EXTI12_PD               AFIO_EXTICR4_EXTI12_PD_Msk        /*!< PD[12] pin */
-#define AFIO_EXTICR4_EXTI12_PE_Pos           (2U)                              
-#define AFIO_EXTICR4_EXTI12_PE_Msk           (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
-#define AFIO_EXTICR4_EXTI12_PE               AFIO_EXTICR4_EXTI12_PE_Msk        /*!< PE[12] pin */
-#define AFIO_EXTICR4_EXTI12_PF_Pos           (0U)                              
-#define AFIO_EXTICR4_EXTI12_PF_Msk           (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
-#define AFIO_EXTICR4_EXTI12_PF               AFIO_EXTICR4_EXTI12_PF_Msk        /*!< PF[12] pin */
-#define AFIO_EXTICR4_EXTI12_PG_Pos           (1U)                              
-#define AFIO_EXTICR4_EXTI12_PG_Msk           (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
-#define AFIO_EXTICR4_EXTI12_PG               AFIO_EXTICR4_EXTI12_PG_Msk        /*!< PG[12] pin */
-
-/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA               ((uint32_t)0x00000000)            /*!< PA[13] pin */
-#define AFIO_EXTICR4_EXTI13_PB_Pos           (4U)                              
-#define AFIO_EXTICR4_EXTI13_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
-#define AFIO_EXTICR4_EXTI13_PB               AFIO_EXTICR4_EXTI13_PB_Msk        /*!< PB[13] pin */
-#define AFIO_EXTICR4_EXTI13_PC_Pos           (5U)                              
-#define AFIO_EXTICR4_EXTI13_PC_Msk           (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
-#define AFIO_EXTICR4_EXTI13_PC               AFIO_EXTICR4_EXTI13_PC_Msk        /*!< PC[13] pin */
-#define AFIO_EXTICR4_EXTI13_PD_Pos           (4U)                              
-#define AFIO_EXTICR4_EXTI13_PD_Msk           (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
-#define AFIO_EXTICR4_EXTI13_PD               AFIO_EXTICR4_EXTI13_PD_Msk        /*!< PD[13] pin */
-#define AFIO_EXTICR4_EXTI13_PE_Pos           (6U)                              
-#define AFIO_EXTICR4_EXTI13_PE_Msk           (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
-#define AFIO_EXTICR4_EXTI13_PE               AFIO_EXTICR4_EXTI13_PE_Msk        /*!< PE[13] pin */
-#define AFIO_EXTICR4_EXTI13_PF_Pos           (4U)                              
-#define AFIO_EXTICR4_EXTI13_PF_Msk           (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
-#define AFIO_EXTICR4_EXTI13_PF               AFIO_EXTICR4_EXTI13_PF_Msk        /*!< PF[13] pin */
-#define AFIO_EXTICR4_EXTI13_PG_Pos           (5U)                              
-#define AFIO_EXTICR4_EXTI13_PG_Msk           (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
-#define AFIO_EXTICR4_EXTI13_PG               AFIO_EXTICR4_EXTI13_PG_Msk        /*!< PG[13] pin */
-
-/*!< EXTI14 configuration */  
-#define AFIO_EXTICR4_EXTI14_PA               ((uint32_t)0x00000000)            /*!< PA[14] pin */
-#define AFIO_EXTICR4_EXTI14_PB_Pos           (8U)                              
-#define AFIO_EXTICR4_EXTI14_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
-#define AFIO_EXTICR4_EXTI14_PB               AFIO_EXTICR4_EXTI14_PB_Msk        /*!< PB[14] pin */
-#define AFIO_EXTICR4_EXTI14_PC_Pos           (9U)                              
-#define AFIO_EXTICR4_EXTI14_PC_Msk           (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
-#define AFIO_EXTICR4_EXTI14_PC               AFIO_EXTICR4_EXTI14_PC_Msk        /*!< PC[14] pin */
-#define AFIO_EXTICR4_EXTI14_PD_Pos           (8U)                              
-#define AFIO_EXTICR4_EXTI14_PD_Msk           (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
-#define AFIO_EXTICR4_EXTI14_PD               AFIO_EXTICR4_EXTI14_PD_Msk        /*!< PD[14] pin */
-#define AFIO_EXTICR4_EXTI14_PE_Pos           (10U)                             
-#define AFIO_EXTICR4_EXTI14_PE_Msk           (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
-#define AFIO_EXTICR4_EXTI14_PE               AFIO_EXTICR4_EXTI14_PE_Msk        /*!< PE[14] pin */
-#define AFIO_EXTICR4_EXTI14_PF_Pos           (8U)                              
-#define AFIO_EXTICR4_EXTI14_PF_Msk           (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
-#define AFIO_EXTICR4_EXTI14_PF               AFIO_EXTICR4_EXTI14_PF_Msk        /*!< PF[14] pin */
-#define AFIO_EXTICR4_EXTI14_PG_Pos           (9U)                              
-#define AFIO_EXTICR4_EXTI14_PG_Msk           (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
-#define AFIO_EXTICR4_EXTI14_PG               AFIO_EXTICR4_EXTI14_PG_Msk        /*!< PG[14] pin */
-
-/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA               ((uint32_t)0x00000000)            /*!< PA[15] pin */
-#define AFIO_EXTICR4_EXTI15_PB_Pos           (12U)                             
-#define AFIO_EXTICR4_EXTI15_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
-#define AFIO_EXTICR4_EXTI15_PB               AFIO_EXTICR4_EXTI15_PB_Msk        /*!< PB[15] pin */
-#define AFIO_EXTICR4_EXTI15_PC_Pos           (13U)                             
-#define AFIO_EXTICR4_EXTI15_PC_Msk           (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
-#define AFIO_EXTICR4_EXTI15_PC               AFIO_EXTICR4_EXTI15_PC_Msk        /*!< PC[15] pin */
-#define AFIO_EXTICR4_EXTI15_PD_Pos           (12U)                             
-#define AFIO_EXTICR4_EXTI15_PD_Msk           (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
-#define AFIO_EXTICR4_EXTI15_PD               AFIO_EXTICR4_EXTI15_PD_Msk        /*!< PD[15] pin */
-#define AFIO_EXTICR4_EXTI15_PE_Pos           (14U)                             
-#define AFIO_EXTICR4_EXTI15_PE_Msk           (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
-#define AFIO_EXTICR4_EXTI15_PE               AFIO_EXTICR4_EXTI15_PE_Msk        /*!< PE[15] pin */
-#define AFIO_EXTICR4_EXTI15_PF_Pos           (12U)                             
-#define AFIO_EXTICR4_EXTI15_PF_Msk           (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
-#define AFIO_EXTICR4_EXTI15_PF               AFIO_EXTICR4_EXTI15_PF_Msk        /*!< PF[15] pin */
-#define AFIO_EXTICR4_EXTI15_PG_Pos           (13U)                             
-#define AFIO_EXTICR4_EXTI15_PG_Msk           (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
-#define AFIO_EXTICR4_EXTI15_PG               AFIO_EXTICR4_EXTI15_PG_Msk        /*!< PG[15] pin */
-
-/******************  Bit definition for AFIO_MAPR2 register  ******************/
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                               SystemTick                                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*****************  Bit definition for SysTick_CTRL register  *****************/
-#define SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)             /*!< Counter enable */
-#define SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)             /*!< Counting down to 0 pends the SysTick handler */
-#define SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)             /*!< Clock source */
-#define SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)             /*!< Count Flag */
-
-/*****************  Bit definition for SysTick_LOAD register  *****************/
-#define SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)             /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/*****************  Bit definition for SysTick_VAL register  ******************/
-#define SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)             /*!< Current value at the time the register is accessed */
-
-/*****************  Bit definition for SysTick_CALIB register  ****************/
-#define SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)             /*!< Reload value to use for 10ms timing */
-#define SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)             /*!< Calibration value is not exactly 10 ms */
-#define SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)             /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  Nested Vectored Interrupt Controller                      */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for NVIC_ISER register  *******************/
-#define NVIC_ISER_SETENA_Pos                (0U)                               
-#define NVIC_ISER_SETENA_Msk                (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISER_SETENA                    NVIC_ISER_SETENA_Msk               /*!< Interrupt set enable bits */
-#define NVIC_ISER_SETENA_0                  (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
-#define NVIC_ISER_SETENA_1                  (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
-#define NVIC_ISER_SETENA_2                  (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
-#define NVIC_ISER_SETENA_3                  (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
-#define NVIC_ISER_SETENA_4                  (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
-#define NVIC_ISER_SETENA_5                  (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
-#define NVIC_ISER_SETENA_6                  (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
-#define NVIC_ISER_SETENA_7                  (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
-#define NVIC_ISER_SETENA_8                  (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
-#define NVIC_ISER_SETENA_9                  (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
-#define NVIC_ISER_SETENA_10                 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
-#define NVIC_ISER_SETENA_11                 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
-#define NVIC_ISER_SETENA_12                 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
-#define NVIC_ISER_SETENA_13                 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
-#define NVIC_ISER_SETENA_14                 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
-#define NVIC_ISER_SETENA_15                 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
-#define NVIC_ISER_SETENA_16                 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
-#define NVIC_ISER_SETENA_17                 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
-#define NVIC_ISER_SETENA_18                 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
-#define NVIC_ISER_SETENA_19                 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
-#define NVIC_ISER_SETENA_20                 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
-#define NVIC_ISER_SETENA_21                 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
-#define NVIC_ISER_SETENA_22                 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
-#define NVIC_ISER_SETENA_23                 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
-#define NVIC_ISER_SETENA_24                 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
-#define NVIC_ISER_SETENA_25                 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
-#define NVIC_ISER_SETENA_26                 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
-#define NVIC_ISER_SETENA_27                 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
-#define NVIC_ISER_SETENA_28                 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
-#define NVIC_ISER_SETENA_29                 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
-#define NVIC_ISER_SETENA_30                 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
-#define NVIC_ISER_SETENA_31                 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for NVIC_ICER register  *******************/
-#define NVIC_ICER_CLRENA_Pos                (0U)                               
-#define NVIC_ICER_CLRENA_Msk                (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICER_CLRENA                    NVIC_ICER_CLRENA_Msk               /*!< Interrupt clear-enable bits */
-#define NVIC_ICER_CLRENA_0                  (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
-#define NVIC_ICER_CLRENA_1                  (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
-#define NVIC_ICER_CLRENA_2                  (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
-#define NVIC_ICER_CLRENA_3                  (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
-#define NVIC_ICER_CLRENA_4                  (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
-#define NVIC_ICER_CLRENA_5                  (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
-#define NVIC_ICER_CLRENA_6                  (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
-#define NVIC_ICER_CLRENA_7                  (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
-#define NVIC_ICER_CLRENA_8                  (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
-#define NVIC_ICER_CLRENA_9                  (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
-#define NVIC_ICER_CLRENA_10                 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
-#define NVIC_ICER_CLRENA_11                 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
-#define NVIC_ICER_CLRENA_12                 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
-#define NVIC_ICER_CLRENA_13                 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
-#define NVIC_ICER_CLRENA_14                 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
-#define NVIC_ICER_CLRENA_15                 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
-#define NVIC_ICER_CLRENA_16                 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
-#define NVIC_ICER_CLRENA_17                 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
-#define NVIC_ICER_CLRENA_18                 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
-#define NVIC_ICER_CLRENA_19                 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
-#define NVIC_ICER_CLRENA_20                 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
-#define NVIC_ICER_CLRENA_21                 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
-#define NVIC_ICER_CLRENA_22                 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
-#define NVIC_ICER_CLRENA_23                 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
-#define NVIC_ICER_CLRENA_24                 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
-#define NVIC_ICER_CLRENA_25                 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
-#define NVIC_ICER_CLRENA_26                 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
-#define NVIC_ICER_CLRENA_27                 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
-#define NVIC_ICER_CLRENA_28                 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
-#define NVIC_ICER_CLRENA_29                 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
-#define NVIC_ICER_CLRENA_30                 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
-#define NVIC_ICER_CLRENA_31                 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for NVIC_ISPR register  *******************/
-#define NVIC_ISPR_SETPEND_Pos               (0U)                               
-#define NVIC_ISPR_SETPEND_Msk               (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISPR_SETPEND                   NVIC_ISPR_SETPEND_Msk              /*!< Interrupt set-pending bits */
-#define NVIC_ISPR_SETPEND_0                 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ISPR_SETPEND_1                 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ISPR_SETPEND_2                 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ISPR_SETPEND_3                 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ISPR_SETPEND_4                 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ISPR_SETPEND_5                 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ISPR_SETPEND_6                 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ISPR_SETPEND_7                 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ISPR_SETPEND_8                 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ISPR_SETPEND_9                 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ISPR_SETPEND_10                (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ISPR_SETPEND_11                (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ISPR_SETPEND_12                (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ISPR_SETPEND_13                (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ISPR_SETPEND_14                (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ISPR_SETPEND_15                (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ISPR_SETPEND_16                (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ISPR_SETPEND_17                (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ISPR_SETPEND_18                (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ISPR_SETPEND_19                (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ISPR_SETPEND_20                (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ISPR_SETPEND_21                (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ISPR_SETPEND_22                (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ISPR_SETPEND_23                (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ISPR_SETPEND_24                (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ISPR_SETPEND_25                (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ISPR_SETPEND_26                (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ISPR_SETPEND_27                (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ISPR_SETPEND_28                (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ISPR_SETPEND_29                (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ISPR_SETPEND_30                (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ISPR_SETPEND_31                (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for NVIC_ICPR register  *******************/
-#define NVIC_ICPR_CLRPEND_Pos               (0U)                               
-#define NVIC_ICPR_CLRPEND_Msk               (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICPR_CLRPEND                   NVIC_ICPR_CLRPEND_Msk              /*!< Interrupt clear-pending bits */
-#define NVIC_ICPR_CLRPEND_0                 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ICPR_CLRPEND_1                 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ICPR_CLRPEND_2                 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ICPR_CLRPEND_3                 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ICPR_CLRPEND_4                 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ICPR_CLRPEND_5                 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ICPR_CLRPEND_6                 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ICPR_CLRPEND_7                 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ICPR_CLRPEND_8                 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ICPR_CLRPEND_9                 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ICPR_CLRPEND_10                (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ICPR_CLRPEND_11                (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ICPR_CLRPEND_12                (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ICPR_CLRPEND_13                (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ICPR_CLRPEND_14                (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ICPR_CLRPEND_15                (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ICPR_CLRPEND_16                (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ICPR_CLRPEND_17                (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ICPR_CLRPEND_18                (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ICPR_CLRPEND_19                (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ICPR_CLRPEND_20                (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ICPR_CLRPEND_21                (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ICPR_CLRPEND_22                (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ICPR_CLRPEND_23                (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ICPR_CLRPEND_24                (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ICPR_CLRPEND_25                (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ICPR_CLRPEND_26                (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ICPR_CLRPEND_27                (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ICPR_CLRPEND_28                (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ICPR_CLRPEND_29                (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ICPR_CLRPEND_30                (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ICPR_CLRPEND_31                (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for NVIC_IABR register  *******************/
-#define NVIC_IABR_ACTIVE_Pos                (0U)                               
-#define NVIC_IABR_ACTIVE_Msk                (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_IABR_ACTIVE                    NVIC_IABR_ACTIVE_Msk               /*!< Interrupt active flags */
-#define NVIC_IABR_ACTIVE_0                  (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
-#define NVIC_IABR_ACTIVE_1                  (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
-#define NVIC_IABR_ACTIVE_2                  (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
-#define NVIC_IABR_ACTIVE_3                  (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
-#define NVIC_IABR_ACTIVE_4                  (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
-#define NVIC_IABR_ACTIVE_5                  (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
-#define NVIC_IABR_ACTIVE_6                  (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
-#define NVIC_IABR_ACTIVE_7                  (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
-#define NVIC_IABR_ACTIVE_8                  (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
-#define NVIC_IABR_ACTIVE_9                  (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
-#define NVIC_IABR_ACTIVE_10                 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
-#define NVIC_IABR_ACTIVE_11                 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
-#define NVIC_IABR_ACTIVE_12                 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
-#define NVIC_IABR_ACTIVE_13                 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
-#define NVIC_IABR_ACTIVE_14                 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
-#define NVIC_IABR_ACTIVE_15                 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
-#define NVIC_IABR_ACTIVE_16                 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
-#define NVIC_IABR_ACTIVE_17                 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
-#define NVIC_IABR_ACTIVE_18                 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
-#define NVIC_IABR_ACTIVE_19                 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
-#define NVIC_IABR_ACTIVE_20                 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
-#define NVIC_IABR_ACTIVE_21                 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
-#define NVIC_IABR_ACTIVE_22                 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
-#define NVIC_IABR_ACTIVE_23                 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
-#define NVIC_IABR_ACTIVE_24                 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
-#define NVIC_IABR_ACTIVE_25                 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
-#define NVIC_IABR_ACTIVE_26                 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
-#define NVIC_IABR_ACTIVE_27                 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
-#define NVIC_IABR_ACTIVE_28                 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
-#define NVIC_IABR_ACTIVE_29                 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
-#define NVIC_IABR_ACTIVE_30                 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
-#define NVIC_IABR_ACTIVE_31                 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for NVIC_PRI0 register  *******************/
-#define NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 0 */
-#define NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 1 */
-#define NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 2 */
-#define NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 3 */
-
-/******************  Bit definition for NVIC_PRI1 register  *******************/
-#define NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 4 */
-#define NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 5 */
-#define NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 6 */
-#define NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 7 */
-
-/******************  Bit definition for NVIC_PRI2 register  *******************/
-#define NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 8 */
-#define NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 9 */
-#define NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 10 */
-#define NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 11 */
-
-/******************  Bit definition for NVIC_PRI3 register  *******************/
-#define NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 12 */
-#define NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 13 */
-#define NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 14 */
-#define NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 15 */
-
-/******************  Bit definition for NVIC_PRI4 register  *******************/
-#define NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 16 */
-#define NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 17 */
-#define NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 18 */
-#define NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 19 */
-
-/******************  Bit definition for NVIC_PRI5 register  *******************/
-#define NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 20 */
-#define NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 21 */
-#define NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 22 */
-#define NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 23 */
-
-/******************  Bit definition for NVIC_PRI6 register  *******************/
-#define NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 24 */
-#define NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 25 */
-#define NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 26 */
-#define NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 27 */
-
-/******************  Bit definition for NVIC_PRI7 register  *******************/
-#define NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 28 */
-#define NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 29 */
-#define NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 30 */
-#define NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 31 */
-
-/******************  Bit definition for SCB_CPUID register  *******************/
-#define SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)             /*!< Implementation defined revision number */
-#define SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)             /*!< Number of processor within family */
-#define SCB_CPUID_Constant                  ((uint32_t)0x000F0000)             /*!< Reads as 0x0F */
-#define SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)             /*!< Implementation defined variant number */
-#define SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)             /*!< Implementer code. ARM is 0x41 */
-
-/*******************  Bit definition for SCB_ICSR register  *******************/
-#define SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)             /*!< Active ISR number field */
-#define SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)             /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)             /*!< Pending ISR number field */
-#define SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)             /*!< Interrupt pending flag */
-#define SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)             /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)             /*!< Clear pending SysTick bit */
-#define SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)             /*!< Set pending SysTick bit */
-#define SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)             /*!< Clear pending pendSV bit */
-#define SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)             /*!< Set pending pendSV bit */
-#define SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)             /*!< Set pending NMI bit */
-
-/*******************  Bit definition for SCB_VTOR register  *******************/
-#define SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)             /*!< Vector table base offset field */
-#define SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)             /*!< Table base in code(0) or RAM(1) */
-
-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/
-#define SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)             /*!< System Reset bit */
-#define SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)             /*!< Clear active vector bit */
-#define SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)             /*!< Requests chip control logic to generate a reset */
-
-#define SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)             /*!< PRIGROUP[2:0] bits (Priority group) */
-#define SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)             /*!< Bit 0 */
-#define SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)             /*!< Bit 1 */
-#define SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)             /*!< Bit 2  */
-
-/* prority group configuration */
-#define SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)             /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)             /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)             /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)             /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)             /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)             /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)             /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)             /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)             /*!< Data endianness bit */
-#define SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)             /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/*******************  Bit definition for SCB_SCR register  ********************/
-#define SCB_SCR_SLEEPONEXIT                 ((uint32_t)0x00000002)             /*!< Sleep on exit bit */
-#define SCB_SCR_SLEEPDEEP                   ((uint32_t)0x00000004)             /*!< Sleep deep bit */
-#define SCB_SCR_SEVONPEND                   ((uint32_t)0x00000010)             /*!< Wake up from WFE */
-
-/********************  Bit definition for SCB_CCR register  *******************/
-#define SCB_CCR_NONBASETHRDENA              ((uint32_t)0x00000001)             /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define SCB_CCR_USERSETMPEND                ((uint32_t)0x00000002)             /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define SCB_CCR_UNALIGN_TRP                 ((uint32_t)0x00000008)             /*!< Trap for unaligned access */
-#define SCB_CCR_DIV_0_TRP                   ((uint32_t)0x00000010)             /*!< Trap on Divide by 0 */
-#define SCB_CCR_BFHFNMIGN                   ((uint32_t)0x00000100)             /*!< Handlers running at priority -1 and -2 */
-#define SCB_CCR_STKALIGN                    ((uint32_t)0x00000200)             /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/*******************  Bit definition for SCB_SHPR register ********************/
-#define SCB_SHPR_PRI_N_Pos                  (0U)                               
-#define SCB_SHPR_PRI_N_Msk                  (0xFFU << SCB_SHPR_PRI_N_Pos)      /*!< 0x000000FF */
-#define SCB_SHPR_PRI_N                      SCB_SHPR_PRI_N_Msk                 /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define SCB_SHPR_PRI_N1_Pos                 (8U)                               
-#define SCB_SHPR_PRI_N1_Msk                 (0xFFU << SCB_SHPR_PRI_N1_Pos)     /*!< 0x0000FF00 */
-#define SCB_SHPR_PRI_N1                     SCB_SHPR_PRI_N1_Msk                /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define SCB_SHPR_PRI_N2_Pos                 (16U)                              
-#define SCB_SHPR_PRI_N2_Msk                 (0xFFU << SCB_SHPR_PRI_N2_Pos)     /*!< 0x00FF0000 */
-#define SCB_SHPR_PRI_N2                     SCB_SHPR_PRI_N2_Msk                /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define SCB_SHPR_PRI_N3_Pos                 (24U)                              
-#define SCB_SHPR_PRI_N3_Msk                 (0xFFU << SCB_SHPR_PRI_N3_Pos)     /*!< 0xFF000000 */
-#define SCB_SHPR_PRI_N3                     SCB_SHPR_PRI_N3_Msk                /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/******************  Bit definition for SCB_SHCSR register  *******************/
-#define SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)             /*!< MemManage is active */
-#define SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)             /*!< BusFault is active */
-#define SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)             /*!< UsageFault is active */
-#define SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)             /*!< SVCall is active */
-#define SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)             /*!< Monitor is active */
-#define SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)             /*!< PendSV is active */
-#define SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)             /*!< SysTick is active */
-#define SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)             /*!< Usage Fault is pended */
-#define SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)             /*!< MemManage is pended */
-#define SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)             /*!< Bus Fault is pended */
-#define SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)             /*!< SVCall is pended */
-#define SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)             /*!< MemManage enable */
-#define SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)             /*!< Bus Fault enable */
-#define SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)             /*!< UsageFault enable */
-
-/*******************  Bit definition for SCB_CFSR register  *******************/
-/*!< MFSR */
-#define SCB_CFSR_IACCVIOL_Pos               (0U)                               
-#define SCB_CFSR_IACCVIOL_Msk               (0x1U << SCB_CFSR_IACCVIOL_Pos)    /*!< 0x00000001 */
-#define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */
-#define SCB_CFSR_DACCVIOL_Pos               (1U)                               
-#define SCB_CFSR_DACCVIOL_Msk               (0x1U << SCB_CFSR_DACCVIOL_Pos)    /*!< 0x00000002 */
-#define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */
-#define SCB_CFSR_MUNSTKERR_Pos              (3U)                               
-#define SCB_CFSR_MUNSTKERR_Msk              (0x1U << SCB_CFSR_MUNSTKERR_Pos)   /*!< 0x00000008 */
-#define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */
-#define SCB_CFSR_MSTKERR_Pos                (4U)                               
-#define SCB_CFSR_MSTKERR_Msk                (0x1U << SCB_CFSR_MSTKERR_Pos)     /*!< 0x00000010 */
-#define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */
-#define SCB_CFSR_MMARVALID_Pos              (7U)                               
-#define SCB_CFSR_MMARVALID_Msk              (0x1U << SCB_CFSR_MMARVALID_Pos)   /*!< 0x00000080 */
-#define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define SCB_CFSR_IBUSERR_Pos                (8U)                               
-#define SCB_CFSR_IBUSERR_Msk                (0x1U << SCB_CFSR_IBUSERR_Pos)     /*!< 0x00000100 */
-#define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */
-#define SCB_CFSR_PRECISERR_Pos              (9U)                               
-#define SCB_CFSR_PRECISERR_Msk              (0x1U << SCB_CFSR_PRECISERR_Pos)   /*!< 0x00000200 */
-#define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */
-#define SCB_CFSR_IMPRECISERR_Pos            (10U)                              
-#define SCB_CFSR_IMPRECISERR_Msk            (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
-#define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */
-#define SCB_CFSR_UNSTKERR_Pos               (11U)                              
-#define SCB_CFSR_UNSTKERR_Msk               (0x1U << SCB_CFSR_UNSTKERR_Pos)    /*!< 0x00000800 */
-#define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */
-#define SCB_CFSR_STKERR_Pos                 (12U)                              
-#define SCB_CFSR_STKERR_Msk                 (0x1U << SCB_CFSR_STKERR_Pos)      /*!< 0x00001000 */
-#define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */
-#define SCB_CFSR_BFARVALID_Pos              (15U)                              
-#define SCB_CFSR_BFARVALID_Msk              (0x1U << SCB_CFSR_BFARVALID_Pos)   /*!< 0x00008000 */
-#define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define SCB_CFSR_UNDEFINSTR_Pos             (16U)                              
-#define SCB_CFSR_UNDEFINSTR_Msk             (0x1U << SCB_CFSR_UNDEFINSTR_Pos)  /*!< 0x00010000 */
-#define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to execute an undefined instruction */
-#define SCB_CFSR_INVSTATE_Pos               (17U)                              
-#define SCB_CFSR_INVSTATE_Msk               (0x1U << SCB_CFSR_INVSTATE_Pos)    /*!< 0x00020000 */
-#define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */
-#define SCB_CFSR_INVPC_Pos                  (18U)                              
-#define SCB_CFSR_INVPC_Msk                  (0x1U << SCB_CFSR_INVPC_Pos)       /*!< 0x00040000 */
-#define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */
-#define SCB_CFSR_NOCP_Pos                   (19U)                              
-#define SCB_CFSR_NOCP_Msk                   (0x1U << SCB_CFSR_NOCP_Pos)        /*!< 0x00080000 */
-#define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */
-#define SCB_CFSR_UNALIGNED_Pos              (24U)                              
-#define SCB_CFSR_UNALIGNED_Msk              (0x1U << SCB_CFSR_UNALIGNED_Pos)   /*!< 0x01000000 */
-#define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define SCB_CFSR_DIVBYZERO_Pos              (25U)                              
-#define SCB_CFSR_DIVBYZERO_Msk              (0x1U << SCB_CFSR_DIVBYZERO_Pos)   /*!< 0x02000000 */
-#define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/*******************  Bit definition for SCB_HFSR register  *******************/
-#define SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)             /*!< Fault occurs because of vector table read on exception processing */
-#define SCB_HFSR_FORCED                     ((uint32_t)0x40000000)             /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)             /*!< Fault related to debug */
-
-/*******************  Bit definition for SCB_DFSR register  *******************/
-#define SCB_DFSR_HALTED                     ((uint32_t)0x00000001)             /*!< Halt request flag */
-#define SCB_DFSR_BKPT                       ((uint32_t)0x00000002)             /*!< BKPT flag */
-#define SCB_DFSR_DWTTRAP                    ((uint32_t)0x00000004)             /*!< Data Watchpoint and Trace (DWT) flag */
-#define SCB_DFSR_VCATCH                     ((uint32_t)0x00000008)             /*!< Vector catch flag */
-#define SCB_DFSR_EXTERNAL                   ((uint32_t)0x00000010)             /*!< External debug request flag */
-
-/*******************  Bit definition for SCB_MMFAR register  ******************/
-#define SCB_MMFAR_ADDRESS_Pos               (0U)                               
-#define SCB_MMFAR_ADDRESS_Msk               (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_MMFAR_ADDRESS                   SCB_MMFAR_ADDRESS_Msk              /*!< Mem Manage fault address field */
-
-/*******************  Bit definition for SCB_BFAR register  *******************/
-#define SCB_BFAR_ADDRESS_Pos                (0U)                               
-#define SCB_BFAR_ADDRESS_Msk                (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_BFAR_ADDRESS                    SCB_BFAR_ADDRESS_Msk               /*!< Bus fault address field */
-
-/*******************  Bit definition for SCB_afsr register  *******************/
-#define SCB_AFSR_IMPDEF_Pos                 (0U)                               
-#define SCB_AFSR_IMPDEF_Msk                 (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
-#define SCB_AFSR_IMPDEF                     SCB_AFSR_IMPDEF_Msk                /*!< Implementation defined */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1U << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1U << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1U << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1U << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1U << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1U << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1U << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1U << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1U << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1U << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1U << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1U << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1U << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1U << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1U << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1U << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1U << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1U << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1U << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1U << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1U << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1U << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1U << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1U << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1U << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1U << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1U << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1U << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1U << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1U << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1U << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1U << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1U << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1U << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1U << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1U << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1U << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1U << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1U << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1U << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1U << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1U << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1U << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1U << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1U << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1U << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1U << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1U << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1U << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1U << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1U << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1U << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1U << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1U << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1U << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1U << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1U << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1U << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1U << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1U << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1U << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1U << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1U << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1U << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1U << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1U << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1U << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1U << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1U << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1U << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1U << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1U << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1U << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1U << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1U << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1U << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1U << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1U << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1U << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1U << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1U << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1U << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1U << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1U << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1U << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1U << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1U << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1U << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1U << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1U << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1U << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1U << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1U << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1U << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1U << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1U << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1U << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1U << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1U << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1U << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1U << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1U << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1U << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1U << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1U << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1U << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1U << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1U << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1U << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1U << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1U << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1U << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1U << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1U << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1U << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1U << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1U << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1U << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1U << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1U << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1U << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1U << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1U << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1U << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1U << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1U << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1U << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1U << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1U << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1U << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1U << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1U << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1U << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1U << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1U << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1U << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1U << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1U << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1U << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1U << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1U << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1U << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1U << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1U << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1U << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1U << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1U << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1U << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1U << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1U << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1U << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1U << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1U << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1U << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1U << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1U << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1U << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1U << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1U << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1U << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1U << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1U << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1U << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1U << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1U << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1U << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1U << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1U << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1U << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1U << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1U << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1U << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1U << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1U << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1U << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1U << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register   *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1U << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable */
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1U << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1U << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1U << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1U << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1U << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1U << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1U << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3U << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1U << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2U << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3U << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1U << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2U << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3U << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1U << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2U << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1U << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition for DMA_CNDTR  register  ******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFU << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CPAR  register  *******************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFU << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CMAR  register  *******************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFU << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
- */
-#define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                      (0U)                               
-#define ADC_SR_AWD_Msk                      (0x1U << ADC_SR_AWD_Pos)           /*!< 0x00000001 */
-#define ADC_SR_AWD                          ADC_SR_AWD_Msk                     /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOS_Pos                      (1U)                               
-#define ADC_SR_EOS_Msk                      (0x1U << ADC_SR_EOS_Pos)           /*!< 0x00000002 */
-#define ADC_SR_EOS                          ADC_SR_EOS_Msk                     /*!< ADC group regular end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                     (2U)                               
-#define ADC_SR_JEOS_Msk                     (0x1U << ADC_SR_JEOS_Pos)          /*!< 0x00000004 */
-#define ADC_SR_JEOS                         ADC_SR_JEOS_Msk                    /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                    (3U)                               
-#define ADC_SR_JSTRT_Msk                    (0x1U << ADC_SR_JSTRT_Pos)         /*!< 0x00000008 */
-#define ADC_SR_JSTRT                        ADC_SR_JSTRT_Msk                   /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                     (4U)                               
-#define ADC_SR_STRT_Msk                     (0x1U << ADC_SR_STRT_Pos)          /*!< 0x00000010 */
-#define ADC_SR_STRT                         ADC_SR_STRT_Msk                    /*!< ADC group regular conversion start flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                   (0U)                               
-#define ADC_CR1_AWDCH_Msk                   (0x1FU << ADC_CR1_AWDCH_Pos)       /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                       ADC_CR1_AWDCH_Msk                  /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                     (0x01U << ADC_CR1_AWDCH_Pos)       /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                     (0x02U << ADC_CR1_AWDCH_Pos)       /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                     (0x04U << ADC_CR1_AWDCH_Pos)       /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                     (0x08U << ADC_CR1_AWDCH_Pos)       /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                     (0x10U << ADC_CR1_AWDCH_Pos)       /*!< 0x00000010 */
-
-#define ADC_CR1_EOSIE_Pos                   (5U)                               
-#define ADC_CR1_EOSIE_Msk                   (0x1U << ADC_CR1_EOSIE_Pos)        /*!< 0x00000020 */
-#define ADC_CR1_EOSIE                       ADC_CR1_EOSIE_Msk                  /*!< ADC group regular end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                   (6U)                               
-#define ADC_CR1_AWDIE_Msk                   (0x1U << ADC_CR1_AWDIE_Pos)        /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                       ADC_CR1_AWDIE_Msk                  /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                  (7U)                               
-#define ADC_CR1_JEOSIE_Msk                  (0x1U << ADC_CR1_JEOSIE_Pos)       /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                      ADC_CR1_JEOSIE_Msk                 /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                    (8U)                               
-#define ADC_CR1_SCAN_Msk                    (0x1U << ADC_CR1_SCAN_Pos)         /*!< 0x00000100 */
-#define ADC_CR1_SCAN                        ADC_CR1_SCAN_Msk                   /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                  (9U)                               
-#define ADC_CR1_AWDSGL_Msk                  (0x1U << ADC_CR1_AWDSGL_Pos)       /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                      ADC_CR1_AWDSGL_Msk                 /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                   (10U)                              
-#define ADC_CR1_JAUTO_Msk                   (0x1U << ADC_CR1_JAUTO_Pos)        /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                       ADC_CR1_JAUTO_Msk                  /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                  (11U)                              
-#define ADC_CR1_DISCEN_Msk                  (0x1U << ADC_CR1_DISCEN_Pos)       /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                      ADC_CR1_DISCEN_Msk                 /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                 (12U)                              
-#define ADC_CR1_JDISCEN_Msk                 (0x1U << ADC_CR1_JDISCEN_Pos)      /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                     ADC_CR1_JDISCEN_Msk                /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                 (13U)                              
-#define ADC_CR1_DISCNUM_Msk                 (0x7U << ADC_CR1_DISCNUM_Pos)      /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                     ADC_CR1_DISCNUM_Msk                /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                   (0x1U << ADC_CR1_DISCNUM_Pos)      /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                   (0x2U << ADC_CR1_DISCNUM_Pos)      /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                   (0x4U << ADC_CR1_DISCNUM_Pos)      /*!< 0x00008000 */
-
-#define ADC_CR1_DUALMOD_Pos                 (16U)                              
-#define ADC_CR1_DUALMOD_Msk                 (0xFU << ADC_CR1_DUALMOD_Pos)      /*!< 0x000F0000 */
-#define ADC_CR1_DUALMOD                     ADC_CR1_DUALMOD_Msk                /*!< ADC multimode mode selection */
-#define ADC_CR1_DUALMOD_0                   (0x1U << ADC_CR1_DUALMOD_Pos)      /*!< 0x00010000 */
-#define ADC_CR1_DUALMOD_1                   (0x2U << ADC_CR1_DUALMOD_Pos)      /*!< 0x00020000 */
-#define ADC_CR1_DUALMOD_2                   (0x4U << ADC_CR1_DUALMOD_Pos)      /*!< 0x00040000 */
-#define ADC_CR1_DUALMOD_3                   (0x8U << ADC_CR1_DUALMOD_Pos)      /*!< 0x00080000 */
-
-#define ADC_CR1_JAWDEN_Pos                  (22U)                              
-#define ADC_CR1_JAWDEN_Msk                  (0x1U << ADC_CR1_JAWDEN_Pos)       /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                      ADC_CR1_JAWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                   (23U)                              
-#define ADC_CR1_AWDEN_Msk                   (0x1U << ADC_CR1_AWDEN_Pos)        /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                       ADC_CR1_AWDEN_Msk                  /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                    (0U)                               
-#define ADC_CR2_ADON_Msk                    (0x1U << ADC_CR2_ADON_Pos)         /*!< 0x00000001 */
-#define ADC_CR2_ADON                        ADC_CR2_ADON_Msk                   /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                    (1U)                               
-#define ADC_CR2_CONT_Msk                    (0x1U << ADC_CR2_CONT_Pos)         /*!< 0x00000002 */
-#define ADC_CR2_CONT                        ADC_CR2_CONT_Msk                   /*!< ADC group regular continuous conversion mode */
-#define ADC_CR2_CAL_Pos                     (2U)                               
-#define ADC_CR2_CAL_Msk                     (0x1U << ADC_CR2_CAL_Pos)          /*!< 0x00000004 */
-#define ADC_CR2_CAL                         ADC_CR2_CAL_Msk                    /*!< ADC calibration start */
-#define ADC_CR2_RSTCAL_Pos                  (3U)                               
-#define ADC_CR2_RSTCAL_Msk                  (0x1U << ADC_CR2_RSTCAL_Pos)       /*!< 0x00000008 */
-#define ADC_CR2_RSTCAL                      ADC_CR2_RSTCAL_Msk                 /*!< ADC calibration reset */
-#define ADC_CR2_DMA_Pos                     (8U)                               
-#define ADC_CR2_DMA_Msk                     (0x1U << ADC_CR2_DMA_Pos)          /*!< 0x00000100 */
-#define ADC_CR2_DMA                         ADC_CR2_DMA_Msk                    /*!< ADC DMA transfer enable */
-#define ADC_CR2_ALIGN_Pos                   (11U)                              
-#define ADC_CR2_ALIGN_Msk                   (0x1U << ADC_CR2_ALIGN_Pos)        /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                       ADC_CR2_ALIGN_Msk                  /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                 (12U)                              
-#define ADC_CR2_JEXTSEL_Msk                 (0x7U << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00007000 */
-#define ADC_CR2_JEXTSEL                     ADC_CR2_JEXTSEL_Msk                /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                   (0x1U << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00001000 */
-#define ADC_CR2_JEXTSEL_1                   (0x2U << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00002000 */
-#define ADC_CR2_JEXTSEL_2                   (0x4U << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00004000 */
-
-#define ADC_CR2_JEXTTRIG_Pos                (15U)                              
-#define ADC_CR2_JEXTTRIG_Msk                (0x1U << ADC_CR2_JEXTTRIG_Pos)     /*!< 0x00008000 */
-#define ADC_CR2_JEXTTRIG                    ADC_CR2_JEXTTRIG_Msk               /*!< ADC group injected external trigger enable */
-
-#define ADC_CR2_EXTSEL_Pos                  (17U)                              
-#define ADC_CR2_EXTSEL_Msk                  (0x7U << ADC_CR2_EXTSEL_Pos)       /*!< 0x000E0000 */
-#define ADC_CR2_EXTSEL                      ADC_CR2_EXTSEL_Msk                 /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                    (0x1U << ADC_CR2_EXTSEL_Pos)       /*!< 0x00020000 */
-#define ADC_CR2_EXTSEL_1                    (0x2U << ADC_CR2_EXTSEL_Pos)       /*!< 0x00040000 */
-#define ADC_CR2_EXTSEL_2                    (0x4U << ADC_CR2_EXTSEL_Pos)       /*!< 0x00080000 */
-
-#define ADC_CR2_EXTTRIG_Pos                 (20U)                              
-#define ADC_CR2_EXTTRIG_Msk                 (0x1U << ADC_CR2_EXTTRIG_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_EXTTRIG                     ADC_CR2_EXTTRIG_Msk                /*!< ADC group regular external trigger enable */
-#define ADC_CR2_JSWSTART_Pos                (21U)                              
-#define ADC_CR2_JSWSTART_Msk                (0x1U << ADC_CR2_JSWSTART_Pos)     /*!< 0x00200000 */
-#define ADC_CR2_JSWSTART                    ADC_CR2_JSWSTART_Msk               /*!< ADC group injected conversion start */
-#define ADC_CR2_SWSTART_Pos                 (22U)                              
-#define ADC_CR2_SWSTART_Msk                 (0x1U << ADC_CR2_SWSTART_Pos)      /*!< 0x00400000 */
-#define ADC_CR2_SWSTART                     ADC_CR2_SWSTART_Msk                /*!< ADC group regular conversion start */
-#define ADC_CR2_TSVREFE_Pos                 (23U)                              
-#define ADC_CR2_TSVREFE_Msk                 (0x1U << ADC_CR2_TSVREFE_Pos)      /*!< 0x00800000 */
-#define ADC_CR2_TSVREFE                     ADC_CR2_TSVREFE_Msk                /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP10_Pos                 (0U)                               
-#define ADC_SMPR1_SMP10_Msk                 (0x7U << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR1_SMP10                     ADC_SMPR1_SMP10_Msk                /*!< ADC channel 10 sampling time selection  */
-#define ADC_SMPR1_SMP10_0                   (0x1U << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR1_SMP10_1                   (0x2U << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR1_SMP10_2                   (0x4U << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP11_Pos                 (3U)                               
-#define ADC_SMPR1_SMP11_Msk                 (0x7U << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR1_SMP11                     ADC_SMPR1_SMP11_Msk                /*!< ADC channel 11 sampling time selection  */
-#define ADC_SMPR1_SMP11_0                   (0x1U << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR1_SMP11_1                   (0x2U << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR1_SMP11_2                   (0x4U << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP12_Pos                 (6U)                               
-#define ADC_SMPR1_SMP12_Msk                 (0x7U << ADC_SMPR1_SMP12_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP12                     ADC_SMPR1_SMP12_Msk                /*!< ADC channel 12 sampling time selection  */
-#define ADC_SMPR1_SMP12_0                   (0x1U << ADC_SMPR1_SMP12_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR1_SMP12_1                   (0x2U << ADC_SMPR1_SMP12_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR1_SMP12_2                   (0x4U << ADC_SMPR1_SMP12_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP13_Pos                 (9U)                               
-#define ADC_SMPR1_SMP13_Msk                 (0x7U << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP13                     ADC_SMPR1_SMP13_Msk                /*!< ADC channel 13 sampling time selection  */
-#define ADC_SMPR1_SMP13_0                   (0x1U << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR1_SMP13_1                   (0x2U << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR1_SMP13_2                   (0x4U << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP14_Pos                 (12U)                              
-#define ADC_SMPR1_SMP14_Msk                 (0x7U << ADC_SMPR1_SMP14_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR1_SMP14                     ADC_SMPR1_SMP14_Msk                /*!< ADC channel 14 sampling time selection  */
-#define ADC_SMPR1_SMP14_0                   (0x1U << ADC_SMPR1_SMP14_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR1_SMP14_1                   (0x2U << ADC_SMPR1_SMP14_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR1_SMP14_2                   (0x4U << ADC_SMPR1_SMP14_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP15_Pos                 (15U)                              
-#define ADC_SMPR1_SMP15_Msk                 (0x7U << ADC_SMPR1_SMP15_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR1_SMP15                     ADC_SMPR1_SMP15_Msk                /*!< ADC channel 15 sampling time selection  */
-#define ADC_SMPR1_SMP15_0                   (0x1U << ADC_SMPR1_SMP15_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR1_SMP15_1                   (0x2U << ADC_SMPR1_SMP15_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR1_SMP15_2                   (0x4U << ADC_SMPR1_SMP15_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP16_Pos                 (18U)                              
-#define ADC_SMPR1_SMP16_Msk                 (0x7U << ADC_SMPR1_SMP16_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP16                     ADC_SMPR1_SMP16_Msk                /*!< ADC channel 16 sampling time selection  */
-#define ADC_SMPR1_SMP16_0                   (0x1U << ADC_SMPR1_SMP16_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR1_SMP16_1                   (0x2U << ADC_SMPR1_SMP16_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR1_SMP16_2                   (0x4U << ADC_SMPR1_SMP16_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR1_SMP17_Pos                 (21U)                              
-#define ADC_SMPR1_SMP17_Msk                 (0x7U << ADC_SMPR1_SMP17_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP17                     ADC_SMPR1_SMP17_Msk                /*!< ADC channel 17 sampling time selection  */
-#define ADC_SMPR1_SMP17_0                   (0x1U << ADC_SMPR1_SMP17_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR1_SMP17_1                   (0x2U << ADC_SMPR1_SMP17_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR1_SMP17_2                   (0x4U << ADC_SMPR1_SMP17_Pos)      /*!< 0x00800000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP0_Pos                  (0U)                               
-#define ADC_SMPR2_SMP0_Msk                  (0x7U << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000007 */
-#define ADC_SMPR2_SMP0                      ADC_SMPR2_SMP0_Msk                 /*!< ADC channel 0 sampling time selection  */
-#define ADC_SMPR2_SMP0_0                    (0x1U << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000001 */
-#define ADC_SMPR2_SMP0_1                    (0x2U << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000002 */
-#define ADC_SMPR2_SMP0_2                    (0x4U << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP1_Pos                  (3U)                               
-#define ADC_SMPR2_SMP1_Msk                  (0x7U << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000038 */
-#define ADC_SMPR2_SMP1                      ADC_SMPR2_SMP1_Msk                 /*!< ADC channel 1 sampling time selection  */
-#define ADC_SMPR2_SMP1_0                    (0x1U << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000008 */
-#define ADC_SMPR2_SMP1_1                    (0x2U << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000010 */
-#define ADC_SMPR2_SMP1_2                    (0x4U << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP2_Pos                  (6U)                               
-#define ADC_SMPR2_SMP2_Msk                  (0x7U << ADC_SMPR2_SMP2_Pos)       /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP2                      ADC_SMPR2_SMP2_Msk                 /*!< ADC channel 2 sampling time selection  */
-#define ADC_SMPR2_SMP2_0                    (0x1U << ADC_SMPR2_SMP2_Pos)       /*!< 0x00000040 */
-#define ADC_SMPR2_SMP2_1                    (0x2U << ADC_SMPR2_SMP2_Pos)       /*!< 0x00000080 */
-#define ADC_SMPR2_SMP2_2                    (0x4U << ADC_SMPR2_SMP2_Pos)       /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP3_Pos                  (9U)                               
-#define ADC_SMPR2_SMP3_Msk                  (0x7U << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP3                      ADC_SMPR2_SMP3_Msk                 /*!< ADC channel 3 sampling time selection  */
-#define ADC_SMPR2_SMP3_0                    (0x1U << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000200 */
-#define ADC_SMPR2_SMP3_1                    (0x2U << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000400 */
-#define ADC_SMPR2_SMP3_2                    (0x4U << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP4_Pos                  (12U)                              
-#define ADC_SMPR2_SMP4_Msk                  (0x7U << ADC_SMPR2_SMP4_Pos)       /*!< 0x00007000 */
-#define ADC_SMPR2_SMP4                      ADC_SMPR2_SMP4_Msk                 /*!< ADC channel 4 sampling time selection  */
-#define ADC_SMPR2_SMP4_0                    (0x1U << ADC_SMPR2_SMP4_Pos)       /*!< 0x00001000 */
-#define ADC_SMPR2_SMP4_1                    (0x2U << ADC_SMPR2_SMP4_Pos)       /*!< 0x00002000 */
-#define ADC_SMPR2_SMP4_2                    (0x4U << ADC_SMPR2_SMP4_Pos)       /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP5_Pos                  (15U)                              
-#define ADC_SMPR2_SMP5_Msk                  (0x7U << ADC_SMPR2_SMP5_Pos)       /*!< 0x00038000 */
-#define ADC_SMPR2_SMP5                      ADC_SMPR2_SMP5_Msk                 /*!< ADC channel 5 sampling time selection  */
-#define ADC_SMPR2_SMP5_0                    (0x1U << ADC_SMPR2_SMP5_Pos)       /*!< 0x00008000 */
-#define ADC_SMPR2_SMP5_1                    (0x2U << ADC_SMPR2_SMP5_Pos)       /*!< 0x00010000 */
-#define ADC_SMPR2_SMP5_2                    (0x4U << ADC_SMPR2_SMP5_Pos)       /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP6_Pos                  (18U)                              
-#define ADC_SMPR2_SMP6_Msk                  (0x7U << ADC_SMPR2_SMP6_Pos)       /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP6                      ADC_SMPR2_SMP6_Msk                 /*!< ADC channel 6 sampling time selection  */
-#define ADC_SMPR2_SMP6_0                    (0x1U << ADC_SMPR2_SMP6_Pos)       /*!< 0x00040000 */
-#define ADC_SMPR2_SMP6_1                    (0x2U << ADC_SMPR2_SMP6_Pos)       /*!< 0x00080000 */
-#define ADC_SMPR2_SMP6_2                    (0x4U << ADC_SMPR2_SMP6_Pos)       /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP7_Pos                  (21U)                              
-#define ADC_SMPR2_SMP7_Msk                  (0x7U << ADC_SMPR2_SMP7_Pos)       /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP7                      ADC_SMPR2_SMP7_Msk                 /*!< ADC channel 7 sampling time selection  */
-#define ADC_SMPR2_SMP7_0                    (0x1U << ADC_SMPR2_SMP7_Pos)       /*!< 0x00200000 */
-#define ADC_SMPR2_SMP7_1                    (0x2U << ADC_SMPR2_SMP7_Pos)       /*!< 0x00400000 */
-#define ADC_SMPR2_SMP7_2                    (0x4U << ADC_SMPR2_SMP7_Pos)       /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP8_Pos                  (24U)                              
-#define ADC_SMPR2_SMP8_Msk                  (0x7U << ADC_SMPR2_SMP8_Pos)       /*!< 0x07000000 */
-#define ADC_SMPR2_SMP8                      ADC_SMPR2_SMP8_Msk                 /*!< ADC channel 8 sampling time selection  */
-#define ADC_SMPR2_SMP8_0                    (0x1U << ADC_SMPR2_SMP8_Pos)       /*!< 0x01000000 */
-#define ADC_SMPR2_SMP8_1                    (0x2U << ADC_SMPR2_SMP8_Pos)       /*!< 0x02000000 */
-#define ADC_SMPR2_SMP8_2                    (0x4U << ADC_SMPR2_SMP8_Pos)       /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP9_Pos                  (27U)                              
-#define ADC_SMPR2_SMP9_Msk                  (0x7U << ADC_SMPR2_SMP9_Pos)       /*!< 0x38000000 */
-#define ADC_SMPR2_SMP9                      ADC_SMPR2_SMP9_Msk                 /*!< ADC channel 9 sampling time selection  */
-#define ADC_SMPR2_SMP9_0                    (0x1U << ADC_SMPR2_SMP9_Pos)       /*!< 0x08000000 */
-#define ADC_SMPR2_SMP9_1                    (0x2U << ADC_SMPR2_SMP9_Pos)       /*!< 0x10000000 */
-#define ADC_SMPR2_SMP9_2                    (0x4U << ADC_SMPR2_SMP9_Pos)       /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos              (0U)                               
-#define ADC_JOFR1_JOFFSET1_Msk              (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                  ADC_JOFR1_JOFFSET1_Msk             /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos              (0U)                               
-#define ADC_JOFR2_JOFFSET2_Msk              (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                  ADC_JOFR2_JOFFSET2_Msk             /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos              (0U)                               
-#define ADC_JOFR3_JOFFSET3_Msk              (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                  ADC_JOFR3_JOFFSET3_Msk             /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos              (0U)                               
-#define ADC_JOFR4_JOFFSET4_Msk              (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                  ADC_JOFR4_JOFFSET4_Msk             /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                      (0U)                               
-#define ADC_HTR_HT_Msk                      (0xFFFU << ADC_HTR_HT_Pos)         /*!< 0x00000FFF */
-#define ADC_HTR_HT                          ADC_HTR_HT_Msk                     /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                      (0U)                               
-#define ADC_LTR_LT_Msk                      (0xFFFU << ADC_LTR_LT_Pos)         /*!< 0x00000FFF */
-#define ADC_LTR_LT                          ADC_LTR_LT_Msk                     /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_SQ13_Pos                   (0U)                               
-#define ADC_SQR1_SQ13_Msk                   (0x1FU << ADC_SQR1_SQ13_Pos)       /*!< 0x0000001F */
-#define ADC_SQR1_SQ13                       ADC_SQR1_SQ13_Msk                  /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR1_SQ13_0                     (0x01U << ADC_SQR1_SQ13_Pos)       /*!< 0x00000001 */
-#define ADC_SQR1_SQ13_1                     (0x02U << ADC_SQR1_SQ13_Pos)       /*!< 0x00000002 */
-#define ADC_SQR1_SQ13_2                     (0x04U << ADC_SQR1_SQ13_Pos)       /*!< 0x00000004 */
-#define ADC_SQR1_SQ13_3                     (0x08U << ADC_SQR1_SQ13_Pos)       /*!< 0x00000008 */
-#define ADC_SQR1_SQ13_4                     (0x10U << ADC_SQR1_SQ13_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR1_SQ14_Pos                   (5U)                               
-#define ADC_SQR1_SQ14_Msk                   (0x1FU << ADC_SQR1_SQ14_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR1_SQ14                       ADC_SQR1_SQ14_Msk                  /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR1_SQ14_0                     (0x01U << ADC_SQR1_SQ14_Pos)       /*!< 0x00000020 */
-#define ADC_SQR1_SQ14_1                     (0x02U << ADC_SQR1_SQ14_Pos)       /*!< 0x00000040 */
-#define ADC_SQR1_SQ14_2                     (0x04U << ADC_SQR1_SQ14_Pos)       /*!< 0x00000080 */
-#define ADC_SQR1_SQ14_3                     (0x08U << ADC_SQR1_SQ14_Pos)       /*!< 0x00000100 */
-#define ADC_SQR1_SQ14_4                     (0x10U << ADC_SQR1_SQ14_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ15_Pos                   (10U)                              
-#define ADC_SQR1_SQ15_Msk                   (0x1FU << ADC_SQR1_SQ15_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR1_SQ15                       ADC_SQR1_SQ15_Msk                  /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR1_SQ15_0                     (0x01U << ADC_SQR1_SQ15_Pos)       /*!< 0x00000400 */
-#define ADC_SQR1_SQ15_1                     (0x02U << ADC_SQR1_SQ15_Pos)       /*!< 0x00000800 */
-#define ADC_SQR1_SQ15_2                     (0x04U << ADC_SQR1_SQ15_Pos)       /*!< 0x00001000 */
-#define ADC_SQR1_SQ15_3                     (0x08U << ADC_SQR1_SQ15_Pos)       /*!< 0x00002000 */
-#define ADC_SQR1_SQ15_4                     (0x10U << ADC_SQR1_SQ15_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ16_Pos                   (15U)                              
-#define ADC_SQR1_SQ16_Msk                   (0x1FU << ADC_SQR1_SQ16_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR1_SQ16                       ADC_SQR1_SQ16_Msk                  /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR1_SQ16_0                     (0x01U << ADC_SQR1_SQ16_Pos)       /*!< 0x00008000 */
-#define ADC_SQR1_SQ16_1                     (0x02U << ADC_SQR1_SQ16_Pos)       /*!< 0x00010000 */
-#define ADC_SQR1_SQ16_2                     (0x04U << ADC_SQR1_SQ16_Pos)       /*!< 0x00020000 */
-#define ADC_SQR1_SQ16_3                     (0x08U << ADC_SQR1_SQ16_Pos)       /*!< 0x00040000 */
-#define ADC_SQR1_SQ16_4                     (0x10U << ADC_SQR1_SQ16_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR1_L_Pos                      (20U)                              
-#define ADC_SQR1_L_Msk                      (0xFU << ADC_SQR1_L_Pos)           /*!< 0x00F00000 */
-#define ADC_SQR1_L                          ADC_SQR1_L_Msk                     /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                        (0x1U << ADC_SQR1_L_Pos)           /*!< 0x00100000 */
-#define ADC_SQR1_L_1                        (0x2U << ADC_SQR1_L_Pos)           /*!< 0x00200000 */
-#define ADC_SQR1_L_2                        (0x4U << ADC_SQR1_L_Pos)           /*!< 0x00400000 */
-#define ADC_SQR1_L_3                        (0x8U << ADC_SQR1_L_Pos)           /*!< 0x00800000 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ7_Pos                    (0U)                               
-#define ADC_SQR2_SQ7_Msk                    (0x1FU << ADC_SQR2_SQ7_Pos)        /*!< 0x0000001F */
-#define ADC_SQR2_SQ7                        ADC_SQR2_SQ7_Msk                   /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR2_SQ7_0                      (0x01U << ADC_SQR2_SQ7_Pos)        /*!< 0x00000001 */
-#define ADC_SQR2_SQ7_1                      (0x02U << ADC_SQR2_SQ7_Pos)        /*!< 0x00000002 */
-#define ADC_SQR2_SQ7_2                      (0x04U << ADC_SQR2_SQ7_Pos)        /*!< 0x00000004 */
-#define ADC_SQR2_SQ7_3                      (0x08U << ADC_SQR2_SQ7_Pos)        /*!< 0x00000008 */
-#define ADC_SQR2_SQ7_4                      (0x10U << ADC_SQR2_SQ7_Pos)        /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ8_Pos                    (5U)                               
-#define ADC_SQR2_SQ8_Msk                    (0x1FU << ADC_SQR2_SQ8_Pos)        /*!< 0x000003E0 */
-#define ADC_SQR2_SQ8                        ADC_SQR2_SQ8_Msk                   /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR2_SQ8_0                      (0x01U << ADC_SQR2_SQ8_Pos)        /*!< 0x00000020 */
-#define ADC_SQR2_SQ8_1                      (0x02U << ADC_SQR2_SQ8_Pos)        /*!< 0x00000040 */
-#define ADC_SQR2_SQ8_2                      (0x04U << ADC_SQR2_SQ8_Pos)        /*!< 0x00000080 */
-#define ADC_SQR2_SQ8_3                      (0x08U << ADC_SQR2_SQ8_Pos)        /*!< 0x00000100 */
-#define ADC_SQR2_SQ8_4                      (0x10U << ADC_SQR2_SQ8_Pos)        /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ9_Pos                    (10U)                              
-#define ADC_SQR2_SQ9_Msk                    (0x1FU << ADC_SQR2_SQ9_Pos)        /*!< 0x00007C00 */
-#define ADC_SQR2_SQ9                        ADC_SQR2_SQ9_Msk                   /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR2_SQ9_0                      (0x01U << ADC_SQR2_SQ9_Pos)        /*!< 0x00000400 */
-#define ADC_SQR2_SQ9_1                      (0x02U << ADC_SQR2_SQ9_Pos)        /*!< 0x00000800 */
-#define ADC_SQR2_SQ9_2                      (0x04U << ADC_SQR2_SQ9_Pos)        /*!< 0x00001000 */
-#define ADC_SQR2_SQ9_3                      (0x08U << ADC_SQR2_SQ9_Pos)        /*!< 0x00002000 */
-#define ADC_SQR2_SQ9_4                      (0x10U << ADC_SQR2_SQ9_Pos)        /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ10_Pos                   (15U)                              
-#define ADC_SQR2_SQ10_Msk                   (0x1FU << ADC_SQR2_SQ10_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR2_SQ10                       ADC_SQR2_SQ10_Msk                  /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR2_SQ10_0                     (0x01U << ADC_SQR2_SQ10_Pos)       /*!< 0x00008000 */
-#define ADC_SQR2_SQ10_1                     (0x02U << ADC_SQR2_SQ10_Pos)       /*!< 0x00010000 */
-#define ADC_SQR2_SQ10_2                     (0x04U << ADC_SQR2_SQ10_Pos)       /*!< 0x00020000 */
-#define ADC_SQR2_SQ10_3                     (0x08U << ADC_SQR2_SQ10_Pos)       /*!< 0x00040000 */
-#define ADC_SQR2_SQ10_4                     (0x10U << ADC_SQR2_SQ10_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ11_Pos                   (20U)                              
-#define ADC_SQR2_SQ11_Msk                   (0x1FU << ADC_SQR2_SQ11_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR2_SQ11                       ADC_SQR2_SQ11_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR2_SQ11_0                     (0x01U << ADC_SQR2_SQ11_Pos)       /*!< 0x00100000 */
-#define ADC_SQR2_SQ11_1                     (0x02U << ADC_SQR2_SQ11_Pos)       /*!< 0x00200000 */
-#define ADC_SQR2_SQ11_2                     (0x04U << ADC_SQR2_SQ11_Pos)       /*!< 0x00400000 */
-#define ADC_SQR2_SQ11_3                     (0x08U << ADC_SQR2_SQ11_Pos)       /*!< 0x00800000 */
-#define ADC_SQR2_SQ11_4                     (0x10U << ADC_SQR2_SQ11_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ12_Pos                   (25U)                              
-#define ADC_SQR2_SQ12_Msk                   (0x1FU << ADC_SQR2_SQ12_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR2_SQ12                       ADC_SQR2_SQ12_Msk                  /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR2_SQ12_0                     (0x01U << ADC_SQR2_SQ12_Pos)       /*!< 0x02000000 */
-#define ADC_SQR2_SQ12_1                     (0x02U << ADC_SQR2_SQ12_Pos)       /*!< 0x04000000 */
-#define ADC_SQR2_SQ12_2                     (0x04U << ADC_SQR2_SQ12_Pos)       /*!< 0x08000000 */
-#define ADC_SQR2_SQ12_3                     (0x08U << ADC_SQR2_SQ12_Pos)       /*!< 0x10000000 */
-#define ADC_SQR2_SQ12_4                     (0x10U << ADC_SQR2_SQ12_Pos)       /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ1_Pos                    (0U)                               
-#define ADC_SQR3_SQ1_Msk                    (0x1FU << ADC_SQR3_SQ1_Pos)        /*!< 0x0000001F */
-#define ADC_SQR3_SQ1                        ADC_SQR3_SQ1_Msk                   /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR3_SQ1_0                      (0x01U << ADC_SQR3_SQ1_Pos)        /*!< 0x00000001 */
-#define ADC_SQR3_SQ1_1                      (0x02U << ADC_SQR3_SQ1_Pos)        /*!< 0x00000002 */
-#define ADC_SQR3_SQ1_2                      (0x04U << ADC_SQR3_SQ1_Pos)        /*!< 0x00000004 */
-#define ADC_SQR3_SQ1_3                      (0x08U << ADC_SQR3_SQ1_Pos)        /*!< 0x00000008 */
-#define ADC_SQR3_SQ1_4                      (0x10U << ADC_SQR3_SQ1_Pos)        /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ2_Pos                    (5U)                               
-#define ADC_SQR3_SQ2_Msk                    (0x1FU << ADC_SQR3_SQ2_Pos)        /*!< 0x000003E0 */
-#define ADC_SQR3_SQ2                        ADC_SQR3_SQ2_Msk                   /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR3_SQ2_0                      (0x01U << ADC_SQR3_SQ2_Pos)        /*!< 0x00000020 */
-#define ADC_SQR3_SQ2_1                      (0x02U << ADC_SQR3_SQ2_Pos)        /*!< 0x00000040 */
-#define ADC_SQR3_SQ2_2                      (0x04U << ADC_SQR3_SQ2_Pos)        /*!< 0x00000080 */
-#define ADC_SQR3_SQ2_3                      (0x08U << ADC_SQR3_SQ2_Pos)        /*!< 0x00000100 */
-#define ADC_SQR3_SQ2_4                      (0x10U << ADC_SQR3_SQ2_Pos)        /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ3_Pos                    (10U)                              
-#define ADC_SQR3_SQ3_Msk                    (0x1FU << ADC_SQR3_SQ3_Pos)        /*!< 0x00007C00 */
-#define ADC_SQR3_SQ3                        ADC_SQR3_SQ3_Msk                   /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR3_SQ3_0                      (0x01U << ADC_SQR3_SQ3_Pos)        /*!< 0x00000400 */
-#define ADC_SQR3_SQ3_1                      (0x02U << ADC_SQR3_SQ3_Pos)        /*!< 0x00000800 */
-#define ADC_SQR3_SQ3_2                      (0x04U << ADC_SQR3_SQ3_Pos)        /*!< 0x00001000 */
-#define ADC_SQR3_SQ3_3                      (0x08U << ADC_SQR3_SQ3_Pos)        /*!< 0x00002000 */
-#define ADC_SQR3_SQ3_4                      (0x10U << ADC_SQR3_SQ3_Pos)        /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ4_Pos                    (15U)                              
-#define ADC_SQR3_SQ4_Msk                    (0x1FU << ADC_SQR3_SQ4_Pos)        /*!< 0x000F8000 */
-#define ADC_SQR3_SQ4                        ADC_SQR3_SQ4_Msk                   /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR3_SQ4_0                      (0x01U << ADC_SQR3_SQ4_Pos)        /*!< 0x00008000 */
-#define ADC_SQR3_SQ4_1                      (0x02U << ADC_SQR3_SQ4_Pos)        /*!< 0x00010000 */
-#define ADC_SQR3_SQ4_2                      (0x04U << ADC_SQR3_SQ4_Pos)        /*!< 0x00020000 */
-#define ADC_SQR3_SQ4_3                      (0x08U << ADC_SQR3_SQ4_Pos)        /*!< 0x00040000 */
-#define ADC_SQR3_SQ4_4                      (0x10U << ADC_SQR3_SQ4_Pos)        /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ5_Pos                    (20U)                              
-#define ADC_SQR3_SQ5_Msk                    (0x1FU << ADC_SQR3_SQ5_Pos)        /*!< 0x01F00000 */
-#define ADC_SQR3_SQ5                        ADC_SQR3_SQ5_Msk                   /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR3_SQ5_0                      (0x01U << ADC_SQR3_SQ5_Pos)        /*!< 0x00100000 */
-#define ADC_SQR3_SQ5_1                      (0x02U << ADC_SQR3_SQ5_Pos)        /*!< 0x00200000 */
-#define ADC_SQR3_SQ5_2                      (0x04U << ADC_SQR3_SQ5_Pos)        /*!< 0x00400000 */
-#define ADC_SQR3_SQ5_3                      (0x08U << ADC_SQR3_SQ5_Pos)        /*!< 0x00800000 */
-#define ADC_SQR3_SQ5_4                      (0x10U << ADC_SQR3_SQ5_Pos)        /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ6_Pos                    (25U)                              
-#define ADC_SQR3_SQ6_Msk                    (0x1FU << ADC_SQR3_SQ6_Pos)        /*!< 0x3E000000 */
-#define ADC_SQR3_SQ6                        ADC_SQR3_SQ6_Msk                   /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR3_SQ6_0                      (0x01U << ADC_SQR3_SQ6_Pos)        /*!< 0x02000000 */
-#define ADC_SQR3_SQ6_1                      (0x02U << ADC_SQR3_SQ6_Pos)        /*!< 0x04000000 */
-#define ADC_SQR3_SQ6_2                      (0x04U << ADC_SQR3_SQ6_Pos)        /*!< 0x08000000 */
-#define ADC_SQR3_SQ6_3                      (0x08U << ADC_SQR3_SQ6_Pos)        /*!< 0x10000000 */
-#define ADC_SQR3_SQ6_4                      (0x10U << ADC_SQR3_SQ6_Pos)        /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                   (0U)                               
-#define ADC_JSQR_JSQ1_Msk                   (0x1FU << ADC_JSQR_JSQ1_Pos)       /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                       ADC_JSQR_JSQ1_Msk                  /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                     (0x01U << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                     (0x02U << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                     (0x04U << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                     (0x08U << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                     (0x10U << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                   (5U)                               
-#define ADC_JSQR_JSQ2_Msk                   (0x1FU << ADC_JSQR_JSQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                       ADC_JSQR_JSQ2_Msk                  /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                     (0x01U << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                     (0x02U << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                     (0x04U << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                     (0x08U << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                     (0x10U << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                   (10U)                              
-#define ADC_JSQR_JSQ3_Msk                   (0x1FU << ADC_JSQR_JSQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                       ADC_JSQR_JSQ3_Msk                  /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                     (0x01U << ADC_JSQR_JSQ3_Pos)       /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                     (0x02U << ADC_JSQR_JSQ3_Pos)       /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                     (0x04U << ADC_JSQR_JSQ3_Pos)       /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                     (0x08U << ADC_JSQR_JSQ3_Pos)       /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                     (0x10U << ADC_JSQR_JSQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                   (15U)                              
-#define ADC_JSQR_JSQ4_Msk                   (0x1FU << ADC_JSQR_JSQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                       ADC_JSQR_JSQ4_Msk                  /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                     (0x01U << ADC_JSQR_JSQ4_Pos)       /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                     (0x02U << ADC_JSQR_JSQ4_Pos)       /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                     (0x04U << ADC_JSQR_JSQ4_Pos)       /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                     (0x08U << ADC_JSQR_JSQ4_Pos)       /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                     (0x10U << ADC_JSQR_JSQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                     (20U)                              
-#define ADC_JSQR_JL_Msk                     (0x3U << ADC_JSQR_JL_Pos)          /*!< 0x00300000 */
-#define ADC_JSQR_JL                         ADC_JSQR_JL_Msk                    /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                       (0x1U << ADC_JSQR_JL_Pos)          /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                       (0x2U << ADC_JSQR_JL_Pos)          /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                  (0U)                               
-#define ADC_JDR1_JDATA_Msk                  (0xFFFFU << ADC_JDR1_JDATA_Pos)    /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                      ADC_JDR1_JDATA_Msk                 /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                  (0U)                               
-#define ADC_JDR2_JDATA_Msk                  (0xFFFFU << ADC_JDR2_JDATA_Pos)    /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                      ADC_JDR2_JDATA_Msk                 /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                  (0U)                               
-#define ADC_JDR3_JDATA_Msk                  (0xFFFFU << ADC_JDR3_JDATA_Pos)    /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                      ADC_JDR3_JDATA_Msk                 /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                  (0U)                               
-#define ADC_JDR4_JDATA_Msk                  (0xFFFFU << ADC_JDR4_JDATA_Pos)    /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                      ADC_JDR4_JDATA_Msk                 /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                     (0U)                               
-#define ADC_DR_DATA_Msk                     (0xFFFFU << ADC_DR_DATA_Pos)       /*!< 0x0000FFFF */
-#define ADC_DR_DATA                         ADC_DR_DATA_Msk                    /*!< ADC group regular conversion data */
-#define ADC_DR_ADC2DATA_Pos                 (16U)                              
-#define ADC_DR_ADC2DATA_Msk                 (0xFFFFU << ADC_DR_ADC2DATA_Pos)   /*!< 0xFFFF0000 */
-#define ADC_DR_ADC2DATA                     ADC_DR_ADC2DATA_Msk                /*!< ADC group regular conversion data for ADC slave, in multimode */
-
-
-/*****************************************************************************/
-/*                                                                           */
-/*                               Timers (TIM)                                */
-/*                                                                           */
-/*****************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  *******************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1U << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1U << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1U << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1U << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1U << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3U << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1U << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2U << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1U << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3U << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1U << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2U << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  *******************/
-#define TIM_CR2_CCPC_Pos                    (0U)                               
-#define TIM_CR2_CCPC_Msk                    (0x1U << TIM_CR2_CCPC_Pos)         /*!< 0x00000001 */
-#define TIM_CR2_CCPC                        TIM_CR2_CCPC_Msk                   /*!<Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS_Pos                    (2U)                               
-#define TIM_CR2_CCUS_Msk                    (0x1U << TIM_CR2_CCUS_Pos)         /*!< 0x00000004 */
-#define TIM_CR2_CCUS                        TIM_CR2_CCUS_Msk                   /*!<Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1U << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7U << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1U << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2U << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4U << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1U << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-#define TIM_CR2_OIS1_Pos                    (8U)                               
-#define TIM_CR2_OIS1_Msk                    (0x1U << TIM_CR2_OIS1_Pos)         /*!< 0x00000100 */
-#define TIM_CR2_OIS1                        TIM_CR2_OIS1_Msk                   /*!<Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N_Pos                   (9U)                               
-#define TIM_CR2_OIS1N_Msk                   (0x1U << TIM_CR2_OIS1N_Pos)        /*!< 0x00000200 */
-#define TIM_CR2_OIS1N                       TIM_CR2_OIS1N_Msk                  /*!<Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2_Pos                    (10U)                              
-#define TIM_CR2_OIS2_Msk                    (0x1U << TIM_CR2_OIS2_Pos)         /*!< 0x00000400 */
-#define TIM_CR2_OIS2                        TIM_CR2_OIS2_Msk                   /*!<Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N_Pos                   (11U)                              
-#define TIM_CR2_OIS2N_Msk                   (0x1U << TIM_CR2_OIS2N_Pos)        /*!< 0x00000800 */
-#define TIM_CR2_OIS2N                       TIM_CR2_OIS2N_Msk                  /*!<Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3_Pos                    (12U)                              
-#define TIM_CR2_OIS3_Msk                    (0x1U << TIM_CR2_OIS3_Pos)         /*!< 0x00001000 */
-#define TIM_CR2_OIS3                        TIM_CR2_OIS3_Msk                   /*!<Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N_Pos                   (13U)                              
-#define TIM_CR2_OIS3N_Msk                   (0x1U << TIM_CR2_OIS3N_Pos)        /*!< 0x00002000 */
-#define TIM_CR2_OIS3N                       TIM_CR2_OIS3N_Msk                  /*!<Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4_Pos                    (14U)                              
-#define TIM_CR2_OIS4_Msk                    (0x1U << TIM_CR2_OIS4_Pos)         /*!< 0x00004000 */
-#define TIM_CR2_OIS4                        TIM_CR2_OIS4_Msk                   /*!<Output Idle state 4 (OC4 output) */
-
-/*******************  Bit definition for TIM_SMCR register  ******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7U << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1U << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2U << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4U << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1U << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7U << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1U << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2U << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4U << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1U << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFU << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1U << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2U << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4U << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8U << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3U << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1U << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2U << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1U << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1U << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  ******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1U << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1U << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1U << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1U << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1U << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_COMIE_Pos                  (5U)                               
-#define TIM_DIER_COMIE_Msk                  (0x1U << TIM_DIER_COMIE_Pos)       /*!< 0x00000020 */
-#define TIM_DIER_COMIE                      TIM_DIER_COMIE_Msk                 /*!<COM interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1U << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_BIE_Pos                    (7U)                               
-#define TIM_DIER_BIE_Msk                    (0x1U << TIM_DIER_BIE_Pos)         /*!< 0x00000080 */
-#define TIM_DIER_BIE                        TIM_DIER_BIE_Msk                   /*!<Break interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1U << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1U << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1U << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1U << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1U << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE_Pos                  (13U)                              
-#define TIM_DIER_COMDE_Msk                  (0x1U << TIM_DIER_COMDE_Pos)       /*!< 0x00002000 */
-#define TIM_DIER_COMDE                      TIM_DIER_COMDE_Msk                 /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1U << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  *******************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1U << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1U << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1U << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1U << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1U << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF_Pos                    (5U)                               
-#define TIM_SR_COMIF_Msk                    (0x1U << TIM_SR_COMIF_Pos)         /*!< 0x00000020 */
-#define TIM_SR_COMIF                        TIM_SR_COMIF_Msk                   /*!<COM interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1U << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_BIF_Pos                      (7U)                               
-#define TIM_SR_BIF_Msk                      (0x1U << TIM_SR_BIF_Pos)           /*!< 0x00000080 */
-#define TIM_SR_BIF                          TIM_SR_BIF_Msk                     /*!<Break interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1U << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1U << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1U << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1U << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  *******************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1U << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1U << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1U << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1U << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1U << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_COMG_Pos                    (5U)                               
-#define TIM_EGR_COMG_Msk                    (0x1U << TIM_EGR_COMG_Pos)         /*!< 0x00000020 */
-#define TIM_EGR_COMG                        TIM_EGR_COMG_Msk                   /*!<Capture/Compare Control Update Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1U << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-#define TIM_EGR_BG_Pos                      (7U)                               
-#define TIM_EGR_BG_Msk                      (0x1U << TIM_EGR_BG_Pos)           /*!< 0x00000080 */
-#define TIM_EGR_BG                          TIM_EGR_BG_Msk                     /*!<Break Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  ******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3U << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1U << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2U << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1U << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1U << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7U << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1U << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2U << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4U << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1U << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3U << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1U << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2U << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1U << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1U << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7U << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1U << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2U << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4U << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1U << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*---------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3U << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1U << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2U << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFU << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1U << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2U << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4U << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8U << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3U << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1U << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2U << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFU << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1U << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2U << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4U << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8U << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  ******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3U << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1U << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2U << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1U << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1U << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7U << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1U << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2U << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4U << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1U << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3U << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1U << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2U << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1U << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1U << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7U << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1U << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2U << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4U << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1U << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*---------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3U << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1U << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2U << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFU << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1U << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2U << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4U << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8U << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3U << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1U << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2U << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFU << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1U << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2U << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4U << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8U << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  ******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1U << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1U << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE_Pos                  (2U)                               
-#define TIM_CCER_CC1NE_Msk                  (0x1U << TIM_CCER_CC1NE_Pos)       /*!< 0x00000004 */
-#define TIM_CCER_CC1NE                      TIM_CCER_CC1NE_Msk                 /*!<Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1U << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1U << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1U << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE_Pos                  (6U)                               
-#define TIM_CCER_CC2NE_Msk                  (0x1U << TIM_CCER_CC2NE_Pos)       /*!< 0x00000040 */
-#define TIM_CCER_CC2NE                      TIM_CCER_CC2NE_Msk                 /*!<Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1U << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1U << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1U << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE_Pos                  (10U)                              
-#define TIM_CCER_CC3NE_Msk                  (0x1U << TIM_CCER_CC3NE_Pos)       /*!< 0x00000400 */
-#define TIM_CCER_CC3NE                      TIM_CCER_CC3NE_Msk                 /*!<Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1U << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1U << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1U << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1U << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  *******************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFU << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  *******************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFU << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  *******************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFU << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  *******************/
-#define TIM_RCR_REP_Pos                     (0U)                               
-#define TIM_RCR_REP_Msk                     (0xFFU << TIM_RCR_REP_Pos)         /*!< 0x000000FF */
-#define TIM_RCR_REP                         TIM_RCR_REP_Msk                    /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  ******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFU << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  ******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFU << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  ******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFU << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  ******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFU << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_BDTR register  ******************/
-#define TIM_BDTR_DTG_Pos                    (0U)                               
-#define TIM_BDTR_DTG_Msk                    (0xFFU << TIM_BDTR_DTG_Pos)        /*!< 0x000000FF */
-#define TIM_BDTR_DTG                        TIM_BDTR_DTG_Msk                   /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0                      (0x01U << TIM_BDTR_DTG_Pos)        /*!< 0x00000001 */
-#define TIM_BDTR_DTG_1                      (0x02U << TIM_BDTR_DTG_Pos)        /*!< 0x00000002 */
-#define TIM_BDTR_DTG_2                      (0x04U << TIM_BDTR_DTG_Pos)        /*!< 0x00000004 */
-#define TIM_BDTR_DTG_3                      (0x08U << TIM_BDTR_DTG_Pos)        /*!< 0x00000008 */
-#define TIM_BDTR_DTG_4                      (0x10U << TIM_BDTR_DTG_Pos)        /*!< 0x00000010 */
-#define TIM_BDTR_DTG_5                      (0x20U << TIM_BDTR_DTG_Pos)        /*!< 0x00000020 */
-#define TIM_BDTR_DTG_6                      (0x40U << TIM_BDTR_DTG_Pos)        /*!< 0x00000040 */
-#define TIM_BDTR_DTG_7                      (0x80U << TIM_BDTR_DTG_Pos)        /*!< 0x00000080 */
-
-#define TIM_BDTR_LOCK_Pos                   (8U)                               
-#define TIM_BDTR_LOCK_Msk                   (0x3U << TIM_BDTR_LOCK_Pos)        /*!< 0x00000300 */
-#define TIM_BDTR_LOCK                       TIM_BDTR_LOCK_Msk                  /*!<LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0                     (0x1U << TIM_BDTR_LOCK_Pos)        /*!< 0x00000100 */
-#define TIM_BDTR_LOCK_1                     (0x2U << TIM_BDTR_LOCK_Pos)        /*!< 0x00000200 */
-
-#define TIM_BDTR_OSSI_Pos                   (10U)                              
-#define TIM_BDTR_OSSI_Msk                   (0x1U << TIM_BDTR_OSSI_Pos)        /*!< 0x00000400 */
-#define TIM_BDTR_OSSI                       TIM_BDTR_OSSI_Msk                  /*!<Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR_Pos                   (11U)                              
-#define TIM_BDTR_OSSR_Msk                   (0x1U << TIM_BDTR_OSSR_Pos)        /*!< 0x00000800 */
-#define TIM_BDTR_OSSR                       TIM_BDTR_OSSR_Msk                  /*!<Off-State Selection for Run mode */
-#define TIM_BDTR_BKE_Pos                    (12U)                              
-#define TIM_BDTR_BKE_Msk                    (0x1U << TIM_BDTR_BKE_Pos)         /*!< 0x00001000 */
-#define TIM_BDTR_BKE                        TIM_BDTR_BKE_Msk                   /*!<Break enable */
-#define TIM_BDTR_BKP_Pos                    (13U)                              
-#define TIM_BDTR_BKP_Msk                    (0x1U << TIM_BDTR_BKP_Pos)         /*!< 0x00002000 */
-#define TIM_BDTR_BKP                        TIM_BDTR_BKP_Msk                   /*!<Break Polarity */
-#define TIM_BDTR_AOE_Pos                    (14U)                              
-#define TIM_BDTR_AOE_Msk                    (0x1U << TIM_BDTR_AOE_Pos)         /*!< 0x00004000 */
-#define TIM_BDTR_AOE                        TIM_BDTR_AOE_Msk                   /*!<Automatic Output enable */
-#define TIM_BDTR_MOE_Pos                    (15U)                              
-#define TIM_BDTR_MOE_Msk                    (0x1U << TIM_BDTR_MOE_Pos)         /*!< 0x00008000 */
-#define TIM_BDTR_MOE                        TIM_BDTR_MOE_Msk                   /*!<Main Output enable */
-
-/*******************  Bit definition for TIM_DCR register  *******************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FU << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01U << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02U << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04U << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08U << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10U << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FU << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01U << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02U << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04U << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08U << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10U << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  ******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFU << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  ********************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Real-Time Clock                                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for RTC_CRH register  ********************/
-#define RTC_CRH_SECIE_Pos                   (0U)                               
-#define RTC_CRH_SECIE_Msk                   (0x1U << RTC_CRH_SECIE_Pos)        /*!< 0x00000001 */
-#define RTC_CRH_SECIE                       RTC_CRH_SECIE_Msk                  /*!< Second Interrupt Enable */
-#define RTC_CRH_ALRIE_Pos                   (1U)                               
-#define RTC_CRH_ALRIE_Msk                   (0x1U << RTC_CRH_ALRIE_Pos)        /*!< 0x00000002 */
-#define RTC_CRH_ALRIE                       RTC_CRH_ALRIE_Msk                  /*!< Alarm Interrupt Enable */
-#define RTC_CRH_OWIE_Pos                    (2U)                               
-#define RTC_CRH_OWIE_Msk                    (0x1U << RTC_CRH_OWIE_Pos)         /*!< 0x00000004 */
-#define RTC_CRH_OWIE                        RTC_CRH_OWIE_Msk                   /*!< OverfloW Interrupt Enable */
-
-/*******************  Bit definition for RTC_CRL register  ********************/
-#define RTC_CRL_SECF_Pos                    (0U)                               
-#define RTC_CRL_SECF_Msk                    (0x1U << RTC_CRL_SECF_Pos)         /*!< 0x00000001 */
-#define RTC_CRL_SECF                        RTC_CRL_SECF_Msk                   /*!< Second Flag */
-#define RTC_CRL_ALRF_Pos                    (1U)                               
-#define RTC_CRL_ALRF_Msk                    (0x1U << RTC_CRL_ALRF_Pos)         /*!< 0x00000002 */
-#define RTC_CRL_ALRF                        RTC_CRL_ALRF_Msk                   /*!< Alarm Flag */
-#define RTC_CRL_OWF_Pos                     (2U)                               
-#define RTC_CRL_OWF_Msk                     (0x1U << RTC_CRL_OWF_Pos)          /*!< 0x00000004 */
-#define RTC_CRL_OWF                         RTC_CRL_OWF_Msk                    /*!< OverfloW Flag */
-#define RTC_CRL_RSF_Pos                     (3U)                               
-#define RTC_CRL_RSF_Msk                     (0x1U << RTC_CRL_RSF_Pos)          /*!< 0x00000008 */
-#define RTC_CRL_RSF                         RTC_CRL_RSF_Msk                    /*!< Registers Synchronized Flag */
-#define RTC_CRL_CNF_Pos                     (4U)                               
-#define RTC_CRL_CNF_Msk                     (0x1U << RTC_CRL_CNF_Pos)          /*!< 0x00000010 */
-#define RTC_CRL_CNF                         RTC_CRL_CNF_Msk                    /*!< Configuration Flag */
-#define RTC_CRL_RTOFF_Pos                   (5U)                               
-#define RTC_CRL_RTOFF_Msk                   (0x1U << RTC_CRL_RTOFF_Pos)        /*!< 0x00000020 */
-#define RTC_CRL_RTOFF                       RTC_CRL_RTOFF_Msk                  /*!< RTC operation OFF */
-
-/*******************  Bit definition for RTC_PRLH register  *******************/
-#define RTC_PRLH_PRL_Pos                    (0U)                               
-#define RTC_PRLH_PRL_Msk                    (0xFU << RTC_PRLH_PRL_Pos)         /*!< 0x0000000F */
-#define RTC_PRLH_PRL                        RTC_PRLH_PRL_Msk                   /*!< RTC Prescaler Reload Value High */
-
-/*******************  Bit definition for RTC_PRLL register  *******************/
-#define RTC_PRLL_PRL_Pos                    (0U)                               
-#define RTC_PRLL_PRL_Msk                    (0xFFFFU << RTC_PRLL_PRL_Pos)      /*!< 0x0000FFFF */
-#define RTC_PRLL_PRL                        RTC_PRLL_PRL_Msk                   /*!< RTC Prescaler Reload Value Low */
-
-/*******************  Bit definition for RTC_DIVH register  *******************/
-#define RTC_DIVH_RTC_DIV_Pos                (0U)                               
-#define RTC_DIVH_RTC_DIV_Msk                (0xFU << RTC_DIVH_RTC_DIV_Pos)     /*!< 0x0000000F */
-#define RTC_DIVH_RTC_DIV                    RTC_DIVH_RTC_DIV_Msk               /*!< RTC Clock Divider High */
-
-/*******************  Bit definition for RTC_DIVL register  *******************/
-#define RTC_DIVL_RTC_DIV_Pos                (0U)                               
-#define RTC_DIVL_RTC_DIV_Msk                (0xFFFFU << RTC_DIVL_RTC_DIV_Pos)  /*!< 0x0000FFFF */
-#define RTC_DIVL_RTC_DIV                    RTC_DIVL_RTC_DIV_Msk               /*!< RTC Clock Divider Low */
-
-/*******************  Bit definition for RTC_CNTH register  *******************/
-#define RTC_CNTH_RTC_CNT_Pos                (0U)                               
-#define RTC_CNTH_RTC_CNT_Msk                (0xFFFFU << RTC_CNTH_RTC_CNT_Pos)  /*!< 0x0000FFFF */
-#define RTC_CNTH_RTC_CNT                    RTC_CNTH_RTC_CNT_Msk               /*!< RTC Counter High */
-
-/*******************  Bit definition for RTC_CNTL register  *******************/
-#define RTC_CNTL_RTC_CNT_Pos                (0U)                               
-#define RTC_CNTL_RTC_CNT_Msk                (0xFFFFU << RTC_CNTL_RTC_CNT_Pos)  /*!< 0x0000FFFF */
-#define RTC_CNTL_RTC_CNT                    RTC_CNTL_RTC_CNT_Msk               /*!< RTC Counter Low */
-
-/*******************  Bit definition for RTC_ALRH register  *******************/
-#define RTC_ALRH_RTC_ALR_Pos                (0U)                               
-#define RTC_ALRH_RTC_ALR_Msk                (0xFFFFU << RTC_ALRH_RTC_ALR_Pos)  /*!< 0x0000FFFF */
-#define RTC_ALRH_RTC_ALR                    RTC_ALRH_RTC_ALR_Msk               /*!< RTC Alarm High */
-
-/*******************  Bit definition for RTC_ALRL register  *******************/
-#define RTC_ALRL_RTC_ALR_Pos                (0U)                               
-#define RTC_ALRL_RTC_ALR_Msk                (0xFFFFU << RTC_ALRL_RTC_ALR_Pos)  /*!< 0x0000FFFF */
-#define RTC_ALRL_RTC_ALR                    RTC_ALRL_RTC_ALR_Msk               /*!< RTC Alarm Low */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFU << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7U << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1U << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2U << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4U << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFU << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1U << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1U << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FU << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01U << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02U << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04U << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08U << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10U << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20U << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40U << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1U << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FU << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01U << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02U << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04U << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08U << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10U << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20U << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40U << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3U << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1U << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2U << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1U << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1U << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define SDIO_POWER_PWRCTRL_Pos              (0U)                               
-#define SDIO_POWER_PWRCTRL_Msk              (0x3U << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x00000003 */
-#define SDIO_POWER_PWRCTRL                  SDIO_POWER_PWRCTRL_Msk             /*!< PWRCTRL[1:0] bits (Power supply control bits) */
-#define SDIO_POWER_PWRCTRL_0                (0x1U << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x01 */
-#define SDIO_POWER_PWRCTRL_1                (0x2U << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x02 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define SDIO_CLKCR_CLKDIV_Pos               (0U)                               
-#define SDIO_CLKCR_CLKDIV_Msk               (0xFFU << SDIO_CLKCR_CLKDIV_Pos)   /*!< 0x000000FF */
-#define SDIO_CLKCR_CLKDIV                   SDIO_CLKCR_CLKDIV_Msk              /*!< Clock divide factor */
-#define SDIO_CLKCR_CLKEN_Pos                (8U)                               
-#define SDIO_CLKCR_CLKEN_Msk                (0x1U << SDIO_CLKCR_CLKEN_Pos)     /*!< 0x00000100 */
-#define SDIO_CLKCR_CLKEN                    SDIO_CLKCR_CLKEN_Msk               /*!< Clock enable bit */
-#define SDIO_CLKCR_PWRSAV_Pos               (9U)                               
-#define SDIO_CLKCR_PWRSAV_Msk               (0x1U << SDIO_CLKCR_PWRSAV_Pos)    /*!< 0x00000200 */
-#define SDIO_CLKCR_PWRSAV                   SDIO_CLKCR_PWRSAV_Msk              /*!< Power saving configuration bit */
-#define SDIO_CLKCR_BYPASS_Pos               (10U)                              
-#define SDIO_CLKCR_BYPASS_Msk               (0x1U << SDIO_CLKCR_BYPASS_Pos)    /*!< 0x00000400 */
-#define SDIO_CLKCR_BYPASS                   SDIO_CLKCR_BYPASS_Msk              /*!< Clock divider bypass enable bit */
-
-#define SDIO_CLKCR_WIDBUS_Pos               (11U)                              
-#define SDIO_CLKCR_WIDBUS_Msk               (0x3U << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x00001800 */
-#define SDIO_CLKCR_WIDBUS                   SDIO_CLKCR_WIDBUS_Msk              /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define SDIO_CLKCR_WIDBUS_0                 (0x1U << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x0800 */
-#define SDIO_CLKCR_WIDBUS_1                 (0x2U << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x1000 */
-
-#define SDIO_CLKCR_NEGEDGE_Pos              (13U)                              
-#define SDIO_CLKCR_NEGEDGE_Msk              (0x1U << SDIO_CLKCR_NEGEDGE_Pos)   /*!< 0x00002000 */
-#define SDIO_CLKCR_NEGEDGE                  SDIO_CLKCR_NEGEDGE_Msk             /*!< SDIO_CK dephasing selection bit */
-#define SDIO_CLKCR_HWFC_EN_Pos              (14U)                              
-#define SDIO_CLKCR_HWFC_EN_Msk              (0x1U << SDIO_CLKCR_HWFC_EN_Pos)   /*!< 0x00004000 */
-#define SDIO_CLKCR_HWFC_EN                  SDIO_CLKCR_HWFC_EN_Msk             /*!< HW Flow Control enable */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define SDIO_ARG_CMDARG_Pos                 (0U)                               
-#define SDIO_ARG_CMDARG_Msk                 (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_ARG_CMDARG                     SDIO_ARG_CMDARG_Msk                /*!< Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define SDIO_CMD_CMDINDEX_Pos               (0U)                               
-#define SDIO_CMD_CMDINDEX_Msk               (0x3FU << SDIO_CMD_CMDINDEX_Pos)   /*!< 0x0000003F */
-#define SDIO_CMD_CMDINDEX                   SDIO_CMD_CMDINDEX_Msk              /*!< Command Index */
-
-#define SDIO_CMD_WAITRESP_Pos               (6U)                               
-#define SDIO_CMD_WAITRESP_Msk               (0x3U << SDIO_CMD_WAITRESP_Pos)    /*!< 0x000000C0 */
-#define SDIO_CMD_WAITRESP                   SDIO_CMD_WAITRESP_Msk              /*!< WAITRESP[1:0] bits (Wait for response bits) */
-#define SDIO_CMD_WAITRESP_0                 (0x1U << SDIO_CMD_WAITRESP_Pos)    /*!< 0x0040 */
-#define SDIO_CMD_WAITRESP_1                 (0x2U << SDIO_CMD_WAITRESP_Pos)    /*!< 0x0080 */
-
-#define SDIO_CMD_WAITINT_Pos                (8U)                               
-#define SDIO_CMD_WAITINT_Msk                (0x1U << SDIO_CMD_WAITINT_Pos)     /*!< 0x00000100 */
-#define SDIO_CMD_WAITINT                    SDIO_CMD_WAITINT_Msk               /*!< CPSM Waits for Interrupt Request */
-#define SDIO_CMD_WAITPEND_Pos               (9U)                               
-#define SDIO_CMD_WAITPEND_Msk               (0x1U << SDIO_CMD_WAITPEND_Pos)    /*!< 0x00000200 */
-#define SDIO_CMD_WAITPEND                   SDIO_CMD_WAITPEND_Msk              /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define SDIO_CMD_CPSMEN_Pos                 (10U)                              
-#define SDIO_CMD_CPSMEN_Msk                 (0x1U << SDIO_CMD_CPSMEN_Pos)      /*!< 0x00000400 */
-#define SDIO_CMD_CPSMEN                     SDIO_CMD_CPSMEN_Msk                /*!< Command path state machine (CPSM) Enable bit */
-#define SDIO_CMD_SDIOSUSPEND_Pos            (11U)                              
-#define SDIO_CMD_SDIOSUSPEND_Msk            (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
-#define SDIO_CMD_SDIOSUSPEND                SDIO_CMD_SDIOSUSPEND_Msk           /*!< SD I/O suspend command */
-#define SDIO_CMD_ENCMDCOMPL_Pos             (12U)                              
-#define SDIO_CMD_ENCMDCOMPL_Msk             (0x1U << SDIO_CMD_ENCMDCOMPL_Pos)  /*!< 0x00001000 */
-#define SDIO_CMD_ENCMDCOMPL                 SDIO_CMD_ENCMDCOMPL_Msk            /*!< Enable CMD completion */
-#define SDIO_CMD_NIEN_Pos                   (13U)                              
-#define SDIO_CMD_NIEN_Msk                   (0x1U << SDIO_CMD_NIEN_Pos)        /*!< 0x00002000 */
-#define SDIO_CMD_NIEN                       SDIO_CMD_NIEN_Msk                  /*!< Not Interrupt Enable */
-#define SDIO_CMD_CEATACMD_Pos               (14U)                              
-#define SDIO_CMD_CEATACMD_Msk               (0x1U << SDIO_CMD_CEATACMD_Pos)    /*!< 0x00004000 */
-#define SDIO_CMD_CEATACMD                   SDIO_CMD_CEATACMD_Msk              /*!< CE-ATA command */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define SDIO_RESPCMD_RESPCMD_Pos            (0U)                               
-#define SDIO_RESPCMD_RESPCMD_Msk            (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
-#define SDIO_RESPCMD_RESPCMD                SDIO_RESPCMD_RESPCMD_Msk           /*!< Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define SDIO_RESP0_CARDSTATUS0_Pos          (0U)                               
-#define SDIO_RESP0_CARDSTATUS0_Msk          (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP0_CARDSTATUS0              SDIO_RESP0_CARDSTATUS0_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define SDIO_RESP1_CARDSTATUS1_Pos          (0U)                               
-#define SDIO_RESP1_CARDSTATUS1_Msk          (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP1_CARDSTATUS1              SDIO_RESP1_CARDSTATUS1_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define SDIO_RESP2_CARDSTATUS2_Pos          (0U)                               
-#define SDIO_RESP2_CARDSTATUS2_Msk          (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP2_CARDSTATUS2              SDIO_RESP2_CARDSTATUS2_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define SDIO_RESP3_CARDSTATUS3_Pos          (0U)                               
-#define SDIO_RESP3_CARDSTATUS3_Msk          (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP3_CARDSTATUS3              SDIO_RESP3_CARDSTATUS3_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define SDIO_RESP4_CARDSTATUS4_Pos          (0U)                               
-#define SDIO_RESP4_CARDSTATUS4_Msk          (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP4_CARDSTATUS4              SDIO_RESP4_CARDSTATUS4_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define SDIO_DTIMER_DATATIME_Pos            (0U)                               
-#define SDIO_DTIMER_DATATIME_Msk            (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_DTIMER_DATATIME                SDIO_DTIMER_DATATIME_Msk           /*!< Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define SDIO_DLEN_DATALENGTH_Pos            (0U)                               
-#define SDIO_DLEN_DATALENGTH_Msk            (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
-#define SDIO_DLEN_DATALENGTH                SDIO_DLEN_DATALENGTH_Msk           /*!< Data length value */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define SDIO_DCTRL_DTEN_Pos                 (0U)                               
-#define SDIO_DCTRL_DTEN_Msk                 (0x1U << SDIO_DCTRL_DTEN_Pos)      /*!< 0x00000001 */
-#define SDIO_DCTRL_DTEN                     SDIO_DCTRL_DTEN_Msk                /*!< Data transfer enabled bit */
-#define SDIO_DCTRL_DTDIR_Pos                (1U)                               
-#define SDIO_DCTRL_DTDIR_Msk                (0x1U << SDIO_DCTRL_DTDIR_Pos)     /*!< 0x00000002 */
-#define SDIO_DCTRL_DTDIR                    SDIO_DCTRL_DTDIR_Msk               /*!< Data transfer direction selection */
-#define SDIO_DCTRL_DTMODE_Pos               (2U)                               
-#define SDIO_DCTRL_DTMODE_Msk               (0x1U << SDIO_DCTRL_DTMODE_Pos)    /*!< 0x00000004 */
-#define SDIO_DCTRL_DTMODE                   SDIO_DCTRL_DTMODE_Msk              /*!< Data transfer mode selection */
-#define SDIO_DCTRL_DMAEN_Pos                (3U)                               
-#define SDIO_DCTRL_DMAEN_Msk                (0x1U << SDIO_DCTRL_DMAEN_Pos)     /*!< 0x00000008 */
-#define SDIO_DCTRL_DMAEN                    SDIO_DCTRL_DMAEN_Msk               /*!< DMA enabled bit */
-
-#define SDIO_DCTRL_DBLOCKSIZE_Pos           (4U)                               
-#define SDIO_DCTRL_DBLOCKSIZE_Msk           (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
-#define SDIO_DCTRL_DBLOCKSIZE               SDIO_DCTRL_DBLOCKSIZE_Msk          /*!< DBLOCKSIZE[3:0] bits (Data block size) */
-#define SDIO_DCTRL_DBLOCKSIZE_0             (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
-#define SDIO_DCTRL_DBLOCKSIZE_1             (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
-#define SDIO_DCTRL_DBLOCKSIZE_2             (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
-#define SDIO_DCTRL_DBLOCKSIZE_3             (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
-
-#define SDIO_DCTRL_RWSTART_Pos              (8U)                               
-#define SDIO_DCTRL_RWSTART_Msk              (0x1U << SDIO_DCTRL_RWSTART_Pos)   /*!< 0x00000100 */
-#define SDIO_DCTRL_RWSTART                  SDIO_DCTRL_RWSTART_Msk             /*!< Read wait start */
-#define SDIO_DCTRL_RWSTOP_Pos               (9U)                               
-#define SDIO_DCTRL_RWSTOP_Msk               (0x1U << SDIO_DCTRL_RWSTOP_Pos)    /*!< 0x00000200 */
-#define SDIO_DCTRL_RWSTOP                   SDIO_DCTRL_RWSTOP_Msk              /*!< Read wait stop */
-#define SDIO_DCTRL_RWMOD_Pos                (10U)                              
-#define SDIO_DCTRL_RWMOD_Msk                (0x1U << SDIO_DCTRL_RWMOD_Pos)     /*!< 0x00000400 */
-#define SDIO_DCTRL_RWMOD                    SDIO_DCTRL_RWMOD_Msk               /*!< Read wait mode */
-#define SDIO_DCTRL_SDIOEN_Pos               (11U)                              
-#define SDIO_DCTRL_SDIOEN_Msk               (0x1U << SDIO_DCTRL_SDIOEN_Pos)    /*!< 0x00000800 */
-#define SDIO_DCTRL_SDIOEN                   SDIO_DCTRL_SDIOEN_Msk              /*!< SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define SDIO_DCOUNT_DATACOUNT_Pos           (0U)                               
-#define SDIO_DCOUNT_DATACOUNT_Msk           (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
-#define SDIO_DCOUNT_DATACOUNT               SDIO_DCOUNT_DATACOUNT_Msk          /*!< Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define SDIO_STA_CCRCFAIL_Pos               (0U)                               
-#define SDIO_STA_CCRCFAIL_Msk               (0x1U << SDIO_STA_CCRCFAIL_Pos)    /*!< 0x00000001 */
-#define SDIO_STA_CCRCFAIL                   SDIO_STA_CCRCFAIL_Msk              /*!< Command response received (CRC check failed) */
-#define SDIO_STA_DCRCFAIL_Pos               (1U)                               
-#define SDIO_STA_DCRCFAIL_Msk               (0x1U << SDIO_STA_DCRCFAIL_Pos)    /*!< 0x00000002 */
-#define SDIO_STA_DCRCFAIL                   SDIO_STA_DCRCFAIL_Msk              /*!< Data block sent/received (CRC check failed) */
-#define SDIO_STA_CTIMEOUT_Pos               (2U)                               
-#define SDIO_STA_CTIMEOUT_Msk               (0x1U << SDIO_STA_CTIMEOUT_Pos)    /*!< 0x00000004 */
-#define SDIO_STA_CTIMEOUT                   SDIO_STA_CTIMEOUT_Msk              /*!< Command response timeout */
-#define SDIO_STA_DTIMEOUT_Pos               (3U)                               
-#define SDIO_STA_DTIMEOUT_Msk               (0x1U << SDIO_STA_DTIMEOUT_Pos)    /*!< 0x00000008 */
-#define SDIO_STA_DTIMEOUT                   SDIO_STA_DTIMEOUT_Msk              /*!< Data timeout */
-#define SDIO_STA_TXUNDERR_Pos               (4U)                               
-#define SDIO_STA_TXUNDERR_Msk               (0x1U << SDIO_STA_TXUNDERR_Pos)    /*!< 0x00000010 */
-#define SDIO_STA_TXUNDERR                   SDIO_STA_TXUNDERR_Msk              /*!< Transmit FIFO underrun error */
-#define SDIO_STA_RXOVERR_Pos                (5U)                               
-#define SDIO_STA_RXOVERR_Msk                (0x1U << SDIO_STA_RXOVERR_Pos)     /*!< 0x00000020 */
-#define SDIO_STA_RXOVERR                    SDIO_STA_RXOVERR_Msk               /*!< Received FIFO overrun error */
-#define SDIO_STA_CMDREND_Pos                (6U)                               
-#define SDIO_STA_CMDREND_Msk                (0x1U << SDIO_STA_CMDREND_Pos)     /*!< 0x00000040 */
-#define SDIO_STA_CMDREND                    SDIO_STA_CMDREND_Msk               /*!< Command response received (CRC check passed) */
-#define SDIO_STA_CMDSENT_Pos                (7U)                               
-#define SDIO_STA_CMDSENT_Msk                (0x1U << SDIO_STA_CMDSENT_Pos)     /*!< 0x00000080 */
-#define SDIO_STA_CMDSENT                    SDIO_STA_CMDSENT_Msk               /*!< Command sent (no response required) */
-#define SDIO_STA_DATAEND_Pos                (8U)                               
-#define SDIO_STA_DATAEND_Msk                (0x1U << SDIO_STA_DATAEND_Pos)     /*!< 0x00000100 */
-#define SDIO_STA_DATAEND                    SDIO_STA_DATAEND_Msk               /*!< Data end (data counter, SDIDCOUNT, is zero) */
-#define SDIO_STA_STBITERR_Pos               (9U)                               
-#define SDIO_STA_STBITERR_Msk               (0x1U << SDIO_STA_STBITERR_Pos)    /*!< 0x00000200 */
-#define SDIO_STA_STBITERR                   SDIO_STA_STBITERR_Msk              /*!< Start bit not detected on all data signals in wide bus mode */
-#define SDIO_STA_DBCKEND_Pos                (10U)                              
-#define SDIO_STA_DBCKEND_Msk                (0x1U << SDIO_STA_DBCKEND_Pos)     /*!< 0x00000400 */
-#define SDIO_STA_DBCKEND                    SDIO_STA_DBCKEND_Msk               /*!< Data block sent/received (CRC check passed) */
-#define SDIO_STA_CMDACT_Pos                 (11U)                              
-#define SDIO_STA_CMDACT_Msk                 (0x1U << SDIO_STA_CMDACT_Pos)      /*!< 0x00000800 */
-#define SDIO_STA_CMDACT                     SDIO_STA_CMDACT_Msk                /*!< Command transfer in progress */
-#define SDIO_STA_TXACT_Pos                  (12U)                              
-#define SDIO_STA_TXACT_Msk                  (0x1U << SDIO_STA_TXACT_Pos)       /*!< 0x00001000 */
-#define SDIO_STA_TXACT                      SDIO_STA_TXACT_Msk                 /*!< Data transmit in progress */
-#define SDIO_STA_RXACT_Pos                  (13U)                              
-#define SDIO_STA_RXACT_Msk                  (0x1U << SDIO_STA_RXACT_Pos)       /*!< 0x00002000 */
-#define SDIO_STA_RXACT                      SDIO_STA_RXACT_Msk                 /*!< Data receive in progress */
-#define SDIO_STA_TXFIFOHE_Pos               (14U)                              
-#define SDIO_STA_TXFIFOHE_Msk               (0x1U << SDIO_STA_TXFIFOHE_Pos)    /*!< 0x00004000 */
-#define SDIO_STA_TXFIFOHE                   SDIO_STA_TXFIFOHE_Msk              /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define SDIO_STA_RXFIFOHF_Pos               (15U)                              
-#define SDIO_STA_RXFIFOHF_Msk               (0x1U << SDIO_STA_RXFIFOHF_Pos)    /*!< 0x00008000 */
-#define SDIO_STA_RXFIFOHF                   SDIO_STA_RXFIFOHF_Msk              /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define SDIO_STA_TXFIFOF_Pos                (16U)                              
-#define SDIO_STA_TXFIFOF_Msk                (0x1U << SDIO_STA_TXFIFOF_Pos)     /*!< 0x00010000 */
-#define SDIO_STA_TXFIFOF                    SDIO_STA_TXFIFOF_Msk               /*!< Transmit FIFO full */
-#define SDIO_STA_RXFIFOF_Pos                (17U)                              
-#define SDIO_STA_RXFIFOF_Msk                (0x1U << SDIO_STA_RXFIFOF_Pos)     /*!< 0x00020000 */
-#define SDIO_STA_RXFIFOF                    SDIO_STA_RXFIFOF_Msk               /*!< Receive FIFO full */
-#define SDIO_STA_TXFIFOE_Pos                (18U)                              
-#define SDIO_STA_TXFIFOE_Msk                (0x1U << SDIO_STA_TXFIFOE_Pos)     /*!< 0x00040000 */
-#define SDIO_STA_TXFIFOE                    SDIO_STA_TXFIFOE_Msk               /*!< Transmit FIFO empty */
-#define SDIO_STA_RXFIFOE_Pos                (19U)                              
-#define SDIO_STA_RXFIFOE_Msk                (0x1U << SDIO_STA_RXFIFOE_Pos)     /*!< 0x00080000 */
-#define SDIO_STA_RXFIFOE                    SDIO_STA_RXFIFOE_Msk               /*!< Receive FIFO empty */
-#define SDIO_STA_TXDAVL_Pos                 (20U)                              
-#define SDIO_STA_TXDAVL_Msk                 (0x1U << SDIO_STA_TXDAVL_Pos)      /*!< 0x00100000 */
-#define SDIO_STA_TXDAVL                     SDIO_STA_TXDAVL_Msk                /*!< Data available in transmit FIFO */
-#define SDIO_STA_RXDAVL_Pos                 (21U)                              
-#define SDIO_STA_RXDAVL_Msk                 (0x1U << SDIO_STA_RXDAVL_Pos)      /*!< 0x00200000 */
-#define SDIO_STA_RXDAVL                     SDIO_STA_RXDAVL_Msk                /*!< Data available in receive FIFO */
-#define SDIO_STA_SDIOIT_Pos                 (22U)                              
-#define SDIO_STA_SDIOIT_Msk                 (0x1U << SDIO_STA_SDIOIT_Pos)      /*!< 0x00400000 */
-#define SDIO_STA_SDIOIT                     SDIO_STA_SDIOIT_Msk                /*!< SDIO interrupt received */
-#define SDIO_STA_CEATAEND_Pos               (23U)                              
-#define SDIO_STA_CEATAEND_Msk               (0x1U << SDIO_STA_CEATAEND_Pos)    /*!< 0x00800000 */
-#define SDIO_STA_CEATAEND                   SDIO_STA_CEATAEND_Msk              /*!< CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define SDIO_ICR_CCRCFAILC_Pos              (0U)                               
-#define SDIO_ICR_CCRCFAILC_Msk              (0x1U << SDIO_ICR_CCRCFAILC_Pos)   /*!< 0x00000001 */
-#define SDIO_ICR_CCRCFAILC                  SDIO_ICR_CCRCFAILC_Msk             /*!< CCRCFAIL flag clear bit */
-#define SDIO_ICR_DCRCFAILC_Pos              (1U)                               
-#define SDIO_ICR_DCRCFAILC_Msk              (0x1U << SDIO_ICR_DCRCFAILC_Pos)   /*!< 0x00000002 */
-#define SDIO_ICR_DCRCFAILC                  SDIO_ICR_DCRCFAILC_Msk             /*!< DCRCFAIL flag clear bit */
-#define SDIO_ICR_CTIMEOUTC_Pos              (2U)                               
-#define SDIO_ICR_CTIMEOUTC_Msk              (0x1U << SDIO_ICR_CTIMEOUTC_Pos)   /*!< 0x00000004 */
-#define SDIO_ICR_CTIMEOUTC                  SDIO_ICR_CTIMEOUTC_Msk             /*!< CTIMEOUT flag clear bit */
-#define SDIO_ICR_DTIMEOUTC_Pos              (3U)                               
-#define SDIO_ICR_DTIMEOUTC_Msk              (0x1U << SDIO_ICR_DTIMEOUTC_Pos)   /*!< 0x00000008 */
-#define SDIO_ICR_DTIMEOUTC                  SDIO_ICR_DTIMEOUTC_Msk             /*!< DTIMEOUT flag clear bit */
-#define SDIO_ICR_TXUNDERRC_Pos              (4U)                               
-#define SDIO_ICR_TXUNDERRC_Msk              (0x1U << SDIO_ICR_TXUNDERRC_Pos)   /*!< 0x00000010 */
-#define SDIO_ICR_TXUNDERRC                  SDIO_ICR_TXUNDERRC_Msk             /*!< TXUNDERR flag clear bit */
-#define SDIO_ICR_RXOVERRC_Pos               (5U)                               
-#define SDIO_ICR_RXOVERRC_Msk               (0x1U << SDIO_ICR_RXOVERRC_Pos)    /*!< 0x00000020 */
-#define SDIO_ICR_RXOVERRC                   SDIO_ICR_RXOVERRC_Msk              /*!< RXOVERR flag clear bit */
-#define SDIO_ICR_CMDRENDC_Pos               (6U)                               
-#define SDIO_ICR_CMDRENDC_Msk               (0x1U << SDIO_ICR_CMDRENDC_Pos)    /*!< 0x00000040 */
-#define SDIO_ICR_CMDRENDC                   SDIO_ICR_CMDRENDC_Msk              /*!< CMDREND flag clear bit */
-#define SDIO_ICR_CMDSENTC_Pos               (7U)                               
-#define SDIO_ICR_CMDSENTC_Msk               (0x1U << SDIO_ICR_CMDSENTC_Pos)    /*!< 0x00000080 */
-#define SDIO_ICR_CMDSENTC                   SDIO_ICR_CMDSENTC_Msk              /*!< CMDSENT flag clear bit */
-#define SDIO_ICR_DATAENDC_Pos               (8U)                               
-#define SDIO_ICR_DATAENDC_Msk               (0x1U << SDIO_ICR_DATAENDC_Pos)    /*!< 0x00000100 */
-#define SDIO_ICR_DATAENDC                   SDIO_ICR_DATAENDC_Msk              /*!< DATAEND flag clear bit */
-#define SDIO_ICR_STBITERRC_Pos              (9U)                               
-#define SDIO_ICR_STBITERRC_Msk              (0x1U << SDIO_ICR_STBITERRC_Pos)   /*!< 0x00000200 */
-#define SDIO_ICR_STBITERRC                  SDIO_ICR_STBITERRC_Msk             /*!< STBITERR flag clear bit */
-#define SDIO_ICR_DBCKENDC_Pos               (10U)                              
-#define SDIO_ICR_DBCKENDC_Msk               (0x1U << SDIO_ICR_DBCKENDC_Pos)    /*!< 0x00000400 */
-#define SDIO_ICR_DBCKENDC                   SDIO_ICR_DBCKENDC_Msk              /*!< DBCKEND flag clear bit */
-#define SDIO_ICR_SDIOITC_Pos                (22U)                              
-#define SDIO_ICR_SDIOITC_Msk                (0x1U << SDIO_ICR_SDIOITC_Pos)     /*!< 0x00400000 */
-#define SDIO_ICR_SDIOITC                    SDIO_ICR_SDIOITC_Msk               /*!< SDIOIT flag clear bit */
-#define SDIO_ICR_CEATAENDC_Pos              (23U)                              
-#define SDIO_ICR_CEATAENDC_Msk              (0x1U << SDIO_ICR_CEATAENDC_Pos)   /*!< 0x00800000 */
-#define SDIO_ICR_CEATAENDC                  SDIO_ICR_CEATAENDC_Msk             /*!< CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define SDIO_MASK_CCRCFAILIE_Pos            (0U)                               
-#define SDIO_MASK_CCRCFAILIE_Msk            (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
-#define SDIO_MASK_CCRCFAILIE                SDIO_MASK_CCRCFAILIE_Msk           /*!< Command CRC Fail Interrupt Enable */
-#define SDIO_MASK_DCRCFAILIE_Pos            (1U)                               
-#define SDIO_MASK_DCRCFAILIE_Msk            (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
-#define SDIO_MASK_DCRCFAILIE                SDIO_MASK_DCRCFAILIE_Msk           /*!< Data CRC Fail Interrupt Enable */
-#define SDIO_MASK_CTIMEOUTIE_Pos            (2U)                               
-#define SDIO_MASK_CTIMEOUTIE_Msk            (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
-#define SDIO_MASK_CTIMEOUTIE                SDIO_MASK_CTIMEOUTIE_Msk           /*!< Command TimeOut Interrupt Enable */
-#define SDIO_MASK_DTIMEOUTIE_Pos            (3U)                               
-#define SDIO_MASK_DTIMEOUTIE_Msk            (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
-#define SDIO_MASK_DTIMEOUTIE                SDIO_MASK_DTIMEOUTIE_Msk           /*!< Data TimeOut Interrupt Enable */
-#define SDIO_MASK_TXUNDERRIE_Pos            (4U)                               
-#define SDIO_MASK_TXUNDERRIE_Msk            (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
-#define SDIO_MASK_TXUNDERRIE                SDIO_MASK_TXUNDERRIE_Msk           /*!< Tx FIFO UnderRun Error Interrupt Enable */
-#define SDIO_MASK_RXOVERRIE_Pos             (5U)                               
-#define SDIO_MASK_RXOVERRIE_Msk             (0x1U << SDIO_MASK_RXOVERRIE_Pos)  /*!< 0x00000020 */
-#define SDIO_MASK_RXOVERRIE                 SDIO_MASK_RXOVERRIE_Msk            /*!< Rx FIFO OverRun Error Interrupt Enable */
-#define SDIO_MASK_CMDRENDIE_Pos             (6U)                               
-#define SDIO_MASK_CMDRENDIE_Msk             (0x1U << SDIO_MASK_CMDRENDIE_Pos)  /*!< 0x00000040 */
-#define SDIO_MASK_CMDRENDIE                 SDIO_MASK_CMDRENDIE_Msk            /*!< Command Response Received Interrupt Enable */
-#define SDIO_MASK_CMDSENTIE_Pos             (7U)                               
-#define SDIO_MASK_CMDSENTIE_Msk             (0x1U << SDIO_MASK_CMDSENTIE_Pos)  /*!< 0x00000080 */
-#define SDIO_MASK_CMDSENTIE                 SDIO_MASK_CMDSENTIE_Msk            /*!< Command Sent Interrupt Enable */
-#define SDIO_MASK_DATAENDIE_Pos             (8U)                               
-#define SDIO_MASK_DATAENDIE_Msk             (0x1U << SDIO_MASK_DATAENDIE_Pos)  /*!< 0x00000100 */
-#define SDIO_MASK_DATAENDIE                 SDIO_MASK_DATAENDIE_Msk            /*!< Data End Interrupt Enable */
-#define SDIO_MASK_STBITERRIE_Pos            (9U)                               
-#define SDIO_MASK_STBITERRIE_Msk            (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
-#define SDIO_MASK_STBITERRIE                SDIO_MASK_STBITERRIE_Msk           /*!< Start Bit Error Interrupt Enable */
-#define SDIO_MASK_DBCKENDIE_Pos             (10U)                              
-#define SDIO_MASK_DBCKENDIE_Msk             (0x1U << SDIO_MASK_DBCKENDIE_Pos)  /*!< 0x00000400 */
-#define SDIO_MASK_DBCKENDIE                 SDIO_MASK_DBCKENDIE_Msk            /*!< Data Block End Interrupt Enable */
-#define SDIO_MASK_CMDACTIE_Pos              (11U)                              
-#define SDIO_MASK_CMDACTIE_Msk              (0x1U << SDIO_MASK_CMDACTIE_Pos)   /*!< 0x00000800 */
-#define SDIO_MASK_CMDACTIE                  SDIO_MASK_CMDACTIE_Msk             /*!< Command Acting Interrupt Enable */
-#define SDIO_MASK_TXACTIE_Pos               (12U)                              
-#define SDIO_MASK_TXACTIE_Msk               (0x1U << SDIO_MASK_TXACTIE_Pos)    /*!< 0x00001000 */
-#define SDIO_MASK_TXACTIE                   SDIO_MASK_TXACTIE_Msk              /*!< Data Transmit Acting Interrupt Enable */
-#define SDIO_MASK_RXACTIE_Pos               (13U)                              
-#define SDIO_MASK_RXACTIE_Msk               (0x1U << SDIO_MASK_RXACTIE_Pos)    /*!< 0x00002000 */
-#define SDIO_MASK_RXACTIE                   SDIO_MASK_RXACTIE_Msk              /*!< Data receive acting interrupt enabled */
-#define SDIO_MASK_TXFIFOHEIE_Pos            (14U)                              
-#define SDIO_MASK_TXFIFOHEIE_Msk            (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
-#define SDIO_MASK_TXFIFOHEIE                SDIO_MASK_TXFIFOHEIE_Msk           /*!< Tx FIFO Half Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOHFIE_Pos            (15U)                              
-#define SDIO_MASK_RXFIFOHFIE_Msk            (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
-#define SDIO_MASK_RXFIFOHFIE                SDIO_MASK_RXFIFOHFIE_Msk           /*!< Rx FIFO Half Full interrupt Enable */
-#define SDIO_MASK_TXFIFOFIE_Pos             (16U)                              
-#define SDIO_MASK_TXFIFOFIE_Msk             (0x1U << SDIO_MASK_TXFIFOFIE_Pos)  /*!< 0x00010000 */
-#define SDIO_MASK_TXFIFOFIE                 SDIO_MASK_TXFIFOFIE_Msk            /*!< Tx FIFO Full interrupt Enable */
-#define SDIO_MASK_RXFIFOFIE_Pos             (17U)                              
-#define SDIO_MASK_RXFIFOFIE_Msk             (0x1U << SDIO_MASK_RXFIFOFIE_Pos)  /*!< 0x00020000 */
-#define SDIO_MASK_RXFIFOFIE                 SDIO_MASK_RXFIFOFIE_Msk            /*!< Rx FIFO Full interrupt Enable */
-#define SDIO_MASK_TXFIFOEIE_Pos             (18U)                              
-#define SDIO_MASK_TXFIFOEIE_Msk             (0x1U << SDIO_MASK_TXFIFOEIE_Pos)  /*!< 0x00040000 */
-#define SDIO_MASK_TXFIFOEIE                 SDIO_MASK_TXFIFOEIE_Msk            /*!< Tx FIFO Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOEIE_Pos             (19U)                              
-#define SDIO_MASK_RXFIFOEIE_Msk             (0x1U << SDIO_MASK_RXFIFOEIE_Pos)  /*!< 0x00080000 */
-#define SDIO_MASK_RXFIFOEIE                 SDIO_MASK_RXFIFOEIE_Msk            /*!< Rx FIFO Empty interrupt Enable */
-#define SDIO_MASK_TXDAVLIE_Pos              (20U)                              
-#define SDIO_MASK_TXDAVLIE_Msk              (0x1U << SDIO_MASK_TXDAVLIE_Pos)   /*!< 0x00100000 */
-#define SDIO_MASK_TXDAVLIE                  SDIO_MASK_TXDAVLIE_Msk             /*!< Data available in Tx FIFO interrupt Enable */
-#define SDIO_MASK_RXDAVLIE_Pos              (21U)                              
-#define SDIO_MASK_RXDAVLIE_Msk              (0x1U << SDIO_MASK_RXDAVLIE_Pos)   /*!< 0x00200000 */
-#define SDIO_MASK_RXDAVLIE                  SDIO_MASK_RXDAVLIE_Msk             /*!< Data available in Rx FIFO interrupt Enable */
-#define SDIO_MASK_SDIOITIE_Pos              (22U)                              
-#define SDIO_MASK_SDIOITIE_Msk              (0x1U << SDIO_MASK_SDIOITIE_Pos)   /*!< 0x00400000 */
-#define SDIO_MASK_SDIOITIE                  SDIO_MASK_SDIOITIE_Msk             /*!< SDIO Mode Interrupt Received interrupt Enable */
-#define SDIO_MASK_CEATAENDIE_Pos            (23U)                              
-#define SDIO_MASK_CEATAENDIE_Msk            (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
-#define SDIO_MASK_CEATAENDIE                SDIO_MASK_CEATAENDIE_Msk           /*!< CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define SDIO_FIFOCNT_FIFOCOUNT_Pos          (0U)                               
-#define SDIO_FIFOCNT_FIFOCOUNT_Msk          (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
-#define SDIO_FIFOCNT_FIFOCOUNT              SDIO_FIFOCNT_FIFOCOUNT_Msk         /*!< Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define SDIO_FIFO_FIFODATA_Pos              (0U)                               
-#define SDIO_FIFO_FIFODATA_Msk              (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_FIFO_FIFODATA                  SDIO_FIFO_FIFODATA_Msk             /*!< Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                   USB Device FS                            */
-/*                                                                            */
-/******************************************************************************/
-
-/*!< Endpoint-specific registers */
-#define  USB_EP0R                            USB_BASE                      /*!< Endpoint 0 register address */
-#define  USB_EP1R                            (USB_BASE + 0x00000004)       /*!< Endpoint 1 register address */
-#define  USB_EP2R                            (USB_BASE + 0x00000008)       /*!< Endpoint 2 register address */
-#define  USB_EP3R                            (USB_BASE + 0x0000000C)       /*!< Endpoint 3 register address */
-#define  USB_EP4R                            (USB_BASE + 0x00000010)       /*!< Endpoint 4 register address */
-#define  USB_EP5R                            (USB_BASE + 0x00000014)       /*!< Endpoint 5 register address */
-#define  USB_EP6R                            (USB_BASE + 0x00000018)       /*!< Endpoint 6 register address */
-#define  USB_EP7R                            (USB_BASE + 0x0000001C)       /*!< Endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                       (15U)                          
-#define USB_EP_CTR_RX_Msk                       (0x1U << USB_EP_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP_CTR_RX                           USB_EP_CTR_RX_Msk              /*!< EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                      (14U)                          
-#define USB_EP_DTOG_RX_Msk                      (0x1U << USB_EP_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                          USB_EP_DTOG_RX_Msk             /*!< EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                       (12U)                          
-#define USB_EPRX_STAT_Msk                       (0x3U << USB_EPRX_STAT_Pos)    /*!< 0x00003000 */
-#define USB_EPRX_STAT                           USB_EPRX_STAT_Msk              /*!< EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                        (11U)                          
-#define USB_EP_SETUP_Msk                        (0x1U << USB_EP_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP_SETUP                            USB_EP_SETUP_Msk               /*!< EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                      (9U)                           
-#define USB_EP_T_FIELD_Msk                      (0x3U << USB_EP_T_FIELD_Pos)   /*!< 0x00000600 */
-#define USB_EP_T_FIELD                          USB_EP_T_FIELD_Msk             /*!< EndPoint TYPE */
-#define USB_EP_KIND_Pos                         (8U)                           
-#define USB_EP_KIND_Msk                         (0x1U << USB_EP_KIND_Pos)      /*!< 0x00000100 */
-#define USB_EP_KIND                             USB_EP_KIND_Msk                /*!< EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                       (7U)                           
-#define USB_EP_CTR_TX_Msk                       (0x1U << USB_EP_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP_CTR_TX                           USB_EP_CTR_TX_Msk              /*!< EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                      (6U)                           
-#define USB_EP_DTOG_TX_Msk                      (0x1U << USB_EP_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                          USB_EP_DTOG_TX_Msk             /*!< EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                       (4U)                           
-#define USB_EPTX_STAT_Msk                       (0x3U << USB_EPTX_STAT_Pos)    /*!< 0x00000030 */
-#define USB_EPTX_STAT                           USB_EPTX_STAT_Msk              /*!< EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                    (0U)                           
-#define USB_EPADDR_FIELD_Msk                    (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                        USB_EPADDR_FIELD_Msk           /*!< EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK                      (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                           /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                    (9U)                           
-#define USB_EP_TYPE_MASK_Msk                    (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                        USB_EP_TYPE_MASK_Msk           /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                             ((uint32_t)0x00000000)         /*!< EndPoint BULK */
-#define USB_EP_CONTROL                          ((uint32_t)0x00000200)         /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                      ((uint32_t)0x00000400)         /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                        ((uint32_t)0x00000600)         /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK                       (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK                     (~USB_EP_KIND & USB_EPREG_MASK)  /*!< EP_KIND EndPoint KIND */
-                                                                           /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                           ((uint32_t)0x00000000)         /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                         ((uint32_t)0x00000010)         /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                           ((uint32_t)0x00000020)         /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                         ((uint32_t)0x00000030)         /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                          ((uint32_t)0x00000010)         /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                          ((uint32_t)0x00000020)         /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                           /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                           ((uint32_t)0x00000000)         /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                         ((uint32_t)0x00001000)         /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                           ((uint32_t)0x00002000)         /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                         ((uint32_t)0x00003000)         /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                          ((uint32_t)0x00001000)         /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                          ((uint32_t)0x00002000)         /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                         (0U)                           
-#define USB_EP0R_EA_Msk                         (0xFU << USB_EP0R_EA_Pos)      /*!< 0x0000000F */
-#define USB_EP0R_EA                             USB_EP0R_EA_Msk                /*!< Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                    (4U)                           
-#define USB_EP0R_STAT_TX_Msk                    (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                        USB_EP0R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                      (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                      (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                    (6U)                           
-#define USB_EP0R_DTOG_TX_Msk                    (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                        USB_EP0R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                     (7U)                           
-#define USB_EP0R_CTR_TX_Msk                     (0x1U << USB_EP0R_CTR_TX_Pos)  /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                         USB_EP0R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                    (8U)                           
-#define USB_EP0R_EP_KIND_Msk                    (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                        USB_EP0R_EP_KIND_Msk           /*!< Endpoint Kind */
-                                                                           
-#define USB_EP0R_EP_TYPE_Pos                    (9U)                           
-#define USB_EP0R_EP_TYPE_Msk                    (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                        USB_EP0R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                      (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                      (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                      (11U)                          
-#define USB_EP0R_SETUP_Msk                      (0x1U << USB_EP0R_SETUP_Pos)   /*!< 0x00000800 */
-#define USB_EP0R_SETUP                          USB_EP0R_SETUP_Msk             /*!< Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                    (12U)                          
-#define USB_EP0R_STAT_RX_Msk                    (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                        USB_EP0R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                      (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                      (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                    (14U)                          
-#define USB_EP0R_DTOG_RX_Msk                    (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                        USB_EP0R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                     (15U)                          
-#define USB_EP0R_CTR_RX_Msk                     (0x1U << USB_EP0R_CTR_RX_Pos)  /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                         USB_EP0R_CTR_RX_Msk            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                         (0U)                           
-#define USB_EP1R_EA_Msk                         (0xFU << USB_EP1R_EA_Pos)      /*!< 0x0000000F */
-#define USB_EP1R_EA                             USB_EP1R_EA_Msk                /*!< Endpoint Address */
-                                                                          
-#define USB_EP1R_STAT_TX_Pos                    (4U)                           
-#define USB_EP1R_STAT_TX_Msk                    (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                        USB_EP1R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                      (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                      (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                    (6U)                           
-#define USB_EP1R_DTOG_TX_Msk                    (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                        USB_EP1R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                     (7U)                           
-#define USB_EP1R_CTR_TX_Msk                     (0x1U << USB_EP1R_CTR_TX_Pos)  /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                         USB_EP1R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                    (8U)                           
-#define USB_EP1R_EP_KIND_Msk                    (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                        USB_EP1R_EP_KIND_Msk           /*!< Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                    (9U)                           
-#define USB_EP1R_EP_TYPE_Msk                    (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                        USB_EP1R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                      (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                      (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                      (11U)                          
-#define USB_EP1R_SETUP_Msk                      (0x1U << USB_EP1R_SETUP_Pos)   /*!< 0x00000800 */
-#define USB_EP1R_SETUP                          USB_EP1R_SETUP_Msk             /*!< Setup transaction completed */
-                                                                           
-#define USB_EP1R_STAT_RX_Pos                    (12U)                          
-#define USB_EP1R_STAT_RX_Msk                    (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                        USB_EP1R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                      (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                      (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                    (14U)                          
-#define USB_EP1R_DTOG_RX_Msk                    (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                        USB_EP1R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                     (15U)                          
-#define USB_EP1R_CTR_RX_Msk                     (0x1U << USB_EP1R_CTR_RX_Pos)  /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                         USB_EP1R_CTR_RX_Msk            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                         (0U)                           
-#define USB_EP2R_EA_Msk                         (0xFU << USB_EP2R_EA_Pos)      /*!< 0x0000000F */
-#define USB_EP2R_EA                             USB_EP2R_EA_Msk                /*!< Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                    (4U)                           
-#define USB_EP2R_STAT_TX_Msk                    (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                        USB_EP2R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                      (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                      (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                    (6U)                           
-#define USB_EP2R_DTOG_TX_Msk                    (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                        USB_EP2R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                     (7U)                           
-#define USB_EP2R_CTR_TX_Msk                     (0x1U << USB_EP2R_CTR_TX_Pos)  /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                         USB_EP2R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                    (8U)                           
-#define USB_EP2R_EP_KIND_Msk                    (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                        USB_EP2R_EP_KIND_Msk           /*!< Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                    (9U)                           
-#define USB_EP2R_EP_TYPE_Msk                    (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                        USB_EP2R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                      (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                      (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                      (11U)                          
-#define USB_EP2R_SETUP_Msk                      (0x1U << USB_EP2R_SETUP_Pos)   /*!< 0x00000800 */
-#define USB_EP2R_SETUP                          USB_EP2R_SETUP_Msk             /*!< Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                    (12U)                          
-#define USB_EP2R_STAT_RX_Msk                    (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                        USB_EP2R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                      (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                      (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                    (14U)                          
-#define USB_EP2R_DTOG_RX_Msk                    (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                        USB_EP2R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                     (15U)                          
-#define USB_EP2R_CTR_RX_Msk                     (0x1U << USB_EP2R_CTR_RX_Pos)  /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                         USB_EP2R_CTR_RX_Msk            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                         (0U)                           
-#define USB_EP3R_EA_Msk                         (0xFU << USB_EP3R_EA_Pos)      /*!< 0x0000000F */
-#define USB_EP3R_EA                             USB_EP3R_EA_Msk                /*!< Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                    (4U)                           
-#define USB_EP3R_STAT_TX_Msk                    (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                        USB_EP3R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                      (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                      (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                    (6U)                           
-#define USB_EP3R_DTOG_TX_Msk                    (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                        USB_EP3R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                     (7U)                           
-#define USB_EP3R_CTR_TX_Msk                     (0x1U << USB_EP3R_CTR_TX_Pos)  /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                         USB_EP3R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                    (8U)                           
-#define USB_EP3R_EP_KIND_Msk                    (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                        USB_EP3R_EP_KIND_Msk           /*!< Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                    (9U)                           
-#define USB_EP3R_EP_TYPE_Msk                    (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                        USB_EP3R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                      (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                      (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                      (11U)                          
-#define USB_EP3R_SETUP_Msk                      (0x1U << USB_EP3R_SETUP_Pos)   /*!< 0x00000800 */
-#define USB_EP3R_SETUP                          USB_EP3R_SETUP_Msk             /*!< Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                    (12U)                          
-#define USB_EP3R_STAT_RX_Msk                    (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                        USB_EP3R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                      (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                      (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                    (14U)                          
-#define USB_EP3R_DTOG_RX_Msk                    (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                        USB_EP3R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                     (15U)                          
-#define USB_EP3R_CTR_RX_Msk                     (0x1U << USB_EP3R_CTR_RX_Pos)  /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                         USB_EP3R_CTR_RX_Msk            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                         (0U)                           
-#define USB_EP4R_EA_Msk                         (0xFU << USB_EP4R_EA_Pos)      /*!< 0x0000000F */
-#define USB_EP4R_EA                             USB_EP4R_EA_Msk                /*!< Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                    (4U)                           
-#define USB_EP4R_STAT_TX_Msk                    (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                        USB_EP4R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                      (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                      (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                    (6U)                           
-#define USB_EP4R_DTOG_TX_Msk                    (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                        USB_EP4R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                     (7U)                           
-#define USB_EP4R_CTR_TX_Msk                     (0x1U << USB_EP4R_CTR_TX_Pos)  /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                         USB_EP4R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                    (8U)                           
-#define USB_EP4R_EP_KIND_Msk                    (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                        USB_EP4R_EP_KIND_Msk           /*!< Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                    (9U)                           
-#define USB_EP4R_EP_TYPE_Msk                    (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                        USB_EP4R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                      (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                      (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                      (11U)                          
-#define USB_EP4R_SETUP_Msk                      (0x1U << USB_EP4R_SETUP_Pos)   /*!< 0x00000800 */
-#define USB_EP4R_SETUP                          USB_EP4R_SETUP_Msk             /*!< Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                    (12U)                          
-#define USB_EP4R_STAT_RX_Msk                    (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                        USB_EP4R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                      (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                      (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                    (14U)                          
-#define USB_EP4R_DTOG_RX_Msk                    (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                        USB_EP4R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                     (15U)                          
-#define USB_EP4R_CTR_RX_Msk                     (0x1U << USB_EP4R_CTR_RX_Pos)  /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                         USB_EP4R_CTR_RX_Msk            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                         (0U)                           
-#define USB_EP5R_EA_Msk                         (0xFU << USB_EP5R_EA_Pos)      /*!< 0x0000000F */
-#define USB_EP5R_EA                             USB_EP5R_EA_Msk                /*!< Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                    (4U)                           
-#define USB_EP5R_STAT_TX_Msk                    (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                        USB_EP5R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                      (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                      (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                    (6U)                           
-#define USB_EP5R_DTOG_TX_Msk                    (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                        USB_EP5R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                     (7U)                           
-#define USB_EP5R_CTR_TX_Msk                     (0x1U << USB_EP5R_CTR_TX_Pos)  /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                         USB_EP5R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                    (8U)                           
-#define USB_EP5R_EP_KIND_Msk                    (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                        USB_EP5R_EP_KIND_Msk           /*!< Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                    (9U)                           
-#define USB_EP5R_EP_TYPE_Msk                    (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                        USB_EP5R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                      (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                      (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                      (11U)                          
-#define USB_EP5R_SETUP_Msk                      (0x1U << USB_EP5R_SETUP_Pos)   /*!< 0x00000800 */
-#define USB_EP5R_SETUP                          USB_EP5R_SETUP_Msk             /*!< Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                    (12U)                          
-#define USB_EP5R_STAT_RX_Msk                    (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                        USB_EP5R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                      (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                      (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                    (14U)                          
-#define USB_EP5R_DTOG_RX_Msk                    (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                        USB_EP5R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                     (15U)                          
-#define USB_EP5R_CTR_RX_Msk                     (0x1U << USB_EP5R_CTR_RX_Pos)  /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                         USB_EP5R_CTR_RX_Msk            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                         (0U)                           
-#define USB_EP6R_EA_Msk                         (0xFU << USB_EP6R_EA_Pos)      /*!< 0x0000000F */
-#define USB_EP6R_EA                             USB_EP6R_EA_Msk                /*!< Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                    (4U)                           
-#define USB_EP6R_STAT_TX_Msk                    (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                        USB_EP6R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                      (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                      (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                    (6U)                           
-#define USB_EP6R_DTOG_TX_Msk                    (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                        USB_EP6R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                     (7U)                           
-#define USB_EP6R_CTR_TX_Msk                     (0x1U << USB_EP6R_CTR_TX_Pos)  /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                         USB_EP6R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                    (8U)                           
-#define USB_EP6R_EP_KIND_Msk                    (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                        USB_EP6R_EP_KIND_Msk           /*!< Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                    (9U)                           
-#define USB_EP6R_EP_TYPE_Msk                    (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                        USB_EP6R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                      (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                      (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                      (11U)                          
-#define USB_EP6R_SETUP_Msk                      (0x1U << USB_EP6R_SETUP_Pos)   /*!< 0x00000800 */
-#define USB_EP6R_SETUP                          USB_EP6R_SETUP_Msk             /*!< Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                    (12U)                          
-#define USB_EP6R_STAT_RX_Msk                    (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                        USB_EP6R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                      (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                      (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                    (14U)                          
-#define USB_EP6R_DTOG_RX_Msk                    (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                        USB_EP6R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                     (15U)                          
-#define USB_EP6R_CTR_RX_Msk                     (0x1U << USB_EP6R_CTR_RX_Pos)  /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                         USB_EP6R_CTR_RX_Msk            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                         (0U)                           
-#define USB_EP7R_EA_Msk                         (0xFU << USB_EP7R_EA_Pos)      /*!< 0x0000000F */
-#define USB_EP7R_EA                             USB_EP7R_EA_Msk                /*!< Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                    (4U)                           
-#define USB_EP7R_STAT_TX_Msk                    (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                        USB_EP7R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                      (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                      (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                    (6U)                           
-#define USB_EP7R_DTOG_TX_Msk                    (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                        USB_EP7R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                     (7U)                           
-#define USB_EP7R_CTR_TX_Msk                     (0x1U << USB_EP7R_CTR_TX_Pos)  /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                         USB_EP7R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                    (8U)                           
-#define USB_EP7R_EP_KIND_Msk                    (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                        USB_EP7R_EP_KIND_Msk           /*!< Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                    (9U)                           
-#define USB_EP7R_EP_TYPE_Msk                    (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                        USB_EP7R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                      (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                      (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                      (11U)                          
-#define USB_EP7R_SETUP_Msk                      (0x1U << USB_EP7R_SETUP_Pos)   /*!< 0x00000800 */
-#define USB_EP7R_SETUP                          USB_EP7R_SETUP_Msk             /*!< Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                    (12U)                          
-#define USB_EP7R_STAT_RX_Msk                    (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                        USB_EP7R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                      (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                      (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                    (14U)                          
-#define USB_EP7R_DTOG_RX_Msk                    (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                        USB_EP7R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                     (15U)                          
-#define USB_EP7R_CTR_RX_Msk                     (0x1U << USB_EP7R_CTR_RX_Pos)  /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                         USB_EP7R_CTR_RX_Msk            /*!< Correct Transfer for reception */
-
-/*!< Common registers */
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                       (0U)                           
-#define USB_CNTR_FRES_Msk                       (0x1U << USB_CNTR_FRES_Pos)    /*!< 0x00000001 */
-#define USB_CNTR_FRES                           USB_CNTR_FRES_Msk              /*!< Force USB Reset */
-#define USB_CNTR_PDWN_Pos                       (1U)                           
-#define USB_CNTR_PDWN_Msk                       (0x1U << USB_CNTR_PDWN_Pos)    /*!< 0x00000002 */
-#define USB_CNTR_PDWN                           USB_CNTR_PDWN_Msk              /*!< Power down */
-#define USB_CNTR_LP_MODE_Pos                    (2U)                           
-#define USB_CNTR_LP_MODE_Msk                    (0x1U << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */
-#define USB_CNTR_LP_MODE                        USB_CNTR_LP_MODE_Msk           /*!< Low-power mode */
-#define USB_CNTR_FSUSP_Pos                      (3U)                           
-#define USB_CNTR_FSUSP_Msk                      (0x1U << USB_CNTR_FSUSP_Pos)   /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                          USB_CNTR_FSUSP_Msk             /*!< Force suspend */
-#define USB_CNTR_RESUME_Pos                     (4U)                           
-#define USB_CNTR_RESUME_Msk                     (0x1U << USB_CNTR_RESUME_Pos)  /*!< 0x00000010 */
-#define USB_CNTR_RESUME                         USB_CNTR_RESUME_Msk            /*!< Resume request */
-#define USB_CNTR_ESOFM_Pos                      (8U)                           
-#define USB_CNTR_ESOFM_Msk                      (0x1U << USB_CNTR_ESOFM_Pos)   /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                          USB_CNTR_ESOFM_Msk             /*!< Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                       (9U)                           
-#define USB_CNTR_SOFM_Msk                       (0x1U << USB_CNTR_SOFM_Pos)    /*!< 0x00000200 */
-#define USB_CNTR_SOFM                           USB_CNTR_SOFM_Msk              /*!< Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                     (10U)                          
-#define USB_CNTR_RESETM_Msk                     (0x1U << USB_CNTR_RESETM_Pos)  /*!< 0x00000400 */
-#define USB_CNTR_RESETM                         USB_CNTR_RESETM_Msk            /*!< RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                      (11U)                          
-#define USB_CNTR_SUSPM_Msk                      (0x1U << USB_CNTR_SUSPM_Pos)   /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                          USB_CNTR_SUSPM_Msk             /*!< Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                      (12U)                          
-#define USB_CNTR_WKUPM_Msk                      (0x1U << USB_CNTR_WKUPM_Pos)   /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                          USB_CNTR_WKUPM_Msk             /*!< Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                       (13U)                          
-#define USB_CNTR_ERRM_Msk                       (0x1U << USB_CNTR_ERRM_Pos)    /*!< 0x00002000 */
-#define USB_CNTR_ERRM                           USB_CNTR_ERRM_Msk              /*!< Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                    (14U)                          
-#define USB_CNTR_PMAOVRM_Msk                    (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                        USB_CNTR_PMAOVRM_Msk           /*!< Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                       (15U)                          
-#define USB_CNTR_CTRM_Msk                       (0x1U << USB_CNTR_CTRM_Pos)    /*!< 0x00008000 */
-#define USB_CNTR_CTRM                           USB_CNTR_CTRM_Msk              /*!< Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                      (0U)                           
-#define USB_ISTR_EP_ID_Msk                      (0xFU << USB_ISTR_EP_ID_Pos)   /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                          USB_ISTR_EP_ID_Msk             /*!< Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                        (4U)                           
-#define USB_ISTR_DIR_Msk                        (0x1U << USB_ISTR_DIR_Pos)     /*!< 0x00000010 */
-#define USB_ISTR_DIR                            USB_ISTR_DIR_Msk               /*!< Direction of transaction */
-#define USB_ISTR_ESOF_Pos                       (8U)                           
-#define USB_ISTR_ESOF_Msk                       (0x1U << USB_ISTR_ESOF_Pos)    /*!< 0x00000100 */
-#define USB_ISTR_ESOF                           USB_ISTR_ESOF_Msk              /*!< Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                        (9U)                           
-#define USB_ISTR_SOF_Msk                        (0x1U << USB_ISTR_SOF_Pos)     /*!< 0x00000200 */
-#define USB_ISTR_SOF                            USB_ISTR_SOF_Msk               /*!< Start Of Frame */
-#define USB_ISTR_RESET_Pos                      (10U)                          
-#define USB_ISTR_RESET_Msk                      (0x1U << USB_ISTR_RESET_Pos)   /*!< 0x00000400 */
-#define USB_ISTR_RESET                          USB_ISTR_RESET_Msk             /*!< USB RESET request */
-#define USB_ISTR_SUSP_Pos                       (11U)                          
-#define USB_ISTR_SUSP_Msk                       (0x1U << USB_ISTR_SUSP_Pos)    /*!< 0x00000800 */
-#define USB_ISTR_SUSP                           USB_ISTR_SUSP_Msk              /*!< Suspend mode request */
-#define USB_ISTR_WKUP_Pos                       (12U)                          
-#define USB_ISTR_WKUP_Msk                       (0x1U << USB_ISTR_WKUP_Pos)    /*!< 0x00001000 */
-#define USB_ISTR_WKUP                           USB_ISTR_WKUP_Msk              /*!< Wake up */
-#define USB_ISTR_ERR_Pos                        (13U)                          
-#define USB_ISTR_ERR_Msk                        (0x1U << USB_ISTR_ERR_Pos)     /*!< 0x00002000 */
-#define USB_ISTR_ERR                            USB_ISTR_ERR_Msk               /*!< Error */
-#define USB_ISTR_PMAOVR_Pos                     (14U)                          
-#define USB_ISTR_PMAOVR_Msk                     (0x1U << USB_ISTR_PMAOVR_Pos)  /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                         USB_ISTR_PMAOVR_Msk            /*!< Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                        (15U)                          
-#define USB_ISTR_CTR_Msk                        (0x1U << USB_ISTR_CTR_Pos)     /*!< 0x00008000 */
-#define USB_ISTR_CTR                            USB_ISTR_CTR_Msk               /*!< Correct Transfer */
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                          (0U)                           
-#define USB_FNR_FN_Msk                          (0x7FFU << USB_FNR_FN_Pos)     /*!< 0x000007FF */
-#define USB_FNR_FN                              USB_FNR_FN_Msk                 /*!< Frame Number */
-#define USB_FNR_LSOF_Pos                        (11U)                          
-#define USB_FNR_LSOF_Msk                        (0x3U << USB_FNR_LSOF_Pos)     /*!< 0x00001800 */
-#define USB_FNR_LSOF                            USB_FNR_LSOF_Msk               /*!< Lost SOF */
-#define USB_FNR_LCK_Pos                         (13U)                          
-#define USB_FNR_LCK_Msk                         (0x1U << USB_FNR_LCK_Pos)      /*!< 0x00002000 */
-#define USB_FNR_LCK                             USB_FNR_LCK_Msk                /*!< Locked */
-#define USB_FNR_RXDM_Pos                        (14U)                          
-#define USB_FNR_RXDM_Msk                        (0x1U << USB_FNR_RXDM_Pos)     /*!< 0x00004000 */
-#define USB_FNR_RXDM                            USB_FNR_RXDM_Msk               /*!< Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                        (15U)                          
-#define USB_FNR_RXDP_Msk                        (0x1U << USB_FNR_RXDP_Pos)     /*!< 0x00008000 */
-#define USB_FNR_RXDP                            USB_FNR_RXDP_Msk               /*!< Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                       (0U)                           
-#define USB_DADDR_ADD_Msk                       (0x7FU << USB_DADDR_ADD_Pos)   /*!< 0x0000007F */
-#define USB_DADDR_ADD                           USB_DADDR_ADD_Msk              /*!< ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                      (0U)                           
-#define USB_DADDR_ADD0_Msk                      (0x1U << USB_DADDR_ADD0_Pos)   /*!< 0x00000001 */
-#define USB_DADDR_ADD0                          USB_DADDR_ADD0_Msk             /*!< Bit 0 */
-#define USB_DADDR_ADD1_Pos                      (1U)                           
-#define USB_DADDR_ADD1_Msk                      (0x1U << USB_DADDR_ADD1_Pos)   /*!< 0x00000002 */
-#define USB_DADDR_ADD1                          USB_DADDR_ADD1_Msk             /*!< Bit 1 */
-#define USB_DADDR_ADD2_Pos                      (2U)                           
-#define USB_DADDR_ADD2_Msk                      (0x1U << USB_DADDR_ADD2_Pos)   /*!< 0x00000004 */
-#define USB_DADDR_ADD2                          USB_DADDR_ADD2_Msk             /*!< Bit 2 */
-#define USB_DADDR_ADD3_Pos                      (3U)                           
-#define USB_DADDR_ADD3_Msk                      (0x1U << USB_DADDR_ADD3_Pos)   /*!< 0x00000008 */
-#define USB_DADDR_ADD3                          USB_DADDR_ADD3_Msk             /*!< Bit 3 */
-#define USB_DADDR_ADD4_Pos                      (4U)                           
-#define USB_DADDR_ADD4_Msk                      (0x1U << USB_DADDR_ADD4_Pos)   /*!< 0x00000010 */
-#define USB_DADDR_ADD4                          USB_DADDR_ADD4_Msk             /*!< Bit 4 */
-#define USB_DADDR_ADD5_Pos                      (5U)                           
-#define USB_DADDR_ADD5_Msk                      (0x1U << USB_DADDR_ADD5_Pos)   /*!< 0x00000020 */
-#define USB_DADDR_ADD5                          USB_DADDR_ADD5_Msk             /*!< Bit 5 */
-#define USB_DADDR_ADD6_Pos                      (6U)                           
-#define USB_DADDR_ADD6_Msk                      (0x1U << USB_DADDR_ADD6_Pos)   /*!< 0x00000040 */
-#define USB_DADDR_ADD6                          USB_DADDR_ADD6_Msk             /*!< Bit 6 */
-
-#define USB_DADDR_EF_Pos                        (7U)                           
-#define USB_DADDR_EF_Msk                        (0x1U << USB_DADDR_EF_Pos)     /*!< 0x00000080 */
-#define USB_DADDR_EF                            USB_DADDR_EF_Msk               /*!< Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                   (3U)                           
-#define USB_BTABLE_BTABLE_Msk                   (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                       USB_BTABLE_BTABLE_Msk          /*!< Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos               (1U)                           
-#define USB_ADDR0_TX_ADDR0_TX_Msk               (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                   USB_ADDR0_TX_ADDR0_TX_Msk      /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos               (1U)                           
-#define USB_ADDR1_TX_ADDR1_TX_Msk               (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                   USB_ADDR1_TX_ADDR1_TX_Msk      /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos               (1U)                           
-#define USB_ADDR2_TX_ADDR2_TX_Msk               (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                   USB_ADDR2_TX_ADDR2_TX_Msk      /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos               (1U)                           
-#define USB_ADDR3_TX_ADDR3_TX_Msk               (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                   USB_ADDR3_TX_ADDR3_TX_Msk      /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos               (1U)                           
-#define USB_ADDR4_TX_ADDR4_TX_Msk               (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                   USB_ADDR4_TX_ADDR4_TX_Msk      /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos               (1U)                           
-#define USB_ADDR5_TX_ADDR5_TX_Msk               (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                   USB_ADDR5_TX_ADDR5_TX_Msk      /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos               (1U)                           
-#define USB_ADDR6_TX_ADDR6_TX_Msk               (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                   USB_ADDR6_TX_ADDR6_TX_Msk      /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos               (1U)                           
-#define USB_ADDR7_TX_ADDR7_TX_Msk               (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                   USB_ADDR7_TX_ADDR7_TX_Msk      /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos             (0U)                           
-#define USB_COUNT0_TX_COUNT0_TX_Msk             (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX                 USB_COUNT0_TX_COUNT0_TX_Msk    /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos             (0U)                           
-#define USB_COUNT1_TX_COUNT1_TX_Msk             (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX                 USB_COUNT1_TX_COUNT1_TX_Msk    /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos             (0U)                           
-#define USB_COUNT2_TX_COUNT2_TX_Msk             (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX                 USB_COUNT2_TX_COUNT2_TX_Msk    /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos             (0U)                           
-#define USB_COUNT3_TX_COUNT3_TX_Msk             (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX                 USB_COUNT3_TX_COUNT3_TX_Msk    /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos             (0U)                           
-#define USB_COUNT4_TX_COUNT4_TX_Msk             (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX                 USB_COUNT4_TX_COUNT4_TX_Msk    /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos             (0U)                           
-#define USB_COUNT5_TX_COUNT5_TX_Msk             (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX                 USB_COUNT5_TX_COUNT5_TX_Msk    /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos             (0U)                           
-#define USB_COUNT6_TX_COUNT6_TX_Msk             (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX                 USB_COUNT6_TX_COUNT6_TX_Msk    /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos             (0U)                           
-#define USB_COUNT7_TX_COUNT7_TX_Msk             (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX                 USB_COUNT7_TX_COUNT7_TX_Msk    /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos               (1U)                           
-#define USB_ADDR0_RX_ADDR0_RX_Msk               (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                   USB_ADDR0_RX_ADDR0_RX_Msk      /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos               (1U)                           
-#define USB_ADDR1_RX_ADDR1_RX_Msk               (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                   USB_ADDR1_RX_ADDR1_RX_Msk      /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos               (1U)                           
-#define USB_ADDR2_RX_ADDR2_RX_Msk               (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                   USB_ADDR2_RX_ADDR2_RX_Msk      /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos               (1U)                           
-#define USB_ADDR3_RX_ADDR3_RX_Msk               (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                   USB_ADDR3_RX_ADDR3_RX_Msk      /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos               (1U)                           
-#define USB_ADDR4_RX_ADDR4_RX_Msk               (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                   USB_ADDR4_RX_ADDR4_RX_Msk      /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos               (1U)                           
-#define USB_ADDR5_RX_ADDR5_RX_Msk               (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                   USB_ADDR5_RX_ADDR5_RX_Msk      /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos               (1U)                           
-#define USB_ADDR6_RX_ADDR6_RX_Msk               (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                   USB_ADDR6_RX_ADDR6_RX_Msk      /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos               (1U)                           
-#define USB_ADDR7_RX_ADDR7_RX_Msk               (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                   USB_ADDR7_RX_ADDR7_RX_Msk      /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos             (0U)                           
-#define USB_COUNT0_RX_COUNT0_RX_Msk             (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX                 USB_COUNT0_RX_COUNT0_RX_Msk    /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos             (10U)                          
-#define USB_COUNT0_RX_NUM_BLOCK_Msk             (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK                 USB_COUNT0_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0               (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1               (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2               (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3               (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4               (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos                (15U)                          
-#define USB_COUNT0_RX_BLSIZE_Msk                (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                    USB_COUNT0_RX_BLSIZE_Msk       /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos             (0U)                           
-#define USB_COUNT1_RX_COUNT1_RX_Msk             (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX                 USB_COUNT1_RX_COUNT1_RX_Msk    /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos             (10U)                          
-#define USB_COUNT1_RX_NUM_BLOCK_Msk             (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK                 USB_COUNT1_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0               (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1               (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2               (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3               (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4               (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos                (15U)                          
-#define USB_COUNT1_RX_BLSIZE_Msk                (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                    USB_COUNT1_RX_BLSIZE_Msk       /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos             (0U)                           
-#define USB_COUNT2_RX_COUNT2_RX_Msk             (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX                 USB_COUNT2_RX_COUNT2_RX_Msk    /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos             (10U)                          
-#define USB_COUNT2_RX_NUM_BLOCK_Msk             (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK                 USB_COUNT2_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0               (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1               (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2               (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3               (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4               (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos                (15U)                          
-#define USB_COUNT2_RX_BLSIZE_Msk                (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                    USB_COUNT2_RX_BLSIZE_Msk       /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos             (0U)                           
-#define USB_COUNT3_RX_COUNT3_RX_Msk             (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX                 USB_COUNT3_RX_COUNT3_RX_Msk    /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos             (10U)                          
-#define USB_COUNT3_RX_NUM_BLOCK_Msk             (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK                 USB_COUNT3_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0               (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1               (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2               (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3               (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4               (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos                (15U)                          
-#define USB_COUNT3_RX_BLSIZE_Msk                (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                    USB_COUNT3_RX_BLSIZE_Msk       /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos             (0U)                           
-#define USB_COUNT4_RX_COUNT4_RX_Msk             (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX                 USB_COUNT4_RX_COUNT4_RX_Msk    /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos             (10U)                          
-#define USB_COUNT4_RX_NUM_BLOCK_Msk             (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK                 USB_COUNT4_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0               (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1               (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2               (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3               (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4               (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos                (15U)                          
-#define USB_COUNT4_RX_BLSIZE_Msk                (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                    USB_COUNT4_RX_BLSIZE_Msk       /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos             (0U)                           
-#define USB_COUNT5_RX_COUNT5_RX_Msk             (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX                 USB_COUNT5_RX_COUNT5_RX_Msk    /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos             (10U)                          
-#define USB_COUNT5_RX_NUM_BLOCK_Msk             (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK                 USB_COUNT5_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0               (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1               (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2               (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3               (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4               (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos                (15U)                          
-#define USB_COUNT5_RX_BLSIZE_Msk                (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                    USB_COUNT5_RX_BLSIZE_Msk       /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos             (0U)                           
-#define USB_COUNT6_RX_COUNT6_RX_Msk             (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX                 USB_COUNT6_RX_COUNT6_RX_Msk    /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos             (10U)                          
-#define USB_COUNT6_RX_NUM_BLOCK_Msk             (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK                 USB_COUNT6_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0               (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1               (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2               (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3               (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4               (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos                (15U)                          
-#define USB_COUNT6_RX_BLSIZE_Msk                (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                    USB_COUNT6_RX_BLSIZE_Msk       /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos             (0U)                           
-#define USB_COUNT7_RX_COUNT7_RX_Msk             (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX                 USB_COUNT7_RX_COUNT7_RX_Msk    /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos             (10U)                          
-#define USB_COUNT7_RX_NUM_BLOCK_Msk             (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK                 USB_COUNT7_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0               (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1               (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2               (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3               (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4               (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos                (15U)                          
-#define USB_COUNT7_RX_BLSIZE_Msk                (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                    USB_COUNT7_RX_BLSIZE_Msk       /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-
-/*!< CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define CAN_MCR_INRQ_Pos                     (0U)                              
-#define CAN_MCR_INRQ_Msk                     (0x1U << CAN_MCR_INRQ_Pos)        /*!< 0x00000001 */
-#define CAN_MCR_INRQ                         CAN_MCR_INRQ_Msk                  /*!< Initialization Request */
-#define CAN_MCR_SLEEP_Pos                    (1U)                              
-#define CAN_MCR_SLEEP_Msk                    (0x1U << CAN_MCR_SLEEP_Pos)       /*!< 0x00000002 */
-#define CAN_MCR_SLEEP                        CAN_MCR_SLEEP_Msk                 /*!< Sleep Mode Request */
-#define CAN_MCR_TXFP_Pos                     (2U)                              
-#define CAN_MCR_TXFP_Msk                     (0x1U << CAN_MCR_TXFP_Pos)        /*!< 0x00000004 */
-#define CAN_MCR_TXFP                         CAN_MCR_TXFP_Msk                  /*!< Transmit FIFO Priority */
-#define CAN_MCR_RFLM_Pos                     (3U)                              
-#define CAN_MCR_RFLM_Msk                     (0x1U << CAN_MCR_RFLM_Pos)        /*!< 0x00000008 */
-#define CAN_MCR_RFLM                         CAN_MCR_RFLM_Msk                  /*!< Receive FIFO Locked Mode */
-#define CAN_MCR_NART_Pos                     (4U)                              
-#define CAN_MCR_NART_Msk                     (0x1U << CAN_MCR_NART_Pos)        /*!< 0x00000010 */
-#define CAN_MCR_NART                         CAN_MCR_NART_Msk                  /*!< No Automatic Retransmission */
-#define CAN_MCR_AWUM_Pos                     (5U)                              
-#define CAN_MCR_AWUM_Msk                     (0x1U << CAN_MCR_AWUM_Pos)        /*!< 0x00000020 */
-#define CAN_MCR_AWUM                         CAN_MCR_AWUM_Msk                  /*!< Automatic Wakeup Mode */
-#define CAN_MCR_ABOM_Pos                     (6U)                              
-#define CAN_MCR_ABOM_Msk                     (0x1U << CAN_MCR_ABOM_Pos)        /*!< 0x00000040 */
-#define CAN_MCR_ABOM                         CAN_MCR_ABOM_Msk                  /*!< Automatic Bus-Off Management */
-#define CAN_MCR_TTCM_Pos                     (7U)                              
-#define CAN_MCR_TTCM_Msk                     (0x1U << CAN_MCR_TTCM_Pos)        /*!< 0x00000080 */
-#define CAN_MCR_TTCM                         CAN_MCR_TTCM_Msk                  /*!< Time Triggered Communication Mode */
-#define CAN_MCR_RESET_Pos                    (15U)                             
-#define CAN_MCR_RESET_Msk                    (0x1U << CAN_MCR_RESET_Pos)       /*!< 0x00008000 */
-#define CAN_MCR_RESET                        CAN_MCR_RESET_Msk                 /*!< CAN software master reset */
-#define CAN_MCR_DBF_Pos                      (16U)                             
-#define CAN_MCR_DBF_Msk                      (0x1U << CAN_MCR_DBF_Pos)         /*!< 0x00010000 */
-#define CAN_MCR_DBF                          CAN_MCR_DBF_Msk                   /*!< CAN Debug freeze */
-
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define CAN_MSR_INAK_Pos                     (0U)                              
-#define CAN_MSR_INAK_Msk                     (0x1U << CAN_MSR_INAK_Pos)        /*!< 0x00000001 */
-#define CAN_MSR_INAK                         CAN_MSR_INAK_Msk                  /*!< Initialization Acknowledge */
-#define CAN_MSR_SLAK_Pos                     (1U)                              
-#define CAN_MSR_SLAK_Msk                     (0x1U << CAN_MSR_SLAK_Pos)        /*!< 0x00000002 */
-#define CAN_MSR_SLAK                         CAN_MSR_SLAK_Msk                  /*!< Sleep Acknowledge */
-#define CAN_MSR_ERRI_Pos                     (2U)                              
-#define CAN_MSR_ERRI_Msk                     (0x1U << CAN_MSR_ERRI_Pos)        /*!< 0x00000004 */
-#define CAN_MSR_ERRI                         CAN_MSR_ERRI_Msk                  /*!< Error Interrupt */
-#define CAN_MSR_WKUI_Pos                     (3U)                              
-#define CAN_MSR_WKUI_Msk                     (0x1U << CAN_MSR_WKUI_Pos)        /*!< 0x00000008 */
-#define CAN_MSR_WKUI                         CAN_MSR_WKUI_Msk                  /*!< Wakeup Interrupt */
-#define CAN_MSR_SLAKI_Pos                    (4U)                              
-#define CAN_MSR_SLAKI_Msk                    (0x1U << CAN_MSR_SLAKI_Pos)       /*!< 0x00000010 */
-#define CAN_MSR_SLAKI                        CAN_MSR_SLAKI_Msk                 /*!< Sleep Acknowledge Interrupt */
-#define CAN_MSR_TXM_Pos                      (8U)                              
-#define CAN_MSR_TXM_Msk                      (0x1U << CAN_MSR_TXM_Pos)         /*!< 0x00000100 */
-#define CAN_MSR_TXM                          CAN_MSR_TXM_Msk                   /*!< Transmit Mode */
-#define CAN_MSR_RXM_Pos                      (9U)                              
-#define CAN_MSR_RXM_Msk                      (0x1U << CAN_MSR_RXM_Pos)         /*!< 0x00000200 */
-#define CAN_MSR_RXM                          CAN_MSR_RXM_Msk                   /*!< Receive Mode */
-#define CAN_MSR_SAMP_Pos                     (10U)                             
-#define CAN_MSR_SAMP_Msk                     (0x1U << CAN_MSR_SAMP_Pos)        /*!< 0x00000400 */
-#define CAN_MSR_SAMP                         CAN_MSR_SAMP_Msk                  /*!< Last Sample Point */
-#define CAN_MSR_RX_Pos                       (11U)                             
-#define CAN_MSR_RX_Msk                       (0x1U << CAN_MSR_RX_Pos)          /*!< 0x00000800 */
-#define CAN_MSR_RX                           CAN_MSR_RX_Msk                    /*!< CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define CAN_TSR_RQCP0_Pos                    (0U)                              
-#define CAN_TSR_RQCP0_Msk                    (0x1U << CAN_TSR_RQCP0_Pos)       /*!< 0x00000001 */
-#define CAN_TSR_RQCP0                        CAN_TSR_RQCP0_Msk                 /*!< Request Completed Mailbox0 */
-#define CAN_TSR_TXOK0_Pos                    (1U)                              
-#define CAN_TSR_TXOK0_Msk                    (0x1U << CAN_TSR_TXOK0_Pos)       /*!< 0x00000002 */
-#define CAN_TSR_TXOK0                        CAN_TSR_TXOK0_Msk                 /*!< Transmission OK of Mailbox0 */
-#define CAN_TSR_ALST0_Pos                    (2U)                              
-#define CAN_TSR_ALST0_Msk                    (0x1U << CAN_TSR_ALST0_Pos)       /*!< 0x00000004 */
-#define CAN_TSR_ALST0                        CAN_TSR_ALST0_Msk                 /*!< Arbitration Lost for Mailbox0 */
-#define CAN_TSR_TERR0_Pos                    (3U)                              
-#define CAN_TSR_TERR0_Msk                    (0x1U << CAN_TSR_TERR0_Pos)       /*!< 0x00000008 */
-#define CAN_TSR_TERR0                        CAN_TSR_TERR0_Msk                 /*!< Transmission Error of Mailbox0 */
-#define CAN_TSR_ABRQ0_Pos                    (7U)                              
-#define CAN_TSR_ABRQ0_Msk                    (0x1U << CAN_TSR_ABRQ0_Pos)       /*!< 0x00000080 */
-#define CAN_TSR_ABRQ0                        CAN_TSR_ABRQ0_Msk                 /*!< Abort Request for Mailbox0 */
-#define CAN_TSR_RQCP1_Pos                    (8U)                              
-#define CAN_TSR_RQCP1_Msk                    (0x1U << CAN_TSR_RQCP1_Pos)       /*!< 0x00000100 */
-#define CAN_TSR_RQCP1                        CAN_TSR_RQCP1_Msk                 /*!< Request Completed Mailbox1 */
-#define CAN_TSR_TXOK1_Pos                    (9U)                              
-#define CAN_TSR_TXOK1_Msk                    (0x1U << CAN_TSR_TXOK1_Pos)       /*!< 0x00000200 */
-#define CAN_TSR_TXOK1                        CAN_TSR_TXOK1_Msk                 /*!< Transmission OK of Mailbox1 */
-#define CAN_TSR_ALST1_Pos                    (10U)                             
-#define CAN_TSR_ALST1_Msk                    (0x1U << CAN_TSR_ALST1_Pos)       /*!< 0x00000400 */
-#define CAN_TSR_ALST1                        CAN_TSR_ALST1_Msk                 /*!< Arbitration Lost for Mailbox1 */
-#define CAN_TSR_TERR1_Pos                    (11U)                             
-#define CAN_TSR_TERR1_Msk                    (0x1U << CAN_TSR_TERR1_Pos)       /*!< 0x00000800 */
-#define CAN_TSR_TERR1                        CAN_TSR_TERR1_Msk                 /*!< Transmission Error of Mailbox1 */
-#define CAN_TSR_ABRQ1_Pos                    (15U)                             
-#define CAN_TSR_ABRQ1_Msk                    (0x1U << CAN_TSR_ABRQ1_Pos)       /*!< 0x00008000 */
-#define CAN_TSR_ABRQ1                        CAN_TSR_ABRQ1_Msk                 /*!< Abort Request for Mailbox 1 */
-#define CAN_TSR_RQCP2_Pos                    (16U)                             
-#define CAN_TSR_RQCP2_Msk                    (0x1U << CAN_TSR_RQCP2_Pos)       /*!< 0x00010000 */
-#define CAN_TSR_RQCP2                        CAN_TSR_RQCP2_Msk                 /*!< Request Completed Mailbox2 */
-#define CAN_TSR_TXOK2_Pos                    (17U)                             
-#define CAN_TSR_TXOK2_Msk                    (0x1U << CAN_TSR_TXOK2_Pos)       /*!< 0x00020000 */
-#define CAN_TSR_TXOK2                        CAN_TSR_TXOK2_Msk                 /*!< Transmission OK of Mailbox 2 */
-#define CAN_TSR_ALST2_Pos                    (18U)                             
-#define CAN_TSR_ALST2_Msk                    (0x1U << CAN_TSR_ALST2_Pos)       /*!< 0x00040000 */
-#define CAN_TSR_ALST2                        CAN_TSR_ALST2_Msk                 /*!< Arbitration Lost for mailbox 2 */
-#define CAN_TSR_TERR2_Pos                    (19U)                             
-#define CAN_TSR_TERR2_Msk                    (0x1U << CAN_TSR_TERR2_Pos)       /*!< 0x00080000 */
-#define CAN_TSR_TERR2                        CAN_TSR_TERR2_Msk                 /*!< Transmission Error of Mailbox 2 */
-#define CAN_TSR_ABRQ2_Pos                    (23U)                             
-#define CAN_TSR_ABRQ2_Msk                    (0x1U << CAN_TSR_ABRQ2_Pos)       /*!< 0x00800000 */
-#define CAN_TSR_ABRQ2                        CAN_TSR_ABRQ2_Msk                 /*!< Abort Request for Mailbox 2 */
-#define CAN_TSR_CODE_Pos                     (24U)                             
-#define CAN_TSR_CODE_Msk                     (0x3U << CAN_TSR_CODE_Pos)        /*!< 0x03000000 */
-#define CAN_TSR_CODE                         CAN_TSR_CODE_Msk                  /*!< Mailbox Code */
-
-#define CAN_TSR_TME_Pos                      (26U)                             
-#define CAN_TSR_TME_Msk                      (0x7U << CAN_TSR_TME_Pos)         /*!< 0x1C000000 */
-#define CAN_TSR_TME                          CAN_TSR_TME_Msk                   /*!< TME[2:0] bits */
-#define CAN_TSR_TME0_Pos                     (26U)                             
-#define CAN_TSR_TME0_Msk                     (0x1U << CAN_TSR_TME0_Pos)        /*!< 0x04000000 */
-#define CAN_TSR_TME0                         CAN_TSR_TME0_Msk                  /*!< Transmit Mailbox 0 Empty */
-#define CAN_TSR_TME1_Pos                     (27U)                             
-#define CAN_TSR_TME1_Msk                     (0x1U << CAN_TSR_TME1_Pos)        /*!< 0x08000000 */
-#define CAN_TSR_TME1                         CAN_TSR_TME1_Msk                  /*!< Transmit Mailbox 1 Empty */
-#define CAN_TSR_TME2_Pos                     (28U)                             
-#define CAN_TSR_TME2_Msk                     (0x1U << CAN_TSR_TME2_Pos)        /*!< 0x10000000 */
-#define CAN_TSR_TME2                         CAN_TSR_TME2_Msk                  /*!< Transmit Mailbox 2 Empty */
-
-#define CAN_TSR_LOW_Pos                      (29U)                             
-#define CAN_TSR_LOW_Msk                      (0x7U << CAN_TSR_LOW_Pos)         /*!< 0xE0000000 */
-#define CAN_TSR_LOW                          CAN_TSR_LOW_Msk                   /*!< LOW[2:0] bits */
-#define CAN_TSR_LOW0_Pos                     (29U)                             
-#define CAN_TSR_LOW0_Msk                     (0x1U << CAN_TSR_LOW0_Pos)        /*!< 0x20000000 */
-#define CAN_TSR_LOW0                         CAN_TSR_LOW0_Msk                  /*!< Lowest Priority Flag for Mailbox 0 */
-#define CAN_TSR_LOW1_Pos                     (30U)                             
-#define CAN_TSR_LOW1_Msk                     (0x1U << CAN_TSR_LOW1_Pos)        /*!< 0x40000000 */
-#define CAN_TSR_LOW1                         CAN_TSR_LOW1_Msk                  /*!< Lowest Priority Flag for Mailbox 1 */
-#define CAN_TSR_LOW2_Pos                     (31U)                             
-#define CAN_TSR_LOW2_Msk                     (0x1U << CAN_TSR_LOW2_Pos)        /*!< 0x80000000 */
-#define CAN_TSR_LOW2                         CAN_TSR_LOW2_Msk                  /*!< Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define CAN_RF0R_FMP0_Pos                    (0U)                              
-#define CAN_RF0R_FMP0_Msk                    (0x3U << CAN_RF0R_FMP0_Pos)       /*!< 0x00000003 */
-#define CAN_RF0R_FMP0                        CAN_RF0R_FMP0_Msk                 /*!< FIFO 0 Message Pending */
-#define CAN_RF0R_FULL0_Pos                   (3U)                              
-#define CAN_RF0R_FULL0_Msk                   (0x1U << CAN_RF0R_FULL0_Pos)      /*!< 0x00000008 */
-#define CAN_RF0R_FULL0                       CAN_RF0R_FULL0_Msk                /*!< FIFO 0 Full */
-#define CAN_RF0R_FOVR0_Pos                   (4U)                              
-#define CAN_RF0R_FOVR0_Msk                   (0x1U << CAN_RF0R_FOVR0_Pos)      /*!< 0x00000010 */
-#define CAN_RF0R_FOVR0                       CAN_RF0R_FOVR0_Msk                /*!< FIFO 0 Overrun */
-#define CAN_RF0R_RFOM0_Pos                   (5U)                              
-#define CAN_RF0R_RFOM0_Msk                   (0x1U << CAN_RF0R_RFOM0_Pos)      /*!< 0x00000020 */
-#define CAN_RF0R_RFOM0                       CAN_RF0R_RFOM0_Msk                /*!< Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define CAN_RF1R_FMP1_Pos                    (0U)                              
-#define CAN_RF1R_FMP1_Msk                    (0x3U << CAN_RF1R_FMP1_Pos)       /*!< 0x00000003 */
-#define CAN_RF1R_FMP1                        CAN_RF1R_FMP1_Msk                 /*!< FIFO 1 Message Pending */
-#define CAN_RF1R_FULL1_Pos                   (3U)                              
-#define CAN_RF1R_FULL1_Msk                   (0x1U << CAN_RF1R_FULL1_Pos)      /*!< 0x00000008 */
-#define CAN_RF1R_FULL1                       CAN_RF1R_FULL1_Msk                /*!< FIFO 1 Full */
-#define CAN_RF1R_FOVR1_Pos                   (4U)                              
-#define CAN_RF1R_FOVR1_Msk                   (0x1U << CAN_RF1R_FOVR1_Pos)      /*!< 0x00000010 */
-#define CAN_RF1R_FOVR1                       CAN_RF1R_FOVR1_Msk                /*!< FIFO 1 Overrun */
-#define CAN_RF1R_RFOM1_Pos                   (5U)                              
-#define CAN_RF1R_RFOM1_Msk                   (0x1U << CAN_RF1R_RFOM1_Pos)      /*!< 0x00000020 */
-#define CAN_RF1R_RFOM1                       CAN_RF1R_RFOM1_Msk                /*!< Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define CAN_IER_TMEIE_Pos                    (0U)                              
-#define CAN_IER_TMEIE_Msk                    (0x1U << CAN_IER_TMEIE_Pos)       /*!< 0x00000001 */
-#define CAN_IER_TMEIE                        CAN_IER_TMEIE_Msk                 /*!< Transmit Mailbox Empty Interrupt Enable */
-#define CAN_IER_FMPIE0_Pos                   (1U)                              
-#define CAN_IER_FMPIE0_Msk                   (0x1U << CAN_IER_FMPIE0_Pos)      /*!< 0x00000002 */
-#define CAN_IER_FMPIE0                       CAN_IER_FMPIE0_Msk                /*!< FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE0_Pos                    (2U)                              
-#define CAN_IER_FFIE0_Msk                    (0x1U << CAN_IER_FFIE0_Pos)       /*!< 0x00000004 */
-#define CAN_IER_FFIE0                        CAN_IER_FFIE0_Msk                 /*!< FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE0_Pos                   (3U)                              
-#define CAN_IER_FOVIE0_Msk                   (0x1U << CAN_IER_FOVIE0_Pos)      /*!< 0x00000008 */
-#define CAN_IER_FOVIE0                       CAN_IER_FOVIE0_Msk                /*!< FIFO Overrun Interrupt Enable */
-#define CAN_IER_FMPIE1_Pos                   (4U)                              
-#define CAN_IER_FMPIE1_Msk                   (0x1U << CAN_IER_FMPIE1_Pos)      /*!< 0x00000010 */
-#define CAN_IER_FMPIE1                       CAN_IER_FMPIE1_Msk                /*!< FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE1_Pos                    (5U)                              
-#define CAN_IER_FFIE1_Msk                    (0x1U << CAN_IER_FFIE1_Pos)       /*!< 0x00000020 */
-#define CAN_IER_FFIE1                        CAN_IER_FFIE1_Msk                 /*!< FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE1_Pos                   (6U)                              
-#define CAN_IER_FOVIE1_Msk                   (0x1U << CAN_IER_FOVIE1_Pos)      /*!< 0x00000040 */
-#define CAN_IER_FOVIE1                       CAN_IER_FOVIE1_Msk                /*!< FIFO Overrun Interrupt Enable */
-#define CAN_IER_EWGIE_Pos                    (8U)                              
-#define CAN_IER_EWGIE_Msk                    (0x1U << CAN_IER_EWGIE_Pos)       /*!< 0x00000100 */
-#define CAN_IER_EWGIE                        CAN_IER_EWGIE_Msk                 /*!< Error Warning Interrupt Enable */
-#define CAN_IER_EPVIE_Pos                    (9U)                              
-#define CAN_IER_EPVIE_Msk                    (0x1U << CAN_IER_EPVIE_Pos)       /*!< 0x00000200 */
-#define CAN_IER_EPVIE                        CAN_IER_EPVIE_Msk                 /*!< Error Passive Interrupt Enable */
-#define CAN_IER_BOFIE_Pos                    (10U)                             
-#define CAN_IER_BOFIE_Msk                    (0x1U << CAN_IER_BOFIE_Pos)       /*!< 0x00000400 */
-#define CAN_IER_BOFIE                        CAN_IER_BOFIE_Msk                 /*!< Bus-Off Interrupt Enable */
-#define CAN_IER_LECIE_Pos                    (11U)                             
-#define CAN_IER_LECIE_Msk                    (0x1U << CAN_IER_LECIE_Pos)       /*!< 0x00000800 */
-#define CAN_IER_LECIE                        CAN_IER_LECIE_Msk                 /*!< Last Error Code Interrupt Enable */
-#define CAN_IER_ERRIE_Pos                    (15U)                             
-#define CAN_IER_ERRIE_Msk                    (0x1U << CAN_IER_ERRIE_Pos)       /*!< 0x00008000 */
-#define CAN_IER_ERRIE                        CAN_IER_ERRIE_Msk                 /*!< Error Interrupt Enable */
-#define CAN_IER_WKUIE_Pos                    (16U)                             
-#define CAN_IER_WKUIE_Msk                    (0x1U << CAN_IER_WKUIE_Pos)       /*!< 0x00010000 */
-#define CAN_IER_WKUIE                        CAN_IER_WKUIE_Msk                 /*!< Wakeup Interrupt Enable */
-#define CAN_IER_SLKIE_Pos                    (17U)                             
-#define CAN_IER_SLKIE_Msk                    (0x1U << CAN_IER_SLKIE_Pos)       /*!< 0x00020000 */
-#define CAN_IER_SLKIE                        CAN_IER_SLKIE_Msk                 /*!< Sleep Interrupt Enable */
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define CAN_ESR_EWGF_Pos                     (0U)                              
-#define CAN_ESR_EWGF_Msk                     (0x1U << CAN_ESR_EWGF_Pos)        /*!< 0x00000001 */
-#define CAN_ESR_EWGF                         CAN_ESR_EWGF_Msk                  /*!< Error Warning Flag */
-#define CAN_ESR_EPVF_Pos                     (1U)                              
-#define CAN_ESR_EPVF_Msk                     (0x1U << CAN_ESR_EPVF_Pos)        /*!< 0x00000002 */
-#define CAN_ESR_EPVF                         CAN_ESR_EPVF_Msk                  /*!< Error Passive Flag */
-#define CAN_ESR_BOFF_Pos                     (2U)                              
-#define CAN_ESR_BOFF_Msk                     (0x1U << CAN_ESR_BOFF_Pos)        /*!< 0x00000004 */
-#define CAN_ESR_BOFF                         CAN_ESR_BOFF_Msk                  /*!< Bus-Off Flag */
-
-#define CAN_ESR_LEC_Pos                      (4U)                              
-#define CAN_ESR_LEC_Msk                      (0x7U << CAN_ESR_LEC_Pos)         /*!< 0x00000070 */
-#define CAN_ESR_LEC                          CAN_ESR_LEC_Msk                   /*!< LEC[2:0] bits (Last Error Code) */
-#define CAN_ESR_LEC_0                        (0x1U << CAN_ESR_LEC_Pos)         /*!< 0x00000010 */
-#define CAN_ESR_LEC_1                        (0x2U << CAN_ESR_LEC_Pos)         /*!< 0x00000020 */
-#define CAN_ESR_LEC_2                        (0x4U << CAN_ESR_LEC_Pos)         /*!< 0x00000040 */
-
-#define CAN_ESR_TEC_Pos                      (16U)                             
-#define CAN_ESR_TEC_Msk                      (0xFFU << CAN_ESR_TEC_Pos)        /*!< 0x00FF0000 */
-#define CAN_ESR_TEC                          CAN_ESR_TEC_Msk                   /*!< Least significant byte of the 9-bit Transmit Error Counter */
-#define CAN_ESR_REC_Pos                      (24U)                             
-#define CAN_ESR_REC_Msk                      (0xFFU << CAN_ESR_REC_Pos)        /*!< 0xFF000000 */
-#define CAN_ESR_REC                          CAN_ESR_REC_Msk                   /*!< Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define CAN_BTR_BRP_Pos                      (0U)                              
-#define CAN_BTR_BRP_Msk                      (0x3FFU << CAN_BTR_BRP_Pos)       /*!< 0x000003FF */
-#define CAN_BTR_BRP                          CAN_BTR_BRP_Msk                   /*!<Baud Rate Prescaler */
-#define CAN_BTR_TS1_Pos                      (16U)                             
-#define CAN_BTR_TS1_Msk                      (0xFU << CAN_BTR_TS1_Pos)         /*!< 0x000F0000 */
-#define CAN_BTR_TS1                          CAN_BTR_TS1_Msk                   /*!<Time Segment 1 */
-#define CAN_BTR_TS1_0                        (0x1U << CAN_BTR_TS1_Pos)         /*!< 0x00010000 */
-#define CAN_BTR_TS1_1                        (0x2U << CAN_BTR_TS1_Pos)         /*!< 0x00020000 */
-#define CAN_BTR_TS1_2                        (0x4U << CAN_BTR_TS1_Pos)         /*!< 0x00040000 */
-#define CAN_BTR_TS1_3                        (0x8U << CAN_BTR_TS1_Pos)         /*!< 0x00080000 */
-#define CAN_BTR_TS2_Pos                      (20U)                             
-#define CAN_BTR_TS2_Msk                      (0x7U << CAN_BTR_TS2_Pos)         /*!< 0x00700000 */
-#define CAN_BTR_TS2                          CAN_BTR_TS2_Msk                   /*!<Time Segment 2 */
-#define CAN_BTR_TS2_0                        (0x1U << CAN_BTR_TS2_Pos)         /*!< 0x00100000 */
-#define CAN_BTR_TS2_1                        (0x2U << CAN_BTR_TS2_Pos)         /*!< 0x00200000 */
-#define CAN_BTR_TS2_2                        (0x4U << CAN_BTR_TS2_Pos)         /*!< 0x00400000 */
-#define CAN_BTR_SJW_Pos                      (24U)                             
-#define CAN_BTR_SJW_Msk                      (0x3U << CAN_BTR_SJW_Pos)         /*!< 0x03000000 */
-#define CAN_BTR_SJW                          CAN_BTR_SJW_Msk                   /*!<Resynchronization Jump Width */
-#define CAN_BTR_SJW_0                        (0x1U << CAN_BTR_SJW_Pos)         /*!< 0x01000000 */
-#define CAN_BTR_SJW_1                        (0x2U << CAN_BTR_SJW_Pos)         /*!< 0x02000000 */
-#define CAN_BTR_LBKM_Pos                     (30U)                             
-#define CAN_BTR_LBKM_Msk                     (0x1U << CAN_BTR_LBKM_Pos)        /*!< 0x40000000 */
-#define CAN_BTR_LBKM                         CAN_BTR_LBKM_Msk                  /*!<Loop Back Mode (Debug) */
-#define CAN_BTR_SILM_Pos                     (31U)                             
-#define CAN_BTR_SILM_Msk                     (0x1U << CAN_BTR_SILM_Pos)        /*!< 0x80000000 */
-#define CAN_BTR_SILM                         CAN_BTR_SILM_Msk                  /*!<Silent Mode */
-
-/*!< Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define CAN_TI0R_TXRQ_Pos                    (0U)                              
-#define CAN_TI0R_TXRQ_Msk                    (0x1U << CAN_TI0R_TXRQ_Pos)       /*!< 0x00000001 */
-#define CAN_TI0R_TXRQ                        CAN_TI0R_TXRQ_Msk                 /*!< Transmit Mailbox Request */
-#define CAN_TI0R_RTR_Pos                     (1U)                              
-#define CAN_TI0R_RTR_Msk                     (0x1U << CAN_TI0R_RTR_Pos)        /*!< 0x00000002 */
-#define CAN_TI0R_RTR                         CAN_TI0R_RTR_Msk                  /*!< Remote Transmission Request */
-#define CAN_TI0R_IDE_Pos                     (2U)                              
-#define CAN_TI0R_IDE_Msk                     (0x1U << CAN_TI0R_IDE_Pos)        /*!< 0x00000004 */
-#define CAN_TI0R_IDE                         CAN_TI0R_IDE_Msk                  /*!< Identifier Extension */
-#define CAN_TI0R_EXID_Pos                    (3U)                              
-#define CAN_TI0R_EXID_Msk                    (0x3FFFFU << CAN_TI0R_EXID_Pos)   /*!< 0x001FFFF8 */
-#define CAN_TI0R_EXID                        CAN_TI0R_EXID_Msk                 /*!< Extended Identifier */
-#define CAN_TI0R_STID_Pos                    (21U)                             
-#define CAN_TI0R_STID_Msk                    (0x7FFU << CAN_TI0R_STID_Pos)     /*!< 0xFFE00000 */
-#define CAN_TI0R_STID                        CAN_TI0R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define CAN_TDT0R_DLC_Pos                    (0U)                              
-#define CAN_TDT0R_DLC_Msk                    (0xFU << CAN_TDT0R_DLC_Pos)       /*!< 0x0000000F */
-#define CAN_TDT0R_DLC                        CAN_TDT0R_DLC_Msk                 /*!< Data Length Code */
-#define CAN_TDT0R_TGT_Pos                    (8U)                              
-#define CAN_TDT0R_TGT_Msk                    (0x1U << CAN_TDT0R_TGT_Pos)       /*!< 0x00000100 */
-#define CAN_TDT0R_TGT                        CAN_TDT0R_TGT_Msk                 /*!< Transmit Global Time */
-#define CAN_TDT0R_TIME_Pos                   (16U)                             
-#define CAN_TDT0R_TIME_Msk                   (0xFFFFU << CAN_TDT0R_TIME_Pos)   /*!< 0xFFFF0000 */
-#define CAN_TDT0R_TIME                       CAN_TDT0R_TIME_Msk                /*!< Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define CAN_TDL0R_DATA0_Pos                  (0U)                              
-#define CAN_TDL0R_DATA0_Msk                  (0xFFU << CAN_TDL0R_DATA0_Pos)    /*!< 0x000000FF */
-#define CAN_TDL0R_DATA0                      CAN_TDL0R_DATA0_Msk               /*!< Data byte 0 */
-#define CAN_TDL0R_DATA1_Pos                  (8U)                              
-#define CAN_TDL0R_DATA1_Msk                  (0xFFU << CAN_TDL0R_DATA1_Pos)    /*!< 0x0000FF00 */
-#define CAN_TDL0R_DATA1                      CAN_TDL0R_DATA1_Msk               /*!< Data byte 1 */
-#define CAN_TDL0R_DATA2_Pos                  (16U)                             
-#define CAN_TDL0R_DATA2_Msk                  (0xFFU << CAN_TDL0R_DATA2_Pos)    /*!< 0x00FF0000 */
-#define CAN_TDL0R_DATA2                      CAN_TDL0R_DATA2_Msk               /*!< Data byte 2 */
-#define CAN_TDL0R_DATA3_Pos                  (24U)                             
-#define CAN_TDL0R_DATA3_Msk                  (0xFFU << CAN_TDL0R_DATA3_Pos)    /*!< 0xFF000000 */
-#define CAN_TDL0R_DATA3                      CAN_TDL0R_DATA3_Msk               /*!< Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define CAN_TDH0R_DATA4_Pos                  (0U)                              
-#define CAN_TDH0R_DATA4_Msk                  (0xFFU << CAN_TDH0R_DATA4_Pos)    /*!< 0x000000FF */
-#define CAN_TDH0R_DATA4                      CAN_TDH0R_DATA4_Msk               /*!< Data byte 4 */
-#define CAN_TDH0R_DATA5_Pos                  (8U)                              
-#define CAN_TDH0R_DATA5_Msk                  (0xFFU << CAN_TDH0R_DATA5_Pos)    /*!< 0x0000FF00 */
-#define CAN_TDH0R_DATA5                      CAN_TDH0R_DATA5_Msk               /*!< Data byte 5 */
-#define CAN_TDH0R_DATA6_Pos                  (16U)                             
-#define CAN_TDH0R_DATA6_Msk                  (0xFFU << CAN_TDH0R_DATA6_Pos)    /*!< 0x00FF0000 */
-#define CAN_TDH0R_DATA6                      CAN_TDH0R_DATA6_Msk               /*!< Data byte 6 */
-#define CAN_TDH0R_DATA7_Pos                  (24U)                             
-#define CAN_TDH0R_DATA7_Msk                  (0xFFU << CAN_TDH0R_DATA7_Pos)    /*!< 0xFF000000 */
-#define CAN_TDH0R_DATA7                      CAN_TDH0R_DATA7_Msk               /*!< Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define CAN_TI1R_TXRQ_Pos                    (0U)                              
-#define CAN_TI1R_TXRQ_Msk                    (0x1U << CAN_TI1R_TXRQ_Pos)       /*!< 0x00000001 */
-#define CAN_TI1R_TXRQ                        CAN_TI1R_TXRQ_Msk                 /*!< Transmit Mailbox Request */
-#define CAN_TI1R_RTR_Pos                     (1U)                              
-#define CAN_TI1R_RTR_Msk                     (0x1U << CAN_TI1R_RTR_Pos)        /*!< 0x00000002 */
-#define CAN_TI1R_RTR                         CAN_TI1R_RTR_Msk                  /*!< Remote Transmission Request */
-#define CAN_TI1R_IDE_Pos                     (2U)                              
-#define CAN_TI1R_IDE_Msk                     (0x1U << CAN_TI1R_IDE_Pos)        /*!< 0x00000004 */
-#define CAN_TI1R_IDE                         CAN_TI1R_IDE_Msk                  /*!< Identifier Extension */
-#define CAN_TI1R_EXID_Pos                    (3U)                              
-#define CAN_TI1R_EXID_Msk                    (0x3FFFFU << CAN_TI1R_EXID_Pos)   /*!< 0x001FFFF8 */
-#define CAN_TI1R_EXID                        CAN_TI1R_EXID_Msk                 /*!< Extended Identifier */
-#define CAN_TI1R_STID_Pos                    (21U)                             
-#define CAN_TI1R_STID_Msk                    (0x7FFU << CAN_TI1R_STID_Pos)     /*!< 0xFFE00000 */
-#define CAN_TI1R_STID                        CAN_TI1R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define CAN_TDT1R_DLC_Pos                    (0U)                              
-#define CAN_TDT1R_DLC_Msk                    (0xFU << CAN_TDT1R_DLC_Pos)       /*!< 0x0000000F */
-#define CAN_TDT1R_DLC                        CAN_TDT1R_DLC_Msk                 /*!< Data Length Code */
-#define CAN_TDT1R_TGT_Pos                    (8U)                              
-#define CAN_TDT1R_TGT_Msk                    (0x1U << CAN_TDT1R_TGT_Pos)       /*!< 0x00000100 */
-#define CAN_TDT1R_TGT                        CAN_TDT1R_TGT_Msk                 /*!< Transmit Global Time */
-#define CAN_TDT1R_TIME_Pos                   (16U)                             
-#define CAN_TDT1R_TIME_Msk                   (0xFFFFU << CAN_TDT1R_TIME_Pos)   /*!< 0xFFFF0000 */
-#define CAN_TDT1R_TIME                       CAN_TDT1R_TIME_Msk                /*!< Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define CAN_TDL1R_DATA0_Pos                  (0U)                              
-#define CAN_TDL1R_DATA0_Msk                  (0xFFU << CAN_TDL1R_DATA0_Pos)    /*!< 0x000000FF */
-#define CAN_TDL1R_DATA0                      CAN_TDL1R_DATA0_Msk               /*!< Data byte 0 */
-#define CAN_TDL1R_DATA1_Pos                  (8U)                              
-#define CAN_TDL1R_DATA1_Msk                  (0xFFU << CAN_TDL1R_DATA1_Pos)    /*!< 0x0000FF00 */
-#define CAN_TDL1R_DATA1                      CAN_TDL1R_DATA1_Msk               /*!< Data byte 1 */
-#define CAN_TDL1R_DATA2_Pos                  (16U)                             
-#define CAN_TDL1R_DATA2_Msk                  (0xFFU << CAN_TDL1R_DATA2_Pos)    /*!< 0x00FF0000 */
-#define CAN_TDL1R_DATA2                      CAN_TDL1R_DATA2_Msk               /*!< Data byte 2 */
-#define CAN_TDL1R_DATA3_Pos                  (24U)                             
-#define CAN_TDL1R_DATA3_Msk                  (0xFFU << CAN_TDL1R_DATA3_Pos)    /*!< 0xFF000000 */
-#define CAN_TDL1R_DATA3                      CAN_TDL1R_DATA3_Msk               /*!< Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define CAN_TDH1R_DATA4_Pos                  (0U)                              
-#define CAN_TDH1R_DATA4_Msk                  (0xFFU << CAN_TDH1R_DATA4_Pos)    /*!< 0x000000FF */
-#define CAN_TDH1R_DATA4                      CAN_TDH1R_DATA4_Msk               /*!< Data byte 4 */
-#define CAN_TDH1R_DATA5_Pos                  (8U)                              
-#define CAN_TDH1R_DATA5_Msk                  (0xFFU << CAN_TDH1R_DATA5_Pos)    /*!< 0x0000FF00 */
-#define CAN_TDH1R_DATA5                      CAN_TDH1R_DATA5_Msk               /*!< Data byte 5 */
-#define CAN_TDH1R_DATA6_Pos                  (16U)                             
-#define CAN_TDH1R_DATA6_Msk                  (0xFFU << CAN_TDH1R_DATA6_Pos)    /*!< 0x00FF0000 */
-#define CAN_TDH1R_DATA6                      CAN_TDH1R_DATA6_Msk               /*!< Data byte 6 */
-#define CAN_TDH1R_DATA7_Pos                  (24U)                             
-#define CAN_TDH1R_DATA7_Msk                  (0xFFU << CAN_TDH1R_DATA7_Pos)    /*!< 0xFF000000 */
-#define CAN_TDH1R_DATA7                      CAN_TDH1R_DATA7_Msk               /*!< Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define CAN_TI2R_TXRQ_Pos                    (0U)                              
-#define CAN_TI2R_TXRQ_Msk                    (0x1U << CAN_TI2R_TXRQ_Pos)       /*!< 0x00000001 */
-#define CAN_TI2R_TXRQ                        CAN_TI2R_TXRQ_Msk                 /*!< Transmit Mailbox Request */
-#define CAN_TI2R_RTR_Pos                     (1U)                              
-#define CAN_TI2R_RTR_Msk                     (0x1U << CAN_TI2R_RTR_Pos)        /*!< 0x00000002 */
-#define CAN_TI2R_RTR                         CAN_TI2R_RTR_Msk                  /*!< Remote Transmission Request */
-#define CAN_TI2R_IDE_Pos                     (2U)                              
-#define CAN_TI2R_IDE_Msk                     (0x1U << CAN_TI2R_IDE_Pos)        /*!< 0x00000004 */
-#define CAN_TI2R_IDE                         CAN_TI2R_IDE_Msk                  /*!< Identifier Extension */
-#define CAN_TI2R_EXID_Pos                    (3U)                              
-#define CAN_TI2R_EXID_Msk                    (0x3FFFFU << CAN_TI2R_EXID_Pos)   /*!< 0x001FFFF8 */
-#define CAN_TI2R_EXID                        CAN_TI2R_EXID_Msk                 /*!< Extended identifier */
-#define CAN_TI2R_STID_Pos                    (21U)                             
-#define CAN_TI2R_STID_Msk                    (0x7FFU << CAN_TI2R_STID_Pos)     /*!< 0xFFE00000 */
-#define CAN_TI2R_STID                        CAN_TI2R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define CAN_TDT2R_DLC_Pos                    (0U)                              
-#define CAN_TDT2R_DLC_Msk                    (0xFU << CAN_TDT2R_DLC_Pos)       /*!< 0x0000000F */
-#define CAN_TDT2R_DLC                        CAN_TDT2R_DLC_Msk                 /*!< Data Length Code */
-#define CAN_TDT2R_TGT_Pos                    (8U)                              
-#define CAN_TDT2R_TGT_Msk                    (0x1U << CAN_TDT2R_TGT_Pos)       /*!< 0x00000100 */
-#define CAN_TDT2R_TGT                        CAN_TDT2R_TGT_Msk                 /*!< Transmit Global Time */
-#define CAN_TDT2R_TIME_Pos                   (16U)                             
-#define CAN_TDT2R_TIME_Msk                   (0xFFFFU << CAN_TDT2R_TIME_Pos)   /*!< 0xFFFF0000 */
-#define CAN_TDT2R_TIME                       CAN_TDT2R_TIME_Msk                /*!< Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define CAN_TDL2R_DATA0_Pos                  (0U)                              
-#define CAN_TDL2R_DATA0_Msk                  (0xFFU << CAN_TDL2R_DATA0_Pos)    /*!< 0x000000FF */
-#define CAN_TDL2R_DATA0                      CAN_TDL2R_DATA0_Msk               /*!< Data byte 0 */
-#define CAN_TDL2R_DATA1_Pos                  (8U)                              
-#define CAN_TDL2R_DATA1_Msk                  (0xFFU << CAN_TDL2R_DATA1_Pos)    /*!< 0x0000FF00 */
-#define CAN_TDL2R_DATA1                      CAN_TDL2R_DATA1_Msk               /*!< Data byte 1 */
-#define CAN_TDL2R_DATA2_Pos                  (16U)                             
-#define CAN_TDL2R_DATA2_Msk                  (0xFFU << CAN_TDL2R_DATA2_Pos)    /*!< 0x00FF0000 */
-#define CAN_TDL2R_DATA2                      CAN_TDL2R_DATA2_Msk               /*!< Data byte 2 */
-#define CAN_TDL2R_DATA3_Pos                  (24U)                             
-#define CAN_TDL2R_DATA3_Msk                  (0xFFU << CAN_TDL2R_DATA3_Pos)    /*!< 0xFF000000 */
-#define CAN_TDL2R_DATA3                      CAN_TDL2R_DATA3_Msk               /*!< Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define CAN_TDH2R_DATA4_Pos                  (0U)                              
-#define CAN_TDH2R_DATA4_Msk                  (0xFFU << CAN_TDH2R_DATA4_Pos)    /*!< 0x000000FF */
-#define CAN_TDH2R_DATA4                      CAN_TDH2R_DATA4_Msk               /*!< Data byte 4 */
-#define CAN_TDH2R_DATA5_Pos                  (8U)                              
-#define CAN_TDH2R_DATA5_Msk                  (0xFFU << CAN_TDH2R_DATA5_Pos)    /*!< 0x0000FF00 */
-#define CAN_TDH2R_DATA5                      CAN_TDH2R_DATA5_Msk               /*!< Data byte 5 */
-#define CAN_TDH2R_DATA6_Pos                  (16U)                             
-#define CAN_TDH2R_DATA6_Msk                  (0xFFU << CAN_TDH2R_DATA6_Pos)    /*!< 0x00FF0000 */
-#define CAN_TDH2R_DATA6                      CAN_TDH2R_DATA6_Msk               /*!< Data byte 6 */
-#define CAN_TDH2R_DATA7_Pos                  (24U)                             
-#define CAN_TDH2R_DATA7_Msk                  (0xFFU << CAN_TDH2R_DATA7_Pos)    /*!< 0xFF000000 */
-#define CAN_TDH2R_DATA7                      CAN_TDH2R_DATA7_Msk               /*!< Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define CAN_RI0R_RTR_Pos                     (1U)                              
-#define CAN_RI0R_RTR_Msk                     (0x1U << CAN_RI0R_RTR_Pos)        /*!< 0x00000002 */
-#define CAN_RI0R_RTR                         CAN_RI0R_RTR_Msk                  /*!< Remote Transmission Request */
-#define CAN_RI0R_IDE_Pos                     (2U)                              
-#define CAN_RI0R_IDE_Msk                     (0x1U << CAN_RI0R_IDE_Pos)        /*!< 0x00000004 */
-#define CAN_RI0R_IDE                         CAN_RI0R_IDE_Msk                  /*!< Identifier Extension */
-#define CAN_RI0R_EXID_Pos                    (3U)                              
-#define CAN_RI0R_EXID_Msk                    (0x3FFFFU << CAN_RI0R_EXID_Pos)   /*!< 0x001FFFF8 */
-#define CAN_RI0R_EXID                        CAN_RI0R_EXID_Msk                 /*!< Extended Identifier */
-#define CAN_RI0R_STID_Pos                    (21U)                             
-#define CAN_RI0R_STID_Msk                    (0x7FFU << CAN_RI0R_STID_Pos)     /*!< 0xFFE00000 */
-#define CAN_RI0R_STID                        CAN_RI0R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define CAN_RDT0R_DLC_Pos                    (0U)                              
-#define CAN_RDT0R_DLC_Msk                    (0xFU << CAN_RDT0R_DLC_Pos)       /*!< 0x0000000F */
-#define CAN_RDT0R_DLC                        CAN_RDT0R_DLC_Msk                 /*!< Data Length Code */
-#define CAN_RDT0R_FMI_Pos                    (8U)                              
-#define CAN_RDT0R_FMI_Msk                    (0xFFU << CAN_RDT0R_FMI_Pos)      /*!< 0x0000FF00 */
-#define CAN_RDT0R_FMI                        CAN_RDT0R_FMI_Msk                 /*!< Filter Match Index */
-#define CAN_RDT0R_TIME_Pos                   (16U)                             
-#define CAN_RDT0R_TIME_Msk                   (0xFFFFU << CAN_RDT0R_TIME_Pos)   /*!< 0xFFFF0000 */
-#define CAN_RDT0R_TIME                       CAN_RDT0R_TIME_Msk                /*!< Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define CAN_RDL0R_DATA0_Pos                  (0U)                              
-#define CAN_RDL0R_DATA0_Msk                  (0xFFU << CAN_RDL0R_DATA0_Pos)    /*!< 0x000000FF */
-#define CAN_RDL0R_DATA0                      CAN_RDL0R_DATA0_Msk               /*!< Data byte 0 */
-#define CAN_RDL0R_DATA1_Pos                  (8U)                              
-#define CAN_RDL0R_DATA1_Msk                  (0xFFU << CAN_RDL0R_DATA1_Pos)    /*!< 0x0000FF00 */
-#define CAN_RDL0R_DATA1                      CAN_RDL0R_DATA1_Msk               /*!< Data byte 1 */
-#define CAN_RDL0R_DATA2_Pos                  (16U)                             
-#define CAN_RDL0R_DATA2_Msk                  (0xFFU << CAN_RDL0R_DATA2_Pos)    /*!< 0x00FF0000 */
-#define CAN_RDL0R_DATA2                      CAN_RDL0R_DATA2_Msk               /*!< Data byte 2 */
-#define CAN_RDL0R_DATA3_Pos                  (24U)                             
-#define CAN_RDL0R_DATA3_Msk                  (0xFFU << CAN_RDL0R_DATA3_Pos)    /*!< 0xFF000000 */
-#define CAN_RDL0R_DATA3                      CAN_RDL0R_DATA3_Msk               /*!< Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define CAN_RDH0R_DATA4_Pos                  (0U)                              
-#define CAN_RDH0R_DATA4_Msk                  (0xFFU << CAN_RDH0R_DATA4_Pos)    /*!< 0x000000FF */
-#define CAN_RDH0R_DATA4                      CAN_RDH0R_DATA4_Msk               /*!< Data byte 4 */
-#define CAN_RDH0R_DATA5_Pos                  (8U)                              
-#define CAN_RDH0R_DATA5_Msk                  (0xFFU << CAN_RDH0R_DATA5_Pos)    /*!< 0x0000FF00 */
-#define CAN_RDH0R_DATA5                      CAN_RDH0R_DATA5_Msk               /*!< Data byte 5 */
-#define CAN_RDH0R_DATA6_Pos                  (16U)                             
-#define CAN_RDH0R_DATA6_Msk                  (0xFFU << CAN_RDH0R_DATA6_Pos)    /*!< 0x00FF0000 */
-#define CAN_RDH0R_DATA6                      CAN_RDH0R_DATA6_Msk               /*!< Data byte 6 */
-#define CAN_RDH0R_DATA7_Pos                  (24U)                             
-#define CAN_RDH0R_DATA7_Msk                  (0xFFU << CAN_RDH0R_DATA7_Pos)    /*!< 0xFF000000 */
-#define CAN_RDH0R_DATA7                      CAN_RDH0R_DATA7_Msk               /*!< Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define CAN_RI1R_RTR_Pos                     (1U)                              
-#define CAN_RI1R_RTR_Msk                     (0x1U << CAN_RI1R_RTR_Pos)        /*!< 0x00000002 */
-#define CAN_RI1R_RTR                         CAN_RI1R_RTR_Msk                  /*!< Remote Transmission Request */
-#define CAN_RI1R_IDE_Pos                     (2U)                              
-#define CAN_RI1R_IDE_Msk                     (0x1U << CAN_RI1R_IDE_Pos)        /*!< 0x00000004 */
-#define CAN_RI1R_IDE                         CAN_RI1R_IDE_Msk                  /*!< Identifier Extension */
-#define CAN_RI1R_EXID_Pos                    (3U)                              
-#define CAN_RI1R_EXID_Msk                    (0x3FFFFU << CAN_RI1R_EXID_Pos)   /*!< 0x001FFFF8 */
-#define CAN_RI1R_EXID                        CAN_RI1R_EXID_Msk                 /*!< Extended identifier */
-#define CAN_RI1R_STID_Pos                    (21U)                             
-#define CAN_RI1R_STID_Msk                    (0x7FFU << CAN_RI1R_STID_Pos)     /*!< 0xFFE00000 */
-#define CAN_RI1R_STID                        CAN_RI1R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define CAN_RDT1R_DLC_Pos                    (0U)                              
-#define CAN_RDT1R_DLC_Msk                    (0xFU << CAN_RDT1R_DLC_Pos)       /*!< 0x0000000F */
-#define CAN_RDT1R_DLC                        CAN_RDT1R_DLC_Msk                 /*!< Data Length Code */
-#define CAN_RDT1R_FMI_Pos                    (8U)                              
-#define CAN_RDT1R_FMI_Msk                    (0xFFU << CAN_RDT1R_FMI_Pos)      /*!< 0x0000FF00 */
-#define CAN_RDT1R_FMI                        CAN_RDT1R_FMI_Msk                 /*!< Filter Match Index */
-#define CAN_RDT1R_TIME_Pos                   (16U)                             
-#define CAN_RDT1R_TIME_Msk                   (0xFFFFU << CAN_RDT1R_TIME_Pos)   /*!< 0xFFFF0000 */
-#define CAN_RDT1R_TIME                       CAN_RDT1R_TIME_Msk                /*!< Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define CAN_RDL1R_DATA0_Pos                  (0U)                              
-#define CAN_RDL1R_DATA0_Msk                  (0xFFU << CAN_RDL1R_DATA0_Pos)    /*!< 0x000000FF */
-#define CAN_RDL1R_DATA0                      CAN_RDL1R_DATA0_Msk               /*!< Data byte 0 */
-#define CAN_RDL1R_DATA1_Pos                  (8U)                              
-#define CAN_RDL1R_DATA1_Msk                  (0xFFU << CAN_RDL1R_DATA1_Pos)    /*!< 0x0000FF00 */
-#define CAN_RDL1R_DATA1                      CAN_RDL1R_DATA1_Msk               /*!< Data byte 1 */
-#define CAN_RDL1R_DATA2_Pos                  (16U)                             
-#define CAN_RDL1R_DATA2_Msk                  (0xFFU << CAN_RDL1R_DATA2_Pos)    /*!< 0x00FF0000 */
-#define CAN_RDL1R_DATA2                      CAN_RDL1R_DATA2_Msk               /*!< Data byte 2 */
-#define CAN_RDL1R_DATA3_Pos                  (24U)                             
-#define CAN_RDL1R_DATA3_Msk                  (0xFFU << CAN_RDL1R_DATA3_Pos)    /*!< 0xFF000000 */
-#define CAN_RDL1R_DATA3                      CAN_RDL1R_DATA3_Msk               /*!< Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define CAN_RDH1R_DATA4_Pos                  (0U)                              
-#define CAN_RDH1R_DATA4_Msk                  (0xFFU << CAN_RDH1R_DATA4_Pos)    /*!< 0x000000FF */
-#define CAN_RDH1R_DATA4                      CAN_RDH1R_DATA4_Msk               /*!< Data byte 4 */
-#define CAN_RDH1R_DATA5_Pos                  (8U)                              
-#define CAN_RDH1R_DATA5_Msk                  (0xFFU << CAN_RDH1R_DATA5_Pos)    /*!< 0x0000FF00 */
-#define CAN_RDH1R_DATA5                      CAN_RDH1R_DATA5_Msk               /*!< Data byte 5 */
-#define CAN_RDH1R_DATA6_Pos                  (16U)                             
-#define CAN_RDH1R_DATA6_Msk                  (0xFFU << CAN_RDH1R_DATA6_Pos)    /*!< 0x00FF0000 */
-#define CAN_RDH1R_DATA6                      CAN_RDH1R_DATA6_Msk               /*!< Data byte 6 */
-#define CAN_RDH1R_DATA7_Pos                  (24U)                             
-#define CAN_RDH1R_DATA7_Msk                  (0xFFU << CAN_RDH1R_DATA7_Pos)    /*!< 0xFF000000 */
-#define CAN_RDH1R_DATA7                      CAN_RDH1R_DATA7_Msk               /*!< Data byte 7 */
-
-/*!< CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define CAN_FMR_FINIT_Pos                    (0U)                              
-#define CAN_FMR_FINIT_Msk                    (0x1U << CAN_FMR_FINIT_Pos)       /*!< 0x00000001 */
-#define CAN_FMR_FINIT                        CAN_FMR_FINIT_Msk                 /*!< Filter Init Mode */
-#define CAN_FMR_CAN2SB_Pos                   (8U)                              
-#define CAN_FMR_CAN2SB_Msk                   (0x3FU << CAN_FMR_CAN2SB_Pos)     /*!< 0x00003F00 */
-#define CAN_FMR_CAN2SB                       CAN_FMR_CAN2SB_Msk                /*!< CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define CAN_FM1R_FBM_Pos                     (0U)                              
-#define CAN_FM1R_FBM_Msk                     (0x3FFFU << CAN_FM1R_FBM_Pos)     /*!< 0x00003FFF */
-#define CAN_FM1R_FBM                         CAN_FM1R_FBM_Msk                  /*!< Filter Mode */
-#define CAN_FM1R_FBM0_Pos                    (0U)                              
-#define CAN_FM1R_FBM0_Msk                    (0x1U << CAN_FM1R_FBM0_Pos)       /*!< 0x00000001 */
-#define CAN_FM1R_FBM0                        CAN_FM1R_FBM0_Msk                 /*!< Filter Init Mode for filter 0 */
-#define CAN_FM1R_FBM1_Pos                    (1U)                              
-#define CAN_FM1R_FBM1_Msk                    (0x1U << CAN_FM1R_FBM1_Pos)       /*!< 0x00000002 */
-#define CAN_FM1R_FBM1                        CAN_FM1R_FBM1_Msk                 /*!< Filter Init Mode for filter 1 */
-#define CAN_FM1R_FBM2_Pos                    (2U)                              
-#define CAN_FM1R_FBM2_Msk                    (0x1U << CAN_FM1R_FBM2_Pos)       /*!< 0x00000004 */
-#define CAN_FM1R_FBM2                        CAN_FM1R_FBM2_Msk                 /*!< Filter Init Mode for filter 2 */
-#define CAN_FM1R_FBM3_Pos                    (3U)                              
-#define CAN_FM1R_FBM3_Msk                    (0x1U << CAN_FM1R_FBM3_Pos)       /*!< 0x00000008 */
-#define CAN_FM1R_FBM3                        CAN_FM1R_FBM3_Msk                 /*!< Filter Init Mode for filter 3 */
-#define CAN_FM1R_FBM4_Pos                    (4U)                              
-#define CAN_FM1R_FBM4_Msk                    (0x1U << CAN_FM1R_FBM4_Pos)       /*!< 0x00000010 */
-#define CAN_FM1R_FBM4                        CAN_FM1R_FBM4_Msk                 /*!< Filter Init Mode for filter 4 */
-#define CAN_FM1R_FBM5_Pos                    (5U)                              
-#define CAN_FM1R_FBM5_Msk                    (0x1U << CAN_FM1R_FBM5_Pos)       /*!< 0x00000020 */
-#define CAN_FM1R_FBM5                        CAN_FM1R_FBM5_Msk                 /*!< Filter Init Mode for filter 5 */
-#define CAN_FM1R_FBM6_Pos                    (6U)                              
-#define CAN_FM1R_FBM6_Msk                    (0x1U << CAN_FM1R_FBM6_Pos)       /*!< 0x00000040 */
-#define CAN_FM1R_FBM6                        CAN_FM1R_FBM6_Msk                 /*!< Filter Init Mode for filter 6 */
-#define CAN_FM1R_FBM7_Pos                    (7U)                              
-#define CAN_FM1R_FBM7_Msk                    (0x1U << CAN_FM1R_FBM7_Pos)       /*!< 0x00000080 */
-#define CAN_FM1R_FBM7                        CAN_FM1R_FBM7_Msk                 /*!< Filter Init Mode for filter 7 */
-#define CAN_FM1R_FBM8_Pos                    (8U)                              
-#define CAN_FM1R_FBM8_Msk                    (0x1U << CAN_FM1R_FBM8_Pos)       /*!< 0x00000100 */
-#define CAN_FM1R_FBM8                        CAN_FM1R_FBM8_Msk                 /*!< Filter Init Mode for filter 8 */
-#define CAN_FM1R_FBM9_Pos                    (9U)                              
-#define CAN_FM1R_FBM9_Msk                    (0x1U << CAN_FM1R_FBM9_Pos)       /*!< 0x00000200 */
-#define CAN_FM1R_FBM9                        CAN_FM1R_FBM9_Msk                 /*!< Filter Init Mode for filter 9 */
-#define CAN_FM1R_FBM10_Pos                   (10U)                             
-#define CAN_FM1R_FBM10_Msk                   (0x1U << CAN_FM1R_FBM10_Pos)      /*!< 0x00000400 */
-#define CAN_FM1R_FBM10                       CAN_FM1R_FBM10_Msk                /*!< Filter Init Mode for filter 10 */
-#define CAN_FM1R_FBM11_Pos                   (11U)                             
-#define CAN_FM1R_FBM11_Msk                   (0x1U << CAN_FM1R_FBM11_Pos)      /*!< 0x00000800 */
-#define CAN_FM1R_FBM11                       CAN_FM1R_FBM11_Msk                /*!< Filter Init Mode for filter 11 */
-#define CAN_FM1R_FBM12_Pos                   (12U)                             
-#define CAN_FM1R_FBM12_Msk                   (0x1U << CAN_FM1R_FBM12_Pos)      /*!< 0x00001000 */
-#define CAN_FM1R_FBM12                       CAN_FM1R_FBM12_Msk                /*!< Filter Init Mode for filter 12 */
-#define CAN_FM1R_FBM13_Pos                   (13U)                             
-#define CAN_FM1R_FBM13_Msk                   (0x1U << CAN_FM1R_FBM13_Pos)      /*!< 0x00002000 */
-#define CAN_FM1R_FBM13                       CAN_FM1R_FBM13_Msk                /*!< Filter Init Mode for filter 13 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define CAN_FS1R_FSC_Pos                     (0U)                              
-#define CAN_FS1R_FSC_Msk                     (0x3FFFU << CAN_FS1R_FSC_Pos)     /*!< 0x00003FFF */
-#define CAN_FS1R_FSC                         CAN_FS1R_FSC_Msk                  /*!< Filter Scale Configuration */
-#define CAN_FS1R_FSC0_Pos                    (0U)                              
-#define CAN_FS1R_FSC0_Msk                    (0x1U << CAN_FS1R_FSC0_Pos)       /*!< 0x00000001 */
-#define CAN_FS1R_FSC0                        CAN_FS1R_FSC0_Msk                 /*!< Filter Scale Configuration for filter 0 */
-#define CAN_FS1R_FSC1_Pos                    (1U)                              
-#define CAN_FS1R_FSC1_Msk                    (0x1U << CAN_FS1R_FSC1_Pos)       /*!< 0x00000002 */
-#define CAN_FS1R_FSC1                        CAN_FS1R_FSC1_Msk                 /*!< Filter Scale Configuration for filter 1 */
-#define CAN_FS1R_FSC2_Pos                    (2U)                              
-#define CAN_FS1R_FSC2_Msk                    (0x1U << CAN_FS1R_FSC2_Pos)       /*!< 0x00000004 */
-#define CAN_FS1R_FSC2                        CAN_FS1R_FSC2_Msk                 /*!< Filter Scale Configuration for filter 2 */
-#define CAN_FS1R_FSC3_Pos                    (3U)                              
-#define CAN_FS1R_FSC3_Msk                    (0x1U << CAN_FS1R_FSC3_Pos)       /*!< 0x00000008 */
-#define CAN_FS1R_FSC3                        CAN_FS1R_FSC3_Msk                 /*!< Filter Scale Configuration for filter 3 */
-#define CAN_FS1R_FSC4_Pos                    (4U)                              
-#define CAN_FS1R_FSC4_Msk                    (0x1U << CAN_FS1R_FSC4_Pos)       /*!< 0x00000010 */
-#define CAN_FS1R_FSC4                        CAN_FS1R_FSC4_Msk                 /*!< Filter Scale Configuration for filter 4 */
-#define CAN_FS1R_FSC5_Pos                    (5U)                              
-#define CAN_FS1R_FSC5_Msk                    (0x1U << CAN_FS1R_FSC5_Pos)       /*!< 0x00000020 */
-#define CAN_FS1R_FSC5                        CAN_FS1R_FSC5_Msk                 /*!< Filter Scale Configuration for filter 5 */
-#define CAN_FS1R_FSC6_Pos                    (6U)                              
-#define CAN_FS1R_FSC6_Msk                    (0x1U << CAN_FS1R_FSC6_Pos)       /*!< 0x00000040 */
-#define CAN_FS1R_FSC6                        CAN_FS1R_FSC6_Msk                 /*!< Filter Scale Configuration for filter 6 */
-#define CAN_FS1R_FSC7_Pos                    (7U)                              
-#define CAN_FS1R_FSC7_Msk                    (0x1U << CAN_FS1R_FSC7_Pos)       /*!< 0x00000080 */
-#define CAN_FS1R_FSC7                        CAN_FS1R_FSC7_Msk                 /*!< Filter Scale Configuration for filter 7 */
-#define CAN_FS1R_FSC8_Pos                    (8U)                              
-#define CAN_FS1R_FSC8_Msk                    (0x1U << CAN_FS1R_FSC8_Pos)       /*!< 0x00000100 */
-#define CAN_FS1R_FSC8                        CAN_FS1R_FSC8_Msk                 /*!< Filter Scale Configuration for filter 8 */
-#define CAN_FS1R_FSC9_Pos                    (9U)                              
-#define CAN_FS1R_FSC9_Msk                    (0x1U << CAN_FS1R_FSC9_Pos)       /*!< 0x00000200 */
-#define CAN_FS1R_FSC9                        CAN_FS1R_FSC9_Msk                 /*!< Filter Scale Configuration for filter 9 */
-#define CAN_FS1R_FSC10_Pos                   (10U)                             
-#define CAN_FS1R_FSC10_Msk                   (0x1U << CAN_FS1R_FSC10_Pos)      /*!< 0x00000400 */
-#define CAN_FS1R_FSC10                       CAN_FS1R_FSC10_Msk                /*!< Filter Scale Configuration for filter 10 */
-#define CAN_FS1R_FSC11_Pos                   (11U)                             
-#define CAN_FS1R_FSC11_Msk                   (0x1U << CAN_FS1R_FSC11_Pos)      /*!< 0x00000800 */
-#define CAN_FS1R_FSC11                       CAN_FS1R_FSC11_Msk                /*!< Filter Scale Configuration for filter 11 */
-#define CAN_FS1R_FSC12_Pos                   (12U)                             
-#define CAN_FS1R_FSC12_Msk                   (0x1U << CAN_FS1R_FSC12_Pos)      /*!< 0x00001000 */
-#define CAN_FS1R_FSC12                       CAN_FS1R_FSC12_Msk                /*!< Filter Scale Configuration for filter 12 */
-#define CAN_FS1R_FSC13_Pos                   (13U)                             
-#define CAN_FS1R_FSC13_Msk                   (0x1U << CAN_FS1R_FSC13_Pos)      /*!< 0x00002000 */
-#define CAN_FS1R_FSC13                       CAN_FS1R_FSC13_Msk                /*!< Filter Scale Configuration for filter 13 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define CAN_FFA1R_FFA_Pos                    (0U)                              
-#define CAN_FFA1R_FFA_Msk                    (0x3FFFU << CAN_FFA1R_FFA_Pos)    /*!< 0x00003FFF */
-#define CAN_FFA1R_FFA                        CAN_FFA1R_FFA_Msk                 /*!< Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0_Pos                   (0U)                              
-#define CAN_FFA1R_FFA0_Msk                   (0x1U << CAN_FFA1R_FFA0_Pos)      /*!< 0x00000001 */
-#define CAN_FFA1R_FFA0                       CAN_FFA1R_FFA0_Msk                /*!< Filter FIFO Assignment for filter 0 */
-#define CAN_FFA1R_FFA1_Pos                   (1U)                              
-#define CAN_FFA1R_FFA1_Msk                   (0x1U << CAN_FFA1R_FFA1_Pos)      /*!< 0x00000002 */
-#define CAN_FFA1R_FFA1                       CAN_FFA1R_FFA1_Msk                /*!< Filter FIFO Assignment for filter 1 */
-#define CAN_FFA1R_FFA2_Pos                   (2U)                              
-#define CAN_FFA1R_FFA2_Msk                   (0x1U << CAN_FFA1R_FFA2_Pos)      /*!< 0x00000004 */
-#define CAN_FFA1R_FFA2                       CAN_FFA1R_FFA2_Msk                /*!< Filter FIFO Assignment for filter 2 */
-#define CAN_FFA1R_FFA3_Pos                   (3U)                              
-#define CAN_FFA1R_FFA3_Msk                   (0x1U << CAN_FFA1R_FFA3_Pos)      /*!< 0x00000008 */
-#define CAN_FFA1R_FFA3                       CAN_FFA1R_FFA3_Msk                /*!< Filter FIFO Assignment for filter 3 */
-#define CAN_FFA1R_FFA4_Pos                   (4U)                              
-#define CAN_FFA1R_FFA4_Msk                   (0x1U << CAN_FFA1R_FFA4_Pos)      /*!< 0x00000010 */
-#define CAN_FFA1R_FFA4                       CAN_FFA1R_FFA4_Msk                /*!< Filter FIFO Assignment for filter 4 */
-#define CAN_FFA1R_FFA5_Pos                   (5U)                              
-#define CAN_FFA1R_FFA5_Msk                   (0x1U << CAN_FFA1R_FFA5_Pos)      /*!< 0x00000020 */
-#define CAN_FFA1R_FFA5                       CAN_FFA1R_FFA5_Msk                /*!< Filter FIFO Assignment for filter 5 */
-#define CAN_FFA1R_FFA6_Pos                   (6U)                              
-#define CAN_FFA1R_FFA6_Msk                   (0x1U << CAN_FFA1R_FFA6_Pos)      /*!< 0x00000040 */
-#define CAN_FFA1R_FFA6                       CAN_FFA1R_FFA6_Msk                /*!< Filter FIFO Assignment for filter 6 */
-#define CAN_FFA1R_FFA7_Pos                   (7U)                              
-#define CAN_FFA1R_FFA7_Msk                   (0x1U << CAN_FFA1R_FFA7_Pos)      /*!< 0x00000080 */
-#define CAN_FFA1R_FFA7                       CAN_FFA1R_FFA7_Msk                /*!< Filter FIFO Assignment for filter 7 */
-#define CAN_FFA1R_FFA8_Pos                   (8U)                              
-#define CAN_FFA1R_FFA8_Msk                   (0x1U << CAN_FFA1R_FFA8_Pos)      /*!< 0x00000100 */
-#define CAN_FFA1R_FFA8                       CAN_FFA1R_FFA8_Msk                /*!< Filter FIFO Assignment for filter 8 */
-#define CAN_FFA1R_FFA9_Pos                   (9U)                              
-#define CAN_FFA1R_FFA9_Msk                   (0x1U << CAN_FFA1R_FFA9_Pos)      /*!< 0x00000200 */
-#define CAN_FFA1R_FFA9                       CAN_FFA1R_FFA9_Msk                /*!< Filter FIFO Assignment for filter 9 */
-#define CAN_FFA1R_FFA10_Pos                  (10U)                             
-#define CAN_FFA1R_FFA10_Msk                  (0x1U << CAN_FFA1R_FFA10_Pos)     /*!< 0x00000400 */
-#define CAN_FFA1R_FFA10                      CAN_FFA1R_FFA10_Msk               /*!< Filter FIFO Assignment for filter 10 */
-#define CAN_FFA1R_FFA11_Pos                  (11U)                             
-#define CAN_FFA1R_FFA11_Msk                  (0x1U << CAN_FFA1R_FFA11_Pos)     /*!< 0x00000800 */
-#define CAN_FFA1R_FFA11                      CAN_FFA1R_FFA11_Msk               /*!< Filter FIFO Assignment for filter 11 */
-#define CAN_FFA1R_FFA12_Pos                  (12U)                             
-#define CAN_FFA1R_FFA12_Msk                  (0x1U << CAN_FFA1R_FFA12_Pos)     /*!< 0x00001000 */
-#define CAN_FFA1R_FFA12                      CAN_FFA1R_FFA12_Msk               /*!< Filter FIFO Assignment for filter 12 */
-#define CAN_FFA1R_FFA13_Pos                  (13U)                             
-#define CAN_FFA1R_FFA13_Msk                  (0x1U << CAN_FFA1R_FFA13_Pos)     /*!< 0x00002000 */
-#define CAN_FFA1R_FFA13                      CAN_FFA1R_FFA13_Msk               /*!< Filter FIFO Assignment for filter 13 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define CAN_FA1R_FACT_Pos                    (0U)                              
-#define CAN_FA1R_FACT_Msk                    (0x3FFFU << CAN_FA1R_FACT_Pos)    /*!< 0x00003FFF */
-#define CAN_FA1R_FACT                        CAN_FA1R_FACT_Msk                 /*!< Filter Active */
-#define CAN_FA1R_FACT0_Pos                   (0U)                              
-#define CAN_FA1R_FACT0_Msk                   (0x1U << CAN_FA1R_FACT0_Pos)      /*!< 0x00000001 */
-#define CAN_FA1R_FACT0                       CAN_FA1R_FACT0_Msk                /*!< Filter 0 Active */
-#define CAN_FA1R_FACT1_Pos                   (1U)                              
-#define CAN_FA1R_FACT1_Msk                   (0x1U << CAN_FA1R_FACT1_Pos)      /*!< 0x00000002 */
-#define CAN_FA1R_FACT1                       CAN_FA1R_FACT1_Msk                /*!< Filter 1 Active */
-#define CAN_FA1R_FACT2_Pos                   (2U)                              
-#define CAN_FA1R_FACT2_Msk                   (0x1U << CAN_FA1R_FACT2_Pos)      /*!< 0x00000004 */
-#define CAN_FA1R_FACT2                       CAN_FA1R_FACT2_Msk                /*!< Filter 2 Active */
-#define CAN_FA1R_FACT3_Pos                   (3U)                              
-#define CAN_FA1R_FACT3_Msk                   (0x1U << CAN_FA1R_FACT3_Pos)      /*!< 0x00000008 */
-#define CAN_FA1R_FACT3                       CAN_FA1R_FACT3_Msk                /*!< Filter 3 Active */
-#define CAN_FA1R_FACT4_Pos                   (4U)                              
-#define CAN_FA1R_FACT4_Msk                   (0x1U << CAN_FA1R_FACT4_Pos)      /*!< 0x00000010 */
-#define CAN_FA1R_FACT4                       CAN_FA1R_FACT4_Msk                /*!< Filter 4 Active */
-#define CAN_FA1R_FACT5_Pos                   (5U)                              
-#define CAN_FA1R_FACT5_Msk                   (0x1U << CAN_FA1R_FACT5_Pos)      /*!< 0x00000020 */
-#define CAN_FA1R_FACT5                       CAN_FA1R_FACT5_Msk                /*!< Filter 5 Active */
-#define CAN_FA1R_FACT6_Pos                   (6U)                              
-#define CAN_FA1R_FACT6_Msk                   (0x1U << CAN_FA1R_FACT6_Pos)      /*!< 0x00000040 */
-#define CAN_FA1R_FACT6                       CAN_FA1R_FACT6_Msk                /*!< Filter 6 Active */
-#define CAN_FA1R_FACT7_Pos                   (7U)                              
-#define CAN_FA1R_FACT7_Msk                   (0x1U << CAN_FA1R_FACT7_Pos)      /*!< 0x00000080 */
-#define CAN_FA1R_FACT7                       CAN_FA1R_FACT7_Msk                /*!< Filter 7 Active */
-#define CAN_FA1R_FACT8_Pos                   (8U)                              
-#define CAN_FA1R_FACT8_Msk                   (0x1U << CAN_FA1R_FACT8_Pos)      /*!< 0x00000100 */
-#define CAN_FA1R_FACT8                       CAN_FA1R_FACT8_Msk                /*!< Filter 8 Active */
-#define CAN_FA1R_FACT9_Pos                   (9U)                              
-#define CAN_FA1R_FACT9_Msk                   (0x1U << CAN_FA1R_FACT9_Pos)      /*!< 0x00000200 */
-#define CAN_FA1R_FACT9                       CAN_FA1R_FACT9_Msk                /*!< Filter 9 Active */
-#define CAN_FA1R_FACT10_Pos                  (10U)                             
-#define CAN_FA1R_FACT10_Msk                  (0x1U << CAN_FA1R_FACT10_Pos)     /*!< 0x00000400 */
-#define CAN_FA1R_FACT10                      CAN_FA1R_FACT10_Msk               /*!< Filter 10 Active */
-#define CAN_FA1R_FACT11_Pos                  (11U)                             
-#define CAN_FA1R_FACT11_Msk                  (0x1U << CAN_FA1R_FACT11_Pos)     /*!< 0x00000800 */
-#define CAN_FA1R_FACT11                      CAN_FA1R_FACT11_Msk               /*!< Filter 11 Active */
-#define CAN_FA1R_FACT12_Pos                  (12U)                             
-#define CAN_FA1R_FACT12_Msk                  (0x1U << CAN_FA1R_FACT12_Pos)     /*!< 0x00001000 */
-#define CAN_FA1R_FACT12                      CAN_FA1R_FACT12_Msk               /*!< Filter 12 Active */
-#define CAN_FA1R_FACT13_Pos                  (13U)                             
-#define CAN_FA1R_FACT13_Msk                  (0x1U << CAN_FA1R_FACT13_Pos)     /*!< 0x00002000 */
-#define CAN_FA1R_FACT13                      CAN_FA1R_FACT13_Msk               /*!< Filter 13 Active */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define CAN_F0R1_FB0_Pos                     (0U)                              
-#define CAN_F0R1_FB0_Msk                     (0x1U << CAN_F0R1_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F0R1_FB0                         CAN_F0R1_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F0R1_FB1_Pos                     (1U)                              
-#define CAN_F0R1_FB1_Msk                     (0x1U << CAN_F0R1_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F0R1_FB1                         CAN_F0R1_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F0R1_FB2_Pos                     (2U)                              
-#define CAN_F0R1_FB2_Msk                     (0x1U << CAN_F0R1_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F0R1_FB2                         CAN_F0R1_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F0R1_FB3_Pos                     (3U)                              
-#define CAN_F0R1_FB3_Msk                     (0x1U << CAN_F0R1_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F0R1_FB3                         CAN_F0R1_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F0R1_FB4_Pos                     (4U)                              
-#define CAN_F0R1_FB4_Msk                     (0x1U << CAN_F0R1_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F0R1_FB4                         CAN_F0R1_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F0R1_FB5_Pos                     (5U)                              
-#define CAN_F0R1_FB5_Msk                     (0x1U << CAN_F0R1_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F0R1_FB5                         CAN_F0R1_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F0R1_FB6_Pos                     (6U)                              
-#define CAN_F0R1_FB6_Msk                     (0x1U << CAN_F0R1_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F0R1_FB6                         CAN_F0R1_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F0R1_FB7_Pos                     (7U)                              
-#define CAN_F0R1_FB7_Msk                     (0x1U << CAN_F0R1_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F0R1_FB7                         CAN_F0R1_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F0R1_FB8_Pos                     (8U)                              
-#define CAN_F0R1_FB8_Msk                     (0x1U << CAN_F0R1_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F0R1_FB8                         CAN_F0R1_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F0R1_FB9_Pos                     (9U)                              
-#define CAN_F0R1_FB9_Msk                     (0x1U << CAN_F0R1_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F0R1_FB9                         CAN_F0R1_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F0R1_FB10_Pos                    (10U)                             
-#define CAN_F0R1_FB10_Msk                    (0x1U << CAN_F0R1_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F0R1_FB10                        CAN_F0R1_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F0R1_FB11_Pos                    (11U)                             
-#define CAN_F0R1_FB11_Msk                    (0x1U << CAN_F0R1_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F0R1_FB11                        CAN_F0R1_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F0R1_FB12_Pos                    (12U)                             
-#define CAN_F0R1_FB12_Msk                    (0x1U << CAN_F0R1_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F0R1_FB12                        CAN_F0R1_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F0R1_FB13_Pos                    (13U)                             
-#define CAN_F0R1_FB13_Msk                    (0x1U << CAN_F0R1_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F0R1_FB13                        CAN_F0R1_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F0R1_FB14_Pos                    (14U)                             
-#define CAN_F0R1_FB14_Msk                    (0x1U << CAN_F0R1_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F0R1_FB14                        CAN_F0R1_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F0R1_FB15_Pos                    (15U)                             
-#define CAN_F0R1_FB15_Msk                    (0x1U << CAN_F0R1_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F0R1_FB15                        CAN_F0R1_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F0R1_FB16_Pos                    (16U)                             
-#define CAN_F0R1_FB16_Msk                    (0x1U << CAN_F0R1_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F0R1_FB16                        CAN_F0R1_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F0R1_FB17_Pos                    (17U)                             
-#define CAN_F0R1_FB17_Msk                    (0x1U << CAN_F0R1_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F0R1_FB17                        CAN_F0R1_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F0R1_FB18_Pos                    (18U)                             
-#define CAN_F0R1_FB18_Msk                    (0x1U << CAN_F0R1_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F0R1_FB18                        CAN_F0R1_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F0R1_FB19_Pos                    (19U)                             
-#define CAN_F0R1_FB19_Msk                    (0x1U << CAN_F0R1_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F0R1_FB19                        CAN_F0R1_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F0R1_FB20_Pos                    (20U)                             
-#define CAN_F0R1_FB20_Msk                    (0x1U << CAN_F0R1_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F0R1_FB20                        CAN_F0R1_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F0R1_FB21_Pos                    (21U)                             
-#define CAN_F0R1_FB21_Msk                    (0x1U << CAN_F0R1_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F0R1_FB21                        CAN_F0R1_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F0R1_FB22_Pos                    (22U)                             
-#define CAN_F0R1_FB22_Msk                    (0x1U << CAN_F0R1_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F0R1_FB22                        CAN_F0R1_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F0R1_FB23_Pos                    (23U)                             
-#define CAN_F0R1_FB23_Msk                    (0x1U << CAN_F0R1_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F0R1_FB23                        CAN_F0R1_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F0R1_FB24_Pos                    (24U)                             
-#define CAN_F0R1_FB24_Msk                    (0x1U << CAN_F0R1_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F0R1_FB24                        CAN_F0R1_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F0R1_FB25_Pos                    (25U)                             
-#define CAN_F0R1_FB25_Msk                    (0x1U << CAN_F0R1_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F0R1_FB25                        CAN_F0R1_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F0R1_FB26_Pos                    (26U)                             
-#define CAN_F0R1_FB26_Msk                    (0x1U << CAN_F0R1_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F0R1_FB26                        CAN_F0R1_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F0R1_FB27_Pos                    (27U)                             
-#define CAN_F0R1_FB27_Msk                    (0x1U << CAN_F0R1_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F0R1_FB27                        CAN_F0R1_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F0R1_FB28_Pos                    (28U)                             
-#define CAN_F0R1_FB28_Msk                    (0x1U << CAN_F0R1_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F0R1_FB28                        CAN_F0R1_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F0R1_FB29_Pos                    (29U)                             
-#define CAN_F0R1_FB29_Msk                    (0x1U << CAN_F0R1_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F0R1_FB29                        CAN_F0R1_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F0R1_FB30_Pos                    (30U)                             
-#define CAN_F0R1_FB30_Msk                    (0x1U << CAN_F0R1_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F0R1_FB30                        CAN_F0R1_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F0R1_FB31_Pos                    (31U)                             
-#define CAN_F0R1_FB31_Msk                    (0x1U << CAN_F0R1_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F0R1_FB31                        CAN_F0R1_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define CAN_F1R1_FB0_Pos                     (0U)                              
-#define CAN_F1R1_FB0_Msk                     (0x1U << CAN_F1R1_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F1R1_FB0                         CAN_F1R1_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F1R1_FB1_Pos                     (1U)                              
-#define CAN_F1R1_FB1_Msk                     (0x1U << CAN_F1R1_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F1R1_FB1                         CAN_F1R1_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F1R1_FB2_Pos                     (2U)                              
-#define CAN_F1R1_FB2_Msk                     (0x1U << CAN_F1R1_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F1R1_FB2                         CAN_F1R1_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F1R1_FB3_Pos                     (3U)                              
-#define CAN_F1R1_FB3_Msk                     (0x1U << CAN_F1R1_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F1R1_FB3                         CAN_F1R1_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F1R1_FB4_Pos                     (4U)                              
-#define CAN_F1R1_FB4_Msk                     (0x1U << CAN_F1R1_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F1R1_FB4                         CAN_F1R1_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F1R1_FB5_Pos                     (5U)                              
-#define CAN_F1R1_FB5_Msk                     (0x1U << CAN_F1R1_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F1R1_FB5                         CAN_F1R1_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F1R1_FB6_Pos                     (6U)                              
-#define CAN_F1R1_FB6_Msk                     (0x1U << CAN_F1R1_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F1R1_FB6                         CAN_F1R1_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F1R1_FB7_Pos                     (7U)                              
-#define CAN_F1R1_FB7_Msk                     (0x1U << CAN_F1R1_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F1R1_FB7                         CAN_F1R1_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F1R1_FB8_Pos                     (8U)                              
-#define CAN_F1R1_FB8_Msk                     (0x1U << CAN_F1R1_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F1R1_FB8                         CAN_F1R1_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F1R1_FB9_Pos                     (9U)                              
-#define CAN_F1R1_FB9_Msk                     (0x1U << CAN_F1R1_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F1R1_FB9                         CAN_F1R1_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F1R1_FB10_Pos                    (10U)                             
-#define CAN_F1R1_FB10_Msk                    (0x1U << CAN_F1R1_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F1R1_FB10                        CAN_F1R1_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F1R1_FB11_Pos                    (11U)                             
-#define CAN_F1R1_FB11_Msk                    (0x1U << CAN_F1R1_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F1R1_FB11                        CAN_F1R1_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F1R1_FB12_Pos                    (12U)                             
-#define CAN_F1R1_FB12_Msk                    (0x1U << CAN_F1R1_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F1R1_FB12                        CAN_F1R1_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F1R1_FB13_Pos                    (13U)                             
-#define CAN_F1R1_FB13_Msk                    (0x1U << CAN_F1R1_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F1R1_FB13                        CAN_F1R1_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F1R1_FB14_Pos                    (14U)                             
-#define CAN_F1R1_FB14_Msk                    (0x1U << CAN_F1R1_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F1R1_FB14                        CAN_F1R1_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F1R1_FB15_Pos                    (15U)                             
-#define CAN_F1R1_FB15_Msk                    (0x1U << CAN_F1R1_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F1R1_FB15                        CAN_F1R1_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F1R1_FB16_Pos                    (16U)                             
-#define CAN_F1R1_FB16_Msk                    (0x1U << CAN_F1R1_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F1R1_FB16                        CAN_F1R1_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F1R1_FB17_Pos                    (17U)                             
-#define CAN_F1R1_FB17_Msk                    (0x1U << CAN_F1R1_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F1R1_FB17                        CAN_F1R1_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F1R1_FB18_Pos                    (18U)                             
-#define CAN_F1R1_FB18_Msk                    (0x1U << CAN_F1R1_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F1R1_FB18                        CAN_F1R1_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F1R1_FB19_Pos                    (19U)                             
-#define CAN_F1R1_FB19_Msk                    (0x1U << CAN_F1R1_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F1R1_FB19                        CAN_F1R1_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F1R1_FB20_Pos                    (20U)                             
-#define CAN_F1R1_FB20_Msk                    (0x1U << CAN_F1R1_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F1R1_FB20                        CAN_F1R1_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F1R1_FB21_Pos                    (21U)                             
-#define CAN_F1R1_FB21_Msk                    (0x1U << CAN_F1R1_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F1R1_FB21                        CAN_F1R1_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F1R1_FB22_Pos                    (22U)                             
-#define CAN_F1R1_FB22_Msk                    (0x1U << CAN_F1R1_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F1R1_FB22                        CAN_F1R1_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F1R1_FB23_Pos                    (23U)                             
-#define CAN_F1R1_FB23_Msk                    (0x1U << CAN_F1R1_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F1R1_FB23                        CAN_F1R1_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F1R1_FB24_Pos                    (24U)                             
-#define CAN_F1R1_FB24_Msk                    (0x1U << CAN_F1R1_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F1R1_FB24                        CAN_F1R1_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F1R1_FB25_Pos                    (25U)                             
-#define CAN_F1R1_FB25_Msk                    (0x1U << CAN_F1R1_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F1R1_FB25                        CAN_F1R1_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F1R1_FB26_Pos                    (26U)                             
-#define CAN_F1R1_FB26_Msk                    (0x1U << CAN_F1R1_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F1R1_FB26                        CAN_F1R1_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F1R1_FB27_Pos                    (27U)                             
-#define CAN_F1R1_FB27_Msk                    (0x1U << CAN_F1R1_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F1R1_FB27                        CAN_F1R1_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F1R1_FB28_Pos                    (28U)                             
-#define CAN_F1R1_FB28_Msk                    (0x1U << CAN_F1R1_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F1R1_FB28                        CAN_F1R1_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F1R1_FB29_Pos                    (29U)                             
-#define CAN_F1R1_FB29_Msk                    (0x1U << CAN_F1R1_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F1R1_FB29                        CAN_F1R1_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F1R1_FB30_Pos                    (30U)                             
-#define CAN_F1R1_FB30_Msk                    (0x1U << CAN_F1R1_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F1R1_FB30                        CAN_F1R1_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F1R1_FB31_Pos                    (31U)                             
-#define CAN_F1R1_FB31_Msk                    (0x1U << CAN_F1R1_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F1R1_FB31                        CAN_F1R1_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define CAN_F2R1_FB0_Pos                     (0U)                              
-#define CAN_F2R1_FB0_Msk                     (0x1U << CAN_F2R1_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F2R1_FB0                         CAN_F2R1_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F2R1_FB1_Pos                     (1U)                              
-#define CAN_F2R1_FB1_Msk                     (0x1U << CAN_F2R1_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F2R1_FB1                         CAN_F2R1_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F2R1_FB2_Pos                     (2U)                              
-#define CAN_F2R1_FB2_Msk                     (0x1U << CAN_F2R1_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F2R1_FB2                         CAN_F2R1_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F2R1_FB3_Pos                     (3U)                              
-#define CAN_F2R1_FB3_Msk                     (0x1U << CAN_F2R1_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F2R1_FB3                         CAN_F2R1_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F2R1_FB4_Pos                     (4U)                              
-#define CAN_F2R1_FB4_Msk                     (0x1U << CAN_F2R1_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F2R1_FB4                         CAN_F2R1_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F2R1_FB5_Pos                     (5U)                              
-#define CAN_F2R1_FB5_Msk                     (0x1U << CAN_F2R1_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F2R1_FB5                         CAN_F2R1_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F2R1_FB6_Pos                     (6U)                              
-#define CAN_F2R1_FB6_Msk                     (0x1U << CAN_F2R1_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F2R1_FB6                         CAN_F2R1_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F2R1_FB7_Pos                     (7U)                              
-#define CAN_F2R1_FB7_Msk                     (0x1U << CAN_F2R1_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F2R1_FB7                         CAN_F2R1_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F2R1_FB8_Pos                     (8U)                              
-#define CAN_F2R1_FB8_Msk                     (0x1U << CAN_F2R1_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F2R1_FB8                         CAN_F2R1_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F2R1_FB9_Pos                     (9U)                              
-#define CAN_F2R1_FB9_Msk                     (0x1U << CAN_F2R1_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F2R1_FB9                         CAN_F2R1_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F2R1_FB10_Pos                    (10U)                             
-#define CAN_F2R1_FB10_Msk                    (0x1U << CAN_F2R1_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F2R1_FB10                        CAN_F2R1_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F2R1_FB11_Pos                    (11U)                             
-#define CAN_F2R1_FB11_Msk                    (0x1U << CAN_F2R1_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F2R1_FB11                        CAN_F2R1_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F2R1_FB12_Pos                    (12U)                             
-#define CAN_F2R1_FB12_Msk                    (0x1U << CAN_F2R1_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F2R1_FB12                        CAN_F2R1_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F2R1_FB13_Pos                    (13U)                             
-#define CAN_F2R1_FB13_Msk                    (0x1U << CAN_F2R1_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F2R1_FB13                        CAN_F2R1_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F2R1_FB14_Pos                    (14U)                             
-#define CAN_F2R1_FB14_Msk                    (0x1U << CAN_F2R1_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F2R1_FB14                        CAN_F2R1_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F2R1_FB15_Pos                    (15U)                             
-#define CAN_F2R1_FB15_Msk                    (0x1U << CAN_F2R1_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F2R1_FB15                        CAN_F2R1_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F2R1_FB16_Pos                    (16U)                             
-#define CAN_F2R1_FB16_Msk                    (0x1U << CAN_F2R1_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F2R1_FB16                        CAN_F2R1_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F2R1_FB17_Pos                    (17U)                             
-#define CAN_F2R1_FB17_Msk                    (0x1U << CAN_F2R1_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F2R1_FB17                        CAN_F2R1_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F2R1_FB18_Pos                    (18U)                             
-#define CAN_F2R1_FB18_Msk                    (0x1U << CAN_F2R1_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F2R1_FB18                        CAN_F2R1_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F2R1_FB19_Pos                    (19U)                             
-#define CAN_F2R1_FB19_Msk                    (0x1U << CAN_F2R1_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F2R1_FB19                        CAN_F2R1_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F2R1_FB20_Pos                    (20U)                             
-#define CAN_F2R1_FB20_Msk                    (0x1U << CAN_F2R1_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F2R1_FB20                        CAN_F2R1_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F2R1_FB21_Pos                    (21U)                             
-#define CAN_F2R1_FB21_Msk                    (0x1U << CAN_F2R1_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F2R1_FB21                        CAN_F2R1_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F2R1_FB22_Pos                    (22U)                             
-#define CAN_F2R1_FB22_Msk                    (0x1U << CAN_F2R1_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F2R1_FB22                        CAN_F2R1_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F2R1_FB23_Pos                    (23U)                             
-#define CAN_F2R1_FB23_Msk                    (0x1U << CAN_F2R1_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F2R1_FB23                        CAN_F2R1_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F2R1_FB24_Pos                    (24U)                             
-#define CAN_F2R1_FB24_Msk                    (0x1U << CAN_F2R1_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F2R1_FB24                        CAN_F2R1_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F2R1_FB25_Pos                    (25U)                             
-#define CAN_F2R1_FB25_Msk                    (0x1U << CAN_F2R1_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F2R1_FB25                        CAN_F2R1_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F2R1_FB26_Pos                    (26U)                             
-#define CAN_F2R1_FB26_Msk                    (0x1U << CAN_F2R1_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F2R1_FB26                        CAN_F2R1_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F2R1_FB27_Pos                    (27U)                             
-#define CAN_F2R1_FB27_Msk                    (0x1U << CAN_F2R1_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F2R1_FB27                        CAN_F2R1_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F2R1_FB28_Pos                    (28U)                             
-#define CAN_F2R1_FB28_Msk                    (0x1U << CAN_F2R1_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F2R1_FB28                        CAN_F2R1_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F2R1_FB29_Pos                    (29U)                             
-#define CAN_F2R1_FB29_Msk                    (0x1U << CAN_F2R1_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F2R1_FB29                        CAN_F2R1_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F2R1_FB30_Pos                    (30U)                             
-#define CAN_F2R1_FB30_Msk                    (0x1U << CAN_F2R1_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F2R1_FB30                        CAN_F2R1_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F2R1_FB31_Pos                    (31U)                             
-#define CAN_F2R1_FB31_Msk                    (0x1U << CAN_F2R1_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F2R1_FB31                        CAN_F2R1_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define CAN_F3R1_FB0_Pos                     (0U)                              
-#define CAN_F3R1_FB0_Msk                     (0x1U << CAN_F3R1_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F3R1_FB0                         CAN_F3R1_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F3R1_FB1_Pos                     (1U)                              
-#define CAN_F3R1_FB1_Msk                     (0x1U << CAN_F3R1_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F3R1_FB1                         CAN_F3R1_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F3R1_FB2_Pos                     (2U)                              
-#define CAN_F3R1_FB2_Msk                     (0x1U << CAN_F3R1_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F3R1_FB2                         CAN_F3R1_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F3R1_FB3_Pos                     (3U)                              
-#define CAN_F3R1_FB3_Msk                     (0x1U << CAN_F3R1_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F3R1_FB3                         CAN_F3R1_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F3R1_FB4_Pos                     (4U)                              
-#define CAN_F3R1_FB4_Msk                     (0x1U << CAN_F3R1_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F3R1_FB4                         CAN_F3R1_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F3R1_FB5_Pos                     (5U)                              
-#define CAN_F3R1_FB5_Msk                     (0x1U << CAN_F3R1_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F3R1_FB5                         CAN_F3R1_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F3R1_FB6_Pos                     (6U)                              
-#define CAN_F3R1_FB6_Msk                     (0x1U << CAN_F3R1_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F3R1_FB6                         CAN_F3R1_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F3R1_FB7_Pos                     (7U)                              
-#define CAN_F3R1_FB7_Msk                     (0x1U << CAN_F3R1_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F3R1_FB7                         CAN_F3R1_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F3R1_FB8_Pos                     (8U)                              
-#define CAN_F3R1_FB8_Msk                     (0x1U << CAN_F3R1_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F3R1_FB8                         CAN_F3R1_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F3R1_FB9_Pos                     (9U)                              
-#define CAN_F3R1_FB9_Msk                     (0x1U << CAN_F3R1_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F3R1_FB9                         CAN_F3R1_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F3R1_FB10_Pos                    (10U)                             
-#define CAN_F3R1_FB10_Msk                    (0x1U << CAN_F3R1_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F3R1_FB10                        CAN_F3R1_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F3R1_FB11_Pos                    (11U)                             
-#define CAN_F3R1_FB11_Msk                    (0x1U << CAN_F3R1_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F3R1_FB11                        CAN_F3R1_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F3R1_FB12_Pos                    (12U)                             
-#define CAN_F3R1_FB12_Msk                    (0x1U << CAN_F3R1_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F3R1_FB12                        CAN_F3R1_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F3R1_FB13_Pos                    (13U)                             
-#define CAN_F3R1_FB13_Msk                    (0x1U << CAN_F3R1_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F3R1_FB13                        CAN_F3R1_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F3R1_FB14_Pos                    (14U)                             
-#define CAN_F3R1_FB14_Msk                    (0x1U << CAN_F3R1_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F3R1_FB14                        CAN_F3R1_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F3R1_FB15_Pos                    (15U)                             
-#define CAN_F3R1_FB15_Msk                    (0x1U << CAN_F3R1_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F3R1_FB15                        CAN_F3R1_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F3R1_FB16_Pos                    (16U)                             
-#define CAN_F3R1_FB16_Msk                    (0x1U << CAN_F3R1_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F3R1_FB16                        CAN_F3R1_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F3R1_FB17_Pos                    (17U)                             
-#define CAN_F3R1_FB17_Msk                    (0x1U << CAN_F3R1_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F3R1_FB17                        CAN_F3R1_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F3R1_FB18_Pos                    (18U)                             
-#define CAN_F3R1_FB18_Msk                    (0x1U << CAN_F3R1_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F3R1_FB18                        CAN_F3R1_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F3R1_FB19_Pos                    (19U)                             
-#define CAN_F3R1_FB19_Msk                    (0x1U << CAN_F3R1_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F3R1_FB19                        CAN_F3R1_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F3R1_FB20_Pos                    (20U)                             
-#define CAN_F3R1_FB20_Msk                    (0x1U << CAN_F3R1_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F3R1_FB20                        CAN_F3R1_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F3R1_FB21_Pos                    (21U)                             
-#define CAN_F3R1_FB21_Msk                    (0x1U << CAN_F3R1_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F3R1_FB21                        CAN_F3R1_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F3R1_FB22_Pos                    (22U)                             
-#define CAN_F3R1_FB22_Msk                    (0x1U << CAN_F3R1_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F3R1_FB22                        CAN_F3R1_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F3R1_FB23_Pos                    (23U)                             
-#define CAN_F3R1_FB23_Msk                    (0x1U << CAN_F3R1_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F3R1_FB23                        CAN_F3R1_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F3R1_FB24_Pos                    (24U)                             
-#define CAN_F3R1_FB24_Msk                    (0x1U << CAN_F3R1_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F3R1_FB24                        CAN_F3R1_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F3R1_FB25_Pos                    (25U)                             
-#define CAN_F3R1_FB25_Msk                    (0x1U << CAN_F3R1_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F3R1_FB25                        CAN_F3R1_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F3R1_FB26_Pos                    (26U)                             
-#define CAN_F3R1_FB26_Msk                    (0x1U << CAN_F3R1_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F3R1_FB26                        CAN_F3R1_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F3R1_FB27_Pos                    (27U)                             
-#define CAN_F3R1_FB27_Msk                    (0x1U << CAN_F3R1_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F3R1_FB27                        CAN_F3R1_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F3R1_FB28_Pos                    (28U)                             
-#define CAN_F3R1_FB28_Msk                    (0x1U << CAN_F3R1_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F3R1_FB28                        CAN_F3R1_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F3R1_FB29_Pos                    (29U)                             
-#define CAN_F3R1_FB29_Msk                    (0x1U << CAN_F3R1_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F3R1_FB29                        CAN_F3R1_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F3R1_FB30_Pos                    (30U)                             
-#define CAN_F3R1_FB30_Msk                    (0x1U << CAN_F3R1_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F3R1_FB30                        CAN_F3R1_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F3R1_FB31_Pos                    (31U)                             
-#define CAN_F3R1_FB31_Msk                    (0x1U << CAN_F3R1_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F3R1_FB31                        CAN_F3R1_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define CAN_F4R1_FB0_Pos                     (0U)                              
-#define CAN_F4R1_FB0_Msk                     (0x1U << CAN_F4R1_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F4R1_FB0                         CAN_F4R1_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F4R1_FB1_Pos                     (1U)                              
-#define CAN_F4R1_FB1_Msk                     (0x1U << CAN_F4R1_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F4R1_FB1                         CAN_F4R1_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F4R1_FB2_Pos                     (2U)                              
-#define CAN_F4R1_FB2_Msk                     (0x1U << CAN_F4R1_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F4R1_FB2                         CAN_F4R1_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F4R1_FB3_Pos                     (3U)                              
-#define CAN_F4R1_FB3_Msk                     (0x1U << CAN_F4R1_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F4R1_FB3                         CAN_F4R1_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F4R1_FB4_Pos                     (4U)                              
-#define CAN_F4R1_FB4_Msk                     (0x1U << CAN_F4R1_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F4R1_FB4                         CAN_F4R1_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F4R1_FB5_Pos                     (5U)                              
-#define CAN_F4R1_FB5_Msk                     (0x1U << CAN_F4R1_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F4R1_FB5                         CAN_F4R1_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F4R1_FB6_Pos                     (6U)                              
-#define CAN_F4R1_FB6_Msk                     (0x1U << CAN_F4R1_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F4R1_FB6                         CAN_F4R1_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F4R1_FB7_Pos                     (7U)                              
-#define CAN_F4R1_FB7_Msk                     (0x1U << CAN_F4R1_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F4R1_FB7                         CAN_F4R1_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F4R1_FB8_Pos                     (8U)                              
-#define CAN_F4R1_FB8_Msk                     (0x1U << CAN_F4R1_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F4R1_FB8                         CAN_F4R1_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F4R1_FB9_Pos                     (9U)                              
-#define CAN_F4R1_FB9_Msk                     (0x1U << CAN_F4R1_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F4R1_FB9                         CAN_F4R1_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F4R1_FB10_Pos                    (10U)                             
-#define CAN_F4R1_FB10_Msk                    (0x1U << CAN_F4R1_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F4R1_FB10                        CAN_F4R1_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F4R1_FB11_Pos                    (11U)                             
-#define CAN_F4R1_FB11_Msk                    (0x1U << CAN_F4R1_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F4R1_FB11                        CAN_F4R1_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F4R1_FB12_Pos                    (12U)                             
-#define CAN_F4R1_FB12_Msk                    (0x1U << CAN_F4R1_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F4R1_FB12                        CAN_F4R1_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F4R1_FB13_Pos                    (13U)                             
-#define CAN_F4R1_FB13_Msk                    (0x1U << CAN_F4R1_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F4R1_FB13                        CAN_F4R1_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F4R1_FB14_Pos                    (14U)                             
-#define CAN_F4R1_FB14_Msk                    (0x1U << CAN_F4R1_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F4R1_FB14                        CAN_F4R1_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F4R1_FB15_Pos                    (15U)                             
-#define CAN_F4R1_FB15_Msk                    (0x1U << CAN_F4R1_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F4R1_FB15                        CAN_F4R1_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F4R1_FB16_Pos                    (16U)                             
-#define CAN_F4R1_FB16_Msk                    (0x1U << CAN_F4R1_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F4R1_FB16                        CAN_F4R1_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F4R1_FB17_Pos                    (17U)                             
-#define CAN_F4R1_FB17_Msk                    (0x1U << CAN_F4R1_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F4R1_FB17                        CAN_F4R1_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F4R1_FB18_Pos                    (18U)                             
-#define CAN_F4R1_FB18_Msk                    (0x1U << CAN_F4R1_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F4R1_FB18                        CAN_F4R1_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F4R1_FB19_Pos                    (19U)                             
-#define CAN_F4R1_FB19_Msk                    (0x1U << CAN_F4R1_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F4R1_FB19                        CAN_F4R1_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F4R1_FB20_Pos                    (20U)                             
-#define CAN_F4R1_FB20_Msk                    (0x1U << CAN_F4R1_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F4R1_FB20                        CAN_F4R1_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F4R1_FB21_Pos                    (21U)                             
-#define CAN_F4R1_FB21_Msk                    (0x1U << CAN_F4R1_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F4R1_FB21                        CAN_F4R1_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F4R1_FB22_Pos                    (22U)                             
-#define CAN_F4R1_FB22_Msk                    (0x1U << CAN_F4R1_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F4R1_FB22                        CAN_F4R1_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F4R1_FB23_Pos                    (23U)                             
-#define CAN_F4R1_FB23_Msk                    (0x1U << CAN_F4R1_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F4R1_FB23                        CAN_F4R1_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F4R1_FB24_Pos                    (24U)                             
-#define CAN_F4R1_FB24_Msk                    (0x1U << CAN_F4R1_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F4R1_FB24                        CAN_F4R1_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F4R1_FB25_Pos                    (25U)                             
-#define CAN_F4R1_FB25_Msk                    (0x1U << CAN_F4R1_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F4R1_FB25                        CAN_F4R1_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F4R1_FB26_Pos                    (26U)                             
-#define CAN_F4R1_FB26_Msk                    (0x1U << CAN_F4R1_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F4R1_FB26                        CAN_F4R1_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F4R1_FB27_Pos                    (27U)                             
-#define CAN_F4R1_FB27_Msk                    (0x1U << CAN_F4R1_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F4R1_FB27                        CAN_F4R1_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F4R1_FB28_Pos                    (28U)                             
-#define CAN_F4R1_FB28_Msk                    (0x1U << CAN_F4R1_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F4R1_FB28                        CAN_F4R1_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F4R1_FB29_Pos                    (29U)                             
-#define CAN_F4R1_FB29_Msk                    (0x1U << CAN_F4R1_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F4R1_FB29                        CAN_F4R1_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F4R1_FB30_Pos                    (30U)                             
-#define CAN_F4R1_FB30_Msk                    (0x1U << CAN_F4R1_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F4R1_FB30                        CAN_F4R1_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F4R1_FB31_Pos                    (31U)                             
-#define CAN_F4R1_FB31_Msk                    (0x1U << CAN_F4R1_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F4R1_FB31                        CAN_F4R1_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define CAN_F5R1_FB0_Pos                     (0U)                              
-#define CAN_F5R1_FB0_Msk                     (0x1U << CAN_F5R1_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F5R1_FB0                         CAN_F5R1_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F5R1_FB1_Pos                     (1U)                              
-#define CAN_F5R1_FB1_Msk                     (0x1U << CAN_F5R1_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F5R1_FB1                         CAN_F5R1_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F5R1_FB2_Pos                     (2U)                              
-#define CAN_F5R1_FB2_Msk                     (0x1U << CAN_F5R1_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F5R1_FB2                         CAN_F5R1_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F5R1_FB3_Pos                     (3U)                              
-#define CAN_F5R1_FB3_Msk                     (0x1U << CAN_F5R1_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F5R1_FB3                         CAN_F5R1_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F5R1_FB4_Pos                     (4U)                              
-#define CAN_F5R1_FB4_Msk                     (0x1U << CAN_F5R1_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F5R1_FB4                         CAN_F5R1_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F5R1_FB5_Pos                     (5U)                              
-#define CAN_F5R1_FB5_Msk                     (0x1U << CAN_F5R1_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F5R1_FB5                         CAN_F5R1_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F5R1_FB6_Pos                     (6U)                              
-#define CAN_F5R1_FB6_Msk                     (0x1U << CAN_F5R1_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F5R1_FB6                         CAN_F5R1_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F5R1_FB7_Pos                     (7U)                              
-#define CAN_F5R1_FB7_Msk                     (0x1U << CAN_F5R1_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F5R1_FB7                         CAN_F5R1_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F5R1_FB8_Pos                     (8U)                              
-#define CAN_F5R1_FB8_Msk                     (0x1U << CAN_F5R1_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F5R1_FB8                         CAN_F5R1_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F5R1_FB9_Pos                     (9U)                              
-#define CAN_F5R1_FB9_Msk                     (0x1U << CAN_F5R1_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F5R1_FB9                         CAN_F5R1_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F5R1_FB10_Pos                    (10U)                             
-#define CAN_F5R1_FB10_Msk                    (0x1U << CAN_F5R1_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F5R1_FB10                        CAN_F5R1_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F5R1_FB11_Pos                    (11U)                             
-#define CAN_F5R1_FB11_Msk                    (0x1U << CAN_F5R1_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F5R1_FB11                        CAN_F5R1_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F5R1_FB12_Pos                    (12U)                             
-#define CAN_F5R1_FB12_Msk                    (0x1U << CAN_F5R1_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F5R1_FB12                        CAN_F5R1_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F5R1_FB13_Pos                    (13U)                             
-#define CAN_F5R1_FB13_Msk                    (0x1U << CAN_F5R1_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F5R1_FB13                        CAN_F5R1_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F5R1_FB14_Pos                    (14U)                             
-#define CAN_F5R1_FB14_Msk                    (0x1U << CAN_F5R1_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F5R1_FB14                        CAN_F5R1_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F5R1_FB15_Pos                    (15U)                             
-#define CAN_F5R1_FB15_Msk                    (0x1U << CAN_F5R1_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F5R1_FB15                        CAN_F5R1_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F5R1_FB16_Pos                    (16U)                             
-#define CAN_F5R1_FB16_Msk                    (0x1U << CAN_F5R1_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F5R1_FB16                        CAN_F5R1_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F5R1_FB17_Pos                    (17U)                             
-#define CAN_F5R1_FB17_Msk                    (0x1U << CAN_F5R1_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F5R1_FB17                        CAN_F5R1_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F5R1_FB18_Pos                    (18U)                             
-#define CAN_F5R1_FB18_Msk                    (0x1U << CAN_F5R1_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F5R1_FB18                        CAN_F5R1_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F5R1_FB19_Pos                    (19U)                             
-#define CAN_F5R1_FB19_Msk                    (0x1U << CAN_F5R1_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F5R1_FB19                        CAN_F5R1_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F5R1_FB20_Pos                    (20U)                             
-#define CAN_F5R1_FB20_Msk                    (0x1U << CAN_F5R1_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F5R1_FB20                        CAN_F5R1_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F5R1_FB21_Pos                    (21U)                             
-#define CAN_F5R1_FB21_Msk                    (0x1U << CAN_F5R1_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F5R1_FB21                        CAN_F5R1_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F5R1_FB22_Pos                    (22U)                             
-#define CAN_F5R1_FB22_Msk                    (0x1U << CAN_F5R1_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F5R1_FB22                        CAN_F5R1_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F5R1_FB23_Pos                    (23U)                             
-#define CAN_F5R1_FB23_Msk                    (0x1U << CAN_F5R1_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F5R1_FB23                        CAN_F5R1_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F5R1_FB24_Pos                    (24U)                             
-#define CAN_F5R1_FB24_Msk                    (0x1U << CAN_F5R1_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F5R1_FB24                        CAN_F5R1_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F5R1_FB25_Pos                    (25U)                             
-#define CAN_F5R1_FB25_Msk                    (0x1U << CAN_F5R1_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F5R1_FB25                        CAN_F5R1_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F5R1_FB26_Pos                    (26U)                             
-#define CAN_F5R1_FB26_Msk                    (0x1U << CAN_F5R1_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F5R1_FB26                        CAN_F5R1_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F5R1_FB27_Pos                    (27U)                             
-#define CAN_F5R1_FB27_Msk                    (0x1U << CAN_F5R1_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F5R1_FB27                        CAN_F5R1_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F5R1_FB28_Pos                    (28U)                             
-#define CAN_F5R1_FB28_Msk                    (0x1U << CAN_F5R1_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F5R1_FB28                        CAN_F5R1_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F5R1_FB29_Pos                    (29U)                             
-#define CAN_F5R1_FB29_Msk                    (0x1U << CAN_F5R1_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F5R1_FB29                        CAN_F5R1_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F5R1_FB30_Pos                    (30U)                             
-#define CAN_F5R1_FB30_Msk                    (0x1U << CAN_F5R1_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F5R1_FB30                        CAN_F5R1_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F5R1_FB31_Pos                    (31U)                             
-#define CAN_F5R1_FB31_Msk                    (0x1U << CAN_F5R1_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F5R1_FB31                        CAN_F5R1_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define CAN_F6R1_FB0_Pos                     (0U)                              
-#define CAN_F6R1_FB0_Msk                     (0x1U << CAN_F6R1_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F6R1_FB0                         CAN_F6R1_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F6R1_FB1_Pos                     (1U)                              
-#define CAN_F6R1_FB1_Msk                     (0x1U << CAN_F6R1_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F6R1_FB1                         CAN_F6R1_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F6R1_FB2_Pos                     (2U)                              
-#define CAN_F6R1_FB2_Msk                     (0x1U << CAN_F6R1_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F6R1_FB2                         CAN_F6R1_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F6R1_FB3_Pos                     (3U)                              
-#define CAN_F6R1_FB3_Msk                     (0x1U << CAN_F6R1_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F6R1_FB3                         CAN_F6R1_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F6R1_FB4_Pos                     (4U)                              
-#define CAN_F6R1_FB4_Msk                     (0x1U << CAN_F6R1_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F6R1_FB4                         CAN_F6R1_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F6R1_FB5_Pos                     (5U)                              
-#define CAN_F6R1_FB5_Msk                     (0x1U << CAN_F6R1_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F6R1_FB5                         CAN_F6R1_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F6R1_FB6_Pos                     (6U)                              
-#define CAN_F6R1_FB6_Msk                     (0x1U << CAN_F6R1_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F6R1_FB6                         CAN_F6R1_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F6R1_FB7_Pos                     (7U)                              
-#define CAN_F6R1_FB7_Msk                     (0x1U << CAN_F6R1_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F6R1_FB7                         CAN_F6R1_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F6R1_FB8_Pos                     (8U)                              
-#define CAN_F6R1_FB8_Msk                     (0x1U << CAN_F6R1_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F6R1_FB8                         CAN_F6R1_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F6R1_FB9_Pos                     (9U)                              
-#define CAN_F6R1_FB9_Msk                     (0x1U << CAN_F6R1_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F6R1_FB9                         CAN_F6R1_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F6R1_FB10_Pos                    (10U)                             
-#define CAN_F6R1_FB10_Msk                    (0x1U << CAN_F6R1_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F6R1_FB10                        CAN_F6R1_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F6R1_FB11_Pos                    (11U)                             
-#define CAN_F6R1_FB11_Msk                    (0x1U << CAN_F6R1_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F6R1_FB11                        CAN_F6R1_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F6R1_FB12_Pos                    (12U)                             
-#define CAN_F6R1_FB12_Msk                    (0x1U << CAN_F6R1_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F6R1_FB12                        CAN_F6R1_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F6R1_FB13_Pos                    (13U)                             
-#define CAN_F6R1_FB13_Msk                    (0x1U << CAN_F6R1_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F6R1_FB13                        CAN_F6R1_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F6R1_FB14_Pos                    (14U)                             
-#define CAN_F6R1_FB14_Msk                    (0x1U << CAN_F6R1_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F6R1_FB14                        CAN_F6R1_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F6R1_FB15_Pos                    (15U)                             
-#define CAN_F6R1_FB15_Msk                    (0x1U << CAN_F6R1_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F6R1_FB15                        CAN_F6R1_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F6R1_FB16_Pos                    (16U)                             
-#define CAN_F6R1_FB16_Msk                    (0x1U << CAN_F6R1_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F6R1_FB16                        CAN_F6R1_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F6R1_FB17_Pos                    (17U)                             
-#define CAN_F6R1_FB17_Msk                    (0x1U << CAN_F6R1_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F6R1_FB17                        CAN_F6R1_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F6R1_FB18_Pos                    (18U)                             
-#define CAN_F6R1_FB18_Msk                    (0x1U << CAN_F6R1_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F6R1_FB18                        CAN_F6R1_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F6R1_FB19_Pos                    (19U)                             
-#define CAN_F6R1_FB19_Msk                    (0x1U << CAN_F6R1_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F6R1_FB19                        CAN_F6R1_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F6R1_FB20_Pos                    (20U)                             
-#define CAN_F6R1_FB20_Msk                    (0x1U << CAN_F6R1_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F6R1_FB20                        CAN_F6R1_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F6R1_FB21_Pos                    (21U)                             
-#define CAN_F6R1_FB21_Msk                    (0x1U << CAN_F6R1_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F6R1_FB21                        CAN_F6R1_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F6R1_FB22_Pos                    (22U)                             
-#define CAN_F6R1_FB22_Msk                    (0x1U << CAN_F6R1_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F6R1_FB22                        CAN_F6R1_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F6R1_FB23_Pos                    (23U)                             
-#define CAN_F6R1_FB23_Msk                    (0x1U << CAN_F6R1_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F6R1_FB23                        CAN_F6R1_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F6R1_FB24_Pos                    (24U)                             
-#define CAN_F6R1_FB24_Msk                    (0x1U << CAN_F6R1_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F6R1_FB24                        CAN_F6R1_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F6R1_FB25_Pos                    (25U)                             
-#define CAN_F6R1_FB25_Msk                    (0x1U << CAN_F6R1_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F6R1_FB25                        CAN_F6R1_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F6R1_FB26_Pos                    (26U)                             
-#define CAN_F6R1_FB26_Msk                    (0x1U << CAN_F6R1_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F6R1_FB26                        CAN_F6R1_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F6R1_FB27_Pos                    (27U)                             
-#define CAN_F6R1_FB27_Msk                    (0x1U << CAN_F6R1_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F6R1_FB27                        CAN_F6R1_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F6R1_FB28_Pos                    (28U)                             
-#define CAN_F6R1_FB28_Msk                    (0x1U << CAN_F6R1_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F6R1_FB28                        CAN_F6R1_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F6R1_FB29_Pos                    (29U)                             
-#define CAN_F6R1_FB29_Msk                    (0x1U << CAN_F6R1_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F6R1_FB29                        CAN_F6R1_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F6R1_FB30_Pos                    (30U)                             
-#define CAN_F6R1_FB30_Msk                    (0x1U << CAN_F6R1_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F6R1_FB30                        CAN_F6R1_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F6R1_FB31_Pos                    (31U)                             
-#define CAN_F6R1_FB31_Msk                    (0x1U << CAN_F6R1_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F6R1_FB31                        CAN_F6R1_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define CAN_F7R1_FB0_Pos                     (0U)                              
-#define CAN_F7R1_FB0_Msk                     (0x1U << CAN_F7R1_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F7R1_FB0                         CAN_F7R1_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F7R1_FB1_Pos                     (1U)                              
-#define CAN_F7R1_FB1_Msk                     (0x1U << CAN_F7R1_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F7R1_FB1                         CAN_F7R1_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F7R1_FB2_Pos                     (2U)                              
-#define CAN_F7R1_FB2_Msk                     (0x1U << CAN_F7R1_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F7R1_FB2                         CAN_F7R1_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F7R1_FB3_Pos                     (3U)                              
-#define CAN_F7R1_FB3_Msk                     (0x1U << CAN_F7R1_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F7R1_FB3                         CAN_F7R1_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F7R1_FB4_Pos                     (4U)                              
-#define CAN_F7R1_FB4_Msk                     (0x1U << CAN_F7R1_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F7R1_FB4                         CAN_F7R1_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F7R1_FB5_Pos                     (5U)                              
-#define CAN_F7R1_FB5_Msk                     (0x1U << CAN_F7R1_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F7R1_FB5                         CAN_F7R1_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F7R1_FB6_Pos                     (6U)                              
-#define CAN_F7R1_FB6_Msk                     (0x1U << CAN_F7R1_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F7R1_FB6                         CAN_F7R1_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F7R1_FB7_Pos                     (7U)                              
-#define CAN_F7R1_FB7_Msk                     (0x1U << CAN_F7R1_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F7R1_FB7                         CAN_F7R1_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F7R1_FB8_Pos                     (8U)                              
-#define CAN_F7R1_FB8_Msk                     (0x1U << CAN_F7R1_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F7R1_FB8                         CAN_F7R1_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F7R1_FB9_Pos                     (9U)                              
-#define CAN_F7R1_FB9_Msk                     (0x1U << CAN_F7R1_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F7R1_FB9                         CAN_F7R1_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F7R1_FB10_Pos                    (10U)                             
-#define CAN_F7R1_FB10_Msk                    (0x1U << CAN_F7R1_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F7R1_FB10                        CAN_F7R1_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F7R1_FB11_Pos                    (11U)                             
-#define CAN_F7R1_FB11_Msk                    (0x1U << CAN_F7R1_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F7R1_FB11                        CAN_F7R1_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F7R1_FB12_Pos                    (12U)                             
-#define CAN_F7R1_FB12_Msk                    (0x1U << CAN_F7R1_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F7R1_FB12                        CAN_F7R1_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F7R1_FB13_Pos                    (13U)                             
-#define CAN_F7R1_FB13_Msk                    (0x1U << CAN_F7R1_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F7R1_FB13                        CAN_F7R1_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F7R1_FB14_Pos                    (14U)                             
-#define CAN_F7R1_FB14_Msk                    (0x1U << CAN_F7R1_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F7R1_FB14                        CAN_F7R1_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F7R1_FB15_Pos                    (15U)                             
-#define CAN_F7R1_FB15_Msk                    (0x1U << CAN_F7R1_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F7R1_FB15                        CAN_F7R1_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F7R1_FB16_Pos                    (16U)                             
-#define CAN_F7R1_FB16_Msk                    (0x1U << CAN_F7R1_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F7R1_FB16                        CAN_F7R1_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F7R1_FB17_Pos                    (17U)                             
-#define CAN_F7R1_FB17_Msk                    (0x1U << CAN_F7R1_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F7R1_FB17                        CAN_F7R1_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F7R1_FB18_Pos                    (18U)                             
-#define CAN_F7R1_FB18_Msk                    (0x1U << CAN_F7R1_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F7R1_FB18                        CAN_F7R1_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F7R1_FB19_Pos                    (19U)                             
-#define CAN_F7R1_FB19_Msk                    (0x1U << CAN_F7R1_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F7R1_FB19                        CAN_F7R1_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F7R1_FB20_Pos                    (20U)                             
-#define CAN_F7R1_FB20_Msk                    (0x1U << CAN_F7R1_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F7R1_FB20                        CAN_F7R1_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F7R1_FB21_Pos                    (21U)                             
-#define CAN_F7R1_FB21_Msk                    (0x1U << CAN_F7R1_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F7R1_FB21                        CAN_F7R1_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F7R1_FB22_Pos                    (22U)                             
-#define CAN_F7R1_FB22_Msk                    (0x1U << CAN_F7R1_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F7R1_FB22                        CAN_F7R1_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F7R1_FB23_Pos                    (23U)                             
-#define CAN_F7R1_FB23_Msk                    (0x1U << CAN_F7R1_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F7R1_FB23                        CAN_F7R1_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F7R1_FB24_Pos                    (24U)                             
-#define CAN_F7R1_FB24_Msk                    (0x1U << CAN_F7R1_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F7R1_FB24                        CAN_F7R1_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F7R1_FB25_Pos                    (25U)                             
-#define CAN_F7R1_FB25_Msk                    (0x1U << CAN_F7R1_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F7R1_FB25                        CAN_F7R1_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F7R1_FB26_Pos                    (26U)                             
-#define CAN_F7R1_FB26_Msk                    (0x1U << CAN_F7R1_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F7R1_FB26                        CAN_F7R1_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F7R1_FB27_Pos                    (27U)                             
-#define CAN_F7R1_FB27_Msk                    (0x1U << CAN_F7R1_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F7R1_FB27                        CAN_F7R1_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F7R1_FB28_Pos                    (28U)                             
-#define CAN_F7R1_FB28_Msk                    (0x1U << CAN_F7R1_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F7R1_FB28                        CAN_F7R1_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F7R1_FB29_Pos                    (29U)                             
-#define CAN_F7R1_FB29_Msk                    (0x1U << CAN_F7R1_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F7R1_FB29                        CAN_F7R1_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F7R1_FB30_Pos                    (30U)                             
-#define CAN_F7R1_FB30_Msk                    (0x1U << CAN_F7R1_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F7R1_FB30                        CAN_F7R1_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F7R1_FB31_Pos                    (31U)                             
-#define CAN_F7R1_FB31_Msk                    (0x1U << CAN_F7R1_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F7R1_FB31                        CAN_F7R1_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define CAN_F8R1_FB0_Pos                     (0U)                              
-#define CAN_F8R1_FB0_Msk                     (0x1U << CAN_F8R1_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F8R1_FB0                         CAN_F8R1_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F8R1_FB1_Pos                     (1U)                              
-#define CAN_F8R1_FB1_Msk                     (0x1U << CAN_F8R1_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F8R1_FB1                         CAN_F8R1_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F8R1_FB2_Pos                     (2U)                              
-#define CAN_F8R1_FB2_Msk                     (0x1U << CAN_F8R1_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F8R1_FB2                         CAN_F8R1_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F8R1_FB3_Pos                     (3U)                              
-#define CAN_F8R1_FB3_Msk                     (0x1U << CAN_F8R1_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F8R1_FB3                         CAN_F8R1_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F8R1_FB4_Pos                     (4U)                              
-#define CAN_F8R1_FB4_Msk                     (0x1U << CAN_F8R1_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F8R1_FB4                         CAN_F8R1_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F8R1_FB5_Pos                     (5U)                              
-#define CAN_F8R1_FB5_Msk                     (0x1U << CAN_F8R1_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F8R1_FB5                         CAN_F8R1_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F8R1_FB6_Pos                     (6U)                              
-#define CAN_F8R1_FB6_Msk                     (0x1U << CAN_F8R1_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F8R1_FB6                         CAN_F8R1_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F8R1_FB7_Pos                     (7U)                              
-#define CAN_F8R1_FB7_Msk                     (0x1U << CAN_F8R1_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F8R1_FB7                         CAN_F8R1_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F8R1_FB8_Pos                     (8U)                              
-#define CAN_F8R1_FB8_Msk                     (0x1U << CAN_F8R1_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F8R1_FB8                         CAN_F8R1_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F8R1_FB9_Pos                     (9U)                              
-#define CAN_F8R1_FB9_Msk                     (0x1U << CAN_F8R1_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F8R1_FB9                         CAN_F8R1_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F8R1_FB10_Pos                    (10U)                             
-#define CAN_F8R1_FB10_Msk                    (0x1U << CAN_F8R1_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F8R1_FB10                        CAN_F8R1_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F8R1_FB11_Pos                    (11U)                             
-#define CAN_F8R1_FB11_Msk                    (0x1U << CAN_F8R1_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F8R1_FB11                        CAN_F8R1_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F8R1_FB12_Pos                    (12U)                             
-#define CAN_F8R1_FB12_Msk                    (0x1U << CAN_F8R1_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F8R1_FB12                        CAN_F8R1_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F8R1_FB13_Pos                    (13U)                             
-#define CAN_F8R1_FB13_Msk                    (0x1U << CAN_F8R1_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F8R1_FB13                        CAN_F8R1_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F8R1_FB14_Pos                    (14U)                             
-#define CAN_F8R1_FB14_Msk                    (0x1U << CAN_F8R1_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F8R1_FB14                        CAN_F8R1_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F8R1_FB15_Pos                    (15U)                             
-#define CAN_F8R1_FB15_Msk                    (0x1U << CAN_F8R1_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F8R1_FB15                        CAN_F8R1_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F8R1_FB16_Pos                    (16U)                             
-#define CAN_F8R1_FB16_Msk                    (0x1U << CAN_F8R1_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F8R1_FB16                        CAN_F8R1_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F8R1_FB17_Pos                    (17U)                             
-#define CAN_F8R1_FB17_Msk                    (0x1U << CAN_F8R1_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F8R1_FB17                        CAN_F8R1_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F8R1_FB18_Pos                    (18U)                             
-#define CAN_F8R1_FB18_Msk                    (0x1U << CAN_F8R1_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F8R1_FB18                        CAN_F8R1_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F8R1_FB19_Pos                    (19U)                             
-#define CAN_F8R1_FB19_Msk                    (0x1U << CAN_F8R1_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F8R1_FB19                        CAN_F8R1_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F8R1_FB20_Pos                    (20U)                             
-#define CAN_F8R1_FB20_Msk                    (0x1U << CAN_F8R1_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F8R1_FB20                        CAN_F8R1_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F8R1_FB21_Pos                    (21U)                             
-#define CAN_F8R1_FB21_Msk                    (0x1U << CAN_F8R1_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F8R1_FB21                        CAN_F8R1_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F8R1_FB22_Pos                    (22U)                             
-#define CAN_F8R1_FB22_Msk                    (0x1U << CAN_F8R1_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F8R1_FB22                        CAN_F8R1_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F8R1_FB23_Pos                    (23U)                             
-#define CAN_F8R1_FB23_Msk                    (0x1U << CAN_F8R1_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F8R1_FB23                        CAN_F8R1_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F8R1_FB24_Pos                    (24U)                             
-#define CAN_F8R1_FB24_Msk                    (0x1U << CAN_F8R1_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F8R1_FB24                        CAN_F8R1_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F8R1_FB25_Pos                    (25U)                             
-#define CAN_F8R1_FB25_Msk                    (0x1U << CAN_F8R1_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F8R1_FB25                        CAN_F8R1_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F8R1_FB26_Pos                    (26U)                             
-#define CAN_F8R1_FB26_Msk                    (0x1U << CAN_F8R1_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F8R1_FB26                        CAN_F8R1_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F8R1_FB27_Pos                    (27U)                             
-#define CAN_F8R1_FB27_Msk                    (0x1U << CAN_F8R1_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F8R1_FB27                        CAN_F8R1_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F8R1_FB28_Pos                    (28U)                             
-#define CAN_F8R1_FB28_Msk                    (0x1U << CAN_F8R1_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F8R1_FB28                        CAN_F8R1_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F8R1_FB29_Pos                    (29U)                             
-#define CAN_F8R1_FB29_Msk                    (0x1U << CAN_F8R1_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F8R1_FB29                        CAN_F8R1_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F8R1_FB30_Pos                    (30U)                             
-#define CAN_F8R1_FB30_Msk                    (0x1U << CAN_F8R1_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F8R1_FB30                        CAN_F8R1_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F8R1_FB31_Pos                    (31U)                             
-#define CAN_F8R1_FB31_Msk                    (0x1U << CAN_F8R1_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F8R1_FB31                        CAN_F8R1_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define CAN_F9R1_FB0_Pos                     (0U)                              
-#define CAN_F9R1_FB0_Msk                     (0x1U << CAN_F9R1_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F9R1_FB0                         CAN_F9R1_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F9R1_FB1_Pos                     (1U)                              
-#define CAN_F9R1_FB1_Msk                     (0x1U << CAN_F9R1_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F9R1_FB1                         CAN_F9R1_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F9R1_FB2_Pos                     (2U)                              
-#define CAN_F9R1_FB2_Msk                     (0x1U << CAN_F9R1_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F9R1_FB2                         CAN_F9R1_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F9R1_FB3_Pos                     (3U)                              
-#define CAN_F9R1_FB3_Msk                     (0x1U << CAN_F9R1_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F9R1_FB3                         CAN_F9R1_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F9R1_FB4_Pos                     (4U)                              
-#define CAN_F9R1_FB4_Msk                     (0x1U << CAN_F9R1_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F9R1_FB4                         CAN_F9R1_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F9R1_FB5_Pos                     (5U)                              
-#define CAN_F9R1_FB5_Msk                     (0x1U << CAN_F9R1_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F9R1_FB5                         CAN_F9R1_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F9R1_FB6_Pos                     (6U)                              
-#define CAN_F9R1_FB6_Msk                     (0x1U << CAN_F9R1_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F9R1_FB6                         CAN_F9R1_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F9R1_FB7_Pos                     (7U)                              
-#define CAN_F9R1_FB7_Msk                     (0x1U << CAN_F9R1_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F9R1_FB7                         CAN_F9R1_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F9R1_FB8_Pos                     (8U)                              
-#define CAN_F9R1_FB8_Msk                     (0x1U << CAN_F9R1_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F9R1_FB8                         CAN_F9R1_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F9R1_FB9_Pos                     (9U)                              
-#define CAN_F9R1_FB9_Msk                     (0x1U << CAN_F9R1_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F9R1_FB9                         CAN_F9R1_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F9R1_FB10_Pos                    (10U)                             
-#define CAN_F9R1_FB10_Msk                    (0x1U << CAN_F9R1_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F9R1_FB10                        CAN_F9R1_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F9R1_FB11_Pos                    (11U)                             
-#define CAN_F9R1_FB11_Msk                    (0x1U << CAN_F9R1_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F9R1_FB11                        CAN_F9R1_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F9R1_FB12_Pos                    (12U)                             
-#define CAN_F9R1_FB12_Msk                    (0x1U << CAN_F9R1_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F9R1_FB12                        CAN_F9R1_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F9R1_FB13_Pos                    (13U)                             
-#define CAN_F9R1_FB13_Msk                    (0x1U << CAN_F9R1_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F9R1_FB13                        CAN_F9R1_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F9R1_FB14_Pos                    (14U)                             
-#define CAN_F9R1_FB14_Msk                    (0x1U << CAN_F9R1_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F9R1_FB14                        CAN_F9R1_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F9R1_FB15_Pos                    (15U)                             
-#define CAN_F9R1_FB15_Msk                    (0x1U << CAN_F9R1_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F9R1_FB15                        CAN_F9R1_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F9R1_FB16_Pos                    (16U)                             
-#define CAN_F9R1_FB16_Msk                    (0x1U << CAN_F9R1_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F9R1_FB16                        CAN_F9R1_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F9R1_FB17_Pos                    (17U)                             
-#define CAN_F9R1_FB17_Msk                    (0x1U << CAN_F9R1_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F9R1_FB17                        CAN_F9R1_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F9R1_FB18_Pos                    (18U)                             
-#define CAN_F9R1_FB18_Msk                    (0x1U << CAN_F9R1_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F9R1_FB18                        CAN_F9R1_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F9R1_FB19_Pos                    (19U)                             
-#define CAN_F9R1_FB19_Msk                    (0x1U << CAN_F9R1_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F9R1_FB19                        CAN_F9R1_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F9R1_FB20_Pos                    (20U)                             
-#define CAN_F9R1_FB20_Msk                    (0x1U << CAN_F9R1_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F9R1_FB20                        CAN_F9R1_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F9R1_FB21_Pos                    (21U)                             
-#define CAN_F9R1_FB21_Msk                    (0x1U << CAN_F9R1_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F9R1_FB21                        CAN_F9R1_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F9R1_FB22_Pos                    (22U)                             
-#define CAN_F9R1_FB22_Msk                    (0x1U << CAN_F9R1_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F9R1_FB22                        CAN_F9R1_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F9R1_FB23_Pos                    (23U)                             
-#define CAN_F9R1_FB23_Msk                    (0x1U << CAN_F9R1_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F9R1_FB23                        CAN_F9R1_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F9R1_FB24_Pos                    (24U)                             
-#define CAN_F9R1_FB24_Msk                    (0x1U << CAN_F9R1_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F9R1_FB24                        CAN_F9R1_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F9R1_FB25_Pos                    (25U)                             
-#define CAN_F9R1_FB25_Msk                    (0x1U << CAN_F9R1_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F9R1_FB25                        CAN_F9R1_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F9R1_FB26_Pos                    (26U)                             
-#define CAN_F9R1_FB26_Msk                    (0x1U << CAN_F9R1_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F9R1_FB26                        CAN_F9R1_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F9R1_FB27_Pos                    (27U)                             
-#define CAN_F9R1_FB27_Msk                    (0x1U << CAN_F9R1_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F9R1_FB27                        CAN_F9R1_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F9R1_FB28_Pos                    (28U)                             
-#define CAN_F9R1_FB28_Msk                    (0x1U << CAN_F9R1_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F9R1_FB28                        CAN_F9R1_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F9R1_FB29_Pos                    (29U)                             
-#define CAN_F9R1_FB29_Msk                    (0x1U << CAN_F9R1_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F9R1_FB29                        CAN_F9R1_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F9R1_FB30_Pos                    (30U)                             
-#define CAN_F9R1_FB30_Msk                    (0x1U << CAN_F9R1_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F9R1_FB30                        CAN_F9R1_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F9R1_FB31_Pos                    (31U)                             
-#define CAN_F9R1_FB31_Msk                    (0x1U << CAN_F9R1_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F9R1_FB31                        CAN_F9R1_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define CAN_F10R1_FB0_Pos                    (0U)                              
-#define CAN_F10R1_FB0_Msk                    (0x1U << CAN_F10R1_FB0_Pos)       /*!< 0x00000001 */
-#define CAN_F10R1_FB0                        CAN_F10R1_FB0_Msk                 /*!< Filter bit 0 */
-#define CAN_F10R1_FB1_Pos                    (1U)                              
-#define CAN_F10R1_FB1_Msk                    (0x1U << CAN_F10R1_FB1_Pos)       /*!< 0x00000002 */
-#define CAN_F10R1_FB1                        CAN_F10R1_FB1_Msk                 /*!< Filter bit 1 */
-#define CAN_F10R1_FB2_Pos                    (2U)                              
-#define CAN_F10R1_FB2_Msk                    (0x1U << CAN_F10R1_FB2_Pos)       /*!< 0x00000004 */
-#define CAN_F10R1_FB2                        CAN_F10R1_FB2_Msk                 /*!< Filter bit 2 */
-#define CAN_F10R1_FB3_Pos                    (3U)                              
-#define CAN_F10R1_FB3_Msk                    (0x1U << CAN_F10R1_FB3_Pos)       /*!< 0x00000008 */
-#define CAN_F10R1_FB3                        CAN_F10R1_FB3_Msk                 /*!< Filter bit 3 */
-#define CAN_F10R1_FB4_Pos                    (4U)                              
-#define CAN_F10R1_FB4_Msk                    (0x1U << CAN_F10R1_FB4_Pos)       /*!< 0x00000010 */
-#define CAN_F10R1_FB4                        CAN_F10R1_FB4_Msk                 /*!< Filter bit 4 */
-#define CAN_F10R1_FB5_Pos                    (5U)                              
-#define CAN_F10R1_FB5_Msk                    (0x1U << CAN_F10R1_FB5_Pos)       /*!< 0x00000020 */
-#define CAN_F10R1_FB5                        CAN_F10R1_FB5_Msk                 /*!< Filter bit 5 */
-#define CAN_F10R1_FB6_Pos                    (6U)                              
-#define CAN_F10R1_FB6_Msk                    (0x1U << CAN_F10R1_FB6_Pos)       /*!< 0x00000040 */
-#define CAN_F10R1_FB6                        CAN_F10R1_FB6_Msk                 /*!< Filter bit 6 */
-#define CAN_F10R1_FB7_Pos                    (7U)                              
-#define CAN_F10R1_FB7_Msk                    (0x1U << CAN_F10R1_FB7_Pos)       /*!< 0x00000080 */
-#define CAN_F10R1_FB7                        CAN_F10R1_FB7_Msk                 /*!< Filter bit 7 */
-#define CAN_F10R1_FB8_Pos                    (8U)                              
-#define CAN_F10R1_FB8_Msk                    (0x1U << CAN_F10R1_FB8_Pos)       /*!< 0x00000100 */
-#define CAN_F10R1_FB8                        CAN_F10R1_FB8_Msk                 /*!< Filter bit 8 */
-#define CAN_F10R1_FB9_Pos                    (9U)                              
-#define CAN_F10R1_FB9_Msk                    (0x1U << CAN_F10R1_FB9_Pos)       /*!< 0x00000200 */
-#define CAN_F10R1_FB9                        CAN_F10R1_FB9_Msk                 /*!< Filter bit 9 */
-#define CAN_F10R1_FB10_Pos                   (10U)                             
-#define CAN_F10R1_FB10_Msk                   (0x1U << CAN_F10R1_FB10_Pos)      /*!< 0x00000400 */
-#define CAN_F10R1_FB10                       CAN_F10R1_FB10_Msk                /*!< Filter bit 10 */
-#define CAN_F10R1_FB11_Pos                   (11U)                             
-#define CAN_F10R1_FB11_Msk                   (0x1U << CAN_F10R1_FB11_Pos)      /*!< 0x00000800 */
-#define CAN_F10R1_FB11                       CAN_F10R1_FB11_Msk                /*!< Filter bit 11 */
-#define CAN_F10R1_FB12_Pos                   (12U)                             
-#define CAN_F10R1_FB12_Msk                   (0x1U << CAN_F10R1_FB12_Pos)      /*!< 0x00001000 */
-#define CAN_F10R1_FB12                       CAN_F10R1_FB12_Msk                /*!< Filter bit 12 */
-#define CAN_F10R1_FB13_Pos                   (13U)                             
-#define CAN_F10R1_FB13_Msk                   (0x1U << CAN_F10R1_FB13_Pos)      /*!< 0x00002000 */
-#define CAN_F10R1_FB13                       CAN_F10R1_FB13_Msk                /*!< Filter bit 13 */
-#define CAN_F10R1_FB14_Pos                   (14U)                             
-#define CAN_F10R1_FB14_Msk                   (0x1U << CAN_F10R1_FB14_Pos)      /*!< 0x00004000 */
-#define CAN_F10R1_FB14                       CAN_F10R1_FB14_Msk                /*!< Filter bit 14 */
-#define CAN_F10R1_FB15_Pos                   (15U)                             
-#define CAN_F10R1_FB15_Msk                   (0x1U << CAN_F10R1_FB15_Pos)      /*!< 0x00008000 */
-#define CAN_F10R1_FB15                       CAN_F10R1_FB15_Msk                /*!< Filter bit 15 */
-#define CAN_F10R1_FB16_Pos                   (16U)                             
-#define CAN_F10R1_FB16_Msk                   (0x1U << CAN_F10R1_FB16_Pos)      /*!< 0x00010000 */
-#define CAN_F10R1_FB16                       CAN_F10R1_FB16_Msk                /*!< Filter bit 16 */
-#define CAN_F10R1_FB17_Pos                   (17U)                             
-#define CAN_F10R1_FB17_Msk                   (0x1U << CAN_F10R1_FB17_Pos)      /*!< 0x00020000 */
-#define CAN_F10R1_FB17                       CAN_F10R1_FB17_Msk                /*!< Filter bit 17 */
-#define CAN_F10R1_FB18_Pos                   (18U)                             
-#define CAN_F10R1_FB18_Msk                   (0x1U << CAN_F10R1_FB18_Pos)      /*!< 0x00040000 */
-#define CAN_F10R1_FB18                       CAN_F10R1_FB18_Msk                /*!< Filter bit 18 */
-#define CAN_F10R1_FB19_Pos                   (19U)                             
-#define CAN_F10R1_FB19_Msk                   (0x1U << CAN_F10R1_FB19_Pos)      /*!< 0x00080000 */
-#define CAN_F10R1_FB19                       CAN_F10R1_FB19_Msk                /*!< Filter bit 19 */
-#define CAN_F10R1_FB20_Pos                   (20U)                             
-#define CAN_F10R1_FB20_Msk                   (0x1U << CAN_F10R1_FB20_Pos)      /*!< 0x00100000 */
-#define CAN_F10R1_FB20                       CAN_F10R1_FB20_Msk                /*!< Filter bit 20 */
-#define CAN_F10R1_FB21_Pos                   (21U)                             
-#define CAN_F10R1_FB21_Msk                   (0x1U << CAN_F10R1_FB21_Pos)      /*!< 0x00200000 */
-#define CAN_F10R1_FB21                       CAN_F10R1_FB21_Msk                /*!< Filter bit 21 */
-#define CAN_F10R1_FB22_Pos                   (22U)                             
-#define CAN_F10R1_FB22_Msk                   (0x1U << CAN_F10R1_FB22_Pos)      /*!< 0x00400000 */
-#define CAN_F10R1_FB22                       CAN_F10R1_FB22_Msk                /*!< Filter bit 22 */
-#define CAN_F10R1_FB23_Pos                   (23U)                             
-#define CAN_F10R1_FB23_Msk                   (0x1U << CAN_F10R1_FB23_Pos)      /*!< 0x00800000 */
-#define CAN_F10R1_FB23                       CAN_F10R1_FB23_Msk                /*!< Filter bit 23 */
-#define CAN_F10R1_FB24_Pos                   (24U)                             
-#define CAN_F10R1_FB24_Msk                   (0x1U << CAN_F10R1_FB24_Pos)      /*!< 0x01000000 */
-#define CAN_F10R1_FB24                       CAN_F10R1_FB24_Msk                /*!< Filter bit 24 */
-#define CAN_F10R1_FB25_Pos                   (25U)                             
-#define CAN_F10R1_FB25_Msk                   (0x1U << CAN_F10R1_FB25_Pos)      /*!< 0x02000000 */
-#define CAN_F10R1_FB25                       CAN_F10R1_FB25_Msk                /*!< Filter bit 25 */
-#define CAN_F10R1_FB26_Pos                   (26U)                             
-#define CAN_F10R1_FB26_Msk                   (0x1U << CAN_F10R1_FB26_Pos)      /*!< 0x04000000 */
-#define CAN_F10R1_FB26                       CAN_F10R1_FB26_Msk                /*!< Filter bit 26 */
-#define CAN_F10R1_FB27_Pos                   (27U)                             
-#define CAN_F10R1_FB27_Msk                   (0x1U << CAN_F10R1_FB27_Pos)      /*!< 0x08000000 */
-#define CAN_F10R1_FB27                       CAN_F10R1_FB27_Msk                /*!< Filter bit 27 */
-#define CAN_F10R1_FB28_Pos                   (28U)                             
-#define CAN_F10R1_FB28_Msk                   (0x1U << CAN_F10R1_FB28_Pos)      /*!< 0x10000000 */
-#define CAN_F10R1_FB28                       CAN_F10R1_FB28_Msk                /*!< Filter bit 28 */
-#define CAN_F10R1_FB29_Pos                   (29U)                             
-#define CAN_F10R1_FB29_Msk                   (0x1U << CAN_F10R1_FB29_Pos)      /*!< 0x20000000 */
-#define CAN_F10R1_FB29                       CAN_F10R1_FB29_Msk                /*!< Filter bit 29 */
-#define CAN_F10R1_FB30_Pos                   (30U)                             
-#define CAN_F10R1_FB30_Msk                   (0x1U << CAN_F10R1_FB30_Pos)      /*!< 0x40000000 */
-#define CAN_F10R1_FB30                       CAN_F10R1_FB30_Msk                /*!< Filter bit 30 */
-#define CAN_F10R1_FB31_Pos                   (31U)                             
-#define CAN_F10R1_FB31_Msk                   (0x1U << CAN_F10R1_FB31_Pos)      /*!< 0x80000000 */
-#define CAN_F10R1_FB31                       CAN_F10R1_FB31_Msk                /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define CAN_F11R1_FB0_Pos                    (0U)                              
-#define CAN_F11R1_FB0_Msk                    (0x1U << CAN_F11R1_FB0_Pos)       /*!< 0x00000001 */
-#define CAN_F11R1_FB0                        CAN_F11R1_FB0_Msk                 /*!< Filter bit 0 */
-#define CAN_F11R1_FB1_Pos                    (1U)                              
-#define CAN_F11R1_FB1_Msk                    (0x1U << CAN_F11R1_FB1_Pos)       /*!< 0x00000002 */
-#define CAN_F11R1_FB1                        CAN_F11R1_FB1_Msk                 /*!< Filter bit 1 */
-#define CAN_F11R1_FB2_Pos                    (2U)                              
-#define CAN_F11R1_FB2_Msk                    (0x1U << CAN_F11R1_FB2_Pos)       /*!< 0x00000004 */
-#define CAN_F11R1_FB2                        CAN_F11R1_FB2_Msk                 /*!< Filter bit 2 */
-#define CAN_F11R1_FB3_Pos                    (3U)                              
-#define CAN_F11R1_FB3_Msk                    (0x1U << CAN_F11R1_FB3_Pos)       /*!< 0x00000008 */
-#define CAN_F11R1_FB3                        CAN_F11R1_FB3_Msk                 /*!< Filter bit 3 */
-#define CAN_F11R1_FB4_Pos                    (4U)                              
-#define CAN_F11R1_FB4_Msk                    (0x1U << CAN_F11R1_FB4_Pos)       /*!< 0x00000010 */
-#define CAN_F11R1_FB4                        CAN_F11R1_FB4_Msk                 /*!< Filter bit 4 */
-#define CAN_F11R1_FB5_Pos                    (5U)                              
-#define CAN_F11R1_FB5_Msk                    (0x1U << CAN_F11R1_FB5_Pos)       /*!< 0x00000020 */
-#define CAN_F11R1_FB5                        CAN_F11R1_FB5_Msk                 /*!< Filter bit 5 */
-#define CAN_F11R1_FB6_Pos                    (6U)                              
-#define CAN_F11R1_FB6_Msk                    (0x1U << CAN_F11R1_FB6_Pos)       /*!< 0x00000040 */
-#define CAN_F11R1_FB6                        CAN_F11R1_FB6_Msk                 /*!< Filter bit 6 */
-#define CAN_F11R1_FB7_Pos                    (7U)                              
-#define CAN_F11R1_FB7_Msk                    (0x1U << CAN_F11R1_FB7_Pos)       /*!< 0x00000080 */
-#define CAN_F11R1_FB7                        CAN_F11R1_FB7_Msk                 /*!< Filter bit 7 */
-#define CAN_F11R1_FB8_Pos                    (8U)                              
-#define CAN_F11R1_FB8_Msk                    (0x1U << CAN_F11R1_FB8_Pos)       /*!< 0x00000100 */
-#define CAN_F11R1_FB8                        CAN_F11R1_FB8_Msk                 /*!< Filter bit 8 */
-#define CAN_F11R1_FB9_Pos                    (9U)                              
-#define CAN_F11R1_FB9_Msk                    (0x1U << CAN_F11R1_FB9_Pos)       /*!< 0x00000200 */
-#define CAN_F11R1_FB9                        CAN_F11R1_FB9_Msk                 /*!< Filter bit 9 */
-#define CAN_F11R1_FB10_Pos                   (10U)                             
-#define CAN_F11R1_FB10_Msk                   (0x1U << CAN_F11R1_FB10_Pos)      /*!< 0x00000400 */
-#define CAN_F11R1_FB10                       CAN_F11R1_FB10_Msk                /*!< Filter bit 10 */
-#define CAN_F11R1_FB11_Pos                   (11U)                             
-#define CAN_F11R1_FB11_Msk                   (0x1U << CAN_F11R1_FB11_Pos)      /*!< 0x00000800 */
-#define CAN_F11R1_FB11                       CAN_F11R1_FB11_Msk                /*!< Filter bit 11 */
-#define CAN_F11R1_FB12_Pos                   (12U)                             
-#define CAN_F11R1_FB12_Msk                   (0x1U << CAN_F11R1_FB12_Pos)      /*!< 0x00001000 */
-#define CAN_F11R1_FB12                       CAN_F11R1_FB12_Msk                /*!< Filter bit 12 */
-#define CAN_F11R1_FB13_Pos                   (13U)                             
-#define CAN_F11R1_FB13_Msk                   (0x1U << CAN_F11R1_FB13_Pos)      /*!< 0x00002000 */
-#define CAN_F11R1_FB13                       CAN_F11R1_FB13_Msk                /*!< Filter bit 13 */
-#define CAN_F11R1_FB14_Pos                   (14U)                             
-#define CAN_F11R1_FB14_Msk                   (0x1U << CAN_F11R1_FB14_Pos)      /*!< 0x00004000 */
-#define CAN_F11R1_FB14                       CAN_F11R1_FB14_Msk                /*!< Filter bit 14 */
-#define CAN_F11R1_FB15_Pos                   (15U)                             
-#define CAN_F11R1_FB15_Msk                   (0x1U << CAN_F11R1_FB15_Pos)      /*!< 0x00008000 */
-#define CAN_F11R1_FB15                       CAN_F11R1_FB15_Msk                /*!< Filter bit 15 */
-#define CAN_F11R1_FB16_Pos                   (16U)                             
-#define CAN_F11R1_FB16_Msk                   (0x1U << CAN_F11R1_FB16_Pos)      /*!< 0x00010000 */
-#define CAN_F11R1_FB16                       CAN_F11R1_FB16_Msk                /*!< Filter bit 16 */
-#define CAN_F11R1_FB17_Pos                   (17U)                             
-#define CAN_F11R1_FB17_Msk                   (0x1U << CAN_F11R1_FB17_Pos)      /*!< 0x00020000 */
-#define CAN_F11R1_FB17                       CAN_F11R1_FB17_Msk                /*!< Filter bit 17 */
-#define CAN_F11R1_FB18_Pos                   (18U)                             
-#define CAN_F11R1_FB18_Msk                   (0x1U << CAN_F11R1_FB18_Pos)      /*!< 0x00040000 */
-#define CAN_F11R1_FB18                       CAN_F11R1_FB18_Msk                /*!< Filter bit 18 */
-#define CAN_F11R1_FB19_Pos                   (19U)                             
-#define CAN_F11R1_FB19_Msk                   (0x1U << CAN_F11R1_FB19_Pos)      /*!< 0x00080000 */
-#define CAN_F11R1_FB19                       CAN_F11R1_FB19_Msk                /*!< Filter bit 19 */
-#define CAN_F11R1_FB20_Pos                   (20U)                             
-#define CAN_F11R1_FB20_Msk                   (0x1U << CAN_F11R1_FB20_Pos)      /*!< 0x00100000 */
-#define CAN_F11R1_FB20                       CAN_F11R1_FB20_Msk                /*!< Filter bit 20 */
-#define CAN_F11R1_FB21_Pos                   (21U)                             
-#define CAN_F11R1_FB21_Msk                   (0x1U << CAN_F11R1_FB21_Pos)      /*!< 0x00200000 */
-#define CAN_F11R1_FB21                       CAN_F11R1_FB21_Msk                /*!< Filter bit 21 */
-#define CAN_F11R1_FB22_Pos                   (22U)                             
-#define CAN_F11R1_FB22_Msk                   (0x1U << CAN_F11R1_FB22_Pos)      /*!< 0x00400000 */
-#define CAN_F11R1_FB22                       CAN_F11R1_FB22_Msk                /*!< Filter bit 22 */
-#define CAN_F11R1_FB23_Pos                   (23U)                             
-#define CAN_F11R1_FB23_Msk                   (0x1U << CAN_F11R1_FB23_Pos)      /*!< 0x00800000 */
-#define CAN_F11R1_FB23                       CAN_F11R1_FB23_Msk                /*!< Filter bit 23 */
-#define CAN_F11R1_FB24_Pos                   (24U)                             
-#define CAN_F11R1_FB24_Msk                   (0x1U << CAN_F11R1_FB24_Pos)      /*!< 0x01000000 */
-#define CAN_F11R1_FB24                       CAN_F11R1_FB24_Msk                /*!< Filter bit 24 */
-#define CAN_F11R1_FB25_Pos                   (25U)                             
-#define CAN_F11R1_FB25_Msk                   (0x1U << CAN_F11R1_FB25_Pos)      /*!< 0x02000000 */
-#define CAN_F11R1_FB25                       CAN_F11R1_FB25_Msk                /*!< Filter bit 25 */
-#define CAN_F11R1_FB26_Pos                   (26U)                             
-#define CAN_F11R1_FB26_Msk                   (0x1U << CAN_F11R1_FB26_Pos)      /*!< 0x04000000 */
-#define CAN_F11R1_FB26                       CAN_F11R1_FB26_Msk                /*!< Filter bit 26 */
-#define CAN_F11R1_FB27_Pos                   (27U)                             
-#define CAN_F11R1_FB27_Msk                   (0x1U << CAN_F11R1_FB27_Pos)      /*!< 0x08000000 */
-#define CAN_F11R1_FB27                       CAN_F11R1_FB27_Msk                /*!< Filter bit 27 */
-#define CAN_F11R1_FB28_Pos                   (28U)                             
-#define CAN_F11R1_FB28_Msk                   (0x1U << CAN_F11R1_FB28_Pos)      /*!< 0x10000000 */
-#define CAN_F11R1_FB28                       CAN_F11R1_FB28_Msk                /*!< Filter bit 28 */
-#define CAN_F11R1_FB29_Pos                   (29U)                             
-#define CAN_F11R1_FB29_Msk                   (0x1U << CAN_F11R1_FB29_Pos)      /*!< 0x20000000 */
-#define CAN_F11R1_FB29                       CAN_F11R1_FB29_Msk                /*!< Filter bit 29 */
-#define CAN_F11R1_FB30_Pos                   (30U)                             
-#define CAN_F11R1_FB30_Msk                   (0x1U << CAN_F11R1_FB30_Pos)      /*!< 0x40000000 */
-#define CAN_F11R1_FB30                       CAN_F11R1_FB30_Msk                /*!< Filter bit 30 */
-#define CAN_F11R1_FB31_Pos                   (31U)                             
-#define CAN_F11R1_FB31_Msk                   (0x1U << CAN_F11R1_FB31_Pos)      /*!< 0x80000000 */
-#define CAN_F11R1_FB31                       CAN_F11R1_FB31_Msk                /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define CAN_F12R1_FB0_Pos                    (0U)                              
-#define CAN_F12R1_FB0_Msk                    (0x1U << CAN_F12R1_FB0_Pos)       /*!< 0x00000001 */
-#define CAN_F12R1_FB0                        CAN_F12R1_FB0_Msk                 /*!< Filter bit 0 */
-#define CAN_F12R1_FB1_Pos                    (1U)                              
-#define CAN_F12R1_FB1_Msk                    (0x1U << CAN_F12R1_FB1_Pos)       /*!< 0x00000002 */
-#define CAN_F12R1_FB1                        CAN_F12R1_FB1_Msk                 /*!< Filter bit 1 */
-#define CAN_F12R1_FB2_Pos                    (2U)                              
-#define CAN_F12R1_FB2_Msk                    (0x1U << CAN_F12R1_FB2_Pos)       /*!< 0x00000004 */
-#define CAN_F12R1_FB2                        CAN_F12R1_FB2_Msk                 /*!< Filter bit 2 */
-#define CAN_F12R1_FB3_Pos                    (3U)                              
-#define CAN_F12R1_FB3_Msk                    (0x1U << CAN_F12R1_FB3_Pos)       /*!< 0x00000008 */
-#define CAN_F12R1_FB3                        CAN_F12R1_FB3_Msk                 /*!< Filter bit 3 */
-#define CAN_F12R1_FB4_Pos                    (4U)                              
-#define CAN_F12R1_FB4_Msk                    (0x1U << CAN_F12R1_FB4_Pos)       /*!< 0x00000010 */
-#define CAN_F12R1_FB4                        CAN_F12R1_FB4_Msk                 /*!< Filter bit 4 */
-#define CAN_F12R1_FB5_Pos                    (5U)                              
-#define CAN_F12R1_FB5_Msk                    (0x1U << CAN_F12R1_FB5_Pos)       /*!< 0x00000020 */
-#define CAN_F12R1_FB5                        CAN_F12R1_FB5_Msk                 /*!< Filter bit 5 */
-#define CAN_F12R1_FB6_Pos                    (6U)                              
-#define CAN_F12R1_FB6_Msk                    (0x1U << CAN_F12R1_FB6_Pos)       /*!< 0x00000040 */
-#define CAN_F12R1_FB6                        CAN_F12R1_FB6_Msk                 /*!< Filter bit 6 */
-#define CAN_F12R1_FB7_Pos                    (7U)                              
-#define CAN_F12R1_FB7_Msk                    (0x1U << CAN_F12R1_FB7_Pos)       /*!< 0x00000080 */
-#define CAN_F12R1_FB7                        CAN_F12R1_FB7_Msk                 /*!< Filter bit 7 */
-#define CAN_F12R1_FB8_Pos                    (8U)                              
-#define CAN_F12R1_FB8_Msk                    (0x1U << CAN_F12R1_FB8_Pos)       /*!< 0x00000100 */
-#define CAN_F12R1_FB8                        CAN_F12R1_FB8_Msk                 /*!< Filter bit 8 */
-#define CAN_F12R1_FB9_Pos                    (9U)                              
-#define CAN_F12R1_FB9_Msk                    (0x1U << CAN_F12R1_FB9_Pos)       /*!< 0x00000200 */
-#define CAN_F12R1_FB9                        CAN_F12R1_FB9_Msk                 /*!< Filter bit 9 */
-#define CAN_F12R1_FB10_Pos                   (10U)                             
-#define CAN_F12R1_FB10_Msk                   (0x1U << CAN_F12R1_FB10_Pos)      /*!< 0x00000400 */
-#define CAN_F12R1_FB10                       CAN_F12R1_FB10_Msk                /*!< Filter bit 10 */
-#define CAN_F12R1_FB11_Pos                   (11U)                             
-#define CAN_F12R1_FB11_Msk                   (0x1U << CAN_F12R1_FB11_Pos)      /*!< 0x00000800 */
-#define CAN_F12R1_FB11                       CAN_F12R1_FB11_Msk                /*!< Filter bit 11 */
-#define CAN_F12R1_FB12_Pos                   (12U)                             
-#define CAN_F12R1_FB12_Msk                   (0x1U << CAN_F12R1_FB12_Pos)      /*!< 0x00001000 */
-#define CAN_F12R1_FB12                       CAN_F12R1_FB12_Msk                /*!< Filter bit 12 */
-#define CAN_F12R1_FB13_Pos                   (13U)                             
-#define CAN_F12R1_FB13_Msk                   (0x1U << CAN_F12R1_FB13_Pos)      /*!< 0x00002000 */
-#define CAN_F12R1_FB13                       CAN_F12R1_FB13_Msk                /*!< Filter bit 13 */
-#define CAN_F12R1_FB14_Pos                   (14U)                             
-#define CAN_F12R1_FB14_Msk                   (0x1U << CAN_F12R1_FB14_Pos)      /*!< 0x00004000 */
-#define CAN_F12R1_FB14                       CAN_F12R1_FB14_Msk                /*!< Filter bit 14 */
-#define CAN_F12R1_FB15_Pos                   (15U)                             
-#define CAN_F12R1_FB15_Msk                   (0x1U << CAN_F12R1_FB15_Pos)      /*!< 0x00008000 */
-#define CAN_F12R1_FB15                       CAN_F12R1_FB15_Msk                /*!< Filter bit 15 */
-#define CAN_F12R1_FB16_Pos                   (16U)                             
-#define CAN_F12R1_FB16_Msk                   (0x1U << CAN_F12R1_FB16_Pos)      /*!< 0x00010000 */
-#define CAN_F12R1_FB16                       CAN_F12R1_FB16_Msk                /*!< Filter bit 16 */
-#define CAN_F12R1_FB17_Pos                   (17U)                             
-#define CAN_F12R1_FB17_Msk                   (0x1U << CAN_F12R1_FB17_Pos)      /*!< 0x00020000 */
-#define CAN_F12R1_FB17                       CAN_F12R1_FB17_Msk                /*!< Filter bit 17 */
-#define CAN_F12R1_FB18_Pos                   (18U)                             
-#define CAN_F12R1_FB18_Msk                   (0x1U << CAN_F12R1_FB18_Pos)      /*!< 0x00040000 */
-#define CAN_F12R1_FB18                       CAN_F12R1_FB18_Msk                /*!< Filter bit 18 */
-#define CAN_F12R1_FB19_Pos                   (19U)                             
-#define CAN_F12R1_FB19_Msk                   (0x1U << CAN_F12R1_FB19_Pos)      /*!< 0x00080000 */
-#define CAN_F12R1_FB19                       CAN_F12R1_FB19_Msk                /*!< Filter bit 19 */
-#define CAN_F12R1_FB20_Pos                   (20U)                             
-#define CAN_F12R1_FB20_Msk                   (0x1U << CAN_F12R1_FB20_Pos)      /*!< 0x00100000 */
-#define CAN_F12R1_FB20                       CAN_F12R1_FB20_Msk                /*!< Filter bit 20 */
-#define CAN_F12R1_FB21_Pos                   (21U)                             
-#define CAN_F12R1_FB21_Msk                   (0x1U << CAN_F12R1_FB21_Pos)      /*!< 0x00200000 */
-#define CAN_F12R1_FB21                       CAN_F12R1_FB21_Msk                /*!< Filter bit 21 */
-#define CAN_F12R1_FB22_Pos                   (22U)                             
-#define CAN_F12R1_FB22_Msk                   (0x1U << CAN_F12R1_FB22_Pos)      /*!< 0x00400000 */
-#define CAN_F12R1_FB22                       CAN_F12R1_FB22_Msk                /*!< Filter bit 22 */
-#define CAN_F12R1_FB23_Pos                   (23U)                             
-#define CAN_F12R1_FB23_Msk                   (0x1U << CAN_F12R1_FB23_Pos)      /*!< 0x00800000 */
-#define CAN_F12R1_FB23                       CAN_F12R1_FB23_Msk                /*!< Filter bit 23 */
-#define CAN_F12R1_FB24_Pos                   (24U)                             
-#define CAN_F12R1_FB24_Msk                   (0x1U << CAN_F12R1_FB24_Pos)      /*!< 0x01000000 */
-#define CAN_F12R1_FB24                       CAN_F12R1_FB24_Msk                /*!< Filter bit 24 */
-#define CAN_F12R1_FB25_Pos                   (25U)                             
-#define CAN_F12R1_FB25_Msk                   (0x1U << CAN_F12R1_FB25_Pos)      /*!< 0x02000000 */
-#define CAN_F12R1_FB25                       CAN_F12R1_FB25_Msk                /*!< Filter bit 25 */
-#define CAN_F12R1_FB26_Pos                   (26U)                             
-#define CAN_F12R1_FB26_Msk                   (0x1U << CAN_F12R1_FB26_Pos)      /*!< 0x04000000 */
-#define CAN_F12R1_FB26                       CAN_F12R1_FB26_Msk                /*!< Filter bit 26 */
-#define CAN_F12R1_FB27_Pos                   (27U)                             
-#define CAN_F12R1_FB27_Msk                   (0x1U << CAN_F12R1_FB27_Pos)      /*!< 0x08000000 */
-#define CAN_F12R1_FB27                       CAN_F12R1_FB27_Msk                /*!< Filter bit 27 */
-#define CAN_F12R1_FB28_Pos                   (28U)                             
-#define CAN_F12R1_FB28_Msk                   (0x1U << CAN_F12R1_FB28_Pos)      /*!< 0x10000000 */
-#define CAN_F12R1_FB28                       CAN_F12R1_FB28_Msk                /*!< Filter bit 28 */
-#define CAN_F12R1_FB29_Pos                   (29U)                             
-#define CAN_F12R1_FB29_Msk                   (0x1U << CAN_F12R1_FB29_Pos)      /*!< 0x20000000 */
-#define CAN_F12R1_FB29                       CAN_F12R1_FB29_Msk                /*!< Filter bit 29 */
-#define CAN_F12R1_FB30_Pos                   (30U)                             
-#define CAN_F12R1_FB30_Msk                   (0x1U << CAN_F12R1_FB30_Pos)      /*!< 0x40000000 */
-#define CAN_F12R1_FB30                       CAN_F12R1_FB30_Msk                /*!< Filter bit 30 */
-#define CAN_F12R1_FB31_Pos                   (31U)                             
-#define CAN_F12R1_FB31_Msk                   (0x1U << CAN_F12R1_FB31_Pos)      /*!< 0x80000000 */
-#define CAN_F12R1_FB31                       CAN_F12R1_FB31_Msk                /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define CAN_F13R1_FB0_Pos                    (0U)                              
-#define CAN_F13R1_FB0_Msk                    (0x1U << CAN_F13R1_FB0_Pos)       /*!< 0x00000001 */
-#define CAN_F13R1_FB0                        CAN_F13R1_FB0_Msk                 /*!< Filter bit 0 */
-#define CAN_F13R1_FB1_Pos                    (1U)                              
-#define CAN_F13R1_FB1_Msk                    (0x1U << CAN_F13R1_FB1_Pos)       /*!< 0x00000002 */
-#define CAN_F13R1_FB1                        CAN_F13R1_FB1_Msk                 /*!< Filter bit 1 */
-#define CAN_F13R1_FB2_Pos                    (2U)                              
-#define CAN_F13R1_FB2_Msk                    (0x1U << CAN_F13R1_FB2_Pos)       /*!< 0x00000004 */
-#define CAN_F13R1_FB2                        CAN_F13R1_FB2_Msk                 /*!< Filter bit 2 */
-#define CAN_F13R1_FB3_Pos                    (3U)                              
-#define CAN_F13R1_FB3_Msk                    (0x1U << CAN_F13R1_FB3_Pos)       /*!< 0x00000008 */
-#define CAN_F13R1_FB3                        CAN_F13R1_FB3_Msk                 /*!< Filter bit 3 */
-#define CAN_F13R1_FB4_Pos                    (4U)                              
-#define CAN_F13R1_FB4_Msk                    (0x1U << CAN_F13R1_FB4_Pos)       /*!< 0x00000010 */
-#define CAN_F13R1_FB4                        CAN_F13R1_FB4_Msk                 /*!< Filter bit 4 */
-#define CAN_F13R1_FB5_Pos                    (5U)                              
-#define CAN_F13R1_FB5_Msk                    (0x1U << CAN_F13R1_FB5_Pos)       /*!< 0x00000020 */
-#define CAN_F13R1_FB5                        CAN_F13R1_FB5_Msk                 /*!< Filter bit 5 */
-#define CAN_F13R1_FB6_Pos                    (6U)                              
-#define CAN_F13R1_FB6_Msk                    (0x1U << CAN_F13R1_FB6_Pos)       /*!< 0x00000040 */
-#define CAN_F13R1_FB6                        CAN_F13R1_FB6_Msk                 /*!< Filter bit 6 */
-#define CAN_F13R1_FB7_Pos                    (7U)                              
-#define CAN_F13R1_FB7_Msk                    (0x1U << CAN_F13R1_FB7_Pos)       /*!< 0x00000080 */
-#define CAN_F13R1_FB7                        CAN_F13R1_FB7_Msk                 /*!< Filter bit 7 */
-#define CAN_F13R1_FB8_Pos                    (8U)                              
-#define CAN_F13R1_FB8_Msk                    (0x1U << CAN_F13R1_FB8_Pos)       /*!< 0x00000100 */
-#define CAN_F13R1_FB8                        CAN_F13R1_FB8_Msk                 /*!< Filter bit 8 */
-#define CAN_F13R1_FB9_Pos                    (9U)                              
-#define CAN_F13R1_FB9_Msk                    (0x1U << CAN_F13R1_FB9_Pos)       /*!< 0x00000200 */
-#define CAN_F13R1_FB9                        CAN_F13R1_FB9_Msk                 /*!< Filter bit 9 */
-#define CAN_F13R1_FB10_Pos                   (10U)                             
-#define CAN_F13R1_FB10_Msk                   (0x1U << CAN_F13R1_FB10_Pos)      /*!< 0x00000400 */
-#define CAN_F13R1_FB10                       CAN_F13R1_FB10_Msk                /*!< Filter bit 10 */
-#define CAN_F13R1_FB11_Pos                   (11U)                             
-#define CAN_F13R1_FB11_Msk                   (0x1U << CAN_F13R1_FB11_Pos)      /*!< 0x00000800 */
-#define CAN_F13R1_FB11                       CAN_F13R1_FB11_Msk                /*!< Filter bit 11 */
-#define CAN_F13R1_FB12_Pos                   (12U)                             
-#define CAN_F13R1_FB12_Msk                   (0x1U << CAN_F13R1_FB12_Pos)      /*!< 0x00001000 */
-#define CAN_F13R1_FB12                       CAN_F13R1_FB12_Msk                /*!< Filter bit 12 */
-#define CAN_F13R1_FB13_Pos                   (13U)                             
-#define CAN_F13R1_FB13_Msk                   (0x1U << CAN_F13R1_FB13_Pos)      /*!< 0x00002000 */
-#define CAN_F13R1_FB13                       CAN_F13R1_FB13_Msk                /*!< Filter bit 13 */
-#define CAN_F13R1_FB14_Pos                   (14U)                             
-#define CAN_F13R1_FB14_Msk                   (0x1U << CAN_F13R1_FB14_Pos)      /*!< 0x00004000 */
-#define CAN_F13R1_FB14                       CAN_F13R1_FB14_Msk                /*!< Filter bit 14 */
-#define CAN_F13R1_FB15_Pos                   (15U)                             
-#define CAN_F13R1_FB15_Msk                   (0x1U << CAN_F13R1_FB15_Pos)      /*!< 0x00008000 */
-#define CAN_F13R1_FB15                       CAN_F13R1_FB15_Msk                /*!< Filter bit 15 */
-#define CAN_F13R1_FB16_Pos                   (16U)                             
-#define CAN_F13R1_FB16_Msk                   (0x1U << CAN_F13R1_FB16_Pos)      /*!< 0x00010000 */
-#define CAN_F13R1_FB16                       CAN_F13R1_FB16_Msk                /*!< Filter bit 16 */
-#define CAN_F13R1_FB17_Pos                   (17U)                             
-#define CAN_F13R1_FB17_Msk                   (0x1U << CAN_F13R1_FB17_Pos)      /*!< 0x00020000 */
-#define CAN_F13R1_FB17                       CAN_F13R1_FB17_Msk                /*!< Filter bit 17 */
-#define CAN_F13R1_FB18_Pos                   (18U)                             
-#define CAN_F13R1_FB18_Msk                   (0x1U << CAN_F13R1_FB18_Pos)      /*!< 0x00040000 */
-#define CAN_F13R1_FB18                       CAN_F13R1_FB18_Msk                /*!< Filter bit 18 */
-#define CAN_F13R1_FB19_Pos                   (19U)                             
-#define CAN_F13R1_FB19_Msk                   (0x1U << CAN_F13R1_FB19_Pos)      /*!< 0x00080000 */
-#define CAN_F13R1_FB19                       CAN_F13R1_FB19_Msk                /*!< Filter bit 19 */
-#define CAN_F13R1_FB20_Pos                   (20U)                             
-#define CAN_F13R1_FB20_Msk                   (0x1U << CAN_F13R1_FB20_Pos)      /*!< 0x00100000 */
-#define CAN_F13R1_FB20                       CAN_F13R1_FB20_Msk                /*!< Filter bit 20 */
-#define CAN_F13R1_FB21_Pos                   (21U)                             
-#define CAN_F13R1_FB21_Msk                   (0x1U << CAN_F13R1_FB21_Pos)      /*!< 0x00200000 */
-#define CAN_F13R1_FB21                       CAN_F13R1_FB21_Msk                /*!< Filter bit 21 */
-#define CAN_F13R1_FB22_Pos                   (22U)                             
-#define CAN_F13R1_FB22_Msk                   (0x1U << CAN_F13R1_FB22_Pos)      /*!< 0x00400000 */
-#define CAN_F13R1_FB22                       CAN_F13R1_FB22_Msk                /*!< Filter bit 22 */
-#define CAN_F13R1_FB23_Pos                   (23U)                             
-#define CAN_F13R1_FB23_Msk                   (0x1U << CAN_F13R1_FB23_Pos)      /*!< 0x00800000 */
-#define CAN_F13R1_FB23                       CAN_F13R1_FB23_Msk                /*!< Filter bit 23 */
-#define CAN_F13R1_FB24_Pos                   (24U)                             
-#define CAN_F13R1_FB24_Msk                   (0x1U << CAN_F13R1_FB24_Pos)      /*!< 0x01000000 */
-#define CAN_F13R1_FB24                       CAN_F13R1_FB24_Msk                /*!< Filter bit 24 */
-#define CAN_F13R1_FB25_Pos                   (25U)                             
-#define CAN_F13R1_FB25_Msk                   (0x1U << CAN_F13R1_FB25_Pos)      /*!< 0x02000000 */
-#define CAN_F13R1_FB25                       CAN_F13R1_FB25_Msk                /*!< Filter bit 25 */
-#define CAN_F13R1_FB26_Pos                   (26U)                             
-#define CAN_F13R1_FB26_Msk                   (0x1U << CAN_F13R1_FB26_Pos)      /*!< 0x04000000 */
-#define CAN_F13R1_FB26                       CAN_F13R1_FB26_Msk                /*!< Filter bit 26 */
-#define CAN_F13R1_FB27_Pos                   (27U)                             
-#define CAN_F13R1_FB27_Msk                   (0x1U << CAN_F13R1_FB27_Pos)      /*!< 0x08000000 */
-#define CAN_F13R1_FB27                       CAN_F13R1_FB27_Msk                /*!< Filter bit 27 */
-#define CAN_F13R1_FB28_Pos                   (28U)                             
-#define CAN_F13R1_FB28_Msk                   (0x1U << CAN_F13R1_FB28_Pos)      /*!< 0x10000000 */
-#define CAN_F13R1_FB28                       CAN_F13R1_FB28_Msk                /*!< Filter bit 28 */
-#define CAN_F13R1_FB29_Pos                   (29U)                             
-#define CAN_F13R1_FB29_Msk                   (0x1U << CAN_F13R1_FB29_Pos)      /*!< 0x20000000 */
-#define CAN_F13R1_FB29                       CAN_F13R1_FB29_Msk                /*!< Filter bit 29 */
-#define CAN_F13R1_FB30_Pos                   (30U)                             
-#define CAN_F13R1_FB30_Msk                   (0x1U << CAN_F13R1_FB30_Pos)      /*!< 0x40000000 */
-#define CAN_F13R1_FB30                       CAN_F13R1_FB30_Msk                /*!< Filter bit 30 */
-#define CAN_F13R1_FB31_Pos                   (31U)                             
-#define CAN_F13R1_FB31_Msk                   (0x1U << CAN_F13R1_FB31_Pos)      /*!< 0x80000000 */
-#define CAN_F13R1_FB31                       CAN_F13R1_FB31_Msk                /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define CAN_F0R2_FB0_Pos                     (0U)                              
-#define CAN_F0R2_FB0_Msk                     (0x1U << CAN_F0R2_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F0R2_FB0                         CAN_F0R2_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F0R2_FB1_Pos                     (1U)                              
-#define CAN_F0R2_FB1_Msk                     (0x1U << CAN_F0R2_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F0R2_FB1                         CAN_F0R2_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F0R2_FB2_Pos                     (2U)                              
-#define CAN_F0R2_FB2_Msk                     (0x1U << CAN_F0R2_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F0R2_FB2                         CAN_F0R2_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F0R2_FB3_Pos                     (3U)                              
-#define CAN_F0R2_FB3_Msk                     (0x1U << CAN_F0R2_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F0R2_FB3                         CAN_F0R2_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F0R2_FB4_Pos                     (4U)                              
-#define CAN_F0R2_FB4_Msk                     (0x1U << CAN_F0R2_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F0R2_FB4                         CAN_F0R2_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F0R2_FB5_Pos                     (5U)                              
-#define CAN_F0R2_FB5_Msk                     (0x1U << CAN_F0R2_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F0R2_FB5                         CAN_F0R2_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F0R2_FB6_Pos                     (6U)                              
-#define CAN_F0R2_FB6_Msk                     (0x1U << CAN_F0R2_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F0R2_FB6                         CAN_F0R2_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F0R2_FB7_Pos                     (7U)                              
-#define CAN_F0R2_FB7_Msk                     (0x1U << CAN_F0R2_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F0R2_FB7                         CAN_F0R2_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F0R2_FB8_Pos                     (8U)                              
-#define CAN_F0R2_FB8_Msk                     (0x1U << CAN_F0R2_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F0R2_FB8                         CAN_F0R2_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F0R2_FB9_Pos                     (9U)                              
-#define CAN_F0R2_FB9_Msk                     (0x1U << CAN_F0R2_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F0R2_FB9                         CAN_F0R2_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F0R2_FB10_Pos                    (10U)                             
-#define CAN_F0R2_FB10_Msk                    (0x1U << CAN_F0R2_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F0R2_FB10                        CAN_F0R2_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F0R2_FB11_Pos                    (11U)                             
-#define CAN_F0R2_FB11_Msk                    (0x1U << CAN_F0R2_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F0R2_FB11                        CAN_F0R2_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F0R2_FB12_Pos                    (12U)                             
-#define CAN_F0R2_FB12_Msk                    (0x1U << CAN_F0R2_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F0R2_FB12                        CAN_F0R2_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F0R2_FB13_Pos                    (13U)                             
-#define CAN_F0R2_FB13_Msk                    (0x1U << CAN_F0R2_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F0R2_FB13                        CAN_F0R2_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F0R2_FB14_Pos                    (14U)                             
-#define CAN_F0R2_FB14_Msk                    (0x1U << CAN_F0R2_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F0R2_FB14                        CAN_F0R2_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F0R2_FB15_Pos                    (15U)                             
-#define CAN_F0R2_FB15_Msk                    (0x1U << CAN_F0R2_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F0R2_FB15                        CAN_F0R2_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F0R2_FB16_Pos                    (16U)                             
-#define CAN_F0R2_FB16_Msk                    (0x1U << CAN_F0R2_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F0R2_FB16                        CAN_F0R2_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F0R2_FB17_Pos                    (17U)                             
-#define CAN_F0R2_FB17_Msk                    (0x1U << CAN_F0R2_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F0R2_FB17                        CAN_F0R2_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F0R2_FB18_Pos                    (18U)                             
-#define CAN_F0R2_FB18_Msk                    (0x1U << CAN_F0R2_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F0R2_FB18                        CAN_F0R2_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F0R2_FB19_Pos                    (19U)                             
-#define CAN_F0R2_FB19_Msk                    (0x1U << CAN_F0R2_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F0R2_FB19                        CAN_F0R2_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F0R2_FB20_Pos                    (20U)                             
-#define CAN_F0R2_FB20_Msk                    (0x1U << CAN_F0R2_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F0R2_FB20                        CAN_F0R2_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F0R2_FB21_Pos                    (21U)                             
-#define CAN_F0R2_FB21_Msk                    (0x1U << CAN_F0R2_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F0R2_FB21                        CAN_F0R2_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F0R2_FB22_Pos                    (22U)                             
-#define CAN_F0R2_FB22_Msk                    (0x1U << CAN_F0R2_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F0R2_FB22                        CAN_F0R2_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F0R2_FB23_Pos                    (23U)                             
-#define CAN_F0R2_FB23_Msk                    (0x1U << CAN_F0R2_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F0R2_FB23                        CAN_F0R2_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F0R2_FB24_Pos                    (24U)                             
-#define CAN_F0R2_FB24_Msk                    (0x1U << CAN_F0R2_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F0R2_FB24                        CAN_F0R2_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F0R2_FB25_Pos                    (25U)                             
-#define CAN_F0R2_FB25_Msk                    (0x1U << CAN_F0R2_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F0R2_FB25                        CAN_F0R2_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F0R2_FB26_Pos                    (26U)                             
-#define CAN_F0R2_FB26_Msk                    (0x1U << CAN_F0R2_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F0R2_FB26                        CAN_F0R2_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F0R2_FB27_Pos                    (27U)                             
-#define CAN_F0R2_FB27_Msk                    (0x1U << CAN_F0R2_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F0R2_FB27                        CAN_F0R2_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F0R2_FB28_Pos                    (28U)                             
-#define CAN_F0R2_FB28_Msk                    (0x1U << CAN_F0R2_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F0R2_FB28                        CAN_F0R2_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F0R2_FB29_Pos                    (29U)                             
-#define CAN_F0R2_FB29_Msk                    (0x1U << CAN_F0R2_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F0R2_FB29                        CAN_F0R2_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F0R2_FB30_Pos                    (30U)                             
-#define CAN_F0R2_FB30_Msk                    (0x1U << CAN_F0R2_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F0R2_FB30                        CAN_F0R2_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F0R2_FB31_Pos                    (31U)                             
-#define CAN_F0R2_FB31_Msk                    (0x1U << CAN_F0R2_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F0R2_FB31                        CAN_F0R2_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define CAN_F1R2_FB0_Pos                     (0U)                              
-#define CAN_F1R2_FB0_Msk                     (0x1U << CAN_F1R2_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F1R2_FB0                         CAN_F1R2_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F1R2_FB1_Pos                     (1U)                              
-#define CAN_F1R2_FB1_Msk                     (0x1U << CAN_F1R2_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F1R2_FB1                         CAN_F1R2_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F1R2_FB2_Pos                     (2U)                              
-#define CAN_F1R2_FB2_Msk                     (0x1U << CAN_F1R2_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F1R2_FB2                         CAN_F1R2_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F1R2_FB3_Pos                     (3U)                              
-#define CAN_F1R2_FB3_Msk                     (0x1U << CAN_F1R2_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F1R2_FB3                         CAN_F1R2_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F1R2_FB4_Pos                     (4U)                              
-#define CAN_F1R2_FB4_Msk                     (0x1U << CAN_F1R2_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F1R2_FB4                         CAN_F1R2_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F1R2_FB5_Pos                     (5U)                              
-#define CAN_F1R2_FB5_Msk                     (0x1U << CAN_F1R2_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F1R2_FB5                         CAN_F1R2_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F1R2_FB6_Pos                     (6U)                              
-#define CAN_F1R2_FB6_Msk                     (0x1U << CAN_F1R2_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F1R2_FB6                         CAN_F1R2_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F1R2_FB7_Pos                     (7U)                              
-#define CAN_F1R2_FB7_Msk                     (0x1U << CAN_F1R2_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F1R2_FB7                         CAN_F1R2_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F1R2_FB8_Pos                     (8U)                              
-#define CAN_F1R2_FB8_Msk                     (0x1U << CAN_F1R2_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F1R2_FB8                         CAN_F1R2_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F1R2_FB9_Pos                     (9U)                              
-#define CAN_F1R2_FB9_Msk                     (0x1U << CAN_F1R2_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F1R2_FB9                         CAN_F1R2_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F1R2_FB10_Pos                    (10U)                             
-#define CAN_F1R2_FB10_Msk                    (0x1U << CAN_F1R2_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F1R2_FB10                        CAN_F1R2_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F1R2_FB11_Pos                    (11U)                             
-#define CAN_F1R2_FB11_Msk                    (0x1U << CAN_F1R2_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F1R2_FB11                        CAN_F1R2_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F1R2_FB12_Pos                    (12U)                             
-#define CAN_F1R2_FB12_Msk                    (0x1U << CAN_F1R2_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F1R2_FB12                        CAN_F1R2_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F1R2_FB13_Pos                    (13U)                             
-#define CAN_F1R2_FB13_Msk                    (0x1U << CAN_F1R2_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F1R2_FB13                        CAN_F1R2_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F1R2_FB14_Pos                    (14U)                             
-#define CAN_F1R2_FB14_Msk                    (0x1U << CAN_F1R2_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F1R2_FB14                        CAN_F1R2_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F1R2_FB15_Pos                    (15U)                             
-#define CAN_F1R2_FB15_Msk                    (0x1U << CAN_F1R2_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F1R2_FB15                        CAN_F1R2_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F1R2_FB16_Pos                    (16U)                             
-#define CAN_F1R2_FB16_Msk                    (0x1U << CAN_F1R2_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F1R2_FB16                        CAN_F1R2_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F1R2_FB17_Pos                    (17U)                             
-#define CAN_F1R2_FB17_Msk                    (0x1U << CAN_F1R2_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F1R2_FB17                        CAN_F1R2_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F1R2_FB18_Pos                    (18U)                             
-#define CAN_F1R2_FB18_Msk                    (0x1U << CAN_F1R2_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F1R2_FB18                        CAN_F1R2_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F1R2_FB19_Pos                    (19U)                             
-#define CAN_F1R2_FB19_Msk                    (0x1U << CAN_F1R2_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F1R2_FB19                        CAN_F1R2_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F1R2_FB20_Pos                    (20U)                             
-#define CAN_F1R2_FB20_Msk                    (0x1U << CAN_F1R2_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F1R2_FB20                        CAN_F1R2_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F1R2_FB21_Pos                    (21U)                             
-#define CAN_F1R2_FB21_Msk                    (0x1U << CAN_F1R2_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F1R2_FB21                        CAN_F1R2_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F1R2_FB22_Pos                    (22U)                             
-#define CAN_F1R2_FB22_Msk                    (0x1U << CAN_F1R2_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F1R2_FB22                        CAN_F1R2_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F1R2_FB23_Pos                    (23U)                             
-#define CAN_F1R2_FB23_Msk                    (0x1U << CAN_F1R2_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F1R2_FB23                        CAN_F1R2_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F1R2_FB24_Pos                    (24U)                             
-#define CAN_F1R2_FB24_Msk                    (0x1U << CAN_F1R2_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F1R2_FB24                        CAN_F1R2_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F1R2_FB25_Pos                    (25U)                             
-#define CAN_F1R2_FB25_Msk                    (0x1U << CAN_F1R2_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F1R2_FB25                        CAN_F1R2_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F1R2_FB26_Pos                    (26U)                             
-#define CAN_F1R2_FB26_Msk                    (0x1U << CAN_F1R2_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F1R2_FB26                        CAN_F1R2_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F1R2_FB27_Pos                    (27U)                             
-#define CAN_F1R2_FB27_Msk                    (0x1U << CAN_F1R2_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F1R2_FB27                        CAN_F1R2_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F1R2_FB28_Pos                    (28U)                             
-#define CAN_F1R2_FB28_Msk                    (0x1U << CAN_F1R2_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F1R2_FB28                        CAN_F1R2_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F1R2_FB29_Pos                    (29U)                             
-#define CAN_F1R2_FB29_Msk                    (0x1U << CAN_F1R2_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F1R2_FB29                        CAN_F1R2_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F1R2_FB30_Pos                    (30U)                             
-#define CAN_F1R2_FB30_Msk                    (0x1U << CAN_F1R2_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F1R2_FB30                        CAN_F1R2_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F1R2_FB31_Pos                    (31U)                             
-#define CAN_F1R2_FB31_Msk                    (0x1U << CAN_F1R2_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F1R2_FB31                        CAN_F1R2_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define CAN_F2R2_FB0_Pos                     (0U)                              
-#define CAN_F2R2_FB0_Msk                     (0x1U << CAN_F2R2_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F2R2_FB0                         CAN_F2R2_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F2R2_FB1_Pos                     (1U)                              
-#define CAN_F2R2_FB1_Msk                     (0x1U << CAN_F2R2_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F2R2_FB1                         CAN_F2R2_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F2R2_FB2_Pos                     (2U)                              
-#define CAN_F2R2_FB2_Msk                     (0x1U << CAN_F2R2_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F2R2_FB2                         CAN_F2R2_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F2R2_FB3_Pos                     (3U)                              
-#define CAN_F2R2_FB3_Msk                     (0x1U << CAN_F2R2_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F2R2_FB3                         CAN_F2R2_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F2R2_FB4_Pos                     (4U)                              
-#define CAN_F2R2_FB4_Msk                     (0x1U << CAN_F2R2_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F2R2_FB4                         CAN_F2R2_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F2R2_FB5_Pos                     (5U)                              
-#define CAN_F2R2_FB5_Msk                     (0x1U << CAN_F2R2_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F2R2_FB5                         CAN_F2R2_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F2R2_FB6_Pos                     (6U)                              
-#define CAN_F2R2_FB6_Msk                     (0x1U << CAN_F2R2_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F2R2_FB6                         CAN_F2R2_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F2R2_FB7_Pos                     (7U)                              
-#define CAN_F2R2_FB7_Msk                     (0x1U << CAN_F2R2_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F2R2_FB7                         CAN_F2R2_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F2R2_FB8_Pos                     (8U)                              
-#define CAN_F2R2_FB8_Msk                     (0x1U << CAN_F2R2_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F2R2_FB8                         CAN_F2R2_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F2R2_FB9_Pos                     (9U)                              
-#define CAN_F2R2_FB9_Msk                     (0x1U << CAN_F2R2_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F2R2_FB9                         CAN_F2R2_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F2R2_FB10_Pos                    (10U)                             
-#define CAN_F2R2_FB10_Msk                    (0x1U << CAN_F2R2_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F2R2_FB10                        CAN_F2R2_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F2R2_FB11_Pos                    (11U)                             
-#define CAN_F2R2_FB11_Msk                    (0x1U << CAN_F2R2_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F2R2_FB11                        CAN_F2R2_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F2R2_FB12_Pos                    (12U)                             
-#define CAN_F2R2_FB12_Msk                    (0x1U << CAN_F2R2_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F2R2_FB12                        CAN_F2R2_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F2R2_FB13_Pos                    (13U)                             
-#define CAN_F2R2_FB13_Msk                    (0x1U << CAN_F2R2_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F2R2_FB13                        CAN_F2R2_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F2R2_FB14_Pos                    (14U)                             
-#define CAN_F2R2_FB14_Msk                    (0x1U << CAN_F2R2_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F2R2_FB14                        CAN_F2R2_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F2R2_FB15_Pos                    (15U)                             
-#define CAN_F2R2_FB15_Msk                    (0x1U << CAN_F2R2_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F2R2_FB15                        CAN_F2R2_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F2R2_FB16_Pos                    (16U)                             
-#define CAN_F2R2_FB16_Msk                    (0x1U << CAN_F2R2_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F2R2_FB16                        CAN_F2R2_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F2R2_FB17_Pos                    (17U)                             
-#define CAN_F2R2_FB17_Msk                    (0x1U << CAN_F2R2_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F2R2_FB17                        CAN_F2R2_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F2R2_FB18_Pos                    (18U)                             
-#define CAN_F2R2_FB18_Msk                    (0x1U << CAN_F2R2_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F2R2_FB18                        CAN_F2R2_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F2R2_FB19_Pos                    (19U)                             
-#define CAN_F2R2_FB19_Msk                    (0x1U << CAN_F2R2_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F2R2_FB19                        CAN_F2R2_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F2R2_FB20_Pos                    (20U)                             
-#define CAN_F2R2_FB20_Msk                    (0x1U << CAN_F2R2_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F2R2_FB20                        CAN_F2R2_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F2R2_FB21_Pos                    (21U)                             
-#define CAN_F2R2_FB21_Msk                    (0x1U << CAN_F2R2_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F2R2_FB21                        CAN_F2R2_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F2R2_FB22_Pos                    (22U)                             
-#define CAN_F2R2_FB22_Msk                    (0x1U << CAN_F2R2_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F2R2_FB22                        CAN_F2R2_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F2R2_FB23_Pos                    (23U)                             
-#define CAN_F2R2_FB23_Msk                    (0x1U << CAN_F2R2_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F2R2_FB23                        CAN_F2R2_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F2R2_FB24_Pos                    (24U)                             
-#define CAN_F2R2_FB24_Msk                    (0x1U << CAN_F2R2_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F2R2_FB24                        CAN_F2R2_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F2R2_FB25_Pos                    (25U)                             
-#define CAN_F2R2_FB25_Msk                    (0x1U << CAN_F2R2_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F2R2_FB25                        CAN_F2R2_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F2R2_FB26_Pos                    (26U)                             
-#define CAN_F2R2_FB26_Msk                    (0x1U << CAN_F2R2_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F2R2_FB26                        CAN_F2R2_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F2R2_FB27_Pos                    (27U)                             
-#define CAN_F2R2_FB27_Msk                    (0x1U << CAN_F2R2_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F2R2_FB27                        CAN_F2R2_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F2R2_FB28_Pos                    (28U)                             
-#define CAN_F2R2_FB28_Msk                    (0x1U << CAN_F2R2_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F2R2_FB28                        CAN_F2R2_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F2R2_FB29_Pos                    (29U)                             
-#define CAN_F2R2_FB29_Msk                    (0x1U << CAN_F2R2_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F2R2_FB29                        CAN_F2R2_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F2R2_FB30_Pos                    (30U)                             
-#define CAN_F2R2_FB30_Msk                    (0x1U << CAN_F2R2_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F2R2_FB30                        CAN_F2R2_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F2R2_FB31_Pos                    (31U)                             
-#define CAN_F2R2_FB31_Msk                    (0x1U << CAN_F2R2_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F2R2_FB31                        CAN_F2R2_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define CAN_F3R2_FB0_Pos                     (0U)                              
-#define CAN_F3R2_FB0_Msk                     (0x1U << CAN_F3R2_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F3R2_FB0                         CAN_F3R2_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F3R2_FB1_Pos                     (1U)                              
-#define CAN_F3R2_FB1_Msk                     (0x1U << CAN_F3R2_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F3R2_FB1                         CAN_F3R2_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F3R2_FB2_Pos                     (2U)                              
-#define CAN_F3R2_FB2_Msk                     (0x1U << CAN_F3R2_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F3R2_FB2                         CAN_F3R2_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F3R2_FB3_Pos                     (3U)                              
-#define CAN_F3R2_FB3_Msk                     (0x1U << CAN_F3R2_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F3R2_FB3                         CAN_F3R2_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F3R2_FB4_Pos                     (4U)                              
-#define CAN_F3R2_FB4_Msk                     (0x1U << CAN_F3R2_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F3R2_FB4                         CAN_F3R2_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F3R2_FB5_Pos                     (5U)                              
-#define CAN_F3R2_FB5_Msk                     (0x1U << CAN_F3R2_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F3R2_FB5                         CAN_F3R2_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F3R2_FB6_Pos                     (6U)                              
-#define CAN_F3R2_FB6_Msk                     (0x1U << CAN_F3R2_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F3R2_FB6                         CAN_F3R2_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F3R2_FB7_Pos                     (7U)                              
-#define CAN_F3R2_FB7_Msk                     (0x1U << CAN_F3R2_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F3R2_FB7                         CAN_F3R2_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F3R2_FB8_Pos                     (8U)                              
-#define CAN_F3R2_FB8_Msk                     (0x1U << CAN_F3R2_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F3R2_FB8                         CAN_F3R2_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F3R2_FB9_Pos                     (9U)                              
-#define CAN_F3R2_FB9_Msk                     (0x1U << CAN_F3R2_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F3R2_FB9                         CAN_F3R2_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F3R2_FB10_Pos                    (10U)                             
-#define CAN_F3R2_FB10_Msk                    (0x1U << CAN_F3R2_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F3R2_FB10                        CAN_F3R2_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F3R2_FB11_Pos                    (11U)                             
-#define CAN_F3R2_FB11_Msk                    (0x1U << CAN_F3R2_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F3R2_FB11                        CAN_F3R2_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F3R2_FB12_Pos                    (12U)                             
-#define CAN_F3R2_FB12_Msk                    (0x1U << CAN_F3R2_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F3R2_FB12                        CAN_F3R2_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F3R2_FB13_Pos                    (13U)                             
-#define CAN_F3R2_FB13_Msk                    (0x1U << CAN_F3R2_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F3R2_FB13                        CAN_F3R2_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F3R2_FB14_Pos                    (14U)                             
-#define CAN_F3R2_FB14_Msk                    (0x1U << CAN_F3R2_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F3R2_FB14                        CAN_F3R2_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F3R2_FB15_Pos                    (15U)                             
-#define CAN_F3R2_FB15_Msk                    (0x1U << CAN_F3R2_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F3R2_FB15                        CAN_F3R2_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F3R2_FB16_Pos                    (16U)                             
-#define CAN_F3R2_FB16_Msk                    (0x1U << CAN_F3R2_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F3R2_FB16                        CAN_F3R2_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F3R2_FB17_Pos                    (17U)                             
-#define CAN_F3R2_FB17_Msk                    (0x1U << CAN_F3R2_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F3R2_FB17                        CAN_F3R2_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F3R2_FB18_Pos                    (18U)                             
-#define CAN_F3R2_FB18_Msk                    (0x1U << CAN_F3R2_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F3R2_FB18                        CAN_F3R2_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F3R2_FB19_Pos                    (19U)                             
-#define CAN_F3R2_FB19_Msk                    (0x1U << CAN_F3R2_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F3R2_FB19                        CAN_F3R2_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F3R2_FB20_Pos                    (20U)                             
-#define CAN_F3R2_FB20_Msk                    (0x1U << CAN_F3R2_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F3R2_FB20                        CAN_F3R2_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F3R2_FB21_Pos                    (21U)                             
-#define CAN_F3R2_FB21_Msk                    (0x1U << CAN_F3R2_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F3R2_FB21                        CAN_F3R2_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F3R2_FB22_Pos                    (22U)                             
-#define CAN_F3R2_FB22_Msk                    (0x1U << CAN_F3R2_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F3R2_FB22                        CAN_F3R2_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F3R2_FB23_Pos                    (23U)                             
-#define CAN_F3R2_FB23_Msk                    (0x1U << CAN_F3R2_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F3R2_FB23                        CAN_F3R2_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F3R2_FB24_Pos                    (24U)                             
-#define CAN_F3R2_FB24_Msk                    (0x1U << CAN_F3R2_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F3R2_FB24                        CAN_F3R2_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F3R2_FB25_Pos                    (25U)                             
-#define CAN_F3R2_FB25_Msk                    (0x1U << CAN_F3R2_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F3R2_FB25                        CAN_F3R2_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F3R2_FB26_Pos                    (26U)                             
-#define CAN_F3R2_FB26_Msk                    (0x1U << CAN_F3R2_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F3R2_FB26                        CAN_F3R2_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F3R2_FB27_Pos                    (27U)                             
-#define CAN_F3R2_FB27_Msk                    (0x1U << CAN_F3R2_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F3R2_FB27                        CAN_F3R2_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F3R2_FB28_Pos                    (28U)                             
-#define CAN_F3R2_FB28_Msk                    (0x1U << CAN_F3R2_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F3R2_FB28                        CAN_F3R2_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F3R2_FB29_Pos                    (29U)                             
-#define CAN_F3R2_FB29_Msk                    (0x1U << CAN_F3R2_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F3R2_FB29                        CAN_F3R2_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F3R2_FB30_Pos                    (30U)                             
-#define CAN_F3R2_FB30_Msk                    (0x1U << CAN_F3R2_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F3R2_FB30                        CAN_F3R2_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F3R2_FB31_Pos                    (31U)                             
-#define CAN_F3R2_FB31_Msk                    (0x1U << CAN_F3R2_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F3R2_FB31                        CAN_F3R2_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define CAN_F4R2_FB0_Pos                     (0U)                              
-#define CAN_F4R2_FB0_Msk                     (0x1U << CAN_F4R2_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F4R2_FB0                         CAN_F4R2_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F4R2_FB1_Pos                     (1U)                              
-#define CAN_F4R2_FB1_Msk                     (0x1U << CAN_F4R2_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F4R2_FB1                         CAN_F4R2_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F4R2_FB2_Pos                     (2U)                              
-#define CAN_F4R2_FB2_Msk                     (0x1U << CAN_F4R2_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F4R2_FB2                         CAN_F4R2_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F4R2_FB3_Pos                     (3U)                              
-#define CAN_F4R2_FB3_Msk                     (0x1U << CAN_F4R2_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F4R2_FB3                         CAN_F4R2_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F4R2_FB4_Pos                     (4U)                              
-#define CAN_F4R2_FB4_Msk                     (0x1U << CAN_F4R2_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F4R2_FB4                         CAN_F4R2_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F4R2_FB5_Pos                     (5U)                              
-#define CAN_F4R2_FB5_Msk                     (0x1U << CAN_F4R2_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F4R2_FB5                         CAN_F4R2_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F4R2_FB6_Pos                     (6U)                              
-#define CAN_F4R2_FB6_Msk                     (0x1U << CAN_F4R2_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F4R2_FB6                         CAN_F4R2_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F4R2_FB7_Pos                     (7U)                              
-#define CAN_F4R2_FB7_Msk                     (0x1U << CAN_F4R2_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F4R2_FB7                         CAN_F4R2_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F4R2_FB8_Pos                     (8U)                              
-#define CAN_F4R2_FB8_Msk                     (0x1U << CAN_F4R2_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F4R2_FB8                         CAN_F4R2_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F4R2_FB9_Pos                     (9U)                              
-#define CAN_F4R2_FB9_Msk                     (0x1U << CAN_F4R2_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F4R2_FB9                         CAN_F4R2_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F4R2_FB10_Pos                    (10U)                             
-#define CAN_F4R2_FB10_Msk                    (0x1U << CAN_F4R2_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F4R2_FB10                        CAN_F4R2_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F4R2_FB11_Pos                    (11U)                             
-#define CAN_F4R2_FB11_Msk                    (0x1U << CAN_F4R2_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F4R2_FB11                        CAN_F4R2_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F4R2_FB12_Pos                    (12U)                             
-#define CAN_F4R2_FB12_Msk                    (0x1U << CAN_F4R2_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F4R2_FB12                        CAN_F4R2_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F4R2_FB13_Pos                    (13U)                             
-#define CAN_F4R2_FB13_Msk                    (0x1U << CAN_F4R2_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F4R2_FB13                        CAN_F4R2_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F4R2_FB14_Pos                    (14U)                             
-#define CAN_F4R2_FB14_Msk                    (0x1U << CAN_F4R2_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F4R2_FB14                        CAN_F4R2_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F4R2_FB15_Pos                    (15U)                             
-#define CAN_F4R2_FB15_Msk                    (0x1U << CAN_F4R2_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F4R2_FB15                        CAN_F4R2_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F4R2_FB16_Pos                    (16U)                             
-#define CAN_F4R2_FB16_Msk                    (0x1U << CAN_F4R2_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F4R2_FB16                        CAN_F4R2_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F4R2_FB17_Pos                    (17U)                             
-#define CAN_F4R2_FB17_Msk                    (0x1U << CAN_F4R2_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F4R2_FB17                        CAN_F4R2_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F4R2_FB18_Pos                    (18U)                             
-#define CAN_F4R2_FB18_Msk                    (0x1U << CAN_F4R2_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F4R2_FB18                        CAN_F4R2_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F4R2_FB19_Pos                    (19U)                             
-#define CAN_F4R2_FB19_Msk                    (0x1U << CAN_F4R2_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F4R2_FB19                        CAN_F4R2_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F4R2_FB20_Pos                    (20U)                             
-#define CAN_F4R2_FB20_Msk                    (0x1U << CAN_F4R2_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F4R2_FB20                        CAN_F4R2_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F4R2_FB21_Pos                    (21U)                             
-#define CAN_F4R2_FB21_Msk                    (0x1U << CAN_F4R2_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F4R2_FB21                        CAN_F4R2_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F4R2_FB22_Pos                    (22U)                             
-#define CAN_F4R2_FB22_Msk                    (0x1U << CAN_F4R2_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F4R2_FB22                        CAN_F4R2_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F4R2_FB23_Pos                    (23U)                             
-#define CAN_F4R2_FB23_Msk                    (0x1U << CAN_F4R2_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F4R2_FB23                        CAN_F4R2_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F4R2_FB24_Pos                    (24U)                             
-#define CAN_F4R2_FB24_Msk                    (0x1U << CAN_F4R2_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F4R2_FB24                        CAN_F4R2_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F4R2_FB25_Pos                    (25U)                             
-#define CAN_F4R2_FB25_Msk                    (0x1U << CAN_F4R2_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F4R2_FB25                        CAN_F4R2_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F4R2_FB26_Pos                    (26U)                             
-#define CAN_F4R2_FB26_Msk                    (0x1U << CAN_F4R2_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F4R2_FB26                        CAN_F4R2_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F4R2_FB27_Pos                    (27U)                             
-#define CAN_F4R2_FB27_Msk                    (0x1U << CAN_F4R2_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F4R2_FB27                        CAN_F4R2_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F4R2_FB28_Pos                    (28U)                             
-#define CAN_F4R2_FB28_Msk                    (0x1U << CAN_F4R2_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F4R2_FB28                        CAN_F4R2_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F4R2_FB29_Pos                    (29U)                             
-#define CAN_F4R2_FB29_Msk                    (0x1U << CAN_F4R2_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F4R2_FB29                        CAN_F4R2_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F4R2_FB30_Pos                    (30U)                             
-#define CAN_F4R2_FB30_Msk                    (0x1U << CAN_F4R2_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F4R2_FB30                        CAN_F4R2_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F4R2_FB31_Pos                    (31U)                             
-#define CAN_F4R2_FB31_Msk                    (0x1U << CAN_F4R2_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F4R2_FB31                        CAN_F4R2_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define CAN_F5R2_FB0_Pos                     (0U)                              
-#define CAN_F5R2_FB0_Msk                     (0x1U << CAN_F5R2_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F5R2_FB0                         CAN_F5R2_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F5R2_FB1_Pos                     (1U)                              
-#define CAN_F5R2_FB1_Msk                     (0x1U << CAN_F5R2_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F5R2_FB1                         CAN_F5R2_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F5R2_FB2_Pos                     (2U)                              
-#define CAN_F5R2_FB2_Msk                     (0x1U << CAN_F5R2_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F5R2_FB2                         CAN_F5R2_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F5R2_FB3_Pos                     (3U)                              
-#define CAN_F5R2_FB3_Msk                     (0x1U << CAN_F5R2_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F5R2_FB3                         CAN_F5R2_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F5R2_FB4_Pos                     (4U)                              
-#define CAN_F5R2_FB4_Msk                     (0x1U << CAN_F5R2_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F5R2_FB4                         CAN_F5R2_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F5R2_FB5_Pos                     (5U)                              
-#define CAN_F5R2_FB5_Msk                     (0x1U << CAN_F5R2_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F5R2_FB5                         CAN_F5R2_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F5R2_FB6_Pos                     (6U)                              
-#define CAN_F5R2_FB6_Msk                     (0x1U << CAN_F5R2_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F5R2_FB6                         CAN_F5R2_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F5R2_FB7_Pos                     (7U)                              
-#define CAN_F5R2_FB7_Msk                     (0x1U << CAN_F5R2_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F5R2_FB7                         CAN_F5R2_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F5R2_FB8_Pos                     (8U)                              
-#define CAN_F5R2_FB8_Msk                     (0x1U << CAN_F5R2_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F5R2_FB8                         CAN_F5R2_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F5R2_FB9_Pos                     (9U)                              
-#define CAN_F5R2_FB9_Msk                     (0x1U << CAN_F5R2_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F5R2_FB9                         CAN_F5R2_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F5R2_FB10_Pos                    (10U)                             
-#define CAN_F5R2_FB10_Msk                    (0x1U << CAN_F5R2_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F5R2_FB10                        CAN_F5R2_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F5R2_FB11_Pos                    (11U)                             
-#define CAN_F5R2_FB11_Msk                    (0x1U << CAN_F5R2_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F5R2_FB11                        CAN_F5R2_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F5R2_FB12_Pos                    (12U)                             
-#define CAN_F5R2_FB12_Msk                    (0x1U << CAN_F5R2_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F5R2_FB12                        CAN_F5R2_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F5R2_FB13_Pos                    (13U)                             
-#define CAN_F5R2_FB13_Msk                    (0x1U << CAN_F5R2_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F5R2_FB13                        CAN_F5R2_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F5R2_FB14_Pos                    (14U)                             
-#define CAN_F5R2_FB14_Msk                    (0x1U << CAN_F5R2_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F5R2_FB14                        CAN_F5R2_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F5R2_FB15_Pos                    (15U)                             
-#define CAN_F5R2_FB15_Msk                    (0x1U << CAN_F5R2_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F5R2_FB15                        CAN_F5R2_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F5R2_FB16_Pos                    (16U)                             
-#define CAN_F5R2_FB16_Msk                    (0x1U << CAN_F5R2_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F5R2_FB16                        CAN_F5R2_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F5R2_FB17_Pos                    (17U)                             
-#define CAN_F5R2_FB17_Msk                    (0x1U << CAN_F5R2_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F5R2_FB17                        CAN_F5R2_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F5R2_FB18_Pos                    (18U)                             
-#define CAN_F5R2_FB18_Msk                    (0x1U << CAN_F5R2_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F5R2_FB18                        CAN_F5R2_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F5R2_FB19_Pos                    (19U)                             
-#define CAN_F5R2_FB19_Msk                    (0x1U << CAN_F5R2_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F5R2_FB19                        CAN_F5R2_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F5R2_FB20_Pos                    (20U)                             
-#define CAN_F5R2_FB20_Msk                    (0x1U << CAN_F5R2_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F5R2_FB20                        CAN_F5R2_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F5R2_FB21_Pos                    (21U)                             
-#define CAN_F5R2_FB21_Msk                    (0x1U << CAN_F5R2_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F5R2_FB21                        CAN_F5R2_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F5R2_FB22_Pos                    (22U)                             
-#define CAN_F5R2_FB22_Msk                    (0x1U << CAN_F5R2_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F5R2_FB22                        CAN_F5R2_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F5R2_FB23_Pos                    (23U)                             
-#define CAN_F5R2_FB23_Msk                    (0x1U << CAN_F5R2_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F5R2_FB23                        CAN_F5R2_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F5R2_FB24_Pos                    (24U)                             
-#define CAN_F5R2_FB24_Msk                    (0x1U << CAN_F5R2_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F5R2_FB24                        CAN_F5R2_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F5R2_FB25_Pos                    (25U)                             
-#define CAN_F5R2_FB25_Msk                    (0x1U << CAN_F5R2_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F5R2_FB25                        CAN_F5R2_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F5R2_FB26_Pos                    (26U)                             
-#define CAN_F5R2_FB26_Msk                    (0x1U << CAN_F5R2_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F5R2_FB26                        CAN_F5R2_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F5R2_FB27_Pos                    (27U)                             
-#define CAN_F5R2_FB27_Msk                    (0x1U << CAN_F5R2_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F5R2_FB27                        CAN_F5R2_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F5R2_FB28_Pos                    (28U)                             
-#define CAN_F5R2_FB28_Msk                    (0x1U << CAN_F5R2_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F5R2_FB28                        CAN_F5R2_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F5R2_FB29_Pos                    (29U)                             
-#define CAN_F5R2_FB29_Msk                    (0x1U << CAN_F5R2_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F5R2_FB29                        CAN_F5R2_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F5R2_FB30_Pos                    (30U)                             
-#define CAN_F5R2_FB30_Msk                    (0x1U << CAN_F5R2_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F5R2_FB30                        CAN_F5R2_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F5R2_FB31_Pos                    (31U)                             
-#define CAN_F5R2_FB31_Msk                    (0x1U << CAN_F5R2_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F5R2_FB31                        CAN_F5R2_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define CAN_F6R2_FB0_Pos                     (0U)                              
-#define CAN_F6R2_FB0_Msk                     (0x1U << CAN_F6R2_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F6R2_FB0                         CAN_F6R2_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F6R2_FB1_Pos                     (1U)                              
-#define CAN_F6R2_FB1_Msk                     (0x1U << CAN_F6R2_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F6R2_FB1                         CAN_F6R2_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F6R2_FB2_Pos                     (2U)                              
-#define CAN_F6R2_FB2_Msk                     (0x1U << CAN_F6R2_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F6R2_FB2                         CAN_F6R2_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F6R2_FB3_Pos                     (3U)                              
-#define CAN_F6R2_FB3_Msk                     (0x1U << CAN_F6R2_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F6R2_FB3                         CAN_F6R2_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F6R2_FB4_Pos                     (4U)                              
-#define CAN_F6R2_FB4_Msk                     (0x1U << CAN_F6R2_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F6R2_FB4                         CAN_F6R2_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F6R2_FB5_Pos                     (5U)                              
-#define CAN_F6R2_FB5_Msk                     (0x1U << CAN_F6R2_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F6R2_FB5                         CAN_F6R2_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F6R2_FB6_Pos                     (6U)                              
-#define CAN_F6R2_FB6_Msk                     (0x1U << CAN_F6R2_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F6R2_FB6                         CAN_F6R2_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F6R2_FB7_Pos                     (7U)                              
-#define CAN_F6R2_FB7_Msk                     (0x1U << CAN_F6R2_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F6R2_FB7                         CAN_F6R2_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F6R2_FB8_Pos                     (8U)                              
-#define CAN_F6R2_FB8_Msk                     (0x1U << CAN_F6R2_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F6R2_FB8                         CAN_F6R2_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F6R2_FB9_Pos                     (9U)                              
-#define CAN_F6R2_FB9_Msk                     (0x1U << CAN_F6R2_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F6R2_FB9                         CAN_F6R2_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F6R2_FB10_Pos                    (10U)                             
-#define CAN_F6R2_FB10_Msk                    (0x1U << CAN_F6R2_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F6R2_FB10                        CAN_F6R2_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F6R2_FB11_Pos                    (11U)                             
-#define CAN_F6R2_FB11_Msk                    (0x1U << CAN_F6R2_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F6R2_FB11                        CAN_F6R2_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F6R2_FB12_Pos                    (12U)                             
-#define CAN_F6R2_FB12_Msk                    (0x1U << CAN_F6R2_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F6R2_FB12                        CAN_F6R2_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F6R2_FB13_Pos                    (13U)                             
-#define CAN_F6R2_FB13_Msk                    (0x1U << CAN_F6R2_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F6R2_FB13                        CAN_F6R2_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F6R2_FB14_Pos                    (14U)                             
-#define CAN_F6R2_FB14_Msk                    (0x1U << CAN_F6R2_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F6R2_FB14                        CAN_F6R2_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F6R2_FB15_Pos                    (15U)                             
-#define CAN_F6R2_FB15_Msk                    (0x1U << CAN_F6R2_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F6R2_FB15                        CAN_F6R2_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F6R2_FB16_Pos                    (16U)                             
-#define CAN_F6R2_FB16_Msk                    (0x1U << CAN_F6R2_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F6R2_FB16                        CAN_F6R2_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F6R2_FB17_Pos                    (17U)                             
-#define CAN_F6R2_FB17_Msk                    (0x1U << CAN_F6R2_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F6R2_FB17                        CAN_F6R2_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F6R2_FB18_Pos                    (18U)                             
-#define CAN_F6R2_FB18_Msk                    (0x1U << CAN_F6R2_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F6R2_FB18                        CAN_F6R2_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F6R2_FB19_Pos                    (19U)                             
-#define CAN_F6R2_FB19_Msk                    (0x1U << CAN_F6R2_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F6R2_FB19                        CAN_F6R2_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F6R2_FB20_Pos                    (20U)                             
-#define CAN_F6R2_FB20_Msk                    (0x1U << CAN_F6R2_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F6R2_FB20                        CAN_F6R2_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F6R2_FB21_Pos                    (21U)                             
-#define CAN_F6R2_FB21_Msk                    (0x1U << CAN_F6R2_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F6R2_FB21                        CAN_F6R2_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F6R2_FB22_Pos                    (22U)                             
-#define CAN_F6R2_FB22_Msk                    (0x1U << CAN_F6R2_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F6R2_FB22                        CAN_F6R2_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F6R2_FB23_Pos                    (23U)                             
-#define CAN_F6R2_FB23_Msk                    (0x1U << CAN_F6R2_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F6R2_FB23                        CAN_F6R2_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F6R2_FB24_Pos                    (24U)                             
-#define CAN_F6R2_FB24_Msk                    (0x1U << CAN_F6R2_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F6R2_FB24                        CAN_F6R2_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F6R2_FB25_Pos                    (25U)                             
-#define CAN_F6R2_FB25_Msk                    (0x1U << CAN_F6R2_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F6R2_FB25                        CAN_F6R2_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F6R2_FB26_Pos                    (26U)                             
-#define CAN_F6R2_FB26_Msk                    (0x1U << CAN_F6R2_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F6R2_FB26                        CAN_F6R2_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F6R2_FB27_Pos                    (27U)                             
-#define CAN_F6R2_FB27_Msk                    (0x1U << CAN_F6R2_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F6R2_FB27                        CAN_F6R2_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F6R2_FB28_Pos                    (28U)                             
-#define CAN_F6R2_FB28_Msk                    (0x1U << CAN_F6R2_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F6R2_FB28                        CAN_F6R2_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F6R2_FB29_Pos                    (29U)                             
-#define CAN_F6R2_FB29_Msk                    (0x1U << CAN_F6R2_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F6R2_FB29                        CAN_F6R2_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F6R2_FB30_Pos                    (30U)                             
-#define CAN_F6R2_FB30_Msk                    (0x1U << CAN_F6R2_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F6R2_FB30                        CAN_F6R2_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F6R2_FB31_Pos                    (31U)                             
-#define CAN_F6R2_FB31_Msk                    (0x1U << CAN_F6R2_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F6R2_FB31                        CAN_F6R2_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define CAN_F7R2_FB0_Pos                     (0U)                              
-#define CAN_F7R2_FB0_Msk                     (0x1U << CAN_F7R2_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F7R2_FB0                         CAN_F7R2_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F7R2_FB1_Pos                     (1U)                              
-#define CAN_F7R2_FB1_Msk                     (0x1U << CAN_F7R2_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F7R2_FB1                         CAN_F7R2_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F7R2_FB2_Pos                     (2U)                              
-#define CAN_F7R2_FB2_Msk                     (0x1U << CAN_F7R2_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F7R2_FB2                         CAN_F7R2_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F7R2_FB3_Pos                     (3U)                              
-#define CAN_F7R2_FB3_Msk                     (0x1U << CAN_F7R2_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F7R2_FB3                         CAN_F7R2_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F7R2_FB4_Pos                     (4U)                              
-#define CAN_F7R2_FB4_Msk                     (0x1U << CAN_F7R2_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F7R2_FB4                         CAN_F7R2_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F7R2_FB5_Pos                     (5U)                              
-#define CAN_F7R2_FB5_Msk                     (0x1U << CAN_F7R2_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F7R2_FB5                         CAN_F7R2_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F7R2_FB6_Pos                     (6U)                              
-#define CAN_F7R2_FB6_Msk                     (0x1U << CAN_F7R2_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F7R2_FB6                         CAN_F7R2_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F7R2_FB7_Pos                     (7U)                              
-#define CAN_F7R2_FB7_Msk                     (0x1U << CAN_F7R2_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F7R2_FB7                         CAN_F7R2_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F7R2_FB8_Pos                     (8U)                              
-#define CAN_F7R2_FB8_Msk                     (0x1U << CAN_F7R2_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F7R2_FB8                         CAN_F7R2_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F7R2_FB9_Pos                     (9U)                              
-#define CAN_F7R2_FB9_Msk                     (0x1U << CAN_F7R2_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F7R2_FB9                         CAN_F7R2_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F7R2_FB10_Pos                    (10U)                             
-#define CAN_F7R2_FB10_Msk                    (0x1U << CAN_F7R2_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F7R2_FB10                        CAN_F7R2_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F7R2_FB11_Pos                    (11U)                             
-#define CAN_F7R2_FB11_Msk                    (0x1U << CAN_F7R2_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F7R2_FB11                        CAN_F7R2_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F7R2_FB12_Pos                    (12U)                             
-#define CAN_F7R2_FB12_Msk                    (0x1U << CAN_F7R2_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F7R2_FB12                        CAN_F7R2_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F7R2_FB13_Pos                    (13U)                             
-#define CAN_F7R2_FB13_Msk                    (0x1U << CAN_F7R2_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F7R2_FB13                        CAN_F7R2_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F7R2_FB14_Pos                    (14U)                             
-#define CAN_F7R2_FB14_Msk                    (0x1U << CAN_F7R2_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F7R2_FB14                        CAN_F7R2_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F7R2_FB15_Pos                    (15U)                             
-#define CAN_F7R2_FB15_Msk                    (0x1U << CAN_F7R2_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F7R2_FB15                        CAN_F7R2_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F7R2_FB16_Pos                    (16U)                             
-#define CAN_F7R2_FB16_Msk                    (0x1U << CAN_F7R2_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F7R2_FB16                        CAN_F7R2_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F7R2_FB17_Pos                    (17U)                             
-#define CAN_F7R2_FB17_Msk                    (0x1U << CAN_F7R2_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F7R2_FB17                        CAN_F7R2_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F7R2_FB18_Pos                    (18U)                             
-#define CAN_F7R2_FB18_Msk                    (0x1U << CAN_F7R2_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F7R2_FB18                        CAN_F7R2_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F7R2_FB19_Pos                    (19U)                             
-#define CAN_F7R2_FB19_Msk                    (0x1U << CAN_F7R2_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F7R2_FB19                        CAN_F7R2_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F7R2_FB20_Pos                    (20U)                             
-#define CAN_F7R2_FB20_Msk                    (0x1U << CAN_F7R2_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F7R2_FB20                        CAN_F7R2_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F7R2_FB21_Pos                    (21U)                             
-#define CAN_F7R2_FB21_Msk                    (0x1U << CAN_F7R2_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F7R2_FB21                        CAN_F7R2_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F7R2_FB22_Pos                    (22U)                             
-#define CAN_F7R2_FB22_Msk                    (0x1U << CAN_F7R2_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F7R2_FB22                        CAN_F7R2_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F7R2_FB23_Pos                    (23U)                             
-#define CAN_F7R2_FB23_Msk                    (0x1U << CAN_F7R2_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F7R2_FB23                        CAN_F7R2_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F7R2_FB24_Pos                    (24U)                             
-#define CAN_F7R2_FB24_Msk                    (0x1U << CAN_F7R2_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F7R2_FB24                        CAN_F7R2_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F7R2_FB25_Pos                    (25U)                             
-#define CAN_F7R2_FB25_Msk                    (0x1U << CAN_F7R2_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F7R2_FB25                        CAN_F7R2_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F7R2_FB26_Pos                    (26U)                             
-#define CAN_F7R2_FB26_Msk                    (0x1U << CAN_F7R2_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F7R2_FB26                        CAN_F7R2_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F7R2_FB27_Pos                    (27U)                             
-#define CAN_F7R2_FB27_Msk                    (0x1U << CAN_F7R2_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F7R2_FB27                        CAN_F7R2_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F7R2_FB28_Pos                    (28U)                             
-#define CAN_F7R2_FB28_Msk                    (0x1U << CAN_F7R2_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F7R2_FB28                        CAN_F7R2_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F7R2_FB29_Pos                    (29U)                             
-#define CAN_F7R2_FB29_Msk                    (0x1U << CAN_F7R2_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F7R2_FB29                        CAN_F7R2_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F7R2_FB30_Pos                    (30U)                             
-#define CAN_F7R2_FB30_Msk                    (0x1U << CAN_F7R2_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F7R2_FB30                        CAN_F7R2_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F7R2_FB31_Pos                    (31U)                             
-#define CAN_F7R2_FB31_Msk                    (0x1U << CAN_F7R2_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F7R2_FB31                        CAN_F7R2_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define CAN_F8R2_FB0_Pos                     (0U)                              
-#define CAN_F8R2_FB0_Msk                     (0x1U << CAN_F8R2_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F8R2_FB0                         CAN_F8R2_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F8R2_FB1_Pos                     (1U)                              
-#define CAN_F8R2_FB1_Msk                     (0x1U << CAN_F8R2_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F8R2_FB1                         CAN_F8R2_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F8R2_FB2_Pos                     (2U)                              
-#define CAN_F8R2_FB2_Msk                     (0x1U << CAN_F8R2_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F8R2_FB2                         CAN_F8R2_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F8R2_FB3_Pos                     (3U)                              
-#define CAN_F8R2_FB3_Msk                     (0x1U << CAN_F8R2_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F8R2_FB3                         CAN_F8R2_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F8R2_FB4_Pos                     (4U)                              
-#define CAN_F8R2_FB4_Msk                     (0x1U << CAN_F8R2_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F8R2_FB4                         CAN_F8R2_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F8R2_FB5_Pos                     (5U)                              
-#define CAN_F8R2_FB5_Msk                     (0x1U << CAN_F8R2_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F8R2_FB5                         CAN_F8R2_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F8R2_FB6_Pos                     (6U)                              
-#define CAN_F8R2_FB6_Msk                     (0x1U << CAN_F8R2_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F8R2_FB6                         CAN_F8R2_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F8R2_FB7_Pos                     (7U)                              
-#define CAN_F8R2_FB7_Msk                     (0x1U << CAN_F8R2_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F8R2_FB7                         CAN_F8R2_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F8R2_FB8_Pos                     (8U)                              
-#define CAN_F8R2_FB8_Msk                     (0x1U << CAN_F8R2_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F8R2_FB8                         CAN_F8R2_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F8R2_FB9_Pos                     (9U)                              
-#define CAN_F8R2_FB9_Msk                     (0x1U << CAN_F8R2_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F8R2_FB9                         CAN_F8R2_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F8R2_FB10_Pos                    (10U)                             
-#define CAN_F8R2_FB10_Msk                    (0x1U << CAN_F8R2_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F8R2_FB10                        CAN_F8R2_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F8R2_FB11_Pos                    (11U)                             
-#define CAN_F8R2_FB11_Msk                    (0x1U << CAN_F8R2_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F8R2_FB11                        CAN_F8R2_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F8R2_FB12_Pos                    (12U)                             
-#define CAN_F8R2_FB12_Msk                    (0x1U << CAN_F8R2_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F8R2_FB12                        CAN_F8R2_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F8R2_FB13_Pos                    (13U)                             
-#define CAN_F8R2_FB13_Msk                    (0x1U << CAN_F8R2_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F8R2_FB13                        CAN_F8R2_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F8R2_FB14_Pos                    (14U)                             
-#define CAN_F8R2_FB14_Msk                    (0x1U << CAN_F8R2_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F8R2_FB14                        CAN_F8R2_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F8R2_FB15_Pos                    (15U)                             
-#define CAN_F8R2_FB15_Msk                    (0x1U << CAN_F8R2_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F8R2_FB15                        CAN_F8R2_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F8R2_FB16_Pos                    (16U)                             
-#define CAN_F8R2_FB16_Msk                    (0x1U << CAN_F8R2_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F8R2_FB16                        CAN_F8R2_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F8R2_FB17_Pos                    (17U)                             
-#define CAN_F8R2_FB17_Msk                    (0x1U << CAN_F8R2_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F8R2_FB17                        CAN_F8R2_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F8R2_FB18_Pos                    (18U)                             
-#define CAN_F8R2_FB18_Msk                    (0x1U << CAN_F8R2_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F8R2_FB18                        CAN_F8R2_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F8R2_FB19_Pos                    (19U)                             
-#define CAN_F8R2_FB19_Msk                    (0x1U << CAN_F8R2_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F8R2_FB19                        CAN_F8R2_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F8R2_FB20_Pos                    (20U)                             
-#define CAN_F8R2_FB20_Msk                    (0x1U << CAN_F8R2_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F8R2_FB20                        CAN_F8R2_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F8R2_FB21_Pos                    (21U)                             
-#define CAN_F8R2_FB21_Msk                    (0x1U << CAN_F8R2_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F8R2_FB21                        CAN_F8R2_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F8R2_FB22_Pos                    (22U)                             
-#define CAN_F8R2_FB22_Msk                    (0x1U << CAN_F8R2_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F8R2_FB22                        CAN_F8R2_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F8R2_FB23_Pos                    (23U)                             
-#define CAN_F8R2_FB23_Msk                    (0x1U << CAN_F8R2_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F8R2_FB23                        CAN_F8R2_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F8R2_FB24_Pos                    (24U)                             
-#define CAN_F8R2_FB24_Msk                    (0x1U << CAN_F8R2_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F8R2_FB24                        CAN_F8R2_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F8R2_FB25_Pos                    (25U)                             
-#define CAN_F8R2_FB25_Msk                    (0x1U << CAN_F8R2_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F8R2_FB25                        CAN_F8R2_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F8R2_FB26_Pos                    (26U)                             
-#define CAN_F8R2_FB26_Msk                    (0x1U << CAN_F8R2_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F8R2_FB26                        CAN_F8R2_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F8R2_FB27_Pos                    (27U)                             
-#define CAN_F8R2_FB27_Msk                    (0x1U << CAN_F8R2_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F8R2_FB27                        CAN_F8R2_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F8R2_FB28_Pos                    (28U)                             
-#define CAN_F8R2_FB28_Msk                    (0x1U << CAN_F8R2_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F8R2_FB28                        CAN_F8R2_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F8R2_FB29_Pos                    (29U)                             
-#define CAN_F8R2_FB29_Msk                    (0x1U << CAN_F8R2_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F8R2_FB29                        CAN_F8R2_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F8R2_FB30_Pos                    (30U)                             
-#define CAN_F8R2_FB30_Msk                    (0x1U << CAN_F8R2_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F8R2_FB30                        CAN_F8R2_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F8R2_FB31_Pos                    (31U)                             
-#define CAN_F8R2_FB31_Msk                    (0x1U << CAN_F8R2_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F8R2_FB31                        CAN_F8R2_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define CAN_F9R2_FB0_Pos                     (0U)                              
-#define CAN_F9R2_FB0_Msk                     (0x1U << CAN_F9R2_FB0_Pos)        /*!< 0x00000001 */
-#define CAN_F9R2_FB0                         CAN_F9R2_FB0_Msk                  /*!< Filter bit 0 */
-#define CAN_F9R2_FB1_Pos                     (1U)                              
-#define CAN_F9R2_FB1_Msk                     (0x1U << CAN_F9R2_FB1_Pos)        /*!< 0x00000002 */
-#define CAN_F9R2_FB1                         CAN_F9R2_FB1_Msk                  /*!< Filter bit 1 */
-#define CAN_F9R2_FB2_Pos                     (2U)                              
-#define CAN_F9R2_FB2_Msk                     (0x1U << CAN_F9R2_FB2_Pos)        /*!< 0x00000004 */
-#define CAN_F9R2_FB2                         CAN_F9R2_FB2_Msk                  /*!< Filter bit 2 */
-#define CAN_F9R2_FB3_Pos                     (3U)                              
-#define CAN_F9R2_FB3_Msk                     (0x1U << CAN_F9R2_FB3_Pos)        /*!< 0x00000008 */
-#define CAN_F9R2_FB3                         CAN_F9R2_FB3_Msk                  /*!< Filter bit 3 */
-#define CAN_F9R2_FB4_Pos                     (4U)                              
-#define CAN_F9R2_FB4_Msk                     (0x1U << CAN_F9R2_FB4_Pos)        /*!< 0x00000010 */
-#define CAN_F9R2_FB4                         CAN_F9R2_FB4_Msk                  /*!< Filter bit 4 */
-#define CAN_F9R2_FB5_Pos                     (5U)                              
-#define CAN_F9R2_FB5_Msk                     (0x1U << CAN_F9R2_FB5_Pos)        /*!< 0x00000020 */
-#define CAN_F9R2_FB5                         CAN_F9R2_FB5_Msk                  /*!< Filter bit 5 */
-#define CAN_F9R2_FB6_Pos                     (6U)                              
-#define CAN_F9R2_FB6_Msk                     (0x1U << CAN_F9R2_FB6_Pos)        /*!< 0x00000040 */
-#define CAN_F9R2_FB6                         CAN_F9R2_FB6_Msk                  /*!< Filter bit 6 */
-#define CAN_F9R2_FB7_Pos                     (7U)                              
-#define CAN_F9R2_FB7_Msk                     (0x1U << CAN_F9R2_FB7_Pos)        /*!< 0x00000080 */
-#define CAN_F9R2_FB7                         CAN_F9R2_FB7_Msk                  /*!< Filter bit 7 */
-#define CAN_F9R2_FB8_Pos                     (8U)                              
-#define CAN_F9R2_FB8_Msk                     (0x1U << CAN_F9R2_FB8_Pos)        /*!< 0x00000100 */
-#define CAN_F9R2_FB8                         CAN_F9R2_FB8_Msk                  /*!< Filter bit 8 */
-#define CAN_F9R2_FB9_Pos                     (9U)                              
-#define CAN_F9R2_FB9_Msk                     (0x1U << CAN_F9R2_FB9_Pos)        /*!< 0x00000200 */
-#define CAN_F9R2_FB9                         CAN_F9R2_FB9_Msk                  /*!< Filter bit 9 */
-#define CAN_F9R2_FB10_Pos                    (10U)                             
-#define CAN_F9R2_FB10_Msk                    (0x1U << CAN_F9R2_FB10_Pos)       /*!< 0x00000400 */
-#define CAN_F9R2_FB10                        CAN_F9R2_FB10_Msk                 /*!< Filter bit 10 */
-#define CAN_F9R2_FB11_Pos                    (11U)                             
-#define CAN_F9R2_FB11_Msk                    (0x1U << CAN_F9R2_FB11_Pos)       /*!< 0x00000800 */
-#define CAN_F9R2_FB11                        CAN_F9R2_FB11_Msk                 /*!< Filter bit 11 */
-#define CAN_F9R2_FB12_Pos                    (12U)                             
-#define CAN_F9R2_FB12_Msk                    (0x1U << CAN_F9R2_FB12_Pos)       /*!< 0x00001000 */
-#define CAN_F9R2_FB12                        CAN_F9R2_FB12_Msk                 /*!< Filter bit 12 */
-#define CAN_F9R2_FB13_Pos                    (13U)                             
-#define CAN_F9R2_FB13_Msk                    (0x1U << CAN_F9R2_FB13_Pos)       /*!< 0x00002000 */
-#define CAN_F9R2_FB13                        CAN_F9R2_FB13_Msk                 /*!< Filter bit 13 */
-#define CAN_F9R2_FB14_Pos                    (14U)                             
-#define CAN_F9R2_FB14_Msk                    (0x1U << CAN_F9R2_FB14_Pos)       /*!< 0x00004000 */
-#define CAN_F9R2_FB14                        CAN_F9R2_FB14_Msk                 /*!< Filter bit 14 */
-#define CAN_F9R2_FB15_Pos                    (15U)                             
-#define CAN_F9R2_FB15_Msk                    (0x1U << CAN_F9R2_FB15_Pos)       /*!< 0x00008000 */
-#define CAN_F9R2_FB15                        CAN_F9R2_FB15_Msk                 /*!< Filter bit 15 */
-#define CAN_F9R2_FB16_Pos                    (16U)                             
-#define CAN_F9R2_FB16_Msk                    (0x1U << CAN_F9R2_FB16_Pos)       /*!< 0x00010000 */
-#define CAN_F9R2_FB16                        CAN_F9R2_FB16_Msk                 /*!< Filter bit 16 */
-#define CAN_F9R2_FB17_Pos                    (17U)                             
-#define CAN_F9R2_FB17_Msk                    (0x1U << CAN_F9R2_FB17_Pos)       /*!< 0x00020000 */
-#define CAN_F9R2_FB17                        CAN_F9R2_FB17_Msk                 /*!< Filter bit 17 */
-#define CAN_F9R2_FB18_Pos                    (18U)                             
-#define CAN_F9R2_FB18_Msk                    (0x1U << CAN_F9R2_FB18_Pos)       /*!< 0x00040000 */
-#define CAN_F9R2_FB18                        CAN_F9R2_FB18_Msk                 /*!< Filter bit 18 */
-#define CAN_F9R2_FB19_Pos                    (19U)                             
-#define CAN_F9R2_FB19_Msk                    (0x1U << CAN_F9R2_FB19_Pos)       /*!< 0x00080000 */
-#define CAN_F9R2_FB19                        CAN_F9R2_FB19_Msk                 /*!< Filter bit 19 */
-#define CAN_F9R2_FB20_Pos                    (20U)                             
-#define CAN_F9R2_FB20_Msk                    (0x1U << CAN_F9R2_FB20_Pos)       /*!< 0x00100000 */
-#define CAN_F9R2_FB20                        CAN_F9R2_FB20_Msk                 /*!< Filter bit 20 */
-#define CAN_F9R2_FB21_Pos                    (21U)                             
-#define CAN_F9R2_FB21_Msk                    (0x1U << CAN_F9R2_FB21_Pos)       /*!< 0x00200000 */
-#define CAN_F9R2_FB21                        CAN_F9R2_FB21_Msk                 /*!< Filter bit 21 */
-#define CAN_F9R2_FB22_Pos                    (22U)                             
-#define CAN_F9R2_FB22_Msk                    (0x1U << CAN_F9R2_FB22_Pos)       /*!< 0x00400000 */
-#define CAN_F9R2_FB22                        CAN_F9R2_FB22_Msk                 /*!< Filter bit 22 */
-#define CAN_F9R2_FB23_Pos                    (23U)                             
-#define CAN_F9R2_FB23_Msk                    (0x1U << CAN_F9R2_FB23_Pos)       /*!< 0x00800000 */
-#define CAN_F9R2_FB23                        CAN_F9R2_FB23_Msk                 /*!< Filter bit 23 */
-#define CAN_F9R2_FB24_Pos                    (24U)                             
-#define CAN_F9R2_FB24_Msk                    (0x1U << CAN_F9R2_FB24_Pos)       /*!< 0x01000000 */
-#define CAN_F9R2_FB24                        CAN_F9R2_FB24_Msk                 /*!< Filter bit 24 */
-#define CAN_F9R2_FB25_Pos                    (25U)                             
-#define CAN_F9R2_FB25_Msk                    (0x1U << CAN_F9R2_FB25_Pos)       /*!< 0x02000000 */
-#define CAN_F9R2_FB25                        CAN_F9R2_FB25_Msk                 /*!< Filter bit 25 */
-#define CAN_F9R2_FB26_Pos                    (26U)                             
-#define CAN_F9R2_FB26_Msk                    (0x1U << CAN_F9R2_FB26_Pos)       /*!< 0x04000000 */
-#define CAN_F9R2_FB26                        CAN_F9R2_FB26_Msk                 /*!< Filter bit 26 */
-#define CAN_F9R2_FB27_Pos                    (27U)                             
-#define CAN_F9R2_FB27_Msk                    (0x1U << CAN_F9R2_FB27_Pos)       /*!< 0x08000000 */
-#define CAN_F9R2_FB27                        CAN_F9R2_FB27_Msk                 /*!< Filter bit 27 */
-#define CAN_F9R2_FB28_Pos                    (28U)                             
-#define CAN_F9R2_FB28_Msk                    (0x1U << CAN_F9R2_FB28_Pos)       /*!< 0x10000000 */
-#define CAN_F9R2_FB28                        CAN_F9R2_FB28_Msk                 /*!< Filter bit 28 */
-#define CAN_F9R2_FB29_Pos                    (29U)                             
-#define CAN_F9R2_FB29_Msk                    (0x1U << CAN_F9R2_FB29_Pos)       /*!< 0x20000000 */
-#define CAN_F9R2_FB29                        CAN_F9R2_FB29_Msk                 /*!< Filter bit 29 */
-#define CAN_F9R2_FB30_Pos                    (30U)                             
-#define CAN_F9R2_FB30_Msk                    (0x1U << CAN_F9R2_FB30_Pos)       /*!< 0x40000000 */
-#define CAN_F9R2_FB30                        CAN_F9R2_FB30_Msk                 /*!< Filter bit 30 */
-#define CAN_F9R2_FB31_Pos                    (31U)                             
-#define CAN_F9R2_FB31_Msk                    (0x1U << CAN_F9R2_FB31_Pos)       /*!< 0x80000000 */
-#define CAN_F9R2_FB31                        CAN_F9R2_FB31_Msk                 /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define CAN_F10R2_FB0_Pos                    (0U)                              
-#define CAN_F10R2_FB0_Msk                    (0x1U << CAN_F10R2_FB0_Pos)       /*!< 0x00000001 */
-#define CAN_F10R2_FB0                        CAN_F10R2_FB0_Msk                 /*!< Filter bit 0 */
-#define CAN_F10R2_FB1_Pos                    (1U)                              
-#define CAN_F10R2_FB1_Msk                    (0x1U << CAN_F10R2_FB1_Pos)       /*!< 0x00000002 */
-#define CAN_F10R2_FB1                        CAN_F10R2_FB1_Msk                 /*!< Filter bit 1 */
-#define CAN_F10R2_FB2_Pos                    (2U)                              
-#define CAN_F10R2_FB2_Msk                    (0x1U << CAN_F10R2_FB2_Pos)       /*!< 0x00000004 */
-#define CAN_F10R2_FB2                        CAN_F10R2_FB2_Msk                 /*!< Filter bit 2 */
-#define CAN_F10R2_FB3_Pos                    (3U)                              
-#define CAN_F10R2_FB3_Msk                    (0x1U << CAN_F10R2_FB3_Pos)       /*!< 0x00000008 */
-#define CAN_F10R2_FB3                        CAN_F10R2_FB3_Msk                 /*!< Filter bit 3 */
-#define CAN_F10R2_FB4_Pos                    (4U)                              
-#define CAN_F10R2_FB4_Msk                    (0x1U << CAN_F10R2_FB4_Pos)       /*!< 0x00000010 */
-#define CAN_F10R2_FB4                        CAN_F10R2_FB4_Msk                 /*!< Filter bit 4 */
-#define CAN_F10R2_FB5_Pos                    (5U)                              
-#define CAN_F10R2_FB5_Msk                    (0x1U << CAN_F10R2_FB5_Pos)       /*!< 0x00000020 */
-#define CAN_F10R2_FB5                        CAN_F10R2_FB5_Msk                 /*!< Filter bit 5 */
-#define CAN_F10R2_FB6_Pos                    (6U)                              
-#define CAN_F10R2_FB6_Msk                    (0x1U << CAN_F10R2_FB6_Pos)       /*!< 0x00000040 */
-#define CAN_F10R2_FB6                        CAN_F10R2_FB6_Msk                 /*!< Filter bit 6 */
-#define CAN_F10R2_FB7_Pos                    (7U)                              
-#define CAN_F10R2_FB7_Msk                    (0x1U << CAN_F10R2_FB7_Pos)       /*!< 0x00000080 */
-#define CAN_F10R2_FB7                        CAN_F10R2_FB7_Msk                 /*!< Filter bit 7 */
-#define CAN_F10R2_FB8_Pos                    (8U)                              
-#define CAN_F10R2_FB8_Msk                    (0x1U << CAN_F10R2_FB8_Pos)       /*!< 0x00000100 */
-#define CAN_F10R2_FB8                        CAN_F10R2_FB8_Msk                 /*!< Filter bit 8 */
-#define CAN_F10R2_FB9_Pos                    (9U)                              
-#define CAN_F10R2_FB9_Msk                    (0x1U << CAN_F10R2_FB9_Pos)       /*!< 0x00000200 */
-#define CAN_F10R2_FB9                        CAN_F10R2_FB9_Msk                 /*!< Filter bit 9 */
-#define CAN_F10R2_FB10_Pos                   (10U)                             
-#define CAN_F10R2_FB10_Msk                   (0x1U << CAN_F10R2_FB10_Pos)      /*!< 0x00000400 */
-#define CAN_F10R2_FB10                       CAN_F10R2_FB10_Msk                /*!< Filter bit 10 */
-#define CAN_F10R2_FB11_Pos                   (11U)                             
-#define CAN_F10R2_FB11_Msk                   (0x1U << CAN_F10R2_FB11_Pos)      /*!< 0x00000800 */
-#define CAN_F10R2_FB11                       CAN_F10R2_FB11_Msk                /*!< Filter bit 11 */
-#define CAN_F10R2_FB12_Pos                   (12U)                             
-#define CAN_F10R2_FB12_Msk                   (0x1U << CAN_F10R2_FB12_Pos)      /*!< 0x00001000 */
-#define CAN_F10R2_FB12                       CAN_F10R2_FB12_Msk                /*!< Filter bit 12 */
-#define CAN_F10R2_FB13_Pos                   (13U)                             
-#define CAN_F10R2_FB13_Msk                   (0x1U << CAN_F10R2_FB13_Pos)      /*!< 0x00002000 */
-#define CAN_F10R2_FB13                       CAN_F10R2_FB13_Msk                /*!< Filter bit 13 */
-#define CAN_F10R2_FB14_Pos                   (14U)                             
-#define CAN_F10R2_FB14_Msk                   (0x1U << CAN_F10R2_FB14_Pos)      /*!< 0x00004000 */
-#define CAN_F10R2_FB14                       CAN_F10R2_FB14_Msk                /*!< Filter bit 14 */
-#define CAN_F10R2_FB15_Pos                   (15U)                             
-#define CAN_F10R2_FB15_Msk                   (0x1U << CAN_F10R2_FB15_Pos)      /*!< 0x00008000 */
-#define CAN_F10R2_FB15                       CAN_F10R2_FB15_Msk                /*!< Filter bit 15 */
-#define CAN_F10R2_FB16_Pos                   (16U)                             
-#define CAN_F10R2_FB16_Msk                   (0x1U << CAN_F10R2_FB16_Pos)      /*!< 0x00010000 */
-#define CAN_F10R2_FB16                       CAN_F10R2_FB16_Msk                /*!< Filter bit 16 */
-#define CAN_F10R2_FB17_Pos                   (17U)                             
-#define CAN_F10R2_FB17_Msk                   (0x1U << CAN_F10R2_FB17_Pos)      /*!< 0x00020000 */
-#define CAN_F10R2_FB17                       CAN_F10R2_FB17_Msk                /*!< Filter bit 17 */
-#define CAN_F10R2_FB18_Pos                   (18U)                             
-#define CAN_F10R2_FB18_Msk                   (0x1U << CAN_F10R2_FB18_Pos)      /*!< 0x00040000 */
-#define CAN_F10R2_FB18                       CAN_F10R2_FB18_Msk                /*!< Filter bit 18 */
-#define CAN_F10R2_FB19_Pos                   (19U)                             
-#define CAN_F10R2_FB19_Msk                   (0x1U << CAN_F10R2_FB19_Pos)      /*!< 0x00080000 */
-#define CAN_F10R2_FB19                       CAN_F10R2_FB19_Msk                /*!< Filter bit 19 */
-#define CAN_F10R2_FB20_Pos                   (20U)                             
-#define CAN_F10R2_FB20_Msk                   (0x1U << CAN_F10R2_FB20_Pos)      /*!< 0x00100000 */
-#define CAN_F10R2_FB20                       CAN_F10R2_FB20_Msk                /*!< Filter bit 20 */
-#define CAN_F10R2_FB21_Pos                   (21U)                             
-#define CAN_F10R2_FB21_Msk                   (0x1U << CAN_F10R2_FB21_Pos)      /*!< 0x00200000 */
-#define CAN_F10R2_FB21                       CAN_F10R2_FB21_Msk                /*!< Filter bit 21 */
-#define CAN_F10R2_FB22_Pos                   (22U)                             
-#define CAN_F10R2_FB22_Msk                   (0x1U << CAN_F10R2_FB22_Pos)      /*!< 0x00400000 */
-#define CAN_F10R2_FB22                       CAN_F10R2_FB22_Msk                /*!< Filter bit 22 */
-#define CAN_F10R2_FB23_Pos                   (23U)                             
-#define CAN_F10R2_FB23_Msk                   (0x1U << CAN_F10R2_FB23_Pos)      /*!< 0x00800000 */
-#define CAN_F10R2_FB23                       CAN_F10R2_FB23_Msk                /*!< Filter bit 23 */
-#define CAN_F10R2_FB24_Pos                   (24U)                             
-#define CAN_F10R2_FB24_Msk                   (0x1U << CAN_F10R2_FB24_Pos)      /*!< 0x01000000 */
-#define CAN_F10R2_FB24                       CAN_F10R2_FB24_Msk                /*!< Filter bit 24 */
-#define CAN_F10R2_FB25_Pos                   (25U)                             
-#define CAN_F10R2_FB25_Msk                   (0x1U << CAN_F10R2_FB25_Pos)      /*!< 0x02000000 */
-#define CAN_F10R2_FB25                       CAN_F10R2_FB25_Msk                /*!< Filter bit 25 */
-#define CAN_F10R2_FB26_Pos                   (26U)                             
-#define CAN_F10R2_FB26_Msk                   (0x1U << CAN_F10R2_FB26_Pos)      /*!< 0x04000000 */
-#define CAN_F10R2_FB26                       CAN_F10R2_FB26_Msk                /*!< Filter bit 26 */
-#define CAN_F10R2_FB27_Pos                   (27U)                             
-#define CAN_F10R2_FB27_Msk                   (0x1U << CAN_F10R2_FB27_Pos)      /*!< 0x08000000 */
-#define CAN_F10R2_FB27                       CAN_F10R2_FB27_Msk                /*!< Filter bit 27 */
-#define CAN_F10R2_FB28_Pos                   (28U)                             
-#define CAN_F10R2_FB28_Msk                   (0x1U << CAN_F10R2_FB28_Pos)      /*!< 0x10000000 */
-#define CAN_F10R2_FB28                       CAN_F10R2_FB28_Msk                /*!< Filter bit 28 */
-#define CAN_F10R2_FB29_Pos                   (29U)                             
-#define CAN_F10R2_FB29_Msk                   (0x1U << CAN_F10R2_FB29_Pos)      /*!< 0x20000000 */
-#define CAN_F10R2_FB29                       CAN_F10R2_FB29_Msk                /*!< Filter bit 29 */
-#define CAN_F10R2_FB30_Pos                   (30U)                             
-#define CAN_F10R2_FB30_Msk                   (0x1U << CAN_F10R2_FB30_Pos)      /*!< 0x40000000 */
-#define CAN_F10R2_FB30                       CAN_F10R2_FB30_Msk                /*!< Filter bit 30 */
-#define CAN_F10R2_FB31_Pos                   (31U)                             
-#define CAN_F10R2_FB31_Msk                   (0x1U << CAN_F10R2_FB31_Pos)      /*!< 0x80000000 */
-#define CAN_F10R2_FB31                       CAN_F10R2_FB31_Msk                /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define CAN_F11R2_FB0_Pos                    (0U)                              
-#define CAN_F11R2_FB0_Msk                    (0x1U << CAN_F11R2_FB0_Pos)       /*!< 0x00000001 */
-#define CAN_F11R2_FB0                        CAN_F11R2_FB0_Msk                 /*!< Filter bit 0 */
-#define CAN_F11R2_FB1_Pos                    (1U)                              
-#define CAN_F11R2_FB1_Msk                    (0x1U << CAN_F11R2_FB1_Pos)       /*!< 0x00000002 */
-#define CAN_F11R2_FB1                        CAN_F11R2_FB1_Msk                 /*!< Filter bit 1 */
-#define CAN_F11R2_FB2_Pos                    (2U)                              
-#define CAN_F11R2_FB2_Msk                    (0x1U << CAN_F11R2_FB2_Pos)       /*!< 0x00000004 */
-#define CAN_F11R2_FB2                        CAN_F11R2_FB2_Msk                 /*!< Filter bit 2 */
-#define CAN_F11R2_FB3_Pos                    (3U)                              
-#define CAN_F11R2_FB3_Msk                    (0x1U << CAN_F11R2_FB3_Pos)       /*!< 0x00000008 */
-#define CAN_F11R2_FB3                        CAN_F11R2_FB3_Msk                 /*!< Filter bit 3 */
-#define CAN_F11R2_FB4_Pos                    (4U)                              
-#define CAN_F11R2_FB4_Msk                    (0x1U << CAN_F11R2_FB4_Pos)       /*!< 0x00000010 */
-#define CAN_F11R2_FB4                        CAN_F11R2_FB4_Msk                 /*!< Filter bit 4 */
-#define CAN_F11R2_FB5_Pos                    (5U)                              
-#define CAN_F11R2_FB5_Msk                    (0x1U << CAN_F11R2_FB5_Pos)       /*!< 0x00000020 */
-#define CAN_F11R2_FB5                        CAN_F11R2_FB5_Msk                 /*!< Filter bit 5 */
-#define CAN_F11R2_FB6_Pos                    (6U)                              
-#define CAN_F11R2_FB6_Msk                    (0x1U << CAN_F11R2_FB6_Pos)       /*!< 0x00000040 */
-#define CAN_F11R2_FB6                        CAN_F11R2_FB6_Msk                 /*!< Filter bit 6 */
-#define CAN_F11R2_FB7_Pos                    (7U)                              
-#define CAN_F11R2_FB7_Msk                    (0x1U << CAN_F11R2_FB7_Pos)       /*!< 0x00000080 */
-#define CAN_F11R2_FB7                        CAN_F11R2_FB7_Msk                 /*!< Filter bit 7 */
-#define CAN_F11R2_FB8_Pos                    (8U)                              
-#define CAN_F11R2_FB8_Msk                    (0x1U << CAN_F11R2_FB8_Pos)       /*!< 0x00000100 */
-#define CAN_F11R2_FB8                        CAN_F11R2_FB8_Msk                 /*!< Filter bit 8 */
-#define CAN_F11R2_FB9_Pos                    (9U)                              
-#define CAN_F11R2_FB9_Msk                    (0x1U << CAN_F11R2_FB9_Pos)       /*!< 0x00000200 */
-#define CAN_F11R2_FB9                        CAN_F11R2_FB9_Msk                 /*!< Filter bit 9 */
-#define CAN_F11R2_FB10_Pos                   (10U)                             
-#define CAN_F11R2_FB10_Msk                   (0x1U << CAN_F11R2_FB10_Pos)      /*!< 0x00000400 */
-#define CAN_F11R2_FB10                       CAN_F11R2_FB10_Msk                /*!< Filter bit 10 */
-#define CAN_F11R2_FB11_Pos                   (11U)                             
-#define CAN_F11R2_FB11_Msk                   (0x1U << CAN_F11R2_FB11_Pos)      /*!< 0x00000800 */
-#define CAN_F11R2_FB11                       CAN_F11R2_FB11_Msk                /*!< Filter bit 11 */
-#define CAN_F11R2_FB12_Pos                   (12U)                             
-#define CAN_F11R2_FB12_Msk                   (0x1U << CAN_F11R2_FB12_Pos)      /*!< 0x00001000 */
-#define CAN_F11R2_FB12                       CAN_F11R2_FB12_Msk                /*!< Filter bit 12 */
-#define CAN_F11R2_FB13_Pos                   (13U)                             
-#define CAN_F11R2_FB13_Msk                   (0x1U << CAN_F11R2_FB13_Pos)      /*!< 0x00002000 */
-#define CAN_F11R2_FB13                       CAN_F11R2_FB13_Msk                /*!< Filter bit 13 */
-#define CAN_F11R2_FB14_Pos                   (14U)                             
-#define CAN_F11R2_FB14_Msk                   (0x1U << CAN_F11R2_FB14_Pos)      /*!< 0x00004000 */
-#define CAN_F11R2_FB14                       CAN_F11R2_FB14_Msk                /*!< Filter bit 14 */
-#define CAN_F11R2_FB15_Pos                   (15U)                             
-#define CAN_F11R2_FB15_Msk                   (0x1U << CAN_F11R2_FB15_Pos)      /*!< 0x00008000 */
-#define CAN_F11R2_FB15                       CAN_F11R2_FB15_Msk                /*!< Filter bit 15 */
-#define CAN_F11R2_FB16_Pos                   (16U)                             
-#define CAN_F11R2_FB16_Msk                   (0x1U << CAN_F11R2_FB16_Pos)      /*!< 0x00010000 */
-#define CAN_F11R2_FB16                       CAN_F11R2_FB16_Msk                /*!< Filter bit 16 */
-#define CAN_F11R2_FB17_Pos                   (17U)                             
-#define CAN_F11R2_FB17_Msk                   (0x1U << CAN_F11R2_FB17_Pos)      /*!< 0x00020000 */
-#define CAN_F11R2_FB17                       CAN_F11R2_FB17_Msk                /*!< Filter bit 17 */
-#define CAN_F11R2_FB18_Pos                   (18U)                             
-#define CAN_F11R2_FB18_Msk                   (0x1U << CAN_F11R2_FB18_Pos)      /*!< 0x00040000 */
-#define CAN_F11R2_FB18                       CAN_F11R2_FB18_Msk                /*!< Filter bit 18 */
-#define CAN_F11R2_FB19_Pos                   (19U)                             
-#define CAN_F11R2_FB19_Msk                   (0x1U << CAN_F11R2_FB19_Pos)      /*!< 0x00080000 */
-#define CAN_F11R2_FB19                       CAN_F11R2_FB19_Msk                /*!< Filter bit 19 */
-#define CAN_F11R2_FB20_Pos                   (20U)                             
-#define CAN_F11R2_FB20_Msk                   (0x1U << CAN_F11R2_FB20_Pos)      /*!< 0x00100000 */
-#define CAN_F11R2_FB20                       CAN_F11R2_FB20_Msk                /*!< Filter bit 20 */
-#define CAN_F11R2_FB21_Pos                   (21U)                             
-#define CAN_F11R2_FB21_Msk                   (0x1U << CAN_F11R2_FB21_Pos)      /*!< 0x00200000 */
-#define CAN_F11R2_FB21                       CAN_F11R2_FB21_Msk                /*!< Filter bit 21 */
-#define CAN_F11R2_FB22_Pos                   (22U)                             
-#define CAN_F11R2_FB22_Msk                   (0x1U << CAN_F11R2_FB22_Pos)      /*!< 0x00400000 */
-#define CAN_F11R2_FB22                       CAN_F11R2_FB22_Msk                /*!< Filter bit 22 */
-#define CAN_F11R2_FB23_Pos                   (23U)                             
-#define CAN_F11R2_FB23_Msk                   (0x1U << CAN_F11R2_FB23_Pos)      /*!< 0x00800000 */
-#define CAN_F11R2_FB23                       CAN_F11R2_FB23_Msk                /*!< Filter bit 23 */
-#define CAN_F11R2_FB24_Pos                   (24U)                             
-#define CAN_F11R2_FB24_Msk                   (0x1U << CAN_F11R2_FB24_Pos)      /*!< 0x01000000 */
-#define CAN_F11R2_FB24                       CAN_F11R2_FB24_Msk                /*!< Filter bit 24 */
-#define CAN_F11R2_FB25_Pos                   (25U)                             
-#define CAN_F11R2_FB25_Msk                   (0x1U << CAN_F11R2_FB25_Pos)      /*!< 0x02000000 */
-#define CAN_F11R2_FB25                       CAN_F11R2_FB25_Msk                /*!< Filter bit 25 */
-#define CAN_F11R2_FB26_Pos                   (26U)                             
-#define CAN_F11R2_FB26_Msk                   (0x1U << CAN_F11R2_FB26_Pos)      /*!< 0x04000000 */
-#define CAN_F11R2_FB26                       CAN_F11R2_FB26_Msk                /*!< Filter bit 26 */
-#define CAN_F11R2_FB27_Pos                   (27U)                             
-#define CAN_F11R2_FB27_Msk                   (0x1U << CAN_F11R2_FB27_Pos)      /*!< 0x08000000 */
-#define CAN_F11R2_FB27                       CAN_F11R2_FB27_Msk                /*!< Filter bit 27 */
-#define CAN_F11R2_FB28_Pos                   (28U)                             
-#define CAN_F11R2_FB28_Msk                   (0x1U << CAN_F11R2_FB28_Pos)      /*!< 0x10000000 */
-#define CAN_F11R2_FB28                       CAN_F11R2_FB28_Msk                /*!< Filter bit 28 */
-#define CAN_F11R2_FB29_Pos                   (29U)                             
-#define CAN_F11R2_FB29_Msk                   (0x1U << CAN_F11R2_FB29_Pos)      /*!< 0x20000000 */
-#define CAN_F11R2_FB29                       CAN_F11R2_FB29_Msk                /*!< Filter bit 29 */
-#define CAN_F11R2_FB30_Pos                   (30U)                             
-#define CAN_F11R2_FB30_Msk                   (0x1U << CAN_F11R2_FB30_Pos)      /*!< 0x40000000 */
-#define CAN_F11R2_FB30                       CAN_F11R2_FB30_Msk                /*!< Filter bit 30 */
-#define CAN_F11R2_FB31_Pos                   (31U)                             
-#define CAN_F11R2_FB31_Msk                   (0x1U << CAN_F11R2_FB31_Pos)      /*!< 0x80000000 */
-#define CAN_F11R2_FB31                       CAN_F11R2_FB31_Msk                /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define CAN_F12R2_FB0_Pos                    (0U)                              
-#define CAN_F12R2_FB0_Msk                    (0x1U << CAN_F12R2_FB0_Pos)       /*!< 0x00000001 */
-#define CAN_F12R2_FB0                        CAN_F12R2_FB0_Msk                 /*!< Filter bit 0 */
-#define CAN_F12R2_FB1_Pos                    (1U)                              
-#define CAN_F12R2_FB1_Msk                    (0x1U << CAN_F12R2_FB1_Pos)       /*!< 0x00000002 */
-#define CAN_F12R2_FB1                        CAN_F12R2_FB1_Msk                 /*!< Filter bit 1 */
-#define CAN_F12R2_FB2_Pos                    (2U)                              
-#define CAN_F12R2_FB2_Msk                    (0x1U << CAN_F12R2_FB2_Pos)       /*!< 0x00000004 */
-#define CAN_F12R2_FB2                        CAN_F12R2_FB2_Msk                 /*!< Filter bit 2 */
-#define CAN_F12R2_FB3_Pos                    (3U)                              
-#define CAN_F12R2_FB3_Msk                    (0x1U << CAN_F12R2_FB3_Pos)       /*!< 0x00000008 */
-#define CAN_F12R2_FB3                        CAN_F12R2_FB3_Msk                 /*!< Filter bit 3 */
-#define CAN_F12R2_FB4_Pos                    (4U)                              
-#define CAN_F12R2_FB4_Msk                    (0x1U << CAN_F12R2_FB4_Pos)       /*!< 0x00000010 */
-#define CAN_F12R2_FB4                        CAN_F12R2_FB4_Msk                 /*!< Filter bit 4 */
-#define CAN_F12R2_FB5_Pos                    (5U)                              
-#define CAN_F12R2_FB5_Msk                    (0x1U << CAN_F12R2_FB5_Pos)       /*!< 0x00000020 */
-#define CAN_F12R2_FB5                        CAN_F12R2_FB5_Msk                 /*!< Filter bit 5 */
-#define CAN_F12R2_FB6_Pos                    (6U)                              
-#define CAN_F12R2_FB6_Msk                    (0x1U << CAN_F12R2_FB6_Pos)       /*!< 0x00000040 */
-#define CAN_F12R2_FB6                        CAN_F12R2_FB6_Msk                 /*!< Filter bit 6 */
-#define CAN_F12R2_FB7_Pos                    (7U)                              
-#define CAN_F12R2_FB7_Msk                    (0x1U << CAN_F12R2_FB7_Pos)       /*!< 0x00000080 */
-#define CAN_F12R2_FB7                        CAN_F12R2_FB7_Msk                 /*!< Filter bit 7 */
-#define CAN_F12R2_FB8_Pos                    (8U)                              
-#define CAN_F12R2_FB8_Msk                    (0x1U << CAN_F12R2_FB8_Pos)       /*!< 0x00000100 */
-#define CAN_F12R2_FB8                        CAN_F12R2_FB8_Msk                 /*!< Filter bit 8 */
-#define CAN_F12R2_FB9_Pos                    (9U)                              
-#define CAN_F12R2_FB9_Msk                    (0x1U << CAN_F12R2_FB9_Pos)       /*!< 0x00000200 */
-#define CAN_F12R2_FB9                        CAN_F12R2_FB9_Msk                 /*!< Filter bit 9 */
-#define CAN_F12R2_FB10_Pos                   (10U)                             
-#define CAN_F12R2_FB10_Msk                   (0x1U << CAN_F12R2_FB10_Pos)      /*!< 0x00000400 */
-#define CAN_F12R2_FB10                       CAN_F12R2_FB10_Msk                /*!< Filter bit 10 */
-#define CAN_F12R2_FB11_Pos                   (11U)                             
-#define CAN_F12R2_FB11_Msk                   (0x1U << CAN_F12R2_FB11_Pos)      /*!< 0x00000800 */
-#define CAN_F12R2_FB11                       CAN_F12R2_FB11_Msk                /*!< Filter bit 11 */
-#define CAN_F12R2_FB12_Pos                   (12U)                             
-#define CAN_F12R2_FB12_Msk                   (0x1U << CAN_F12R2_FB12_Pos)      /*!< 0x00001000 */
-#define CAN_F12R2_FB12                       CAN_F12R2_FB12_Msk                /*!< Filter bit 12 */
-#define CAN_F12R2_FB13_Pos                   (13U)                             
-#define CAN_F12R2_FB13_Msk                   (0x1U << CAN_F12R2_FB13_Pos)      /*!< 0x00002000 */
-#define CAN_F12R2_FB13                       CAN_F12R2_FB13_Msk                /*!< Filter bit 13 */
-#define CAN_F12R2_FB14_Pos                   (14U)                             
-#define CAN_F12R2_FB14_Msk                   (0x1U << CAN_F12R2_FB14_Pos)      /*!< 0x00004000 */
-#define CAN_F12R2_FB14                       CAN_F12R2_FB14_Msk                /*!< Filter bit 14 */
-#define CAN_F12R2_FB15_Pos                   (15U)                             
-#define CAN_F12R2_FB15_Msk                   (0x1U << CAN_F12R2_FB15_Pos)      /*!< 0x00008000 */
-#define CAN_F12R2_FB15                       CAN_F12R2_FB15_Msk                /*!< Filter bit 15 */
-#define CAN_F12R2_FB16_Pos                   (16U)                             
-#define CAN_F12R2_FB16_Msk                   (0x1U << CAN_F12R2_FB16_Pos)      /*!< 0x00010000 */
-#define CAN_F12R2_FB16                       CAN_F12R2_FB16_Msk                /*!< Filter bit 16 */
-#define CAN_F12R2_FB17_Pos                   (17U)                             
-#define CAN_F12R2_FB17_Msk                   (0x1U << CAN_F12R2_FB17_Pos)      /*!< 0x00020000 */
-#define CAN_F12R2_FB17                       CAN_F12R2_FB17_Msk                /*!< Filter bit 17 */
-#define CAN_F12R2_FB18_Pos                   (18U)                             
-#define CAN_F12R2_FB18_Msk                   (0x1U << CAN_F12R2_FB18_Pos)      /*!< 0x00040000 */
-#define CAN_F12R2_FB18                       CAN_F12R2_FB18_Msk                /*!< Filter bit 18 */
-#define CAN_F12R2_FB19_Pos                   (19U)                             
-#define CAN_F12R2_FB19_Msk                   (0x1U << CAN_F12R2_FB19_Pos)      /*!< 0x00080000 */
-#define CAN_F12R2_FB19                       CAN_F12R2_FB19_Msk                /*!< Filter bit 19 */
-#define CAN_F12R2_FB20_Pos                   (20U)                             
-#define CAN_F12R2_FB20_Msk                   (0x1U << CAN_F12R2_FB20_Pos)      /*!< 0x00100000 */
-#define CAN_F12R2_FB20                       CAN_F12R2_FB20_Msk                /*!< Filter bit 20 */
-#define CAN_F12R2_FB21_Pos                   (21U)                             
-#define CAN_F12R2_FB21_Msk                   (0x1U << CAN_F12R2_FB21_Pos)      /*!< 0x00200000 */
-#define CAN_F12R2_FB21                       CAN_F12R2_FB21_Msk                /*!< Filter bit 21 */
-#define CAN_F12R2_FB22_Pos                   (22U)                             
-#define CAN_F12R2_FB22_Msk                   (0x1U << CAN_F12R2_FB22_Pos)      /*!< 0x00400000 */
-#define CAN_F12R2_FB22                       CAN_F12R2_FB22_Msk                /*!< Filter bit 22 */
-#define CAN_F12R2_FB23_Pos                   (23U)                             
-#define CAN_F12R2_FB23_Msk                   (0x1U << CAN_F12R2_FB23_Pos)      /*!< 0x00800000 */
-#define CAN_F12R2_FB23                       CAN_F12R2_FB23_Msk                /*!< Filter bit 23 */
-#define CAN_F12R2_FB24_Pos                   (24U)                             
-#define CAN_F12R2_FB24_Msk                   (0x1U << CAN_F12R2_FB24_Pos)      /*!< 0x01000000 */
-#define CAN_F12R2_FB24                       CAN_F12R2_FB24_Msk                /*!< Filter bit 24 */
-#define CAN_F12R2_FB25_Pos                   (25U)                             
-#define CAN_F12R2_FB25_Msk                   (0x1U << CAN_F12R2_FB25_Pos)      /*!< 0x02000000 */
-#define CAN_F12R2_FB25                       CAN_F12R2_FB25_Msk                /*!< Filter bit 25 */
-#define CAN_F12R2_FB26_Pos                   (26U)                             
-#define CAN_F12R2_FB26_Msk                   (0x1U << CAN_F12R2_FB26_Pos)      /*!< 0x04000000 */
-#define CAN_F12R2_FB26                       CAN_F12R2_FB26_Msk                /*!< Filter bit 26 */
-#define CAN_F12R2_FB27_Pos                   (27U)                             
-#define CAN_F12R2_FB27_Msk                   (0x1U << CAN_F12R2_FB27_Pos)      /*!< 0x08000000 */
-#define CAN_F12R2_FB27                       CAN_F12R2_FB27_Msk                /*!< Filter bit 27 */
-#define CAN_F12R2_FB28_Pos                   (28U)                             
-#define CAN_F12R2_FB28_Msk                   (0x1U << CAN_F12R2_FB28_Pos)      /*!< 0x10000000 */
-#define CAN_F12R2_FB28                       CAN_F12R2_FB28_Msk                /*!< Filter bit 28 */
-#define CAN_F12R2_FB29_Pos                   (29U)                             
-#define CAN_F12R2_FB29_Msk                   (0x1U << CAN_F12R2_FB29_Pos)      /*!< 0x20000000 */
-#define CAN_F12R2_FB29                       CAN_F12R2_FB29_Msk                /*!< Filter bit 29 */
-#define CAN_F12R2_FB30_Pos                   (30U)                             
-#define CAN_F12R2_FB30_Msk                   (0x1U << CAN_F12R2_FB30_Pos)      /*!< 0x40000000 */
-#define CAN_F12R2_FB30                       CAN_F12R2_FB30_Msk                /*!< Filter bit 30 */
-#define CAN_F12R2_FB31_Pos                   (31U)                             
-#define CAN_F12R2_FB31_Msk                   (0x1U << CAN_F12R2_FB31_Pos)      /*!< 0x80000000 */
-#define CAN_F12R2_FB31                       CAN_F12R2_FB31_Msk                /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define CAN_F13R2_FB0_Pos                    (0U)                              
-#define CAN_F13R2_FB0_Msk                    (0x1U << CAN_F13R2_FB0_Pos)       /*!< 0x00000001 */
-#define CAN_F13R2_FB0                        CAN_F13R2_FB0_Msk                 /*!< Filter bit 0 */
-#define CAN_F13R2_FB1_Pos                    (1U)                              
-#define CAN_F13R2_FB1_Msk                    (0x1U << CAN_F13R2_FB1_Pos)       /*!< 0x00000002 */
-#define CAN_F13R2_FB1                        CAN_F13R2_FB1_Msk                 /*!< Filter bit 1 */
-#define CAN_F13R2_FB2_Pos                    (2U)                              
-#define CAN_F13R2_FB2_Msk                    (0x1U << CAN_F13R2_FB2_Pos)       /*!< 0x00000004 */
-#define CAN_F13R2_FB2                        CAN_F13R2_FB2_Msk                 /*!< Filter bit 2 */
-#define CAN_F13R2_FB3_Pos                    (3U)                              
-#define CAN_F13R2_FB3_Msk                    (0x1U << CAN_F13R2_FB3_Pos)       /*!< 0x00000008 */
-#define CAN_F13R2_FB3                        CAN_F13R2_FB3_Msk                 /*!< Filter bit 3 */
-#define CAN_F13R2_FB4_Pos                    (4U)                              
-#define CAN_F13R2_FB4_Msk                    (0x1U << CAN_F13R2_FB4_Pos)       /*!< 0x00000010 */
-#define CAN_F13R2_FB4                        CAN_F13R2_FB4_Msk                 /*!< Filter bit 4 */
-#define CAN_F13R2_FB5_Pos                    (5U)                              
-#define CAN_F13R2_FB5_Msk                    (0x1U << CAN_F13R2_FB5_Pos)       /*!< 0x00000020 */
-#define CAN_F13R2_FB5                        CAN_F13R2_FB5_Msk                 /*!< Filter bit 5 */
-#define CAN_F13R2_FB6_Pos                    (6U)                              
-#define CAN_F13R2_FB6_Msk                    (0x1U << CAN_F13R2_FB6_Pos)       /*!< 0x00000040 */
-#define CAN_F13R2_FB6                        CAN_F13R2_FB6_Msk                 /*!< Filter bit 6 */
-#define CAN_F13R2_FB7_Pos                    (7U)                              
-#define CAN_F13R2_FB7_Msk                    (0x1U << CAN_F13R2_FB7_Pos)       /*!< 0x00000080 */
-#define CAN_F13R2_FB7                        CAN_F13R2_FB7_Msk                 /*!< Filter bit 7 */
-#define CAN_F13R2_FB8_Pos                    (8U)                              
-#define CAN_F13R2_FB8_Msk                    (0x1U << CAN_F13R2_FB8_Pos)       /*!< 0x00000100 */
-#define CAN_F13R2_FB8                        CAN_F13R2_FB8_Msk                 /*!< Filter bit 8 */
-#define CAN_F13R2_FB9_Pos                    (9U)                              
-#define CAN_F13R2_FB9_Msk                    (0x1U << CAN_F13R2_FB9_Pos)       /*!< 0x00000200 */
-#define CAN_F13R2_FB9                        CAN_F13R2_FB9_Msk                 /*!< Filter bit 9 */
-#define CAN_F13R2_FB10_Pos                   (10U)                             
-#define CAN_F13R2_FB10_Msk                   (0x1U << CAN_F13R2_FB10_Pos)      /*!< 0x00000400 */
-#define CAN_F13R2_FB10                       CAN_F13R2_FB10_Msk                /*!< Filter bit 10 */
-#define CAN_F13R2_FB11_Pos                   (11U)                             
-#define CAN_F13R2_FB11_Msk                   (0x1U << CAN_F13R2_FB11_Pos)      /*!< 0x00000800 */
-#define CAN_F13R2_FB11                       CAN_F13R2_FB11_Msk                /*!< Filter bit 11 */
-#define CAN_F13R2_FB12_Pos                   (12U)                             
-#define CAN_F13R2_FB12_Msk                   (0x1U << CAN_F13R2_FB12_Pos)      /*!< 0x00001000 */
-#define CAN_F13R2_FB12                       CAN_F13R2_FB12_Msk                /*!< Filter bit 12 */
-#define CAN_F13R2_FB13_Pos                   (13U)                             
-#define CAN_F13R2_FB13_Msk                   (0x1U << CAN_F13R2_FB13_Pos)      /*!< 0x00002000 */
-#define CAN_F13R2_FB13                       CAN_F13R2_FB13_Msk                /*!< Filter bit 13 */
-#define CAN_F13R2_FB14_Pos                   (14U)                             
-#define CAN_F13R2_FB14_Msk                   (0x1U << CAN_F13R2_FB14_Pos)      /*!< 0x00004000 */
-#define CAN_F13R2_FB14                       CAN_F13R2_FB14_Msk                /*!< Filter bit 14 */
-#define CAN_F13R2_FB15_Pos                   (15U)                             
-#define CAN_F13R2_FB15_Msk                   (0x1U << CAN_F13R2_FB15_Pos)      /*!< 0x00008000 */
-#define CAN_F13R2_FB15                       CAN_F13R2_FB15_Msk                /*!< Filter bit 15 */
-#define CAN_F13R2_FB16_Pos                   (16U)                             
-#define CAN_F13R2_FB16_Msk                   (0x1U << CAN_F13R2_FB16_Pos)      /*!< 0x00010000 */
-#define CAN_F13R2_FB16                       CAN_F13R2_FB16_Msk                /*!< Filter bit 16 */
-#define CAN_F13R2_FB17_Pos                   (17U)                             
-#define CAN_F13R2_FB17_Msk                   (0x1U << CAN_F13R2_FB17_Pos)      /*!< 0x00020000 */
-#define CAN_F13R2_FB17                       CAN_F13R2_FB17_Msk                /*!< Filter bit 17 */
-#define CAN_F13R2_FB18_Pos                   (18U)                             
-#define CAN_F13R2_FB18_Msk                   (0x1U << CAN_F13R2_FB18_Pos)      /*!< 0x00040000 */
-#define CAN_F13R2_FB18                       CAN_F13R2_FB18_Msk                /*!< Filter bit 18 */
-#define CAN_F13R2_FB19_Pos                   (19U)                             
-#define CAN_F13R2_FB19_Msk                   (0x1U << CAN_F13R2_FB19_Pos)      /*!< 0x00080000 */
-#define CAN_F13R2_FB19                       CAN_F13R2_FB19_Msk                /*!< Filter bit 19 */
-#define CAN_F13R2_FB20_Pos                   (20U)                             
-#define CAN_F13R2_FB20_Msk                   (0x1U << CAN_F13R2_FB20_Pos)      /*!< 0x00100000 */
-#define CAN_F13R2_FB20                       CAN_F13R2_FB20_Msk                /*!< Filter bit 20 */
-#define CAN_F13R2_FB21_Pos                   (21U)                             
-#define CAN_F13R2_FB21_Msk                   (0x1U << CAN_F13R2_FB21_Pos)      /*!< 0x00200000 */
-#define CAN_F13R2_FB21                       CAN_F13R2_FB21_Msk                /*!< Filter bit 21 */
-#define CAN_F13R2_FB22_Pos                   (22U)                             
-#define CAN_F13R2_FB22_Msk                   (0x1U << CAN_F13R2_FB22_Pos)      /*!< 0x00400000 */
-#define CAN_F13R2_FB22                       CAN_F13R2_FB22_Msk                /*!< Filter bit 22 */
-#define CAN_F13R2_FB23_Pos                   (23U)                             
-#define CAN_F13R2_FB23_Msk                   (0x1U << CAN_F13R2_FB23_Pos)      /*!< 0x00800000 */
-#define CAN_F13R2_FB23                       CAN_F13R2_FB23_Msk                /*!< Filter bit 23 */
-#define CAN_F13R2_FB24_Pos                   (24U)                             
-#define CAN_F13R2_FB24_Msk                   (0x1U << CAN_F13R2_FB24_Pos)      /*!< 0x01000000 */
-#define CAN_F13R2_FB24                       CAN_F13R2_FB24_Msk                /*!< Filter bit 24 */
-#define CAN_F13R2_FB25_Pos                   (25U)                             
-#define CAN_F13R2_FB25_Msk                   (0x1U << CAN_F13R2_FB25_Pos)      /*!< 0x02000000 */
-#define CAN_F13R2_FB25                       CAN_F13R2_FB25_Msk                /*!< Filter bit 25 */
-#define CAN_F13R2_FB26_Pos                   (26U)                             
-#define CAN_F13R2_FB26_Msk                   (0x1U << CAN_F13R2_FB26_Pos)      /*!< 0x04000000 */
-#define CAN_F13R2_FB26                       CAN_F13R2_FB26_Msk                /*!< Filter bit 26 */
-#define CAN_F13R2_FB27_Pos                   (27U)                             
-#define CAN_F13R2_FB27_Msk                   (0x1U << CAN_F13R2_FB27_Pos)      /*!< 0x08000000 */
-#define CAN_F13R2_FB27                       CAN_F13R2_FB27_Msk                /*!< Filter bit 27 */
-#define CAN_F13R2_FB28_Pos                   (28U)                             
-#define CAN_F13R2_FB28_Msk                   (0x1U << CAN_F13R2_FB28_Pos)      /*!< 0x10000000 */
-#define CAN_F13R2_FB28                       CAN_F13R2_FB28_Msk                /*!< Filter bit 28 */
-#define CAN_F13R2_FB29_Pos                   (29U)                             
-#define CAN_F13R2_FB29_Msk                   (0x1U << CAN_F13R2_FB29_Pos)      /*!< 0x20000000 */
-#define CAN_F13R2_FB29                       CAN_F13R2_FB29_Msk                /*!< Filter bit 29 */
-#define CAN_F13R2_FB30_Pos                   (30U)                             
-#define CAN_F13R2_FB30_Msk                   (0x1U << CAN_F13R2_FB30_Pos)      /*!< 0x40000000 */
-#define CAN_F13R2_FB30                       CAN_F13R2_FB30_Msk                /*!< Filter bit 30 */
-#define CAN_F13R2_FB31_Pos                   (31U)                             
-#define CAN_F13R2_FB31_Msk                   (0x1U << CAN_F13R2_FB31_Pos)      /*!< 0x80000000 */
-#define CAN_F13R2_FB31                       CAN_F13R2_FB31_Msk                /*!< Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1U << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1U << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1U << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7U << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1U << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2U << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4U << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1U << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1U << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1U << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1U << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1U << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1U << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1U << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1U << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1U << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1U << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1U << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1U << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1U << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1U << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1U << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1U << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1U << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1U << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1U << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1U << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1U << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1U << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1U << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1U << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFU << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_I2SMOD_Pos              (11U)                              
-#define SPI_I2SCFGR_I2SMOD_Msk              (0x1U << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!< I2S mode selection */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1U << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1U << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1U << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1U << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1U << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1U << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1U << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1U << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1U << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1U << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1U << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1U << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1U << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1U << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FU << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01U << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02U << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04U << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08U << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10U << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20U << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1U << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1U << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1U << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1U << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1U << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)             /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)             /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1U << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1U << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1U << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1U << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1U << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1U << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1U << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1U << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1U << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1U << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1U << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1U << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FU << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1U << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1U << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1U << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1U << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1U << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1U << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1U << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1U << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1U << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1U << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1U << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1U << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1U << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1U << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1U << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1U << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1U << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1U << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1U << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1U << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1U << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFU << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFU << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1U << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1U << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FU << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1U << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1U << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1U << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1U << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1U << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1U << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1U << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1U << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1U << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1U << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFU << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_Fraction_Pos          (0U)                               
-#define USART_BRR_DIV_Fraction_Msk          (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_Fraction              USART_BRR_DIV_Fraction_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_Mantissa_Pos          (4U)                               
-#define USART_BRR_DIV_Mantissa_Msk          (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_Mantissa              USART_BRR_DIV_Mantissa_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1U << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1U << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1U << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1U << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1U << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1U << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1U << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1U << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1U << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1U << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1U << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1U << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1U << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1U << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFU << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1U << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1U << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1U << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1U << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1U << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1U << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3U << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1U << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2U << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1U << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1U << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1U << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1U << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1U << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1U << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1U << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1U << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1U << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1U << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1U << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1U << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFU << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01U << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02U << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04U << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08U << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10U << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20U << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40U << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80U << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFU << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos            (0U)                               
-#define DBGMCU_IDCODE_DEV_ID_Msk            (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                DBGMCU_IDCODE_DEV_ID_Msk           /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos            (16U)                              
-#define DBGMCU_IDCODE_REV_ID_Msk            (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                DBGMCU_IDCODE_REV_ID_Msk           /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0              (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1              (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2              (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3              (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4              (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5              (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6              (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7              (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8              (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9              (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10             (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11             (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12             (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13             (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14             (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15             (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos             (0U)                               
-#define DBGMCU_CR_DBG_SLEEP_Msk             (0x1U << DBGMCU_CR_DBG_SLEEP_Pos)  /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                 DBGMCU_CR_DBG_SLEEP_Msk            /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos              (1U)                               
-#define DBGMCU_CR_DBG_STOP_Msk              (0x1U << DBGMCU_CR_DBG_STOP_Pos)   /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                  DBGMCU_CR_DBG_STOP_Msk             /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos           (2U)                               
-#define DBGMCU_CR_DBG_STANDBY_Msk           (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY               DBGMCU_CR_DBG_STANDBY_Msk          /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos            (5U)                               
-#define DBGMCU_CR_TRACE_IOEN_Msk            (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                DBGMCU_CR_TRACE_IOEN_Msk           /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos            (6U)                               
-#define DBGMCU_CR_TRACE_MODE_Msk            (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                DBGMCU_CR_TRACE_MODE_Msk           /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0              (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1              (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-#define DBGMCU_CR_DBG_IWDG_STOP_Pos         (8U)                               
-#define DBGMCU_CR_DBG_IWDG_STOP_Msk         (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
-#define DBGMCU_CR_DBG_IWDG_STOP             DBGMCU_CR_DBG_IWDG_STOP_Msk        /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_CR_DBG_WWDG_STOP_Pos         (9U)                               
-#define DBGMCU_CR_DBG_WWDG_STOP_Msk         (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
-#define DBGMCU_CR_DBG_WWDG_STOP             DBGMCU_CR_DBG_WWDG_STOP_Msk        /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM1_STOP_Pos         (10U)                              
-#define DBGMCU_CR_DBG_TIM1_STOP_Msk         (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_CR_DBG_TIM1_STOP             DBGMCU_CR_DBG_TIM1_STOP_Msk        /*!< TIM1 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM2_STOP_Pos         (11U)                              
-#define DBGMCU_CR_DBG_TIM2_STOP_Msk         (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_CR_DBG_TIM2_STOP             DBGMCU_CR_DBG_TIM2_STOP_Msk        /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM3_STOP_Pos         (12U)                              
-#define DBGMCU_CR_DBG_TIM3_STOP_Msk         (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_CR_DBG_TIM3_STOP             DBGMCU_CR_DBG_TIM3_STOP_Msk        /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM4_STOP_Pos         (13U)                              
-#define DBGMCU_CR_DBG_TIM4_STOP_Msk         (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
-#define DBGMCU_CR_DBG_TIM4_STOP             DBGMCU_CR_DBG_TIM4_STOP_Msk        /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_CAN1_STOP_Pos         (14U)                              
-#define DBGMCU_CR_DBG_CAN1_STOP_Msk         (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */
-#define DBGMCU_CR_DBG_CAN1_STOP             DBGMCU_CR_DBG_CAN1_STOP_Msk        /*!< Debug CAN1 stopped when Core is halted */
-#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)                             
-#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
-#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)                             
-#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
-#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos               (0U)                               
-#define FLASH_ACR_LATENCY_Msk               (0x7U << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000007 */
-#define FLASH_ACR_LATENCY                   FLASH_ACR_LATENCY_Msk              /*!< LATENCY[2:0] bits (Latency) */
-#define FLASH_ACR_LATENCY_0                 (0x1U << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY_1                 (0x2U << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_LATENCY_2                 (0x4U << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000004 */
-
-#define FLASH_ACR_HLFCYA_Pos                (3U)                               
-#define FLASH_ACR_HLFCYA_Msk                (0x1U << FLASH_ACR_HLFCYA_Pos)     /*!< 0x00000008 */
-#define FLASH_ACR_HLFCYA                    FLASH_ACR_HLFCYA_Msk               /*!< Flash Half Cycle Access Enable */
-#define FLASH_ACR_PRFTBE_Pos                (4U)                               
-#define FLASH_ACR_PRFTBE_Msk                (0x1U << FLASH_ACR_PRFTBE_Pos)     /*!< 0x00000010 */
-#define FLASH_ACR_PRFTBE                    FLASH_ACR_PRFTBE_Msk               /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_PRFTBS_Pos                (5U)                               
-#define FLASH_ACR_PRFTBS_Msk                (0x1U << FLASH_ACR_PRFTBS_Pos)     /*!< 0x00000020 */
-#define FLASH_ACR_PRFTBS                    FLASH_ACR_PRFTBS_Msk               /*!< Prefetch Buffer Status */
-
-/******************  Bit definition for FLASH_KEYR register  ******************/
-#define FLASH_KEYR_FKEYR_Pos                (0U)                               
-#define FLASH_KEYR_FKEYR_Msk                (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_KEYR_FKEYR                    FLASH_KEYR_FKEYR_Msk               /*!< FPEC Key */
-
-#define RDP_KEY_Pos                         (0U)                               
-#define RDP_KEY_Msk                         (0xA5U << RDP_KEY_Pos)             /*!< 0x000000A5 */
-#define RDP_KEY                             RDP_KEY_Msk                        /*!< RDP Key */
-#define FLASH_KEY1_Pos                      (0U)                               
-#define FLASH_KEY1_Msk                      (0x45670123U << FLASH_KEY1_Pos)    /*!< 0x45670123 */
-#define FLASH_KEY1                          FLASH_KEY1_Msk                     /*!< FPEC Key1 */
-#define FLASH_KEY2_Pos                      (0U)                               
-#define FLASH_KEY2_Msk                      (0xCDEF89ABU << FLASH_KEY2_Pos)    /*!< 0xCDEF89AB */
-#define FLASH_KEY2                          FLASH_KEY2_Msk                     /*!< FPEC Key2 */
-
-/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos           (0U)                               
-#define FLASH_OPTKEYR_OPTKEYR_Msk           (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR               FLASH_OPTKEYR_OPTKEYR_Msk          /*!< Option Byte Key */
-
-#define  FLASH_OPTKEY1                       FLASH_KEY1                    /*!< Option Byte Key1 */
-#define  FLASH_OPTKEY2                       FLASH_KEY2                    /*!< Option Byte Key2 */
-
-/******************  Bit definition for FLASH_SR register  ********************/
-#define FLASH_SR_BSY_Pos                    (0U)                               
-#define FLASH_SR_BSY_Msk                    (0x1U << FLASH_SR_BSY_Pos)         /*!< 0x00000001 */
-#define FLASH_SR_BSY                        FLASH_SR_BSY_Msk                   /*!< Busy */
-#define FLASH_SR_PGERR_Pos                  (2U)                               
-#define FLASH_SR_PGERR_Msk                  (0x1U << FLASH_SR_PGERR_Pos)       /*!< 0x00000004 */
-#define FLASH_SR_PGERR                      FLASH_SR_PGERR_Msk                 /*!< Programming Error */
-#define FLASH_SR_WRPRTERR_Pos               (4U)                               
-#define FLASH_SR_WRPRTERR_Msk               (0x1U << FLASH_SR_WRPRTERR_Pos)    /*!< 0x00000010 */
-#define FLASH_SR_WRPRTERR                   FLASH_SR_WRPRTERR_Msk              /*!< Write Protection Error */
-#define FLASH_SR_EOP_Pos                    (5U)                               
-#define FLASH_SR_EOP_Msk                    (0x1U << FLASH_SR_EOP_Pos)         /*!< 0x00000020 */
-#define FLASH_SR_EOP                        FLASH_SR_EOP_Msk                   /*!< End of operation */
-
-/*******************  Bit definition for FLASH_CR register  *******************/
-#define FLASH_CR_PG_Pos                     (0U)                               
-#define FLASH_CR_PG_Msk                     (0x1U << FLASH_CR_PG_Pos)          /*!< 0x00000001 */
-#define FLASH_CR_PG                         FLASH_CR_PG_Msk                    /*!< Programming */
-#define FLASH_CR_PER_Pos                    (1U)                               
-#define FLASH_CR_PER_Msk                    (0x1U << FLASH_CR_PER_Pos)         /*!< 0x00000002 */
-#define FLASH_CR_PER                        FLASH_CR_PER_Msk                   /*!< Page Erase */
-#define FLASH_CR_MER_Pos                    (2U)                               
-#define FLASH_CR_MER_Msk                    (0x1U << FLASH_CR_MER_Pos)         /*!< 0x00000004 */
-#define FLASH_CR_MER                        FLASH_CR_MER_Msk                   /*!< Mass Erase */
-#define FLASH_CR_OPTPG_Pos                  (4U)                               
-#define FLASH_CR_OPTPG_Msk                  (0x1U << FLASH_CR_OPTPG_Pos)       /*!< 0x00000010 */
-#define FLASH_CR_OPTPG                      FLASH_CR_OPTPG_Msk                 /*!< Option Byte Programming */
-#define FLASH_CR_OPTER_Pos                  (5U)                               
-#define FLASH_CR_OPTER_Msk                  (0x1U << FLASH_CR_OPTER_Pos)       /*!< 0x00000020 */
-#define FLASH_CR_OPTER                      FLASH_CR_OPTER_Msk                 /*!< Option Byte Erase */
-#define FLASH_CR_STRT_Pos                   (6U)                               
-#define FLASH_CR_STRT_Msk                   (0x1U << FLASH_CR_STRT_Pos)        /*!< 0x00000040 */
-#define FLASH_CR_STRT                       FLASH_CR_STRT_Msk                  /*!< Start */
-#define FLASH_CR_LOCK_Pos                   (7U)                               
-#define FLASH_CR_LOCK_Msk                   (0x1U << FLASH_CR_LOCK_Pos)        /*!< 0x00000080 */
-#define FLASH_CR_LOCK                       FLASH_CR_LOCK_Msk                  /*!< Lock */
-#define FLASH_CR_OPTWRE_Pos                 (9U)                               
-#define FLASH_CR_OPTWRE_Msk                 (0x1U << FLASH_CR_OPTWRE_Pos)      /*!< 0x00000200 */
-#define FLASH_CR_OPTWRE                     FLASH_CR_OPTWRE_Msk                /*!< Option Bytes Write Enable */
-#define FLASH_CR_ERRIE_Pos                  (10U)                              
-#define FLASH_CR_ERRIE_Msk                  (0x1U << FLASH_CR_ERRIE_Pos)       /*!< 0x00000400 */
-#define FLASH_CR_ERRIE                      FLASH_CR_ERRIE_Msk                 /*!< Error Interrupt Enable */
-#define FLASH_CR_EOPIE_Pos                  (12U)                              
-#define FLASH_CR_EOPIE_Msk                  (0x1U << FLASH_CR_EOPIE_Pos)       /*!< 0x00001000 */
-#define FLASH_CR_EOPIE                      FLASH_CR_EOPIE_Msk                 /*!< End of operation interrupt enable */
-
-/*******************  Bit definition for FLASH_AR register  *******************/
-#define FLASH_AR_FAR_Pos                    (0U)                               
-#define FLASH_AR_FAR_Msk                    (0xFFFFFFFFU << FLASH_AR_FAR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_AR_FAR                        FLASH_AR_FAR_Msk                   /*!< Flash Address */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_OPTERR_Pos                (0U)                               
-#define FLASH_OBR_OPTERR_Msk                (0x1U << FLASH_OBR_OPTERR_Pos)     /*!< 0x00000001 */
-#define FLASH_OBR_OPTERR                    FLASH_OBR_OPTERR_Msk               /*!< Option Byte Error */
-#define FLASH_OBR_RDPRT_Pos                 (1U)                               
-#define FLASH_OBR_RDPRT_Msk                 (0x1U << FLASH_OBR_RDPRT_Pos)      /*!< 0x00000002 */
-#define FLASH_OBR_RDPRT                     FLASH_OBR_RDPRT_Msk                /*!< Read protection */
-
-#define FLASH_OBR_IWDG_SW_Pos               (2U)                               
-#define FLASH_OBR_IWDG_SW_Msk               (0x1U << FLASH_OBR_IWDG_SW_Pos)    /*!< 0x00000004 */
-#define FLASH_OBR_IWDG_SW                   FLASH_OBR_IWDG_SW_Msk              /*!< IWDG SW */
-#define FLASH_OBR_nRST_STOP_Pos             (3U)                               
-#define FLASH_OBR_nRST_STOP_Msk             (0x1U << FLASH_OBR_nRST_STOP_Pos)  /*!< 0x00000008 */
-#define FLASH_OBR_nRST_STOP                 FLASH_OBR_nRST_STOP_Msk            /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos            (4U)                               
-#define FLASH_OBR_nRST_STDBY_Msk            (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
-#define FLASH_OBR_nRST_STDBY                FLASH_OBR_nRST_STDBY_Msk           /*!< nRST_STDBY */
-#define FLASH_OBR_USER_Pos                  (2U)                               
-#define FLASH_OBR_USER_Msk                  (0x7U << FLASH_OBR_USER_Pos)       /*!< 0x0000001C */
-#define FLASH_OBR_USER                      FLASH_OBR_USER_Msk                 /*!< User Option Bytes */
-#define FLASH_OBR_DATA0_Pos                 (10U)                              
-#define FLASH_OBR_DATA0_Msk                 (0xFFU << FLASH_OBR_DATA0_Pos)     /*!< 0x0003FC00 */
-#define FLASH_OBR_DATA0                     FLASH_OBR_DATA0_Msk                /*!< Data0 */
-#define FLASH_OBR_DATA1_Pos                 (18U)                              
-#define FLASH_OBR_DATA1_Msk                 (0xFFU << FLASH_OBR_DATA1_Pos)     /*!< 0x03FC0000 */
-#define FLASH_OBR_DATA1                     FLASH_OBR_DATA1_Msk                /*!< Data1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos                  (0U)                               
-#define FLASH_WRPR_WRP_Msk                  (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR_WRP                      FLASH_WRPR_WRP_Msk                 /*!< Write Protect */
-
-/*----------------------------------------------------------------------------*/
-
-/******************  Bit definition for FLASH_RDP register  *******************/
-#define FLASH_RDP_RDP_Pos                   (0U)                               
-#define FLASH_RDP_RDP_Msk                   (0xFFU << FLASH_RDP_RDP_Pos)       /*!< 0x000000FF */
-#define FLASH_RDP_RDP                       FLASH_RDP_RDP_Msk                  /*!< Read protection option byte */
-#define FLASH_RDP_nRDP_Pos                  (8U)                               
-#define FLASH_RDP_nRDP_Msk                  (0xFFU << FLASH_RDP_nRDP_Pos)      /*!< 0x0000FF00 */
-#define FLASH_RDP_nRDP                      FLASH_RDP_nRDP_Msk                 /*!< Read protection complemented option byte */
-
-/******************  Bit definition for FLASH_USER register  ******************/
-#define FLASH_USER_USER_Pos                 (16U)                              
-#define FLASH_USER_USER_Msk                 (0xFFU << FLASH_USER_USER_Pos)     /*!< 0x00FF0000 */
-#define FLASH_USER_USER                     FLASH_USER_USER_Msk                /*!< User option byte */
-#define FLASH_USER_nUSER_Pos                (24U)                              
-#define FLASH_USER_nUSER_Msk                (0xFFU << FLASH_USER_nUSER_Pos)    /*!< 0xFF000000 */
-#define FLASH_USER_nUSER                    FLASH_USER_nUSER_Msk               /*!< User complemented option byte */
-
-/******************  Bit definition for FLASH_Data0 register  *****************/
-#define FLASH_DATA0_DATA0_Pos               (0U)                               
-#define FLASH_DATA0_DATA0_Msk               (0xFFU << FLASH_DATA0_DATA0_Pos)   /*!< 0x000000FF */
-#define FLASH_DATA0_DATA0                   FLASH_DATA0_DATA0_Msk              /*!< User data storage option byte */
-#define FLASH_DATA0_nDATA0_Pos              (8U)                               
-#define FLASH_DATA0_nDATA0_Msk              (0xFFU << FLASH_DATA0_nDATA0_Pos)  /*!< 0x0000FF00 */
-#define FLASH_DATA0_nDATA0                  FLASH_DATA0_nDATA0_Msk             /*!< User data storage complemented option byte */
-
-/******************  Bit definition for FLASH_Data1 register  *****************/
-#define FLASH_DATA1_DATA1_Pos               (16U)                              
-#define FLASH_DATA1_DATA1_Msk               (0xFFU << FLASH_DATA1_DATA1_Pos)   /*!< 0x00FF0000 */
-#define FLASH_DATA1_DATA1                   FLASH_DATA1_DATA1_Msk              /*!< User data storage option byte */
-#define FLASH_DATA1_nDATA1_Pos              (24U)                              
-#define FLASH_DATA1_nDATA1_Msk              (0xFFU << FLASH_DATA1_nDATA1_Pos)  /*!< 0xFF000000 */
-#define FLASH_DATA1_nDATA1                  FLASH_DATA1_nDATA1_Msk             /*!< User data storage complemented option byte */
-
-/******************  Bit definition for FLASH_WRP0 register  ******************/
-#define FLASH_WRP0_WRP0_Pos                 (0U)                               
-#define FLASH_WRP0_WRP0_Msk                 (0xFFU << FLASH_WRP0_WRP0_Pos)     /*!< 0x000000FF */
-#define FLASH_WRP0_WRP0                     FLASH_WRP0_WRP0_Msk                /*!< Flash memory write protection option bytes */
-#define FLASH_WRP0_nWRP0_Pos                (8U)                               
-#define FLASH_WRP0_nWRP0_Msk                (0xFFU << FLASH_WRP0_nWRP0_Pos)    /*!< 0x0000FF00 */
-#define FLASH_WRP0_nWRP0                    FLASH_WRP0_nWRP0_Msk               /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for FLASH_WRP1 register  ******************/
-#define FLASH_WRP1_WRP1_Pos                 (16U)                              
-#define FLASH_WRP1_WRP1_Msk                 (0xFFU << FLASH_WRP1_WRP1_Pos)     /*!< 0x00FF0000 */
-#define FLASH_WRP1_WRP1                     FLASH_WRP1_WRP1_Msk                /*!< Flash memory write protection option bytes */
-#define FLASH_WRP1_nWRP1_Pos                (24U)                              
-#define FLASH_WRP1_nWRP1_Msk                (0xFFU << FLASH_WRP1_nWRP1_Pos)    /*!< 0xFF000000 */
-#define FLASH_WRP1_nWRP1                    FLASH_WRP1_nWRP1_Msk               /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for FLASH_WRP2 register  ******************/
-#define FLASH_WRP2_WRP2_Pos                 (0U)                               
-#define FLASH_WRP2_WRP2_Msk                 (0xFFU << FLASH_WRP2_WRP2_Pos)     /*!< 0x000000FF */
-#define FLASH_WRP2_WRP2                     FLASH_WRP2_WRP2_Msk                /*!< Flash memory write protection option bytes */
-#define FLASH_WRP2_nWRP2_Pos                (8U)                               
-#define FLASH_WRP2_nWRP2_Msk                (0xFFU << FLASH_WRP2_nWRP2_Pos)    /*!< 0x0000FF00 */
-#define FLASH_WRP2_nWRP2                    FLASH_WRP2_nWRP2_Msk               /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for FLASH_WRP3 register  ******************/
-#define FLASH_WRP3_WRP3_Pos                 (16U)                              
-#define FLASH_WRP3_WRP3_Msk                 (0xFFU << FLASH_WRP3_WRP3_Pos)     /*!< 0x00FF0000 */
-#define FLASH_WRP3_WRP3                     FLASH_WRP3_WRP3_Msk                /*!< Flash memory write protection option bytes */
-#define FLASH_WRP3_nWRP3_Pos                (24U)                              
-#define FLASH_WRP3_nWRP3_Msk                (0xFFU << FLASH_WRP3_nWRP3_Pos)    /*!< 0xFF000000 */
-#define FLASH_WRP3_nWRP3                    FLASH_WRP3_nWRP3_Msk               /*!< Flash memory write protection complemented option bytes */
-
-
-
-/**
-  * @}
-*/
-
-/**
-  * @}
-*/ 
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
-                                       ((INSTANCE) == ADC2))
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
-
-#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-/****************************** CAN Instances *********************************/    
-#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-  
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************************** START TIM Instances ***************************/
-/****************************** TIM Instances *********************************/
-#define IS_TIM_INSTANCE(INSTANCE)\
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE)\
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE)\
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE)\
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE)\
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE)\
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
-
-#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
-  ((INSTANCE) == TIM1)
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4))))
-
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-    (((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
-
-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
-  ((INSTANCE) == TIM1)
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE)\
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
-    
-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
-  ((INSTANCE) == TIM1)
-
-/****************************** END TIM Instances *****************************/
-
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                               ((INSTANCE) == USART2) || \
-                                               ((INSTANCE) == USART3))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                        ((INSTANCE) == USART2) || \
-                                        ((INSTANCE) == USART3))
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                   ((INSTANCE) == USART2) || \
-                                                   ((INSTANCE) == USART3))
-
-/***************** UART Instances : DMA mode available **********************/
-#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                        ((INSTANCE) == USART2) || \
-                                        ((INSTANCE) == USART3))
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/**************************** WWDG Instances *****************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == USB)
-
-
-
-
-/**
-  * @}
-*/ 
-/******************************************************************************/
-/*  For a painless codes migration between the STM32F1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32F1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-#define ADC1_IRQn               ADC1_2_IRQn
-#define TIM1_BRK_TIM15_IRQn     TIM1_BRK_IRQn
-#define TIM1_BRK_TIM9_IRQn      TIM1_BRK_IRQn
-#define TIM9_IRQn               TIM1_BRK_IRQn
-#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
-#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
-#define TIM11_IRQn              TIM1_TRG_COM_IRQn
-#define TIM10_IRQn              TIM1_UP_IRQn
-#define TIM1_UP_TIM16_IRQn      TIM1_UP_IRQn
-#define TIM1_UP_TIM10_IRQn      TIM1_UP_IRQn
-#define CEC_IRQn                USBWakeUp_IRQn
-#define OTG_FS_WKUP_IRQn        USBWakeUp_IRQn
-#define CAN1_TX_IRQn            USB_HP_CAN1_TX_IRQn
-#define USB_HP_IRQn             USB_HP_CAN1_TX_IRQn
-#define USB_LP_IRQn             USB_LP_CAN1_RX0_IRQn
-#define CAN1_RX0_IRQn           USB_LP_CAN1_RX0_IRQn
-
-
-/* Aliases for __IRQHandler */
-#define ADC1_IRQHandler               ADC1_2_IRQHandler
-#define TIM1_BRK_TIM15_IRQHandler     TIM1_BRK_IRQHandler
-#define TIM1_BRK_TIM9_IRQHandler      TIM1_BRK_IRQHandler
-#define TIM9_IRQHandler               TIM1_BRK_IRQHandler
-#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM11_IRQHandler              TIM1_TRG_COM_IRQHandler
-#define TIM10_IRQHandler              TIM1_UP_IRQHandler
-#define TIM1_UP_TIM16_IRQHandler      TIM1_UP_IRQHandler
-#define TIM1_UP_TIM10_IRQHandler      TIM1_UP_IRQHandler
-#define CEC_IRQHandler                USBWakeUp_IRQHandler
-#define OTG_FS_WKUP_IRQHandler        USBWakeUp_IRQHandler
-#define CAN1_TX_IRQHandler            USB_HP_CAN1_TX_IRQHandler
-#define USB_HP_IRQHandler             USB_HP_CAN1_TX_IRQHandler
-#define USB_LP_IRQHandler             USB_LP_CAN1_RX0_IRQHandler
-#define CAN1_RX0_IRQHandler           USB_LP_CAN1_RX0_IRQHandler
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-#ifdef __cplusplus
-  }
-#endif /* __cplusplus */
-  
-#endif /* __STM32F103xB_H */
-  
-  
-  
-  /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,238 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx.h
-  * @author  MCD Application Team
-  * @version V4.1.0
-  * @date    29-April-2016
-  * @brief   CMSIS STM32F1xx Device Peripheral Access Layer Header File. 
-  *
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *            - Configuration section that allows to select:
-  *              - The STM32F1xx device used in the target application
-  *              - To use or not the peripheral’s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral’s registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_HAL_DRIVER"
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f1xx
-  * @{
-  */
-    
-#ifndef __STM32F1XX_H
-#define __STM32F1XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-
-/**
-  * @brief STM32 Family
-  */
-#if !defined (STM32F1)
-#define STM32F1
-#endif /* STM32F1 */
-
-/* Uncomment the line below according to the target STM32L device used in your 
-   application 
-  */
-
-#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
-    !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
-    !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
-  /* #define STM32F100xB */   /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
-  /* #define STM32F100xE */   /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
-  /* #define STM32F101x6 */   /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
-  /* #define STM32F101xB */   /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
-  /* #define STM32F101xE */   /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ 
-  /* #define STM32F101xG */   /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
-  /* #define STM32F102x6 */   /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
-  /* #define STM32F102xB */   /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
-  /* #define STM32F103x6 */   /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
-#define STM32F103xB           /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
-  /* #define STM32F103xE */   /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
-  /* #define STM32F103xG */   /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
-  /* #define STM32F105xC */   /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
-  /* #define STM32F107xC */   /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */  
-#endif
-
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-  
-#if !defined  (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-#define USE_HAL_DRIVER
-#endif /* USE_HAL_DRIVER */
-
-/**
-  * @brief CMSIS Device version number V4.0.0
-  */
-#define __STM32F1_CMSIS_VERSION_MAIN   (0x04) /*!< [31:24] main version */                                  
-#define __STM32F1_CMSIS_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
-#define __STM32F1_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32F1_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32F1_CMSIS_VERSION        ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
-                                       |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
-                                       |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
-                                       |(__STM32F1_CMSIS_VERSION_RC))
-
-/**
-  * @}
-  */
-
-/** @addtogroup Device_Included
-  * @{
-  */
-
-#if defined(STM32F100xB)
-  #include "stm32f100xb.h"
-#elif defined(STM32F100xE)
-  #include "stm32f100xe.h"
-#elif defined(STM32F101x6)
-  #include "stm32f101x6.h"
-#elif defined(STM32F101xB)
-  #include "stm32f101xb.h"
-#elif defined(STM32F101xE)
-  #include "stm32f101xe.h"
-#elif defined(STM32F101xG)
-  #include "stm32f101xg.h"
-#elif defined(STM32F102x6)
-  #include "stm32f102x6.h"
-#elif defined(STM32F102xB)
-  #include "stm32f102xb.h"
-#elif defined(STM32F103x6)
-  #include "stm32f103x6.h"
-#elif defined(STM32F103xB)
-  #include "stm32f103xb.h"
-#elif defined(STM32F103xE)
-  #include "stm32f103xe.h"
-#elif defined(STM32F103xG)
-  #include "stm32f103xg.h"
-#elif defined(STM32F105xC)
-  #include "stm32f105xc.h"
-#elif defined(STM32F107xC)
-  #include "stm32f107xc.h"
-#else
- #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_types
-  * @{
-  */  
-typedef enum 
-{
-  RESET = 0, 
-  SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum 
-{
-  DISABLE = 0, 
-  ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum 
-{
-  ERROR = 0, 
-  SUCCESS = !ERROR
-} ErrorStatus;
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
-
-
-/**
-  * @}
-  */
-
-#if defined (USE_HAL_DRIVER)
- #include "stm32f1xx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F1xx_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,328 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   This file contains all the functions prototypes for the HAL 
-  *          module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_H
-#define __STM32F1xx_HAL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_conf.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup HAL
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Macros HAL Exported Macros
-  * @{
-  */
-
-/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
-  * @brief   Freeze/Unfreeze Peripherals in Debug mode 
-  * Note: On devices STM32F10xx8 and STM32F10xxB,
-  *                  STM32F101xC/D/E and STM32F103xC/D/E,
-  *                  STM32F101xF/G and STM32F103xF/G
-  *                  STM32F10xx4 and STM32F10xx6
-  *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in 
-  *       debug mode (not accessible by the user software in normal mode).
-  *       Refer to errata sheet of these devices for more details.
-  * @{
-  */
-   
-/* Peripherals on APB1 */
-/**
-  * @brief  TIM2 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_TIM2()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM2()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
-
-/**
-  * @brief  TIM3 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_TIM3()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM3()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
-
-#if defined (DBGMCU_CR_DBG_TIM4_STOP)
-/**
-  * @brief  TIM4 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_TIM4()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM4()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM5_STOP)
-/**
-  * @brief  TIM5 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_TIM5()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM5()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM6_STOP)
-/**
-  * @brief  TIM6 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_TIM6()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM6()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM7_STOP)
-/**
-  * @brief  TIM7 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_TIM7()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM7()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM12_STOP)
-/**
-  * @brief  TIM12 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_TIM12()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM12()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM13_STOP)
-/**
-  * @brief  TIM13 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_TIM13()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM13()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM14_STOP)
-/**
-  * @brief  TIM14 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_TIM14()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM14()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
-#endif
-
-/**
-  * @brief  WWDG Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_WWDG()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
-#define __HAL_DBGMCU_UNFREEZE_WWDG()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
-
-/**
-  * @brief  IWDG Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_IWDG()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
-#define __HAL_DBGMCU_UNFREEZE_IWDG()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
-
-/**
-  * @brief  I2C1 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()    SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
-#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
-
-#if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
-/**
-  * @brief  I2C2 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()    SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
-#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT()  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
-#endif
-
-#if defined (DBGMCU_CR_DBG_CAN1_STOP)
-/**
-  * @brief  CAN1 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_CAN1()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_CAN1()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_CAN2_STOP)
-/**
-  * @brief  CAN2 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_CAN2()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_CAN2()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
-#endif   
-   
-/* Peripherals on APB2 */
-#if defined (DBGMCU_CR_DBG_TIM1_STOP)
-/**
-  * @brief  TIM1 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_TIM1()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM1()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM8_STOP)
-/**
-  * @brief  TIM8 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_TIM8()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM8()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM9_STOP)
-/**
-  * @brief  TIM9 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_TIM9()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM9()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM10_STOP)
-/**
-  * @brief  TIM10 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_TIM10()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM10()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM11_STOP)
-/**
-  * @brief  TIM11 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_TIM11()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM11()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
-#endif
-
-
-#if defined (DBGMCU_CR_DBG_TIM15_STOP)
-/**
-  * @brief  TIM15 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_TIM15()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM15()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM16_STOP)
-/**
-  * @brief  TIM16 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_TIM16()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM16()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM17_STOP)
-/**
-  * @brief  TIM17 Peripherals Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_TIM17()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM17()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup HAL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup HAL_Exported_Functions_Group1
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ******************************/
-HAL_StatusTypeDef HAL_Init(void);
-HAL_StatusTypeDef HAL_DeInit(void);
-void              HAL_MspInit(void);
-void              HAL_MspDeInit(void);
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
-
-/**
-  * @}
-  */
-
-/** @addtogroup HAL_Exported_Functions_Group2
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-void              HAL_IncTick(void);
-void              HAL_Delay(__IO uint32_t Delay);
-uint32_t          HAL_GetTick(void);
-void              HAL_SuspendTick(void);
-void              HAL_ResumeTick(void);
-uint32_t          HAL_GetHalVersion(void);
-uint32_t          HAL_GetREVID(void);
-uint32_t          HAL_GetDEVID(void);
-void              HAL_DBGMCU_EnableDBGSleepMode(void);
-void              HAL_DBGMCU_DisableDBGSleepMode(void);
-void              HAL_DBGMCU_EnableDBGStopMode(void);
-void              HAL_DBGMCU_DisableDBGStopMode(void);
-void              HAL_DBGMCU_EnableDBGStandbyMode(void);
-void              HAL_DBGMCU_DisableDBGStandbyMode(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_adc.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,967 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_adc.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file containing functions prototypes of ADC HAL library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_ADC_H
-#define __STM32F1xx_HAL_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"  
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup ADC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup ADC_Exported_Types ADC Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  Structure definition of ADC and regular group initialization 
-  * @note   Parameters of this structure are shared within 2 scopes:
-  *          - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
-  *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
-  * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
-  *         ADC can be either disabled or enabled without conversion on going on regular group.
-  */
-typedef struct
-{
-  uint32_t DataAlign;             /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
-                                       or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
-                                       This parameter can be a value of @ref ADC_Data_align */
-  uint32_t ScanConvMode;          /*!< Configures the sequencer of regular and injected groups.
-                                       This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
-                                       If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
-                                                    Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
-                                       If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
-                                                    Scan direction is upward: from rank1 to rank 'n'.
-                                       This parameter can be a value of @ref ADC_Scan_mode
-                                       Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1)
-                                             or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
-                                             the last conversion of the sequence. All previous conversions would be overwritten by the last one.
-                                             Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
-  uint32_t ContinuousConvMode;    /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
-                                       after the selected trigger occurred (software start or external trigger).
-                                       This parameter can be set to ENABLE or DISABLE. */
-  uint32_t NbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
-                                       To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
-                                       This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
-  uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
-                                       Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
-                                       Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
-                                       This parameter can be set to ENABLE or DISABLE. */
-  uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.
-                                       If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
-                                       This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
-  uint32_t ExternalTrigConv;      /*!< Selects the external event used to trigger the conversion start of regular group.
-                                       If set to ADC_SOFTWARE_START, external triggers are disabled.
-                                       If set to external trigger source, triggering is on event rising edge.
-                                       This parameter can be a value of @ref ADC_External_trigger_source_Regular */
-}ADC_InitTypeDef;
-
-/** 
-  * @brief  Structure definition of ADC channel for regular group   
-  * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
-  *         ADC can be either disabled or enabled without conversion on going on regular group.
-  */ 
-typedef struct 
-{
-  uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
-                                        This parameter can be a value of @ref ADC_channels
-                                        Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
-                                        Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) 
-                                        Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
-                                              It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
-                                              Refer to errata sheet of these devices for more details. */
-  uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer 
-                                        This parameter can be a value of @ref ADC_regular_rank
-                                        Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
-  uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
-                                        Unit: ADC clock cycles
-                                        Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
-                                        This parameter can be a value of @ref ADC_sampling_times
-                                        Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
-                                                 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
-                                        Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
-                                              sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
-                                              Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
-}ADC_ChannelConfTypeDef;
-
-/**
-  * @brief  ADC Configuration analog watchdog definition
-  * @note   The setting of these parameters with function is conditioned to ADC state.
-  *         ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
-  */
-typedef struct
-{
-  uint32_t WatchdogMode;      /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
-                                   This parameter can be a value of @ref ADC_analog_watchdog_mode. */
-  uint32_t Channel;           /*!< Selects which ADC channel to monitor by analog watchdog.
-                                   This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
-                                   This parameter can be a value of @ref ADC_channels. */
-  uint32_t ITMode;            /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
-                                   This parameter can be set to ENABLE or DISABLE */
-  uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
-                                   This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
-  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.
-                                   This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
-  uint32_t WatchdogNumber;    /*!< Reserved for future use, can be set to 0 */
-}ADC_AnalogWDGConfTypeDef;
-
-/** 
-  * @brief  HAL ADC state machine: ADC states definition (bitfields)
-  */ 
-/* States of ADC global scope */
-#define HAL_ADC_STATE_RESET             ((uint32_t)0x00000000)    /*!< ADC not yet initialized or disabled */
-#define HAL_ADC_STATE_READY             ((uint32_t)0x00000001)    /*!< ADC peripheral ready for use */
-#define HAL_ADC_STATE_BUSY_INTERNAL     ((uint32_t)0x00000002)    /*!< ADC is busy to internal process (initialization, calibration) */
-#define HAL_ADC_STATE_TIMEOUT           ((uint32_t)0x00000004)    /*!< TimeOut occurrence */
-
-/* States of ADC errors */
-#define HAL_ADC_STATE_ERROR_INTERNAL    ((uint32_t)0x00000010)    /*!< Internal error occurrence */
-#define HAL_ADC_STATE_ERROR_CONFIG      ((uint32_t)0x00000020)    /*!< Configuration error occurrence */
-#define HAL_ADC_STATE_ERROR_DMA         ((uint32_t)0x00000040)    /*!< DMA error occurrence */
-
-/* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY          ((uint32_t)0x00000100)    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
-                                                                       external trigger, low power auto power-on, multimode ADC master control) */
-#define HAL_ADC_STATE_REG_EOC           ((uint32_t)0x00000200)    /*!< Conversion data available on group regular */
-#define HAL_ADC_STATE_REG_OVR           ((uint32_t)0x00000400)    /*!< Not available on STM32F1 device: Overrun occurrence */
-#define HAL_ADC_STATE_REG_EOSMP         ((uint32_t)0x00000800)    /*!< Not available on STM32F1 device: End Of Sampling flag raised  */
-
-/* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY          ((uint32_t)0x00001000)    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
-                                                                       external trigger, low power auto power-on, multimode ADC master control) */
-#define HAL_ADC_STATE_INJ_EOC           ((uint32_t)0x00002000)    /*!< Conversion data available on group injected */
-#define HAL_ADC_STATE_INJ_JQOVF         ((uint32_t)0x00004000)    /*!< Not available on STM32F1 device: Injected queue overflow occurrence */
-
-/* States of ADC analog watchdogs */
-#define HAL_ADC_STATE_AWD1              ((uint32_t)0x00010000)    /*!< Out-of-window occurrence of analog watchdog 1 */
-#define HAL_ADC_STATE_AWD2              ((uint32_t)0x00020000)    /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */
-#define HAL_ADC_STATE_AWD3              ((uint32_t)0x00040000)    /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */
-
-/* States of ADC multi-mode */
-#define HAL_ADC_STATE_MULTIMODE_SLAVE   ((uint32_t)0x00100000)    /*!< ADC in multimode slave state, controlled by another ADC master ( */
-
-
-/** 
-  * @brief  ADC handle Structure definition  
-  */ 
-typedef struct
-{
-  ADC_TypeDef                   *Instance;              /*!< Register base address */
-
-  ADC_InitTypeDef               Init;                   /*!< ADC required parameters */
-
-  DMA_HandleTypeDef             *DMA_Handle;            /*!< Pointer DMA Handler */
-
-  HAL_LockTypeDef               Lock;                   /*!< ADC locking object */
-  
-  __IO uint32_t                 State;                  /*!< ADC communication state (bitmap of ADC states) */
-
-  __IO uint32_t                 ErrorCode;              /*!< ADC Error code */
-}ADC_HandleTypeDef;
-/**
-  * @}
-  */
-
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Constants ADC Exported Constants
-  * @{
-  */
-
-/** @defgroup ADC_Error_Code ADC Error Code
-  * @{
-  */
-#define HAL_ADC_ERROR_NONE        ((uint32_t)0x00)   /*!< No error                                              */
-#define HAL_ADC_ERROR_INTERNAL    ((uint32_t)0x01)   /*!< ADC IP internal error: if problem of clocking, 
-                                                          enable/disable, erroneous state                       */
-#define HAL_ADC_ERROR_OVR         ((uint32_t)0x02)   /*!< Overrun error                                         */
-#define HAL_ADC_ERROR_DMA         ((uint32_t)0x04)   /*!< DMA transfer error                                    */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup ADC_Data_align ADC data alignment
-  * @{
-  */
-#define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000)
-#define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Scan_mode ADC scan mode
-  * @{
-  */
-/* Note: Scan mode values are not among binary choices ENABLE/DISABLE for     */
-/*       compatibility with other STM32 devices having a sequencer with       */
-/*       additional options.                                                  */
-#define ADC_SCAN_DISABLE         ((uint32_t)0x00000000)
-#define ADC_SCAN_ENABLE          ((uint32_t)ADC_CR1_SCAN)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
-  * @{
-  */
-#define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000)
-#define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTTRIG)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_channels ADC channels
-  * @{
-  */
-/* Note: Depending on devices, some channels may not be available on package  */
-/*       pins. Refer to device datasheet for channels availability.           */
-#define ADC_CHANNEL_0           ((uint32_t)0x00000000)                                                                          
-#define ADC_CHANNEL_1           ((uint32_t)(                                                                    ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_2           ((uint32_t)(                                                   ADC_SQR3_SQ1_1                 ))
-#define ADC_CHANNEL_3           ((uint32_t)(                                                   ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_4           ((uint32_t)(                                  ADC_SQR3_SQ1_2                                  ))
-#define ADC_CHANNEL_5           ((uint32_t)(                                  ADC_SQR3_SQ1_2                  | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_6           ((uint32_t)(                                  ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1                 ))
-#define ADC_CHANNEL_7           ((uint32_t)(                                  ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_8           ((uint32_t)(                 ADC_SQR3_SQ1_3                                                   ))
-#define ADC_CHANNEL_9           ((uint32_t)(                 ADC_SQR3_SQ1_3                                   | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_10          ((uint32_t)(                 ADC_SQR3_SQ1_3                  | ADC_SQR3_SQ1_1                 ))
-#define ADC_CHANNEL_11          ((uint32_t)(                 ADC_SQR3_SQ1_3                  | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_12          ((uint32_t)(                 ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2                                  ))
-#define ADC_CHANNEL_13          ((uint32_t)(                 ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2                  | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_14          ((uint32_t)(                 ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1                 ))
-#define ADC_CHANNEL_15          ((uint32_t)(                 ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_16          ((uint32_t)(ADC_SQR3_SQ1_4                                                                    ))
-#define ADC_CHANNEL_17          ((uint32_t)(ADC_SQR3_SQ1_4                                                    | ADC_SQR3_SQ1_0))
-
-#define ADC_CHANNEL_TEMPSENSOR  ADC_CHANNEL_16  /* ADC internal channel (no connection on device pin) */
-#define ADC_CHANNEL_VREFINT     ADC_CHANNEL_17  /* ADC internal channel (no connection on device pin) */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_sampling_times ADC sampling times
-  * @{
-  */
-#define ADC_SAMPLETIME_1CYCLE_5       ((uint32_t)0x00000000)                                               /*!< Sampling time 1.5 ADC clock cycle */
-#define ADC_SAMPLETIME_7CYCLES_5      ((uint32_t)(                                      ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */
-#define ADC_SAMPLETIME_13CYCLES_5     ((uint32_t)(                   ADC_SMPR2_SMP0_1                   )) /*!< Sampling time 13.5 ADC clock cycles */
-#define ADC_SAMPLETIME_28CYCLES_5     ((uint32_t)(                   ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */
-#define ADC_SAMPLETIME_41CYCLES_5     ((uint32_t)(ADC_SMPR2_SMP0_2                                      )) /*!< Sampling time 41.5 ADC clock cycles */
-#define ADC_SAMPLETIME_55CYCLES_5     ((uint32_t)(ADC_SMPR2_SMP0_2                    | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */
-#define ADC_SAMPLETIME_71CYCLES_5     ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1                   )) /*!< Sampling time 71.5 ADC clock cycles */
-#define ADC_SAMPLETIME_239CYCLES_5    ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_regular_rank ADC rank into regular group
-  * @{
-  */
-#define ADC_REGULAR_RANK_1    ((uint32_t)0x00000001)
-#define ADC_REGULAR_RANK_2    ((uint32_t)0x00000002)
-#define ADC_REGULAR_RANK_3    ((uint32_t)0x00000003)
-#define ADC_REGULAR_RANK_4    ((uint32_t)0x00000004)
-#define ADC_REGULAR_RANK_5    ((uint32_t)0x00000005)
-#define ADC_REGULAR_RANK_6    ((uint32_t)0x00000006)
-#define ADC_REGULAR_RANK_7    ((uint32_t)0x00000007)
-#define ADC_REGULAR_RANK_8    ((uint32_t)0x00000008)
-#define ADC_REGULAR_RANK_9    ((uint32_t)0x00000009)
-#define ADC_REGULAR_RANK_10   ((uint32_t)0x0000000A)
-#define ADC_REGULAR_RANK_11   ((uint32_t)0x0000000B)
-#define ADC_REGULAR_RANK_12   ((uint32_t)0x0000000C)
-#define ADC_REGULAR_RANK_13   ((uint32_t)0x0000000D)
-#define ADC_REGULAR_RANK_14   ((uint32_t)0x0000000E)
-#define ADC_REGULAR_RANK_15   ((uint32_t)0x0000000F)
-#define ADC_REGULAR_RANK_16   ((uint32_t)0x00000010)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
-  * @{
-  */
-#define ADC_ANALOGWATCHDOG_NONE                 ((uint32_t)0x00000000)
-#define ADC_ANALOGWATCHDOG_SINGLE_REG           ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
-#define ADC_ANALOGWATCHDOG_SINGLE_INJEC         ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC      ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_ALL_REG              ((uint32_t) ADC_CR1_AWDEN)
-#define ADC_ANALOGWATCHDOG_ALL_INJEC            ((uint32_t) ADC_CR1_JAWDEN)
-#define ADC_ANALOGWATCHDOG_ALL_REGINJEC         ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-/**
-  * @}
-  */
-
-/** @defgroup ADC_conversion_group ADC conversion group
-  * @{
-  */
-#define ADC_REGULAR_GROUP             ((uint32_t)(ADC_FLAG_EOC))
-#define ADC_INJECTED_GROUP            ((uint32_t)(ADC_FLAG_JEOC))
-#define ADC_REGULAR_INJECTED_GROUP    ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Event_type ADC Event type
-  * @{
-  */
-#define ADC_AWD_EVENT               ((uint32_t)ADC_FLAG_AWD)   /*!< ADC Analog watchdog event */
-
-#define ADC_AWD1_EVENT              ADC_AWD_EVENT              /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_interrupts_definition ADC interrupts definition
-  * @{
-  */
-#define ADC_IT_EOC           ADC_CR1_EOCIE        /*!< ADC End of Regular Conversion interrupt source */
-#define ADC_IT_JEOC          ADC_CR1_JEOCIE       /*!< ADC End of Injected Conversion interrupt source */
-#define ADC_IT_AWD           ADC_CR1_AWDIE        /*!< ADC Analog watchdog interrupt source */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_flags_definition ADC flags definition
-  * @{
-  */
-#define ADC_FLAG_STRT          ADC_SR_STRT     /*!< ADC Regular group start flag */
-#define ADC_FLAG_JSTRT         ADC_SR_JSTRT    /*!< ADC Injected group start flag */
-#define ADC_FLAG_EOC           ADC_SR_EOC      /*!< ADC End of Regular conversion flag */
-#define ADC_FLAG_JEOC          ADC_SR_JEOC     /*!< ADC End of Injected conversion flag */
-#define ADC_FLAG_AWD           ADC_SR_AWD      /*!< ADC Analog watchdog flag */
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */ 
-
-/* Private constants ---------------------------------------------------------*/
-
-/** @addtogroup ADC_Private_Constants ADC Private Constants
-  * @{
-  */
-
-/** @defgroup ADC_conversion_cycles ADC conversion cycles
-  * @{
-  */
-/* ADC conversion cycles (unit: ADC clock cycles)                           */
-/* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
-/* resolution 12 bits)                                                      */
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5    ((uint32_t) 14)
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5   ((uint32_t) 20)
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5  ((uint32_t) 26)
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5  ((uint32_t) 41)
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5  ((uint32_t) 54)
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5  ((uint32_t) 68)
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5  ((uint32_t) 84)
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 ((uint32_t)252)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
-  * @{
-  */
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2                                          \
-     (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 |     \
-      ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 |     \
-      ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2                                          \
-     (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \
-      ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 )
-
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1                                          \
-     (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 |     \
-      ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 |     \
-      ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1                                          \
-     (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \
-      ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 )
-
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0                                          \
-     (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 |     \
-      ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 |     \
-      ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0                                          \
-     (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \
-      ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )
-
-#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS    ((uint32_t)0x00000000)
-#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS   (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
-#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
-#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
-#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
-#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
-#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
-#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
-
-#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS    ((uint32_t)0x00000000)
-#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS   (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
-#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
-#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
-#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
-#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
-#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
-#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
-/**
-  * @}
-  */
-
-/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
-#define ADC_FLAG_POSTCONV_ALL   (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD )
-
-/**
-  * @}
-  */
-
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Macros ADC Exported Macros
-  * @{
-  */
-/* Macro for internal HAL driver usage, and possibly can be used into code of */
-/* final user.                                                                */    
-
-/**
-  * @brief Enable the ADC peripheral
-  * @note ADC enable requires a delay for ADC stabilization time
-  *       (refer to device datasheet, parameter tSTAB)
-  * @note On STM32F1, if ADC is already enabled this macro trigs a conversion 
-  *       SW start on regular group.
-  * @param __HANDLE__: ADC handle
-  * @retval None
-  */
-#define __HAL_ADC_ENABLE(__HANDLE__)                                           \
-  (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
-    
-/**
-  * @brief Disable the ADC peripheral
-  * @param __HANDLE__: ADC handle
-  * @retval None
-  */
-#define __HAL_ADC_DISABLE(__HANDLE__)                                          \
-  (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
-    
-/** @brief Enable the ADC end of conversion interrupt.
-  * @param __HANDLE__: ADC handle
-  * @param __INTERRUPT__: ADC Interrupt
-  *          This parameter can be any combination of the following values:
-  *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
-  *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
-  *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
-  * @retval None
-  */
-#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                         \
-  (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
-    
-/** @brief Disable the ADC end of conversion interrupt.
-  * @param __HANDLE__: ADC handle
-  * @param __INTERRUPT__: ADC Interrupt
-  *          This parameter can be any combination of the following values:
-  *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
-  *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
-  *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
-  * @retval None
-  */
-#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                        \
-  (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
-
-/** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
-  * @param __HANDLE__: ADC handle
-  * @param __INTERRUPT__: ADC interrupt source to check
-  *          This parameter can be any combination of the following values:
-  *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
-  *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
-  *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
-  * @retval None
-  */
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
-  (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Get the selected ADC's flag status.
-  * @param __HANDLE__: ADC handle
-  * @param __FLAG__: ADC flag
-  *          This parameter can be any combination of the following values:
-  *            @arg ADC_FLAG_STRT: ADC Regular group start flag
-  *            @arg ADC_FLAG_JSTRT: ADC Injected group start flag
-  *            @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
-  *            @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
-  *            @arg ADC_FLAG_AWD: ADC Analog watchdog flag
-  * @retval None
-  */
-#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
-  ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-    
-/** @brief Clear the ADC's pending flags
-  * @param __HANDLE__: ADC handle
-  * @param __FLAG__: ADC flag
-  *          This parameter can be any combination of the following values:
-  *            @arg ADC_FLAG_STRT: ADC Regular group start flag
-  *            @arg ADC_FLAG_JSTRT: ADC Injected group start flag
-  *            @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
-  *            @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
-  *            @arg ADC_FLAG_AWD: ADC Analog watchdog flag
-  * @retval None
-  */
-#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                             \
-  (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
-
-/** @brief  Reset ADC handle state
-  * @param  __HANDLE__: ADC handle
-  * @retval None
-  */
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
-  ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-
-/**
-  * @}
-  */
-
-/* Private macro ------------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Macros ADC Private Macros
-  * @{
-  */
-/* Macro reserved for internal HAL driver usage, not intended to be used in   */
-/* code of final user.                                                        */
-
-/**
-  * @brief Verification of ADC state: enabled or disabled
-  * @param __HANDLE__: ADC handle
-  * @retval SET (ADC enabled) or RESET (ADC disabled)
-  */
-#define ADC_IS_ENABLE(__HANDLE__)                                              \
-  ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON )           \
-   ) ? SET : RESET)
-
-/**
-  * @brief Test if conversion trigger of regular group is software start
-  *        or external trigger.
-  * @param __HANDLE__: ADC handle
-  * @retval SET (software start) or RESET (external trigger)
-  */
-#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
-  (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
-
-/**
-  * @brief Test if conversion trigger of injected group is software start
-  *        or external trigger.
-  * @param __HANDLE__: ADC handle
-  * @retval SET (software start) or RESET (external trigger)
-  */
-#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
-  (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
-
-/**
-  * @brief Simultaneously clears and sets specific bits of the handle State
-  * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
-  *        the first parameter is the ADC handle State, the second parameter is the
-  *        bit field to clear, the third and last parameter is the bit field to set.
-  * @retval None
-  */
-#define ADC_STATE_CLR_SET MODIFY_REG
-
-/**
-  * @brief Clear ADC error code (set it to error code: "no error")
-  * @param __HANDLE__: ADC handle
-  * @retval None
-  */
-#define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
-  ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
-
-/**
-  * @brief Set ADC number of conversions into regular channel sequence length.
-  * @param _NbrOfConversion_: Regular channel sequence length 
-  * @retval None
-  */
-#define ADC_SQR1_L_SHIFT(_NbrOfConversion_)                                    \
-  (((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L))
-
-/**
-  * @brief Set the ADC's sample time for channel numbers between 10 and 18.
-  * @param _SAMPLETIME_: Sample time parameter.
-  * @param _CHANNELNB_: Channel number.  
-  * @retval None
-  */
-#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_)                                   \
-  ((_SAMPLETIME_) << (POSITION_VAL(ADC_SMPR1_SMP11) * ((_CHANNELNB_) - 10)))
-
-/**
-  * @brief Set the ADC's sample time for channel numbers between 0 and 9.
-  * @param _SAMPLETIME_: Sample time parameter.
-  * @param _CHANNELNB_: Channel number.  
-  * @retval None
-  */
-#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_)                                   \
-  ((_SAMPLETIME_) << (POSITION_VAL(ADC_SMPR2_SMP1) * (_CHANNELNB_)))
-
-/**
-  * @brief Set the selected regular channel rank for rank between 1 and 6.
-  * @param _CHANNELNB_: Channel number.
-  * @param _RANKNB_: Rank number.    
-  * @retval None
-  */
-#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_)                                     \
-  ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR3_SQ2) * ((_RANKNB_) - 1)))
-
-/**
-  * @brief Set the selected regular channel rank for rank between 7 and 12.
-  * @param _CHANNELNB_: Channel number.
-  * @param _RANKNB_: Rank number.    
-  * @retval None
-  */
-#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_)                                     \
-  ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR2_SQ8) * ((_RANKNB_) - 7)))
-
-/**
-  * @brief Set the selected regular channel rank for rank between 13 and 16.
-  * @param _CHANNELNB_: Channel number.
-  * @param _RANKNB_: Rank number.    
-  * @retval None
-  */
-#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_)                                     \
-  ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR1_SQ14) * ((_RANKNB_) - 13)))
-
-/**
-  * @brief Set the injected sequence length.
-  * @param _JSQR_JL_: Sequence length.
-  * @retval None
-  */
-#define ADC_JSQR_JL_SHIFT(_JSQR_JL_)                                           \
-  (((_JSQR_JL_) -1) << POSITION_VAL(ADC_JSQR_JL))
-
-/**
-  * @brief Set the selected injected channel rank
-  *        Note: on STM32F1 devices, channel rank position in JSQR register
-  *              is depending on total number of ranks selected into
-  *              injected sequencer (ranks sequence starting from 4-JL)
-  * @param _CHANNELNB_: Channel number.
-  * @param _RANKNB_: Rank number.
-  * @param _JSQR_JL_: Sequence length.
-  * @retval None
-  */
-#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_)                       \
-  ((_CHANNELNB_) << (POSITION_VAL(ADC_JSQR_JSQ2) * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
-
-/**
-  * @brief Enable ADC continuous conversion mode.
-  * @param _CONTINUOUS_MODE_: Continuous mode.
-  * @retval None
-  */
-#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_)                                  \
-  ((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT))
-
-/**
-  * @brief Configures the number of discontinuous conversions for the regular group channels.
-  * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
-  * @retval None
-  */
-#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_)                    \
-  (((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
-
-/**
-  * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
-  * @param _SCAN_MODE_: Scan conversion mode.
-  * @retval None
-  */
-/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter   */
-/*       is equivalent to ADC_SCAN_ENABLE.                                    */
-#define ADC_CR1_SCAN_SET(_SCAN_MODE_)                                          \
-  (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE)           \
-   )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE)                                   \
-  )
-
-/**
-  * @brief Get the maximum ADC conversion cycles on all channels.
-  * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
-  * Approximation of sampling time within 4 ranges, returns the highest value:
-  *   below 7.5 cycles {1.5 cycle; 7.5 cycles},
-  *   between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
-  *   between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
-  *   equal to 239.5 cycles
-  * Unit: ADC clock cycles
-  * @param __HANDLE__: ADC handle
-  * @retval ADC conversion cycles on all channels
-  */   
-#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)                                                                     \
-    (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET)  &&                     \
-       (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ?                     \
-                                                                                                                 \
-          (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET)  &&               \
-             (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ?               \
-               ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5)   \
-          :                                                                                                      \
-          ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET)  &&               \
-             (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) ||               \
-            ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET)  &&               \
-             (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ?               \
-               ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
-     )
-
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
-                                  ((ALIGN) == ADC_DATAALIGN_LEFT)    )
-
-#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
-                                     ((SCAN_MODE) == ADC_SCAN_ENABLE)    )
-
-#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)  || \
-                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)  )
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_1)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_2)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_3)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_4)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_5)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_6)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_7)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_8)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_9)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_10)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_11)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_12)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_13)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_14)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_15)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_16)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_17)            )
-
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5)    || \
-                                  ((TIME) == ADC_SAMPLETIME_7CYCLES_5)   || \
-                                  ((TIME) == ADC_SAMPLETIME_13CYCLES_5)  || \
-                                  ((TIME) == ADC_SAMPLETIME_28CYCLES_5)  || \
-                                  ((TIME) == ADC_SAMPLETIME_41CYCLES_5)  || \
-                                  ((TIME) == ADC_SAMPLETIME_55CYCLES_5)  || \
-                                  ((TIME) == ADC_SAMPLETIME_71CYCLES_5)  || \
-                                  ((TIME) == ADC_SAMPLETIME_239CYCLES_5)   )
-
-#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_10) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_11) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_12) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_13) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_14) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_15) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_16)   )
-
-#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)             || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       )
-
-#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP)         || \
-                                             ((CONVERSION) == ADC_INJECTED_GROUP)        || \
-                                             ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP)  )
-
-#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
-
-
-/** @defgroup ADC_range_verification ADC range verification
-  * For a unique ADC resolution: 12 bits
-  * @{
-  */
-#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= ((uint32_t)0x0FFF))
-/**
-  * @}
-  */
-
-/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification
-  * @{
-  */
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
-/**
-  * @}
-  */
-
-/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification
-  * @{
-  */
-#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
-/**
-  * @}
-  */
-      
-/**
-  * @}
-  */
-    
-/* Include ADC HAL Extension module */
-#include "stm32f1xx_hal_adc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup ADC_Exported_Functions_Group1
-  * @{
-  */
-
-
-/* Initialization and de-initialization functions  **********************************/
-HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
-void                    HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
-/**
-  * @}
-  */
-
-/* IO operation functions  *****************************************************/
-
-/** @addtogroup ADC_Exported_Functions_Group2
-  * @{
-  */
-
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
-
-/* Non-blocking mode: Interruption */
-HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
-
-/* Non-blocking mode: DMA */
-HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
-HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
-
-/* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
-
-/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
-void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
-/**
-  * @}
-  */
-
-
-/* Peripheral Control functions ***********************************************/
-/** @addtogroup ADC_Exported_Functions_Group3
-  * @{
-  */
-HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
-HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
-/**
-  * @}
-  */
-
-
-/* Peripheral State functions *************************************************/
-/** @addtogroup ADC_Exported_Functions_Group4
-  * @{
-  */
-uint32_t                HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
-uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-
-/* Internal HAL driver functions **********************************************/
-/** @addtogroup ADC_Private_Functions
-  * @{
-  */
-HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
-void              ADC_StabilizationTime(uint32_t DelayUs);
-void              ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
-void              ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
-void              ADC_DMAError(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */ 
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F1xx_HAL_ADC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_adc_ex.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,721 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_adc_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of ADC HAL extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_ADC_EX_H
-#define __STM32F1xx_HAL_ADC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"  
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup ADCEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup ADCEx_Exported_Types ADCEx Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  ADC Configuration injected Channel structure definition
-  * @note   Parameters of this structure are shared within 2 scopes:
-  *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
-  *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
-  *            AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
-  * @note   The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
-  *         ADC state can be either:
-  *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
-  *          - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
-  */
-typedef struct 
-{
-  uint32_t InjectedChannel;               /*!< Selection of ADC channel to configure
-                                               This parameter can be a value of @ref ADC_channels
-                                               Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
-                                               Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) 
-                                               Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
-                                                     It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
-                                                     Refer to errata sheet of these devices for more details. */
-  uint32_t InjectedRank;                  /*!< Rank in the injected group sequencer
-                                               This parameter must be a value of @ref ADCEx_injected_rank
-                                               Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
-  uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
-                                               Unit: ADC clock cycles
-                                               Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
-                                               This parameter can be a value of @ref ADC_sampling_times
-                                               Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
-                                                        If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
-                                               Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
-                                                     sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
-                                                     Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
-  uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
-                                               Offset value must be a positive number.
-                                               Depending of ADC resolution selected (12, 10, 8 or 6 bits),
-                                               this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
-  uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
-                                               To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
-                                               This parameter must be a number between Min_Data = 1 and Max_Data = 4.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
-                                               Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
-                                               Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
-                                               This parameter can be set to ENABLE or DISABLE.
-                                               Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t AutoInjectedConv;              /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
-                                               This parameter can be set to ENABLE or DISABLE.      
-                                               Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
-                                               Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
-                                               Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
-                                                     To maintain JAUTO always enabled, DMA must be configured in circular mode.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.
-                                               If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
-                                               If set to external trigger source, triggering is on event rising edge.
-                                               This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
-                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
-                                                     If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-}ADC_InjectionConfTypeDef;
-
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-/** 
-  * @brief  Structure definition of ADC multimode
-  * @note   The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
-  *         State of ADCs of the common group must be: disabled.
-  */
-typedef struct
-{
-  uint32_t Mode;              /*!< Configures the ADC to operate in independent or multi mode. 
-                                   This parameter can be a value of @ref ADCEx_Common_mode
-                                   Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change.
-                                   Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1 and ADC2.
-                                   Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC clock cycles for slow interleaved mode.
-                                   Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration structure can have additional parameters).
-                                         The equivalences are:
-                                           - Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'.
-                                           - Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */
-
-  
-}ADC_MultiModeTypeDef;                                                          
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-/**
-  * @}
-  */
-
-
-/* Exported constants --------------------------------------------------------*/
-   
-/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
-  * @{
-  */
-
-/** @defgroup ADCEx_injected_rank ADCEx rank into injected group
-  * @{
-  */
-#define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001)
-#define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002)
-#define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003)
-#define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004)
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group
-  * @{
-  */
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           ((uint32_t)0x00000000)
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         ((uint32_t)ADC_CR2_JEXTTRIG)
-/**
-  * @}
-  */
-    
-/** @defgroup ADC_External_trigger_source_Regular ADC External trigger selection for regular group
-  * @{
-  */
-/*!< List of external triggers with generic trigger name, independently of    */
-/* ADC target, sorted by trigger name:                                        */
-
-/*!< External triggers of regular group for ADC1&ADC2 only */
-#define ADC_EXTERNALTRIGCONV_T1_CC1         ADC1_2_EXTERNALTRIG_T1_CC1
-#define ADC_EXTERNALTRIGCONV_T1_CC2         ADC1_2_EXTERNALTRIG_T1_CC2
-#define ADC_EXTERNALTRIGCONV_T2_CC2         ADC1_2_EXTERNALTRIG_T2_CC2
-#define ADC_EXTERNALTRIGCONV_T3_TRGO        ADC1_2_EXTERNALTRIG_T3_TRGO
-#define ADC_EXTERNALTRIGCONV_T4_CC4         ADC1_2_EXTERNALTRIG_T4_CC4
-#define ADC_EXTERNALTRIGCONV_EXT_IT11       ADC1_2_EXTERNALTRIG_EXT_IT11
-
-#if defined (STM32F103xE) || defined (STM32F103xG)
-/*!< External triggers of regular group for ADC3 only */
-#define ADC_EXTERNALTRIGCONV_T2_CC3         ADC3_EXTERNALTRIG_T2_CC3
-#define ADC_EXTERNALTRIGCONV_T3_CC1         ADC3_EXTERNALTRIG_T3_CC1
-#define ADC_EXTERNALTRIGCONV_T5_CC1         ADC3_EXTERNALTRIG_T5_CC1
-#define ADC_EXTERNALTRIGCONV_T5_CC3         ADC3_EXTERNALTRIG_T5_CC3
-#define ADC_EXTERNALTRIGCONV_T8_CC1         ADC3_EXTERNALTRIG_T8_CC1
-#endif /* STM32F103xE || defined STM32F103xG */
-
-/*!< External triggers of regular group for all ADC instances */
-#define ADC_EXTERNALTRIGCONV_T1_CC3         ADC1_2_3_EXTERNALTRIG_T1_CC3
-
-#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
-/*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and   */
-/*         XL-density devices.                                                */
-/*         To use it on ADC or ADC2, a remap of trigger must be done from     */
-/*         EXTI line 11 to TIM8_TRGO with macro:                              */
-/*           __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE()                           */
-/*           __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE()                           */
-
-/* Note for internal constant value management: If TIM8_TRGO is available,    */
-/* its definition is set to value for ADC1&ADC2 by default and changed to     */
-/* value for ADC3 by HAL ADC driver if ADC3 is selected.                      */
-#define ADC_EXTERNALTRIGCONV_T8_TRGO        ADC1_2_EXTERNALTRIG_T8_TRGO
-#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#define ADC_SOFTWARE_START                  ADC1_2_3_SWSTART
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger selection for injected group
-  * @{
-  */
-/*!< List of external triggers with generic trigger name, independently of    */
-/* ADC target, sorted by trigger name:                                        */
-
-/*!< External triggers of injected group for ADC1&ADC2 only */
-#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO        ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T2_CC1         ADC1_2_EXTERNALTRIGINJEC_T2_CC1
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC4         ADC1_2_EXTERNALTRIGINJEC_T3_CC4
-#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO        ADC1_2_EXTERNALTRIGINJEC_T4_TRGO 
-#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15       ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
-
-#if defined (STM32F103xE) || defined (STM32F103xG)
-/*!< External triggers of injected group for ADC3 only */
-#define ADC_EXTERNALTRIGINJECCONV_T4_CC3         ADC3_EXTERNALTRIGINJEC_T4_CC3
-#define ADC_EXTERNALTRIGINJECCONV_T8_CC2         ADC3_EXTERNALTRIGINJEC_T8_CC2
-#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO        ADC3_EXTERNALTRIGINJEC_T5_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T5_CC4         ADC3_EXTERNALTRIGINJEC_T5_CC4
-#endif /* STM32F103xE || defined STM32F103xG */
-
-/*!< External triggers of injected group for all ADC instances */
-#define ADC_EXTERNALTRIGINJECCONV_T1_CC4         ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4
-#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO        ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO
-
-#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
-/*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and    */
-/*         XL-density devices.                                                */
-/*         To use it on ADC1 or ADC2, a remap of trigger must be done from    */
-/*         EXTI line 11 to TIM8_CC4 with macro:                               */
-/*           __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE()                           */
-/*           __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE()                           */
-
-/* Note for internal constant value management: If TIM8_CC4 is available,     */
-/* its definition is set to value for ADC1&ADC2 by default and changed to     */
-/* value for ADC3 by HAL ADC driver if ADC3 is selected.                      */
-#define ADC_EXTERNALTRIGINJECCONV_T8_CC4         ADC1_2_EXTERNALTRIGINJEC_T8_CC4
-#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#define ADC_INJECTED_SOFTWARE_START              ADC1_2_3_JSWSTART
-/**
-  * @}
-  */
-
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
-  * @{
-  */
-#define ADC_MODE_INDEPENDENT                  ((uint32_t)(0x00000000)) /*!< ADC dual mode disabled (ADC independent mode) */
-#define ADC_DUALMODE_REGSIMULT_INJECSIMULT    ((uint32_t)(                                                            ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */
-#define ADC_DUALMODE_REGSIMULT_ALTERTRIG      ((uint32_t)(                                        ADC_CR1_DUALMOD_1                    )) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */
-#define ADC_DUALMODE_INJECSIMULT_INTERLFAST   ((uint32_t)(                                        ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
-#define ADC_DUALMODE_INJECSIMULT_INTERLSLOW   ((uint32_t)(                    ADC_CR1_DUALMOD_2                                        )) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
-#define ADC_DUALMODE_INJECSIMULT              ((uint32_t)(                    ADC_CR1_DUALMOD_2 |                     ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */
-#define ADC_DUALMODE_REGSIMULT                ((uint32_t)(                    ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1                    )) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */
-#define ADC_DUALMODE_INTERLFAST               ((uint32_t)(                    ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
-#define ADC_DUALMODE_INTERLSLOW               ((uint32_t)(ADC_CR1_DUALMOD_3                                                            )) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
-#define ADC_DUALMODE_ALTERTRIG                ((uint32_t)(ADC_CR1_DUALMOD_3 |                                         ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */
-/**
-  * @}
-  */
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-/**
-  * @}
-  */
-
-
-/* Private constants ---------------------------------------------------------*/
-
-/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
-  * @{
-  */
-
-/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
-  * @{
-  */
-/* List of external triggers of regular group for ADC1, ADC2, ADC3 (if ADC    */
-/* instance is available on the selected device).                             */
-/* (used internally by HAL driver. To not use into HAL structure parameters)  */
-
-/* External triggers of regular group for ADC1&ADC2 (if ADCx available) */
-#define ADC1_2_EXTERNALTRIG_T1_CC1           ((uint32_t) 0x00000000)
-#define ADC1_2_EXTERNALTRIG_T1_CC2           ((uint32_t)(                                      ADC_CR2_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T2_CC2           ((uint32_t)(                   ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T3_TRGO          ((uint32_t)(ADC_CR2_EXTSEL_2                                      ))
-#define ADC1_2_EXTERNALTRIG_T4_CC4           ((uint32_t)(ADC_CR2_EXTSEL_2 |                    ADC_CR2_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_EXT_IT11         ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1                   ))
-#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
-/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and     */
-/* XL-density devices.                                                        */
-#define ADC1_2_EXTERNALTRIG_T8_TRGO          ADC1_2_EXTERNALTRIG_EXT_IT11
-#endif
-
-#if defined (STM32F103xE) || defined (STM32F103xG)
-/* External triggers of regular group for ADC3 */
-#define ADC3_EXTERNALTRIG_T3_CC1             ADC1_2_EXTERNALTRIG_T1_CC1
-#define ADC3_EXTERNALTRIG_T2_CC3             ADC1_2_EXTERNALTRIG_T1_CC2
-#define ADC3_EXTERNALTRIG_T8_CC1             ADC1_2_EXTERNALTRIG_T2_CC2
-#define ADC3_EXTERNALTRIG_T8_TRGO            ADC1_2_EXTERNALTRIG_T3_TRGO
-#define ADC3_EXTERNALTRIG_T5_CC1             ADC1_2_EXTERNALTRIG_T4_CC4
-#define ADC3_EXTERNALTRIG_T5_CC3             ADC1_2_EXTERNALTRIG_EXT_IT11
-#endif
-
-/* External triggers of regular group for ADC1&ADC2&ADC3 (if ADCx available) */
-#define ADC1_2_3_EXTERNALTRIG_T1_CC3         ((uint32_t)(                   ADC_CR2_EXTSEL_1                   ))
-#define ADC1_2_3_SWSTART                     ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
-  * @{
-  */
-/* List of external triggers of injected group for ADC1, ADC2, ADC3 (if ADC    */
-/* instance is available on the selected device).                             */
-/* (used internally by HAL driver. To not use into HAL structure parameters)  */
-
-/* External triggers of injected group for ADC1&ADC2 (if ADCx available) */
-#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO          ((uint32_t)(                    ADC_CR2_JEXTSEL_1                    ))
-#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1           ((uint32_t)(                    ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4           ((uint32_t)(ADC_CR2_JEXTSEL_2                                        ))
-#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO          ((uint32_t)(ADC_CR2_JEXTSEL_2 |                     ADC_CR2_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15         ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1                    ))
-#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
-/* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and      */
-/* XL-density devices.                                                        */
-#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4           ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
-#endif
-
-#if defined (STM32F103xE) || defined (STM32F103xG)
-/* External triggers of injected group for ADC3 */
-#define ADC3_EXTERNALTRIGINJEC_T4_CC3             ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
-#define ADC3_EXTERNALTRIGINJEC_T8_CC2             ADC1_2_EXTERNALTRIGINJEC_T2_CC1
-#define ADC3_EXTERNALTRIGINJEC_T8_CC4             ADC1_2_EXTERNALTRIGINJEC_T3_CC4
-#define ADC3_EXTERNALTRIGINJEC_T5_TRGO            ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
-#define ADC3_EXTERNALTRIGINJEC_T5_CC4             ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
-#endif /* STM32F103xE || defined STM32F103xG */
-
-/* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */
-#define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO        ((uint32_t) 0x00000000)
-#define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4         ((uint32_t)(                                        ADC_CR2_JEXTSEL_0))
-#define ADC1_2_3_JSWSTART                         ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup ADCEx_Private_Macro ADCEx Private Macro
-  * @{
-  */
-/* Macro reserved for internal HAL driver usage, not intended to be used in   */
-/* code of final user.                                                        */
-
-    
-/**
-  * @brief For devices with 3 ADCs: Defines the external trigger source 
-  *        for regular group according to ADC into common group ADC1&ADC2 or 
-  *        ADC3 (some triggers with same source have different value to
-  *        be programmed into ADC EXTSEL bits of CR2 register).
-  *        For devices with 2 ADCs or less: this macro makes no change.
-  * @param __HANDLE__: ADC handle
-  * @param __EXT_TRIG_CONV__: External trigger selected for regular group.
-  * @retval External trigger to be programmed into EXTSEL bits of CR2 register
-  */
-#if defined (STM32F103xE) || defined (STM32F103xG)
-#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__)                         \
- (( (((__HANDLE__)->Instance) == ADC3)                                         \
-  )?                                                                           \
-   ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO                     \
-     )?                                                                        \
-      (ADC3_EXTERNALTRIG_T8_TRGO)                                              \
-      :                                                                        \
-      (__EXT_TRIG_CONV__)                                                      \
-   )                                                                           \
-   :                                                                           \
-   (__EXT_TRIG_CONV__)                                                         \
- )
-#else
-#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__)                         \
-  (__EXT_TRIG_CONV__)
-#endif /* STM32F103xE || STM32F103xG */
-
-/**
-  * @brief For devices with 3 ADCs: Defines the external trigger source 
-  *        for injected group according to ADC into common group ADC1&ADC2 or 
-  *        ADC3 (some triggers with same source have different value to
-  *        be programmed into ADC JEXTSEL bits of CR2 register).
-  *        For devices with 2 ADCs or less: this macro makes no change.
-  * @param __HANDLE__: ADC handle
-  * @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group.
-  * @retval External trigger to be programmed into JEXTSEL bits of CR2 register
-  */
-#if defined (STM32F103xE) || defined (STM32F103xG)
-#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__)                  \
- (( (((__HANDLE__)->Instance) == ADC3)                                         \
-  )?                                                                           \
-   ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4           \
-     )?                                                                        \
-      (ADC3_EXTERNALTRIGINJEC_T8_CC4)                                          \
-      :                                                                        \
-      (__EXT_TRIG_INJECTCONV__)                                                \
-   )                                                                           \
-   :                                                                           \
-   (__EXT_TRIG_INJECTCONV__)                                                   \
- )
-#else
-#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__)                  \
-   (__EXT_TRIG_INJECTCONV__)
-#endif /* STM32F103xE || STM32F103xG */
-
-
-/**
-  * @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs)
-  * @param __HANDLE__: ADC handle
-  * @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled
-  */
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__)                                    \
- (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)   \
-  )?                                                                           \
-   (ADC1->CR1 & ADC_CR1_DUALMOD)                                               \
-   :                                                                           \
-   (RESET)                                                                     \
- )
-#else
-#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__)                                    \
-  (RESET)
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-/**
-  * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
-  * @param __HANDLE__: ADC handle
-  * @retval None
-  */
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)                        \
-  (( (((__HANDLE__)->Instance) == ADC2)                                        \
-   )?                                                                          \
-    ((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET)                                   \
-    :                                                                          \
-    (!RESET)                                                                   \
-  )
-#else
-#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)                        \
-  (!RESET)
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-/**
-  * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)
-  * @param __HANDLE__: ADC handle
-  * @retval None
-  */
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__)                                \
-  (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)  \
-   )?                                                                          \
-    (ADC1->CR1 & ADC_CR1_JAUTO)                                                \
-    :                                                                          \
-    (RESET)                                                                    \
-  )
-#else
-#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__)                                \
-  (RESET)
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-/**
-  * @brief Set handle of the other ADC sharing the common multimode settings
-  * @param __HANDLE__: ADC handle
-  * @param __HANDLE_OTHER_ADC__: other ADC handle
-  * @retval None
-  */
-#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__)                 \
-  ((__HANDLE_OTHER_ADC__)->Instance = ADC2)
-
-/**
-  * @brief Set handle of the ADC slave associated to the ADC master
-  * On STM32F1 devices, ADC slave is always ADC2 (this can be different
-  * on other STM32 devices)
-  * @param __HANDLE_MASTER__: ADC master handle
-  * @param __HANDLE_SLAVE__: ADC slave handle
-  * @retval None
-  */
-#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)                   \
-  ((__HANDLE_SLAVE__)->Instance = ADC2)
-       
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
-                                       ((CHANNEL) == ADC_INJECTED_RANK_2) || \
-                                       ((CHANNEL) == ADC_INJECTED_RANK_3) || \
-                                       ((CHANNEL) == ADC_INJECTED_RANK_4)   )
-
-#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)  || \
-                                        ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)  )
-
-/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
-  * @{
-  */
-#define IS_ADC_INJECTED_NB_CONV(LENGTH)                                        \
-  (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
-/**
-  * @}
-  */
-
-#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC)
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11)  || \
-                                                                                  \
-                                 ((REGTRIG) == ADC_SOFTWARE_START)               )
-#endif
-#if defined (STM32F101xE) || defined (STM32F101xG)
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11)  || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO)   || \
-                                                                                  \
-                                 ((REGTRIG) == ADC_SOFTWARE_START)               )
-#endif
-#if defined (STM32F103xE) || defined (STM32F103xG)
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11)  || \
-                                                                                  \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3)    || \
-                                                                                  \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO)   || \
-                                 ((REGTRIG) == ADC_SOFTWARE_START)               )
-#endif
-
-#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC)
-#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
-                                                                                           \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
-                                                                                           \
-                                      ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)          )
-#endif
-#if defined (STM32F101xE) || defined (STM32F101xG)
-#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
-                                                                                           \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)   || \
-                                                                                           \
-                                      ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)          )
-#endif
-#if defined (STM32F103xE) || defined (STM32F103xG)
-#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
-                                                                                           \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4)   || \
-                                                                                           \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)   || \
-                                                                                           \
-                                      ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)          )
-#endif
-
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT)                || \
-                           ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT)  || \
-                           ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)    || \
-                           ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) || \
-                           ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || \
-                           ((MODE) == ADC_DUALMODE_INJECSIMULT)            || \
-                           ((MODE) == ADC_DUALMODE_REGSIMULT)              || \
-                           ((MODE) == ADC_DUALMODE_INTERLFAST)             || \
-                           ((MODE) == ADC_DUALMODE_INTERLSLOW)             || \
-                           ((MODE) == ADC_DUALMODE_ALTERTRIG)                )
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-/**
-  * @}
-  */      
-   
-    
-
-    
-    
-   
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADCEx_Exported_Functions
-  * @{
-  */
-
-/* IO operation functions  *****************************************************/
-/** @addtogroup ADCEx_Exported_Functions_Group1
-  * @{
-  */
-
-/* ADC calibration */
-HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc);
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-
-/* Non-blocking mode: Interruption */
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
-
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-/* ADC multimode */
-HAL_StatusTypeDef       HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
-HAL_StatusTypeDef       HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); 
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-/* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t                HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-uint32_t                HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
-void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
-/**
-  * @}
-  */
-
-
-/* Peripheral Control functions ***********************************************/
-/** @addtogroup ADCEx_Exported_Functions_Group2
-  * @{
-  */
-HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_ADC_EX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_can.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,825 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_can.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of CAN HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __stm32f1xx_CAN_H
-#define __stm32f1xx_CAN_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-      
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
-    defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CAN
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CAN_Exported_Types CAN Exported Types
-  * @{
-  */  
-/** 
-  * @brief  HAL State structures definition  
-  */ 
-typedef enum
-{
-  HAL_CAN_STATE_RESET             = 0x00,  /*!< CAN not yet initialized or disabled */
-  HAL_CAN_STATE_READY             = 0x01,  /*!< CAN initialized and ready for use   */  
-  HAL_CAN_STATE_BUSY              = 0x02,  /*!< CAN process is ongoing              */     
-  HAL_CAN_STATE_BUSY_TX           = 0x12,  /*!< CAN process is ongoing              */   
-  HAL_CAN_STATE_BUSY_RX           = 0x22,  /*!< CAN process is ongoing              */ 
-  HAL_CAN_STATE_BUSY_TX_RX        = 0x32,  /*!< CAN process is ongoing              */
-  HAL_CAN_STATE_TIMEOUT           = 0x03,  /*!< CAN in Timeout state                */
-  HAL_CAN_STATE_ERROR             = 0x04   /*!< CAN error state                     */  
-
-}HAL_CAN_StateTypeDef;
-
-
-/** 
-  * @brief  CAN init structure definition
-  */
-typedef struct
-{
-  uint32_t Prescaler;  /*!< Specifies the length of a time quantum. 
-                            This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
-  
-  uint32_t Mode;       /*!< Specifies the CAN operating mode.
-                            This parameter can be a value of @ref CAN_operating_mode */
-
-  uint32_t SJW;        /*!< Specifies the maximum number of time quanta 
-                            the CAN hardware is allowed to lengthen or 
-                            shorten a bit to perform resynchronization.
-                            This parameter can be a value of @ref CAN_synchronisation_jump_width */
-
-  uint32_t BS1;        /*!< Specifies the number of time quanta in Bit Segment 1.
-                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
-
-  uint32_t BS2;        /*!< Specifies the number of time quanta in Bit Segment 2.
-                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-  
-  uint32_t TTCM;       /*!< Enable or disable the time triggered communication mode.
-                            This parameter can be set to ENABLE or DISABLE. */
-  
-  uint32_t ABOM;       /*!< Enable or disable the automatic bus-off management.
-                            This parameter can be set to ENABLE or DISABLE. */
-
-  uint32_t AWUM;       /*!< Enable or disable the automatic wake-up mode. 
-                            This parameter can be set to ENABLE or DISABLE. */
-
-  uint32_t NART;       /*!< Enable or disable the non-automatic retransmission mode.
-                            This parameter can be set to ENABLE or DISABLE. */
-
-  uint32_t RFLM;       /*!< Enable or disable the Receive FIFO Locked mode.
-                            This parameter can be set to ENABLE or DISABLE. */
-
-  uint32_t TXFP;       /*!< Enable or disable the transmit FIFO priority.
-                            This parameter can be set to ENABLE or DISABLE. */
-}CAN_InitTypeDef;
-
-/** 
-  * @brief  CAN Tx message structure definition  
-  */
-typedef struct
-{
-  uint32_t StdId;    /*!< Specifies the standard identifier.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ 
-                        
-  uint32_t ExtId;    /*!< Specifies the extended identifier.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ 
-                        
-  uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
-                          This parameter can be a value of @ref CAN_identifier_type */
-
-  uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
-                          This parameter can be a value of @ref CAN_remote_transmission_request */
-
-  uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
-
-  uint8_t Data[8];   /*!< Contains the data to be transmitted. 
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
-   
-}CanTxMsgTypeDef;
-
-/** 
-  * @brief  CAN Rx message structure definition  
-  */
-typedef struct
-{
-  uint32_t StdId;       /*!< Specifies the standard identifier.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ 
-
-  uint32_t ExtId;       /*!< Specifies the extended identifier.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ 
-
-  uint32_t IDE;         /*!< Specifies the type of identifier for the message that will be received.
-                             This parameter can be a value of @ref CAN_identifier_type */
-
-  uint32_t RTR;         /*!< Specifies the type of frame for the received message.
-                             This parameter can be a value of @ref CAN_remote_transmission_request */
-
-  uint32_t DLC;         /*!< Specifies the length of the frame that will be received.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
-
-  uint8_t Data[8];      /*!< Contains the data to be received. 
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
-
-  uint32_t FMI;         /*!< Specifies the index of the filter the message stored in the mailbox passes through.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
-
-  uint32_t FIFONumber;  /*!< Specifies the receive FIFO number. 
-                             This parameter can be a value of @ref CAN_receive_FIFO_number_constants */
-
-}CanRxMsgTypeDef;
-
-/** 
-  * @brief  CAN handle Structure definition  
-  */ 
-typedef struct
-{
-  CAN_TypeDef                 *Instance;  /*!< Register base address          */
-  
-  CAN_InitTypeDef             Init;       /*!< CAN required parameters        */
-  
-  CanTxMsgTypeDef*            pTxMsg;     /*!< Pointer to transmit structure  */
-
-  CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure */
-  
-  HAL_LockTypeDef             Lock;       /*!< CAN locking object             */
-  
-  __IO HAL_CAN_StateTypeDef   State;      /*!< CAN communication state        */
-  
-  __IO uint32_t               ErrorCode;  /*!< CAN Error code                 */
-  
-}CAN_HandleTypeDef;
-/**
-  * @}
-  */
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CAN_Exported_Constants CAN Exported Constants
-  * @{
-  */
-
-/** @defgroup CAN_Error_Code CAN Error Code
-  * @{
-  */
-
-
-#define HAL_CAN_ERROR_NONE              ((uint32_t)0x00)   /*!< No error             */
-#define HAL_CAN_ERROR_EWG               ((uint32_t)0x01)   /*!< EWG error            */   
-#define HAL_CAN_ERROR_EPV               ((uint32_t)0x02)   /*!< EPV error            */
-#define HAL_CAN_ERROR_BOF               ((uint32_t)0x04)   /*!< BOF error            */
-#define HAL_CAN_ERROR_STF               ((uint32_t)0x08)   /*!< Stuff error          */
-#define HAL_CAN_ERROR_FOR               ((uint32_t)0x10)   /*!< Form error           */
-#define HAL_CAN_ERROR_ACK               ((uint32_t)0x20)   /*!< Acknowledgment error */
-#define HAL_CAN_ERROR_BR                ((uint32_t)0x40)   /*!< Bit recessive        */
-#define HAL_CAN_ERROR_BD                ((uint32_t)0x80)   /*!< LEC dominant         */
-#define HAL_CAN_ERROR_CRC               ((uint32_t)0x100)  /*!< LEC transfer error   */
-
-
-/**
-  * @}
-  */
-
-
-/** @defgroup CAN_InitStatus CAN initialization Status
-  * @{
-  */
-#define CAN_INITSTATUS_FAILED       ((uint32_t)0x00000000)  /*!< CAN initialization failed */
-#define CAN_INITSTATUS_SUCCESS      ((uint32_t)0x00000001)  /*!< CAN initialization OK */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_operating_mode CAN Operating Mode
-  * @{
-  */
-#define CAN_MODE_NORMAL             ((uint32_t)0x00000000)                     /*!< Normal mode   */
-#define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */
-#define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */
-#define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
-  * @{
-  */
-#define CAN_SJW_1TQ                 ((uint32_t)0x00000000)     /*!< 1 time quantum */
-#define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */
-#define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */
-#define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
-  * @{
-  */
-#define CAN_BS1_1TQ                 ((uint32_t)0x00000000)                                       /*!< 1 time quantum  */
-#define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */
-#define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */
-#define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */
-#define CAN_BS1_5TQ                 ((uint32_t)CAN_BTR_TS1_2)                                    /*!< 5 time quantum  */
-#define CAN_BS1_6TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))                  /*!< 6 time quantum  */
-#define CAN_BS1_7TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))                  /*!< 7 time quantum  */
-#define CAN_BS1_8TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 8 time quantum  */
-#define CAN_BS1_9TQ                 ((uint32_t)CAN_BTR_TS1_3)                                    /*!< 9 time quantum  */
-#define CAN_BS1_10TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))                  /*!< 10 time quantum */
-#define CAN_BS1_11TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))                  /*!< 11 time quantum */
-#define CAN_BS1_12TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 12 time quantum */
-#define CAN_BS1_13TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))                  /*!< 13 time quantum */
-#define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */
-#define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */
-#define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
-  * @{
-  */
-#define CAN_BS2_1TQ                 ((uint32_t)0x00000000)                       /*!< 1 time quantum */
-#define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */
-#define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */
-#define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */
-#define CAN_BS2_5TQ                 ((uint32_t)CAN_BTR_TS2_2)                    /*!< 5 time quantum */
-#define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */
-#define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */
-#define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_mode CAN Filter Mode
-  * @{
-  */
-#define CAN_FILTERMODE_IDMASK       ((uint8_t)0x00)  /*!< Identifier mask mode */
-#define CAN_FILTERMODE_IDLIST       ((uint8_t)0x01)  /*!< Identifier list mode */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_scale CAN Filter Scale
-  * @{
-  */
-#define CAN_FILTERSCALE_16BIT       ((uint8_t)0x00)  /*!< Two 16-bit filters */
-#define CAN_FILTERSCALE_32BIT       ((uint8_t)0x01)  /*!< One 32-bit filter  */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_FIFO CAN Filter FIFO
-  * @{
-  */
-#define CAN_FILTER_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_FILTER_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
-
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_identifier_type CAN Identifier Type
-  * @{
-  */
-#define CAN_ID_STD             ((uint32_t)0x00000000)  /*!< Standard Id */
-#define CAN_ID_EXT             ((uint32_t)0x00000004)  /*!< Extended Id */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
-  * @{
-  */
-#define CAN_RTR_DATA                ((uint32_t)0x00000000)  /*!< Data frame */
-#define CAN_RTR_REMOTE              ((uint32_t)0x00000002)  /*!< Remote frame */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_transmit_constants CAN Transmit Constants
-  * @{
-  */
-#define CAN_TXSTATUS_NOMAILBOX      ((uint8_t)0x04)  /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
-  * @{
-  */
-#define CAN_FIFO0                   ((uint8_t)0x00)  /*!< CAN FIFO 0 used to receive */
-#define CAN_FIFO1                   ((uint8_t)0x01)  /*!< CAN FIFO 1 used to receive */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_flags CAN Flags
-  * @{
-  */
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
-   and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with 
-   CAN_GetFlagStatus() function.  */
-
-/* Transmit Flags */
-#define CAN_FLAG_RQCP0             ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION))  /*!< Request MailBox0 flag         */
-#define CAN_FLAG_RQCP1             ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP1_BIT_POSITION))  /*!< Request MailBox1 flag         */
-#define CAN_FLAG_RQCP2             ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP2_BIT_POSITION))  /*!< Request MailBox2 flag         */
-#define CAN_FLAG_TXOK0             ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK0_BIT_POSITION))  /*!< Transmission OK MailBox0 flag */
-#define CAN_FLAG_TXOK1             ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK1_BIT_POSITION))  /*!< Transmission OK MailBox1 flag */
-#define CAN_FLAG_TXOK2             ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION))  /*!< Transmission OK MailBox2 flag */
-#define CAN_FLAG_TME0              ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME0_BIT_POSITION))   /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME1              ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME1_BIT_POSITION))   /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME2              ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME2_BIT_POSITION))   /*!< Transmit mailbox 0 empty flag */
-
-/* Receive Flags */
-#define CAN_FLAG_FF0               ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FF0_BIT_POSITION))  /*!< FIFO 0 Full flag    */
-#define CAN_FLAG_FOV0              ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FOV0_BIT_POSITION)) /*!< FIFO 0 Overrun flag */
-
-#define CAN_FLAG_FF1               ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FF1_BIT_POSITION))  /*!< FIFO 1 Full flag    */
-#define CAN_FLAG_FOV1              ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FOV1_BIT_POSITION)) /*!< FIFO 1 Overrun flag */
-
-/* Operating Mode Flags */
-#define CAN_FLAG_WKU               ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_WKU_BIT_POSITION))    /*!< Wake up flag           */
-#define CAN_FLAG_SLAK              ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAK_BIT_POSITION))   /*!< Sleep acknowledge flag */
-#define CAN_FLAG_SLAKI             ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAKI_BIT_POSITION))  /*!< Sleep acknowledge flag */
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. 
-         In this case the SLAK bit can be polled.*/
-
-/* Error Flags */
-#define CAN_FLAG_EWG               ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EWG_BIT_POSITION))    /*!< Error warning flag   */
-#define CAN_FLAG_EPV               ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EPV_BIT_POSITION))    /*!< Error passive flag   */
-#define CAN_FLAG_BOF               ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_BOF_BIT_POSITION))    /*!< Bus-Off flag         */
-
-/**
-  * @}
-  */
-
-  
-/** @defgroup CAN_interrupts CAN Interrupts
-  * @{
-  */ 
-#define CAN_IT_TME                  ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
-
-/* Receive Interrupts */
-#define CAN_IT_FMP0                 ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */
-#define CAN_IT_FF0                  ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */
-#define CAN_IT_FOV0                 ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */
-#define CAN_IT_FMP1                 ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */
-#define CAN_IT_FF1                  ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */
-#define CAN_IT_FOV1                 ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */
-
-/* Operating Mode Interrupts */
-#define CAN_IT_WKU                  ((uint32_t)CAN_IER_WKUIE)  /*!< Wake-up interrupt           */
-#define CAN_IT_SLK                  ((uint32_t)CAN_IER_SLKIE)  /*!< Sleep acknowledge interrupt */
-
-/* Error Interrupts */
-#define CAN_IT_EWG                  ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt   */
-#define CAN_IT_EPV                  ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt   */
-#define CAN_IT_BOF                  ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt         */
-#define CAN_IT_LEC                  ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
-#define CAN_IT_ERR                  ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt           */
-
-
-/**
-  * @}
-  */
-
-
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Private_Constants CAN Private Constants
-  * @{
-  */
-
-/* CAN intermediate shift values used for CAN flags */
-#define TSR_REGISTER_INDEX      ((uint32_t)0x5)
-#define RF0R_REGISTER_INDEX     ((uint32_t)0x2)
-#define RF1R_REGISTER_INDEX     ((uint32_t)0x4)
-#define MSR_REGISTER_INDEX      ((uint32_t)0x1)
-#define ESR_REGISTER_INDEX      ((uint32_t)0x3)
-
-/* CAN flags bits position into their respective register (TSR, RF0R, RF1R or MSR regsiters) */
-/* Transmit Flags */
-#define CAN_TSR_RQCP0_BIT_POSITION     ((uint32_t)0x00000000)
-#define CAN_TSR_RQCP1_BIT_POSITION     ((uint32_t)0x00000008)
-#define CAN_TSR_RQCP2_BIT_POSITION     ((uint32_t)0x00000010)
-#define CAN_TSR_TXOK0_BIT_POSITION     ((uint32_t)0x00000001)
-#define CAN_TSR_TXOK1_BIT_POSITION     ((uint32_t)0x00000009)
-#define CAN_TSR_TXOK2_BIT_POSITION     ((uint32_t)0x00000011)
-#define CAN_TSR_TME0_BIT_POSITION      ((uint32_t)0x0000001A)
-#define CAN_TSR_TME1_BIT_POSITION      ((uint32_t)0x0000001B)
-#define CAN_TSR_TME2_BIT_POSITION      ((uint32_t)0x0000001C)
-
-/* Receive Flags */
-#define CAN_RF0R_FF0_BIT_POSITION       ((uint32_t)0x00000003)
-#define CAN_RF0R_FOV0_BIT_POSITION      ((uint32_t)0x00000004)
-
-#define CAN_RF1R_FF1_BIT_POSITION       ((uint32_t)0x00000003)
-#define CAN_RF1R_FOV1_BIT_POSITION      ((uint32_t)0x00000004)
-
-/* Operating Mode Flags */
-#define CAN_MSR_WKU_BIT_POSITION       ((uint32_t)0x00000003)
-#define CAN_MSR_SLAK_BIT_POSITION      ((uint32_t)0x00000001)
-#define CAN_MSR_SLAKI_BIT_POSITION     ((uint32_t)0x00000004)
-
-/* Error Flags */
-#define CAN_ESR_EWG_BIT_POSITION       ((uint32_t)0x00000000)
-#define CAN_ESR_EPV_BIT_POSITION       ((uint32_t)0x00000001)
-#define CAN_ESR_BOF_BIT_POSITION       ((uint32_t)0x00000002)
-
-/* Mask used by macro to get/clear CAN flags*/
-#define CAN_FLAG_MASK     ((uint32_t)0x000000FF)
-
-/* Mailboxes definition */
-#define CAN_TXMAILBOX_0   ((uint8_t)0x00)
-#define CAN_TXMAILBOX_1   ((uint8_t)0x01)
-#define CAN_TXMAILBOX_2   ((uint8_t)0x02)
-
-
-/**
-  * @}
-  */
-
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CAN_Exported_Macro CAN Exported Macros
-  * @{
-  */
-
-/** @brief  Reset CAN handle state
-  * @param  __HANDLE__: CAN handle.
-  * @retval None
-  */
-#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
-
-/**
-  * @brief  Enable the specified CAN interrupts
-  * @param  __HANDLE__: CAN handle.
-  * @param  __INTERRUPT__: CAN Interrupt.
-  *         This parameter can be one of the following values:
-  *            @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
-  *            @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
-  *            @arg CAN_IT_FF0 : FIFO 0 full interrupt
-  *            @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
-  *            @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
-  *            @arg CAN_IT_FF1 : FIFO 1 full interrupt
-  *            @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
-  *            @arg CAN_IT_WKU : Wake-up interrupt
-  *            @arg CAN_IT_SLK : Sleep acknowledge interrupt
-  *            @arg CAN_IT_EWG : Error warning interrupt
-  *            @arg CAN_IT_EPV : Error passive interrupt
-  *            @arg CAN_IT_BOF : Bus-off interrupt
-  *            @arg CAN_IT_LEC : Last error code interrupt
-  *            @arg CAN_IT_ERR : Error Interrupt
-  * @retval None.
-  */
-#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the specified CAN interrupts
-  * @param  __HANDLE__: CAN handle.
-  * @param  __INTERRUPT__: CAN Interrupt.
-  *         This parameter can be one of the following values:
-  *            @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
-  *            @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
-  *            @arg CAN_IT_FF0 : FIFO 0 full interrupt
-  *            @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
-  *            @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
-  *            @arg CAN_IT_FF1 : FIFO 1 full interrupt
-  *            @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
-  *            @arg CAN_IT_WKU : Wake-up interrupt
-  *            @arg CAN_IT_SLK : Sleep acknowledge interrupt
-  *            @arg CAN_IT_EWG : Error warning interrupt
-  *            @arg CAN_IT_EPV : Error passive interrupt
-  *            @arg CAN_IT_BOF : Bus-off interrupt
-  *            @arg CAN_IT_LEC : Last error code interrupt
-  *            @arg CAN_IT_ERR : Error Interrupt
-  * @retval None.
-  */
-#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Return the number of pending received messages.
-  * @param  __HANDLE__: CAN handle.
-  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
-  * @retval The number of pending message.
-  */
-#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
-
-/** @brief  Check whether the specified CAN flag is set or not.
-  * @param  __HANDLE__: specifies the CAN Handle.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
-  *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
-  *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
-  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
-  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
-  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
-  *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
-  *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
-  *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
-  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
-  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
-  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
-  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
-  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
-  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
-  *            @arg CAN_FLAG_WKU: Wake up Flag
-  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
-  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
-  *            @arg CAN_FLAG_EWG: Error Warning Flag
-  *            @arg CAN_FLAG_EPV: Error Passive Flag
-  *            @arg CAN_FLAG_BOF: Bus-Off Flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
-
-/** @brief  Clear the specified CAN pending flag.
-  * @param  __HANDLE__: specifies the CAN Handle.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
-  *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
-  *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
-  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
-  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
-  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
-  *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
-  *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
-  *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
-  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
-  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
-  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
-  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
-  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
-  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
-  *            @arg CAN_FLAG_WKU: Wake up Flag
-  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8U) == TSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->TSR)  = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == RF0R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == RF1R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == MSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->MSR)  = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0)
-
-
-/** @brief  Check if the specified CAN interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the CAN Handle.
-  * @param  __INTERRUPT__: specifies the CAN interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
-  *            @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
-  *            @arg CAN_IT_FF0 : FIFO 0 full interrupt
-  *            @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
-  *            @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
-  *            @arg CAN_IT_FF1 : FIFO 1 full interrupt
-  *            @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
-  *            @arg CAN_IT_WKU : Wake-up interrupt
-  *            @arg CAN_IT_SLK : Sleep acknowledge interrupt
-  *            @arg CAN_IT_EWG : Error warning interrupt
-  *            @arg CAN_IT_EPV : Error passive interrupt
-  *            @arg CAN_IT_BOF : Bus-off interrupt
-  *            @arg CAN_IT_LEC : Last error code interrupt
-  *            @arg CAN_IT_ERR : Error Interrupt
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/**
-  * @brief  Check the transmission status of a CAN Frame.
-  * @param  __HANDLE__: specifies the CAN Handle.
-  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
-  * @retval The new status of transmission  (TRUE or FALSE).
-  */
-#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
- ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
-
-/**
-  * @brief  Release the specified receive FIFO.
-  * @param  __HANDLE__: CAN handle.
-  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
-  * @retval None.
-  */
-#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) 
-
-/**
-  * @brief  Cancel a transmit request.
-  * @param  __HANDLE__: specifies the CAN Handle.
-  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
-  * @retval None.
-  */
-#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
- ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
-
-/**
-  * @brief  Enable or disables the DBG Freeze for CAN.
-  * @param  __HANDLE__: specifies the CAN Handle.
-  * @param  __NEWSTATE__: new state of the CAN peripheral. 
-  *         This parameter can be: ENABLE (CAN reception/transmission is frozen
-  *         during debug. Reception FIFOs can still be accessed/controlled normally) 
-  *         or DISABLE (CAN is working during debug).
-  * @retval None
-  */
-#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
-((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) 
-
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup CAN_Private_Macros   CAN Private Macros
-  * @{
-  */
-
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
-                           ((MODE) == CAN_MODE_LOOPBACK)|| \
-                           ((MODE) == CAN_MODE_SILENT) || \
-                           ((MODE) == CAN_MODE_SILENT_LOOPBACK))
-
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
-                         ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
-
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
-
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
-
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
-                                  ((MODE) == CAN_FILTERMODE_IDLIST))
-
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
-                                    ((SCALE) == CAN_FILTERSCALE_32BIT))
-
-
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
-                                  ((FIFO) == CAN_FILTER_FIFO1))
-
-#define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \
-                                ((IDTYPE) == CAN_ID_EXT))
-
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
-
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
-
-#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
-
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
-#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
-#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
-
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
-
-/**
-  * @}
-  */
-
-/* Include CAN HAL Extension module */
-#include "stm32f1xx_hal_can_ex.h"
-
-/* Exported functions --------------------------------------------------------*/  
-/** @addtogroup CAN_Exported_Functions
-  * @{
-  */
-  
-/** @addtogroup CAN_Exported_Functions_Group1
- *  @brief    Initialization and Configuration functions 
- * @{
- */
-/* Initialization and de-initialization functions *****************************/ 
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
-/**
- * @}
- */ 
- 
-/** @addtogroup CAN_Exported_Functions_Group2
- *  @brief    I/O operation functions 
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
-void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
-/**
- * @}
- */ 
- 
-/** @addtogroup CAN_Exported_Functions_Group3
- *  @brief   CAN Peripheral State functions 
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
-/**
- * @}
- */ 
- 
-/**
- * @}
- */ 
- 
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || */
-       /* STM32F103xG) || STM32F105xC || STM32F107xC    */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __stm32f1xx_CAN_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_can_ex.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,147 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_can_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of CAN HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_CAN_EX_H
-#define __STM32F1xx_HAL_CAN_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
-    defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CANEx CANEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-      
-/** 
-  * @brief  CAN filter configuration structure definition
-  */
-/* CAN filter banks differences over STM32F1 devices:                         */
-/* - STM32F1 Connectivity line: 28 filter banks shared between CAN1 and CAN2  */
-/* - Other STM32F10x devices:   14 filter banks                               */
-
-typedef struct
-{
-  uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit
-                                       configuration, first one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 
-                                              
-  uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit
-                                       configuration, second one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 
-
-  uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,
-                                       according to the mode (MSBs for a 32-bit configuration,
-                                       first one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 
-
-  uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,
-                                       according to the mode (LSBs for a 32-bit configuration,
-                                       second one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 
-
-  uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
-                                       This parameter can be a value of @ref CAN_filter_FIFO */
-#if defined(STM32F105xC) || defined(STM32F107xC)
-  uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized. 
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
-#else
-  uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized. 
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 13. */
-#endif /* STM32F105xC || STM32F107xC */
-  uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.
-                                       This parameter can be a value of @ref CAN_filter_mode */
-
-  uint32_t FilterScale;           /*!< Specifies the filter scale.
-                                       This parameter can be a value of @ref CAN_filter_scale */
-
-  uint32_t FilterActivation;      /*!< Enable or disable the filter.
-                                       This parameter can be set to ENABLE or DISABLE. */
-                                       
-  uint32_t BankNumber;            /*!< Select the start slave bank filter
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 28. */ 
-  
-}CAN_FilterConfTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup CANEx_Private_Macros CAN Extended Private Macros
-  * @{
-  */
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
-#else
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || */
-       /* STM32F103xG) || STM32F105xC || STM32F107xC    */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_CAN_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_cec.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,411 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_cec.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of CEC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_CEC_H
-#define __STM32F1xx_HAL_CEC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F100xB) || defined(STM32F100xE)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CEC
-  * @{
-  */ 
-  
-/** @addtogroup CEC_Private_Constants
-  * @{
-  */
-#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BIT_TIMING_ERROR_MODE_STANDARD) || \
-                                        ((MODE) == CEC_BIT_TIMING_ERROR_MODE_ERRORFREE))
-#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BIT_PERIOD_ERROR_MODE_STANDARD) || \
-                                        ((MODE) == CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE))
-
-/** @brief Check CEC device Own Address Register (OAR) setting.
-  * @param  __ADDRESS__: CEC own address.               
-  * @retval Test result (TRUE or FALSE).
-  */
-#define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)  
-
-/** @brief Check CEC initiator or destination logical address setting.
-  *        Initiator and destination addresses are coded over 4 bits. 
-  * @param  __ADDRESS__: CEC initiator or logical address.               
-  * @retval Test result (TRUE or FALSE).
-  */
-#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)    
-
-/** @brief Check CEC message size.
-  *       The message size is the payload size: without counting the header, 
-  *       it varies from 0 byte (ping operation, one header only, no payload) to 
-  *       15 bytes (1 opcode and up to 14 operands following the header). 
-  * @param  __SIZE__: CEC message size.               
-  * @retval Test result (TRUE or FALSE).
-  */
-#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)   
-
-/**
- * @}
- */ 
- 
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup CEC_Exported_Types CEC Exported Types
-  * @{
-  */ 
-/** 
-  * @brief CEC Init Structure definition  
-  */ 
-typedef struct
-{  
-  uint32_t TimingErrorFree; /*!< Configures the CEC Bit Timing Error Mode. 
-                                 This parameter can be a value of @ref CEC_BitTimingErrorMode */
-  uint32_t PeriodErrorFree; /*!< Configures the CEC Bit Period Error Mode. 
-                                 This parameter can be a value of @ref CEC_BitPeriodErrorMode */
-  uint8_t  InitiatorAddress; /*!< Initiator address (source logical address, sent in each header) 
-                                 This parameter can be a value <= 0xF */
-}CEC_InitTypeDef;
-
-/** 
-  * @brief HAL CEC State structures definition  
-  */ 
-typedef enum
-{
-  HAL_CEC_STATE_RESET             = 0x00,    /*!< Peripheral Reset state                              */
-  HAL_CEC_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use            */
-  HAL_CEC_STATE_BUSY              = 0x02,    /*!< An internal process is ongoing                      */
-  HAL_CEC_STATE_BUSY_TX           = 0x03,    /*!< Data Transmission process is ongoing                */
-  HAL_CEC_STATE_BUSY_RX           = 0x04,    /*!< Data Reception process is ongoing                   */
-  HAL_CEC_STATE_BUSY_TX_RX        = 0x05,    /*!< Data Transmission and Reception process is ongoing  */
-  HAL_CEC_STATE_TIMEOUT           = 0x06,    /*!< Timeout state                                       */
-  HAL_CEC_STATE_ERROR             = 0x07     /*!< State Error                                         */
-}HAL_CEC_StateTypeDef;
-
-/** 
-  * @brief  HAL Error structures definition  
-  */ 
-typedef enum
-{
-  HAL_CEC_ERROR_NONE  = (uint32_t) 0x0, /*!< no error */
-  HAL_CEC_ERROR_BTE   = CEC_ESR_BTE,    /*!< Bit Timing Error */
-  HAL_CEC_ERROR_BPE   = CEC_ESR_BPE,    /*!< Bit Period Error */
-  HAL_CEC_ERROR_RBTFE = CEC_ESR_RBTFE,  /*!< Rx Block Transfer Finished Error */
-  HAL_CEC_ERROR_SBE   = CEC_ESR_SBE,    /*!< Start Bit Error */
-  HAL_CEC_ERROR_ACKE  = CEC_ESR_ACKE,   /*!< Block Acknowledge Error */
-  HAL_CEC_ERROR_LINE  = CEC_ESR_LINE,   /*!< Line Error */
-  HAL_CEC_ERROR_TBTFE = CEC_ESR_TBTFE,  /*!< Tx Block Transfer Finished Error */
-}HAL_CEC_ErrorTypeDef;
-
-/** 
-  * @brief  CEC handle Structure definition  
-  */  
-typedef struct
-{
-  CEC_TypeDef             *Instance;      /*!< CEC registers base address */
-  
-  CEC_InitTypeDef         Init;           /*!< CEC communication parameters */
-  
-  uint8_t                 *pTxBuffPtr;    /*!< Pointer to CEC Tx transfer Buffer */
-  
-  uint16_t                TxXferCount;    /*!< CEC Tx Transfer Counter */
-  
-  uint8_t                 *pRxBuffPtr;    /*!< Pointer to CEC Rx transfer Buffer */
-  
-  uint16_t                RxXferSize;     /*!< CEC Rx Transfer size, 0: header received only */
-  
-  uint32_t                ErrorCode;      /*!< For errors handling purposes, copy of ESR register in case error is reported */
-  
-  HAL_LockTypeDef         Lock;           /*!< Locking object */
-  
-  HAL_CEC_StateTypeDef    State;          /*!< CEC communication state */
-    
-}CEC_HandleTypeDef;
-
-/**
- * @}
- */ 
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CEC_Exported_Constants CEC Exported Constants
-  * @{
-  */
-  
-/** @defgroup CEC_BitTimingErrorMode Bit Timing Error Mode
-  * @{
-  */ 
-#define CEC_BIT_TIMING_ERROR_MODE_STANDARD  ((uint32_t)0x00) /*!< Bit timing error Standard Mode */
-#define CEC_BIT_TIMING_ERROR_MODE_ERRORFREE CEC_CFGR_BTEM    /*!< Bit timing error Free Mode */
-/**
-  * @}
-  */
-
-/** @defgroup CEC_BitPeriodErrorMode Bit Period Error Mode
-  * @{
-  */ 
-#define CEC_BIT_PERIOD_ERROR_MODE_STANDARD ((uint32_t)0x00) /*!< Bit period error Standard Mode */
-#define CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE CEC_CFGR_BPEM    /*!< Bit period error Flexible Mode */
-/**
-  * @}
-  */ 
-  
-/** @defgroup CEC_Initiator_Position Initiator logical address position in message header     
-  * @{
-  */
-#define CEC_INITIATOR_LSB_POS           ((uint32_t) 4)
-/**
-  * @}
-  */
-/** @defgroup CEC_Interrupts_Definitions  Interrupts definition
-  * @{
-  */
-#define CEC_IT_IE CEC_CFGR_IE
-/**
-  * @}
-  */
-
-/** @defgroup CEC_Flags_Definitions  Flags definition
-  * @{
-  */
-#define CEC_FLAG_TSOM  CEC_CSR_TSOM
-#define CEC_FLAG_TEOM  CEC_CSR_TEOM
-#define CEC_FLAG_TERR  CEC_CSR_TERR
-#define CEC_FLAG_TBTRF CEC_CSR_TBTRF
-#define CEC_FLAG_RSOM  CEC_CSR_RSOM
-#define CEC_FLAG_REOM  CEC_CSR_REOM
-#define CEC_FLAG_RERR  CEC_CSR_RERR
-#define CEC_FLAG_RBTF  CEC_CSR_RBTF
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
-  
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CEC_Exported_Macros CEC Exported Macros
-  * @{
-  */
-
-/** @brief  Reset CEC handle state
-  * @param  __HANDLE__: CEC handle.
-  * @retval None
-  */
-#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
-
-/** @brief  Checks whether or not the specified CEC interrupt flag is set.
-  * @param  __HANDLE__: specifies the CEC Handle.
-  * @param  __INTERRUPT__: specifies the interrupt to check.
-  *     @arg CEC_FLAG_TERR: Tx Error
-  *     @arg CEC_FLAG_TBTF: Tx Block Transfer Finished
-  *     @arg CEC_FLAG_RERR: Rx Error
-  *     @arg CEC_FLAG_RBTF: Rx Block Transfer Finished
-  * @retval ITStatus
-  */
-#define __HAL_CEC_GET_FLAG(__HANDLE__, __INTERRUPT__) READ_BIT((__HANDLE__)->Instance->CSR,(__INTERRUPT__)) 
-
-/** @brief  Clears the CEC's pending flags.
-  * @param  __HANDLE__: specifies the CEC Handle.
-  * @param  __FLAG__: specifies the flag to clear. 
-  *   This parameter can be any combination of the following values:
-  *     @arg CEC_CSR_TERR: Tx Error
-  *     @arg CEC_CSR_TBTF: Tx Block Transfer Finished
-  *     @arg CEC_CSR_RERR: Rx Error
-  *     @arg CEC_CSR_RBTF: Rx Block Transfer Finished
-  * @retval none  
-  */
-#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__)                                                                  \
-                          do {                                                                                      \
-                            uint32_t tmp = 0x0;                                                                     \
-                            tmp = (__HANDLE__)->Instance->CSR & 0x2;                                                \
-                            (__HANDLE__)->Instance->CSR &= (uint32_t)(((~(uint32_t)(__FLAG__)) & 0xFFFFFFFC) | tmp);\
-                          } while(0)
-                      
-/** @brief  Enables the specified CEC interrupt.
-  * @param  __HANDLE__: specifies the CEC Handle.
-  * @param  __INTERRUPT__: The CEC interrupt to enable.
-  *          This parameter can be:
-  *            @arg CEC_IT_IE         : Interrupt Enable                 
-  * @retval none
-  */
-#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
-
-/** @brief  Disables the specified CEC interrupt.
-  * @param  __HANDLE__: specifies the CEC Handle.
-  * @param  __INTERRUPT__: The CEC interrupt to enable.
-  *          This parameter can be:
-  *            @arg CEC_IT_IE         : Interrupt Enable                         
-  * @retval none
-  */   
-#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
-
-/** @brief  Checks whether or not the specified CEC interrupt is enabled.
-  * @param  __HANDLE__: specifies the CEC Handle.
-  * @param  __INTERRUPT__: The CEC interrupt to enable.
-  *          This parameter can be:
-  *            @arg CEC_IT_IE         : Interrupt Enable                        
-  * @retval FlagStatus  
-  */
-#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) READ_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
-
-/** @brief  Enables the CEC device
-  * @param  __HANDLE__: specifies the CEC Handle.               
-  * @retval none 
-  */
-#define __HAL_CEC_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
-
-/** @brief  Disables the CEC device
-  * @param  __HANDLE__: specifies the CEC Handle.               
-  * @retval none 
-  */
-#define __HAL_CEC_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
-
-/** @brief  Set Transmission Start flag
-  * @param  __HANDLE__: specifies the CEC Handle.               
-  * @retval none 
-  */
-#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
-
-/** @brief  Set Transmission End flag
-  * @param  __HANDLE__: specifies the CEC Handle.               
-  * @retval none  
-  */
-#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
-
-/** @brief  Get Transmission Start flag
-  * @param  __HANDLE__: specifies the CEC Handle.               
-  * @retval FlagStatus 
-  */
-#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
-
-/** @brief  Get Transmission End flag
-  * @param  __HANDLE__: specifies the CEC Handle.               
-  * @retval FlagStatus 
-  */
-#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
-
-/** @brief  Clear OAR register
-  * @param  __HANDLE__: specifies the CEC Handle.               
-  * @retval none 
-  */
-#define __HAL_CEC_CLEAR_OAR(__HANDLE__)   CLEAR_BIT((__HANDLE__)->Instance->OAR, CEC_OAR_OA)
-
-/** @brief  Set OAR register
-  * @param  __HANDLE__: specifies the CEC Handle. 
-  * @param  __ADDRESS__: Own Address value.
-  * @retval none 
-  */
-#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) MODIFY_REG((__HANDLE__)->Instance->OAR, CEC_OAR_OA, (__ADDRESS__));
-
-/**
-  * @}
-  */                       
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CEC_Exported_Functions CEC Exported Functions
-  * @{
-  */
-  
-/** @addtogroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions 
-  * @{
-  */
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
-HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
-void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
-void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
-/**
-  * @}
-  */
-
-/** @addtogroup CEC_Exported_Functions_Group2 Input and Output operation functions 
-  *  @brief CEC Transmit/Receive functions 
-  * @{
-  */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
-HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
-uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec);
-void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
-void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
-void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
-void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
-/**
-  * @}
-  */
-
-/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions 
-  *  @brief   CEC control functions 
-  * @{
-  */
-/* Peripheral State and Error functions ***************************************/
-HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
-uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_CEC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_conf.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,367 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_conf.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   HAL configuration template file.
-  *          This file should be copied to the application folder and renamed
-  *          to stm32f1xx_hal_conf.h.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_CONF_H
-#define __STM32F1xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
-#define HAL_CAN_MODULE_ENABLED
-#define HAL_CEC_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_CRC_MODULE_ENABLED
-#define HAL_DAC_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_ETH_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_HCD_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-#define HAL_I2S_MODULE_ENABLED
-#define HAL_IRDA_MODULE_ENABLED
-#define HAL_IWDG_MODULE_ENABLED
-#define HAL_NAND_MODULE_ENABLED
-#define HAL_NOR_MODULE_ENABLED
-#define HAL_PCCARD_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_RTC_MODULE_ENABLED
-#define HAL_SD_MODULE_ENABLED
-#define HAL_SMARTCARD_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED
-#define HAL_SRAM_MODULE_ENABLED
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-#define HAL_USART_MODULE_ENABLED
-#define HAL_WWDG_MODULE_ENABLED
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-#if defined(USE_STM3210C_EVAL)
-  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
-#else
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  *        This value is used by the UART, RTC HAL module to compute the system frequency
-  */
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE    ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-   
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for LSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-   
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */           
-#define  TICK_INT_PRIORITY            ((uint32_t)0x000F)    /*!< tick interrupt priority */            
-#define  USE_RTOS                     0     
-#define  PREFETCH_ENABLE              1
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/*#define USE_FULL_ASSERT    1*/ 
-
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2
-#define MAC_ADDR1   0
-#define MAC_ADDR2   0
-#define MAC_ADDR3   0
-#define MAC_ADDR4   0
-#define MAC_ADDR5   0
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)8)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/ 
-#define DP83848_PHY_ADDRESS             0x01
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
- 
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32f1xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32f1xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-   
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f1xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f1xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */  
-   
-#ifdef HAL_CAN_MODULE_ENABLED
- #include "stm32f1xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f1xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32f1xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32f1xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32f1xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
- #include "stm32f1xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32f1xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
- #include "stm32f1xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
- #include "stm32f1xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f1xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f1xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f1xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f1xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f1xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
- #include "stm32f1xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f1xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */  
-
-#ifdef HAL_NAND_MODULE_ENABLED
- #include "stm32f1xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */     
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f1xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f1xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f1xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f1xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f1xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f1xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f1xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f1xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f1xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */   
-   
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_cortex.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,476 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_cortex.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of CORTEX HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_CORTEX_H
-#define __STM32F1xx_HAL_CORTEX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CORTEX
-  * @{
-  */ 
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Types Cortex Exported Types
-  * @{
-  */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
-  * @brief  MPU Region initialization structure 
-  * @{
-  */
-typedef struct
-{
-  uint8_t                Enable;                /*!< Specifies the status of the region. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
-  uint8_t                Number;                /*!< Specifies the number of the region to protect. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
-  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
-  uint8_t                Size;                  /*!< Specifies the size of the region to protect. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
-  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable. 
-                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */         
-  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
-                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */                 
-  uint8_t                AccessPermission;      /*!< Specifies the region access permission type. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
-  uint8_t                DisableExec;           /*!< Specifies the instruction access status. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
-  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
-  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
-  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
-}MPU_Region_InitTypeDef;
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
-  * @{
-  */
-
-
-/** @defgroup CORTEX_Preemption_Priority_Group  CORTEX Preemption Priority Group 
-  * @{
-  */
-
-#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
-                                                                 4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
-                                                                 3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
-                                                                 2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
-                                                                 1 bits for subpriority */
-#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
-                                                                 0 bits for subpriority */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
-  * @{
-  */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
-#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
-
-/**
-  * @}
-  */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
-  * @{
-  */
-#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)  
-#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
-#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
-#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
-  * @{
-  */
-#define  MPU_REGION_ENABLE     ((uint8_t)0x01)
-#define  MPU_REGION_DISABLE    ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
-  * @{
-  */
-#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
-#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
-  * @{
-  */
-#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
-  * @{
-  */
-#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
-  * @{
-  */
-#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
-  * @{
-  */
-#define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
-#define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
-#define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
-  * @{
-  */
-#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
-#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
-#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06) 
-#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07) 
-#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08) 
-#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)  
-#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
-#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B) 
-#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C) 
-#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D) 
-#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E) 
-#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F) 
-#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
-#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
-#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
-#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13) 
-#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14) 
-#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15) 
-#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16) 
-#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
-#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
-#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
-#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
-#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
-#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
-#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D) 
-#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E) 
-#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
-/**                                
-  * @}
-  */
-   
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 
-  * @{
-  */
-#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)  
-#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01) 
-#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)  
-#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)  
-#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05) 
-#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
-  * @{
-  */
-#define  MPU_REGION_NUMBER0    ((uint8_t)0x00)  
-#define  MPU_REGION_NUMBER1    ((uint8_t)0x01) 
-#define  MPU_REGION_NUMBER2    ((uint8_t)0x02)  
-#define  MPU_REGION_NUMBER3    ((uint8_t)0x03)  
-#define  MPU_REGION_NUMBER4    ((uint8_t)0x04) 
-#define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
-#define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
-#define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-  
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
-  * @{
-  */  
-
-/** @defgroup CORTEX_Preemption_Priority_Group_Macro  CORTEX Preemption Priority Group 
-  * @{
-  */
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
- 
-#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
-
-#define IS_NVIC_DEVICE_IRQ(IRQ)  ((IRQ) >= 0x00)
-
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
-  * @{
-  */                       
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
-                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
-/**
-  * @}
-  */
-#if (__MPU_PRESENT == 1)
-#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
-                                     ((STATE) == MPU_REGION_DISABLE))
-
-#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
-                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
-
-#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
-
-#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
-
-#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
-
-#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
-                                ((TYPE) == MPU_TEX_LEVEL1)  || \
-                                ((TYPE) == MPU_TEX_LEVEL2))
-
-#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
-                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
-
-#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER7))
-
-#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4GB))
-
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CORTEX_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup CORTEX_Exported_Functions_Group1
-  * @{
-  */  
-/* Initialization and de-initialization functions *****************************/
-void     HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
-void     HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
-void     HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
-void     HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
-void     HAL_NVIC_SystemReset(void);
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
-/**
-  * @}
-  */
-
-/** @addtogroup CORTEX_Exported_Functions_Group2
-  * @{
-  */ 
-/* Peripheral Control functions ***********************************************/
-#if (__MPU_PRESENT == 1)
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-#endif /* __MPU_PRESENT */
-uint32_t HAL_NVIC_GetPriorityGrouping(void);
-void     HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
-void     HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
-void     HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
-void     HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
-void     HAL_SYSTICK_IRQHandler(void);
-void     HAL_SYSTICK_Callback(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-                                                                               
-/* Private functions ---------------------------------------------------------*/   
-/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
-  * @brief    CORTEX private  functions 
-  * @{
-  */
-
-#if (__MPU_PRESENT == 1)
-/**
-  * @brief  Disables the MPU
-  * @retval None
-  */
-__STATIC_INLINE void HAL_MPU_Disable(void)
-{
-  /* Disable fault exceptions */
-  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-  
-  /* Disable the MPU */
-  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
-}
-
-/**
-  * @brief  Enables the MPU
-  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault, 
-  *          NMI, FAULTMASK and privileged accessto the default memory 
-  *          This parameter can be one of the following values:
-  *            @arg MPU_HFNMI_PRIVDEF_NONE
-  *            @arg MPU_HARDFAULT_NMI
-  *            @arg MPU_PRIVILEGED_DEFAULT
-  *            @arg MPU_HFNMI_PRIVDEF
-  * @retval None
-  */
-__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
-{
-  /* Enable the MPU */
-  MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
-  
-  /* Enable fault exceptions */
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-}
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_CORTEX_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_crc.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,195 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_crc.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of CRC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_CRC_H
-#define __STM32F1xx_HAL_CRC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CRC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup CRC_Exported_Types CRC Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  CRC HAL State Structure definition  
-  */ 
-typedef enum
-{
-  HAL_CRC_STATE_RESET     = 0x00,  /*!< CRC not yet initialized or disabled */
-  HAL_CRC_STATE_READY     = 0x01,  /*!< CRC initialized and ready for use   */
-  HAL_CRC_STATE_BUSY      = 0x02,  /*!< CRC internal process is ongoing     */
-  HAL_CRC_STATE_TIMEOUT   = 0x03,  /*!< CRC timeout state                   */
-  HAL_CRC_STATE_ERROR     = 0x04   /*!< CRC error state                     */
-
-}HAL_CRC_StateTypeDef;
-
-/** 
-  * @brief  CRC handle Structure definition
-  */ 
-typedef struct
-{
-  CRC_TypeDef                 *Instance;  /*!< Register base address   */
-
-  HAL_LockTypeDef             Lock;       /*!< CRC locking object      */
-
-  __IO HAL_CRC_StateTypeDef   State;      /*!< CRC communication state */
-
-}CRC_HandleTypeDef;
-
-/**
-  * @}
-  */ 
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup CRC_Exported_Macros CRC Exported Macros
-  * @{
-  */
-
-/** @brief Reset CRC handle state
-  * @param  __HANDLE__: CRC handle
-  * @retval None
-  */
-#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
-
-/**
-  * @brief  Resets CRC Data Register.
-  * @param  __HANDLE__: CRC handle
-  * @retval None
-  */
-#define __HAL_CRC_DR_RESET(__HANDLE__)            (SET_BIT((__HANDLE__)->Instance->CR,CRC_CR_RESET))
-
-/**
-  * @brief Stores a 8-bit data in the Independent Data(ID) register.
-  * @param __HANDLE__: CRC handle
-  * @param __VALUE__: 8-bit value to be stored in the ID register
-  * @retval None
-  */
-#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
-
-/**
-  * @brief Returns the 8-bit data stored in the Independent Data(ID) register.
-  * @param __HANDLE__: CRC handle
-  * @retval 8-bit value of the ID register 
-  */
-#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
-
-/**
-  * @}
-  */ 
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup CRC_Exported_Functions
-  * @{
-  */ 
-
-/** @addtogroup CRC_Exported_Functions_Group1
-  * @{
-  */ 
-
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef     HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
-HAL_StatusTypeDef     HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
-void                  HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
-void                  HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup CRC_Exported_Functions_Group2
-  * @{
-  */ 
-
-/* Peripheral Control functions  ************************************************/
-uint32_t              HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-uint32_t              HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-
-  
-/**
-  * @}
-  */ 
-
-/** @addtogroup CRC_Exported_Functions_Group3
-  ** @{
-  */ 
-
-/* Peripheral State functions  **************************************************/
-HAL_CRC_StateTypeDef  HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
-
-/**
-  * @}
-  */ 
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_dac.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,324 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_dac.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of DAC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_DAC_H
-#define __STM32F1xx_HAL_DAC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
-   
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DAC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Types DAC Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  HAL State structures definition  
-  */ 
-typedef enum
-{
-  HAL_DAC_STATE_RESET             = 0x00,  /*!< DAC not yet initialized or disabled  */
-  HAL_DAC_STATE_READY             = 0x01,  /*!< DAC initialized and ready for use    */
-  HAL_DAC_STATE_BUSY              = 0x02,  /*!< DAC internal processing is ongoing   */
-  HAL_DAC_STATE_TIMEOUT           = 0x03,  /*!< DAC timeout state                    */
-  HAL_DAC_STATE_ERROR             = 0x04   /*!< DAC error state                      */
- 
-}HAL_DAC_StateTypeDef;
- 
-/** 
-  * @brief  DAC handle Structure definition  
-  */ 
-typedef struct
-{
-  DAC_TypeDef                 *Instance;     /*!< Register base address             */
-  
-  __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
-
-  HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
-  
-  DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
-  
-  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */ 
-  
-  __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
-  
-}DAC_HandleTypeDef;
-
-/** 
-  * @brief   DAC Configuration regular Channel structure definition  
-  */ 
-typedef struct
-{
-  uint32_t DAC_Trigger;       /*!< Specifies the external trigger for the selected DAC channel.
-                                   This parameter can be a value of @ref DACEx_trigger_selection
-                                   Note: For STM32F100x high-density value line devices, additional trigger sources are available. */
-  
-  uint32_t DAC_OutputBuffer;  /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
-                                   This parameter can be a value of @ref DAC_output_buffer */
-  
-}DAC_ChannelConfTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Constants DAC Exported Constants
-  * @{
-  */
-
-/** @defgroup DAC_Error_Code DAC Error Code
-  * @{
-  */
-#define  HAL_DAC_ERROR_NONE              0x00    /*!< No error                          */
-#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01    /*!< DAC channel1 DMA underrun error   */
-#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02    /*!< DAC channel2 DMA underrun error   */
-#define  HAL_DAC_ERROR_DMA               0x04    /*!< DMA error                         */   
-/**
-  * @}
-  */
-  
-/** @defgroup DAC_output_buffer DAC output buffer
-  * @{
-  */
-#define DAC_OUTPUTBUFFER_ENABLE            ((uint32_t)0x00000000)
-#define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_CR_BOFF1)
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Channel_selection DAC Channel selection
-  * @{
-  */
-#define DAC_CHANNEL_1                      ((uint32_t)0x00000000)
-#define DAC_CHANNEL_2                      ((uint32_t)0x00000010)
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_data_alignement DAC data alignement
-  * @{
-  */
-#define DAC_ALIGN_12B_R                    ((uint32_t)0x00000000)
-#define DAC_ALIGN_12B_L                    ((uint32_t)0x00000004)
-#define DAC_ALIGN_8B_R                     ((uint32_t)0x00000008)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Macros DAC Exported Macros
-  * @{
-  */
-
-/** @brief Reset DAC handle state
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @retval None
-  */
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
-
-/** @brief Enable the DAC channel
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __DAC_Channel__: specifies the DAC channel
-  * @retval None
-  */
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_Channel__)))
-
-/** @brief Disable the DAC channel
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __DAC_Channel__: specifies the DAC channel.
-  * @retval None
-  */
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_Channel__)))
- 
-
-/**
-  * @}
-  */ 
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup DAC_Private_Macros DAC Private Macros
-  * @{
-  */
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
-                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
-
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
-                                 ((CHANNEL) == DAC_CHANNEL_2))
-
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
-                             ((ALIGN) == DAC_ALIGN_12B_L) || \
-                             ((ALIGN) == DAC_ALIGN_8B_R))
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
-
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
-
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
-
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
-
-/**
-  * @}
-  */
-  
-
-/* Include DAC HAL Extension module */
-#include "stm32f1xx_hal_dac_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup DAC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions *****************************/ 
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
-
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group4
-  * @{
-  */
-/* Peripheral State functions *************************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
-
-void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Private_Functions DAC Private Functions
-  * @{
-  */ 
-void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); 
-void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-#endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /*__STM32F1xx_HAL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_dac_ex.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,382 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_dac_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of DAC HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_DAC_EX_H
-#define __STM32F1xx_HAL_DAC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
-   
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DACEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-  
-/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
-  * @{
-  */ 
-
-/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
-  * @{
-  */
-#define DAC_LFSRUNMASK_BIT0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
-#define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
-#define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
-#define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
-#define DAC_TRIANGLEAMPLITUDE_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
-#define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
-#define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
-#define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
-#define DAC_TRIANGLEAMPLITUDE_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
-#define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
-
-/**
-  * @}
-  */
-
-/** @defgroup DACEx_wave_generation DACEx wave generation
-  * @{
-  */
-#define DAC_WAVE_NOISE                     ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVE_TRIANGLE                  ((uint32_t)DAC_CR_WAVE1_1)
-
-/**
-  * @}
-  */
-   
-/** @defgroup DACEx_trigger_selection DAC trigger selection
-  * @{
-  */
-#define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
-                                                                       has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T6_TRGO                ((uint32_t)                                                    DAC_CR_TEN1)  /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO                ((uint32_t)(                 DAC_CR_TSEL1_1                  | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2                                   | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1                                     | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
-
-#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
-/* For STM32F10x high-density and XL-density devices: TIM8 */
-#define DAC_TRIGGER_T8_TRGO                ((uint32_t)                                   DAC_CR_TSEL1_0 | DAC_CR_TEN1)  /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
-#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-   
-#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
-/* For STM32F10x connectivity line devices and STM32F100x devices: TIM3 */
-#define DAC_TRIGGER_T3_TRGO                ((uint32_t)                                   DAC_CR_TSEL1_0 | DAC_CR_TEN1)  /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
-#endif /* STM32F100xB || STM32F100xE || STM32F105xC || STM32F107xC */
-
-/* Availability of trigger from TIM5 and TIM15:                               */
-/*  - For STM32F10x value line devices STM32F100xB:                           */
-/*    trigger from TIM15 is available, TIM5 not available.                    */
-/*  - For STM32F10x value line devices STM32F100xE:                           */
-/*    trigger from TIM15 and TIM5 are both available,                         */
-/*    selection depends on remap (with TIM5 as default configuration).        */
-/*  - Other STM32F1 devices:                                                  */
-/*    trigger from TIM5 is available, TIM15 not  available.                   */
-#if defined (STM32F100xB)
-#define DAC_TRIGGER_T15_TRGO               ((uint32_t)(                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
-#else
-
-#define DAC_TRIGGER_T5_TRGO                ((uint32_t)(                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-
-#if defined (STM32F100xE)
-/*!< DAC trigger availability depending on STM32F1 devices:
-     For STM32F100x high-density value line devices, the TIM15 TRGO event can be selected 
-     as replacement of TIM5 TRGO if the MISC_REMAP bit in the AFIO_MAPR2 register is set.
-     Refer to macro "__HAL_AFIO_REMAP_MISC_ENABLE()/__HAL_AFIO_REMAP_MISC_DISABLE()".
-     Otherwise, TIM5 TRGO is used and TIM15 TRGO is not used (default case).
-     For more details please refer to the AFIO section. */
-#define DAC_TRIGGER_T15_TRGO    DAC_TRIGGER_T5_TRGO
-#endif /* STM32F100xE */
-   
-#endif /* STM32F100xB */
-/**
-  * @}
-  */
-
-#if defined (STM32F100xB) || defined (STM32F100xE)
-/** @defgroup DAC_flags_definition DAC flags definition
-  * @{
-  */ 
-#define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)   
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_IT_definition DAC IT definition
-  * @{
-  */ 
-#define DAC_IT_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)   
-
-/**
-  * @}
-  */
-#endif /* STM32F100xB || STM32F100xE */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-#if defined (STM32F100xB) || defined (STM32F100xE)
-/** @defgroup DACEx_Exported_Macros DACEx Exported Macros
-  * @{
-  */
-
-/** @brief Enable the DAC interrupt
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __INTERRUPT__: specifies the DAC interrupt.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
-  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
-  * @retval None
-  */
-#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
-
-/** @brief Disable the DAC interrupt
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __INTERRUPT__: specifies the DAC interrupt.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
-  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
-  * @retval None
-  */
-#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
-
-/** @brief  Checks if the specified DAC interrupt source is enabled or disabled.
-  * @param __HANDLE__: DAC handle
-  * @param __INTERRUPT__: DAC interrupt source to check
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
-  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
-  * @retval State of interruption (SET or RESET)
-  */
-#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
-    
-/** @brief  Get the selected DAC's flag status.
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __FLAG__: specifies the DAC flag to get.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
-  *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
-  * @retval None
-  */
-#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the DAC's flag.
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __FLAG__: specifies the DAC flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
-  *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
-  * @retval None
-  */
-#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
-
-
-/**
-  * @}
-  */
-#endif /* STM32F100xB || STM32F100xE */
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup DACEx_Private_Macros DACEx Private Macros
-  * @{
-  */
-#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)    || \
-                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
-                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-#if defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)    || \
-                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
-                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-#endif /* STM32F100xE || STM32F105xC || STM32F107xC */
-#if defined (STM32F100xB)
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)     || \
-                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO)  || \
-                                 ((TRIGGER) == DAC_TRIGGER_T3_TRGO)  || \
-                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO)  || \
-                                 ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO)  || \
-                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO)  || \
-                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9)  || \
-                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-#endif /* STM32F100xB */
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/  
-
-/** @addtogroup DACEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DACEx_Exported_Functions_Group1
-  * @{
-  */
-/* Extension features functions ***********************************************/
-
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
-
-#if defined (STM32F100xB) || defined (STM32F100xE)
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
-void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
-#endif /* STM32F100xB) || defined (STM32F100xE) */
-
-/**
-  * @}
-  */
-
-
-
-    
-/**
-  * @}
-  */
-
-/** @addtogroup DACEx_Private_Functions
-  * @{
-  */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); 
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F1xx_HAL_DAC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_def.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,214 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_def.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   This file contains HAL common defines, enumeration, macros and 
-  *          structures definitions. 
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_DEF
-#define __STM32F1xx_HAL_DEF
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-#include "stm32_hal_legacy.h"
-#include <stdio.h>
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  HAL Status structures definition  
-  */  
-typedef enum 
-{
-  HAL_OK       = 0x00,
-  HAL_ERROR    = 0x01,
-  HAL_BUSY     = 0x02,
-  HAL_TIMEOUT  = 0x03
-} HAL_StatusTypeDef;
-
-/** 
-  * @brief  HAL Lock structures definition  
-  */
-typedef enum 
-{
-  HAL_UNLOCKED = 0x00,
-  HAL_LOCKED   = 0x01  
-} HAL_LockTypeDef;
-
-/* Exported macro ------------------------------------------------------------*/
-
-#define HAL_MAX_DELAY      0xFFFFFFFF
-
-#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) != RESET)
-#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == RESET)
-
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_)           \
-                        do{                                                  \
-                              (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
-                              (__DMA_HANDLE_).Parent = (__HANDLE__);             \
-                          } while(0)
-
-#define UNUSED(x) ((void)(x))
-
-/** @brief Reset the Handle's State field.
-  * @param __HANDLE__: specifies the Peripheral Handle.
-  * @note  This macro can be used for the following purpose: 
-  *          - When the Handle is declared as local variable; before passing it as parameter
-  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro 
-  *            to set to 0 the Handle's "State" field.
-  *            Otherwise, "State" field may have any random value and the first time the function 
-  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
-  *            (i.e. HAL_PPP_MspInit() will not be executed).
-  *          - When there is a need to reconfigure the low level hardware: instead of calling
-  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
-  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
-  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
-  * @retval None
-  */
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
-
-#if (USE_RTOS == 1)
-  #error " USE_RTOS should be 0 in the current HAL release "
-#else
-  #define __HAL_LOCK(__HANDLE__)                                           \
-                                do{                                        \
-                                    if((__HANDLE__)->Lock == HAL_LOCKED)  \
-                                    {                                      \
-                                       return HAL_BUSY;                    \
-                                    }                                      \
-                                    else                                   \
-                                    {                                      \
-                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
-                                    }                                      \
-                                  }while (0)
-
-  #define __HAL_UNLOCK(__HANDLE__)                                          \
-                                  do{                                       \
-                                      (__HANDLE__)->Lock = HAL_UNLOCKED;   \
-                                    }while (0)
-#endif /* USE_RTOS */
-
-#if  defined ( __GNUC__ )
-  #ifndef __weak
-    #define __weak   __attribute__((weak))
-  #endif /* __weak */
-  #ifndef __packed
-    #define __packed __attribute__((__packed__))
-  #endif /* __packed */
-#endif /* __GNUC__ */
-
-
-/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined   (__GNUC__)        /* GNU Compiler */
-  #ifndef __ALIGN_END
-    #define __ALIGN_END    __attribute__ ((aligned (4)))
-  #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN  
-    #define __ALIGN_BEGIN
-  #endif /* __ALIGN_BEGIN */
-#else
-  #ifndef __ALIGN_END
-    #define __ALIGN_END
-  #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN      
-    #if defined   (__CC_ARM)      /* ARM Compiler */
-      #define __ALIGN_BEGIN    __align(4)  
-    #elif defined (__ICCARM__)    /* IAR Compiler */
-      #define __ALIGN_BEGIN 
-    #endif /* __CC_ARM */
-  #endif /* __ALIGN_BEGIN */
-#endif /* __GNUC__ */
-
-/** 
-  * @brief  __RAM_FUNC definition
-  */ 
-#if defined ( __CC_ARM   )
-/* ARM Compiler
-   ------------
-   RAM functions are defined using the toolchain options. 
-   Functions that are executed in RAM should reside in a separate source module.
-   Using the 'Options for File' dialog you can simply change the 'Code / Const' 
-   area of a module to a memory space in physical RAM.
-   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
-   dialog. 
-*/
-#define __RAM_FUNC HAL_StatusTypeDef 
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
-   ---------------
-   RAM functions are defined using a specific toolchain keyword "__ramfunc". 
-*/
-#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
-
-#elif defined   (  __GNUC__  )
-/* GNU Compiler
-   ------------
-  RAM functions are defined using a specific toolchain attribute 
-   "__attribute__((section(".RamFunc")))".
-*/
-#define __RAM_FUNC HAL_StatusTypeDef  __attribute__((section(".RamFunc")))
-
-#endif
-
-/** 
-  * @brief  __NOINLINE definition
-  */ 
-#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )
-/* ARM & GNUCompiler 
-   ---------------- 
-*/
-#define __NOINLINE __attribute__ ( (noinline) )  
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
-   ---------------
-*/
-#define __NOINLINE _Pragma("optimize = no_inline")
-
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32F1xx_HAL_DEF */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_dma.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,480 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_dma.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of DMA HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_DMA_H
-#define __STM32F1xx_HAL_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DMA
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Types DMA Exported Types
-  * @{
-  */
-   
-/** 
-  * @brief  DMA Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral, 
-                                           from memory to memory or from peripheral to memory.
-                                           This parameter can be a value of @ref DMA_Data_transfer_direction */
-
-  uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
-                                           This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
-                               
-  uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
-                                           This parameter can be a value of @ref DMA_Memory_incremented_mode */
-  
-  uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
-                                           This parameter can be a value of @ref DMA_Peripheral_data_size */
-
-  uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
-                                           This parameter can be a value of @ref DMA_Memory_data_size */
-                               
-  uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
-                                           This parameter can be a value of @ref DMA_mode
-                                           @note The circular buffer mode cannot be used if the memory-to-memory
-                                                 data transfer is configured on the selected Channel */ 
-
-  uint32_t Priority;                   /*!< Specifies the software priority for the DMAy Channelx.
-                                            This parameter can be a value of @ref DMA_Priority_level */
-} DMA_InitTypeDef;
-
-/** 
-  * @brief DMA Configuration enumeration values definition
-  */  
-typedef enum 
-{
-  DMA_MODE            = 0,      /*!< Control related DMA mode Parameter in DMA_InitTypeDef        */
-  DMA_PRIORITY        = 1,      /*!< Control related priority level Parameter in DMA_InitTypeDef  */
-  
-} DMA_ControlTypeDef;
-
-/**
-  * @brief  HAL DMA State structures definition  
-  */
-typedef enum
-{
-  HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled */
-  HAL_DMA_STATE_READY             = 0x01,  /*!< DMA initialized and ready for use   */
-  HAL_DMA_STATE_READY_HALF        = 0x11,  /*!< DMA Half process success            */
-  HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing              */
-  HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                   */
-  HAL_DMA_STATE_ERROR             = 0x04,  /*!< DMA error state                     */
-}HAL_DMA_StateTypeDef;
-
-/** 
-  * @brief  HAL DMA Error Code structure definition
-  */
-typedef enum
-{
-  HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
-  HAL_DMA_HALF_TRANSFER      = 0x01,    /*!< Half Transfer     */
-}HAL_DMA_LevelCompleteTypeDef;
-
-/** 
-  * @brief  DMA handle Structure definition
-  */
-typedef struct __DMA_HandleTypeDef
-{
-  DMA_Channel_TypeDef   *Instance;                       /*!< Register base address                  */
-  
-  DMA_InitTypeDef       Init;                            /*!< DMA communication parameters           */ 
-  
-  HAL_LockTypeDef       Lock;                            /*!< DMA locking object                     */  
-  
-  HAL_DMA_StateTypeDef  State;                           /*!< DMA transfer state                     */
-  
-  void                  *Parent;                                                      /*!< Parent object state                    */  
-  
-  void                  (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
-  
-  void                  (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
-  
-  void                  (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
-  
-  __IO uint32_t         ErrorCode;                                                    /*!< DMA Error code                         */
-} DMA_HandleTypeDef;    
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants DMA Exported Constants
-  * @{
-  */
-
-/** @defgroup DMA_Error_Code DMA Error Code
-  * @{
-  */
- #define HAL_DMA_ERROR_NONE      ((uint32_t)0x00)    /*!< No error             */
- #define HAL_DMA_ERROR_TE        ((uint32_t)0x01)    /*!< Transfer error       */
- #define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x20)    /*!< Timeout error        */
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
-  * @{
-  */ 
-#define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)      /*!< Peripheral to memory direction */
-#define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)     /*!< Memory to peripheral direction */
-#define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction     */
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
-  * @{
-  */ 
-#define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)   /*!< Peripheral increment mode Enable */
-#define DMA_PINC_DISABLE       ((uint32_t)0x00000000)     /*!< Peripheral increment mode Disable */
-/**
-  * @}
-  */ 
-
-/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
-  * @{
-  */ 
-#define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)   /*!< Memory increment mode Enable  */
-#define DMA_MINC_DISABLE        ((uint32_t)0x00000000)     /*!< Memory increment mode Disable */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
-  * @{
-  */ 
-#define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Peripheral data alignment: Byte     */
-#define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)   /*!< Peripheral data alignment: HalfWord */
-#define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)   /*!< Peripheral data alignment: Word     */
-/**
-  * @}
-  */ 
-
-/** @defgroup DMA_Memory_data_size DMA Memory data size
-  * @{ 
-  */
-#define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Memory data alignment: Byte     */
-#define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)   /*!< Memory data alignment: HalfWord */
-#define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)   /*!< Memory data alignment: Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_mode DMA mode
-  * @{
-  */ 
-#define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal mode                  */
-#define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)     /*!< Circular mode                */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Priority_level DMA Priority level
-  * @{
-  */
-#define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)     /*!< Priority level : Low       */
-#define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)   /*!< Priority level : Medium    */
-#define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)   /*!< Priority level : High      */
-#define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)     /*!< Priority level : Very_High */
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
-  * @{
-  */
-#define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
-#define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
-#define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
-/**
-  * @}
-  */
-
-/** @defgroup DMA_flag_definitions DMA flag definitions
-  * @{
-  */ 
-#define DMA_FLAG_GL1                      ((uint32_t)0x00000001)
-#define DMA_FLAG_TC1                      ((uint32_t)0x00000002)
-#define DMA_FLAG_HT1                      ((uint32_t)0x00000004)
-#define DMA_FLAG_TE1                      ((uint32_t)0x00000008)
-#define DMA_FLAG_GL2                      ((uint32_t)0x00000010)
-#define DMA_FLAG_TC2                      ((uint32_t)0x00000020)
-#define DMA_FLAG_HT2                      ((uint32_t)0x00000040)
-#define DMA_FLAG_TE2                      ((uint32_t)0x00000080)
-#define DMA_FLAG_GL3                      ((uint32_t)0x00000100)
-#define DMA_FLAG_TC3                      ((uint32_t)0x00000200)
-#define DMA_FLAG_HT3                      ((uint32_t)0x00000400)
-#define DMA_FLAG_TE3                      ((uint32_t)0x00000800)
-#define DMA_FLAG_GL4                      ((uint32_t)0x00001000)
-#define DMA_FLAG_TC4                      ((uint32_t)0x00002000)
-#define DMA_FLAG_HT4                      ((uint32_t)0x00004000)
-#define DMA_FLAG_TE4                      ((uint32_t)0x00008000)
-#define DMA_FLAG_GL5                      ((uint32_t)0x00010000)
-#define DMA_FLAG_TC5                      ((uint32_t)0x00020000)
-#define DMA_FLAG_HT5                      ((uint32_t)0x00040000)
-#define DMA_FLAG_TE5                      ((uint32_t)0x00080000)
-#define DMA_FLAG_GL6                      ((uint32_t)0x00100000)
-#define DMA_FLAG_TC6                      ((uint32_t)0x00200000)
-#define DMA_FLAG_HT6                      ((uint32_t)0x00400000)
-#define DMA_FLAG_TE6                      ((uint32_t)0x00800000)
-#define DMA_FLAG_GL7                      ((uint32_t)0x01000000)
-#define DMA_FLAG_TC7                      ((uint32_t)0x02000000)
-#define DMA_FLAG_HT7                      ((uint32_t)0x04000000)
-#define DMA_FLAG_TE7                      ((uint32_t)0x08000000)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
- 
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMA_Exported_Macros DMA Exported Macros
-  * @{
-  */
-
-/** @brief  Reset DMA handle state
-  * @param  __HANDLE__: DMA handle.
-  * @retval None
-  */
-#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
-
-/**
-  * @brief  Enable the specified DMA Channel.
-  * @param  __HANDLE__: DMA handle
-  * @retval None.
-  */
-#define __HAL_DMA_ENABLE(__HANDLE__)        (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
-
-/**
-  * @brief  Disable the specified DMA Channel.
-  * @param  __HANDLE__: DMA handle
-  * @retval None.
-  */
-#define __HAL_DMA_DISABLE(__HANDLE__)       (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
-
-
-/* Interrupt & Flag management */
-
-/**
-  * @brief  Enables the specified DMA Channel interrupts.
-  * @param  __HANDLE__: DMA handle
-  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @retval None
-  */
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
-
-/**
-  * @brief  Disables the specified DMA Channel interrupts.
-  * @param  __HANDLE__: DMA handle
-  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @retval None
-  */
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
-
-/**
-  * @brief  Checks whether the specified DMA Channel interrupt is enabled or disabled.
-  * @param  __HANDLE__: DMA handle
-  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @retval The state of DMA_IT (SET or RESET).
-  */
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/**
-  * @brief  Returns the number of remaining data units in the current DMAy Channelx transfer.
-  * @param  __HANDLE__: DMA handle
-  *   
-  * @retval The number of remaining data units in the current DMA Channel transfer.
-  */
-#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
-
-/**
-  * @}
-  */
-
-/* Include DMA HAL Extension module */
-#include "stm32f1xx_hal_dma_ex.h"   
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMA_Exported_Functions DMA Exported Functions
-  * @{
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @{
-  */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions 
-  * @{
-  */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
-void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
-  * @{
-  */
-/* Peripheral State and Error functions ***************************************/
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
-uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private Constants -------------------------------------------------------------*/
-/** @defgroup DMA_Private_Constants DMA Private Constants
-  * @brief    DMA private defines and constants 
-  * @{
-  */
-/**
-  * @}
-  */ 
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMA_Private_Macros DMA Private Macros
-  * @brief    DMA private macros 
-  * @{
-  */
-
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
-
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
-                                            ((STATE) == DMA_PINC_DISABLE))
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
-                                        ((STATE) == DMA_MINC_DISABLE))
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
-                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
-                                           ((SIZE) == DMA_PDATAALIGN_WORD))
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
-                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
-                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
-                           ((MODE) == DMA_CIRCULAR)) 
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
-                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
-                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
-                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 
-
-/**
-  * @}
-  */ 
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DMA_Private_Functions DMA Private Functions
-  * @brief    DMA private  functions 
-  * @{
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_dma_ex.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,260 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_dma_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of DMA HAL extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_DMA_EX_H
-#define __STM32F1xx_HAL_DMA_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup DMAEx DMAEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
-  * @{
-  */
-/* Interrupt & Flag management */
-#if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \
-    defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
-/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
-  * @{
-  */
-
-/**
-  * @brief  Returns the current DMA Channel transfer complete flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified transfer complete flag index.
-  */
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
-   DMA_FLAG_TC5)
-
-/**
-  * @brief  Returns the current DMA Channel half transfer complete flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified half transfer complete flag index.
-  */      
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
-   DMA_FLAG_HT5)
-
-/**
-  * @brief  Returns the current DMA Channel transfer error flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified transfer error flag index.
-  */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
-   DMA_FLAG_TE5)
-
-/**
-  * @brief  Get the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: Get the specified flag.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCx:  Transfer complete flag
-  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
-  *            @arg DMA_FLAG_TEx:  Transfer error flag
-  *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.   
-  * @retval The state of FLAG (SET or RESET).
-  */
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
-  (DMA1->ISR & (__FLAG__)))
-
-/**
-  * @brief  Clears the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: specifies the flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCx:  Transfer complete flag
-  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
-  *            @arg DMA_FLAG_TEx:  Transfer error flag
-  *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.   
-  * @retval None
-  */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
-  (DMA1->IFCR = (__FLAG__)))
-
-/**
-  * @}
-  */
-
-#else
-/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
-  * @{
-  */
-
-/**
-  * @brief  Returns the current DMA Channel transfer complete flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified transfer complete flag index.
-  */
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
-   DMA_FLAG_TC7)
-
-/**
-  * @brief  Returns the current DMA Channel half transfer complete flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified half transfer complete flag index.
-  */      
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
-   DMA_FLAG_HT7)
-
-/**
-  * @brief  Returns the current DMA Channel transfer error flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified transfer error flag index.
-  */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
-   DMA_FLAG_TE7)
-
-/**
-  * @brief  Get the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: Get the specified flag.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCx:  Transfer complete flag
-  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
-  *            @arg DMA_FLAG_TEx:  Transfer error flag
-  *         Where x can be 1_7 to select the DMA Channel flag.   
-  * @retval The state of FLAG (SET or RESET).
-  */
-
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)   (DMA1->ISR & (__FLAG__))
-
-/**
-  * @brief  Clears the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: specifies the flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCx:  Transfer complete flag
-  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
-  *            @arg DMA_FLAG_TEx:  Transfer error flag
-  *         Where x can be 1_7 to select the DMA Channel flag.   
-  * @retval None
-  */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
-
-/**
-  * @}
-  */
-
-#endif
-  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */
-       /* STM32F103xG || STM32F105xC || STM32F107xC */
-
-#endif /* __STM32F1xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_eth.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,2135 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_eth.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of ETH HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_ETH_H
-#define __STM32F1xx_HAL_ETH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-#if defined (STM32F107xC) 
-
-/** @addtogroup ETH
-  * @{
-  */ 
-  
-/** @addtogroup ETH_Private_Macros
-  * @{
-  */
-#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
-#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
-                                     ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
-#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
-                             ((SPEED) == ETH_SPEED_100M))
-#define IS_ETH_DUPLEX_MODE(MODE)  (((MODE) == ETH_MODE_FULLDUPLEX) || \
-                                  ((MODE) == ETH_MODE_HALFDUPLEX))
-#define IS_ETH_RX_MODE(MODE)    (((MODE) == ETH_RXPOLLING_MODE) || \
-                                 ((MODE) == ETH_RXINTERRUPT_MODE))
-#define IS_ETH_CHECKSUM_MODE(MODE)    (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
-                                      ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
-#define IS_ETH_MEDIA_INTERFACE(MODE)         (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
-                                              ((MODE) == ETH_MEDIA_INTERFACE_RMII))
-#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
-                              ((CMD) == ETH_WATCHDOG_DISABLE))
-#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
-                            ((CMD) == ETH_JABBER_DISABLE))
-#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
-                                     ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
-                                     ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
-                                     ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
-                                     ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
-                                     ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
-                                     ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
-                                     ((GAP) == ETH_INTERFRAMEGAP_40BIT))
-#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
-                                   ((CMD) == ETH_CARRIERSENCE_DISABLE))
-#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
-                                 ((CMD) == ETH_RECEIVEOWN_DISABLE))
-#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
-                                   ((CMD) == ETH_LOOPBACKMODE_DISABLE))
-#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
-                                      ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
-#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
-                                        ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
-#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
-                                            ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
-#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
-                                     ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
-                                     ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
-                                     ((LIMIT) == ETH_BACKOFFLIMIT_1))
-#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
-                                    ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
-#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
-                                 ((CMD) == ETH_RECEIVEAll_DISABLE))
-#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
-                                        ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
-                                        ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
-#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
-                                     ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
-                                     ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
-#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
-                                                ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
-#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
-                                                ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
-#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
-                                      ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
-#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
-                                                ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
-                                                ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
-                                                ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
-#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
-                                              ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
-                                              ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
-#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
-#define IS_ETH_ZEROQUANTA_PAUSE(CMD)   (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
-                                        ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
-#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
-                                               ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
-                                               ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
-                                               ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
-#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
-                                                ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
-#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
-                                         ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
-#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
-                                          ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
-#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
-                                                ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
-#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
-#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
-                                         ((ADDRESS) == ETH_MAC_ADDRESS1) || \
-                                         ((ADDRESS) == ETH_MAC_ADDRESS2) || \
-                                         ((ADDRESS) == ETH_MAC_ADDRESS3))
-#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
-                                        ((ADDRESS) == ETH_MAC_ADDRESS2) || \
-                                        ((ADDRESS) == ETH_MAC_ADDRESS3))
-#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
-                                           ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
-#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
-                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
-                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
-                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
-                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
-                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
-#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
-                                               ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
-#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
-                                           ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
-#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
-                                         ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
-#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
-                                            ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
-#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
-                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
-                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
-                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
-                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
-                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
-                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
-                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
-#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
-                                          ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
-#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
-                                                    ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
-#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
-                                                     ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
-                                                     ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
-                                                     ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
-#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
-                                          ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
-#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
-                                           ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
-#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
-                                 ((CMD) == ETH_FIXEDBURST_DISABLE))
-#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
-                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
-                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
-                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
-                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
-                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
-                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
-                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
-                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
-                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
-                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
-                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
-#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
-                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
-                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
-                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
-                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
-                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
-                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
-                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
-                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
-                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
-                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
-                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
-#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
-#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
-                                                       ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
-                                                       ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
-                                                       ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
-                                                       ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
-
-#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
-                                            ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
-#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
-                                              ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
-                                              ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
-                                              ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
-#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
-
-#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
-                                          ((BUFFER) == ETH_DMARXDESC_BUFFER2))
-
-#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
-                                           ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
-
-/**
-  * @}
-  */
-
-/** @addtogroup ETH_Private_Constants
-  * @{
-  */
-/* Delay to wait when writing to some Ethernet registers */
-#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
-
-/* ETHERNET Errors */
-#define  ETH_SUCCESS            ((uint32_t)0)
-#define  ETH_ERROR              ((uint32_t)1)
-
-/* ETHERNET DMA Tx descriptors Collision Count Shift */
-#define  ETH_DMATXDESC_COLLISION_COUNTSHIFT         ((uint32_t)3)
-
-/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
-#define  ETH_DMATXDESC_BUFFER2_SIZESHIFT           ((uint32_t)16)
-
-/* ETHERNET DMA Rx descriptors Frame Length Shift */
-#define  ETH_DMARXDESC_FRAME_LENGTHSHIFT           ((uint32_t)16)
-
-/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
-#define  ETH_DMARXDESC_BUFFER2_SIZESHIFT           ((uint32_t)16)
-
-/* ETHERNET DMA Rx descriptors Frame length Shift */
-#define  ETH_DMARXDESC_FRAMELENGTHSHIFT            ((uint32_t)16)
-
-/* ETHERNET MAC address offsets */
-#define ETH_MAC_ADDR_HBASE    (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40)  /* ETHERNET MAC address high offset */
-#define ETH_MAC_ADDR_LBASE    (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44)  /* ETHERNET MAC address low offset */
-
-/* ETHERNET MACMIIAR register Mask */
-#define ETH_MACMIIAR_CR_MASK    ((uint32_t)0xFFFFFFE3)
-
-/* ETHERNET MACCR register Mask */
-#define ETH_MACCR_CLEAR_MASK    ((uint32_t)0xFF20810F)  
-
-/* ETHERNET MACFCR register Mask */
-#define ETH_MACFCR_CLEAR_MASK   ((uint32_t)0x0000FF41)
-
-/* ETHERNET DMAOMR register Mask */
-#define ETH_DMAOMR_CLEAR_MASK   ((uint32_t)0xF8DE3F23)
-
-/* ETHERNET Remote Wake-up frame register length */
-#define ETH_WAKEUP_REGISTER_LENGTH      8
-
-/* ETHERNET Missed frames counter Shift */
-#define  ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT     17
- /**
-  * @}
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup ETH_Exported_Types ETH Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  HAL State structures definition  
-  */ 
-typedef enum
-{
-  HAL_ETH_STATE_RESET             = 0x00,    /*!< Peripheral not yet Initialized or disabled         */
-  HAL_ETH_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
-  HAL_ETH_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */
-  HAL_ETH_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */
-  HAL_ETH_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
-  HAL_ETH_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
-  HAL_ETH_STATE_BUSY_WR           = 0x42,    /*!< Write process is ongoing                           */
-  HAL_ETH_STATE_BUSY_RD           = 0x82,    /*!< Read process is ongoing                            */
-  HAL_ETH_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
-  HAL_ETH_STATE_ERROR             = 0x04     /*!< Reception process is ongoing                       */
-}HAL_ETH_StateTypeDef;
-
-/** 
-  * @brief  ETH Init Structure definition  
-  */
-
-typedef struct
-{
-  uint32_t             AutoNegotiation;           /*!< Selects or not the AutoNegotiation mode for the external PHY
-                                                           The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
-                                                           and the mode (half/full-duplex).
-                                                           This parameter can be a value of @ref ETH_AutoNegotiation */
-
-  uint32_t             Speed;                     /*!< Sets the Ethernet speed: 10/100 Mbps.
-                                                           This parameter can be a value of @ref ETH_Speed */
-
-  uint32_t             DuplexMode;                /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
-                                                           This parameter can be a value of @ref ETH_Duplex_Mode */
-  
-  uint16_t             PhyAddress;                /*!< Ethernet PHY address.
-                                                           This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
-  
-  uint8_t             *MACAddr;                   /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
-  
-  uint32_t             RxMode;                    /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
-                                                           This parameter can be a value of @ref ETH_Rx_Mode */
-  
-  uint32_t             ChecksumMode;              /*!< Selects if the checksum is check by hardware or by software. 
-                                                         This parameter can be a value of @ref ETH_Checksum_Mode */
-  
-  uint32_t             MediaInterface    ;               /*!< Selects the media-independent interface or the reduced media-independent interface. 
-                                                         This parameter can be a value of @ref ETH_Media_Interface */
-
-} ETH_InitTypeDef;
-
-
- /** 
-  * @brief  ETH MAC Configuration Structure definition  
-  */
-
-typedef struct
-{
-  uint32_t             Watchdog;                  /*!< Selects or not the Watchdog timer
-                                                           When enabled, the MAC allows no more then 2048 bytes to be received.
-                                                           When disabled, the MAC can receive up to 16384 bytes.
-                                                           This parameter can be a value of @ref ETH_Watchdog */  
-
-  uint32_t             Jabber;                    /*!< Selects or not Jabber timer
-                                                           When enabled, the MAC allows no more then 2048 bytes to be sent.
-                                                           When disabled, the MAC can send up to 16384 bytes.
-                                                           This parameter can be a value of @ref ETH_Jabber */
-
-  uint32_t             InterFrameGap;             /*!< Selects the minimum IFG between frames during transmission.
-                                                           This parameter can be a value of @ref ETH_Inter_Frame_Gap */   
-
-  uint32_t             CarrierSense;              /*!< Selects or not the Carrier Sense.
-                                                           This parameter can be a value of @ref ETH_Carrier_Sense */
-
-  uint32_t             ReceiveOwn;                /*!< Selects or not the ReceiveOwn,
-                                                           ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
-                                                           in Half-Duplex mode.
-                                                           This parameter can be a value of @ref ETH_Receive_Own */  
-
-  uint32_t             LoopbackMode;              /*!< Selects or not the internal MAC MII Loopback mode.
-                                                           This parameter can be a value of @ref ETH_Loop_Back_Mode */  
-
-  uint32_t             ChecksumOffload;           /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
-                                                           This parameter can be a value of @ref ETH_Checksum_Offload */    
-
-  uint32_t             RetryTransmission;         /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
-                                                           when a collision occurs (Half-Duplex mode).
-                                                           This parameter can be a value of @ref ETH_Retry_Transmission */
-
-  uint32_t             AutomaticPadCRCStrip;      /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
-                                                           This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ 
-
-  uint32_t             BackOffLimit;              /*!< Selects the BackOff limit value.
-                                                           This parameter can be a value of @ref ETH_Back_Off_Limit */
-
-  uint32_t             DeferralCheck;             /*!< Selects or not the deferral check function (Half-Duplex mode).
-                                                           This parameter can be a value of @ref ETH_Deferral_Check */                                                                                                        
-
-  uint32_t             ReceiveAll;                /*!< Selects or not all frames reception by the MAC (No filtering).
-                                                           This parameter can be a value of @ref ETH_Receive_All */   
-
-  uint32_t             SourceAddrFilter;          /*!< Selects the Source Address Filter mode.                                                           
-                                                           This parameter can be a value of @ref ETH_Source_Addr_Filter */                  
-
-  uint32_t             PassControlFrames;         /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)                                                          
-                                                           This parameter can be a value of @ref ETH_Pass_Control_Frames */ 
-
-  uint32_t             BroadcastFramesReception;  /*!< Selects or not the reception of Broadcast Frames.
-                                                           This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
-
-  uint32_t             DestinationAddrFilter;     /*!< Sets the destination filter mode for both unicast and multicast frames.
-                                                           This parameter can be a value of @ref ETH_Destination_Addr_Filter */ 
-
-  uint32_t             PromiscuousMode;           /*!< Selects or not the Promiscuous Mode
-                                                           This parameter can be a value of @ref ETH_Promiscuous_Mode */
-
-  uint32_t             MulticastFramesFilter;     /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
-                                                           This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ 
-
-  uint32_t             UnicastFramesFilter;       /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
-                                                           This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ 
-
-  uint32_t             HashTableHigh;             /*!< This field holds the higher 32 bits of Hash table.
-                                                           This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
-
-  uint32_t             HashTableLow;              /*!< This field holds the lower 32 bits of Hash table.
-                                                           This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF  */    
-
-  uint32_t             PauseTime;                 /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. 
-                                                           This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
-
-  uint32_t             ZeroQuantaPause;           /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
-                                                           This parameter can be a value of @ref ETH_Zero_Quanta_Pause */  
-
-  uint32_t             PauseLowThreshold;         /*!< This field configures the threshold of the PAUSE to be checked for
-                                                           automatic retransmission of PAUSE Frame.
-                                                           This parameter can be a value of @ref ETH_Pause_Low_Threshold */
-                                                           
-  uint32_t             UnicastPauseFrameDetect;   /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
-                                                           unicast address and unique multicast address).
-                                                           This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */  
-
-  uint32_t             ReceiveFlowControl;        /*!< Enables or disables the MAC to decode the received Pause frame and
-                                                           disable its transmitter for a specified time (Pause Time)
-                                                           This parameter can be a value of @ref ETH_Receive_Flow_Control */
-
-  uint32_t             TransmitFlowControl;       /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
-                                                           or the MAC back-pressure operation (Half-Duplex mode)
-                                                           This parameter can be a value of @ref ETH_Transmit_Flow_Control */     
-
-  uint32_t             VLANTagComparison;         /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
-                                                           comparison and filtering.
-                                                           This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ 
-
-  uint32_t             VLANTagIdentifier;         /*!< Holds the VLAN tag identifier for receive frames */
-
-} ETH_MACInitTypeDef;
-
-
-/** 
-  * @brief  ETH DMA Configuration Structure definition  
-  */
-
-typedef struct
-{
- uint32_t              DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
-                                                             This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ 
-
-  uint32_t             ReceiveStoreForward;         /*!< Enables or disables the Receive store and forward mode.
-                                                             This parameter can be a value of @ref ETH_Receive_Store_Forward */ 
-
-  uint32_t             FlushReceivedFrame;          /*!< Enables or disables the flushing of received frames.
-                                                             This parameter can be a value of @ref ETH_Flush_Received_Frame */ 
-
-  uint32_t             TransmitStoreForward;        /*!< Enables or disables Transmit store and forward mode.
-                                                             This parameter can be a value of @ref ETH_Transmit_Store_Forward */ 
-
-  uint32_t             TransmitThresholdControl;    /*!< Selects or not the Transmit Threshold Control.
-                                                             This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
-
-  uint32_t             ForwardErrorFrames;          /*!< Selects or not the forward to the DMA of erroneous frames.
-                                                             This parameter can be a value of @ref ETH_Forward_Error_Frames */
-
-  uint32_t             ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
-                                                             and length less than 64 bytes) including pad-bytes and CRC)
-                                                             This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
-
-  uint32_t             ReceiveThresholdControl;     /*!< Selects the threshold level of the Receive FIFO.
-                                                             This parameter can be a value of @ref ETH_Receive_Threshold_Control */
-
-  uint32_t             SecondFrameOperate;          /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
-                                                             frame of Transmit data even before obtaining the status for the first frame.
-                                                             This parameter can be a value of @ref ETH_Second_Frame_Operate */
-
-  uint32_t             AddressAlignedBeats;         /*!< Enables or disables the Address Aligned Beats.
-                                                             This parameter can be a value of @ref ETH_Address_Aligned_Beats */
-
-  uint32_t             FixedBurst;                  /*!< Enables or disables the AHB Master interface fixed burst transfers.
-                                                             This parameter can be a value of @ref ETH_Fixed_Burst */
-                       
-  uint32_t             RxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
-                                                             This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 
-
-  uint32_t             TxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
-                                                             This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
-
-  uint32_t             DescriptorSkipLength;        /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
-                                                             This parameter must be a number between Min_Data = 0 and Max_Data = 32 */                                                             
-
-  uint32_t             DMAArbitration;              /*!< Selects the DMA Tx/Rx arbitration.
-                                                             This parameter can be a value of @ref ETH_DMA_Arbitration */  
-} ETH_DMAInitTypeDef;
-
-
-/** 
-  * @brief  ETH DMA Descriptors data structure definition
-  */ 
-
-typedef struct  
-{
-  __IO uint32_t   Status;           /*!< Status */
-  
-  uint32_t   ControlBufferSize;     /*!< Control and Buffer1, Buffer2 lengths */
-  
-  uint32_t   Buffer1Addr;           /*!< Buffer1 address pointer */
-  
-  uint32_t   Buffer2NextDescAddr;   /*!< Buffer2 or next descriptor address pointer */
-
-} ETH_DMADescTypeDef;
-
-
-/** 
-  * @brief  Received Frame Informations structure definition
-  */ 
-typedef struct  
-{
-  ETH_DMADescTypeDef *FSRxDesc;          /*!< First Segment Rx Desc */
-  
-  ETH_DMADescTypeDef *LSRxDesc;          /*!< Last Segment Rx Desc */
-  
-  uint32_t  SegCount;                    /*!< Segment count */
-  
-  uint32_t length;                       /*!< Frame length */
-  
-  uint32_t buffer;                       /*!< Frame buffer */
-
-} ETH_DMARxFrameInfos;
-
-
-/** 
-  * @brief  ETH Handle Structure definition  
-  */
-  
-typedef struct
-{
-  ETH_TypeDef                *Instance;     /*!< Register base address       */
-  
-  ETH_InitTypeDef            Init;          /*!< Ethernet Init Configuration */
-  
-  uint32_t                   LinkStatus;    /*!< Ethernet link status        */
-  
-  ETH_DMADescTypeDef         *RxDesc;       /*!< Rx descriptor to Get        */
-  
-  ETH_DMADescTypeDef         *TxDesc;       /*!< Tx descriptor to Set        */
-  
-  ETH_DMARxFrameInfos        RxFrameInfos;  /*!< last Rx frame infos         */
-  
-  __IO HAL_ETH_StateTypeDef  State;         /*!< ETH communication state     */
-  
-  HAL_LockTypeDef            Lock;          /*!< ETH Lock                    */
-
-} ETH_HandleTypeDef;
-
- /**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup ETH_Exported_Constants ETH Exported Constants
-  * @{
-  */
-
-/** @defgroup ETH_Buffers_setting ETH Buffers setting
-  * @{
-  */ 
-#define ETH_MAX_PACKET_SIZE    ((uint32_t)1524)    /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
-#define ETH_HEADER               ((uint32_t)14)    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
-#define ETH_CRC                   ((uint32_t)4)    /*!< Ethernet CRC */
-#define ETH_EXTRA                 ((uint32_t)2)    /*!< Extra bytes in some cases */   
-#define ETH_VLAN_TAG                  ((uint32_t)4)    /*!< optional 802.1q VLAN Tag */
-#define ETH_MIN_ETH_PAYLOAD          ((uint32_t)46)    /*!< Minimum Ethernet payload size */
-#define ETH_MAX_ETH_PAYLOAD        ((uint32_t)1500)    /*!< Maximum Ethernet payload size */
-#define ETH_JUMBO_FRAME_PAYLOAD    ((uint32_t)9000)    /*!< Jumbo frame payload size */      
-
- /* Ethernet driver receive buffers are organized in a chained linked-list, when
-    an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
-    to the driver receive buffers memory.
-
-    Depending on the size of the received ethernet packet and the size of 
-    each ethernet driver receive buffer, the received packet can take one or more
-    ethernet driver receive buffer. 
-
-    In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE 
-    and the total count of the driver receive buffers ETH_RXBUFNB.
-
-    The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as 
-    example, they can be reconfigured in the application layer to fit the application 
-    needs */ 
-
-/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
-   packet */
-#ifndef ETH_RX_BUF_SIZE
- #define ETH_RX_BUF_SIZE         ETH_MAX_PACKET_SIZE 
-#endif
-
-/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ 
-#ifndef ETH_RXBUFNB
- #define ETH_RXBUFNB             ((uint32_t)5     /*  5 Rx buffers of size ETH_RX_BUF_SIZE */
-#endif
-
-
- /* Ethernet driver transmit buffers are organized in a chained linked-list, when
-    an ethernet packet is transmitted, Tx-DMA will transfer the packet from the 
-    driver transmit buffers memory to the TxFIFO.
-
-    Depending on the size of the Ethernet packet to be transmitted and the size of 
-    each ethernet driver transmit buffer, the packet to be transmitted can take 
-    one or more ethernet driver transmit buffer. 
-
-    In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE 
-    and the total count of the driver transmit buffers ETH_TXBUFNB.
-
-    The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as 
-    example, they can be reconfigured in the application layer to fit the application 
-    needs */ 
-
-/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
-   packet */
-#ifndef ETH_TX_BUF_SIZE 
- #define ETH_TX_BUF_SIZE         ETH_MAX_PACKET_SIZE
-#endif
-
-/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ 
-#ifndef ETH_TXBUFNB
- #define ETH_TXBUFNB             ((uint32_t)5      /* 5  Tx buffers of size ETH_TX_BUF_SIZE */
-#endif
-
- /**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
-  * @{
-  */
-
-/*
-   DMA Tx Desciptor
-  -----------------------------------------------------------------------------------------------
-  TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
-  -----------------------------------------------------------------------------------------------
-  TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
-  -----------------------------------------------------------------------------------------------
-  TDES2 |                         Buffer1 Address [31:0]                                         |
-  -----------------------------------------------------------------------------------------------
-  TDES3 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |
-  -----------------------------------------------------------------------------------------------
-*/
-
-/** 
-  * @brief  Bit definition of TDES0 register: DMA Tx descriptor status register
-  */ 
-#define ETH_DMATXDESC_OWN                     ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMATXDESC_IC                      ((uint32_t)0x40000000)  /*!< Interrupt on Completion */
-#define ETH_DMATXDESC_LS                      ((uint32_t)0x20000000)  /*!< Last Segment */
-#define ETH_DMATXDESC_FS                      ((uint32_t)0x10000000)  /*!< First Segment */
-#define ETH_DMATXDESC_DC                      ((uint32_t)0x08000000)  /*!< Disable CRC */
-#define ETH_DMATXDESC_DP                      ((uint32_t)0x04000000)  /*!< Disable Padding */
-#define ETH_DMATXDESC_TTSE                    ((uint32_t)0x02000000)  /*!< Transmit Time Stamp Enable */
-#define ETH_DMATXDESC_CIC                     ((uint32_t)0x00C00000)  /*!< Checksum Insertion Control: 4 cases */
-#define ETH_DMATXDESC_CIC_BYPASS              ((uint32_t)0x00000000)  /*!< Do Nothing: Checksum Engine is bypassed */ 
-#define ETH_DMATXDESC_CIC_IPV4HEADER          ((uint32_t)0x00400000)  /*!< IPV4 header Checksum Insertion */ 
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT  ((uint32_t)0x00800000)  /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL     ((uint32_t)0x00C00000)  /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 
-#define ETH_DMATXDESC_TER                     ((uint32_t)0x00200000)  /*!< Transmit End of Ring */
-#define ETH_DMATXDESC_TCH                     ((uint32_t)0x00100000)  /*!< Second Address Chained */
-#define ETH_DMATXDESC_TTSS                    ((uint32_t)0x00020000)  /*!< Tx Time Stamp Status */
-#define ETH_DMATXDESC_IHE                     ((uint32_t)0x00010000)  /*!< IP Header Error */
-#define ETH_DMATXDESC_ES                      ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
-#define ETH_DMATXDESC_JT                      ((uint32_t)0x00004000)  /*!< Jabber Timeout */
-#define ETH_DMATXDESC_FF                      ((uint32_t)0x00002000)  /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
-#define ETH_DMATXDESC_PCE                     ((uint32_t)0x00001000)  /*!< Payload Checksum Error */
-#define ETH_DMATXDESC_LCA                     ((uint32_t)0x00000800)  /*!< Loss of Carrier: carrier lost during transmission */
-#define ETH_DMATXDESC_NC                      ((uint32_t)0x00000400)  /*!< No Carrier: no carrier signal from the transceiver */
-#define ETH_DMATXDESC_LCO                     ((uint32_t)0x00000200)  /*!< Late Collision: transmission aborted due to collision */
-#define ETH_DMATXDESC_EC                      ((uint32_t)0x00000100)  /*!< Excessive Collision: transmission aborted after 16 collisions */
-#define ETH_DMATXDESC_VF                      ((uint32_t)0x00000080)  /*!< VLAN Frame */
-#define ETH_DMATXDESC_CC                      ((uint32_t)0x00000078)  /*!< Collision Count */
-#define ETH_DMATXDESC_ED                      ((uint32_t)0x00000004)  /*!< Excessive Deferral */
-#define ETH_DMATXDESC_UF                      ((uint32_t)0x00000002)  /*!< Underflow Error: late data arrival from the memory */
-#define ETH_DMATXDESC_DB                      ((uint32_t)0x00000001)  /*!< Deferred Bit */
-
-/** 
-  * @brief  Bit definition of TDES1 register
-  */ 
-#define ETH_DMATXDESC_TBS2  ((uint32_t)0x1FFF0000)  /*!< Transmit Buffer2 Size */
-#define ETH_DMATXDESC_TBS1  ((uint32_t)0x00001FFF)  /*!< Transmit Buffer1 Size */
-
-/** 
-  * @brief  Bit definition of TDES2 register
-  */ 
-#define ETH_DMATXDESC_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */
-
-/** 
-  * @brief  Bit definition of TDES3 register
-  */ 
-#define ETH_DMATXDESC_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */
-
-/**
-  * @}
-  */ 
-/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor 
-  * @{
-  */
-
-/*
-  DMA Rx Descriptor
-  --------------------------------------------------------------------------------------------------------------------
-  RDES0 | OWN(31) |                                             Status [30:0]                                          |
-  ---------------------------------------------------------------------------------------------------------------------
-  RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
-  ---------------------------------------------------------------------------------------------------------------------
-  RDES2 |                                       Buffer1 Address [31:0]                                                 |
-  ---------------------------------------------------------------------------------------------------------------------
-  RDES3 |                          Buffer2 Address [31:0] / Next Descriptor Address [31:0]                             |
-  ---------------------------------------------------------------------------------------------------------------------
-*/
-
-/** 
-  * @brief  Bit definition of RDES0 register: DMA Rx descriptor status register
-  */ 
-#define ETH_DMARXDESC_OWN         ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine  */
-#define ETH_DMARXDESC_AFM         ((uint32_t)0x40000000)  /*!< DA Filter Fail for the rx frame  */
-#define ETH_DMARXDESC_FL          ((uint32_t)0x3FFF0000)  /*!< Receive descriptor frame length  */
-#define ETH_DMARXDESC_ES          ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
-#define ETH_DMARXDESC_DE          ((uint32_t)0x00004000)  /*!< Descriptor error: no more descriptors for receive frame  */
-#define ETH_DMARXDESC_SAF         ((uint32_t)0x00002000)  /*!< SA Filter Fail for the received frame */
-#define ETH_DMARXDESC_LE          ((uint32_t)0x00001000)  /*!< Frame size not matching with length field */
-#define ETH_DMARXDESC_OE          ((uint32_t)0x00000800)  /*!< Overflow Error: Frame was damaged due to buffer overflow */
-#define ETH_DMARXDESC_VLAN        ((uint32_t)0x00000400)  /*!< VLAN Tag: received frame is a VLAN frame */
-#define ETH_DMARXDESC_FS          ((uint32_t)0x00000200)  /*!< First descriptor of the frame  */
-#define ETH_DMARXDESC_LS          ((uint32_t)0x00000100)  /*!< Last descriptor of the frame  */ 
-#define ETH_DMARXDESC_IPV4HCE     ((uint32_t)0x00000080)  /*!< IPC Checksum Error: Rx Ipv4 header checksum error   */    
-#define ETH_DMARXDESC_LC          ((uint32_t)0x00000040)  /*!< Late collision occurred during reception   */
-#define ETH_DMARXDESC_FT          ((uint32_t)0x00000020)  /*!< Frame type - Ethernet, otherwise 802.3    */
-#define ETH_DMARXDESC_RWT         ((uint32_t)0x00000010)  /*!< Receive Watchdog Timeout: watchdog timer expired during reception    */
-#define ETH_DMARXDESC_RE          ((uint32_t)0x00000008)  /*!< Receive error: error reported by MII interface  */
-#define ETH_DMARXDESC_DBE         ((uint32_t)0x00000004)  /*!< Dribble bit error: frame contains non int multiple of 8 bits  */
-#define ETH_DMARXDESC_CE          ((uint32_t)0x00000002)  /*!< CRC error */
-#define ETH_DMARXDESC_MAMPCE      ((uint32_t)0x00000001)  /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
-
-/** 
-  * @brief  Bit definition of RDES1 register
-  */ 
-#define ETH_DMARXDESC_DIC   ((uint32_t)0x80000000)  /*!< Disable Interrupt on Completion */
-#define ETH_DMARXDESC_RBS2  ((uint32_t)0x1FFF0000)  /*!< Receive Buffer2 Size */
-#define ETH_DMARXDESC_RER   ((uint32_t)0x00008000)  /*!< Receive End of Ring */
-#define ETH_DMARXDESC_RCH   ((uint32_t)0x00004000)  /*!< Second Address Chained */
-#define ETH_DMARXDESC_RBS1  ((uint32_t)0x00001FFF)  /*!< Receive Buffer1 Size */
-
-/** 
-  * @brief  Bit definition of RDES2 register  
-  */ 
-#define ETH_DMARXDESC_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */
-
-/** 
-  * @brief  Bit definition of RDES3 register  
-  */ 
-#define ETH_DMARXDESC_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */
-
-/**
-  * @}
-  */
- /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation 
-  * @{
-  */ 
-#define ETH_AUTONEGOTIATION_ENABLE     ((uint32_t)0x00000001)
-#define ETH_AUTONEGOTIATION_DISABLE    ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-/** @defgroup ETH_Speed ETH Speed 
-  * @{
-  */ 
-#define ETH_SPEED_10M        ((uint32_t)0x00000000)
-#define ETH_SPEED_100M       ((uint32_t)0x00004000)
-
-/**
-  * @}
-  */
-/** @defgroup ETH_Duplex_Mode ETH Duplex Mode 
-  * @{
-  */ 
-#define ETH_MODE_FULLDUPLEX       ((uint32_t)0x00000800)
-#define ETH_MODE_HALFDUPLEX       ((uint32_t)0x00000000)
-/**
-  * @}
-  */
-/** @defgroup ETH_Rx_Mode ETH Rx Mode 
-  * @{
-  */ 
-#define ETH_RXPOLLING_MODE      ((uint32_t)0x00000000)
-#define ETH_RXINTERRUPT_MODE    ((uint32_t)0x00000001)
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
-  * @{
-  */ 
-#define ETH_CHECKSUM_BY_HARDWARE      ((uint32_t)0x00000000)
-#define ETH_CHECKSUM_BY_SOFTWARE      ((uint32_t)0x00000001)
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Media_Interface ETH Media Interface
-  * @{
-  */ 
-#define ETH_MEDIA_INTERFACE_MII       ((uint32_t)0x00000000)
-#define ETH_MEDIA_INTERFACE_RMII      ((uint32_t)AFIO_MAPR_MII_RMII_SEL)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Watchdog ETH Watchdog
-  * @{
-  */ 
-#define ETH_WATCHDOG_ENABLE       ((uint32_t)0x00000000)
-#define ETH_WATCHDOG_DISABLE      ((uint32_t)0x00800000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Jabber ETH Jabber 
-  * @{
-  */ 
-#define ETH_JABBER_ENABLE    ((uint32_t)0x00000000)
-#define ETH_JABBER_DISABLE   ((uint32_t)0x00400000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap 
-  * @{
-  */ 
-#define ETH_INTERFRAMEGAP_96BIT   ((uint32_t)0x00000000)  /*!< minimum IFG between frames during transmission is 96Bit */
-#define ETH_INTERFRAMEGAP_88BIT   ((uint32_t)0x00020000)  /*!< minimum IFG between frames during transmission is 88Bit */
-#define ETH_INTERFRAMEGAP_80BIT   ((uint32_t)0x00040000)  /*!< minimum IFG between frames during transmission is 80Bit */
-#define ETH_INTERFRAMEGAP_72BIT   ((uint32_t)0x00060000)  /*!< minimum IFG between frames during transmission is 72Bit */
-#define ETH_INTERFRAMEGAP_64BIT   ((uint32_t)0x00080000)  /*!< minimum IFG between frames during transmission is 64Bit */
-#define ETH_INTERFRAMEGAP_56BIT   ((uint32_t)0x000A0000)  /*!< minimum IFG between frames during transmission is 56Bit */
-#define ETH_INTERFRAMEGAP_48BIT   ((uint32_t)0x000C0000)  /*!< minimum IFG between frames during transmission is 48Bit */
-#define ETH_INTERFRAMEGAP_40BIT   ((uint32_t)0x000E0000)  /*!< minimum IFG between frames during transmission is 40Bit */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
-  * @{
-  */ 
-#define ETH_CARRIERSENCE_ENABLE   ((uint32_t)0x00000000)
-#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Receive_Own ETH Receive Own 
-  * @{
-  */ 
-#define ETH_RECEIVEOWN_ENABLE     ((uint32_t)0x00000000)
-#define ETH_RECEIVEOWN_DISABLE   ((uint32_t)0x00002000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
-  * @{
-  */ 
-#define ETH_LOOPBACKMODE_ENABLE        ((uint32_t)0x00001000)
-#define ETH_LOOPBACKMODE_DISABLE       ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
-  * @{
-  */ 
-#define ETH_CHECKSUMOFFLAOD_ENABLE     ((uint32_t)0x00000400)
-#define ETH_CHECKSUMOFFLAOD_DISABLE    ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
-  * @{
-  */ 
-#define ETH_RETRYTRANSMISSION_ENABLE   ((uint32_t)0x00000000)
-#define ETH_RETRYTRANSMISSION_DISABLE  ((uint32_t)0x00000200)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
-  * @{
-  */ 
-#define ETH_AUTOMATICPADCRCSTRIP_ENABLE     ((uint32_t)0x00000080)
-#define ETH_AUTOMATICPADCRCSTRIP_DISABLE    ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
-  * @{
-  */ 
-#define ETH_BACKOFFLIMIT_10  ((uint32_t)0x00000000)
-#define ETH_BACKOFFLIMIT_8   ((uint32_t)0x00000020)
-#define ETH_BACKOFFLIMIT_4   ((uint32_t)0x00000040)
-#define ETH_BACKOFFLIMIT_1   ((uint32_t)0x00000060)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Deferral_Check ETH Deferral Check
-  * @{
-  */
-#define ETH_DEFFERRALCHECK_ENABLE       ((uint32_t)0x00000010)
-#define ETH_DEFFERRALCHECK_DISABLE      ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Receive_All ETH Receive All
-  * @{
-  */ 
-#define ETH_RECEIVEALL_ENABLE     ((uint32_t)0x80000000)
-#define ETH_RECEIVEAll_DISABLE    ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
-  * @{
-  */ 
-#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE       ((uint32_t)0x00000200)
-#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE      ((uint32_t)0x00000300)
-#define ETH_SOURCEADDRFILTER_DISABLE             ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
-  * @{
-  */ 
-#define ETH_PASSCONTROLFRAMES_BLOCKALL                ((uint32_t)0x00000040)  /*!< MAC filters all control frames from reaching the application */
-#define ETH_PASSCONTROLFRAMES_FORWARDALL              ((uint32_t)0x00000080)  /*!< MAC forwards all control frames to application even if they fail the Address Filter */
-#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0)  /*!< MAC forwards control frames that pass the Address Filter. */ 
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
-  * @{
-  */ 
-#define ETH_BROADCASTFRAMESRECEPTION_ENABLE     ((uint32_t)0x00000000)
-#define ETH_BROADCASTFRAMESRECEPTION_DISABLE    ((uint32_t)0x00000020)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
-  * @{
-  */ 
-#define ETH_DESTINATIONADDRFILTER_NORMAL    ((uint32_t)0x00000000)
-#define ETH_DESTINATIONADDRFILTER_INVERSE   ((uint32_t)0x00000008)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
-  * @{
-  */ 
-#define ETH_PROMISCUOUS_MODE_ENABLE     ((uint32_t)0x00000001)
-#define ETH_PROMISCUOUS_MODE_DISABLE    ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
-  * @{
-  */ 
-#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE    ((uint32_t)0x00000404)
-#define ETH_MULTICASTFRAMESFILTER_HASHTABLE           ((uint32_t)0x00000004)
-#define ETH_MULTICASTFRAMESFILTER_PERFECT             ((uint32_t)0x00000000)
-#define ETH_MULTICASTFRAMESFILTER_NONE                ((uint32_t)0x00000010)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
-  * @{
-  */ 
-#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
-#define ETH_UNICASTFRAMESFILTER_HASHTABLE        ((uint32_t)0x00000002)
-#define ETH_UNICASTFRAMESFILTER_PERFECT          ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
-  * @{
-  */ 
-#define ETH_ZEROQUANTAPAUSE_ENABLE     ((uint32_t)0x00000000)
-#define ETH_ZEROQUANTAPAUSE_DISABLE    ((uint32_t)0x00000080)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
-  * @{
-  */ 
-#define ETH_PAUSELOWTHRESHOLD_MINUS4        ((uint32_t)0x00000000)  /*!< Pause time minus 4 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS28       ((uint32_t)0x00000010)  /*!< Pause time minus 28 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS144      ((uint32_t)0x00000020)  /*!< Pause time minus 144 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS256      ((uint32_t)0x00000030)  /*!< Pause time minus 256 slot times */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
-  * @{
-  */ 
-#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE  ((uint32_t)0x00000008)
-#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
-  * @{
-  */ 
-#define ETH_RECEIVEFLOWCONTROL_ENABLE       ((uint32_t)0x00000004)
-#define ETH_RECEIVEFLOWCONTROL_DISABLE      ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
-  * @{
-  */ 
-#define ETH_TRANSMITFLOWCONTROL_ENABLE      ((uint32_t)0x00000002)
-#define ETH_TRANSMITFLOWCONTROL_DISABLE     ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
-  * @{
-  */ 
-#define ETH_VLANTAGCOMPARISON_12BIT    ((uint32_t)0x00010000)
-#define ETH_VLANTAGCOMPARISON_16BIT    ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_MAC_addresses ETH MAC addresses
-  * @{
-  */ 
-#define ETH_MAC_ADDRESS0     ((uint32_t)0x00000000)
-#define ETH_MAC_ADDRESS1     ((uint32_t)0x00000008)
-#define ETH_MAC_ADDRESS2     ((uint32_t)0x00000010)
-#define ETH_MAC_ADDRESS3     ((uint32_t)0x00000018)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_MAC_Addresses_Filter_SA_DA ETH MAC Addresses Filter SA DA 
-  * @{
-  */ 
-#define ETH_MAC_ADDRESSFILTER_SA       ((uint32_t)0x00000000)
-#define ETH_MAC_ADDRESSFILTER_DA       ((uint32_t)0x00000008)
-/**
-  * @}
-  */
-
-/** @defgroup ETH_MAC_Addresses_Filter_Mask_Bytes ETH_MAC Addresses Filter Mask Bytes
-  * @{
-  */ 
-#define ETH_MAC_ADDRESSMASK_BYTE6      ((uint32_t)0x20000000)  /*!< Mask MAC Address high reg bits [15:8] */
-#define ETH_MAC_ADDRESSMASK_BYTE5      ((uint32_t)0x10000000)  /*!< Mask MAC Address high reg bits [7:0] */
-#define ETH_MAC_ADDRESSMASK_BYTE4      ((uint32_t)0x08000000)  /*!< Mask MAC Address low reg bits [31:24] */
-#define ETH_MAC_ADDRESSMASK_BYTE3      ((uint32_t)0x04000000)  /*!< Mask MAC Address low reg bits [23:16] */
-#define ETH_MAC_ADDRESSMASK_BYTE2      ((uint32_t)0x02000000)  /*!< Mask MAC Address low reg bits [15:8] */
-#define ETH_MAC_ADDRESSMASK_BYTE1      ((uint32_t)0x01000000)  /*!< Mask MAC Address low reg bits [70] */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_MAC_Debug_Flags ETH MAC Debug Flags
-  * @{
-  */ 
-#define ETH_MAC_TXFIFO_FULL          ((uint32_t)0x02000000)  /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY      ((uint32_t)0x01000000)  /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE  ((uint32_t)0x00400000)  /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE     ((uint32_t)0x00000000)  /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ     ((uint32_t)0x00100000)  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING  ((uint32_t)0x00200000)  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING  ((uint32_t)0x00300000)  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE     ((uint32_t)0x00080000)  /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            ((uint32_t)0x00000000)  /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         ((uint32_t)0x00020000)  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   ((uint32_t)0x00040000)  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    ((uint32_t)0x00060000)  /* MAC transmit frame controller: Transferring input frame for transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE      ((uint32_t)0x00010000)  /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY             ((uint32_t)0x00000000)  /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD   ((uint32_t)0x00000100)  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD   ((uint32_t)0x00000200)  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
-#define ETH_MAC_RXFIFO_FULL              ((uint32_t)0x00000300)  /* Rx FIFO fill level: full */
-#define ETH_MAC_READCONTROLLER_IDLE            ((uint32_t)0x00000060)  /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA    ((uint32_t)0x00000060)  /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS  ((uint32_t)0x00000060)  /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#define ETH_MAC_READCONTROLLER_FLUSHING        ((uint32_t)0x00000060)  /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE     ((uint32_t)0x00000010)  /* Rx FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE    ((uint32_t)0x00000000)  /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE  ((uint32_t)0x00000002)  /* MAC small FIFO read controller active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004)  /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE    ((uint32_t)0x00000006)  /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   ((uint32_t)0x00000001)  /* MAC MII receive protocol engine active */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
-  * @{
-  */ 
-#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE   ((uint32_t)0x00000000)
-#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE  ((uint32_t)0x04000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward 
-  * @{
-  */ 
-#define ETH_RECEIVESTOREFORWARD_ENABLE      ((uint32_t)0x02000000)
-#define ETH_RECEIVESTOREFORWARD_DISABLE     ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
-  * @{
-  */ 
-#define ETH_FLUSHRECEIVEDFRAME_ENABLE       ((uint32_t)0x00000000)
-#define ETH_FLUSHRECEIVEDFRAME_DISABLE      ((uint32_t)0x01000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
-  * @{
-  */ 
-#define ETH_TRANSMITSTOREFORWARD_ENABLE     ((uint32_t)0x00200000)
-#define ETH_TRANSMITSTOREFORWARD_DISABLE    ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
-  * @{
-  */ 
-#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES     ((uint32_t)0x00000000)  /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES    ((uint32_t)0x00004000)  /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES    ((uint32_t)0x00008000)  /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES    ((uint32_t)0x0000C000)  /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES     ((uint32_t)0x00010000)  /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES     ((uint32_t)0x00014000)  /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES     ((uint32_t)0x00018000)  /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES     ((uint32_t)0x0001C000)  /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
-  * @{
-  */ 
-#define ETH_FORWARDERRORFRAMES_ENABLE       ((uint32_t)0x00000080)
-#define ETH_FORWARDERRORFRAMES_DISABLE      ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
-  * @{
-  */ 
-#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE   ((uint32_t)0x00000040)
-#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE  ((uint32_t)0x00000000)     
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
-  * @{
-  */ 
-#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES      ((uint32_t)0x00000000)  /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES      ((uint32_t)0x00000008)  /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES      ((uint32_t)0x00000010)  /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES     ((uint32_t)0x00000018)  /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
-  * @{
-  */ 
-#define ETH_SECONDFRAMEOPERARTE_ENABLE       ((uint32_t)0x00000004)
-#define ETH_SECONDFRAMEOPERARTE_DISABLE      ((uint32_t)0x00000000)  
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
-  * @{
-  */ 
-#define ETH_ADDRESSALIGNEDBEATS_ENABLE      ((uint32_t)0x02000000)
-#define ETH_ADDRESSALIGNEDBEATS_DISABLE     ((uint32_t)0x00000000) 
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
-  * @{
-  */ 
-#define ETH_FIXEDBURST_ENABLE     ((uint32_t)0x00010000)
-#define ETH_FIXEDBURST_DISABLE    ((uint32_t)0x00000000) 
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA_Burst Length
-  * @{
-  */ 
-#define ETH_RXDMABURSTLENGTH_1BEAT          ((uint32_t)0x00020000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
-#define ETH_RXDMABURSTLENGTH_2BEAT          ((uint32_t)0x00040000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
-#define ETH_RXDMABURSTLENGTH_4BEAT          ((uint32_t)0x00080000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_RXDMABURSTLENGTH_8BEAT          ((uint32_t)0x00100000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_RXDMABURSTLENGTH_16BEAT         ((uint32_t)0x00200000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_RXDMABURSTLENGTH_32BEAT         ((uint32_t)0x00400000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT    ((uint32_t)0x01020000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT    ((uint32_t)0x01040000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT   ((uint32_t)0x01080000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT   ((uint32_t)0x01100000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT   ((uint32_t)0x01200000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT  ((uint32_t)0x01400000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
- 
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
-  * @{
-  */ 
-#define ETH_TXDMABURSTLENGTH_1BEAT          ((uint32_t)0x00000100)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-#define ETH_TXDMABURSTLENGTH_2BEAT          ((uint32_t)0x00000200)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-#define ETH_TXDMABURSTLENGTH_4BEAT          ((uint32_t)0x00000400)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-#define ETH_TXDMABURSTLENGTH_8BEAT          ((uint32_t)0x00000800)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-#define ETH_TXDMABURSTLENGTH_16BEAT         ((uint32_t)0x00001000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-#define ETH_TXDMABURSTLENGTH_32BEAT         ((uint32_t)0x00002000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT    ((uint32_t)0x01000100)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT    ((uint32_t)0x01000200)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT   ((uint32_t)0x01000400)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT   ((uint32_t)0x01000800)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT   ((uint32_t)0x01001000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT  ((uint32_t)0x01002000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
-  * @{
-  */ 
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1   ((uint32_t)0x00000000)
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1   ((uint32_t)0x00004000)
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1   ((uint32_t)0x00008000)
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1   ((uint32_t)0x0000C000)
-#define ETH_DMAARBITRATION_RXPRIORTX             ((uint32_t)0x00000002)
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_Tx_Descriptor_Segment ETH DMA Tx Descriptor Segment
-  * @{
-  */ 
-#define ETH_DMATXDESC_LASTSEGMENTS      ((uint32_t)0x40000000)  /*!< Last Segment */
-#define ETH_DMATXDESC_FIRSTSEGMENT      ((uint32_t)0x20000000)  /*!< First Segment */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_Tx_Descriptor_Checksum_Insertion_Control ETH DMA Tx Descriptor Checksum Insertion Control
-  * @{
-  */ 
-#define ETH_DMATXDESC_CHECKSUMBYPASS             ((uint32_t)0x00000000)   /*!< Checksum engine bypass */
-#define ETH_DMATXDESC_CHECKSUMIPV4HEADER         ((uint32_t)0x00400000)   /*!< IPv4 header checksum insertion  */
-#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT  ((uint32_t)0x00800000)   /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
-#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL     ((uint32_t)0x00C00000)   /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_Rx_Descriptor_Buffers ETH DMA Rx Descriptor Buffers
-  * @{
-  */ 
-#define ETH_DMARXDESC_BUFFER1     ((uint32_t)0x00000000)  /*!< DMA Rx Desc Buffer1 */
-#define ETH_DMARXDESC_BUFFER2     ((uint32_t)0x00000001)  /*!< DMA Rx Desc Buffer2 */
- 
-/**
-  * @}
-  */
-
-/** @defgroup ETH_PMT_Flags ETH PMT Flags
-  * @{
-  */ 
-#define ETH_PMT_FLAG_WUFFRPR      ((uint32_t)0x80000000)  /*!< Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_PMT_FLAG_WUFR         ((uint32_t)0x00000040)  /*!< Wake-Up Frame Received */
-#define ETH_PMT_FLAG_MPR          ((uint32_t)0x00000020)  /*!< Magic Packet Received */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
-  * @{
-  */ 
-#define ETH_MMC_IT_TGF       ((uint32_t)0x00200000)  /*!< When Tx good frame counter reaches half the maximum value */
-#define ETH_MMC_IT_TGFMSC    ((uint32_t)0x00008000)  /*!< When Tx good multi col counter reaches half the maximum value */
-#define ETH_MMC_IT_TGFSC     ((uint32_t)0x00004000)  /*!< When Tx good single col counter reaches half the maximum value */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
-  * @{
-  */
-#define ETH_MMC_IT_RGUF      ((uint32_t)0x10020000)  /*!< When Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMC_IT_RFAE      ((uint32_t)0x10000040)  /*!< When Rx alignment error counter reaches half the maximum value */
-#define ETH_MMC_IT_RFCE      ((uint32_t)0x10000020)  /*!< When Rx crc error counter reaches half the maximum value */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_MAC_Flags ETH MAC Flags
-  * @{
-  */ 
-#define ETH_MAC_FLAG_TST     ((uint32_t)0x00000200)  /*!< Time stamp trigger flag (on MAC) */
-#define ETH_MAC_FLAG_MMCT    ((uint32_t)0x00000040)  /*!< MMC transmit flag  */
-#define ETH_MAC_FLAG_MMCR    ((uint32_t)0x00000020)  /*!< MMC receive flag */
-#define ETH_MAC_FLAG_MMC     ((uint32_t)0x00000010)  /*!< MMC flag (on MAC) */
-#define ETH_MAC_FLAG_PMT     ((uint32_t)0x00000008)  /*!< PMT flag (on MAC) */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_Flags ETH DMA Flags
-  * @{
-  */ 
-#define ETH_DMA_FLAG_TST               ((uint32_t)0x20000000)  /*!< Time-stamp trigger interrupt (on DMA) */
-#define ETH_DMA_FLAG_PMT               ((uint32_t)0x10000000)  /*!< PMT interrupt (on DMA) */
-#define ETH_DMA_FLAG_MMC               ((uint32_t)0x08000000)  /*!< MMC interrupt (on DMA) */
-#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000)  /*!< Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMA_FLAG_READWRITEERROR    ((uint32_t)0x01000000)  /*!< Error bits 0-write trnsf, 1-read transfr */
-#define ETH_DMA_FLAG_ACCESSERROR       ((uint32_t)0x02000000)  /*!< Error bits 0-data buffer, 1-desc. access */
-#define ETH_DMA_FLAG_NIS               ((uint32_t)0x00010000)  /*!< Normal interrupt summary flag */
-#define ETH_DMA_FLAG_AIS               ((uint32_t)0x00008000)  /*!< Abnormal interrupt summary flag */
-#define ETH_DMA_FLAG_ER                ((uint32_t)0x00004000)  /*!< Early receive flag */
-#define ETH_DMA_FLAG_FBE               ((uint32_t)0x00002000)  /*!< Fatal bus error flag */
-#define ETH_DMA_FLAG_ET                ((uint32_t)0x00000400)  /*!< Early transmit flag */
-#define ETH_DMA_FLAG_RWT               ((uint32_t)0x00000200)  /*!< Receive watchdog timeout flag */
-#define ETH_DMA_FLAG_RPS               ((uint32_t)0x00000100)  /*!< Receive process stopped flag */
-#define ETH_DMA_FLAG_RBU               ((uint32_t)0x00000080)  /*!< Receive buffer unavailable flag */
-#define ETH_DMA_FLAG_R                 ((uint32_t)0x00000040)  /*!< Receive flag */
-#define ETH_DMA_FLAG_TU                ((uint32_t)0x00000020)  /*!< Underflow flag */
-#define ETH_DMA_FLAG_RO                ((uint32_t)0x00000010)  /*!< Overflow flag */
-#define ETH_DMA_FLAG_TJT               ((uint32_t)0x00000008)  /*!< Transmit jabber timeout flag */
-#define ETH_DMA_FLAG_TBU               ((uint32_t)0x00000004)  /*!< Transmit buffer unavailable flag */
-#define ETH_DMA_FLAG_TPS               ((uint32_t)0x00000002)  /*!< Transmit process stopped flag */
-#define ETH_DMA_FLAG_T                 ((uint32_t)0x00000001)  /*!< Transmit flag */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
-  * @{
-  */ 
-#define ETH_MAC_IT_TST       ((uint32_t)0x00000200)  /*!< Time stamp trigger interrupt (on MAC) */
-#define ETH_MAC_IT_MMCT      ((uint32_t)0x00000040)  /*!< MMC transmit interrupt */
-#define ETH_MAC_IT_MMCR      ((uint32_t)0x00000020)  /*!< MMC receive interrupt */
-#define ETH_MAC_IT_MMC       ((uint32_t)0x00000010)  /*!< MMC interrupt (on MAC) */
-#define ETH_MAC_IT_PMT       ((uint32_t)0x00000008)  /*!< PMT interrupt (on MAC) */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
-  * @{
-  */ 
-#define ETH_DMA_IT_TST       ((uint32_t)0x20000000)  /*!< Time-stamp trigger interrupt (on DMA) */
-#define ETH_DMA_IT_PMT       ((uint32_t)0x10000000)  /*!< PMT interrupt (on DMA) */
-#define ETH_DMA_IT_MMC       ((uint32_t)0x08000000)  /*!< MMC interrupt (on DMA) */
-#define ETH_DMA_IT_NIS       ((uint32_t)0x00010000)  /*!< Normal interrupt summary */
-#define ETH_DMA_IT_AIS       ((uint32_t)0x00008000)  /*!< Abnormal interrupt summary */
-#define ETH_DMA_IT_ER        ((uint32_t)0x00004000)  /*!< Early receive interrupt */
-#define ETH_DMA_IT_FBE       ((uint32_t)0x00002000)  /*!< Fatal bus error interrupt */
-#define ETH_DMA_IT_ET        ((uint32_t)0x00000400)  /*!< Early transmit interrupt */
-#define ETH_DMA_IT_RWT       ((uint32_t)0x00000200)  /*!< Receive watchdog timeout interrupt */
-#define ETH_DMA_IT_RPS       ((uint32_t)0x00000100)  /*!< Receive process stopped interrupt */
-#define ETH_DMA_IT_RBU       ((uint32_t)0x00000080)  /*!< Receive buffer unavailable interrupt */
-#define ETH_DMA_IT_R         ((uint32_t)0x00000040)  /*!< Receive interrupt */
-#define ETH_DMA_IT_TU        ((uint32_t)0x00000020)  /*!< Underflow interrupt */
-#define ETH_DMA_IT_RO        ((uint32_t)0x00000010)  /*!< Overflow interrupt */
-#define ETH_DMA_IT_TJT       ((uint32_t)0x00000008)  /*!< Transmit jabber timeout interrupt */
-#define ETH_DMA_IT_TBU       ((uint32_t)0x00000004)  /*!< Transmit buffer unavailable interrupt */
-#define ETH_DMA_IT_TPS       ((uint32_t)0x00000002)  /*!< Transmit process stopped interrupt */
-#define ETH_DMA_IT_T         ((uint32_t)0x00000001)  /*!< Transmit interrupt */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state 
-  * @{
-  */ 
-#define ETH_DMA_TRANSMITPROCESS_STOPPED     ((uint32_t)0x00000000)  /*!< Stopped - Reset or Stop Tx Command issued */
-#define ETH_DMA_TRANSMITPROCESS_FETCHING    ((uint32_t)0x00100000)  /*!< Running - fetching the Tx descriptor */
-#define ETH_DMA_TRANSMITPROCESS_WAITING     ((uint32_t)0x00200000)  /*!< Running - waiting for status */
-#define ETH_DMA_TRANSMITPROCESS_READING     ((uint32_t)0x00300000)  /*!< Running - reading the data from host memory */
-#define ETH_DMA_TRANSMITPROCESS_SUSPENDED   ((uint32_t)0x00600000)  /*!< Suspended - Tx Descriptor unavailable */
-#define ETH_DMA_TRANSMITPROCESS_CLOSING     ((uint32_t)0x00700000)  /*!< Running - closing Rx descriptor */
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state 
-  * @{
-  */ 
-#define ETH_DMA_RECEIVEPROCESS_STOPPED      ((uint32_t)0x00000000)  /*!< Stopped - Reset or Stop Rx Command issued */
-#define ETH_DMA_RECEIVEPROCESS_FETCHING     ((uint32_t)0x00020000)  /*!< Running - fetching the Rx descriptor */
-#define ETH_DMA_RECEIVEPROCESS_WAITING      ((uint32_t)0x00060000)  /*!< Running - waiting for packet */
-#define ETH_DMA_RECEIVEPROCESS_SUSPENDED    ((uint32_t)0x00080000)  /*!< Suspended - Rx Descriptor unavailable */
-#define ETH_DMA_RECEIVEPROCESS_CLOSING      ((uint32_t)0x000A0000)  /*!< Running - closing descriptor */
-#define ETH_DMA_RECEIVEPROCESS_QUEUING      ((uint32_t)0x000E0000)  /*!< Running - queuing the receive frame into host memory */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_overflow ETH DMA overflow
-  * @{
-  */ 
-#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER      ((uint32_t)0x10000000)  /*!< Overflow bit for FIFO overflow counter */
-#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000)  /*!< Overflow bit for missed frame counter */
-
-/**
-  * @}
-  */ 
-
-  /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
-  * @{
-  */ 
-#define ETH_EXTI_LINE_WAKEUP              ((uint32_t)0x00080000)  /*!< External interrupt line 19 Connected to the ETH EXTI Line */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup ETH_Exported_Macros ETH Exported Macros
- *  @brief macros to handle interrupts and specific clock configurations
- * @{
- */
- 
-/** @brief Reset ETH handle state
-  * @param  __HANDLE__: specifies the ETH handle.
-  * @retval None
-  */
-#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
-
-/** 
-  * @brief  Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
-  * @param  __HANDLE__: ETH Handle
-  * @param  __FLAG__: specifies the flag of TDES0 to check .
-  * @retval the ETH_DMATxDescFlag (SET or RESET).
-  */
-#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
-
-/**
-  * @brief  Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
-  * @param  __HANDLE__: ETH Handle
-  * @param  __FLAG__: specifies the flag of RDES0 to check.
-  * @retval the ETH_DMATxDescFlag (SET or RESET).
-  */
-#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
-
-/**
-  * @brief  Enables the specified DMA Rx Desc receive interrupt.
-  * @param  __HANDLE__: ETH Handle
-  * @retval None
-  */
-#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__)                          ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
-
-/**
-  * @brief  Disables the specified DMA Rx Desc receive interrupt.
-  * @param  __HANDLE__: ETH Handle
-  * @retval None
-  */
-#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__)                         ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
-
-/**
-  * @brief  Set the specified DMA Rx Desc Own bit.
-  * @param  __HANDLE__: ETH Handle
-  * @retval None
-  */
-#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__)                           ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
-
-/**
-  * @brief  Returns the specified ETHERNET DMA Tx Desc collision count.
-  * @param  __HANDLE__: ETH Handle                     
-  * @retval The Transmit descriptor collision counter value.
-  */
-#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__)                   (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
-
-/**
-  * @brief  Set the specified DMA Tx Desc Own bit.
-  * @param  __HANDLE__: ETH Handle
-  * @retval None
-  */
-#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__)                       ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
-
-/**
-  * @brief  Enables the specified DMA Tx Desc Transmit interrupt.
-  * @param  __HANDLE__: ETH Handle                   
-  * @retval None
-  */
-#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
-
-/**
-  * @brief  Disables the specified DMA Tx Desc Transmit interrupt.
-  * @param  __HANDLE__: ETH Handle             
-  * @retval None
-  */
-#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
-
-/**
-  * @brief  Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
-  * @param  __HANDLE__: ETH Handle  
-  * @param  __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
-  *   This parameter can be one of the following values:
-  *     @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
-  *     @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
-  *     @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
-  *     @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header                                                                
-  * @retval None
-  */
-#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__)     ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
-
-/**
-  * @brief  Enables the DMA Tx Desc CRC.
-  * @param  __HANDLE__: ETH Handle 
-  * @retval None
-  */
-#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
-
-/**
-  * @brief  Disables the DMA Tx Desc CRC.
-  * @param  __HANDLE__: ETH Handle 
-  * @retval None
-  */
-#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__)                         ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
-
-/**
-  * @brief  Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
-  * @param  __HANDLE__: ETH Handle 
-  * @retval None
-  */
-#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__)            ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
-
-/**
-  * @brief  Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
-  * @param  __HANDLE__: ETH Handle 
-  * @retval None
-  */
-#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__)           ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
-
-/** 
- * @brief  Enables the specified ETHERNET MAC interrupts.
-  * @param  __HANDLE__   : ETH Handle
-  * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
-  *   enabled or disabled.
-  *   This parameter can be any combination of the following values:
-  *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 
-  *     @arg ETH_MAC_IT_PMT : PMT interrupt 
-  * @retval None
-  */
-#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disables the specified ETHERNET MAC interrupts.
-  * @param  __HANDLE__   : ETH Handle
-  * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
-  *   enabled or disabled.
-  *   This parameter can be any combination of the following values:
-  *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 
-  *     @arg ETH_MAC_IT_PMT : PMT interrupt
-  * @retval None
-  */
-#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Initiate a Pause Control Frame (Full-duplex only).
-  * @param  __HANDLE__: ETH Handle
-  * @retval None
-  */
-#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__)              ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
-
-/**
-  * @brief  Checks whether the ETHERNET flow control busy bit is set or not.
-  * @param  __HANDLE__: ETH Handle
-  * @retval The new state of flow control busy status bit (SET or RESET).
-  */
-#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__)               (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
-
-/**
-  * @brief  Enables the MAC Back Pressure operation activation (Half-duplex only).
-  * @param  __HANDLE__: ETH Handle
-  * @retval None
-  */
-#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__)          ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
-
-/**
-  * @brief  Disables the MAC BackPressure operation activation (Half-duplex only).
-  * @param  __HANDLE__: ETH Handle
-  * @retval None
-  */
-#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__)         ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
-
-/**
-  * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
-  * @param  __HANDLE__: ETH Handle
-  * @param  __FLAG__: specifies the flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg ETH_MAC_FLAG_TST  : Time stamp trigger flag   
-  *     @arg ETH_MAC_FLAG_MMCT : MMC transmit flag  
-  *     @arg ETH_MAC_FLAG_MMCR : MMC receive flag   
-  *     @arg ETH_MAC_FLAG_MMC  : MMC flag  
-  *     @arg ETH_MAC_FLAG_PMT  : PMT flag  
-  * @retval The state of ETHERNET MAC flag.
-  */
-#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
-
-/** 
-  * @brief  Enables the specified ETHERNET DMA interrupts.
-  * @param  __HANDLE__   : ETH Handle
-  * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
-  *   enabled @ref ETH_DMA_Interrupts
-  * @retval None
-  */
-#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
-
-/**
-  * @brief  Disables the specified ETHERNET DMA interrupts.
-  * @param  __HANDLE__   : ETH Handle
-  * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
-  *   disabled. @ref ETH_DMA_Interrupts
-  * @retval None
-  */
-#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Clears the ETHERNET DMA IT pending bit.
-  * @param  __HANDLE__   : ETH Handle
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
-  * @retval None
-  */
-#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
-
-/**
-  * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
-* @param  __HANDLE__: ETH Handle
-  * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
-  * @retval The new state of ETH_DMA_FLAG (SET or RESET).
-  */
-#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
-
-/**
-  * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
-  * @param  __HANDLE__: ETH Handle
-  * @param  __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
-  * @retval The new state of ETH_DMA_FLAG (SET or RESET).
-  */
-#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)                 ((__HANDLE__)->Instance->DMASR = (__FLAG__))
-
-/**
-  * @brief  Checks whether the specified ETHERNET DMA overflow flag is set or not.
-  * @param  __HANDLE__: ETH Handle
-  * @param  __OVERFLOW__: specifies the DMA overflow flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
-  *     @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
-  * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
-  */
-#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__)       (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
-
-/**
-  * @brief  Set the DMA Receive status watchdog timer register value
-  * @param  __HANDLE__: ETH Handle
-  * @param  __VALUE__: DMA Receive status watchdog timer register value   
-  * @retval None
-  */
-#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__)       ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
-
-/** 
-  * @brief  Enables any unicast packet filtered by the MAC address
-  *   recognition to be a wake-up frame.
-  * @param  __HANDLE__: ETH Handle.
-  * @retval None
-  */
-#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
-
-/**
-  * @brief  Disables any unicast packet filtered by the MAC address
-  *   recognition to be a wake-up frame.
-  * @param  __HANDLE__: ETH Handle.
-  * @retval None
-  */
-#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
-
-/**
-  * @brief  Enables the MAC Wake-Up Frame Detection.
-  * @param  __HANDLE__: ETH Handle.
-  * @retval None
-  */
-#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
-
-/**
-  * @brief  Disables the MAC Wake-Up Frame Detection.
-  * @param  __HANDLE__: ETH Handle.
-  * @retval None
-  */
-#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__)             ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
-
-/**
-  * @brief  Enables the MAC Magic Packet Detection.
-  * @param  __HANDLE__: ETH Handle.
-  * @retval None
-  */
-#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
-
-/**
-  * @brief  Disables the MAC Magic Packet Detection.
-  * @param  __HANDLE__: ETH Handle.
-  * @retval None
-  */
-#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__)             ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
-
-/**
-  * @brief  Enables the MAC Power Down.
-  * @param  __HANDLE__: ETH Handle
-  * @retval None
-  */
-#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
-
-/**
-  * @brief  Disables the MAC Power Down.
-  * @param  __HANDLE__: ETH Handle
-  * @retval None
-  */
-#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
-
-/**
-  * @brief  Checks whether the specified ETHERNET PMT flag is set or not.
-  * @param  __HANDLE__: ETH Handle.
-  * @param  __FLAG__: specifies the flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset 
-  *     @arg ETH_PMT_FLAG_WUFR    : Wake-Up Frame Received 
-  *     @arg ETH_PMT_FLAG_MPR     : Magic Packet Received
-  * @retval The new state of ETHERNET PMT Flag (SET or RESET).
-  */
-#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__)               (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
-
-/** 
-  * @brief  Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
-  * @param   __HANDLE__: ETH Handle.
-  * @retval None
-  */
-#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__)                     ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
-
-/**
-  * @brief  Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
-  * @param  __HANDLE__: ETH Handle.
-  * @retval None
-  */
-#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__)                     do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
-                                                                          (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
-
-/**
-  * @brief  Enables the MMC Counter Freeze.
-  * @param  __HANDLE__: ETH Handle.
-  * @retval None
-  */
-#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__)                  ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
-
-/**
-  * @brief  Disables the MMC Counter Freeze.
-  * @param  __HANDLE__: ETH Handle.
-  * @retval None
-  */
-#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__)                 ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
-
-/**
-  * @brief  Enables the MMC Reset On Read.
-  * @param  __HANDLE__: ETH Handle.
-  * @retval None
-  */
-#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
-
-/**
-  * @brief  Disables the MMC Reset On Read.
-  * @param  __HANDLE__: ETH Handle.
-  * @retval None
-  */
-#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
-
-/**
-  * @brief  Enables the MMC Counter Stop Rollover.
-  * @param  __HANDLE__: ETH Handle.
-  * @retval None
-  */
-#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__)            ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
-
-/**
-  * @brief  Disables the MMC Counter Stop Rollover.
-  * @param  __HANDLE__: ETH Handle.
-  * @retval None
-  */
-#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__)           ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
-
-/**
-  * @brief  Resets the MMC Counters.
-  * @param   __HANDLE__: ETH Handle.
-  * @retval None
-  */
-#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__)                         ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
-
-/**
-  * @brief  Enables the specified ETHERNET MMC Rx interrupts.
-  * @param   __HANDLE__: ETH Handle.
-  * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
-  *   This parameter can be one of the following values:  
-  *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value 
-  *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value 
-  *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
-  * @retval None
-  */
-#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__)               (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
-/**
-  * @brief  Disables the specified ETHERNET MMC Rx interrupts.
-  * @param   __HANDLE__: ETH Handle.
-  * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
-  *   This parameter can be one of the following values: 
-  *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value 
-  *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value 
-  *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
-  * @retval None
-  */
-#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__)              (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
-/**
-  * @brief  Enables the specified ETHERNET MMC Tx interrupts.
-  * @param   __HANDLE__: ETH Handle.
-  * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
-  *   This parameter can be one of the following values:  
-  *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value 
-  *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 
-  *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 
-  * @retval None
-  */
-#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__)            ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
-
-/**
-  * @brief  Disables the specified ETHERNET MMC Tx interrupts.
-  * @param   __HANDLE__: ETH Handle.
-  * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
-  *   This parameter can be one of the following values:  
-  *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value 
-  *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 
-  *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 
-  * @retval None
-  */
-#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__)           ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
-
-/**
-  * @brief  Enables the ETH External interrupt line.
-  * @retval None
-  */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
-
-/**
-  * @brief  Disables the ETH External interrupt line.
-  * @retval None
-  */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
-
-/**
-  * @brief Enable event on ETH External event line.
-  * @retval None.
-  */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT()  EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
-
-/**
-  * @brief Disable event on ETH External event line
-  * @retval None.
-  */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
-
-/**
-  * @brief  Get flag of the ETH External interrupt line.
-  * @retval None
-  */
-#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
-
-/**
-  * @brief  Clear flag of the ETH External interrupt line.
-  * @retval None
-  */
-#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
-
-/**
-  * @brief  Enables rising edge trigger to the ETH External interrupt line.
-  * @retval None
-  */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER()  EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
-                                                            
-/**
-  * @brief  Disables the rising edge trigger to the ETH External interrupt line.
-  * @retval None
-  */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER()  EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)                                                          
-
-/**
-  * @brief  Enables falling edge trigger to the ETH External interrupt line.
-  * @retval None
-  */                                                      
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER()  EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
-
-/**
-  * @brief  Disables falling edge trigger to the ETH External interrupt line.
-  * @retval None
-  */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER()  EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
-                                                  
-
-/**
-  * @brief  Enables rising/falling edge trigger to the ETH External interrupt line.
-  * @retval None
-  */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER()   \
-                        do{                                    \
-                            EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
-                            EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
-                          } while(0)
-
-/**
-  * @brief  Disables rising/falling edge trigger to the ETH External interrupt line.
-  * @retval None
-  */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER()     \
-                        do{                                       \
-                            EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
-                            EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
-                          } while(0)
-
-/**
-  * @brief Generate a Software interrupt on selected EXTI line.
-  * @retval None.
-  */
-#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT()                  EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup ETH_Exported_Functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-
-/** @addtogroup ETH_Exported_Functions_Group1
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
-void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
-void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
-HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
-
-/**
-  * @}
-  */
-
-/* IO operation functions  ****************************************************/
-
-/** @addtogroup ETH_Exported_Functions_Group2
-  * @{
-  */
-HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
-HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
-/* Communication with PHY functions*/
-HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
-HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
- /* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
-void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
- /* Callback in non blocking modes (Interrupt) */
-void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
-void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
-void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
-
-/**
-  * @}
-  */
-
-/* Peripheral Control functions  **********************************************/
-
-/** @addtogroup ETH_Exported_Functions_Group3
-  * @{
-  */
-HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
-HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
-/**
-  * @}
-  */ 
-  
-/* Peripheral State functions  ************************************************/
-
-/** @addtogroup ETH_Exported_Functions_Group4
-  * @{
-  */
-HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */ 
-  
-/**
-  * @}
-  */
-
-#endif /* STM32F107xC */
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_ETH_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_flash.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,348 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_flash.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of Flash HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_FLASH_H
-#define __STM32F1xx_HAL_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-   
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASH
-  * @{
-  */
-  
-/** @addtogroup FLASH_Private_Constants
-  * @{
-  */
-#define FLASH_TIMEOUT_VALUE   ((uint32_t)50000)/* 50 s */
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_Private_Macros
-  * @{
-  */
-
-#define IS_FLASH_TYPEPROGRAM(VALUE)  (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
-                                      ((VALUE) == FLASH_TYPEPROGRAM_WORD)     || \
-                                      ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))  
-
-#if   defined(FLASH_ACR_LATENCY)
-#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
-                                       ((__LATENCY__) == FLASH_LATENCY_1) || \
-                                       ((__LATENCY__) == FLASH_LATENCY_2))
-
-#else
-#define IS_FLASH_LATENCY(__LATENCY__)   ((__LATENCY__) == FLASH_LATENCY_0)
-#endif /* FLASH_ACR_LATENCY */
-/**
-  * @}
-  */  
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup FLASH_Exported_Types FLASH Exported Types
-  * @{
-  */  
-
-
-/**
-  * @brief  FLASH Procedure structure definition
-  */
-typedef enum 
-{
-  FLASH_PROC_NONE              = 0, 
-  FLASH_PROC_PAGEERASE         = 1,
-  FLASH_PROC_MASSERASE         = 2,
-  FLASH_PROC_PROGRAMHALFWORD   = 3,
-  FLASH_PROC_PROGRAMWORD       = 4,
-  FLASH_PROC_PROGRAMDOUBLEWORD = 5
-} FLASH_ProcedureTypeDef;
-
-/** 
-  * @brief  FLASH handle Structure definition  
-  */
-typedef struct
-{
-  __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
-  
-  __IO uint32_t               DataRemaining;    /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
-
-  __IO uint32_t               Address;          /*!< Internal variable to save address selected for program or erase */
-
-  __IO uint64_t               Data;             /*!< Internal variable to save data to be programmed */
-
-  HAL_LockTypeDef             Lock;             /*!< FLASH locking object                */
-
-  __IO uint32_t               ErrorCode;        /*!< FLASH error code                    
-                                                     This parameter can be a value of @ref FLASH_Error_Codes  */
-} FLASH_ProcessTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
-  * @{
-  */  
-
-/** @defgroup FLASH_Error_Codes FLASH Error Codes
-  * @{
-  */
-
-#define HAL_FLASH_ERROR_NONE      ((uint32_t)0x00)  /*!< No error */
-#define HAL_FLASH_ERROR_PROG      ((uint32_t)0x01)  /*!< Programming error */
-#define HAL_FLASH_ERROR_WRP       ((uint32_t)0x02)  /*!< Write protection error */
-#define HAL_FLASH_ERROR_OPTV      ((uint32_t)0x04)  /*!< Option validity error */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Type_Program FLASH Type Program
-  * @{
-  */ 
-#define FLASH_TYPEPROGRAM_HALFWORD   ((uint32_t)0x01)  /*!<Program a half-word (16-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAM_WORD       ((uint32_t)0x02)  /*!<Program a word (32-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03)  /*!<Program a double word (64-bit) at a specified address*/
-
-/**
-  * @}
-  */
-
-#if   defined(FLASH_ACR_LATENCY)
-/** @defgroup FLASH_Latency FLASH Latency
-  * @{
-  */
-#define FLASH_LATENCY_0            ((uint32_t)0x00000000)    /*!< FLASH Zero Latency cycle */
-#define FLASH_LATENCY_1            FLASH_ACR_LATENCY_0       /*!< FLASH One Latency cycle */
-#define FLASH_LATENCY_2            FLASH_ACR_LATENCY_1       /*!< FLASH Two Latency cycles */
-
-/**
-  * @}
-  */
-
-#else
-/** @defgroup FLASH_Latency FLASH Latency
-  * @{
-  */
-#define FLASH_LATENCY_0            ((uint32_t)0x00000000)    /*!< FLASH Zero Latency cycle */
-
-/**
-  * @}
-  */
-
-#endif /* FLASH_ACR_LATENCY */
-/**
-  * @}
-  */  
-  
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
- *  @brief macros to control FLASH features 
- *  @{
- */
- 
-/** @defgroup FLASH_Half_Cycle FLASH Half Cycle
- *  @brief macros to handle FLASH half cycle
- * @{
- */
-
-/**
-  * @brief  Enable the FLASH half cycle access.
-  * @note   half cycle access can only be used with a low-frequency clock of less than
-            8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
-  * @retval None
-  */
-#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE()  (FLASH->ACR |= FLASH_ACR_HLFCYA)
-
-/**
-  * @brief  Disable the FLASH half cycle access.
-  * @note   half cycle access can only be used with a low-frequency clock of less than
-            8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
-  * @retval None
-  */
-#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
-
-/**
-  * @}
-  */
-
-#if defined(FLASH_ACR_LATENCY)
-/** @defgroup FLASH_EM_Latency FLASH Latency
- *  @brief macros to handle FLASH Latency
- * @{
- */ 
-  
-/**
-  * @brief  Set the FLASH Latency.
-  * @param  __LATENCY__ FLASH Latency                   
-  *         The value of this parameter depend on device used within the same series
-  * @retval None
-  */ 
-#define __HAL_FLASH_SET_LATENCY(__LATENCY__)    (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
-
-
-/**
-  * @brief  Get the FLASH Latency.
-  * @retval FLASH Latency                   
-  *         The value of this parameter depend on device used within the same series
-  */ 
-#define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
-
-/**
-  * @}
-  */
-
-#endif /* FLASH_ACR_LATENCY */
-/** @defgroup FLASH_Prefetch FLASH Prefetch
- *  @brief macros to handle FLASH Prefetch buffer
- * @{
- */   
-/**
-  * @brief  Enable the FLASH prefetch buffer.
-  * @retval None
-  */ 
-#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    (FLASH->ACR |= FLASH_ACR_PRFTBE)
-
-/**
-  * @brief  Disable the FLASH prefetch buffer.
-  * @retval None
-  */
-#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */ 
-
-/* Include FLASH HAL Extended module */
-#include "stm32f1xx_hal_flash_ex.h"  
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASH_Exported_Functions
-  * @{
-  */
-  
-/** @addtogroup FLASH_Exported_Functions_Group1
-  * @{
-  */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-
-/* FLASH IRQ handler function */
-void       HAL_FLASH_IRQHandler(void);
-/* Callbacks in non blocking modes */ 
-void       HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
-void       HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_Exported_Functions_Group2
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_FLASH_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_Lock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State and Error functions ***************************************/
-uint32_t HAL_FLASH_GetError(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private function -------------------------------------------------*/
-/** @addtogroup FLASH_Private_Functions
- * @{
- */
-void                    FLASH_PageErase(uint32_t PageAddress);
-HAL_StatusTypeDef       FLASH_WaitForLastOperation(uint32_t Timeout);
-#if defined(FLASH_BANK2_END)
-HAL_StatusTypeDef       FLASH_WaitForLastOperationBank2(uint32_t Timeout);
-#endif /* FLASH_BANK2_END */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_FLASH_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_flash_ex.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,804 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_flash_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of Flash HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_FLASH_EX_H
-#define __STM32F1xx_HAL_FLASH_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASHEx
-  * @{
-  */ 
-
-/** @addtogroup FLASHEx_Private_Constants
-  * @{
-  */
-
-#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFFF7E0)
-#define OBR_REG_INDEX            ((uint32_t)1)
-#define SR_FLAG_MASK             ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))
-
-/**
-  * @}
-  */  
-
-/** @addtogroup FLASHEx_Private_Macros
-  * @{
-  */
-
-#define IS_FLASH_TYPEERASE(VALUE)   (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))
-
-#define IS_OPTIONBYTE(VALUE)        (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))
-
-#define IS_WRPSTATE(VALUE)          (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))  
-
-#define IS_OB_RDP_LEVEL(LEVEL)      (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))
-
-#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) 
-
-#define IS_OB_IWDG_SOURCE(SOURCE)   (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-
-#define IS_OB_STOP_SOURCE(SOURCE)   (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
-
-#define IS_OB_STDBY_SOURCE(SOURCE)  (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
-
-#if defined(FLASH_BANK2_END)
-#define IS_OB_BOOT1(BOOT1)         (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
-#endif /* FLASH_BANK2_END */
-
-/* Low Density */
-#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF) : \
-                                           ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFF))
-#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
-
-/* Medium Density */
-#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF) : \
-                                           (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF) : \
-                                           (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF) : \
-                                           ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFF))))
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
-
-/* High Density */
-#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFF) : \
-                                           (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFF) : \
-                                           ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF)))
-#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
-
-/* XL Density */
-#if defined(FLASH_BANK2_END)
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFF) : \
-                                           ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFF))
-#endif /* FLASH_BANK2_END */
-
-/* Connectivity Line */
-#if (defined(STM32F105xC) || defined(STM32F107xC))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF) : \
-                                           (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) ==  0x80) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF) : \
-                                           ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF)))
-#endif /* STM32F105xC || STM32F107xC */
-
-#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
-
-#if defined(FLASH_BANK2_END)
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)  || \
-                             ((BANK) == FLASH_BANK_2)  || \
-                             ((BANK) == FLASH_BANK_BOTH))
-#else
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
-#endif /* FLASH_BANK2_END */
-
-/* Low Density */
-#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)  (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? \
-                                            ((ADDRESS) <= FLASH_BANK1_END) :  ((ADDRESS) <= 0x08003FFF)))
-
-#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
-
-/* Medium Density */
-#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? \
-                                           ((ADDRESS) <= FLASH_BANK1_END) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? \
-                                           ((ADDRESS) <= 0x0800FFFF) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? \
-                                           ((ADDRESS) <= 0x08007FFF) :  ((ADDRESS) <= 0x08003FFF)))))
-
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
-
-/* High Density */
-#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200) ? \
-                                           ((ADDRESS) <= FLASH_BANK1_END) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180) ? \
-                                           ((ADDRESS) <= 0x0805FFFF) :  ((ADDRESS) <= 0x0803FFFF))))
-
-#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
-
-/* XL Density */
-#if defined(FLASH_BANK2_END)
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400) ? \
-                                           ((ADDRESS) <= FLASH_BANK2_END) :  ((ADDRESS) <= 0x080BFFFF)))
-
-#endif /* FLASH_BANK2_END */
-
-/* Connectivity Line */
-#if (defined(STM32F105xC) || defined(STM32F107xC))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? \
-                                           ((ADDRESS) <= FLASH_BANK1_END) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? \
-                                           ((ADDRESS) <= 0x0801FFFF) :  ((ADDRESS) <= 0x0800FFFF))))
-
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
-  * @}
-  */  
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
-  * @{
-  */  
-
-/**
-  * @brief  FLASH Erase structure definition
-  */
-typedef struct
-{
-  uint32_t TypeErase;   /*!< TypeErase: Mass erase or page erase.
-                             This parameter can be a value of @ref FLASHEx_Type_Erase */
-  
-  uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.
-                             This parameter must be a value of @ref FLASHEx_Banks */    
-  
-  uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
-                             This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END 
-                             (x = 1 or 2 depending on devices)*/
-  
-  uint32_t NbPages;     /*!< NbPages: Number of pagess to be erased.
-                             This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
-                                                          
-} FLASH_EraseInitTypeDef;
-
-/**
-  * @brief  FLASH Options bytes program structure definition
-  */
-typedef struct
-{
-  uint32_t OptionType;  /*!< OptionType: Option byte to be configured.
-                             This parameter can be a value of @ref FLASHEx_OB_Type */
-
-  uint32_t WRPState;    /*!< WRPState: Write protection activation or deactivation.
-                             This parameter can be a value of @ref FLASHEx_OB_WRP_State */
-
-  uint32_t WRPPage;     /*!< WRPPage: specifies the page(s) to be write protected
-                             This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
-
-  uint32_t Banks;        /*!< Select banks for WRP activation/deactivation of all sectors.
-                              This parameter must be a value of @ref FLASHEx_Banks */ 
-    
-  uint8_t RDPLevel;     /*!< RDPLevel: Set the read protection level..
-                             This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
-
-#if defined(FLASH_BANK2_END)
-  uint8_t USERConfig;   /*!< USERConfig: Program the FLASH User Option Byte: 
-                             IWDG / STOP / STDBY / BOOT1
-                             This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, 
-                             @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */
-#else
-  uint8_t USERConfig;   /*!< USERConfig: Program the FLASH User Option Byte: 
-                             IWDG / STOP / STDBY
-                             This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, 
-                             @ref FLASHEx_OB_nRST_STDBY */
-#endif /* FLASH_BANK2_END */
-
-  uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
-                             This parameter can be a value of @ref FLASHEx_OB_Data_Address */
-  
-  uint8_t DATAData;     /*!< DATAData: Data to be stored in the option byte DATA
-                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
-} FLASH_OBProgramInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
-  * @{
-  */  
-
-/** @defgroup FLASHEx_Constants FLASH Constants
-  * @{
-  */ 
-
-/** @defgroup FLASHEx_Page_Size Page Size
-  * @{
-  */ 
-#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
-#define FLASH_PAGE_SIZE          ((uint32_t)0x400)
-#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
-       /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
-
-#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC))
-#define FLASH_PAGE_SIZE          ((uint32_t)0x800)
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
-       /* STM32F101xG || STM32F103xG */ 
-       /* STM32F105xC || STM32F107xC */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Type_Erase Type Erase
-  * @{
-  */ 
-#define FLASH_TYPEERASE_PAGES     ((uint32_t)0x00)  /*!<Pages erase only*/
-#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x02)  /*!<Flash mass erase activation*/
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Banks Banks
-  * @{
-  */
-#if defined(FLASH_BANK2_END)
-#define FLASH_BANK_1     ((uint32_t)1) /*!< Bank 1   */
-#define FLASH_BANK_2     ((uint32_t)2) /*!< Bank 2   */
-#define FLASH_BANK_BOTH  ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
-
-#else
-#define FLASH_BANK_1     ((uint32_t)1) /*!< Bank 1   */
-#endif
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
-  * @{
-  */ 
-
-/** @defgroup FLASHEx_OB_Type Option Bytes Type
-  * @{
-  */
-#define OPTIONBYTE_WRP            ((uint32_t)0x01)  /*!<WRP option byte configuration*/
-#define OPTIONBYTE_RDP            ((uint32_t)0x02)  /*!<RDP option byte configuration*/
-#define OPTIONBYTE_USER           ((uint32_t)0x04)  /*!<USER option byte configuration*/
-#define OPTIONBYTE_DATA           ((uint32_t)0x08)  /*!<DATA option byte configuration*/
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
-  * @{
-  */ 
-#define OB_WRPSTATE_DISABLE       ((uint32_t)0x00)  /*!<Disable the write protection of the desired pages*/
-#define OB_WRPSTATE_ENABLE        ((uint32_t)0x01)  /*!<Enable the write protection of the desired pagess*/
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_OB_Write_Protection Option Bytes Write Protection
-  * @{
-  */
-/* STM32 Low and Medium density devices */
-#if  defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) \
-  || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) \
-  || defined(STM32F103xB)
-#define OB_WRP_PAGES0TO3               ((uint32_t)0x00000001) /*!< Write protection of page 0 to 3 */
-#define OB_WRP_PAGES4TO7               ((uint32_t)0x00000002) /*!< Write protection of page 4 to 7 */
-#define OB_WRP_PAGES8TO11              ((uint32_t)0x00000004) /*!< Write protection of page 8 to 11 */
-#define OB_WRP_PAGES12TO15             ((uint32_t)0x00000008) /*!< Write protection of page 12 to 15 */
-#define OB_WRP_PAGES16TO19             ((uint32_t)0x00000010) /*!< Write protection of page 16 to 19 */
-#define OB_WRP_PAGES20TO23             ((uint32_t)0x00000020) /*!< Write protection of page 20 to 23 */
-#define OB_WRP_PAGES24TO27             ((uint32_t)0x00000040) /*!< Write protection of page 24 to 27 */
-#define OB_WRP_PAGES28TO31             ((uint32_t)0x00000080) /*!< Write protection of page 28 to 31 */
-#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
-       /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
-       
-/* STM32 Medium-density devices */
-#if  defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
-#define OB_WRP_PAGES32TO35             ((uint32_t)0x00000100) /*!< Write protection of page 32 to 35 */
-#define OB_WRP_PAGES36TO39             ((uint32_t)0x00000200) /*!< Write protection of page 36 to 39 */
-#define OB_WRP_PAGES40TO43             ((uint32_t)0x00000400) /*!< Write protection of page 40 to 43 */
-#define OB_WRP_PAGES44TO47             ((uint32_t)0x00000800) /*!< Write protection of page 44 to 47 */
-#define OB_WRP_PAGES48TO51             ((uint32_t)0x00001000) /*!< Write protection of page 48 to 51 */
-#define OB_WRP_PAGES52TO55             ((uint32_t)0x00002000) /*!< Write protection of page 52 to 55 */
-#define OB_WRP_PAGES56TO59             ((uint32_t)0x00004000) /*!< Write protection of page 56 to 59 */
-#define OB_WRP_PAGES60TO63             ((uint32_t)0x00008000) /*!< Write protection of page 60 to 63 */
-#define OB_WRP_PAGES64TO67             ((uint32_t)0x00010000) /*!< Write protection of page 64 to 67 */
-#define OB_WRP_PAGES68TO71             ((uint32_t)0x00020000) /*!< Write protection of page 68 to 71 */
-#define OB_WRP_PAGES72TO75             ((uint32_t)0x00040000) /*!< Write protection of page 72 to 75 */
-#define OB_WRP_PAGES76TO79             ((uint32_t)0x00080000) /*!< Write protection of page 76 to 79 */
-#define OB_WRP_PAGES80TO83             ((uint32_t)0x00100000) /*!< Write protection of page 80 to 83 */
-#define OB_WRP_PAGES84TO87             ((uint32_t)0x00200000) /*!< Write protection of page 84 to 87 */
-#define OB_WRP_PAGES88TO91             ((uint32_t)0x00400000) /*!< Write protection of page 88 to 91 */
-#define OB_WRP_PAGES92TO95             ((uint32_t)0x00800000) /*!< Write protection of page 92 to 95 */
-#define OB_WRP_PAGES96TO99             ((uint32_t)0x01000000) /*!< Write protection of page 96 to 99 */
-#define OB_WRP_PAGES100TO103           ((uint32_t)0x02000000) /*!< Write protection of page 100 to 103 */
-#define OB_WRP_PAGES104TO107           ((uint32_t)0x04000000) /*!< Write protection of page 104 to 107 */
-#define OB_WRP_PAGES108TO111           ((uint32_t)0x08000000) /*!< Write protection of page 108 to 111 */
-#define OB_WRP_PAGES112TO115           ((uint32_t)0x10000000) /*!< Write protection of page 112 to 115 */
-#define OB_WRP_PAGES116TO119           ((uint32_t)0x20000000) /*!< Write protection of page 115 to 119 */
-#define OB_WRP_PAGES120TO123           ((uint32_t)0x40000000) /*!< Write protection of page 120 to 123 */
-#define OB_WRP_PAGES124TO127           ((uint32_t)0x80000000) /*!< Write protection of page 124 to 127 */
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
-
-
-/* STM32 High-density, XL-density and Connectivity line devices */
-#if  defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) \
-  || defined(STM32F101xG) || defined(STM32F103xG) \
-  || defined(STM32F105xC) || defined(STM32F107xC)
-#define OB_WRP_PAGES0TO1               ((uint32_t)0x00000001) /*!< Write protection of page 0 TO 1 */
-#define OB_WRP_PAGES2TO3               ((uint32_t)0x00000002) /*!< Write protection of page 2 TO 3 */
-#define OB_WRP_PAGES4TO5               ((uint32_t)0x00000004) /*!< Write protection of page 4 TO 5 */
-#define OB_WRP_PAGES6TO7               ((uint32_t)0x00000008) /*!< Write protection of page 6 TO 7 */
-#define OB_WRP_PAGES8TO9               ((uint32_t)0x00000010) /*!< Write protection of page 8 TO 9 */
-#define OB_WRP_PAGES10TO11             ((uint32_t)0x00000020) /*!< Write protection of page 10 TO 11 */
-#define OB_WRP_PAGES12TO13             ((uint32_t)0x00000040) /*!< Write protection of page 12 TO 13 */
-#define OB_WRP_PAGES14TO15             ((uint32_t)0x00000080) /*!< Write protection of page 14 TO 15 */
-#define OB_WRP_PAGES16TO17             ((uint32_t)0x00000100) /*!< Write protection of page 16 TO 17 */
-#define OB_WRP_PAGES18TO19             ((uint32_t)0x00000200) /*!< Write protection of page 18 TO 19 */
-#define OB_WRP_PAGES20TO21             ((uint32_t)0x00000400) /*!< Write protection of page 20 TO 21 */
-#define OB_WRP_PAGES22TO23             ((uint32_t)0x00000800) /*!< Write protection of page 22 TO 23 */
-#define OB_WRP_PAGES24TO25             ((uint32_t)0x00001000) /*!< Write protection of page 24 TO 25 */
-#define OB_WRP_PAGES26TO27             ((uint32_t)0x00002000) /*!< Write protection of page 26 TO 27 */
-#define OB_WRP_PAGES28TO29             ((uint32_t)0x00004000) /*!< Write protection of page 28 TO 29 */
-#define OB_WRP_PAGES30TO31             ((uint32_t)0x00008000) /*!< Write protection of page 30 TO 31 */
-#define OB_WRP_PAGES32TO33             ((uint32_t)0x00010000) /*!< Write protection of page 32 TO 33 */
-#define OB_WRP_PAGES34TO35             ((uint32_t)0x00020000) /*!< Write protection of page 34 TO 35 */
-#define OB_WRP_PAGES36TO37             ((uint32_t)0x00040000) /*!< Write protection of page 36 TO 37 */
-#define OB_WRP_PAGES38TO39             ((uint32_t)0x00080000) /*!< Write protection of page 38 TO 39 */
-#define OB_WRP_PAGES40TO41             ((uint32_t)0x00100000) /*!< Write protection of page 40 TO 41 */
-#define OB_WRP_PAGES42TO43             ((uint32_t)0x00200000) /*!< Write protection of page 42 TO 43 */
-#define OB_WRP_PAGES44TO45             ((uint32_t)0x00400000) /*!< Write protection of page 44 TO 45 */
-#define OB_WRP_PAGES46TO47             ((uint32_t)0x00800000) /*!< Write protection of page 46 TO 47 */
-#define OB_WRP_PAGES48TO49             ((uint32_t)0x01000000) /*!< Write protection of page 48 TO 49 */
-#define OB_WRP_PAGES50TO51             ((uint32_t)0x02000000) /*!< Write protection of page 50 TO 51 */
-#define OB_WRP_PAGES52TO53             ((uint32_t)0x04000000) /*!< Write protection of page 52 TO 53 */
-#define OB_WRP_PAGES54TO55             ((uint32_t)0x08000000) /*!< Write protection of page 54 TO 55 */
-#define OB_WRP_PAGES56TO57             ((uint32_t)0x10000000) /*!< Write protection of page 56 TO 57 */
-#define OB_WRP_PAGES58TO59             ((uint32_t)0x20000000) /*!< Write protection of page 58 TO 59 */
-#define OB_WRP_PAGES60TO61             ((uint32_t)0x40000000) /*!< Write protection of page 60 TO 61 */
-#define OB_WRP_PAGES62TO127            ((uint32_t)0x80000000) /*!< Write protection of page 62 TO 127 */
-#define OB_WRP_PAGES62TO255            ((uint32_t)0x80000000) /*!< Write protection of page 62 TO 255 */
-#define OB_WRP_PAGES62TO511            ((uint32_t)0x80000000) /*!< Write protection of page 62 TO 511 */
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
-       /* STM32F101xG || STM32F103xG */ 
-       /* STM32F105xC || STM32F107xC */
-
-#define OB_WRP_ALLPAGES                ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
- 
-/* Low Density */
-#if  defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)
-#define OB_WRP_PAGES0TO31MASK          ((uint32_t)0x000000FF)
-#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
-
-/* Medium Density */
-#if  defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
-#define OB_WRP_PAGES0TO31MASK          ((uint32_t)0x000000FF)
-#define OB_WRP_PAGES32TO63MASK         ((uint32_t)0x0000FF00)
-#define OB_WRP_PAGES64TO95MASK         ((uint32_t)0x00FF0000)
-#define OB_WRP_PAGES96TO127MASK        ((uint32_t)0xFF000000)
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
-       
-/* High Density */
-#if  defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)  
-#define OB_WRP_PAGES0TO15MASK          ((uint32_t)0x000000FF)
-#define OB_WRP_PAGES16TO31MASK         ((uint32_t)0x0000FF00)
-#define OB_WRP_PAGES32TO47MASK         ((uint32_t)0x00FF0000)
-#define OB_WRP_PAGES48TO255MASK        ((uint32_t)0xFF000000)
-#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
-
-/* XL Density */
-#if  defined(STM32F101xG) || defined(STM32F103xG) 
-#define OB_WRP_PAGES0TO15MASK          ((uint32_t)0x000000FF)
-#define OB_WRP_PAGES16TO31MASK         ((uint32_t)0x0000FF00)
-#define OB_WRP_PAGES32TO47MASK         ((uint32_t)0x00FF0000)
-#define OB_WRP_PAGES48TO511MASK        ((uint32_t)0xFF000000)
-#endif /* STM32F101xG || STM32F103xG */
-      
-/* Connectivity line devices */
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define OB_WRP_PAGES0TO15MASK          ((uint32_t)0x000000FF)
-#define OB_WRP_PAGES16TO31MASK         ((uint32_t)0x0000FF00)
-#define OB_WRP_PAGES32TO47MASK         ((uint32_t)0x00FF0000)
-#define OB_WRP_PAGES48TO127MASK        ((uint32_t)0xFF000000)
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
-  * @{
-  */
-#define OB_RDP_LEVEL_0            ((uint8_t)0xA5)
-#define OB_RDP_LEVEL_1            ((uint8_t)0x00)
-/**
-  * @}
-  */
-  
-/** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
-  * @{
-  */ 
-#define OB_IWDG_SW                ((uint16_t)0x0001)  /*!< Software IWDG selected */
-#define OB_IWDG_HW                ((uint16_t)0x0000)  /*!< Hardware IWDG selected */
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
-  * @{
-  */ 
-#define OB_STOP_NO_RST            ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST               ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
-  * @{
-  */ 
-#define OB_STDBY_NO_RST           ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST              ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
-/**
-  * @}
-  */
-
-#if defined(FLASH_BANK2_END)
-/** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
-  * @{
-  */
-#define OB_BOOT1_RESET            ((uint16_t)0x0000) /*!< BOOT1 Reset */
-#define OB_BOOT1_SET              ((uint16_t)0x0008) /*!< BOOT1 Set */
-/**
-  * @}
-  */
-#endif /* FLASH_BANK2_END */
-
-/** @defgroup FLASHEx_OB_Data_Address  Option Byte Data Address
-  * @{
-  */
-#define OB_DATA_ADDRESS_DATA0     ((uint32_t)0x1FFFF804)
-#define OB_DATA_ADDRESS_DATA1     ((uint32_t)0x1FFFF806)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASHEx_Constants
-  * @{
-  */ 
-
-/** @defgroup FLASH_Flag_definition Flag definition
-  * @brief Flag definition
-  * @{
-  */
-#if defined(FLASH_BANK2_END)
- #define FLASH_FLAG_BSY             FLASH_FLAG_BSY_BANK1       /*!< FLASH Bank1 Busy flag                   */ 
- #define FLASH_FLAG_PGERR           FLASH_FLAG_PGERR_BANK1     /*!< FLASH Bank1 Programming error flag      */
- #define FLASH_FLAG_WRPERR          FLASH_FLAG_WRPERR_BANK1    /*!< FLASH Bank1 Write protected error flag  */
- #define FLASH_FLAG_EOP             FLASH_FLAG_EOP_BANK1       /*!< FLASH Bank1 End of Operation flag       */
-
- #define FLASH_FLAG_BSY_BANK1       FLASH_SR_BSY               /*!< FLASH Bank1 Busy flag                   */ 
- #define FLASH_FLAG_PGERR_BANK1     FLASH_SR_PGERR             /*!< FLASH Bank1 Programming error flag      */
- #define FLASH_FLAG_WRPERR_BANK1    FLASH_SR_WRPRTERR          /*!< FLASH Bank1 Write protected error flag  */
- #define FLASH_FLAG_EOP_BANK1       FLASH_SR_EOP               /*!< FLASH Bank1 End of Operation flag       */
-       
- #define FLASH_FLAG_BSY_BANK2       (FLASH_SR2_BSY << 16)      /*!< FLASH Bank2 Busy flag                   */ 
- #define FLASH_FLAG_PGERR_BANK2     (FLASH_SR2_PGERR << 16)    /*!< FLASH Bank2 Programming error flag      */
- #define FLASH_FLAG_WRPERR_BANK2    (FLASH_SR2_WRPRTERR << 16) /*!< FLASH Bank2 Write protected error flag  */
- #define FLASH_FLAG_EOP_BANK2       (FLASH_SR2_EOP << 16)      /*!< FLASH Bank2 End of Operation flag       */
-
-#else  
-
- #define FLASH_FLAG_BSY             FLASH_SR_BSY              /*!< FLASH Busy flag                          */ 
- #define FLASH_FLAG_PGERR           FLASH_SR_PGERR            /*!< FLASH Programming error flag             */
- #define FLASH_FLAG_WRPERR          FLASH_SR_WRPRTERR         /*!< FLASH Write protected error flag         */
- #define FLASH_FLAG_EOP             FLASH_SR_EOP              /*!< FLASH End of Operation flag              */
-
-#endif
- #define FLASH_FLAG_OPTVERR         ((OBR_REG_INDEX << 8 | FLASH_OBR_OPTERR)) /*!< Option Byte Error        */
-/**
-  * @}
-  */
-  
-/** @defgroup FLASH_Interrupt_definition Interrupt definition
-  * @brief FLASH Interrupt definition
-  * @{
-  */
-#if defined(FLASH_BANK2_END)
- #define FLASH_IT_EOP               FLASH_IT_EOP_BANK1        /*!< End of FLASH Operation Interrupt source Bank1 */
- #define FLASH_IT_ERR               FLASH_IT_ERR_BANK1        /*!< Error Interrupt source Bank1                  */
-
- #define FLASH_IT_EOP_BANK1         FLASH_CR_EOPIE            /*!< End of FLASH Operation Interrupt source Bank1 */
- #define FLASH_IT_ERR_BANK1         FLASH_CR_ERRIE            /*!< Error Interrupt source Bank1                  */
-
- #define FLASH_IT_EOP_BANK2         (FLASH_CR2_EOPIE << 16)   /*!< End of FLASH Operation Interrupt source Bank2 */
- #define FLASH_IT_ERR_BANK2         (FLASH_CR2_ERRIE << 16)   /*!< Error Interrupt source Bank2                  */
-
-#else
-
- #define FLASH_IT_EOP               FLASH_CR_EOPIE          /*!< End of FLASH Operation Interrupt source */
- #define FLASH_IT_ERR               FLASH_CR_ERRIE          /*!< Error Interrupt source                  */
-
-#endif
-/**
-  * @}
-  */  
-
-/**
-  * @}
-  */
-  
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
-  * @{
-  */
-
-/** @defgroup FLASH_Interrupt Interrupt
- *  @brief macros to handle FLASH interrupts
- * @{
- */ 
-
-#if defined(FLASH_BANK2_END)
-/**
-  * @brief  Enable the specified FLASH interrupt.
-  * @param  __INTERRUPT__  FLASH interrupt 
-  *     This parameter can be any combination of the following values:
-  *     @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
-  *     @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
-  *     @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
-  *     @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
-  * @retval none
-  */ 
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  do { \
-                          /* Enable Bank1 IT */ \
-                          SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFF)); \
-                          /* Enable Bank2 IT */ \
-                          SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16)); \
-                    } while(0)
-
-/**
-  * @brief  Disable the specified FLASH interrupt.
-  * @param  __INTERRUPT__  FLASH interrupt 
-  *     This parameter can be any combination of the following values:
-  *     @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
-  *     @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
-  *     @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
-  *     @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
-  * @retval none
-  */ 
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  do { \
-                          /* Disable Bank1 IT */ \
-                          CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFF)); \
-                          /* Disable Bank2 IT */ \
-                          CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16)); \
-                    } while(0)
-
-/**
-  * @brief  Get the specified FLASH flag status. 
-  * @param  __FLAG__ specifies the FLASH flag to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref FLASH_FLAG_EOP_BANK1    FLASH End of Operation flag on bank1
-  *            @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
-  *            @arg @ref FLASH_FLAG_PGERR_BANK1  FLASH Programming error flag on bank1
-  *            @arg @ref FLASH_FLAG_BSY_BANK1    FLASH Busy flag on bank1
-  *            @arg @ref FLASH_FLAG_EOP_BANK2    FLASH End of Operation flag on bank2
-  *            @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
-  *            @arg @ref FLASH_FLAG_PGERR_BANK2  FLASH Programming error flag on bank2
-  *            @arg @ref FLASH_FLAG_BSY_BANK2    FLASH Busy flag on bank2
-  *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
-  * @retval The new state of __FLAG__ (SET or RESET).
-  */
-#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
-                                            (FLASH->OBR & FLASH_OBR_OPTERR) : \
-                                        ((((__FLAG__) & SR_FLAG_MASK) != RESET)? \
-                                            (FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \
-                                            (FLASH->SR2 & ((__FLAG__) >> 16))))
-
-/**
-  * @brief  Clear the specified FLASH flag.
-  * @param  __FLAG__ specifies the FLASH flags to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref FLASH_FLAG_EOP_BANK1    FLASH End of Operation flag on bank1
-  *            @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
-  *            @arg @ref FLASH_FLAG_PGERR_BANK1  FLASH Programming error flag on bank1
-  *            @arg @ref FLASH_FLAG_BSY_BANK1    FLASH Busy flag on bank1
-  *            @arg @ref FLASH_FLAG_EOP_BANK2    FLASH End of Operation flag on bank2
-  *            @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
-  *            @arg @ref FLASH_FLAG_PGERR_BANK2  FLASH Programming error flag on bank2
-  *            @arg @ref FLASH_FLAG_BSY_BANK2    FLASH Busy flag on bank2
-  *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
-  * @retval none
-  */
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)  do { \
-                          /* Clear FLASH_FLAG_OPTVERR flag */ \
-                          if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
-                          { \
-                            CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
-                          } \
-                          else { \
-                          /* Clear Flag in Bank1 */ \
-                          if (((__FLAG__) & SR_FLAG_MASK) != RESET) \
-                          { \
-                            FLASH->SR  = ((__FLAG__) & SR_FLAG_MASK); \
-                          } \
-                          /* Clear Flag in Bank2 */ \
-                          if (((__FLAG__) >> 16) != RESET) \
-                          { \
-                            FLASH->SR2 = ((__FLAG__) >> 16); \
-                          } \
-                          } \
-                    } while(0)
-#else
-/**
-  * @brief  Enable the specified FLASH interrupt.
-  * @param  __INTERRUPT__  FLASH interrupt 
-  *         This parameter can be any combination of the following values:
-  *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
-  *     @arg @ref FLASH_IT_ERR Error Interrupt    
-  * @retval none
-  */ 
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  (FLASH->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the specified FLASH interrupt.
-  * @param  __INTERRUPT__  FLASH interrupt 
-  *         This parameter can be any combination of the following values:
-  *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
-  *     @arg @ref FLASH_IT_ERR Error Interrupt    
-  * @retval none
-  */ 
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)   (FLASH->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Get the specified FLASH flag status. 
-  * @param  __FLAG__ specifies the FLASH flag to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref FLASH_FLAG_EOP    FLASH End of Operation flag 
-  *            @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag 
-  *            @arg @ref FLASH_FLAG_PGERR  FLASH Programming error flag
-  *            @arg @ref FLASH_FLAG_BSY    FLASH Busy flag
-  *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
-  * @retval The new state of __FLAG__ (SET or RESET).
-  */
-#define __HAL_FLASH_GET_FLAG(__FLAG__)  (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
-                                            (FLASH->OBR & FLASH_OBR_OPTERR) : \
-                                            (FLASH->SR & (__FLAG__)))
-/**
-  * @brief  Clear the specified FLASH flag.
-  * @param  __FLAG__ specifies the FLASH flags to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref FLASH_FLAG_EOP    FLASH End of Operation flag 
-  *            @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag 
-  *            @arg @ref FLASH_FLAG_PGERR  FLASH Programming error flag 
-  *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
-  * @retval none
-  */
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   do { \
-                          /* Clear FLASH_FLAG_OPTVERR flag */ \
-                          if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
-                          { \
-                            CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
-                          } \
-                          else { \
-                            /* Clear Flag in Bank1 */ \
-                            FLASH->SR  = (__FLAG__); \
-                          } \
-                    } while(0)
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASHEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group1
-  * @{
-  */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef  HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
-HAL_StatusTypeDef  HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group2
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef  HAL_FLASHEx_OBErase(void);
-HAL_StatusTypeDef  HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
-void               HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
-uint32_t           HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_FLASH_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_gpio.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,324 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_gpio.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of GPIO HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_GPIO_H
-#define __STM32F1xx_HAL_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup GPIO
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Types GPIO Exported Types
-  * @{
-  */ 
-
-/** 
-  * @brief   GPIO Init structure definition  
-  */ 
-typedef struct
-{
-  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
-                           This parameter can be any value of @ref GPIO_pins_define */
-
-  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
-                           This parameter can be a value of @ref GPIO_mode_define */
-                           
-  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
-                           This parameter can be a value of @ref GPIO_pull_define */
-                           
-  uint32_t Speed;     /*!< Specifies the speed for the selected pins.
-                           This parameter can be a value of @ref GPIO_speed_define */
-}GPIO_InitTypeDef;
- 
-/** 
-  * @brief  GPIO Bit SET and Bit RESET enumeration 
-  */
-typedef enum
-{ 
-  GPIO_PIN_RESET = 0,
-  GPIO_PIN_SET
-}GPIO_PinState;
-
-/**
-  * @}
-  */
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
-  * @{
-  */ 
-
-/** @defgroup GPIO_pins_define GPIO pins define
-  * @{
-  */ 
-#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
-#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
-#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
-#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
-#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
-#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
-#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
-#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
-#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
-#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
-#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
-#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
-#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
-#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
-#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
-#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
-#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
-
-#define GPIO_PIN_MASK              ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
-/**
-  * @}
-  */ 
-
-     
-/** @defgroup GPIO_mode_define GPIO mode define
-  * @brief GPIO Configuration Mode 
-  *        Elements values convention: 0xX0yz00YZ
-  *           - X  : GPIO mode or EXTI Mode
-  *           - y  : External IT or Event trigger detection 
-  *           - z  : IO configuration on External IT or Event
-  *           - Y  : Output type (Push Pull or Open Drain)
-  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
-  * @{
-  */ 
-#define  GPIO_MODE_INPUT                        ((uint32_t)0x00000000)   /*!< Input Floating Mode                   */
-#define  GPIO_MODE_OUTPUT_PP                    ((uint32_t)0x00000001)   /*!< Output Push Pull Mode                 */
-#define  GPIO_MODE_OUTPUT_OD                    ((uint32_t)0x00000011)   /*!< Output Open Drain Mode                */
-#define  GPIO_MODE_AF_PP                        ((uint32_t)0x00000002)   /*!< Alternate Function Push Pull Mode     */
-#define  GPIO_MODE_AF_OD                        ((uint32_t)0x00000012)   /*!< Alternate Function Open Drain Mode    */
-#define  GPIO_MODE_AF_INPUT                     GPIO_MODE_INPUT          /*!< Alternate Function Input Mode         */
-
-#define  GPIO_MODE_ANALOG                       ((uint32_t)0x00000003)   /*!< Analog Mode  */
-    
-#define  GPIO_MODE_IT_RISING                    ((uint32_t)0x10110000)   /*!< External Interrupt Mode with Rising edge trigger detection          */
-#define  GPIO_MODE_IT_FALLING                   ((uint32_t)0x10210000)   /*!< External Interrupt Mode with Falling edge trigger detection         */
-#define  GPIO_MODE_IT_RISING_FALLING            ((uint32_t)0x10310000)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
- 
-#define  GPIO_MODE_EVT_RISING                   ((uint32_t)0x10120000)   /*!< External Event Mode with Rising edge trigger detection               */
-#define  GPIO_MODE_EVT_FALLING                  ((uint32_t)0x10220000)   /*!< External Event Mode with Falling edge trigger detection              */
-#define  GPIO_MODE_EVT_RISING_FALLING           ((uint32_t)0x10320000)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
-
-/**
-  * @}
-  */
-                                                    
-                                                         
-/** @defgroup GPIO_speed_define GPIO speed define
-  * @brief GPIO Output Maximum frequency
-  * @{
-  */  
-#define  GPIO_SPEED_FREQ_LOW              (GPIO_CRL_MODE0_1) /*!< Low speed */
-#define  GPIO_SPEED_FREQ_MEDIUM           (GPIO_CRL_MODE0_0) /*!< Medium speed */
-#define  GPIO_SPEED_FREQ_HIGH             (GPIO_CRL_MODE0)   /*!< High speed */
-
-/**
-  * @}
-  */
-
-
- /** @defgroup GPIO_pull_define GPIO pull define
-   * @brief GPIO Pull-Up or Pull-Down Activation
-   * @{
-   */  
-#define  GPIO_NOPULL        ((uint32_t)0x00000000)   /*!< No Pull-up or Pull-down activation  */
-#define  GPIO_PULLUP        ((uint32_t)0x00000001)   /*!< Pull-up activation                  */
-#define  GPIO_PULLDOWN      ((uint32_t)0x00000002)   /*!< Pull-down activation                */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup GPIO_Private_Macros
-  * @{
-  */
-
-#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-
-#define IS_GPIO_PIN(PIN)           (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
-
-#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
-                            ((PULL) == GPIO_PULLDOWN))
-                            
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \
-                              ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
-
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
-                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
-                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
-                            ((MODE) == GPIO_MODE_AF_PP)              ||\
-                            ((MODE) == GPIO_MODE_AF_OD)              ||\
-                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
-                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
-                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
-                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
-                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
-                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
-                            ((MODE) == GPIO_MODE_ANALOG))
-
-/**
-  * @}
-  */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
-  * @{
-  */
-
-/**
-  * @brief  Checks whether the specified EXTI line flag is set or not.
-  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
-  *         This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).
-  */
-#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))   
-     
-/**
-  * @brief  Clears the EXTI's line pending flags.
-  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
-  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
-  * @brief  Checks whether the specified EXTI line is asserted or not.
-  * @param  __EXTI_LINE__: specifies the EXTI line to check.
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).
-  */
-#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))   
-     
-/**
-  * @brief  Clears the EXTI's line pending bits.
-  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
-  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
-  * @brief  Generates a Software interrupt on selected EXTI line.
-  * @param  __EXTI_LINE__: specifies the EXTI line to check.
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
-
-/* Include GPIO HAL Extension module */
-#include "stm32f1xx_hal_gpio_ex.h"
-
-/**
-  * @}
-  */
-
-
-
-/* Exported functions --------------------------------------------------------*/ 
-/* Initialization and de-initialization functions *******************************/
-/** @addtogroup GPIO_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup GPIO_Exported_Functions_Group1
-  * @{
-  */
-void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
-void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
-/**
-  * @}
-  */
-
-/* IO operation functions *******************************************************/
-/** @addtogroup GPIO_Exported_Functions_Group2
-  * @{
-  */
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void          HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
-void          HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void          HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
-void          HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_GPIO_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_gpio_ex.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,887 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_gpio_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of GPIO HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_GPIO_EX_H
-#define __STM32F1xx_HAL_GPIO_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup GPIOEx GPIOEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
-  * @{
-  */ 
-  
-/** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration
-  * @brief This section propose definition to use the Cortex EVENTOUT signal.
-  * @{
-  */
-  
-/** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin 
-  * @{
-  */
-  
-#define AFIO_EVENTOUT_PIN_0  AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
-#define AFIO_EVENTOUT_PIN_1  AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
-#define AFIO_EVENTOUT_PIN_2  AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
-#define AFIO_EVENTOUT_PIN_3  AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
-#define AFIO_EVENTOUT_PIN_4  AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
-#define AFIO_EVENTOUT_PIN_5  AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
-#define AFIO_EVENTOUT_PIN_6  AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
-#define AFIO_EVENTOUT_PIN_7  AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
-#define AFIO_EVENTOUT_PIN_8  AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
-#define AFIO_EVENTOUT_PIN_9  AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
-#define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
-#define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
-#define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
-#define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
-#define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
-#define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
-
-#define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_15))
-/**
-  * @}
-  */ 
-  
-/** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port
-  * @{
-  */
-  
-#define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
-#define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
-#define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
-#define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
-#define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
-
-#define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \
-                                         ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \
-                                         ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \
-                                         ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \
-                                         ((__PORT__) == AFIO_EVENTOUT_PORT_E))
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping
-  * @brief This section propose definition to remap the alternate function to some other port/pins.
-  * @{
-  */
-  
-/**
-  * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
-  * @note  ENABLE: Remap     (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_SPI1_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
-
-/**
-  * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
-  * @note  DISABLE: No remap (NSS/PA4,  SCK/PA5, MISO/PA6, MOSI/PA7)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_SPI1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
-
-/**
-  * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
-  * @note  ENABLE: Remap     (SCL/PB8, SDA/PB9)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_I2C1_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
-
-/**
-  * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
-  * @note  DISABLE: No remap (SCL/PB6, SDA/PB7)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_I2C1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
-
-/**
-  * @brief Enable the remapping of USART1 alternate function TX and RX.
-  * @note  ENABLE: Remap     (TX/PB6, RX/PB7)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_USART1_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
-
-/**
-  * @brief Disable the remapping of USART1 alternate function TX and RX.
-  * @note  DISABLE: No remap (TX/PA9, RX/PA10)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_USART1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
-
-/**
-  * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
-  * @note  ENABLE: Remap     (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_USART2_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
-
-/**
-  * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
-  * @note  DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_USART2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
-
-/**
-  * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
-  * @note  ENABLE: Full remap     (TX/PD8,  RX/PD9,  CK/PD10, CTS/PD11, RTS/PD12)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_USART3_ENABLE()  MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
-
-/**
-  * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
-  * @note  PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_USART3_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_PARTIALREMAP)
-
-/**
-  * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
-  * @note  DISABLE: No remap      (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_USART3_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_NOREMAP)
-
-/**
-  * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
-  * @note  ENABLE: Full remap     (ETR/PE7,  CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8,  CH2N/PE10, CH3N/PE12)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM1_ENABLE()  MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
-
-/**
-  * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
-  * @note  PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PA6,  CH1N/PA7,  CH2N/PB0,  CH3N/PB1)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM1_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP)
-
-/**
-  * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
-  * @note  DISABLE: No remap      (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM1_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_NOREMAP)
-
-/**
-  * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
-  * @note  ENABLE: Full remap       (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM2_ENABLE()    MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
-
-/**
-  * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
-  * @note  PARTIAL_2: Partial remap (CH1/ETR/PA0,  CH2/PA1, CH3/PB10, CH4/PB11)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2)
-
-/**
-  * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
-  * @note  PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2,  CH4/PA3)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1)
-
-/**
-  * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
-  * @note  DISABLE: No remap        (CH1/ETR/PA0,  CH2/PA1, CH3/PA2,  CH4/PA3)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM2_DISABLE()   MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_NOREMAP)
-
-/**
-  * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
-  * @note  ENABLE: Full remap     (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
-  * @note  TIM3_ETR on PE0 is not re-mapped.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM3_ENABLE()  MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
-
-/**
-  * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
-  * @note  PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
-  * @note  TIM3_ETR on PE0 is not re-mapped.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM3_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP)
-
-/**
-  * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
-  * @note  DISABLE: No remap      (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
-  * @note  TIM3_ETR on PE0 is not re-mapped.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM3_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_NOREMAP)
-
-/**
-  * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
-  * @note  ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
-  * @note  TIM4_ETR on PE0 is not re-mapped.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM4_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
-
-/**
-  * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
-  * @note  DISABLE: No remap  (TIM4_CH1/PB6,  TIM4_CH2/PB7,  TIM4_CH3/PB8,  TIM4_CH4/PB9)
-  * @note  TIM4_ETR on PE0 is not re-mapped.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
-
-#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
-
-/**
-  * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
-  * @note  CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_CAN1_1() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP1)
-
-/**
-  * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
-  * @note  CASE 2: CAN_RX mapped to PB8,  CAN_TX mapped to PB9 (not available on 36-pin package)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_CAN1_2() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP2)
-
-/**
-  * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
-  * @note  CASE 3: CAN_RX mapped to PD0,  CAN_TX mapped to PD1
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_CAN1_3() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP3)
-#endif
-
-/**
-  * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used 
-  *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and 
-  *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available 
-  *        on 100-pin and 144-pin packages, no need for remapping).
-  * @note  ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_PD01_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
-
-/**
-  * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used 
-  *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and 
-  *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available 
-  *        on 100-pin and 144-pin packages, no need for remapping).
-  * @note  DISABLE: No remapping of PD0 and PD1
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_PD01_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
-
-#if defined(AFIO_MAPR_TIM5CH4_IREMAP)
-/**
-  * @brief Enable the remapping of TIM5CH4.
-  * @note  ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
-  * @note  This function is available only in high density value line devices.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM5CH4_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP)
-
-/**
-  * @brief Disable the remapping of TIM5CH4.
-  * @note  DISABLE: TIM5_CH4 is connected to PA3
-  * @note  This function is available only in high density value line devices.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP)
-#endif
-
-#if defined(AFIO_MAPR_ETH_REMAP)
-/**
-  * @brief Enable the remapping of Ethernet MAC connections with the PHY.
-  * @note  ENABLE: Remap     (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
-  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_ETH_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP)
-
-/**
-  * @brief Disable the remapping of Ethernet MAC connections with the PHY.
-  * @note  DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5,  RXD2/PB0,  RXD3/PB1)
-  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_ETH_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP)
-#endif
-
-#if defined(AFIO_MAPR_CAN2_REMAP)
-
-/**
-  * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
-  * @note  ENABLE: Remap     (CAN2_RX/PB5,  CAN2_TX/PB6)
-  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_CAN2_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP)
-
-/**
-  * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
-  * @note  DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
-  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_CAN2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP)
-#endif
-
-#if defined(AFIO_MAPR_MII_RMII_SEL)
-/**
-  * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
-  * @note  ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
-  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
-  * @retval None
-  */
-#define __HAL_AFIO_ETH_RMII() SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL)
-
-/**
-  * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
-  * @note  ETH_MII: Configure Ethernet MAC for connection with an MII PHY
-  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
-  * @retval None
-  */
-#define __HAL_AFIO_ETH_MII()  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL)
-#endif
-
-/**
-  * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
-  * @note  ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
-
-/**
-  * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
-  * @note  DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
-
-/**
-  * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
-  * @note  ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
-
-/**
-  * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
-  * @note  DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
-
-#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
-
-/**
-  * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
-  * @note  ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP)
-
-/**
-  * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
-  * @note  DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP)
-#endif
-
-#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
-
-/**
-  * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
-  * @note  ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP)
-
-/**
-  * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
-  * @note  DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP)
-#endif
-
-/**
-  * @brief Enable the Serial wire JTAG configuration
-  * @note  ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_SWJ_ENABLE()   MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_RESET)
-
-/**
-  * @brief Enable the Serial wire JTAG configuration
-  * @note  NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_SWJ_NONJTRST() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_NOJNTRST)
-
-/**
-  * @brief Enable the Serial wire JTAG configuration
-  * @note  NOJTAG: JTAG-DP Disabled and SW-DP Enabled
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_SWJ_NOJTAG()   MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_JTAGDISABLE)
-
-/**
-  * @brief Disable the Serial wire JTAG configuration
-  * @note  DISABLE: JTAG-DP Disabled and SW-DP Disabled
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_SWJ_DISABLE()  MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_DISABLE)
-
-#if defined(AFIO_MAPR_SPI3_REMAP)
-
-/**
-  * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
-  * @note  ENABLE: Remap     (SPI3_NSS-I2S3_WS/PA4,  SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
-  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_SPI3_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP)
-
-/**
-  * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
-  * @note  DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3,  SPI3_MISO/PB4,  SPI3_MOSI-I2S3_SD/PB5).
-  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_SPI3_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP)
-#endif
-
-#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
-
-/**
-  * @brief Control of TIM2_ITR1 internal mapping.
-  * @note  TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
-  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
-  * @retval None
-  */
-#define __HAL_AFIO_TIM2ITR1_TO_USB() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP)
-
-/**
-  * @brief Control of TIM2_ITR1 internal mapping.
-  * @note  TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
-  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
-  * @retval None
-  */
-#define __HAL_AFIO_TIM2ITR1_TO_ETH() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP)
-#endif
-
-#if defined(AFIO_MAPR_PTP_PPS_REMAP)
-
-/**
-  * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
-  * @note  ENABLE: PTP_PPS is output on PB5 pin.
-  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
-  * @retval None
-  */
-#define __HAL_AFIO_ETH_PTP_PPS_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP)
-
-/**
-  * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
-  * @note  DISABLE: PTP_PPS not output on PB5 pin.
-  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
-  * @retval None
-  */
-#define __HAL_AFIO_ETH_PTP_PPS_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM9_REMAP)
-
-/**
-  * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
-  * @note  ENABLE: Remap     (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM9_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
-
-/**
-  * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
-  * @note  DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM10_REMAP)
-
-/**
-  * @brief Enable the remapping of TIM10_CH1.
-  * @note  ENABLE: Remap     (TIM10_CH1 on PF6).
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM10_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
-
-/**
-  * @brief Disable the remapping of TIM10_CH1.
-  * @note  DISABLE: No remap (TIM10_CH1 on PB8).
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM11_REMAP)
-/**
-  * @brief Enable the remapping of TIM11_CH1.
-  * @note  ENABLE: Remap     (TIM11_CH1 on PF7).
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM11_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
-
-/**
-  * @brief Disable the remapping of TIM11_CH1.
-  * @note  DISABLE: No remap (TIM11_CH1 on PB9).
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM13_REMAP)
-
-/**
-  * @brief Enable the remapping of TIM13_CH1.
-  * @note  ENABLE: Remap     STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM13_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
-
-/**
-  * @brief Disable the remapping of TIM13_CH1.
-  * @note  DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM14_REMAP)
-
-/**
-  * @brief Enable the remapping of TIM14_CH1.
-  * @note  ENABLE: Remap     STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM14_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
-
-/**
-  * @brief Disable the remapping of TIM14_CH1.
-  * @note  DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
-
-/**
-  * @brief Controls the use of the optional FSMC_NADV signal.
-  * @note  DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
-  * @retval None
-  */
-#define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
-
-/**
-  * @brief Controls the use of the optional FSMC_NADV signal.
-  * @note  CONNECTED: The NADV signal is connected to the output (default).
-  * @retval None
-  */
-#define __HAL_AFIO_FSMCNADV_CONNECTED()    CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM15_REMAP)
-
-/**
-  * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
-  * @note  ENABLE: Remap     (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM15_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
-
-/**
-  * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
-  * @note  DISABLE: No remap (TIM15_CH1 on PA2  and TIM15_CH2 on PA3).
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM16_REMAP)
-
-/**
-  * @brief Enable the remapping of TIM16_CH1.
-  * @note  ENABLE: Remap     (TIM16_CH1 on PA6).
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM16_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
-
-/**
-  * @brief Disable the remapping of TIM16_CH1.
-  * @note  DISABLE: No remap (TIM16_CH1 on PB8).
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM17_REMAP)
-
-/**
-  * @brief Enable the remapping of TIM17_CH1.
-  * @note  ENABLE: Remap     (TIM17_CH1 on PA7).
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM17_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
-
-/**
-  * @brief Disable the remapping of TIM17_CH1.
-  * @note  DISABLE: No remap (TIM17_CH1 on PB9).
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_CEC_REMAP)
-
-/**
-  * @brief Enable the remapping of CEC.
-  * @note  ENABLE: Remap     (CEC on PB10).
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_CEC_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
-
-/**
-  * @brief Disable the remapping of CEC.
-  * @note  DISABLE: No remap (CEC on PB8).
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
-
-/**
-  * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
-  * @note  ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM1DMA_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
-
-/**
-  * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
-  * @note  DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
-
-/**
-  * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
-  * @note  ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
-
-/**
-  * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
-  * @note  DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM12_REMAP)
-
-/**
-  * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
-  * @note  ENABLE: Remap     (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
-  * @note  This bit is available only in high density value line devices.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM12_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
-
-/**
-  * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
-  * @note  DISABLE: No remap (TIM12_CH1 on PC4  and TIM12_CH2 on PC5).
-  * @note  This bit is available only in high density value line devices.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_MISC_REMAP)
-
-/**
-  * @brief Miscellaneous features remapping.
-  *        This bit is set and cleared by software. It controls miscellaneous features.
-  *        The DMA2 channel 5 interrupt position in the vector table.
-  *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
-  * @note  ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
-  *        selected as DAC Trigger 3, TIM15 triggers TIM1/3.
-  * @note  This bit is available only in high density value line devices.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_MISC_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
-
-/**
-  * @brief Miscellaneous features remapping.
-  *        This bit is set and cleared by software. It controls miscellaneous features.
-  *        The DMA2 channel 5 interrupt position in the vector table.
-  *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
-  * @note  DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
-  *        event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
-  * @note  This bit is available only in high density value line devices.
-  * @retval None
-  */
-#define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
-#endif
-
-/**
-  * @}
-  */ 
-  
-/**
-  * @}
-  */
-  
-/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
-  * @{
-  */
-#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
-                                   ((__GPIOx__) == (GPIOB))? 1U :\
-                                   ((__GPIOx__) == (GPIOC))? 2U :3U)
-#elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
-                                   ((__GPIOx__) == (GPIOB))? 1U :\
-                                   ((__GPIOx__) == (GPIOC))? 2U :\
-                                   ((__GPIOx__) == (GPIOD))? 3U :4U)
-#elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
-                                   ((__GPIOx__) == (GPIOB))? 1U :\
-                                   ((__GPIOx__) == (GPIOC))? 2U :\
-                                   ((__GPIOx__) == (GPIOD))? 3U :\
-                                   ((__GPIOx__) == (GPIOE))? 4U :\
-                                   ((__GPIOx__) == (GPIOF))? 5U :6U)
-#endif
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup GPIOEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup GPIOEx_Exported_Functions_Group1
-  * @{
-  */
-void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource);
-void HAL_GPIOEx_EnableEventout(void);
-void HAL_GPIOEx_DisableEventout(void);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_GPIO_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_hcd.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,254 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_hcd.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of HCD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_HCD_H
-#define __STM32F1xx_HAL_HCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_usb.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup HCD
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup HCD_Exported_Types HCD Exported Types
-  * @{
-  */
-
-/**
-  * @brief  HCD Status structure definition
-  */
-typedef enum
-{
-  HAL_HCD_STATE_RESET    = 0x00,
-  HAL_HCD_STATE_READY    = 0x01,
-  HAL_HCD_STATE_ERROR    = 0x02,
-  HAL_HCD_STATE_BUSY     = 0x03,
-  HAL_HCD_STATE_TIMEOUT  = 0x04
-} HCD_StateTypeDef;
-
-typedef USB_OTG_GlobalTypeDef   HCD_TypeDef;
-typedef USB_OTG_CfgTypeDef      HCD_InitTypeDef;
-typedef USB_OTG_HCTypeDef       HCD_HCTypeDef;
-typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;
-typedef USB_OTG_HCStateTypeDef  HCD_HCStateTypeDef;
-
-/**
-  * @brief  HCD Handle Structure definition
-  */
-typedef struct
-{
-  HCD_TypeDef               *Instance;  /*!< Register base address    */
-  HCD_InitTypeDef           Init;       /*!< HCD required parameters  */
-  HCD_HCTypeDef             hc[15];     /*!< Host channels parameters */
-  HAL_LockTypeDef           Lock;       /*!< HCD peripheral status    */
-  __IO HCD_StateTypeDef     State;      /*!< HCD communication state  */
-  void                      *pData;     /*!< Pointer Stack Handler    */
-} HCD_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup HCD_Exported_Constants HCD Exported Constants
-  * @{
-  */
-/** @defgroup HCD_Speed HCD Speed
-  * @{
-  */
-#define HCD_SPEED_LOW                2
-#define HCD_SPEED_FULL               3
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup HCD_Exported_Macros HCD Exported Macros
- *  @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-#define __HAL_HCD_ENABLE(__HANDLE__)                       USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_HCD_DISABLE(__HANDLE__)                      USB_DisableGlobalInt ((__HANDLE__)->Instance)
-   
-   
-#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
-#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)    
-   
-   
-#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__)       (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) 
-#define __HAL_HCD_MASK_HALT_HC_INT(chnum)                  (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) 
-#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)                (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) 
-#define __HAL_HCD_MASK_ACK_HC_INT(chnum)                   (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) 
-#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)                 (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) 
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HCD_Exported_Functions HCD Exported Functions
-  * @{
-  */
-
-/* Initialization/de-initialization functions  ********************************/
-/** @addtogroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-HAL_StatusTypeDef      HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef      HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef      HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
-                                       uint8_t ch_num,
-                                       uint8_t epnum,
-                                       uint8_t dev_address,
-                                       uint8_t speed,
-                                       uint8_t ep_type,
-                                       uint16_t mps);
-
-HAL_StatusTypeDef      HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
-                                       uint8_t ch_num);
-
-void                   HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
-void                   HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
-/**
-  * @}
-  */
-
-/* I/O operation functions  ***************************************************/
-/** @addtogroup HCD_Exported_Functions_Group2 IO operation functions
-  * @{
-  */
-HAL_StatusTypeDef      HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
-                                                uint8_t pipe,
-                                                uint8_t direction,
-                                                uint8_t ep_type,
-                                                uint8_t token,
-                                                uint8_t* pbuff,
-                                                uint16_t length,
-                                                uint8_t do_ping);
-
- /* Non-Blocking mode: Interrupt */
-void                   HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
-void                   HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
-void                   HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
-void                   HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
-void                   HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
-                                                           uint8_t chnum,
-                                                           HCD_URBStateTypeDef urb_state);
-/**
-  * @}
-  */
-/* Peripheral Control functions  **********************************************/
-/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
-  * @{
-  */
-HAL_StatusTypeDef      HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef      HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef      HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
-/**
-  * @}
-  */
-/* Peripheral State functions  ************************************************/
-/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
-  * @{
-  */
-HCD_StateTypeDef       HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
-HCD_URBStateTypeDef    HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t               HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-HCD_HCStateTypeDef     HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t               HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
-uint32_t               HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup HCD_Private_Macros HCD Private Macros
- * @{
- */
-/** @defgroup HCD_Instance_definition HCD Instance definition
-  * @{
-  */
- #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
-/**
-  * @}
-  */
-/**
-  * @}
-  */
- 
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32F105xC || STM32F107xC */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_HCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_i2c.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,600 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_i2c.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of I2C HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_I2C_H
-#define __STM32F1xx_HAL_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2C
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup I2C_Exported_Types I2C Exported Types
-  * @{
-  */
-
-/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
-  * @brief  I2C Configuration Structure definition
-  * @{
-  */
-typedef struct
-{
-  uint32_t ClockSpeed;       /*!< Specifies the clock frequency.
-                                  This parameter must be set to a value lower than 400kHz */
-
-  uint32_t DutyCycle;        /*!< Specifies the I2C fast mode duty cycle.
-                                  This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
-
-  uint32_t OwnAddress1;      /*!< Specifies the first device own address.
-                                  This parameter can be a 7-bit or 10-bit address. */
-
-  uint32_t AddressingMode;   /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
-                                  This parameter can be a value of @ref I2C_addressing_mode */
-
-  uint32_t DualAddressMode;  /*!< Specifies if dual addressing mode is selected.
-                                  This parameter can be a value of @ref I2C_dual_addressing_mode */
-
-  uint32_t OwnAddress2;      /*!< Specifies the second device own address if dual addressing mode is selected
-                                  This parameter can be a 7-bit address. */
-
-  uint32_t GeneralCallMode;  /*!< Specifies if general call mode is selected.
-                                  This parameter can be a value of @ref I2C_general_call_addressing_mode */
-
-  uint32_t NoStretchMode;    /*!< Specifies if nostretch mode is selected.
-                                  This parameter can be a value of @ref I2C_nostretch_mode */
-
-}I2C_InitTypeDef;
-
-/** 
-  * @}
-  */
-
-/** @defgroup HAL_state_structure_definition HAL state structure definition
-  * @brief  HAL State structure definition  
-  * @{
-  */ 
-
-typedef enum
-{
-  HAL_I2C_STATE_RESET             = 0x00,   /*!< Peripheral is not yet Initialized         */
-  HAL_I2C_STATE_READY             = 0x20,   /*!< Peripheral Initialized and ready for use  */
-  HAL_I2C_STATE_BUSY              = 0x24,   /*!< An internal process is ongoing            */   
-  HAL_I2C_STATE_BUSY_TX           = 0x21,   /*!< Data Transmission process is ongoing      */ 
-  HAL_I2C_STATE_BUSY_RX           = 0x22,   /*!< Data Reception process is ongoing         */
-  HAL_I2C_STATE_TIMEOUT           = 0xA0,   /*!< Timeout state                             */
-  HAL_I2C_STATE_ERROR             = 0xE0    /*!< Error                                     */ 
-
-}HAL_I2C_StateTypeDef;
-
-/** 
-  * @}
-  */
-
-/** @defgroup HAL_mode_structure_definition HAL mode structure definition
-  * @brief  HAL Mode structure definition
-  * @{
-  */
-typedef enum
-{
-  HAL_I2C_MODE_NONE               = 0x00,   /*!< No I2C communication on going             */
-  HAL_I2C_MODE_MASTER             = 0x10,   /*!< I2C communication is in Master Mode       */
-  HAL_I2C_MODE_SLAVE              = 0x20,   /*!< I2C communication is in Slave Mode        */
-  HAL_I2C_MODE_MEM                = 0x40    /*!< I2C communication is in Memory Mode       */
-
-}HAL_I2C_ModeTypeDef;
-
-/** 
-  * @}
-  */
-
-/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition 
-  * @brief  I2C handle Structure definition  
-  * @{
-  */
-typedef struct
-{
-  I2C_TypeDef                *Instance;  /*!< I2C registers base address     */
-
-  I2C_InitTypeDef            Init;       /*!< I2C communication parameters   */
-
-  uint8_t                    *pBuffPtr;  /*!< Pointer to I2C transfer buffer */
-
-  uint16_t                   XferSize;   /*!< I2C transfer size              */
-
-  __IO uint16_t              XferCount;  /*!< I2C transfer counter           */
-
-  DMA_HandleTypeDef          *hdmatx;    /*!< I2C Tx DMA handle parameters   */
-
-  DMA_HandleTypeDef          *hdmarx;    /*!< I2C Rx DMA handle parameters   */
-
-  HAL_LockTypeDef            Lock;       /*!< I2C locking object             */
-
-  __IO HAL_I2C_StateTypeDef  State;      /*!< I2C communication state        */
-
-  __IO HAL_I2C_ModeTypeDef   Mode;       /*!< I2C communication mode         */
-
-  __IO uint32_t              ErrorCode;  /*!< I2C Error code                 */
-
-}I2C_HandleTypeDef;
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */  
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Constants I2C Exported Constants
-  * @{
-  */
-
-/** @defgroup I2C_Error_Codes I2C Error Codes  
-  * @{
-  */ 
-  
-#define HAL_I2C_ERROR_NONE      ((uint32_t)0x00)    /*!< No error             */
-#define HAL_I2C_ERROR_BERR      ((uint32_t)0x01)    /*!< BERR error           */
-#define HAL_I2C_ERROR_ARLO      ((uint32_t)0x02)    /*!< ARLO error           */
-#define HAL_I2C_ERROR_AF        ((uint32_t)0x04)    /*!< AF error             */
-#define HAL_I2C_ERROR_OVR       ((uint32_t)0x08)    /*!< OVR error            */
-#define HAL_I2C_ERROR_DMA       ((uint32_t)0x10)    /*!< DMA transfer error   */
-#define HAL_I2C_ERROR_TIMEOUT   ((uint32_t)0x20)     /*!< Timeout error        */
-
-/** 
-  * @}
-  */
-
-
-
-/** @defgroup I2C_duty_cycle_in_fast_mode I2C Duty Cycle
-  * @{
-  */
-#define I2C_DUTYCYCLE_2                 ((uint32_t)0x00000000)
-#define I2C_DUTYCYCLE_16_9              I2C_CCR_DUTY
-/**
-  * @}
-  */
-
-/** @defgroup I2C_addressing_mode I2C addressing mode
-  * @{
-  */
-#define I2C_ADDRESSINGMODE_7BIT         ((uint32_t)0x00004000)
-#define I2C_ADDRESSINGMODE_10BIT        (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
-  * @{
-  */
-#define I2C_DUALADDRESS_DISABLE         ((uint32_t)0x00000000)
-#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_ENDUAL
-/**
-  * @}
-  */
-
-/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
-  * @{
-  */
-#define I2C_GENERALCALL_DISABLE         ((uint32_t)0x00000000)
-#define I2C_GENERALCALL_ENABLE          I2C_CR1_ENGC
-/**
-  * @}
-  */
-
-/** @defgroup I2C_nostretch_mode I2C nostretch mode
-  * @{
-  */
-#define I2C_NOSTRETCH_DISABLE           ((uint32_t)0x00000000)
-#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
-  * @{
-  */
-#define I2C_MEMADD_SIZE_8BIT            ((uint32_t)0x00000001)
-#define I2C_MEMADD_SIZE_16BIT           ((uint32_t)0x00000010)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
-  * @{
-  */
-#define I2C_IT_BUF                      I2C_CR2_ITBUFEN
-#define I2C_IT_EVT                      I2C_CR2_ITEVTEN
-#define I2C_IT_ERR                      I2C_CR2_ITERREN
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Flag_definition I2C Flag definition
-  * @brief I2C Interrupt definition
-  *           - 0001XXXX  : Flag control mask for SR1 Register
-  *           - 0010XXXX  : Flag control mask for SR2 Register
-  * @{
-  */
-#define I2C_FLAG_SMBALERT               ((uint32_t)0x00018000)
-#define I2C_FLAG_TIMEOUT                ((uint32_t)0x00014000)
-#define I2C_FLAG_PECERR                 ((uint32_t)0x00011000)
-#define I2C_FLAG_OVR                    ((uint32_t)0x00010800)
-#define I2C_FLAG_AF                     ((uint32_t)0x00010400)
-#define I2C_FLAG_ARLO                   ((uint32_t)0x00010200)
-#define I2C_FLAG_BERR                   ((uint32_t)0x00010100)
-#define I2C_FLAG_TXE                    ((uint32_t)0x00010080)
-#define I2C_FLAG_RXNE                   ((uint32_t)0x00010040)
-#define I2C_FLAG_STOPF                  ((uint32_t)0x00010010)
-#define I2C_FLAG_ADD10                  ((uint32_t)0x00010008)
-#define I2C_FLAG_BTF                    ((uint32_t)0x00010004)
-#define I2C_FLAG_ADDR                   ((uint32_t)0x00010002)
-#define I2C_FLAG_SB                     ((uint32_t)0x00010001)
-#define I2C_FLAG_DUALF                  ((uint32_t)0x00100080)
-#define I2C_FLAG_SMBHOST                ((uint32_t)0x00100040)
-#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00100020)
-#define I2C_FLAG_GENCALL                ((uint32_t)0x00100010)
-#define I2C_FLAG_TRA                    ((uint32_t)0x00100004)
-#define I2C_FLAG_BUSY                   ((uint32_t)0x00100002)
-#define I2C_FLAG_MSL                    ((uint32_t)0x00100001)
-#define I2C_FLAG_MASK                   ((uint32_t)0x0000FFFF)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-  
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Macros I2C Exported Macros
-  * @{
-  */
-
-/** @brief Reset I2C handle state.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
-
-/** @brief  Enable the specified I2C interrupt.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable.
-  *         This parameter can be one of the following values:
-  *            @arg @ref I2C_IT_BUF Buffer interrupt enable
-  *            @arg @ref I2C_IT_EVT Event interrupt enable
-  *            @arg @ref I2C_IT_ERR Error interrupt enable
-  * @retval None
-  */
-#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)))
-
-/** @brief  Disable the specified I2C interrupt.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __INTERRUPT__: specifies the interrupt source to disable.
-  *         This parameter can be one of the following values:
-  *            @arg @ref I2C_IT_BUF Buffer interrupt enable
-  *            @arg @ref I2C_IT_EVT Event interrupt enable
-  *            @arg @ref I2C_IT_ERR Error interrupt enable
-  * @retval None
-  */
-#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)))
-
-/** @brief  Check whether the specified I2C interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __INTERRUPT__: specifies the I2C interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref I2C_IT_BUF Buffer interrupt enable
-  *            @arg @ref I2C_IT_EVT Event interrupt enable
-  *            @arg @ref I2C_IT_ERR Error interrupt enable
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
-  */
-#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Check whether the specified I2C flag is set or not.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg @ref I2C_FLAG_SMBALERT SMBus Alert flag
-  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow error flag
-  *            @arg @ref I2C_FLAG_PECERR PEC error in reception flag
-  *            @arg @ref I2C_FLAG_OVR Overrun/Underrun flag
-  *            @arg @ref I2C_FLAG_AF Acknowledge failure flag
-  *            @arg @ref I2C_FLAG_ARLO Arbitration lost flag
-  *            @arg @ref I2C_FLAG_BERR Bus error flag
-  *            @arg @ref I2C_FLAG_TXE Data register empty flag
-  *            @arg @ref I2C_FLAG_RXNE Data register not empty flag
-  *            @arg @ref I2C_FLAG_STOPF Stop detection flag
-  *            @arg @ref I2C_FLAG_ADD10 10-bit header sent flag
-  *            @arg @ref I2C_FLAG_BTF Byte transfer finished flag
-  *            @arg @ref I2C_FLAG_ADDR Address sent flag
-  *                                     Address matched flag
-  *            @arg @ref I2C_FLAG_SB Start bit flag
-  *            @arg @ref I2C_FLAG_DUALF Dual flag
-  *            @arg @ref I2C_FLAG_SMBHOST SMBus host header
-  *            @arg @ref I2C_FLAG_SMBDEFAULT SMBus default header
-  *            @arg @ref I2C_FLAG_GENCALL General call header flag
-  *            @arg @ref I2C_FLAG_TRA Transmitter/Receiver flag
-  *            @arg @ref I2C_FLAG_BUSY Bus busy flag
-  *            @arg @ref I2C_FLAG_MSL Master/Slave flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16)) == 0x01)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
-                                                 ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
-
-/** @brief  Clear the I2C pending flags which are cleared by writing 0 in a specific bit.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __FLAG__ specifies the flag to clear.
-  *         This parameter can be any combination of the following values:
-  *            @arg @ref I2C_FLAG_SMBALERT SMBus Alert flag
-  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow error flag
-  *            @arg @ref I2C_FLAG_PECERR PEC error in reception flag
-  *            @arg @ref I2C_FLAG_OVR Overrun/Underrun flag (Slave mode)
-  *            @arg @ref I2C_FLAG_AF Acknowledge failure flag
-  *            @arg @ref I2C_FLAG_ARLO Arbitration lost flag (Master mode)
-  *            @arg @ref I2C_FLAG_BERR Bus error flag
-  *   
-  * @retval None
-  */
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__)  (__HANDLE__)->Instance->SR1 = (((__HANDLE__)->Instance->SR1) & (~((__FLAG__) & I2C_FLAG_MASK)))
-
-/** @brief  Clears the I2C ADDR pending flag.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
- do{                                         \
-    __IO uint32_t tmpreg;                    \
-    tmpreg = (__HANDLE__)->Instance->SR1;    \
-    tmpreg = (__HANDLE__)->Instance->SR2;    \
-    UNUSED(tmpreg);                          \
-}while(0)
-
-/** @brief  Clears the I2C STOPF pending flag.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__)               \
-do{                                                        \
-    __IO uint32_t tmpreg;                                  \
-    tmpreg = (__HANDLE__)->Instance->SR1;                  \
-    tmpreg = (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE;    \
-    UNUSED(tmpreg);                                        \
-}while(0)  
-
-/** @brief  Enable the specified I2C peripheral.
-  * @param  __HANDLE__ specifies the I2C Handle. 
-  * @retval None
-  */
-#define __HAL_I2C_ENABLE(__HANDLE__)                             (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))
-
-/** @brief  Disable the specified I2C peripheral.
-  * @param  __HANDLE__ specifies the I2C Handle. 
-  * @retval None
-  */
-#define __HAL_I2C_DISABLE(__HANDLE__)                            (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/**
-  * @}
-  */ 
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2C_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-  
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
-  * @{
-  */
-   
-/* IO operation functions  ****************************************************/
-
- /******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
-   
- /******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
- 
- /******* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-/**
-  * @}
-  */ 
-
-/** @addtogroup I2C_Exported_Functions_Group4 IRQ Handler and Callbacks
- * @{
- */   
-/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
-
-/**
-  * @}
-  */ 
-
-  
-/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
-  * @{
-  */
-  
-/* Peripheral State and Errors functions  *************************************/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Constants I2C Private Constants
-  * @{
-  */
-#define I2C_STANDARD_MODE_MAX_CLK ((uint32_t)100000) /* Standard Clock Up to 100kHz */
-#define I2C_FAST_MODE_MAX_CLK     ((uint32_t)400000) /* Fast Clock up to 400kHz */
-/**
-  * @}
-  */ 
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Macro I2C Private Macros
-  * @{
-  */
-#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
-                                         ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
-
-#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
-                                      ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
-
-#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
-                                   ((CALL) == I2C_GENERALCALL_ENABLE))
-
-#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
-                                  ((SIZE) == I2C_MEMADD_SIZE_16BIT))
-
-#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
-                                    ((STRETCH) == I2C_NOSTRETCH_ENABLE))
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0)
-
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0)
-
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= I2C_FAST_MODE_MAX_CLK))
-
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
-                                  ((CYCLE) == I2C_DUTYCYCLE_16_9))
-
-#define I2C_FREQ_RANGE(__PCLK__)                 ((__PCLK__)/1000000)
-#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__)  (((__SPEED__) <= I2C_STANDARD_MODE_MAX_CLK) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1))
-
-#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__)            (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1)))
-#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9))
-#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)      (((__SPEED__) <= 100000)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
-                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \
-                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
-
-#define I2C_MEM_ADD_MSB(__ADDRESS__)             ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__)             ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
-                                              
-#define I2C_7BIT_ADD_WRITE(__ADDRESS__)          ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
-#define I2C_7BIT_ADD_READ(__ADDRESS__)           ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
-
-#define I2C_10BIT_ADDRESS(__ADDRESS__)           ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
-#define I2C_10BIT_HEADER_WRITE(__ADDRESS__)      ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
-#define I2C_10BIT_HEADER_READ(__ADDRESS__)       ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
-/**
-  * @}
-  */ 
-
-/* Private Fonctions ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Functions I2C Private Functions
-  * @{
-  */
-/* Private functions are defined in stm32f1xx_hal_i2c.c file */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F1xx_HAL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_i2s.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,475 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_i2s.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of I2S HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_I2S_H
-#define __STM32F1xx_HAL_I2S_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"  
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2S
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_Types I2S Exported Types
-  * @{
-  */
-
-/** 
-  * @brief I2S Init structure definition  
-  */
-typedef struct
-{
-  uint32_t Mode;         /*!< Specifies the I2S operating mode.
-                              This parameter can be a value of @ref I2S_Mode */
-
-  uint32_t Standard;     /*!< Specifies the standard used for the I2S communication.
-                              This parameter can be a value of @ref I2S_Standard */
-
-  uint32_t DataFormat;   /*!< Specifies the data format for the I2S communication.
-                              This parameter can be a value of @ref I2S_Data_Format */
-
-  uint32_t MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
-                              This parameter can be a value of @ref I2S_MCLK_Output */
-
-  uint32_t AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
-                              This parameter can be a value of @ref I2S_Audio_Frequency */
-
-  uint32_t CPOL;         /*!< Specifies the idle state of the I2S clock.
-                              This parameter can be a value of @ref I2S_Clock_Polarity */
-
-}I2S_InitTypeDef;
-
-/** 
-  * @brief  HAL State structures definition
-  */ 
-typedef enum
-{
-  HAL_I2S_STATE_RESET      = 0x00,  /*!< I2S not yet initialized or disabled                */
-  HAL_I2S_STATE_READY      = 0x01,  /*!< I2S initialized and ready for use                  */
-  HAL_I2S_STATE_BUSY       = 0x02,  /*!< I2S internal process is ongoing                    */   
-  HAL_I2S_STATE_BUSY_TX    = 0x12,  /*!< Data Transmission process is ongoing               */ 
-  HAL_I2S_STATE_BUSY_RX    = 0x22,  /*!< Data Reception process is ongoing                  */
-  HAL_I2S_STATE_TIMEOUT    = 0x03,  /*!< I2S timeout state                                  */ 
-  HAL_I2S_STATE_ERROR      = 0x04   /*!< I2S error state                                    */      
-}HAL_I2S_StateTypeDef;
-
-/** 
-  * @brief I2S handle Structure definition  
-  */
-typedef struct
-{
-  SPI_TypeDef                *Instance;    /* I2S registers base address        */
-
-  I2S_InitTypeDef            Init;         /* I2S communication parameters      */
-  
-  uint16_t                   *pTxBuffPtr;  /* Pointer to I2S Tx transfer buffer */
-  
-  __IO uint16_t              TxXferSize;   /* I2S Tx transfer size              */
-  
-  __IO uint16_t              TxXferCount;  /* I2S Tx transfer Counter           */
-  
-  uint16_t                   *pRxBuffPtr;  /* Pointer to I2S Rx transfer buffer */
-  
-  __IO uint16_t              RxXferSize;   /* I2S Rx transfer size              */
-  
-  __IO uint16_t              RxXferCount;  /* I2S Rx transfer counter 
-                                              (This field is initialized at the 
-                                               same value as transfer size at the 
-                                               beginning of the transfer and 
-                                               decremented when a sample is received. 
-                                               NbSamplesReceived = RxBufferSize-RxBufferCount) */
-
-  DMA_HandleTypeDef          *hdmatx;      /* I2S Tx DMA handle parameters      */
-
-  DMA_HandleTypeDef          *hdmarx;      /* I2S Rx DMA handle parameters      */
-  
-  __IO HAL_LockTypeDef       Lock;         /* I2S locking object                */
-  
-  __IO HAL_I2S_StateTypeDef  State;        /* I2S communication state           */
-
-  __IO uint32_t  ErrorCode;    /* I2S Error code                    */
-
-}I2S_HandleTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_Exported_Constants I2S Exported Constants
-  * @{
-  */
-
-/** @defgroup I2S_Error_Codes I2S Error Codes
-  * @{
-  */
-#define HAL_I2S_ERROR_NONE      ((uint32_t)0x00)    /*!< No error                    */
-#define HAL_I2S_ERROR_UDR       ((uint32_t)0x01)    /*!< I2S Underrun error          */
-#define HAL_I2S_ERROR_OVR       ((uint32_t)0x02)    /*!< I2S Overrun error           */
-#define HAL_I2S_ERROR_FRE       ((uint32_t)0x04)    /*!< I2S Frame format error      */
-#define HAL_I2S_ERROR_DMA       ((uint32_t)0x08)    /*!< DMA transfer error          */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup I2S_Mode I2S Mode
-  * @{
-  */
-#define I2S_MODE_SLAVE_TX                ((uint32_t) 0x00000000)
-#define I2S_MODE_SLAVE_RX                ((uint32_t) SPI_I2SCFGR_I2SCFG_0)
-#define I2S_MODE_MASTER_TX               ((uint32_t) SPI_I2SCFGR_I2SCFG_1)
-#define I2S_MODE_MASTER_RX               ((uint32_t)(SPI_I2SCFGR_I2SCFG_0 |\
-                                                     SPI_I2SCFGR_I2SCFG_1))
-
-/**
-  * @}
-  */
-  
-/** @defgroup I2S_Standard I2S Standard
-  * @{
-  */
-#define I2S_STANDARD_PHILIPS             ((uint32_t) 0x00000000)
-#define I2S_STANDARD_MSB                 ((uint32_t) SPI_I2SCFGR_I2SSTD_0)
-#define I2S_STANDARD_LSB                 ((uint32_t) SPI_I2SCFGR_I2SSTD_1)
-#define I2S_STANDARD_PCM_SHORT           ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
-                                                     SPI_I2SCFGR_I2SSTD_1))
-#define I2S_STANDARD_PCM_LONG            ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
-                                                     SPI_I2SCFGR_I2SSTD_1 |\
-                                                     SPI_I2SCFGR_PCMSYNC))
-
-/**
-  * @}
-  */
-  
-/** @defgroup I2S_Data_Format I2S Data Format
-  * @{
-  */
-#define I2S_DATAFORMAT_16B               ((uint32_t) 0x00000000)
-#define I2S_DATAFORMAT_16B_EXTENDED      ((uint32_t) SPI_I2SCFGR_CHLEN)
-#define I2S_DATAFORMAT_24B               ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
-#define I2S_DATAFORMAT_32B               ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
-/**
-  * @}
-  */
-
-/** @defgroup I2S_MCLK_Output I2S MCLK Output
-  * @{
-  */
-#define I2S_MCLKOUTPUT_ENABLE           ((uint32_t)SPI_I2SPR_MCKOE)
-#define I2S_MCLKOUTPUT_DISABLE          ((uint32_t)0x00000000)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
-  * @{
-  */
-#define I2S_AUDIOFREQ_192K               ((uint32_t)192000)
-#define I2S_AUDIOFREQ_96K                ((uint32_t)96000)
-#define I2S_AUDIOFREQ_48K                ((uint32_t)48000)
-#define I2S_AUDIOFREQ_44K                ((uint32_t)44100)
-#define I2S_AUDIOFREQ_32K                ((uint32_t)32000)
-#define I2S_AUDIOFREQ_22K                ((uint32_t)22050)
-#define I2S_AUDIOFREQ_16K                ((uint32_t)16000)
-#define I2S_AUDIOFREQ_11K                ((uint32_t)11025)
-#define I2S_AUDIOFREQ_8K                 ((uint32_t)8000)
-#define I2S_AUDIOFREQ_DEFAULT            ((uint32_t)2)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
-  * @{
-  */
-#define I2S_CPOL_LOW                    ((uint32_t)0x00000000)
-#define I2S_CPOL_HIGH                   ((uint32_t)SPI_I2SCFGR_CKPOL)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition
-  * @{
-  */
-#define I2S_IT_TXE                      SPI_CR2_TXEIE
-#define I2S_IT_RXNE                     SPI_CR2_RXNEIE
-#define I2S_IT_ERR                      SPI_CR2_ERRIE
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Flag_definition I2S Flag definition
-  * @{
-  */
-#define I2S_FLAG_TXE                    SPI_SR_TXE
-#define I2S_FLAG_RXNE                   SPI_SR_RXNE
-
-#define I2S_FLAG_UDR                    SPI_SR_UDR
-#define I2S_FLAG_OVR                    SPI_SR_OVR
-#define I2S_FLAG_FRE                    SPI_SR_FRE
-
-#define I2S_FLAG_CHSIDE                 SPI_SR_CHSIDE
-#define I2S_FLAG_BSY                    SPI_SR_BSY
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_macros I2S Exported Macros
-  * @{
-  */
-
-/** @brief  Reset I2S handle state
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
-
-/** @brief  Enable the specified SPI peripheral (in I2S mode).
-  * @param  __HANDLE__: specifies the I2S Handle. 
-  * @retval None
-  */
-#define __HAL_I2S_ENABLE(__HANDLE__)    (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-
-/** @brief  Disable the specified SPI peripheral (in I2S mode).
-  * @param  __HANDLE__: specifies the I2S Handle. 
-  * @retval None
-  */
-#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-
-/** @brief  Enable the specified I2S interrupts.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval None
-  */  
-#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__)    (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
-
-/** @brief  Disable the specified I2S interrupts.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval None
-  */ 
-#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
- 
-/** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
-  * @param  __INTERRUPT__: specifies the I2S interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks whether the specified I2S flag is set or not.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
-  *            @arg I2S_FLAG_UDR: Underrun flag
-  *            @arg I2S_FLAG_OVR: Overrun flag
-  *            @arg I2S_FLAG_CHSIDE: Channel Side flag
-  *            @arg I2S_FLAG_BSY: Busy flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clears the I2S OVR pending flag.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @retval None
-  */                                                                                                   
-#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{__IO uint32_t tmpreg = (__HANDLE__)->Instance->DR;\
-                                                             tmpreg = (__HANDLE__)->Instance->SR;\
-                                                             UNUSED(tmpreg); \
-                                              }while(0)
-/** @brief Clears the I2S UDR pending flag.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
-/**
-  * @}
-  */ 
-                                                
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_Exported_Functions
-  * @{
-  */
-                                                
-/** @addtogroup I2S_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions  ***************************************************/
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-
- /* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
-
-/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
-void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control and State functions  ************************************/
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2S_Private_Macros I2S Private Macros
-  * @{
-  */
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX)  || \
-                           ((MODE) == I2S_MODE_SLAVE_RX)  || \
-                           ((MODE) == I2S_MODE_MASTER_TX) || \
-                           ((MODE) == I2S_MODE_MASTER_RX))
-
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS)   || \
-                                   ((STANDARD) == I2S_STANDARD_MSB)       || \
-                                   ((STANDARD) == I2S_STANDARD_LSB)       || \
-                                   ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
-                                   ((STANDARD) == I2S_STANDARD_PCM_LONG))
-
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B)          || \
-                                    ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
-                                    ((FORMAT) == I2S_DATAFORMAT_24B)          || \
-                                    ((FORMAT) == I2S_DATAFORMAT_32B))
-
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
-                                    ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
-
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K)    && \
-                                  ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
-                                  ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
-
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
-                           ((CPOL) == I2S_CPOL_HIGH))
-/**
-  * @}
-  */
-
-/* Private Fonctions ---------------------------------------------------------*/
-/** @defgroup I2S_Private_Functions I2S Private Functions
-  * @{
-  */
-/* Private functions are defined in stm32f1xx_hal_i2s.c file */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_I2S_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_irda.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,559 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_irda.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of IRDA HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_IRDA_H
-#define __STM32F1xx_HAL_IRDA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup IRDA
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup IRDA_Exported_Types IRDA Exported Types
-  * @{
-  */ 
-
-/**
-  * @brief IRDA Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
-                                           The baud rate is computed using the following formula:
-                                           - IntegerDivider = ((PCLKx) / (16 * (hirda->Init.BaudRate)))
-                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref IRDA_Word_Length */
-
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref IRDA_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits). */
- 
-  uint32_t Mode;                      /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref IRDA_Transfer_Mode */
-                                            
-  uint8_t  Prescaler;                 /*!< Specifies the Prescaler value prescaler value to be programmed 
-                                           in the IrDA low-power Baud Register, for defining pulse width on which
-                                           burst acceptance/rejection will be decided. This value is used as divisor 
-                                           of system clock to achieve required pulse width. */
-  
-  uint32_t IrDAMode;                  /*!< Specifies the IrDA mode
-                                           This parameter can be a value of @ref IRDA_Low_Power */
-}IRDA_InitTypeDef;
-
-/** 
-  * @brief HAL IRDA State structures definition  
-  */ 
-typedef enum
-{
-  HAL_IRDA_STATE_RESET             = 0x00,    /*!< Peripheral is not initialized */
-  HAL_IRDA_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
-  HAL_IRDA_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing */
-  HAL_IRDA_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing */
-  HAL_IRDA_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing */
-  HAL_IRDA_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
-  HAL_IRDA_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
-  HAL_IRDA_STATE_ERROR             = 0x04     /*!< Error */
-}HAL_IRDA_StateTypeDef;
-
-
-/** 
-  * @brief  IRDA handle Structure definition  
-  */  
-typedef struct
-{
-  USART_TypeDef               *Instance;        /*!< USART registers base address       */
-  
-  IRDA_InitTypeDef            Init;             /*!< IRDA communication parameters      */
-  
-  uint8_t                     *pTxBuffPtr;      /*!< Pointer to IRDA Tx transfer Buffer */
-  
-  uint16_t                    TxXferSize;       /*!< IRDA Tx Transfer size              */
-  
-  uint16_t                    TxXferCount;      /*!< IRDA Tx Transfer Counter           */
-  
-  uint8_t                     *pRxBuffPtr;      /*!< Pointer to IRDA Rx transfer Buffer */
-  
-  uint16_t                    RxXferSize;       /*!< IRDA Rx Transfer size              */
-  
-  uint16_t                    RxXferCount;      /*!< IRDA Rx Transfer Counter           */  
-  
-  DMA_HandleTypeDef           *hdmatx;          /*!< IRDA Tx DMA Handle parameters      */
-    
-  DMA_HandleTypeDef           *hdmarx;          /*!< IRDA Rx DMA Handle parameters      */
-  
-  HAL_LockTypeDef             Lock;             /*!< Locking object                     */
-  
-  __IO HAL_IRDA_StateTypeDef  State;            /*!< IRDA communication state           */
-  
-  __IO uint32_t  ErrorCode;        /*!< IRDA Error code                    */
-  
-}IRDA_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Constants IRDA Exported constants
-  * @{
-  */
-
-/** @defgroup IRDA_Error_Codes IRDA Error Codes
-  * @{
-  */
-#define HAL_IRDA_ERROR_NONE      ((uint32_t)0x00)    /*!< No error            */
-#define HAL_IRDA_ERROR_PE        ((uint32_t)0x01)    /*!< Parity error        */
-#define HAL_IRDA_ERROR_NE        ((uint32_t)0x02)    /*!< Noise error         */
-#define HAL_IRDA_ERROR_FE        ((uint32_t)0x04)    /*!< frame error         */
-#define HAL_IRDA_ERROR_ORE       ((uint32_t)0x08)    /*!< Overrun error       */
-#define HAL_IRDA_ERROR_DMA       ((uint32_t)0x10)    /*!< DMA transfer error  */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup IRDA_Word_Length IRDA Word Length
-  * @{
-  */
-#define IRDA_WORDLENGTH_8B                  ((uint32_t)0x00000000)
-#define IRDA_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
-/**
-  * @}
-  */
-
-
-/** @defgroup IRDA_Parity IRDA Parity 
-  * @{
-  */ 
-#define IRDA_PARITY_NONE                    ((uint32_t)0x00000000)
-#define IRDA_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
-#define IRDA_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode  
-  * @{
-  */ 
-#define IRDA_MODE_RX                        ((uint32_t)USART_CR1_RE)
-#define IRDA_MODE_TX                        ((uint32_t)USART_CR1_TE)
-#define IRDA_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Low_Power IRDA Low Power 
-  * @{
-  */
-#define IRDA_POWERMODE_LOWPOWER             ((uint32_t)USART_CR3_IRLP)
-#define IRDA_POWERMODE_NORMAL               ((uint32_t)0x00000000)
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Flags IRDA Flags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the SR register
-  * @{
-  */
-#define IRDA_FLAG_TXE                       ((uint32_t)USART_SR_TXE)
-#define IRDA_FLAG_TC                        ((uint32_t)USART_SR_TC)
-#define IRDA_FLAG_RXNE                      ((uint32_t)USART_SR_RXNE)
-#define IRDA_FLAG_IDLE                      ((uint32_t)USART_SR_IDLE)
-#define IRDA_FLAG_ORE                       ((uint32_t)USART_SR_ORE)
-#define IRDA_FLAG_NE                        ((uint32_t)USART_SR_NE)
-#define IRDA_FLAG_FE                        ((uint32_t)USART_SR_FE)
-#define IRDA_FLAG_PE                        ((uint32_t)USART_SR_PE)
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
-  *        Elements values convention: 0xY000XXXX
-  *           - XXXX  : Interrupt mask (16 bits) in the Y register
-  *           - Y  : Interrupt source register (4 bits)
-  *                 - 0001: CR1 register
-  *                 - 0010: CR2 register
-  *                 - 0011: CR3 register
-  *
-  * @{
-  */
-
-#define IRDA_IT_PE                          ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
-#define IRDA_IT_TXE                         ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
-#define IRDA_IT_TC                          ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
-#define IRDA_IT_RXNE                        ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
-#define IRDA_IT_IDLE                        ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
-
-#define IRDA_IT_LBD                         ((uint32_t)(IRDA_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
-
-#define IRDA_IT_CTS                         ((uint32_t)(IRDA_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
-#define IRDA_IT_ERR                         ((uint32_t)(IRDA_CR3_REG_INDEX << 28 | USART_CR3_EIE))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-    
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
-  * @{
-  */
-
-/** @brief Reset IRDA handle state
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
-
-/** @brief  Flush the IRDA DR register 
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  */
-#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-
-/** @brief  Check whether the specified IRDA flag is set or not.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __FLAG__: specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg IRDA_FLAG_TXE:  Transmit data register empty flag
-  *            @arg IRDA_FLAG_TC:   Transmission Complete flag
-  *            @arg IRDA_FLAG_RXNE: Receive data register not empty flag
-  *            @arg IRDA_FLAG_IDLE: Idle Line detection flag
-  *            @arg IRDA_FLAG_ORE:  OverRun Error flag
-  *            @arg IRDA_FLAG_NE:   Noise Error flag
-  *            @arg IRDA_FLAG_FE:   Framing Error flag
-  *            @arg IRDA_FLAG_PE:   Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the specified IRDA pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __FLAG__: specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg IRDA_FLAG_TC:   Transmission Complete flag.
-  *            @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
-  *   
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
-  *          error) and IDLE (Idle line detected) flags are cleared by software 
-  *          sequence: a read operation to USART_SR register followed by a read
-  *          operation to USART_DR register.
-  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to 
-  *          USART_SR register followed by a write operation to USART_DR register.
-  * @note   TXE flag is cleared only by a write to the USART_DR register.
-  *   
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief  Clear the IRDA PE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) \
-do{                                         \
-  __IO uint32_t tmpreg;                     \
-  tmpreg = (__HANDLE__)->Instance->SR;      \
-  tmpreg = (__HANDLE__)->Instance->DR;      \
-  UNUSED(tmpreg);                           \
-  }while(0)                                 \
-    
-/** @brief  Clear the IRDA FE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the IRDA NE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the IRDA ORE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the IRDA IDLE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Enable the specified IRDA interrupt.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __INTERRUPT__: specifies the IRDA interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg IRDA_IT_TC:   Transmission complete interrupt
-  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg IRDA_IT_IDLE: Idle line detection interrupt
-  *            @arg IRDA_IT_PE:   Parity Error interrupt
-  *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & IRDA_IT_MASK)): \
-                                                           ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
-
-/** @brief  Disable the specified IRDA interrupt.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __INTERRUPT__: specifies the IRDA interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg IRDA_IT_TC:   Transmission complete interrupt
-  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg IRDA_IT_IDLE: Idle line detection interrupt
-  *            @arg IRDA_IT_PE:   Parity Error interrupt
-  *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
-                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
-    
-/** @brief  Check whether the specified IRDA interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __IT__: specifies the IRDA interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
-  *            @arg IRDA_IT_TC:  Transmission complete interrupt
-  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg IRDA_IT_IDLE: Idle line detection interrupt
-  *            @arg IRDA_IT_ERR: Error interrupt
-  *            @arg IRDA_IT_PE: Parity Error interrupt
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == IRDA_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:((((__IT__) >> 28) == IRDA_CR2_REG_INDEX)? \
-                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
-
-/** @brief  Enable UART/USART associated to IRDA Handle
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */ 
-#define __HAL_IRDA_ENABLE(__HANDLE__)                   (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
-
-/** @brief  Disable UART/USART associated to IRDA Handle
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_IRDA_DISABLE(__HANDLE__)                  (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
-
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup IRDA_Private_Macros   IRDA Private Macros
-  * @{
-  */
-
-#define IRDA_CR1_REG_INDEX                  1    
-#define IRDA_CR2_REG_INDEX                  2    
-#define IRDA_CR3_REG_INDEX                  3    
-
-#define IRDA_DIV(__PCLK__, __BAUD__)                    (((__PCLK__)*25)/(4*(__BAUD__)))
-#define IRDA_DIVMANT(__PCLK__, __BAUD__)                (IRDA_DIV((__PCLK__), (__BAUD__))/100)
-#define IRDA_DIVFRAQ(__PCLK__, __BAUD__)                (((IRDA_DIV((__PCLK__), (__BAUD__)) - (IRDA_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100)
-/* UART BRR = mantissa + overflow + fraction
-            = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0F) */
-#define IRDA_BRR(_PCLK_, _BAUD_)            (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4) + \
-                                             (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0)) + \
-                                             (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
-
-/** Ensure that IRDA Baud rate is less or equal to maximum value
-  *    __BAUDRATE__: specifies the IRDA Baudrate set by the user.
-  *                  The maximum Baud Rate is 115200bps 
-  * Returns : True or False
-  */   
-#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
-
-#define IS_IRDA_WORD_LENGTH(LENGTH)    (((LENGTH) == IRDA_WORDLENGTH_8B) || \
-                                        ((LENGTH) == IRDA_WORDLENGTH_9B))
-
-#define IS_IRDA_PARITY(PARITY)         (((PARITY) == IRDA_PARITY_NONE) || \
-                                        ((PARITY) == IRDA_PARITY_EVEN) || \
-                                        ((PARITY) == IRDA_PARITY_ODD))
-
-#define IS_IRDA_MODE(MODE)             ((((MODE) & (~((uint32_t)IRDA_MODE_TX_RX))) == 0x00) && \
-                                        ((MODE) != (uint32_t)0x00000000))
-
-#define IS_IRDA_POWERMODE(MODE)        (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
-                                        ((MODE) == IRDA_POWERMODE_NORMAL))
-
-/** IRDA interruptions flag mask
-  * 
-  */ 
-#define IRDA_IT_MASK  ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
-                                  USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
-  * @{
-  */
-  
-/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
-
-/**
-  * @}
-  */
-
-/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions 
-  * @{
-  */
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
-
-/**
-  * @}
-  */
-
-/** @addtogroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions 
-  * @{
-  */
-
-/* Peripheral State and Error functions ***************************************/
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
-uint32_t              HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_IRDA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_iwdg.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,299 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_iwdg.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of IWDG HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_IWDG_H
-#define __STM32F1xx_HAL_IWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup IWDG
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup IWDG_Exported_Types IWDG Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  IWDG HAL State Structure definition  
-  */ 
-typedef enum
-{
-  HAL_IWDG_STATE_RESET     = 0x00,  /*!< IWDG not yet initialized or disabled */
-  HAL_IWDG_STATE_READY     = 0x01,  /*!< IWDG initialized and ready for use   */
-  HAL_IWDG_STATE_BUSY      = 0x02,  /*!< IWDG internal process is ongoing     */
-  HAL_IWDG_STATE_TIMEOUT   = 0x03,  /*!< IWDG timeout state                   */
-  HAL_IWDG_STATE_ERROR     = 0x04   /*!< IWDG error state                     */
-    
-}HAL_IWDG_StateTypeDef;
-
-/** 
-  * @brief  IWDG Init structure definition  
-  */ 
-typedef struct
-{
-  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.  
-                            This parameter can be a value of @ref IWDG_Prescaler */
-  
-  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value. 
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
-
-}IWDG_InitTypeDef;
-
-/** 
-  * @brief  IWDG Handle Structure definition  
-  */ 
-typedef struct
-{
-  IWDG_TypeDef                 *Instance;  /*!< Register base address    */ 
-  
-  IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
-  
-  HAL_LockTypeDef              Lock;       /*!< IWDG Locking object      */
-  
-  __IO HAL_IWDG_StateTypeDef   State;      /*!< IWDG communication state */
-  
-}IWDG_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
-  * @{
-  */
-
-/** @defgroup IWDG_Registers_BitMask IWDG Registers BitMask
-  * @brief IWDG registers bit mask
-  * @{
-  */
-/* --- KR Register ---*/
-/* KR register bit mask */
-#define IWDG_KEY_RELOAD               ((uint32_t)0xAAAA)  /*!< IWDG Reload Counter Enable   */
-#define IWDG_KEY_ENABLE               ((uint32_t)0xCCCC)  /*!< IWDG Peripheral Enable       */
-#define IWDG_KEY_WRITE_ACCESS_ENABLE  ((uint32_t)0x5555)  /*!< IWDG KR Write Access Enable  */
-#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x0000)  /*!< IWDG KR Write Access Disable */
-
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Flag_definition IWDG Flag definition
-  * @{
-  */ 
-#define IWDG_FLAG_PVU   ((uint32_t)IWDG_SR_PVU)  /*!< Watchdog counter prescaler value update Flag */
-#define IWDG_FLAG_RVU   ((uint32_t)IWDG_SR_RVU)  /*!< Watchdog counter reload value update Flag    */
-
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Prescaler IWDG Prescaler
-  * @{
-  */ 
-#define IWDG_PRESCALER_4     ((uint8_t)0x00)  /*!< IWDG prescaler set to 4   */
-#define IWDG_PRESCALER_8     ((uint8_t)(IWDG_PR_PR_0))                  /*!< IWDG prescaler set to 8   */
-#define IWDG_PRESCALER_16    ((uint8_t)(IWDG_PR_PR_1))                  /*!< IWDG prescaler set to 16  */
-#define IWDG_PRESCALER_32    ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0))   /*!< IWDG prescaler set to 32  */
-#define IWDG_PRESCALER_64    ((uint8_t)(IWDG_PR_PR_2))                  /*!< IWDG prescaler set to 64  */
-#define IWDG_PRESCALER_128   ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0))   /*!< IWDG prescaler set to 128 */
-#define IWDG_PRESCALER_256   ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1))   /*!< IWDG prescaler set to 256 */
-
-/**
-  * @}
-  */ 
-
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
-  * @{
-  */
-
-/** @brief Reset IWDG handle state
-  * @param  __HANDLE__: IWDG handle.
-  * @retval None
-  */
-#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
-
-/**
-  * @brief  Enables the IWDG peripheral.
-  * @param  __HANDLE__: IWDG handle
-  * @retval None
-  */
-#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
-
-/**
-  * @brief  Reloads IWDG counter with value defined in the reload register
-  *         (write access to IWDG_PR and IWDG_RLR registers disabled).
-  * @param  __HANDLE__: IWDG handle
-  * @retval None
-  */
-#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
-
-
-
-/**
-  * @brief  Gets the selected IWDG's flag status.
-  * @param  __HANDLE__: IWDG handle
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
-  *            @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @}
-  */ 
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup IWDG_Private_Macros IWDG Private Macros
-  * @{
-  */
-
-
-/**
-  * @brief  Enables write access to IWDG_PR and IWDG_RLR registers.
-  * @param  __HANDLE__: IWDG handle
-  * @retval None
-  */
-#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
-
-/**
-  * @brief  Disables write access to IWDG_PR and IWDG_RLR registers.
-  * @param  __HANDLE__: IWDG handle
-  * @retval None
-  */
-#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
-
-
-#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_16) || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_32) || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_64) || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_256))
-
-
-#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
-
-
-/**
-  * @}
-  */
-
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup IWDG_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup IWDG_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
-void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
-
-/**
-  * @}
-  */
-  
-/** @addtogroup IWDG_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
-
-/**
-  * @}
-  */
-  
-/** @addtogroup IWDG_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State functions  ************************************************/
-HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_nand.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,304 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_nand.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of NAND HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_NAND_H
-#define __STM32F1xx_HAL_NAND_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_fsmc.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
-/** @addtogroup NAND
-  * @{
-  */ 
-
-/** @addtogroup NAND_Private_Constants
-  * @{
-  */
-
-#define NAND_DEVICE1               FSMC_BANK2
-#define NAND_DEVICE2               FSMC_BANK3
-#define NAND_WRITE_TIMEOUT         ((uint32_t)1000)
-
-#define CMD_AREA                   ((uint32_t)(1<<16))  /* A16 = CLE high */
-#define ADDR_AREA                  ((uint32_t)(1<<17))  /* A17 = ALE high */
-
-#define NAND_CMD_AREA_A            ((uint8_t)0x00)
-#define NAND_CMD_AREA_B            ((uint8_t)0x01)
-#define NAND_CMD_AREA_C            ((uint8_t)0x50)
-#define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
-
-#define NAND_CMD_WRITE0            ((uint8_t)0x80)
-#define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)  
-#define NAND_CMD_ERASE0            ((uint8_t)0x60)
-#define NAND_CMD_ERASE1            ((uint8_t)0xD0)  
-#define NAND_CMD_READID            ((uint8_t)0x90)  
-#define NAND_CMD_STATUS            ((uint8_t)0x70)
-#define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
-#define NAND_CMD_RESET             ((uint8_t)0xFF)
-
-/* NAND memory status */
-#define NAND_VALID_ADDRESS         ((uint32_t)0x00000100)
-#define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200)
-#define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400)
-#define NAND_BUSY                  ((uint32_t)0x00000000)
-#define NAND_ERROR                 ((uint32_t)0x00000001)
-#define NAND_READY                 ((uint32_t)0x00000040)
-
-/**
-  * @}
-  */
-
-/** @addtogroup NAND_Private_Macros
-  * @{
-  */
-
-/**
-  * @brief  NAND memory address computation.
-  * @param  __ADDRESS__: NAND memory address.
-  * @param  __HANDLE__ : NAND handle.
-  * @retval NAND Raw address value
-  */
-#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
-                         (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
-   
-/**
-  * @brief  NAND memory address cycling.
-  * @param  __ADDRESS__: NAND memory address.
-  * @retval NAND address cycling value.
-  */
-#define ADDR_1st_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
-#define ADDR_2nd_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
-#define ADDR_3rd_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
-#define ADDR_4th_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
-
-/**
-  * @}
-  */
-
-/* Exported typedef ----------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup NAND_Exported_Types NAND Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  HAL NAND State structures definition
-  */
-typedef enum
-{
-  HAL_NAND_STATE_RESET     = 0x00,  /*!< NAND not yet initialized or disabled */
-  HAL_NAND_STATE_READY     = 0x01,  /*!< NAND initialized and ready for use   */
-  HAL_NAND_STATE_BUSY      = 0x02,  /*!< NAND internal process is ongoing     */
-  HAL_NAND_STATE_ERROR     = 0x03   /*!< NAND error state                     */
-}HAL_NAND_StateTypeDef;
-   
-/** 
-  * @brief  NAND Memory electronic signature Structure definition
-  */
-typedef struct
-{
-  /*<! NAND memory electronic signature maker and device IDs */
-
-  uint8_t Maker_Id; 
-
-  uint8_t Device_Id;
-
-  uint8_t Third_Id;
-
-  uint8_t Fourth_Id;
-}NAND_IDTypeDef;
-
-/** 
-  * @brief  NAND Memory address Structure definition
-  */
-typedef struct 
-{
-  uint16_t Page;   /*!< NAND memory Page address  */
-
-  uint16_t Zone;   /*!< NAND memory Zone address  */
-
-  uint16_t Block;  /*!< NAND memory Block address */
-
-}NAND_AddressTypeDef;
-
-/** 
-  * @brief  NAND Memory info Structure definition
-  */ 
-typedef struct
-{
-  uint32_t PageSize;       /*!< NAND memory page (without spare area) size measured in K. bytes */
-
-  uint32_t SpareAreaSize;  /*!< NAND memory spare area size measured in K. bytes                */
-
-  uint32_t BlockSize;      /*!< NAND memory block size number of pages                          */
-
-  uint32_t BlockNbr;       /*!< NAND memory number of blocks                                    */
-
-  uint32_t ZoneSize;       /*!< NAND memory zone size measured in number of blocks              */
-}NAND_InfoTypeDef;
-
-/** 
-  * @brief  NAND handle Structure definition
-  */   
-typedef struct
-{
-  FSMC_NAND_TypeDef             *Instance;  /*!< Register base address                        */
-  
-  FSMC_NAND_InitTypeDef         Init;       /*!< NAND device control configuration parameters */
-
-  HAL_LockTypeDef              Lock;       /*!< NAND locking object                          */
-
-  __IO HAL_NAND_StateTypeDef   State;      /*!< NAND device access state                     */
-
-  NAND_InfoTypeDef             Info;       /*!< NAND characteristic information structure    */
-}NAND_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup NAND_Exported_Macros NAND Exported Macros
- * @{
- */ 
-
-/** @brief Reset NAND handle state
-  * @param  __HANDLE__: specifies the NAND handle.
-  * @retval None
-  */
-#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup NAND_Exported_Functions NAND Exported Functions
-  * @{
-  */
-    
-/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @{
-  */
-
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef   HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
-HAL_StatusTypeDef   HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
-void                HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
-void                HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
-void                HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
-void                HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
-
-/**
-  * @}
-  */
-  
-/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions 
-  * @{
-  */
-
-/* IO operation functions  ****************************************************/
-HAL_StatusTypeDef   HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
-HAL_StatusTypeDef   HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef   HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef   HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef   HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef   HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
-HAL_StatusTypeDef   HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
-uint32_t            HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
-uint32_t            HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
-
-/**
-  * @}
-  */
-
-/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions 
-  * @{
-  */
-
-/* NAND Control functions  ****************************************************/
-HAL_StatusTypeDef   HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef   HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef   HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
-
-/**
-  * @}
-  */
-    
-/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions 
-  * @{
-  */
-
-/* NAND State functions *******************************************************/
-HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
-uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
-
-/**
-  * @}
-  */
-    
-/**
-  * @}
-  */
-    
-/**
-  * @}
-  */ 
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_NAND_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_nor.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,306 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_nor.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of NOR HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_NOR_H
-#define __STM32F1xx_HAL_NOR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_fsmc.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
-/** @addtogroup NOR
-  * @{
-  */ 
-
-/** @addtogroup NOR_Private_Constants
-  * @{
-  */
-
-/* NOR device IDs addresses */
-#define MC_ADDRESS               ((uint16_t)0x0000)
-#define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
-#define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
-#define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
-
-/* NOR CFI IDs addresses */
-#define CFI1_ADDRESS             ((uint16_t)0x10)
-#define CFI2_ADDRESS             ((uint16_t)0x11)
-#define CFI3_ADDRESS             ((uint16_t)0x12)
-#define CFI4_ADDRESS             ((uint16_t)0x13)
-
-/* NOR operation wait timeout */
-#define NOR_TMEOUT               ((uint16_t)0xFFFF)
-   
-/* NOR memory data width */
-#define NOR_MEMORY_8B            ((uint8_t)0x0)
-#define NOR_MEMORY_16B           ((uint8_t)0x1)
-
-/* NOR memory device read/write start address */
-#define NOR_MEMORY_ADRESS1       FSMC_BANK1_1
-#define NOR_MEMORY_ADRESS2       FSMC_BANK1_2
-#define NOR_MEMORY_ADRESS3       FSMC_BANK1_3
-#define NOR_MEMORY_ADRESS4       FSMC_BANK1_4
-
-/**
-  * @}
-  */
-
-/** @addtogroup NOR_Private_Macros
-  * @{
-  */
-
-/**
-  * @brief  NOR memory address shifting.
-  * @param  __NOR_ADDRESS: NOR base address 
-  * @param  __NOR_MEMORY_WIDTH_: NOR memory width
-  * @param  __ADDRESS__: NOR memory address 
-  * @retval NOR shifted address value
-  */
-#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)       \
-            ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?              \
-              ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):              \
-              ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
-
-/**
-  * @brief  NOR memory write data to specified address.
-  * @param  __ADDRESS__: NOR memory address 
-  * @param  __DATA__: Data to write
-  * @retval None
-  */
-#define NOR_WRITE(__ADDRESS__, __DATA__)  (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
-
-/**
-  * @}
-  */
-
-/* Exported typedef ----------------------------------------------------------*/ 
-/** @defgroup NOR_Exported_Types NOR Exported Types
-  * @{
-  */ 
-  
-/** 
-  * @brief  HAL SRAM State structures definition  
-  */ 
-typedef enum
-{  
-  HAL_NOR_STATE_RESET             = 0x00,  /*!< NOR not yet initialized or disabled  */
-  HAL_NOR_STATE_READY             = 0x01,  /*!< NOR initialized and ready for use    */
-  HAL_NOR_STATE_BUSY              = 0x02,  /*!< NOR internal processing is ongoing   */
-  HAL_NOR_STATE_ERROR             = 0x03,  /*!< NOR error state                      */ 
-  HAL_NOR_STATE_PROTECTED         = 0x04   /*!< NOR NORSRAM device write protected  */
-}HAL_NOR_StateTypeDef;    
-
-/**
-  * @brief  FSMC NOR Status typedef
-  */
-typedef enum
-{
-  HAL_NOR_STATUS_SUCCESS = 0,
-  HAL_NOR_STATUS_ONGOING,
-  HAL_NOR_STATUS_ERROR,
-  HAL_NOR_STATUS_TIMEOUT
-}HAL_NOR_StatusTypeDef; 
-
-/**
-  * @brief  FSMC NOR ID typedef
-  */
-typedef struct
-{
-  uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
-  
-  uint16_t Device_Code1;
-  
-  uint16_t Device_Code2;
-        
-  uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory. 
-                                    These codes can be accessed by performing read operations with specific 
-                                    control signals and addresses set.They can also be accessed by issuing 
-                                    an Auto Select command                                                   */    
-}NOR_IDTypeDef;
-
-/**
-  * @brief  FSMC NOR CFI typedef
-  */
-typedef struct
-{
-  /*!< Defines the information stored in the memory's Common flash interface
-       which contains a description of various electrical and timing parameters, 
-       density information and functions supported by the memory                   */
-  
-  uint16_t CFI_1;
-  
-  uint16_t CFI_2;
-  
-  uint16_t CFI_3;
-  
-  uint16_t CFI_4;
-}NOR_CFITypeDef;
-
-/** 
-  * @brief  NOR handle Structure definition  
-  */ 
-typedef struct
-{
-  FSMC_NORSRAM_TypeDef          *Instance;    /*!< Register base address                        */ 
-  
-  FSMC_NORSRAM_EXTENDED_TypeDef *Extended;    /*!< Extended mode register base address          */
-  
-  FSMC_NORSRAM_InitTypeDef      Init;         /*!< NOR device control configuration parameters  */
-
-  HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */ 
-  
-  __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
-   
-}NOR_HandleTypeDef; 
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup NOR_Exported_macro NOR Exported Macros
-  * @{
-  */
-
-/** @brief Reset NOR handle state
-  * @param  __HANDLE__: NOR handle
-  * @retval None
-  */
-#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup NOR_Exported_Functions NOR Exported Functions
- *  @{
- */
-
-/** @addtogroup NOR_Exported_Functions_Group1
- *  @{
- */
-
-/* Initialization/de-initialization functions  **********************************/  
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
-HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
-void              HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
-void              HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
-void              HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
-
-/**
-  * @}
-  */
-  
-/** @addtogroup NOR_Exported_Functions_Group2
- *  @{
- */
-
-/* I/O operation functions  ***************************************************/
-HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
-HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
-HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
-
-HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
-HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
-HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
-
-/**
-  * @}
-  */
-  
-/** @addtogroup NOR_Exported_Functions_Group3
- *  @{
- */
-
-/* NOR Control functions  *****************************************************/
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
-
-/**
-  * @}
-  */
-  
-/** @addtogroup NOR_Exported_Functions_Group4
- *  @{
- */
-
-/* NOR State functions ********************************************************/
-HAL_NOR_StateTypeDef  HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
-HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-  
-
-/**
-  * @}
-  */ 
-
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_NOR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_pccard.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,249 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_pccard.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of PCCARD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_PCCARD_H
-#define __STM32F1xx_HAL_PCCARD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_fsmc.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
-/** @addtogroup PCCARD
-  * @{
-  */ 
-
-/** @addtogroup PCCARD_Private_Constants
-  * @{
-  */
-  
-#define PCCARD_DEVICE_ADDRESS           FSMC_BANK4
-#define PCCARD_ATTRIBUTE_SPACE_ADDRESS  ((uint32_t)(FSMC_BANK4 + 0x08000000))  /* Attribute space size to @0x9BFF FFFF */
-#define PCCARD_COMMON_SPACE_ADDRESS     PCCARD_DEVICE_ADDRESS                           /* Common space size to @0x93FF FFFF    */
-#define PCCARD_IO_SPACE_ADDRESS         ((uint32_t)(FSMC_BANK4 + 0x0C000000))  /* IO space size to @0x9FFF FFFF        */
-#define PCCARD_IO_SPACE_PRIMARY_ADDR    ((uint32_t)(FSMC_BANK4 + 0x0C0001F0))  /* IO space size to @0x9FFF FFFF        */
-
-/* Compact Flash-ATA registers description */
-#define ATA_DATA                        ((uint8_t)0x00)    /* Data register */
-#define ATA_SECTOR_COUNT                ((uint8_t)0x02)    /* Sector Count register */
-#define ATA_SECTOR_NUMBER               ((uint8_t)0x03)    /* Sector Number register */
-#define ATA_CYLINDER_LOW                ((uint8_t)0x04)    /* Cylinder low register */
-#define ATA_CYLINDER_HIGH               ((uint8_t)0x05)    /* Cylinder high register */
-#define ATA_CARD_HEAD                   ((uint8_t)0x06)    /* Card/Head register */
-#define ATA_STATUS_CMD                  ((uint8_t)0x07)    /* Status(read)/Command(write) register */
-#define ATA_STATUS_CMD_ALTERNATE        ((uint8_t)0x0E)    /* Alternate Status(read)/Command(write) register */
-#define ATA_COMMON_DATA_AREA            ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
-#define ATA_CARD_CONFIGURATION          ((uint16_t)0x0202) /* Card Configuration and Status Register */
-
-/* Compact Flash-ATA commands */
-#define ATA_READ_SECTOR_CMD             ((uint8_t)0x20)
-#define ATA_WRITE_SECTOR_CMD            ((uint8_t)0x30)
-#define ATA_ERASE_SECTOR_CMD            ((uint8_t)0xC0)
-#define ATA_IDENTIFY_CMD                ((uint8_t)0xEC)
-
-/* Compact Flash status */
-#define PCCARD_TIMEOUT_ERROR            ((uint8_t)0x60)
-#define PCCARD_BUSY                     ((uint8_t)0x80)
-#define PCCARD_PROGR                    ((uint8_t)0x01)
-#define PCCARD_READY                    ((uint8_t)0x40)
-
-#define PCCARD_SECTOR_SIZE              ((uint32_t)255)    /* In half words */ 
- 
-
-/* Compact Flash redefinition */
-#define HAL_CF_Read_ID              HAL_PCCARD_Read_ID
-#define HAL_CF_Write_Sector         HAL_PCCARD_Write_Sector
-#define HAL_CF_Read_Sector          HAL_PCCARD_Read_Sector
-#define HAL_CF_Erase_Sector         HAL_PCCARD_Erase_Sector
-#define HAL_CF_Reset                HAL_PCCARD_Reset
-                                        
-#define HAL_CF_GetStatus            HAL_PCCARD_GetStatus
-#define HAL_CF_ReadStatus           HAL_PCCARD_ReadStatus
-                                        
-#define CF_SUCCESS                  HAL_PCCARD_STATUS_SUCCESS
-#define CF_ONGOING                  HAL_PCCARD_STATUS_ONGOING
-#define CF_ERROR                    HAL_PCCARD_STATUS_ERROR
-#define CF_TIMEOUT                  HAL_PCCARD_STATUS_TIMEOUT
-#define CF_StatusTypedef            HAL_PCCARD_StatusTypeDef
-
-
-#define CF_DEVICE_ADDRESS           PCCARD_DEVICE_ADDRESS               
-#define CF_ATTRIBUTE_SPACE_ADDRESS  PCCARD_ATTRIBUTE_SPACE_ADDRESS
-#define CF_COMMON_SPACE_ADDRESS     PCCARD_COMMON_SPACE_ADDRESS   
-#define CF_IO_SPACE_ADDRESS         PCCARD_IO_SPACE_ADDRESS       
-#define CF_IO_SPACE_PRIMARY_ADDR    PCCARD_IO_SPACE_PRIMARY_ADDR  
-
-#define CF_TIMEOUT_ERROR            PCCARD_TIMEOUT_ERROR
-#define CF_BUSY                     PCCARD_BUSY         
-#define CF_PROGR                    PCCARD_PROGR        
-#define CF_READY                    PCCARD_READY        
-
-#define CF_SECTOR_SIZE              PCCARD_SECTOR_SIZE
-
-/**
-  * @}
-  */ 
-
-/* Exported typedef ----------------------------------------------------------*/
-/** @defgroup PCCARD_Exported_Types PCCARD Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  HAL PCCARD State structures definition  
-  */ 
-typedef enum
-{
-  HAL_PCCARD_STATE_RESET     = 0x00,    /*!< PCCARD peripheral not yet initialized or disabled */
-  HAL_PCCARD_STATE_READY     = 0x01,    /*!< PCCARD peripheral ready                           */
-  HAL_PCCARD_STATE_BUSY      = 0x02,    /*!< PCCARD peripheral busy                            */   
-  HAL_PCCARD_STATE_ERROR     = 0x04     /*!< PCCARD peripheral error                           */
-}HAL_PCCARD_StateTypeDef;
-
-typedef enum
-{
-  HAL_PCCARD_STATUS_SUCCESS = 0,
-  HAL_PCCARD_STATUS_ONGOING,
-  HAL_PCCARD_STATUS_ERROR,
-  HAL_PCCARD_STATUS_TIMEOUT
-}HAL_PCCARD_StatusTypeDef;
-
-/** 
-  * @brief  FSMC_PCCARD handle Structure definition  
-  */   
-typedef struct
-{
-  FSMC_PCCARD_TypeDef           *Instance;              /*!< Register base address for PCCARD device          */
-  
-  FSMC_PCCARD_InitTypeDef       Init;                   /*!< PCCARD device control configuration parameters   */
-
-  __IO HAL_PCCARD_StateTypeDef State;                  /*!< PCCARD device access state                       */
-   
-  HAL_LockTypeDef              Lock;                   /*!< PCCARD Lock                                      */ 
- 
-}PCCARD_HandleTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
-  * @{
-  */
-
-/** @brief Reset PCCARD handle state
-  * @param  __HANDLE__: specifies the PCCARD handle.
-  * @retval None
-  */
-#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
-/**
-  * @}
-  */ 
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCCARD_Exported_Functions PCCARD Exported Functions
-  * @{
-  */
-
-/** @addtogroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @{
-  */
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef  HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
-HAL_StatusTypeDef  HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);   
-void               HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
-void               HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
-/**
-  * @}
-  */
-
-/** @addtogroup PCCARD_Exported_Functions_Group2 Input Output and memory functions 
-  * @{
-  */
-/* IO operation functions  *****************************************************/
-HAL_StatusTypeDef  HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
-HAL_StatusTypeDef  HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,  uint8_t *pStatus);
-HAL_StatusTypeDef  HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
-HAL_StatusTypeDef  HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
-HAL_StatusTypeDef  HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
-void               HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
-void               HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
-
-/**
-  * @}
-  */
-
-/** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions 
-  * @{
-  */
-/* PCCARD State functions *******************************************************/
-HAL_PCCARD_StateTypeDef  HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
-HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard);
-HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_PCCARD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_pcd.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,853 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_pcd.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of PCD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_PCD_H
-#define __STM32F1xx_HAL_PCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || \
-    defined(STM32F103x6) || defined(STM32F103xB) || \
-    defined(STM32F103xE) || defined(STM32F103xG) || \
-    defined(STM32F105xC) || defined(STM32F107xC)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_usb.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PCD
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup PCD_Exported_Types PCD Exported Types
-  * @{
-  */
-
-/**
-  * @brief  PCD State structure definition
-  */
-typedef enum
-{
-  HAL_PCD_STATE_RESET   = 0x00,
-  HAL_PCD_STATE_READY   = 0x01,
-  HAL_PCD_STATE_ERROR   = 0x02,
-  HAL_PCD_STATE_BUSY    = 0x03,
-  HAL_PCD_STATE_TIMEOUT = 0x04
-} PCD_StateTypeDef;
-
-#if defined (USB)
-/**
-  * @brief  PCD double buffered endpoint direction
-  */
-typedef enum
-{
-  PCD_EP_DBUF_OUT,
-  PCD_EP_DBUF_IN,
-  PCD_EP_DBUF_ERR,
-}PCD_EP_DBUF_DIR;
-
-/**
-  * @brief  PCD endpoint buffer number
-  */
-typedef enum 
-{
-  PCD_EP_NOBUF,
-  PCD_EP_BUF0,
-  PCD_EP_BUF1
-}PCD_EP_BUF_NUM;  
-#endif /* USB */
-
-#if defined (USB_OTG_FS)
-typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;
-typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;
-typedef USB_OTG_EPTypeDef      PCD_EPTypeDef;
-#endif /* USB_OTG_FS */
-
-#if defined (USB)
-typedef USB_TypeDef        PCD_TypeDef;
-typedef USB_CfgTypeDef     PCD_InitTypeDef;
-typedef USB_EPTypeDef      PCD_EPTypeDef;
-#endif /* USB */
-
-/** 
-  * @brief  PCD Handle Structure definition
-  */
-typedef struct
-{
-  PCD_TypeDef             *Instance;   /*!< Register base address               */
-  PCD_InitTypeDef         Init;        /*!< PCD required parameters             */
-  __IO uint8_t            USB_Address; /*!< USB Address: not used by USB OTG FS */  
-  PCD_EPTypeDef           IN_ep[15];   /*!< IN endpoint parameters              */
-  PCD_EPTypeDef           OUT_ep[15];  /*!< OUT endpoint parameters             */
-  HAL_LockTypeDef         Lock;        /*!< PCD peripheral status               */
-  __IO PCD_StateTypeDef   State;       /*!< PCD communication state             */
-  uint32_t                Setup[12];   /*!< Setup packet buffer                 */
-  void                    *pData;      /*!< Pointer to upper stack Handler      */
-} PCD_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Include PCD HAL Extension module */
-#include "stm32f1xx_hal_pcd_ex.h"
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
-  * @{
-  */
-
-/** @defgroup PCD_Speed PCD Speed
-  * @{
-  */
-#define PCD_SPEED_HIGH                                                0 /* Not Supported */
-#define PCD_SPEED_HIGH_IN_FULL                                        1 /* Not Supported */
-#define PCD_SPEED_FULL                                                2
-/**
-  * @}
-  */
-  
-/** @defgroup PCD_PHY_Module PCD PHY Module
-  * @{
-  */
-#define PCD_PHY_EMBEDDED                                              2
-/**
-  * @}
-  */
-
-/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
-  * @{
-  */
-#ifndef USBD_FS_TRDT_VALUE
- #define USBD_FS_TRDT_VALUE           5
-#endif /* USBD_FS_TRDT_VALUE */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PCD_Exported_Macros PCD Exported Macros
- *  @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-#if defined (USB_OTG_FS)
-
-#define __HAL_PCD_ENABLE(__HANDLE__)                                  USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_DISABLE(__HANDLE__)                                 USB_DisableGlobalInt ((__HANDLE__)->Instance)
-
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)                 ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)               (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
-#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)                    (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
-
-#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)                         *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
-                                                                      ~(USB_OTG_PCGCCTL_STOPCLK)
-
-#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)                           *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)                        ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()                      EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()                     EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG()                       EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG()                     EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE()                 \
-                        do{                                               \
-                            EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
-                            EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;    \
-                          } while(0)
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()                \
-                        do{                                               \
-                            EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);  \
-                            EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
-                          } while(0)
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()         \
-                        do{                                               \
-                            EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
-                            EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
-                            EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;    \
-                            EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;    \
-                          } while(0)
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT()                  (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
-#endif /* USB_OTG_FS */
-
-#if defined (USB)
-#define __HAL_PCD_ENABLE(__HANDLE__)                                  USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_DISABLE(__HANDLE__)                                 USB_DisableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)                 ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)               (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
-
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT()                             EXTI->IMR |= USB_WAKEUP_EXTI_LINE
-#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT()                            EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
-#define __HAL_USB_WAKEUP_EXTI_GET_FLAG()                              EXTI->PR & (USB_WAKEUP_EXTI_LINE)
-#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG()                            EXTI->PR = USB_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE()                 \
-                        do{                                        \
-                            EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
-                            EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;    \
-                          } while(0)
-
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE()                \
-                        do{                                        \
-                            EXTI->FTSR |= (USB_WAKEUP_EXTI_LINE);  \
-                            EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE); \
-                          } while(0)
-
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()         \
-                        do{                                        \
-                            EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE); \
-                            EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
-                            EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;    \
-                            EXTI->FTSR |= USB_WAKEUP_EXTI_LINE;    \
-                          } while(0)
-#endif /* USB */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCD_Exported_Functions PCD Exported Functions
-  * @{
-  */
-
-/* Initialization/de-initialization functions  ********************************/
-/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
-/**
-  * @}
-  */
-
-/* I/O operation functions  ***************************************************/
-/* Non-Blocking mode: Interrupt */
-/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
-/**
-  * @}
-  */
-
-/* Peripheral Control functions  **********************************************/
-/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-/**
-  * @}
-  */
-
-/* Peripheral State functions  ************************************************/
-/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
-  * @{
-  */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PCD_Private_Constants PCD Private Constants
-  * @{
-  */
-/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
-  * @{
-  */
-#if defined (USB_OTG_FS)
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                            ((uint32_t)0x08)
-#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE                           ((uint32_t)0x0C)
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE                    ((uint32_t)0x10)
-
-#define USB_OTG_FS_WAKEUP_EXTI_LINE                                   ((uint32_t)0x00040000)  /*!< External interrupt line 18 Connected to the USB EXTI Line */
-#endif /* USB_OTG_FS */
-
-#if defined (USB)
-#define  USB_WAKEUP_EXTI_LINE                                         ((uint32_t)0x00040000)  /*!< External interrupt line 18 Connected to the USB EXTI Line */
-#endif /* USB */
-/**
-  * @}
-  */
-
-#if defined (USB)
-/** @defgroup PCD_EP0_MPS PCD EP0 MPS
-  * @{
-  */
-#define PCD_EP0MPS_64                                                 DEP0CTL_MPS_64
-#define PCD_EP0MPS_32                                                 DEP0CTL_MPS_32
-#define PCD_EP0MPS_16                                                 DEP0CTL_MPS_16
-#define PCD_EP0MPS_08                                                 DEP0CTL_MPS_8 
-/**
-  * @}
-  */
-  
-/** @defgroup PCD_ENDP PCD ENDP
-  * @{
-  */
-#define PCD_ENDP0                                                     ((uint8_t)0)
-#define PCD_ENDP1                                                     ((uint8_t)1)
-#define PCD_ENDP2                                                     ((uint8_t)2)
-#define PCD_ENDP3                                                     ((uint8_t)3)
-#define PCD_ENDP4                                                     ((uint8_t)4)
-#define PCD_ENDP5                                                     ((uint8_t)5)
-#define PCD_ENDP6                                                     ((uint8_t)6)
-#define PCD_ENDP7                                                     ((uint8_t)7)
-/**
-  * @}
-  */
-
-/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
-  * @{
-  */
-#define PCD_SNG_BUF                                                   0
-#define PCD_DBL_BUF                                                   1
-/**
-  * @}
-  */
-#endif /* USB */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup PCD_Private_Macros PCD Private Macros
- * @{
- */
-#if defined (USB)
-/* SetENDPOINT */
-#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue)  (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue))
-
-/* GetENDPOINT */
-#define PCD_GET_ENDPOINT(USBx, bEpNum)            (*(&(USBx)->EP0R + (bEpNum) * 2))
-
-/* ENDPOINT transfer */
-#define USB_EP0StartXfer                          USB_EPStartXfer
-
-/**
-  * @brief  sets the type in the endpoint register(bits EP_TYPE[1:0])
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wType: Endpoint Type.
-  * @retval None
-  */
-#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
-                                  ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))
-
-/**
-  * @brief  gets the type in the endpoint register(bits EP_TYPE[1:0])
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval Endpoint Type
-  */
-#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
-
-/**
-  * @brief free buffer used from the application realizing it to the line
-          toggles bit SW_BUF in the double buffered endpoint register
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  bDir: Direction
-  * @retval None
-  */
-#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
-{\
-  if ((bDir) == PCD_EP_DBUF_OUT)\
-  { /* OUT double buffered endpoint */\
-    PCD_TX_DTOG((USBx), (bEpNum));\
-  }\
-  else if ((bDir) == PCD_EP_DBUF_IN)\
-  { /* IN double buffered endpoint */\
-    PCD_RX_DTOG((USBx), (bEpNum));\
-  }\
-}
-
-/**
-  * @brief gets direction of the double buffered endpoint
-  * @param   USBx: USB peripheral instance register address.
-  * @param   bEpNum: Endpoint Number.
-  * @retval EP_DBUF_OUT, EP_DBUF_IN,
-  *         EP_DBUF_ERR if the endpoint counter not yet programmed.
-  */
-#define PCD_GET_DB_DIR(USBx, bEpNum)\
-{\
-  if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\
-    return(PCD_EP_DBUF_OUT);\
-  else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\
-    return(PCD_EP_DBUF_IN);\
-  else\
-    return(PCD_EP_DBUF_ERR);\
-}
-
-/**
-  * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wState: new state
-  * @retval None
-  */
-#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
-   \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\
-   /* toggle first bit ? */     \
-   if((USB_EPTX_DTOG1 & (wState))!= 0)\
-   {                                                                            \
-     _wRegVal ^= USB_EPTX_DTOG1;        \
-   }                                                                            \
-   /* toggle second bit ?  */         \
-   if((USB_EPTX_DTOG2 & (wState))!= 0)      \
-   {                                                                            \
-     _wRegVal ^= USB_EPTX_DTOG2;        \
-   }                                                                            \
-   PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX));\
-  } /* PCD_SET_EP_TX_STATUS */
-
-/**
-  * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wState: new state
-  * @retval None
-  */
-#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
-    register uint16_t _wRegVal;   \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\
-    /* toggle first bit ? */  \
-    if((USB_EPRX_DTOG1 & (wState))!= 0) \
-    {                                                                             \
-      _wRegVal ^= USB_EPRX_DTOG1;  \
-    }                                                                             \
-    /* toggle second bit ? */  \
-    if((USB_EPRX_DTOG2 & (wState))!= 0) \
-    {                                                                             \
-      _wRegVal ^= USB_EPRX_DTOG2;  \
-    }                                                                             \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
-  } /* PCD_SET_EP_RX_STATUS */
-
-/**
-  * @brief  sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wStaterx: new state.
-  * @param  wStatetx: new state.
-  * @retval None
-  */
-#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
-    register uint32_t _wRegVal;   \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
-    /* toggle first bit ? */  \
-    if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \
-    {                                                                                    \
-      _wRegVal ^= USB_EPRX_DTOG1;  \
-    }                                                                                    \
-    /* toggle second bit ? */  \
-    if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \
-    {                                                                                    \
-      _wRegVal ^= USB_EPRX_DTOG2;  \
-    }                                                                                    \
-    /* toggle first bit ? */     \
-    if((USB_EPTX_DTOG1 & (wStatetx))!= 0)      \
-    {                                                                                    \
-      _wRegVal ^= USB_EPTX_DTOG1;        \
-    }                                                                                    \
-    /* toggle second bit ?  */         \
-    if((USB_EPTX_DTOG2 & (wStatetx))!= 0)      \
-    {                                                                                    \
-      _wRegVal ^= USB_EPTX_DTOG2;        \
-    }                                                                                    \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX);    \
-  } /* PCD_SET_EP_TXRX_STATUS */
-
-/**
-  * @brief  gets the status for tx/rx transfer (bits STAT_TX[1:0]
-  *         /STAT_RX[1:0])
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval status
-  */
-#define PCD_GET_EP_TX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
-#define PCD_GET_EP_RX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
-
-/**
-  * @brief  sets directly the VALID tx/rx-status into the endpoint register
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval None
-  */
-#define PCD_SET_EP_TX_VALID(USBx, bEpNum)      (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
-#define PCD_SET_EP_RX_VALID(USBx, bEpNum)      (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
-
-/**
-  * @brief  checks stall condition in an endpoint.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval TRUE = endpoint in stall condition.
-  */
-#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
-                                   == USB_EP_TX_STALL)
-#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
-                                   == USB_EP_RX_STALL)
-
-/**
-  * @brief  set & clear EP_KIND bit.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval None
-  */
-#define PCD_SET_EP_KIND(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
-                                (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK))))
-#define PCD_CLEAR_EP_KIND(USBx, bEpNum)  (PCD_SET_ENDPOINT((USBx), (bEpNum), \
-                                (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK))))
-
-/**
-  * @brief  Sets/clears directly STATUS_OUT bit in the endpoint register.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval None
-  */
-#define PCD_SET_OUT_STATUS(USBx, bEpNum)       PCD_SET_EP_KIND((USBx), (bEpNum))
-#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum)     PCD_CLEAR_EP_KIND((USBx), (bEpNum))
-
-/**
-  * @brief  Sets/clears directly EP_KIND bit in the endpoint register.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval None
-  */
-#define PCD_SET_EP_DBUF(USBx, bEpNum)          PCD_SET_EP_KIND((USBx), (bEpNum))
-#define PCD_CLEAR_EP_DBUF(USBx, bEpNum)        PCD_CLEAR_EP_KIND((USBx), (bEpNum))
-
-/**
-  * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval None
-  */
-#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum)   (PCD_SET_ENDPOINT((USBx), (bEpNum),\
-                                   PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK))
-#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum)   (PCD_SET_ENDPOINT((USBx), (bEpNum),\
-                                   PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK))
-
-/**
-  * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval None
-  */
-#define PCD_RX_DTOG(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
-                                   USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
-#define PCD_TX_DTOG(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
-                                   USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
-
-/**
-  * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval None
-  */
-#define PCD_CLEAR_RX_DTOG(USBx, bEpNum)  if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\
-                                         {                                                              \
-                                           PCD_RX_DTOG((USBx), (bEpNum));                               \
-                                         }
-#define PCD_CLEAR_TX_DTOG(USBx, bEpNum)  if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\
-                                         {                                                              \
-                                            PCD_TX_DTOG((USBx), (bEpNum));                              \
-                                         }
-      
-/**
-  * @brief  Sets address in an endpoint register.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  bAddr: Address.
-  * @retval None
-  */
-#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
-    USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr))
-
-#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
-
-#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8)*2+     ((uint32_t)(USBx) + 0x400)))
-#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+2)*2+  ((uint32_t)(USBx) + 0x400)))
-#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+4)*2+  ((uint32_t)(USBx) + 0x400)))
-#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+6)*2+  ((uint32_t)(USBx) + 0x400)))
-      
-#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
-    uint32_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \
-    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
-  }
-
-/**
-  * @brief  sets address of the tx/rx buffer.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wAddr: address to be set (must be word aligned).
-  * @retval None
-  */
-#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
-#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
-
-/**
-  * @brief  Gets address of the tx/rx buffer.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval address of the buffer.
-  */
-#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
-#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
-
-/**
-  * @brief  Sets counter of rx buffer with no. of blocks.
-  * @param  dwReg: Register
-  * @param  wCount: Counter.
-  * @param  wNBlocks: no. of Blocks.
-  * @retval None
-  */
-#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
-    (wNBlocks) = (wCount) >> 5;\
-    if(((wCount) & 0x1f) == 0)\
-    {                                                  \
-      (wNBlocks)--;\
-    }                                                  \
-    *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10) | 0x8000); \
-  }/* PCD_CALC_BLK32 */
-
-#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
-    (wNBlocks) = (wCount) >> 1;\
-    if(((wCount) & 0x1) != 0)\
-    {                                                  \
-      (wNBlocks)++;\
-    }                                                  \
-    *pdwReg = (uint16_t)((wNBlocks) << 10);\
-  }/* PCD_CALC_BLK2 */
-
-#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount)  {\
-    uint16_t wNBlocks;\
-    if((wCount) > 62)                                \
-    {                                                \
-      PCD_CALC_BLK32((dwReg),(wCount),wNBlocks);     \
-    }                                                \
-    else                                             \
-    {                                                \
-      PCD_CALC_BLK2((dwReg),(wCount),wNBlocks);      \
-    }                                                \
-  }/* PCD_SET_EP_CNT_RX_REG */
-
-#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
-    uint32_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
-    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
-  }
-
-/**
-  * @brief  sets counter for the tx/rx buffer.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wCount: Counter value.
-  * @retval None
-  */
-#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
-
-
-/**
-  * @brief  gets counter of the tx buffer.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval Counter value
-  */
-#define PCD_GET_EP_TX_CNT(USBx, bEpNum)        ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff)
-#define PCD_GET_EP_RX_CNT(USBx, bEpNum)        ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff)
-
-/**
-  * @brief  Sets buffer 0/1 address in a double buffer endpoint.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wBuf0Addr: buffer 0 address.
-  * @retval Counter value
-  */
-#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}
-#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}
-
-/**
-  * @brief  Sets addresses in a double buffer endpoint.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wBuf0Addr: buffer 0 address.
-  * @param  wBuf1Addr = buffer 1 address.
-  * @retval None
-  */
-#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
-    PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\
-    PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\
-  } /* PCD_SET_EP_DBUF_ADDR */
-
-/**
-  * @brief  Gets buffer 0/1 address of a double buffer endpoint.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval None
-  */
-#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum)    (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
-#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum)    (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
-
-/**
-  * @brief  Gets buffer 0/1 address of a double buffer endpoint.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  bDir: endpoint dir  EP_DBUF_OUT = OUT 
-  *         EP_DBUF_IN  = IN 
-  * @param  wCount: Counter value 
-  * @retval None
-  */
-#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount)  { \
-    if((bDir) == PCD_EP_DBUF_OUT)\
-      /* OUT endpoint */ \
-    {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \
-    else if((bDir) == PCD_EP_DBUF_IN)\
-      /* IN endpoint */ \
-      *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount);  \
-  } /* SetEPDblBuf0Count*/
-
-#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount)  { \
-    if((bDir) == PCD_EP_DBUF_OUT)\
-    {/* OUT endpoint */                                       \
-      PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount));           \
-    }                                                         \
-    else if((bDir) == PCD_EP_DBUF_IN)\
-    {/* IN endpoint */                                        \
-      *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
-    }                                                         \
-  } /* SetEPDblBuf1Count */
-
-#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
-    PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
-    PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
-  } /* PCD_SET_EP_DBUF_CNT  */
-
-/**
-  * @brief  Gets buffer 0/1 rx/tx counter for double buffering.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval None
-  */
-#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum)     (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
-#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum)     (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
-
-#endif /* USB */
-
-/** @defgroup PCD_Instance_definition PCD Instance definition
-  * @{
-  */
-#define IS_PCD_ALL_INSTANCE                                        IS_USB_ALL_INSTANCE
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32F102x6 || STM32F102xB || */
-       /* STM32F103x6 || STM32F103xB || */
-       /* STM32F103xE || STM32F103xG || */
-       /* STM32F105xC || STM32F107xC    */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F1xx_HAL_PCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_pcd_ex.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,116 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_pcd_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of Extended PCD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_PCD_EX_H
-#define __STM32F1xx_HAL_PCD_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || \
-    defined(STM32F103x6) || defined(STM32F103xB) || \
-    defined(STM32F103xE) || defined(STM32F103xG) || \
-    defined(STM32F105xC) || defined(STM32F107xC)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PCDEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
-  * @{
-  */
-/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
-  * @{
-  */
-#if defined (USB_OTG_FS)
-HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
-HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
-#endif /* USB_OTG_FS */
-
-#if defined (USB)
-HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, 
-                                     uint16_t ep_addr,
-                                     uint16_t ep_kind,
-                                     uint32_t pmaadress);
-#endif /* USB */
-/**
-  * @}
-  */
-
-/** @addtogroup PCDEx_Exported_Functions_Group2 Peripheral State functions
-  * @{
-  */
-void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-#endif /* STM32F102x6 || STM32F102xB || */
-       /* STM32F103x6 || STM32F103xB || */
-       /* STM32F103xE || STM32F103xG || */
-       /* STM32F105xC || STM32F107xC    */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F1xx_HAL_PCD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_pwr.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,406 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_pwr.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of PWR HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_PWR_H
-#define __STM32F1xx_HAL_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PWR
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Types PWR Exported Types
-  * @{
-  */ 
-
-/**
-  * @brief  PWR PVD configuration structure definition
-  */
-typedef struct
-{
-  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
-                            This parameter can be a value of @ref PWR_PVD_detection_level */
-
-  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
-                           This parameter can be a value of @ref PWR_PVD_Mode */
-}PWR_PVDTypeDef;
-
-
-/**
-  * @}
-  */
-
-
-/* Internal constants --------------------------------------------------------*/
-
-/** @addtogroup PWR_Private_Constants
-  * @{
-  */ 
-
-#define PWR_EXTI_LINE_PVD  ((uint32_t)0x00010000)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
-
-/**
-  * @}
-  */
-
- 
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Constants PWR Exported Constants
-  * @{
-  */ 
-
-/** @defgroup PWR_PVD_detection_level PWR PVD detection level
-  * @{
-  */
-#define PWR_PVDLEVEL_0                  PWR_CR_PLS_2V2
-#define PWR_PVDLEVEL_1                  PWR_CR_PLS_2V3
-#define PWR_PVDLEVEL_2                  PWR_CR_PLS_2V4
-#define PWR_PVDLEVEL_3                  PWR_CR_PLS_2V5
-#define PWR_PVDLEVEL_4                  PWR_CR_PLS_2V6
-#define PWR_PVDLEVEL_5                  PWR_CR_PLS_2V7
-#define PWR_PVDLEVEL_6                  PWR_CR_PLS_2V8
-#define PWR_PVDLEVEL_7                  PWR_CR_PLS_2V9 
-                                                          
-/**
-  * @}
-  */
-
-/** @defgroup PWR_PVD_Mode PWR PVD Mode
-  * @{
-  */
-#define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< basic mode is used */
-#define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
-  * @{
-  */
-
-#define PWR_WAKEUP_PIN1                 PWR_CSR_EWUP
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
-  * @{
-  */
-#define PWR_MAINREGULATOR_ON                        ((uint32_t)0x00000000)
-#define PWR_LOWPOWERREGULATOR_ON                    PWR_CR_LPDS
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
-  * @{
-  */
-#define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01)
-#define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02)
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
-  * @{
-  */
-#define PWR_STOPENTRY_WFI               ((uint8_t)0x01)
-#define PWR_STOPENTRY_WFE               ((uint8_t)0x02)
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Flag PWR Flag
-  * @{
-  */
-#define PWR_FLAG_WU                     PWR_CSR_WUF
-#define PWR_FLAG_SB                     PWR_CSR_SBF
-#define PWR_FLAG_PVDO                   PWR_CSR_PVDO
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_Exported_Macros PWR Exported Macros
-  * @{
-  */
-
-/** @brief  Check PWR flag is set or not.
-  * @param  __FLAG__: specifies the flag to check.
-  *           This parameter can be one of the following values:
-  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
-  *                  was received from the WKUP pin or from the RTC alarm
-  *                  An additional wakeup event is detected if the WKUP pin is enabled
-  *                  (by setting the EWUP bit) when the WKUP pin level is already high.
-  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
-  *                  resumed from StandBy mode.
-  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
-  *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
-  *                  For this reason, this bit is equal to 0 after Standby or reset
-  *                  until the PVDE bit is set.
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the PWR's pending flags.
-  * @param  __FLAG__: specifies the flag to clear.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_FLAG_WU: Wake Up flag
-  *            @arg PWR_FLAG_SB: StandBy flag
-  */
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
-
-/**
-  * @brief Enable interrupt on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Disable interrupt on PVD Exti Line 16. 
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Enable event on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Disable event on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
-
-
-/**
-  * @brief  PVD EXTI line configuration: set falling edge trigger.  
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
-
-
-/**
-  * @brief Disable the PVD Extended Interrupt Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
-
-
-/**
-  * @brief  PVD EXTI line configuration: set rising edge trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Disable the PVD Extended Interrupt Rising Trigger.
-  * This parameter can be:
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
-
-/**
-  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
-  * This parameter can be:
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
-
-
-
-/**
-  * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
-  * @retval EXTI PVD Line Status.
-  */
-#define __HAL_PWR_PVD_EXTI_GET_FLAG()       (EXTI->PR & (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Clear the PVD EXTI flag.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()     (EXTI->PR = (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Generate a Software interrupt on selected EXTI line.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup PWR_Private_Macros PWR Private Macros
-  * @{
-  */
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
-
-
-#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
-                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
-                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
-                              ((MODE) == PWR_PVD_MODE_NORMAL)) 
-
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
-
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
-                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
-
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
-
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
-
-/**
-  * @}
-  */
-
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup PWR_Exported_Functions PWR Exported Functions
-  * @{
-  */
-  
-/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @{
-  */
-
-/* Initialization and de-initialization functions *******************************/
-void HAL_PWR_DeInit(void);
-void HAL_PWR_EnableBkUpAccess(void);
-void HAL_PWR_DisableBkUpAccess(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
-/* #define HAL_PWR_ConfigPVD 12*/
-void HAL_PWR_EnablePVD(void);
-void HAL_PWR_DisablePVD(void);
-
-/* WakeUp pins configuration functions ****************************************/
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
-
-/* Low Power modes configuration functions ************************************/
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
-void HAL_PWR_EnterSTANDBYMode(void);
-
-void HAL_PWR_EnableSleepOnExit(void);
-void HAL_PWR_DisableSleepOnExit(void);
-void HAL_PWR_EnableSEVOnPend(void);
-void HAL_PWR_DisableSEVOnPend(void);
-
-
-
-void HAL_PWR_PVD_IRQHandler(void);
-void HAL_PWR_PVDCallback(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F1xx_HAL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_rcc.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1395 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_rcc.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of RCC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_RCC_H
-#define __STM32F1xx_HAL_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RCC
-  * @{
-  */
-
-/** @addtogroup RCC_Private_Constants
-  * @{
-  */
-
-/** @defgroup RCC_Timeout RCC Timeout
-  * @{
-  */ 
-  
-/* Disable Backup domain write protection state change timeout */
-#define RCC_DBP_TIMEOUT_VALUE  ((uint32_t)100)       /* 100 ms */
-/* LSE state change timeout */
-#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
-#define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000)  /* 5 s    */
-#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE         ((uint32_t)2)      /* 2 ms (minimum Tick + 1) */
-#define LSI_TIMEOUT_VALUE         ((uint32_t)2)      /* 2 ms (minimum Tick + 1) */
-#define PLL_TIMEOUT_VALUE         ((uint32_t)2)      /* 2 ms (minimum Tick + 1) */
-#define LSI_VALUE                 ((uint32_t)40000)  /* 40kHz */
-/**
-  * @}
-  */
-  
-/** @defgroup RCC_Register_Offset Register offsets
-  * @{
-  */
-#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
-#define RCC_CR_OFFSET             0x00
-#define RCC_CFGR_OFFSET           0x04
-#define RCC_CIR_OFFSET            0x08
-#define RCC_BDCR_OFFSET           0x20
-#define RCC_CSR_OFFSET            0x24
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
-  * @brief RCC registers bit address in the alias region
-  * @{
-  */
-#define RCC_CR_OFFSET_BB          (RCC_OFFSET + RCC_CR_OFFSET)
-#define RCC_CFGR_OFFSET_BB        (RCC_OFFSET + RCC_CFGR_OFFSET)
-#define RCC_CIR_OFFSET_BB         (RCC_OFFSET + RCC_CIR_OFFSET)
-#define RCC_BDCR_OFFSET_BB        (RCC_OFFSET + RCC_BDCR_OFFSET)
-#define RCC_CSR_OFFSET_BB         (RCC_OFFSET + RCC_CSR_OFFSET)
-
-/* --- CR Register ---*/
-/* Alias word address of HSION bit */
-#define RCC_HSION_BIT_NUMBER      POSITION_VAL(RCC_CR_HSION)
-#define RCC_CR_HSION_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSION_BIT_NUMBER * 4)))
-/* Alias word address of HSEON bit */
-#define RCC_HSEON_BIT_NUMBER      POSITION_VAL(RCC_CR_HSEON)
-#define RCC_CR_HSEON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSEON_BIT_NUMBER * 4)))
-/* Alias word address of CSSON bit */
-#define RCC_CSSON_BIT_NUMBER      POSITION_VAL(RCC_CR_CSSON)
-#define RCC_CR_CSSON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_CSSON_BIT_NUMBER * 4)))
-/* Alias word address of PLLON bit */
-#define RCC_PLLON_BIT_NUMBER      POSITION_VAL(RCC_CR_PLLON)
-#define RCC_CR_PLLON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_PLLON_BIT_NUMBER * 4)))
-
-/* --- CSR Register ---*/
-/* Alias word address of LSION bit */
-#define RCC_LSION_BIT_NUMBER      POSITION_VAL(RCC_CSR_LSION)
-#define RCC_CSR_LSION_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSION_BIT_NUMBER * 4)))
-
-/* Alias word address of RMVF bit */
-#define RCC_RMVF_BIT_NUMBER       POSITION_VAL(RCC_CSR_RMVF)
-#define RCC_CSR_RMVF_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RMVF_BIT_NUMBER * 4)))
-
-/* --- BDCR Registers ---*/
-/* Alias word address of LSEON bit */
-#define RCC_LSEON_BIT_NUMBER      POSITION_VAL(RCC_BDCR_LSEON)
-#define RCC_BDCR_LSEON_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEON_BIT_NUMBER * 4)))
-
-/* Alias word address of LSEON bit */
-#define RCC_LSEBYP_BIT_NUMBER     POSITION_VAL(RCC_BDCR_LSEBYP)
-#define RCC_BDCR_LSEBYP_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEBYP_BIT_NUMBER * 4)))
-
-/* Alias word address of RTCEN bit */
-#define RCC_RTCEN_BIT_NUMBER      POSITION_VAL(RCC_BDCR_RTCEN)
-#define RCC_BDCR_RTCEN_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_RTCEN_BIT_NUMBER * 4)))
-
-/* Alias word address of BDRST bit */
-#define RCC_BDRST_BIT_NUMBER          POSITION_VAL(RCC_BDCR_BDRST)
-#define RCC_BDCR_BDRST_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_BDRST_BIT_NUMBER * 4)))
-
-/**
-  * @}
-  */
-  
-/* CR register byte 2 (Bits[23:16]) base address */
-#define RCC_CR_BYTE2_ADDRESS          ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
-
-/* CIR register byte 1 (Bits[15:8]) base address */
-#define RCC_CIR_BYTE1_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
-
-/* CIR register byte 2 (Bits[23:16]) base address */
-#define RCC_CIR_BYTE2_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
-
-/* Defines used for Flags */
-#define CR_REG_INDEX                     ((uint8_t)1)
-#define BDCR_REG_INDEX                   ((uint8_t)2)
-#define CSR_REG_INDEX                    ((uint8_t)3)
-
-#define RCC_FLAG_MASK                    ((uint8_t)0x1F)
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCC_Private_Macros
-  * @{
-  */
-/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
-  * @{
-  */
-#define __HAL_RCC_SYSCFG_CLK_DISABLE    __HAL_RCC_AFIO_CLK_DISABLE
-#define __HAL_RCC_SYSCFG_CLK_ENABLE     __HAL_RCC_AFIO_CLK_ENABLE
-#define __HAL_RCC_SYSCFG_FORCE_RESET    __HAL_RCC_AFIO_FORCE_RESET
-#define __HAL_RCC_SYSCFG_RELEASE_RESET  __HAL_RCC_AFIO_RELEASE_RESET
-/**
-  * @}
-  */
-
-#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \
-                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE))
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
-#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
-                             ((__HSE__) == RCC_HSE_BYPASS))
-#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
-                             ((__LSE__) == RCC_LSE_BYPASS))
-#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
-#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
-#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
-#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
-                             ((__PLL__) == RCC_PLL_ON))
-
-#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
-                               (((CLK) & RCC_CLOCKTYPE_HCLK)   == RCC_CLOCKTYPE_HCLK)   || \
-                               (((CLK) & RCC_CLOCKTYPE_PCLK1)  == RCC_CLOCKTYPE_PCLK1)  || \
-                               (((CLK) & RCC_CLOCKTYPE_PCLK2)  == RCC_CLOCKTYPE_PCLK2))
-#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
-#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
-                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
-                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
-#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV512))
-#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
-                               ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
-                               ((__PCLK__) == RCC_HCLK_DIV16))
-#define IS_RCC_MCO(__MCO__)  ((__MCO__) == RCC_MCO)
-#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) 
-#define IS_RCC_RTCCLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
-                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)  || \
-                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)  || \
-                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
-
-/**
-  * @}
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Types RCC Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  RCC PLL configuration structure definition  
-  */
-typedef struct
-{
-  uint32_t PLLState;      /*!< PLLState: The new state of the PLL.
-                              This parameter can be a value of @ref RCC_PLL_Config */
-
-  uint32_t PLLSource;     /*!< PLLSource: PLL entry clock source.
-                              This parameter must be a value of @ref RCC_PLL_Clock_Source */          
-
-  uint32_t PLLMUL;        /*!< PLLMUL: Multiplication factor for PLL VCO input clock
-                              This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
-} RCC_PLLInitTypeDef;
-   
-/**
-  * @brief  RCC System, AHB and APB busses clock configuration structure definition  
-  */
-typedef struct
-{
-  uint32_t ClockType;             /*!< The clock to be configured.
-                                       This parameter can be a value of @ref RCC_System_Clock_Type */
-
-  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
-                                       This parameter can be a value of @ref RCC_System_Clock_Source */
-
-  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
-                                       This parameter can be a value of @ref RCC_AHB_Clock_Source */
-
-  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-
-  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-} RCC_ClkInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_Exported_Constants RCC Exported Constants
-  * @{
-  */
-
-/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
-  * @{
-  */
-
-#define RCC_PLLSOURCE_HSI_DIV2      ((uint32_t)0x00000000)     /*!< HSI clock divided by 2 selected as PLL entry clock source */
-#define RCC_PLLSOURCE_HSE           RCC_CFGR_PLLSRC            /*!< HSE clock selected as PLL entry clock source */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Oscillator_Type Oscillator Type
-  * @{
-  */
-#define RCC_OSCILLATORTYPE_NONE            ((uint32_t)0x00000000)
-#define RCC_OSCILLATORTYPE_HSE             ((uint32_t)0x00000001)
-#define RCC_OSCILLATORTYPE_HSI             ((uint32_t)0x00000002)
-#define RCC_OSCILLATORTYPE_LSE             ((uint32_t)0x00000004)
-#define RCC_OSCILLATORTYPE_LSI             ((uint32_t)0x00000008)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSE_Config HSE Config
-  * @{
-  */
-#define RCC_HSE_OFF                      ((uint32_t)0x00000000)                     /*!< HSE clock deactivation */
-#define RCC_HSE_ON                       RCC_CR_HSEON                               /*!< HSE clock activation */
-#define RCC_HSE_BYPASS                   ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSE_Config LSE Config
-  * @{
-  */
-#define RCC_LSE_OFF                      ((uint32_t)0x00000000)                       /*!< LSE clock deactivation */
-#define RCC_LSE_ON                       RCC_BDCR_LSEON                                /*!< LSE clock activation */
-#define RCC_LSE_BYPASS                   ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSI_Config HSI Config
-  * @{
-  */
-#define RCC_HSI_OFF                      ((uint32_t)0x00000000)           /*!< HSI clock deactivation */
-#define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */
-
-#define RCC_HSICALIBRATION_DEFAULT       ((uint32_t)0x10)         /* Default HSI calibration trimming value */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSI_Config LSI Config
-  * @{
-  */
-#define RCC_LSI_OFF                      ((uint32_t)0x00000000)   /*!< LSI clock deactivation */
-#define RCC_LSI_ON                       RCC_CSR_LSION            /*!< LSI clock activation */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Config PLL Config
-  * @{
-  */
-#define RCC_PLL_NONE                      ((uint32_t)0x00000000)  /*!< PLL is not configured */
-#define RCC_PLL_OFF                       ((uint32_t)0x00000001)  /*!< PLL deactivation */
-#define RCC_PLL_ON                        ((uint32_t)0x00000002)  /*!< PLL activation */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Type System Clock Type
-  * @{
-  */
-#define RCC_CLOCKTYPE_SYSCLK             ((uint32_t)0x00000001) /*!< SYSCLK to configure */
-#define RCC_CLOCKTYPE_HCLK               ((uint32_t)0x00000002) /*!< HCLK to configure */
-#define RCC_CLOCKTYPE_PCLK1              ((uint32_t)0x00000004) /*!< PCLK1 to configure */
-#define RCC_CLOCKTYPE_PCLK2              ((uint32_t)0x00000008) /*!< PCLK2 to configure */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Source System Clock Source
-  * @{
-  */
-#define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
-#define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
-#define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
-  * @{
-  */
-#define RCC_SYSCLKSOURCE_STATUS_HSI      RCC_CFGR_SWS_HSI            /*!< HSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSE      RCC_CFGR_SWS_HSE            /*!< HSE used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK   RCC_CFGR_SWS_PLL            /*!< PLL used as system clock */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
-  * @{
-  */
-#define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
-#define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
-#define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
-#define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
-#define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
-#define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
-#define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
-#define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
-#define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
-
-/**
-  * @}
-  */
-  
-/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
-  * @{
-  */
-#define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
-#define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
-#define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
-#define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
-#define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
-  * @{
-  */
-#define RCC_RTCCLKSOURCE_NO_CLK          ((uint32_t)0x00000000)                 /*!< No clock */
-#define RCC_RTCCLKSOURCE_LSE             RCC_BDCR_RTCSEL_LSE                  /*!< LSE oscillator clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_LSI             RCC_BDCR_RTCSEL_LSI                  /*!< LSI oscillator clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_HSE_DIV128      RCC_BDCR_RTCSEL_HSE                    /*!< HSE oscillator clock divided by 128 used as RTC clock */
-/**
-  * @}
-  */
-
-
-/** @defgroup RCC_MCO_Index MCO Index
-  * @{
-  */
-#define RCC_MCO1                         ((uint32_t)0x00000000)
-#define RCC_MCO                          RCC_MCO1               /*!< MCO1 to be compliant with other families with 2 MCOs*/
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
-  * @{
-  */
-#define RCC_MCODIV_1                    ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Interrupt Interrupts
-  * @{
-  */
-#define RCC_IT_LSIRDY                    ((uint8_t)RCC_CIR_LSIRDYF)   /*!< LSI Ready Interrupt flag */
-#define RCC_IT_LSERDY                    ((uint8_t)RCC_CIR_LSERDYF)   /*!< LSE Ready Interrupt flag */
-#define RCC_IT_HSIRDY                    ((uint8_t)RCC_CIR_HSIRDYF)   /*!< HSI Ready Interrupt flag */
-#define RCC_IT_HSERDY                    ((uint8_t)RCC_CIR_HSERDYF)   /*!< HSE Ready Interrupt flag */
-#define RCC_IT_PLLRDY                    ((uint8_t)RCC_CIR_PLLRDYF)   /*!< PLL Ready Interrupt flag */
-#define RCC_IT_CSS                       ((uint8_t)RCC_CIR_CSSF)      /*!< Clock Security System Interrupt flag */
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCC_Flag Flags
-  *        Elements values convention: XXXYYYYYb
-  *           - YYYYY  : Flag position in the register
-  *           - XXX  : Register index
-  *                 - 001: CR register
-  *                 - 010: BDCR register
-  *                 - 011: CSR register
-  * @{
-  */
-/* Flags in the CR register */
-#define RCC_FLAG_HSIRDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
-#define RCC_FLAG_HSERDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
-#define RCC_FLAG_PLLRDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
-
-/* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY)))   /*!< Internal Low Speed oscillator Ready */
-#define RCC_FLAG_PINRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF)))  /*!< PIN reset flag */
-#define RCC_FLAG_PORRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF)))  /*!< POR/PDR reset flag */
-#define RCC_FLAG_SFTRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF)))  /*!< Software Reset flag */
-#define RCC_FLAG_IWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
-#define RCC_FLAG_WWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
-#define RCC_FLAG_LPWRRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
-
-/* Flags in the BDCR register */
-#define RCC_FLAG_LSERDY                  ((uint8_t)((BDCR_REG_INDEX << 5) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Macros RCC Exported Macros
-  * @{
-  */
-
-/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.   
-  * @{
-  */
-#define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_SRAM_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_FLITF_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_CRC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_DMA1_CLK_DISABLE()      (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
-#define __HAL_RCC_SRAM_CLK_DISABLE()      (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
-#define __HAL_RCC_FLITF_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
-#define __HAL_RCC_CRC_CLK_DISABLE()       (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#define __HAL_RCC_DMA1_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
-#define __HAL_RCC_DMA1_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
-#define __HAL_RCC_SRAM_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
-#define __HAL_RCC_SRAM_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
-#define __HAL_RCC_FLITF_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
-#define __HAL_RCC_FLITF_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
-  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it. 
-  * @{   
-  */
-#define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_WWDG_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_USART2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_BKP_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_PWR_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM2_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_WWDG_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
-#define __HAL_RCC_USART2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_I2C1_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
-
-#define __HAL_RCC_BKP_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
-#define __HAL_RCC_PWR_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
-#define __HAL_RCC_USART2_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
-#define __HAL_RCC_USART2_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
-#define __HAL_RCC_I2C1_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
-#define __HAL_RCC_BKP_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
-#define __HAL_RCC_BKP_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
-#define __HAL_RCC_PWR_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
-#define __HAL_RCC_PWR_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{   
-  */
-#define __HAL_RCC_AFIO_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_USART1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_AFIO_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
-#define __HAL_RCC_GPIOA_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
-#define __HAL_RCC_GPIOB_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
-#define __HAL_RCC_GPIOC_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
-#define __HAL_RCC_GPIOD_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
-#define __HAL_RCC_ADC1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
-
-#define __HAL_RCC_TIM1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
-#define __HAL_RCC_SPI1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
-#define __HAL_RCC_USART1_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
-
-/**
-  * @}
-  */
-  
-/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#define __HAL_RCC_AFIO_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
-#define __HAL_RCC_AFIO_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
-#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
-#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
-#define __HAL_RCC_ADC1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
-#define __HAL_RCC_ADC1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
-#define __HAL_RCC_TIM1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
-#define __HAL_RCC_TIM1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
-#define __HAL_RCC_SPI1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
-#define __HAL_RCC_USART1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
-#define __HAL_RCC_USART1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
-  * @brief  Force or release APB1 peripheral reset.
-  * @{   
-  */
-#define __HAL_RCC_APB1_FORCE_RESET()       (RCC->APB2RSTR = 0xFFFFFFFFU)  
-#define __HAL_RCC_TIM2_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_WWDG_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_USART2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_I2C1_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-
-#define __HAL_RCC_BKP_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))
-#define __HAL_RCC_PWR_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
-
-#define __HAL_RCC_APB1_RELEASE_RESET()      (RCC->APB1RSTR = 0x00)  
-#define __HAL_RCC_TIM2_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_WWDG_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_USART2_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_I2C1_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
-
-#define __HAL_RCC_BKP_RELEASE_RESET()        (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
-#define __HAL_RCC_PWR_RELEASE_RESET()        (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
-  * @brief  Force or release APB2 peripheral reset.
-  * @{   
-  */
-#define __HAL_RCC_APB2_FORCE_RESET()       (RCC->APB2RSTR = 0xFFFFFFFFU)  
-#define __HAL_RCC_AFIO_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
-#define __HAL_RCC_GPIOA_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
-#define __HAL_RCC_GPIOB_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
-#define __HAL_RCC_GPIOC_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))
-#define __HAL_RCC_GPIOD_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))
-#define __HAL_RCC_ADC1_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
-
-#define __HAL_RCC_TIM1_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
-#define __HAL_RCC_SPI1_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_USART1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
-
-#define __HAL_RCC_APB2_RELEASE_RESET()      (RCC->APB2RSTR = 0x00)  
-#define __HAL_RCC_AFIO_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
-#define __HAL_RCC_GPIOA_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
-#define __HAL_RCC_GPIOB_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
-#define __HAL_RCC_GPIOC_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
-#define __HAL_RCC_GPIOD_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
-#define __HAL_RCC_ADC1_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
-
-#define __HAL_RCC_TIM1_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
-#define __HAL_RCC_SPI1_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_USART1_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSI_Configuration HSI Configuration
-  * @{   
-  */
-
-/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
-  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
-  * @note   HSI can not be stopped if it is used as system clock source. In this case,
-  *         you have to select another source of the system clock then stop the HSI.  
-  * @note   After enabling the HSI, the application software should wait on HSIRDY
-  *         flag to be set indicating that HSI clock is stable and can be used as
-  *         system clock source.  
-  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
-  *         clock cycles.  
-  */
-#define __HAL_RCC_HSI_ENABLE()  (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
-#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
-
-/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
-  * @note   The calibration is used to compensate for the variations in voltage
-  *         and temperature that influence the frequency of the internal HSI RC.
-  * @param  _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
-  *         (default is RCC_HSICALIBRATION_DEFAULT).
-  *         This parameter must be a number between 0 and 0x1F.
-  */  
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
-          (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSI_Configuration  LSI Configuration
-  * @{   
-  */
-
-/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
-  * @note   After enabling the LSI, the application software should wait on 
-  *         LSIRDY flag to be set indicating that LSI clock is stable and can
-  *         be used to clock the IWDG and/or the RTC.
-  */
-#define __HAL_RCC_LSI_ENABLE()  (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
-
-/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
-  * @note   LSI can not be disabled if the IWDG is running.  
-  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
-  *         clock cycles. 
-  */
-#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSE_Configuration HSE Configuration
-  * @{   
-  */
-
-/**
-  * @brief  Macro to configure the External High Speed oscillator (HSE).
-  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
-  *         supported by this macro. User should request a transition to HSE Off
-  *         first and then HSE On or HSE Bypass.
-  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
-  *         software should wait on HSERDY flag to be set indicating that HSE clock
-  *         is stable and can be used to clock the PLL and/or system clock.
-  * @note   HSE state can not be changed if it is used directly or through the
-  *         PLL as system clock. In this case, you have to select another source
-  *         of the system clock then change the HSE state (ex. disable it).
-  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
-  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
-  *         was previously enabled you have to enable it again after calling this
-  *         function.
-  * @param  __STATE__ specifies the new state of the HSE.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
-  *                              6 HSE oscillator clock cycles.
-  *            @arg @ref RCC_HSE_ON turn ON the HSE oscillator
-  *            @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
-  */
-#define __HAL_RCC_HSE_CONFIG(__STATE__)                                     \
-                    do{                                                     \
-                      if ((__STATE__) == RCC_HSE_ON)                        \
-                      {                                                     \
-                        SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
-                      }                                                     \
-                      else if ((__STATE__) == RCC_HSE_OFF)                  \
-                      {                                                     \
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
-                      }                                                     \
-                      else if ((__STATE__) == RCC_HSE_BYPASS)               \
-                      {                                                     \
-                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);                    \
-                        SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
-                      }                                                     \
-                      else                                                  \
-                      {                                                     \
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
-                      }                                                     \
-                    }while(0)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSE_Configuration LSE Configuration
-  * @{   
-  */
-
-/**
-  * @brief  Macro to configure the External Low Speed oscillator (LSE).
-  * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 
-  * @note   As the LSE is in the Backup domain and write access is denied to
-  *         this domain after reset, you have to enable write access using 
-  *         @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
-  *         (to be done once after reset).  
-  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
-  *         software should wait on LSERDY flag to be set indicating that LSE clock
-  *         is stable and can be used to clock the RTC.
-  * @param  __STATE__ specifies the new state of the LSE.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
-  *                              6 LSE oscillator clock cycles.
-  *            @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
-  *            @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
-  */
-#define __HAL_RCC_LSE_CONFIG(__STATE__)                                     \
-                    do{                                                     \
-                      if ((__STATE__) == RCC_LSE_ON)                        \
-                      {                                                     \
-                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                   \
-                      }                                                     \
-                      else if ((__STATE__) == RCC_LSE_OFF)                  \
-                      {                                                     \
-                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                 \
-                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                \
-                      }                                                     \
-                      else if ((__STATE__) == RCC_LSE_BYPASS)               \
-                      {                                                     \
-                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                  \
-                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                   \
-                      }                                                     \
-                      else                                                  \
-                      {                                                     \
-                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                 \
-                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                \
-                      }                                                     \
-                    }while(0)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Configuration PLL Configuration
-  * @{   
-  */
-
-/** @brief Macro to enable the main PLL.
-  * @note   After enabling the main PLL, the application software should wait on 
-  *         PLLRDY flag to be set indicating that PLL clock is stable and can
-  *         be used as system clock source.
-  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
-  */
-#define __HAL_RCC_PLL_ENABLE()          (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
-
-/** @brief Macro to disable the main PLL.
-  * @note   The main PLL can not be disabled if it is used as system clock source
-  */
-#define __HAL_RCC_PLL_DISABLE()         (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
-
-/** @brief Macro to configure the main PLL clock source and multiplication factors.
-  * @note   This function must be used only when the main PLL is disabled.
-  *  
-  * @param  __RCC_PLLSOURCE__ specifies the PLL entry clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry
-  *            @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
-  * @param  __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
-  *          This parameter can be one of the following values:
-  *             @arg @ref RCC_PLL_MUL4   PLLVCO = PLL clock entry x 4
-  *             @arg @ref RCC_PLL_MUL6   PLLVCO = PLL clock entry x 6
-  @if STM32F105xC
-  *             @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
-  @elseif STM32F107xC
-  *             @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
-  @else
-  *             @arg @ref RCC_PLL_MUL2   PLLVCO = PLL clock entry x 2
-  *             @arg @ref RCC_PLL_MUL3   PLLVCO = PLL clock entry x 3
-  *             @arg @ref RCC_PLL_MUL10  PLLVCO = PLL clock entry x 10
-  *             @arg @ref RCC_PLL_MUL11  PLLVCO = PLL clock entry x 11
-  *             @arg @ref RCC_PLL_MUL12  PLLVCO = PLL clock entry x 12
-  *             @arg @ref RCC_PLL_MUL13  PLLVCO = PLL clock entry x 13
-  *             @arg @ref RCC_PLL_MUL14  PLLVCO = PLL clock entry x 14
-  *             @arg @ref RCC_PLL_MUL15  PLLVCO = PLL clock entry x 15
-  *             @arg @ref RCC_PLL_MUL16  PLLVCO = PLL clock entry x 16
-  @endif
-  *             @arg @ref RCC_PLL_MUL8   PLLVCO = PLL clock entry x 8
-  *             @arg @ref RCC_PLL_MUL9   PLLVCO = PLL clock entry x 9
-  *   
-  */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
-          MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
-
-/** @brief  Get oscillator clock selected as PLL input clock
-  * @retval The clock source used for PLL entry. The returned value can be one
-  *         of the following:
-  *             @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock
-  *             @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
-  */
-#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Get_Clock_source Get Clock source
-  * @{   
-  */
-
-/**
-  * @brief  Macro to configure the system clock source.
-  * @param  __SYSCLKSOURCE__ specifies the system clock source.
-  *          This parameter can be one of the following values:
-  *              @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
-  *              @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
-  *              @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
-  */
-#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
-                  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
-
-/** @brief  Macro to get the clock source used as system clock.
-  * @retval The clock source used as system clock. The returned value can be one
-  *         of the following:
-  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
-  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
-  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
-  */
-#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
-  * @{   
-  */ 
-
-#if   defined(RCC_CFGR_MCO_3)
-/** @brief  Macro to configure the MCO clock.
-  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK      No clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_SYSCLK       System clock (SYSCLK) selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_HSI          HSI selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_HSE          HSE selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_PLLCLK       PLL clock divided by 2 selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_PLL2CLK      PLL2 clock selected by 2 selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1  external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_PLL3CLK      PLL3 clock selected (for Ethernet) as MCO clock
-  * @param  __MCODIV__ specifies the MCO clock prescaler.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
-  */
-#else
-/** @brief  Macro to configure the MCO clock.
-  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_SYSCLK  System clock (SYSCLK) selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_PLLCLK  PLL clock divided by 2 selected as MCO clock
-  * @param  __MCODIV__ specifies the MCO clock prescaler.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
-  */
-#endif
-
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
-                 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
-
-
-/**
-  * @}
-  */
-
-  /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
-  * @{   
-  */
-
-/** @brief Macro to configure the RTC clock (RTCCLK).
-  * @note   As the RTC clock configuration bits are in the Backup domain and write
-  *         access is denied to this domain after reset, you have to enable write
-  *         access using the Power Backup Access macro before to configure
-  *         the RTC clock source (to be done once after reset).    
-  * @note   Once the RTC clock is configured it can't be changed unless the  
-  *         Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
-  *         a Power On Reset (POR).
-  *
-  * @param  __RTC_CLKSOURCE__ specifies the RTC clock source.
-  *          This parameter can be one of the following values:
-  *             @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
-  *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
-  *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
-  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
-  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
-  *         work in STOP and STANDBY modes, and can be used as wakeup source.
-  *         However, when the HSE clock is used as RTC clock source, the RTC
-  *         cannot be used in STOP and STANDBY modes.    
-  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
-  *         RTC clock source).
-  */
-#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
-                                                   
-/** @brief Macro to get the RTC clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
-  *            @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
-  *            @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
-  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
-  */
-#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
-
-/** @brief Macro to enable the the RTC clock.
-  * @note   These macros must be used only after the RTC clock source was selected.
-  */
-#define __HAL_RCC_RTC_ENABLE()          (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
-
-/** @brief Macro to disable the the RTC clock.
-  * @note  These macros must be used only after the RTC clock source was selected.
-  */
-#define __HAL_RCC_RTC_DISABLE()         (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
-
-/** @brief  Macro to force the Backup domain reset.
-  * @note   This function resets the RTC peripheral (including the backup registers)
-  *         and the RTC clock source selection in RCC_BDCR register.
-  */
-#define __HAL_RCC_BACKUPRESET_FORCE()   (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
-
-/** @brief  Macros to release the Backup domain reset.
-  */
-#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
-  * @brief macros to manage the specified RCC Flags and interrupts.
-  * @{
-  */
-
-/** @brief Enable RCC interrupt.
-  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
-  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
-  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
-  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
-  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
-  @if STM32F105xx
-  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
-  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
-  @elsif STM32F107xx
-  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
-  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
-  @endif
-  */
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
-
-/** @brief Disable RCC interrupt.
-  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
-  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
-  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
-  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
-  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
-  @if STM32F105xx
-  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
-  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
-  @elsif STM32F107xx
-  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
-  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
-  @endif
-  */
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
-
-/** @brief Clear the RCC's interrupt pending bits.
-  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
-  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
-  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
-  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
-  *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
-  @if STM32F105xx
-  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
-  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
-  @elsif STM32F107xx
-  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
-  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
-  @endif
-  *            @arg @ref RCC_IT_CSS Clock Security System interrupt
-  */
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
-
-/** @brief Check the RCC's interrupt has occurred or not.
-  * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
-  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
-  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
-  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
-  *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
-  @if STM32F105xx
-  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
-  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
-  @elsif STM32F107xx
-  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
-  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
-  @endif
-  *            @arg @ref RCC_IT_CSS Clock Security System interrupt
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
-  */
-#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Set RMVF bit to clear the reset flags.
-  *         The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
-  *         RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
-  */
-#define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
-
-/** @brief  Check RCC flag is set or not.
-  * @param  __FLAG__ specifies the flag to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
-  *            @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
-  *            @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
-  @if STM32F105xx
-  *            @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
-  *            @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
-  @elsif STM32F107xx
-  *            @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
-  *            @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
-  @endif
-  *            @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
-  *            @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
-  *            @arg @ref RCC_FLAG_PINRST  Pin reset.
-  *            @arg @ref RCC_FLAG_PORRST  POR/PDR reset.
-  *            @arg @ref RCC_FLAG_SFTRST  Software reset.
-  *            @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
-  *            @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
-  *            @arg @ref RCC_FLAG_LPWRRST Low Power reset.
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)?   RCC->CR   : \
-                                      ((((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : \
-                                                                              RCC->CSR)) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Include RCC HAL Extension module */
-#include "stm32f1xx_hal_rcc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RCC_Exported_Functions_Group1
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ******************************/
-void              HAL_RCC_DeInit(void);
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency);
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCC_Exported_Functions_Group2
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
-void              HAL_RCC_EnableCSS(void);
-void              HAL_RCC_DisableCSS(void);
-uint32_t          HAL_RCC_GetSysClockFreq(void);
-uint32_t          HAL_RCC_GetHCLKFreq(void);
-uint32_t          HAL_RCC_GetPCLK1Freq(void);
-uint32_t          HAL_RCC_GetPCLK2Freq(void);
-void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
-void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency);
-
-/* CSS NMI IRQ handler */
-void              HAL_RCC_NMI_IRQHandler(void);
-
-/* User Callbacks in non blocking mode (IT mode) */
-void              HAL_RCC_CSSCallback(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_rcc_ex.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1926 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_rcc_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of RCC HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_RCC_EX_H
-#define __STM32F1xx_HAL_RCC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RCCEx
-  * @{
-  */ 
-
-/** @addtogroup RCCEx_Private_Constants
- * @{
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-
-/* Alias word address of PLLI2SON bit */
-#define PLLI2SON_BITNUMBER           POSITION_VAL(RCC_CR_PLL3ON)
-#define RCC_CR_PLLI2SON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLI2SON_BITNUMBER * 4)))
-/* Alias word address of PLL2ON bit */
-#define PLL2ON_BITNUMBER             POSITION_VAL(RCC_CR_PLL2ON)
-#define RCC_CR_PLL2ON_BB             ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLL2ON_BITNUMBER * 4)))
-
-#define PLLI2S_TIMEOUT_VALUE         ((uint32_t)100)  /* 100 ms */
-#define PLL2_TIMEOUT_VALUE           ((uint32_t)100)  /* 100 ms */
-
-#endif /* STM32F105xC || STM32F107xC */
-
-
-#define CR_REG_INDEX                 ((uint8_t)1)    
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCCEx_Private_Macros
- * @{
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \
-                                           ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2))
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
- || defined(STM32F100xE)
-#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1)  || ((__DIV__) == RCC_HSE_PREDIV_DIV2)  || \
-                                    ((__DIV__) == RCC_HSE_PREDIV_DIV3)  || ((__DIV__) == RCC_HSE_PREDIV_DIV4)  || \
-                                    ((__DIV__) == RCC_HSE_PREDIV_DIV5)  || ((__DIV__) == RCC_HSE_PREDIV_DIV6)  || \
-                                    ((__DIV__) == RCC_HSE_PREDIV_DIV7)  || ((__DIV__) == RCC_HSE_PREDIV_DIV8)  || \
-                                    ((__DIV__) == RCC_HSE_PREDIV_DIV9)  || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \
-                                    ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \
-                                    ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \
-                                    ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16))
-
-#else
-#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1)  || ((__DIV__) == RCC_HSE_PREDIV_DIV2))
-#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4)  || ((__MUL__) == RCC_PLL_MUL5) || \
-                                 ((__MUL__) == RCC_PLL_MUL6)  || ((__MUL__) == RCC_PLL_MUL7) || \
-                                 ((__MUL__) == RCC_PLL_MUL8)  || ((__MUL__) == RCC_PLL_MUL9) || \
-                                 ((__MUL__) == RCC_PLL_MUL6_5))
-
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK)  || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
-                                    || ((__SOURCE__) == RCC_MCO1SOURCE_HSE)     || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
-                                    || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \
-                                    || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \
-                                    || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
-
-#else
-#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2)  || ((__MUL__) == RCC_PLL_MUL3)  || \
-                                 ((__MUL__) == RCC_PLL_MUL4)  || ((__MUL__) == RCC_PLL_MUL5)  || \
-                                 ((__MUL__) == RCC_PLL_MUL6)  || ((__MUL__) == RCC_PLL_MUL7)  || \
-                                 ((__MUL__) == RCC_PLL_MUL8)  || ((__MUL__) == RCC_PLL_MUL9)  || \
-                                 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
-                                 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
-                                 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
-                                 ((__MUL__) == RCC_PLL_MUL16))
-
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK)  || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
-                                    || ((__SOURCE__) == RCC_MCO1SOURCE_HSE)     || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
-                                    || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
-
-#endif /* STM32F105xC || STM32F107xC*/
-
-#define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2)  || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4)   || \
-                                          ((__ADCCLK__) == RCC_ADCPCLK2_DIV6)  || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8))
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)  || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO))
-
-#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)  || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO))
-
-#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2)  || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3))
-
-#define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8)   || ((__MUL__) == RCC_PLLI2S_MUL9)  || \
-                                    ((__MUL__) == RCC_PLLI2S_MUL10)  || ((__MUL__) == RCC_PLLI2S_MUL11)  || \
-                                    ((__MUL__) == RCC_PLLI2S_MUL12)  || ((__MUL__) == RCC_PLLI2S_MUL13)  || \
-                                    ((__MUL__) == RCC_PLLI2S_MUL14)  || ((__MUL__) == RCC_PLLI2S_MUL16)  || \
-                                    ((__MUL__) == RCC_PLLI2S_MUL20))
-
-#define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1)  || ((__DIV__) == RCC_HSE_PREDIV2_DIV2)  || \
-                                     ((__DIV__) == RCC_HSE_PREDIV2_DIV3)  || ((__DIV__) == RCC_HSE_PREDIV2_DIV4)  || \
-                                     ((__DIV__) == RCC_HSE_PREDIV2_DIV5)  || ((__DIV__) == RCC_HSE_PREDIV2_DIV6)  || \
-                                     ((__DIV__) == RCC_HSE_PREDIV2_DIV7)  || ((__DIV__) == RCC_HSE_PREDIV2_DIV8)  || \
-                                     ((__DIV__) == RCC_HSE_PREDIV2_DIV9)  || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \
-                                     ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \
-                                     ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \
-                                     ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16))
-
-#define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \
-                              ((__PLL__) == RCC_PLL2_ON))
-
-#define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8)  || ((__MUL__) == RCC_PLL2_MUL9)  || \
-                                  ((__MUL__) == RCC_PLL2_MUL10)  || ((__MUL__) == RCC_PLL2_MUL11)  || \
-                                  ((__MUL__) == RCC_PLL2_MUL12)  || ((__MUL__) == RCC_PLL2_MUL13)  || \
-                                  ((__MUL__) == RCC_PLL2_MUL14)  || ((__MUL__) == RCC_PLL2_MUL16)  || \
-                                  ((__MUL__) == RCC_PLL2_MUL20))
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
-               ((((__SELECTION__) & RCC_PERIPHCLK_RTC)  == RCC_PERIPHCLK_RTC)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_ADC)  == RCC_PERIPHCLK_ADC)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_I2S2)  == RCC_PERIPHCLK_I2S2)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_I2S3)   == RCC_PERIPHCLK_I2S3)   || \
-                (((__SELECTION__) & RCC_PERIPHCLK_USB)   == RCC_PERIPHCLK_USB))
-
-#elif defined(STM32F103xE) || defined(STM32F103xG)
-
-#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)
-
-#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
-               ((((__SELECTION__) & RCC_PERIPHCLK_RTC)  == RCC_PERIPHCLK_RTC)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_ADC)  == RCC_PERIPHCLK_ADC)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3)   || \
-                (((__SELECTION__) & RCC_PERIPHCLK_USB)  == RCC_PERIPHCLK_USB))
-
-
-#elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
-               ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
-
-#else
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
-               ((((__SELECTION__) & RCC_PERIPHCLK_RTC)  == RCC_PERIPHCLK_RTC)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_ADC)  == RCC_PERIPHCLK_ADC))
-
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
-
-#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL)  || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5))
-
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
-
-/**
-  * @}
-  */
-
-/* Exported types ------------------------------------------------------------*/ 
-
-/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
-  * @{
-  */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** 
-  * @brief  RCC PLL2 configuration structure definition  
-  */
-typedef struct
-{
-  uint32_t PLL2State;     /*!< The new state of the PLL2.
-                              This parameter can be a value of @ref RCCEx_PLL2_Config */
-
-  uint32_t PLL2MUL;         /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock
-                              This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/        
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-  uint32_t HSEPrediv2Value;       /*!<  The Prediv2 factor value.
-                                       This parameter can be a value of @ref RCCEx_Prediv2_Factor */
-
-#endif /* STM32F105xC || STM32F107xC */
-} RCC_PLL2InitTypeDef;
-
-#endif /* STM32F105xC || STM32F107xC */
-
-/** 
-  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition  
-  */
-typedef struct
-{
-  uint32_t OscillatorType;       /*!< The oscillators to be configured.
-                                       This parameter can be a value of @ref RCC_Oscillator_Type */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-  uint32_t Prediv1Source;       /*!<  The Prediv1 source value.
-                                       This parameter can be a value of @ref RCCEx_Prediv1_Source */
-#endif /* STM32F105xC || STM32F107xC */
-
-  uint32_t HSEState;              /*!< The new state of the HSE.
-                                       This parameter can be a value of @ref RCC_HSE_Config */
-                          
-  uint32_t HSEPredivValue;       /*!<  The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM)
-                                       This parameter can be a value of @ref RCCEx_Prediv1_Factor */
-
-  uint32_t LSEState;              /*!<  The new state of the LSE.
-                                        This parameter can be a value of @ref RCC_LSE_Config */
-                                          
-  uint32_t HSIState;              /*!< The new state of the HSI.
-                                       This parameter can be a value of @ref RCC_HSI_Config */
-
-  uint32_t HSICalibrationValue;   /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
-                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
-                               
-  uint32_t LSIState;              /*!<  The new state of the LSI.
-                                        This parameter can be a value of @ref RCC_LSI_Config */
-
-  RCC_PLLInitTypeDef PLL;         /*!< PLL structure parameters */      
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-  RCC_PLL2InitTypeDef PLL2;         /*!< PLL2 structure parameters */      
-#endif /* STM32F105xC || STM32F107xC */
-} RCC_OscInitTypeDef;
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** 
-  * @brief  RCC PLLI2S configuration structure definition  
-  */
-typedef struct
-{
-  uint32_t PLLI2SMUL;         /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock
-                              This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/        
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-  uint32_t HSEPrediv2Value;       /*!<  The Prediv2 factor value.
-                                       This parameter can be a value of @ref RCCEx_Prediv2_Factor */
-
-#endif /* STM32F105xC || STM32F107xC */
-} RCC_PLLI2SInitTypeDef;
-#endif /* STM32F105xC || STM32F107xC */
-
-/** 
-  * @brief  RCC extended clocks structure definition  
-  */
-typedef struct
-{
-  uint32_t PeriphClockSelection;      /*!< The Extended Clock to be configured.
-                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
-  uint32_t RTCClockSelection;         /*!< specifies the RTC clock source.
-                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
-  uint32_t AdcClockSelection;         /*!< ADC clock source      
-                                       This parameter can be a value of @ref RCCEx_ADC_Prescaler */
-
-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
- || defined(STM32F107xC)
-  uint32_t I2s2ClockSelection;         /*!< I2S2 clock source
-                                       This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */
-
-  uint32_t I2s3ClockSelection;         /*!< I2S3 clock source
-                                       This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */
-  
-#if defined(STM32F105xC) || defined(STM32F107xC)
-  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters 
-                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */
-
-#endif /* STM32F105xC || STM32F107xC */
-#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
-  uint32_t UsbClockSelection;         /*!< USB clock source      
-                                       This parameter can be a value of @ref RCCEx_USB_Prescaler */
-
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-} RCC_PeriphCLKInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
-  * @{
-  */
-
-/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
-  * @{
-  */
-#define RCC_PERIPHCLK_RTC           ((uint32_t)0x00000001)
-#define RCC_PERIPHCLK_ADC           ((uint32_t)0x00000002)
-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
- || defined(STM32F107xC)
-#define RCC_PERIPHCLK_I2S2          ((uint32_t)0x00000004)
-#define RCC_PERIPHCLK_I2S3          ((uint32_t)0x00000008)
-#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
-#define RCC_PERIPHCLK_USB          ((uint32_t)0x00000010)
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_ADC_Prescaler ADC Prescaler
-  * @{
-  */
-#define RCC_ADCPCLK2_DIV2              RCC_CFGR_ADCPRE_DIV2
-#define RCC_ADCPCLK2_DIV4              RCC_CFGR_ADCPRE_DIV4
-#define RCC_ADCPCLK2_DIV6              RCC_CFGR_ADCPRE_DIV6
-#define RCC_ADCPCLK2_DIV8              RCC_CFGR_ADCPRE_DIV8
-
-/**
-  * @}
-  */
-
-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
- || defined(STM32F107xC)
-/** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source
-  * @{
-  */
-#define RCC_I2S2CLKSOURCE_SYSCLK              ((uint32_t)0x00000000)
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define RCC_I2S2CLKSOURCE_PLLI2S_VCO            RCC_CFGR2_I2S2SRC
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source
-  * @{
-  */
-#define RCC_I2S3CLKSOURCE_SYSCLK              ((uint32_t)0x00000000)
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define RCC_I2S3CLKSOURCE_PLLI2S_VCO            RCC_CFGR2_I2S3SRC
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
-  * @}
-  */
-
-#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
-
-/** @defgroup RCCEx_USB_Prescaler USB Prescaler
-  * @{
-  */
-#define RCC_USBCLKSOURCE_PLL              RCC_CFGR_USBPRE
-#define RCC_USBCLKSOURCE_PLL_DIV1_5            ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
-
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_USB_Prescaler USB Prescaler
-  * @{
-  */
-#define RCC_USBCLKSOURCE_PLL_DIV2              RCC_CFGR_OTGFSPRE
-#define RCC_USBCLKSOURCE_PLL_DIV3              ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor
-  * @{
-  */
-
-#define RCC_PLLI2S_MUL8                   RCC_CFGR2_PLL3MUL8   /*!< PLLI2S input clock * 8 */
-#define RCC_PLLI2S_MUL9                   RCC_CFGR2_PLL3MUL9   /*!< PLLI2S input clock * 9 */
-#define RCC_PLLI2S_MUL10                  RCC_CFGR2_PLL3MUL10  /*!< PLLI2S input clock * 10 */
-#define RCC_PLLI2S_MUL11                  RCC_CFGR2_PLL3MUL11  /*!< PLLI2S input clock * 11 */
-#define RCC_PLLI2S_MUL12                  RCC_CFGR2_PLL3MUL12  /*!< PLLI2S input clock * 12 */
-#define RCC_PLLI2S_MUL13                  RCC_CFGR2_PLL3MUL13  /*!< PLLI2S input clock * 13 */
-#define RCC_PLLI2S_MUL14                  RCC_CFGR2_PLL3MUL14  /*!< PLLI2S input clock * 14 */
-#define RCC_PLLI2S_MUL16                  RCC_CFGR2_PLL3MUL16  /*!< PLLI2S input clock * 16 */
-#define RCC_PLLI2S_MUL20                  RCC_CFGR2_PLL3MUL20  /*!< PLLI2S input clock * 20 */
-
-/**
-  * @}
-  */
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_Prediv1_Source Prediv1 Source
-  * @{
-  */
-
-#define RCC_PREDIV1_SOURCE_HSE           RCC_CFGR2_PREDIV1SRC_HSE
-#define RCC_PREDIV1_SOURCE_PLL2          RCC_CFGR2_PREDIV1SRC_PLL2
-
-/**
-  * @}
-  */
-#endif /* STM32F105xC || STM32F107xC */
-
-/** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor
-  * @{
-  */
-
-#define RCC_HSE_PREDIV_DIV1              ((uint32_t)0x00000000)
-
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
- || defined(STM32F100xE)
-#define RCC_HSE_PREDIV_DIV2              RCC_CFGR2_PREDIV1_DIV2
-#define RCC_HSE_PREDIV_DIV3              RCC_CFGR2_PREDIV1_DIV3
-#define RCC_HSE_PREDIV_DIV4              RCC_CFGR2_PREDIV1_DIV4
-#define RCC_HSE_PREDIV_DIV5              RCC_CFGR2_PREDIV1_DIV5
-#define RCC_HSE_PREDIV_DIV6              RCC_CFGR2_PREDIV1_DIV6
-#define RCC_HSE_PREDIV_DIV7              RCC_CFGR2_PREDIV1_DIV7
-#define RCC_HSE_PREDIV_DIV8              RCC_CFGR2_PREDIV1_DIV8
-#define RCC_HSE_PREDIV_DIV9              RCC_CFGR2_PREDIV1_DIV9
-#define RCC_HSE_PREDIV_DIV10             RCC_CFGR2_PREDIV1_DIV10
-#define RCC_HSE_PREDIV_DIV11             RCC_CFGR2_PREDIV1_DIV11
-#define RCC_HSE_PREDIV_DIV12             RCC_CFGR2_PREDIV1_DIV12
-#define RCC_HSE_PREDIV_DIV13             RCC_CFGR2_PREDIV1_DIV13
-#define RCC_HSE_PREDIV_DIV14             RCC_CFGR2_PREDIV1_DIV14
-#define RCC_HSE_PREDIV_DIV15             RCC_CFGR2_PREDIV1_DIV15
-#define RCC_HSE_PREDIV_DIV16             RCC_CFGR2_PREDIV1_DIV16
-#else
-#define RCC_HSE_PREDIV_DIV2              RCC_CFGR_PLLXTPRE
-#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
-
-/**
-  * @}
-  */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor
-  * @{
-  */
-
-#define RCC_HSE_PREDIV2_DIV1                RCC_CFGR2_PREDIV2_DIV1   /*!< PREDIV2 input clock not divided */
-#define RCC_HSE_PREDIV2_DIV2                RCC_CFGR2_PREDIV2_DIV2   /*!< PREDIV2 input clock divided by 2 */
-#define RCC_HSE_PREDIV2_DIV3                RCC_CFGR2_PREDIV2_DIV3   /*!< PREDIV2 input clock divided by 3 */
-#define RCC_HSE_PREDIV2_DIV4                RCC_CFGR2_PREDIV2_DIV4   /*!< PREDIV2 input clock divided by 4 */
-#define RCC_HSE_PREDIV2_DIV5                RCC_CFGR2_PREDIV2_DIV5   /*!< PREDIV2 input clock divided by 5 */
-#define RCC_HSE_PREDIV2_DIV6                RCC_CFGR2_PREDIV2_DIV6   /*!< PREDIV2 input clock divided by 6 */
-#define RCC_HSE_PREDIV2_DIV7                RCC_CFGR2_PREDIV2_DIV7   /*!< PREDIV2 input clock divided by 7 */
-#define RCC_HSE_PREDIV2_DIV8                RCC_CFGR2_PREDIV2_DIV8   /*!< PREDIV2 input clock divided by 8 */
-#define RCC_HSE_PREDIV2_DIV9                RCC_CFGR2_PREDIV2_DIV9   /*!< PREDIV2 input clock divided by 9 */
-#define RCC_HSE_PREDIV2_DIV10               RCC_CFGR2_PREDIV2_DIV10  /*!< PREDIV2 input clock divided by 10 */
-#define RCC_HSE_PREDIV2_DIV11               RCC_CFGR2_PREDIV2_DIV11  /*!< PREDIV2 input clock divided by 11 */
-#define RCC_HSE_PREDIV2_DIV12               RCC_CFGR2_PREDIV2_DIV12  /*!< PREDIV2 input clock divided by 12 */
-#define RCC_HSE_PREDIV2_DIV13               RCC_CFGR2_PREDIV2_DIV13  /*!< PREDIV2 input clock divided by 13 */
-#define RCC_HSE_PREDIV2_DIV14               RCC_CFGR2_PREDIV2_DIV14  /*!< PREDIV2 input clock divided by 14 */
-#define RCC_HSE_PREDIV2_DIV15               RCC_CFGR2_PREDIV2_DIV15  /*!< PREDIV2 input clock divided by 15 */
-#define RCC_HSE_PREDIV2_DIV16               RCC_CFGR2_PREDIV2_DIV16  /*!< PREDIV2 input clock divided by 16 */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_PLL2_Config PLL Config
-  * @{
-  */
-#define RCC_PLL2_NONE                      ((uint32_t)0x00000000)
-#define RCC_PLL2_OFF                       ((uint32_t)0x00000001)
-#define RCC_PLL2_ON                        ((uint32_t)0x00000002)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor
-  * @{
-  */
-
-#define RCC_PLL2_MUL8                   RCC_CFGR2_PLL2MUL8   /*!< PLL2 input clock * 8 */
-#define RCC_PLL2_MUL9                   RCC_CFGR2_PLL2MUL9   /*!< PLL2 input clock * 9 */
-#define RCC_PLL2_MUL10                  RCC_CFGR2_PLL2MUL10  /*!< PLL2 input clock * 10 */
-#define RCC_PLL2_MUL11                  RCC_CFGR2_PLL2MUL11  /*!< PLL2 input clock * 11 */
-#define RCC_PLL2_MUL12                  RCC_CFGR2_PLL2MUL12  /*!< PLL2 input clock * 12 */
-#define RCC_PLL2_MUL13                  RCC_CFGR2_PLL2MUL13  /*!< PLL2 input clock * 13 */
-#define RCC_PLL2_MUL14                  RCC_CFGR2_PLL2MUL14  /*!< PLL2 input clock * 14 */
-#define RCC_PLL2_MUL16                  RCC_CFGR2_PLL2MUL16  /*!< PLL2 input clock * 16 */
-#define RCC_PLL2_MUL20                  RCC_CFGR2_PLL2MUL20  /*!< PLL2 input clock * 20 */
-
-/**
-  * @}
-  */
-
-#endif /* STM32F105xC || STM32F107xC */
-
-/** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor
-  * @{
-  */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#else
-#define RCC_PLL_MUL2                    RCC_CFGR_PLLMULL2
-#define RCC_PLL_MUL3                    RCC_CFGR_PLLMULL3
-#endif /* STM32F105xC || STM32F107xC */
-#define RCC_PLL_MUL4                    RCC_CFGR_PLLMULL4
-#define RCC_PLL_MUL5                    RCC_CFGR_PLLMULL5
-#define RCC_PLL_MUL6                    RCC_CFGR_PLLMULL6
-#define RCC_PLL_MUL7                    RCC_CFGR_PLLMULL7
-#define RCC_PLL_MUL8                    RCC_CFGR_PLLMULL8
-#define RCC_PLL_MUL9                    RCC_CFGR_PLLMULL9
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define RCC_PLL_MUL6_5                  RCC_CFGR_PLLMULL6_5
-#else
-#define RCC_PLL_MUL10                   RCC_CFGR_PLLMULL10
-#define RCC_PLL_MUL11                   RCC_CFGR_PLLMULL11
-#define RCC_PLL_MUL12                   RCC_CFGR_PLLMULL12
-#define RCC_PLL_MUL13                   RCC_CFGR_PLLMULL13
-#define RCC_PLL_MUL14                   RCC_CFGR_PLLMULL14
-#define RCC_PLL_MUL15                   RCC_CFGR_PLLMULL15
-#define RCC_PLL_MUL16                   RCC_CFGR_PLLMULL16
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source
-  * @{
-  */
-#define RCC_MCO1SOURCE_NOCLOCK           ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
-#define RCC_MCO1SOURCE_SYSCLK            ((uint32_t)RCC_CFGR_MCO_SYSCLK)
-#define RCC_MCO1SOURCE_HSI               ((uint32_t)RCC_CFGR_MCO_HSI)
-#define RCC_MCO1SOURCE_HSE               ((uint32_t)RCC_CFGR_MCO_HSE)
-#define RCC_MCO1SOURCE_PLLCLK            ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define RCC_MCO1SOURCE_PLL2CLK           ((uint32_t)RCC_CFGR_MCO_PLL2CLK)
-#define RCC_MCO1SOURCE_PLL3CLK_DIV2      ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2)
-#define RCC_MCO1SOURCE_EXT_HSE           ((uint32_t)RCC_CFGR_MCO_EXT_HSE)
-#define RCC_MCO1SOURCE_PLL3CLK           ((uint32_t)RCC_CFGR_MCO_PLL3CLK)
-#endif /* STM32F105xC || STM32F107xC*/
-/**
-  * @}
-  */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_Interrupt RCCEx Interrupt
-  * @{
-  */
-#define RCC_IT_PLL2RDY                   ((uint8_t)RCC_CIR_PLL2RDYF)
-#define RCC_IT_PLLI2SRDY                 ((uint8_t)RCC_CIR_PLL3RDYF)
-/**
-  * @}
-  */  
-
-/** @defgroup RCCEx_Flag RCCEx Flag
-  *        Elements values convention: 0XXYYYYYb
-  *           - YYYYY  : Flag position in the register
-  *           - XX  : Register index
-  *                 - 01: CR register
-  * @{
-  */
-/* Flags in the CR register */
-#define RCC_FLAG_PLL2RDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL2RDY)))
-#define RCC_FLAG_PLLI2SRDY                ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL3RDY)))
-/**
-  * @}
-  */ 
-#endif /* STM32F105xC || STM32F107xC*/
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
- * @{
- */
-
-/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.   
-  * @{
-  */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined(STM32F105xC) || defined  (STM32F107xC)\
- || defined  (STM32F100xE)
-#define __HAL_RCC_DMA2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_DMA2_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined  (STM32F100xE)
-#define __HAL_RCC_FSMC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_FSMC_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
-
-#if defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_SDIO_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-
-#define __HAL_RCC_SDIO_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))
-#endif /* STM32F103xE || STM32F103xG */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()       (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN))
-#endif /* STM32F105xC || STM32F107xC*/
-
-#if defined(STM32F107xC)
-#define __HAL_RCC_ETHMAC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_ETHMACTX_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_ETHMACRX_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_ETHMAC_CLK_DISABLE()      (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN))
-#define __HAL_RCC_ETHMACTX_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN))
-#define __HAL_RCC_ETHMACRX_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN))
-
-/**
-  * @brief  Enable ETHERNET clock.
-  */
-#define __HAL_RCC_ETH_CLK_ENABLE() do {                                     \
-                                        __HAL_RCC_ETHMAC_CLK_ENABLE();      \
-                                        __HAL_RCC_ETHMACTX_CLK_ENABLE();    \
-                                        __HAL_RCC_ETHMACRX_CLK_ENABLE();    \
-                                      } while(0)
-/**
-  * @brief  Disable ETHERNET clock.
-  */
-#define __HAL_RCC_ETH_CLK_DISABLE()  do {                                      \
-                                          __HAL_RCC_ETHMACTX_CLK_DISABLE();    \
-                                          __HAL_RCC_ETHMACRX_CLK_DISABLE();    \
-                                          __HAL_RCC_ETHMAC_CLK_DISABLE();      \
-                                        } while(0)
-                                     
-#endif /* STM32F107xC*/
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined(STM32F105xC) || defined  (STM32F107xC)\
- || defined  (STM32F100xE)
-#define __HAL_RCC_DMA2_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
-#define __HAL_RCC_DMA2_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined  (STM32F100xE)
-#define __HAL_RCC_FSMC_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET)
-#define __HAL_RCC_FSMC_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET)
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
-#if defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET)
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET)
-#endif /* STM32F103xE || STM32F103xG */
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET)
-#endif /* STM32F105xC || STM32F107xC*/
-#if defined(STM32F107xC)
-#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET)
-#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET)
-#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET)
-#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET)
-#endif /* STM32F107xC*/
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
-  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it. 
-  * @{   
-  */
-
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
- || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
-#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_CAN1_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
-#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
- || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM4_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_USART3_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM4_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_SPI2_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_USART3_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#define __HAL_RCC_I2C2_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
-#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_USB_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_USB_CLK_DISABLE()         (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM5_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_UART4_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_UART5_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_DAC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM5_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_UART4_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __HAL_RCC_UART5_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-#define __HAL_RCC_DAC_CLK_DISABLE()         (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F100xB) || defined  (STM32F100xE)
-#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_DAC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_CEC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM6_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_DAC_CLK_DISABLE()         (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-#define __HAL_RCC_CEC_CLK_DISABLE()         (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
-#endif /* STM32F100xB || STM32F100xE */
-
-#ifdef STM32F100xE
-#define __HAL_RCC_TIM5_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM12_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM13_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM14_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_UART4_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_UART5_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM5_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
-#define __HAL_RCC_TIM12_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __HAL_RCC_TIM13_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __HAL_RCC_TIM14_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_UART4_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __HAL_RCC_UART5_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-#endif /* STM32F100xE */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_CAN2_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F101xG) || defined(STM32F103xG)
-#define __HAL_RCC_TIM12_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM13_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM14_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM12_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __HAL_RCC_TIM13_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __HAL_RCC_TIM14_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#endif /* STM32F101xG || STM32F103xG*/
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
- || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
-#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
- || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
-#define __HAL_RCC_SPI2_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
-#define __HAL_RCC_USART3_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
-#define __HAL_RCC_USART3_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
-#define __HAL_RCC_I2C2_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
-#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_USB_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
-#define __HAL_RCC_USB_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM5_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
-#define __HAL_RCC_TIM5_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
-#define __HAL_RCC_UART4_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
-#define __HAL_RCC_UART4_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
-#define __HAL_RCC_UART5_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
-#define __HAL_RCC_UART5_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
-#define __HAL_RCC_DAC_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
-#define __HAL_RCC_DAC_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
-#if defined(STM32F100xB) || defined  (STM32F100xE)
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
-#define __HAL_RCC_DAC_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
-#define __HAL_RCC_DAC_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
-#define __HAL_RCC_CEC_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
-#define __HAL_RCC_CEC_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
-#endif /* STM32F100xB || STM32F100xE */
-#ifdef STM32F100xE
-#define __HAL_RCC_TIM5_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
-#define __HAL_RCC_TIM5_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
-#define __HAL_RCC_TIM12_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
-#define __HAL_RCC_TIM12_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
-#define __HAL_RCC_TIM13_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
-#define __HAL_RCC_TIM13_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
-#define __HAL_RCC_TIM14_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
-#define __HAL_RCC_TIM14_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
-#define __HAL_RCC_UART4_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
-#define __HAL_RCC_UART4_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
-#define __HAL_RCC_UART5_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
-#define __HAL_RCC_UART5_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
-#define __HAL_RCC_CAN2_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
-#define __HAL_RCC_CAN2_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
-#endif /* STM32F100xE */
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM12_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
-#define __HAL_RCC_TIM12_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
-#endif /* STM32F105xC || STM32F107xC */
-#if defined(STM32F101xG) || defined(STM32F103xG)
-#define __HAL_RCC_TIM13_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
-#define __HAL_RCC_TIM13_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
-#define __HAL_RCC_TIM14_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
-#define __HAL_RCC_TIM14_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
-#endif /* STM32F101xG || STM32F103xG*/
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{   
-  */
-
-#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
- || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
- || defined(STM32F103xG)
-#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_ADC2_CLK_DISABLE()        (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
-#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
-
-#if defined(STM32F100xB) || defined(STM32F100xE)
-#define __HAL_RCC_TIM15_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM16_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM17_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM15_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
-#define __HAL_RCC_TIM16_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
-#define __HAL_RCC_TIM17_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
-#endif /* STM32F100xB || STM32F100xE */
-
-#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
- || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
- || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
- || defined(STM32F107xC)
-#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOE_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))
-#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG)
-#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOF_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
-#define __HAL_RCC_GPIOG_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
-
-#if defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM8_CLK_DISABLE()        (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#define __HAL_RCC_ADC3_CLK_DISABLE()        (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
-#endif /* STM32F103xE || STM32F103xG */
-
-#if defined(STM32F100xE)
-#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOF_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
-#define __HAL_RCC_GPIOG_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
-#endif /* STM32F100xE */
-
-#if defined(STM32F101xG) || defined(STM32F103xG)
-#define __HAL_RCC_TIM9_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM10_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM11_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM9_CLK_DISABLE()        (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
-#define __HAL_RCC_TIM10_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-#define __HAL_RCC_TIM11_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
-#endif /* STM32F101xG || STM32F103xG */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
- || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
- || defined(STM32F103xG)
-#define __HAL_RCC_ADC2_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
-#define __HAL_RCC_ADC2_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
-#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
-#if defined(STM32F100xB) || defined(STM32F100xE)
-#define __HAL_RCC_TIM15_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
-#define __HAL_RCC_TIM15_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
-#define __HAL_RCC_TIM16_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
-#define __HAL_RCC_TIM16_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
-#define __HAL_RCC_TIM17_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
-#define __HAL_RCC_TIM17_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
-#endif /* STM32F100xB || STM32F100xE */
-#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
- || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
- || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
- || defined(STM32F107xC)
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
-#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG)
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
-#if defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
-#define __HAL_RCC_ADC3_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
-#define __HAL_RCC_ADC3_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
-#endif /* STM32F103xE || STM32F103xG */
-#if defined(STM32F100xE)
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
-#endif /* STM32F100xE */
-#if defined(STM32F101xG) || defined(STM32F103xG)
-#define __HAL_RCC_TIM9_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
-#define __HAL_RCC_TIM9_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
-#define __HAL_RCC_TIM10_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
-#define __HAL_RCC_TIM10_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
-#define __HAL_RCC_TIM11_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
-#define __HAL_RCC_TIM11_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
-#endif /* STM32F101xG || STM32F103xG */
-
-/**
-  * @}
-  */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release
-  * @brief  Force or release AHB peripheral reset.
-  * @{
-  */  
-#define __HAL_RCC_AHB_FORCE_RESET()         (RCC->AHBRSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()       (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST))
-#if defined(STM32F107xC)
-#define __HAL_RCC_ETHMAC_FORCE_RESET()      (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST))
-#endif /* STM32F107xC */
-
-#define __HAL_RCC_AHB_RELEASE_RESET()       (RCC->AHBRSTR = 0x00)
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()     (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST))
-#if defined(STM32F107xC)
-#define __HAL_RCC_ETHMAC_RELEASE_RESET()    (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST))
-#endif /* STM32F107xC */
-
-/**
-  * @}
-  */
-#endif /* STM32F105xC || STM32F107xC */
-
-/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
-  * @brief  Force or release APB1 peripheral reset.
-  * @{   
-  */
-
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
- || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
-#define __HAL_RCC_CAN1_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
-
-#define __HAL_RCC_CAN1_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
-#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
- || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM4_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI2_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_USART3_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_I2C2_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-
-#define __HAL_RCC_TIM4_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI2_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_USART3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_I2C2_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
-#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_USB_FORCE_RESET()         (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
-#define __HAL_RCC_USB_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM5_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_TIM6_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_SPI3_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_UART4_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_DAC_FORCE_RESET()         (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-
-#define __HAL_RCC_TIM5_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_UART4_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_DAC_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F100xB) || defined  (STM32F100xE)
-#define __HAL_RCC_TIM6_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_DAC_FORCE_RESET()         (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_CEC_FORCE_RESET()         (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
-
-#define __HAL_RCC_TIM6_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_DAC_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_CEC_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
-#endif /* STM32F100xB || STM32F100xE */
-
-#if defined  (STM32F100xE)
-#define __HAL_RCC_TIM5_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_TIM12_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_SPI3_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_UART4_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-
-#define __HAL_RCC_TIM5_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_TIM12_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_UART4_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-#endif /* STM32F100xE */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_CAN2_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
-
-#define __HAL_RCC_CAN2_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F101xG) || defined(STM32F103xG)
-#define __HAL_RCC_TIM12_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-
-#define __HAL_RCC_TIM12_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#endif /* STM32F101xG || STM32F103xG */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
-  * @brief  Force or release APB2 peripheral reset.
-  * @{   
-  */
-
-#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
- || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
- || defined(STM32F103xG)
-#define __HAL_RCC_ADC2_FORCE_RESET()        (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))
-
-#define __HAL_RCC_ADC2_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
-#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
-
-#if defined(STM32F100xB) || defined(STM32F100xE)
-#define __HAL_RCC_TIM15_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
-#define __HAL_RCC_TIM16_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
-#define __HAL_RCC_TIM17_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
-
-#define __HAL_RCC_TIM15_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
-#define __HAL_RCC_TIM16_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
-#define __HAL_RCC_TIM17_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
-#endif /* STM32F100xB || STM32F100xE */
-
-#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
- || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
- || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
- || defined(STM32F107xC)
-#define __HAL_RCC_GPIOE_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))
-
-#define __HAL_RCC_GPIOE_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
-#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG)
-#define __HAL_RCC_GPIOF_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
-#define __HAL_RCC_GPIOG_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
-
-#define __HAL_RCC_GPIOF_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
-#define __HAL_RCC_GPIOG_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
-
-#if defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_TIM8_FORCE_RESET()        (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_ADC3_FORCE_RESET()        (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST))
-
-#define __HAL_RCC_TIM8_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_ADC3_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))
-#endif /* STM32F103xE || STM32F103xG */
-
-#if defined(STM32F100xE)
-#define __HAL_RCC_GPIOF_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
-#define __HAL_RCC_GPIOG_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
-
-#define __HAL_RCC_GPIOF_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
-#define __HAL_RCC_GPIOG_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
-#endif /* STM32F100xE */
-
-#if defined(STM32F101xG) || defined(STM32F103xG)
-#define __HAL_RCC_TIM9_FORCE_RESET()        (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
-#define __HAL_RCC_TIM10_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_TIM11_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
-
-#define __HAL_RCC_TIM9_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
-#define __HAL_RCC_TIM10_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_TIM11_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
-#endif /* STM32F101xG || STM32F103xG*/
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_HSE_Configuration HSE Configuration
-  * @{   
-  */ 
-
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
- || defined(STM32F100xE)
-/**
-  * @brief  Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
-  * @note   Predivision factor can not be changed if PLL is used as system clock
-  *         In this case, you have to select another source of the system clock, disable the PLL and
-  *         then change the HSE predivision factor.
-  * @param  __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
-  *         This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
-  */
-#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__))
-#else
-/**
-  * @brief  Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
-  * @note   Predivision factor can not be changed if PLL is used as system clock
-  *         In this case, you have to select another source of the system clock, disable the PLL and
-  *         then change the HSE predivision factor.
-  * @param  __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
-  *         This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2.
-  */
-#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
-                  MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
-
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
- || defined(STM32F100xE)
-/**
-  * @brief  Macro to get prediv1 factor for PLL.
-  */
-#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)
-
-#else
-/**
-  * @brief  Macro to get prediv1 factor for PLL.
-  */
-#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
-
-#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
-
-/**
-  * @}
-  */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration
-  * @{   
-  */ 
-
-/** @brief Macros to enable the main PLLI2S.
-  * @note   After enabling the main PLLI2S, the application software should wait on 
-  *         PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can
-  *         be used as system clock source.
-  * @note   The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
-  */
-#define __HAL_RCC_PLLI2S_ENABLE()          (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
-
-/** @brief Macros to disable the main PLLI2S.
-  * @note   The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
-  */
-#define __HAL_RCC_PLLI2S_DISABLE()         (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
-
-/** @brief macros to configure the main PLLI2S multiplication factor.
-  * @note   This function must be used only when the main PLLI2S is disabled.
-  *  
-  * @param  __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock
-  *          This parameter can be one of the following values:
-  *             @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8
-  *             @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9
-  *             @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10
-  *             @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11
-  *             @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12
-  *             @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13
-  *             @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14
-  *             @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16
-  *             @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20
-  *   
-  */
-#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\
-          MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__))
-
-/**
-  * @}
-  */
-
-#endif /* STM32F105xC || STM32F107xC */
-
-/** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration
-  * @brief  Macros to configure clock source of different peripherals.
-  * @{
-  */  
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
-/** @brief  Macro to configure the USB clock.
-  * @param  __USBCLKSOURCE__ specifies the USB clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
-  *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
-  */
-#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
-                  MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
-
-/** @brief  Macro to get the USB clock (USBCLK).
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
-  *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
-  */
-#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
-
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-
-/** @brief  Macro to configure the USB OTSclock.
-  * @param  __USBCLKSOURCE__ specifies the USB clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
-  *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
-  */
-#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
-                  MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__))
-
-/** @brief  Macro to get the USB clock (USBCLK).
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
-  *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
-  */
-#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE)))
-
-#endif /* STM32F105xC || STM32F107xC */
-
-/** @brief  Macro to configure the ADCx clock (x=1 to 3 depending on devices).
-  * @param  __ADCCLKSOURCE__ specifies the ADC clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
-  *            @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
-  *            @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
-  *            @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
-  */
-#define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \
-                  MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
-
-/** @brief  Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
-  *            @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
-  *            @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
-  *            @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
-  */
-#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
-
-/**
-  * @}
-  */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-
-/** @addtogroup RCCEx_HSE_Configuration
-  * @{   
-  */ 
-
-/**
-  * @brief  Macro to configure the PLL2 & PLLI2S Predivision factor.
-  * @note   Predivision factor can not be changed if PLL2 is used indirectly as system clock
-  *         In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and
-  *         then change the PREDIV2 factor.
-  * @param  __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S.
-  *         This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16.
-  */
-#define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \
-                  MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__))
-                  
-/**
-  * @brief  Macro to get prediv2 factor for PLL2 & PLL3.
-  */
-#define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCCEx_PLLI2S_Configuration
-  * @{   
-  */ 
-
-/** @brief Macros to enable the main PLL2.
-  * @note   After enabling the main PLL2, the application software should wait on 
-  *         PLL2RDY flag to be set indicating that PLL2 clock is stable and can
-  *         be used as system clock source.
-  * @note   The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
-  */
-#define __HAL_RCC_PLL2_ENABLE()          (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE)
-
-/** @brief Macros to disable the main PLL2.
-  * @note   The main PLL2 can not be disabled if it is used indirectly as system clock source
-  * @note   The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
-  */
-#define __HAL_RCC_PLL2_DISABLE()         (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE)
-
-/** @brief macros to configure the main PLL2 multiplication factor.
-  * @note   This function must be used only when the main PLL2 is disabled.
-  *  
-  * @param  __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock
-  *          This parameter can be one of the following values:
-  *             @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8
-  *             @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9
-  *             @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10
-  *             @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11
-  *             @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12
-  *             @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13
-  *             @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14
-  *             @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16
-  *             @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20
-  *   
-  */
-#define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\
-          MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2S_Configuration I2S Configuration
-  * @brief  Macros to configure clock source of I2S peripherals.
-  * @{
-  */  
-
-/** @brief  Macro to configure the I2S2 clock.
-  * @param  __I2S2CLKSOURCE__ specifies the I2S2 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
-  *            @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
-  */
-#define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \
-                  MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__))
-
-/** @brief  Macro to get the I2S2 clock (I2S2CLK).
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
-  *            @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
-  */
-#define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC)))
-
-/** @brief  Macro to configure the I2S3 clock.
-  * @param  __I2S2CLKSOURCE__ specifies the I2S3 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
-  *            @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
-  */
-#define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \
-                  MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__))
-
-/** @brief  Macro to get the I2S3 clock (I2S3CLK).
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
-  *            @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
-  */
-#define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC)))
-
-/**
-  * @}
-  */
-
-#endif /* STM32F105xC || STM32F107xC */
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCCEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RCCEx_Exported_Functions_Group1
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
-void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
-uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
-
-/**
-  * @}
-  */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @addtogroup RCCEx_Exported_Functions_Group2
-  * @{
-  */
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit);
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCCEx_Exported_Functions_Group3
-  * @{
-  */
-HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef  *PLL2Init);
-HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);
-
-/**
-  * @}
-  */
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_RCC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_rtc.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,570 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_rtc.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of RTC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_RTC_H
-#define __STM32F1xx_HAL_RTC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RTC
-  * @{
-  */ 
-
-/** @addtogroup RTC_Private_Macros
-  * @{
-  */
-
-#define IS_RTC_ASYNCH_PREDIV(PREDIV)  (((PREDIV) <= (uint32_t)0xFFFFF) || ((PREDIV) == RTC_AUTO_1_SECOND))
-#define IS_RTC_HOUR24(HOUR)           ((HOUR) <= (uint32_t)23)
-#define IS_RTC_MINUTES(MINUTES)       ((MINUTES) <= (uint32_t)59)
-#define IS_RTC_SECONDS(SECONDS)       ((SECONDS) <= (uint32_t)59)
-#define IS_RTC_FORMAT(FORMAT)         (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
-#define IS_RTC_YEAR(YEAR)             ((YEAR) <= (uint32_t)99)
-#define IS_RTC_MONTH(MONTH)           (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
-#define IS_RTC_DATE(DATE)             (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
-#define IS_RTC_ALARM(ALARM)           ((ALARM) == RTC_ALARM_A)
-#define IS_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_OUTPUTSOURCE_NONE) || \
-                                         ((__OUTPUT__) == RTC_OUTPUTSOURCE_CALIBCLOCK) || \
-                                         ((__OUTPUT__) == RTC_OUTPUTSOURCE_ALARM) || \
-                                         ((__OUTPUT__) == RTC_OUTPUTSOURCE_SECOND)) 
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Private_Constants
-  * @{
-  */
-/** @defgroup RTC_Timeout_Value Default Timeout Value
-  * @{
-  */ 
-#define RTC_TIMEOUT_VALUE           1000
-/**
-  * @}
-  */  
-  
-/** @defgroup RTC_EXTI_Line_Event RTC EXTI Line event
-  * @{
-  */ 
-#define RTC_EXTI_LINE_ALARM_EVENT   ((uint32_t)EXTI_IMR_MR17)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup RTC_Exported_Types RTC Exported Types
-  * @{
-  */
-/** 
-  * @brief  RTC Time structure definition  
-  */
-typedef struct
-{
-  uint8_t Hours;            /*!< Specifies the RTC Time Hour.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 23 */
-
-  uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-  
-  uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-  
-}RTC_TimeTypeDef; 
-
-/** 
-  * @brief  RTC Alarm structure definition  
-  */
-typedef struct
-{
-  RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
-    
-  uint32_t Alarm;                /*!< Specifies the alarm ID (only 1 alarm ID for STM32F1).
-                                      This parameter can be a value of @ref RTC_Alarms_Definitions */
-}RTC_AlarmTypeDef;
-  
-/** 
-  * @brief  HAL State structures definition  
-  */ 
-typedef enum
-{
-  HAL_RTC_STATE_RESET             = 0x00,  /*!< RTC not yet initialized or disabled */
-  HAL_RTC_STATE_READY             = 0x01,  /*!< RTC initialized and ready for use   */
-  HAL_RTC_STATE_BUSY              = 0x02,  /*!< RTC process is ongoing              */     
-  HAL_RTC_STATE_TIMEOUT           = 0x03,  /*!< RTC timeout state                   */  
-  HAL_RTC_STATE_ERROR             = 0x04   /*!< RTC error state                     */      
-                                                                        
-}HAL_RTCStateTypeDef;
-
-/** 
-  * @brief  RTC Configuration Structure definition  
-  */
-typedef struct
-{
-  uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
-                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFF  or RTC_AUTO_1_SECOND 
-                                 If RTC_AUTO_1_SECOND is selected, AsynchPrediv will be set automatically to get 1sec timebase */
-                               
-  uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC Tamper pin.
-                                 This parameter can be a value of @ref RTC_output_source_to_output_on_the_Tamper_pin */      
-  
-}RTC_InitTypeDef;
-  
-/** 
-  * @brief  RTC Date structure definition  
-  */
-typedef struct
-{
-  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay (not necessary for HAL_RTC_SetDate).
-                         This parameter can be a value of @ref RTC_WeekDay_Definitions */
-  
-  uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
-                         This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
-  uint8_t Date;     /*!< Specifies the RTC Date.
-                         This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-  
-  uint8_t Year;     /*!< Specifies the RTC Date Year.
-                         This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
-                        
-}RTC_DateTypeDef;
-
-/** 
-  * @brief  Time Handle Structure definition  
-  */ 
-typedef struct
-{
-  RTC_TypeDef                 *Instance;  /*!< Register base address    */
-
-  RTC_InitTypeDef             Init;       /*!< RTC required parameters  */ 
-
-  RTC_DateTypeDef             DateToUpdate;       /*!< Current date set by user and updated automatically  */ 
-
-  HAL_LockTypeDef             Lock;       /*!< RTC locking object       */
-
-  __IO HAL_RTCStateTypeDef    State;      /*!< Time communication state */
-
-}RTC_HandleTypeDef;
-
-/**
-  * @}
-  */ 
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Constants RTC Exported Constants
-  * @{
-  */ 
-  
-/** @defgroup RTC_Automatic_Prediv_1_Second Automatic calculation of prediv for 1sec timebase
-  * @{
-  */ 
-#define RTC_AUTO_1_SECOND                      ((uint32_t)0xFFFFFFFF)
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format
-  * @{
-  */ 
-#define RTC_FORMAT_BIN                      ((uint32_t)0x000000000)
-#define RTC_FORMAT_BCD                      ((uint32_t)0x000000001)
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Month_Date_Definitions Month Definitions
-  * @{
-  */ 
-
-/* Coded in BCD format */
-#define RTC_MONTH_JANUARY              ((uint8_t)0x01)
-#define RTC_MONTH_FEBRUARY             ((uint8_t)0x02)
-#define RTC_MONTH_MARCH                ((uint8_t)0x03)
-#define RTC_MONTH_APRIL                ((uint8_t)0x04)
-#define RTC_MONTH_MAY                  ((uint8_t)0x05)
-#define RTC_MONTH_JUNE                 ((uint8_t)0x06)
-#define RTC_MONTH_JULY                 ((uint8_t)0x07)
-#define RTC_MONTH_AUGUST               ((uint8_t)0x08)
-#define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09)
-#define RTC_MONTH_OCTOBER              ((uint8_t)0x10)
-#define RTC_MONTH_NOVEMBER             ((uint8_t)0x11)
-#define RTC_MONTH_DECEMBER             ((uint8_t)0x12)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_WeekDay_Definitions WeekDay Definitions 
-  * @{
-  */ 
-#define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01)
-#define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02)
-#define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03)
-#define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04)
-#define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05)
-#define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06)
-#define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x00)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Alarms_Definitions Alarms Definitions 
-  * @{
-  */ 
-#define RTC_ALARM_A          0                  /*!< Specify alarm ID (mainly for legacy purposes) */
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin Output source to output on the Tamper pin
-  * @{
-  */
-
-#define RTC_OUTPUTSOURCE_NONE               ((uint32_t)0x00000000)            /*!< No output on the TAMPER pin  */
-#define RTC_OUTPUTSOURCE_CALIBCLOCK         BKP_RTCCR_CCO                     /*!< RTC clock with a frequency divided by 64 on the TAMPER pin  */
-#define RTC_OUTPUTSOURCE_ALARM              BKP_RTCCR_ASOE                    /*!< Alarm pulse signal on the TAMPER pin  */
-#define RTC_OUTPUTSOURCE_SECOND             (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Second pulse signal on the TAMPER pin  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Interrupts_Definitions Interrupts Definitions 
-  * @{
-  */ 
-#define RTC_IT_OW            RTC_CRH_OWIE       /*!< Overflow interrupt */
-#define RTC_IT_ALRA          RTC_CRH_ALRIE      /*!< Alarm interrupt */
-#define RTC_IT_SEC           RTC_CRH_SECIE      /*!< Second interrupt */
-#define RTC_IT_TAMP1         BKP_CSR_TPIE       /*!< TAMPER Pin interrupt enable */  
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Flags_Definitions Flags Definitions 
-  * @{
-  */ 
-#define RTC_FLAG_RTOFF       RTC_CRL_RTOFF      /*!< RTC Operation OFF flag */
-#define RTC_FLAG_RSF         RTC_CRL_RSF        /*!< Registers Synchronized flag */
-#define RTC_FLAG_OW          RTC_CRL_OWF        /*!< Overflow flag */
-#define RTC_FLAG_ALRAF       RTC_CRL_ALRF       /*!< Alarm flag */
-#define RTC_FLAG_SEC         RTC_CRL_SECF       /*!< Second flag */
-#define RTC_FLAG_TAMP1F      BKP_CSR_TEF        /*!< Tamper Interrupt Flag */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTC_Exported_macros RTC Exported Macros
-  * @{
-  */
-  
-/** @brief  Reset RTC handle state
-  * @param  __HANDLE__: RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__)              ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
- 
-/**
-  * @brief  Disable the write protection for RTC registers.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)         SET_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)
-
-/**
-  * @brief  Enable the write protection for RTC registers.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)          CLEAR_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)
- 
-/**
-  * @brief  Enable the RTC Alarm interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. 
-  *          This parameter can be any combination of the following values:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  * @retval None
-  */   
-#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)  SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC Alarm interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. 
-  *         This parameter can be any combination of the following values:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be checked
-  *         This parameter can be:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC Alarm's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
-  *          This parameter can be:
-  *            @arg RTC_FLAG_ALRAF
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)        (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->CRL) & (__INTERRUPT__)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Clear the RTC Alarm's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_ALRAF
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
-
-/**
-  * @brief Enable interrupt on ALARM Exti Line 17.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_IT()                  SET_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief Disable interrupt on ALARM Exti Line 17. 
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_IT()                 CLEAR_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief Enable event on ALARM Exti Line 17.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()               SET_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief Disable event on ALARM Exti Line 17.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()              CLEAR_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)
-
-
-/**
-  * @brief  ALARM EXTI line configuration: set falling edge trigger.  
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()        SET_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)
-
-
-/**
-  * @brief Disable the ALARM Extended Interrupt Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()       CLEAR_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)
-
-
-/**
-  * @brief  ALARM EXTI line configuration: set rising edge trigger.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()         SET_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief Disable the ALARM Extended Interrupt Rising Trigger.
-  * This parameter can be:
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()        CLEAR_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  ALARM EXTI line configuration: set rising & falling edge trigger.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
-
-/**
-  * @brief Disable the ALARM Extended Interrupt Rising & Falling Trigger.
-  * This parameter can be:
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()();
-
-/**
-  * @brief Check whether the specified ALARM EXTI interrupt flag is set or not.
-  * @retval EXTI ALARM Line Status.
-  */
-#define __HAL_RTC_ALARM_EXTI_GET_FLAG()                   (EXTI->PR & (RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief Clear the ALARM EXTI flag.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()                 (EXTI->PR = (RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief Generate a Software interrupt on selected EXTI line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()              SET_BIT(EXTI->SWIER, RTC_EXTI_LINE_ALARM_EVENT)
-/**
-  * @}
-  */
-
-/* Include RTC HAL Extension module */
-#include "stm32f1xx_hal_rtc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTC_Exported_Functions
-  * @{
-  */
-
-
-/* Initialization and de-initialization functions  ****************************/
-/** @addtogroup RTC_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
-void              HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
-void              HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-  
-/* RTC Time and Date functions ************************************************/
-/** @addtogroup RTC_Exported_Functions_Group2
-  * @{
-  */
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-/**
-  * @}
-  */
-
-/* RTC Alarm functions ********************************************************/
-/** @addtogroup RTC_Exported_Functions_Group3
-  * @{
-  */
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
-void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-void              HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/* Peripheral State functions *************************************************/
-/** @addtogroup RTC_Exported_Functions_Group4
-  * @{
-  */
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/* Peripheral Control functions ***********************************************/
-/** @addtogroup RTC_Exported_Functions_Group5
-  * @{
-  */
-HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_rtc_ex.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,430 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_rtc_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of RTC HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_RTC_EX_H
-#define __STM32F1xx_HAL_RTC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RTCEx
-  * @{
-  */ 
-
-/** @addtogroup RTCEx_Private_Macros
-  * @{
-  */
-  
-/** @defgroup RTCEx_Alias_For_Legacy Alias define maintained for legacy
-  * @{
-  */ 
-#define HAL_RTCEx_TamperTimeStampIRQHandler HAL_RTCEx_TamperIRQHandler
-
-/**
-  * @}
-  */
-  
-/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
-  * @{
-  */ 
-#define IS_RTC_TAMPER(__TAMPER__) ((__TAMPER__) == RTC_TAMPER_1)
-
-#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__)  (((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
-                                         ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL)) 
-
-#if RTC_BKP_NUMBER > 10
-#define IS_RTC_BKP(BKP)                   (((BKP) <= (uint32_t) RTC_BKP_DR10) || (((BKP) >= (uint32_t) RTC_BKP_DR11) && ((BKP) <= (uint32_t) RTC_BKP_DR42)))
-#else
-#define IS_RTC_BKP(BKP)                   ((BKP) <= (uint32_t) RTC_BKP_NUMBER)
-#endif
-#define IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x0000007F)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
-  * @{
-  */
-/** 
-  * @brief  RTC Tamper structure definition  
-  */
-typedef struct 
-{
-  uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */
-  
-  uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */
-
-}RTC_TamperTypeDef;
-
-/**
-  * @}
-  */ 
-  
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
-  * @{
-  */ 
-  
-/** @defgroup RTCEx_Tamper_Pins_Definitions Tamper Pins Definitions
-  * @{
-  */
-#define RTC_TAMPER_1                        BKP_CR_TPE            /*!< Select tamper to be enabled (mainly for legacy purposes) */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Trigger_Definitions Tamper Trigger Definitions 
-  * @{
-  */ 
-#define RTC_TAMPERTRIGGER_LOWLEVEL          BKP_CR_TPAL           /*!< A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
-#define RTC_TAMPERTRIGGER_HIGHLEVEL        ((uint32_t)0x00000000) /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
-
-/**
-  * @}
-  */  
-
-/** @defgroup RTCEx_Backup_Registers_Definitions Backup Registers Definitions 
-  * @{
-  */
-#if RTC_BKP_NUMBER > 0
-#define RTC_BKP_DR1                       ((uint32_t)0x00000001)
-#define RTC_BKP_DR2                       ((uint32_t)0x00000002)
-#define RTC_BKP_DR3                       ((uint32_t)0x00000003)
-#define RTC_BKP_DR4                       ((uint32_t)0x00000004)
-#define RTC_BKP_DR5                       ((uint32_t)0x00000005)
-#define RTC_BKP_DR6                       ((uint32_t)0x00000006)
-#define RTC_BKP_DR7                       ((uint32_t)0x00000007)
-#define RTC_BKP_DR8                       ((uint32_t)0x00000008)
-#define RTC_BKP_DR9                       ((uint32_t)0x00000009)
-#define RTC_BKP_DR10                      ((uint32_t)0x0000000A)
-#endif /* RTC_BKP_NUMBER > 0 */
-   
-#if RTC_BKP_NUMBER > 10
-#define RTC_BKP_DR11                      ((uint32_t)0x00000010)
-#define RTC_BKP_DR12                      ((uint32_t)0x00000011)
-#define RTC_BKP_DR13                      ((uint32_t)0x00000012)
-#define RTC_BKP_DR14                      ((uint32_t)0x00000013)
-#define RTC_BKP_DR15                      ((uint32_t)0x00000014)
-#define RTC_BKP_DR16                      ((uint32_t)0x00000015)
-#define RTC_BKP_DR17                      ((uint32_t)0x00000016)
-#define RTC_BKP_DR18                      ((uint32_t)0x00000017)
-#define RTC_BKP_DR19                      ((uint32_t)0x00000018)
-#define RTC_BKP_DR20                      ((uint32_t)0x00000019)
-#define RTC_BKP_DR21                      ((uint32_t)0x0000001A)
-#define RTC_BKP_DR22                      ((uint32_t)0x0000001B)
-#define RTC_BKP_DR23                      ((uint32_t)0x0000001C)
-#define RTC_BKP_DR24                      ((uint32_t)0x0000001D)
-#define RTC_BKP_DR25                      ((uint32_t)0x0000001E)
-#define RTC_BKP_DR26                      ((uint32_t)0x0000001F)
-#define RTC_BKP_DR27                      ((uint32_t)0x00000020)
-#define RTC_BKP_DR28                      ((uint32_t)0x00000021)
-#define RTC_BKP_DR29                      ((uint32_t)0x00000022)
-#define RTC_BKP_DR30                      ((uint32_t)0x00000023)
-#define RTC_BKP_DR31                      ((uint32_t)0x00000024)
-#define RTC_BKP_DR32                      ((uint32_t)0x00000025)
-#define RTC_BKP_DR33                      ((uint32_t)0x00000026)
-#define RTC_BKP_DR34                      ((uint32_t)0x00000027)
-#define RTC_BKP_DR35                      ((uint32_t)0x00000028)
-#define RTC_BKP_DR36                      ((uint32_t)0x00000029)
-#define RTC_BKP_DR37                      ((uint32_t)0x0000002A)
-#define RTC_BKP_DR38                      ((uint32_t)0x0000002B)
-#define RTC_BKP_DR39                      ((uint32_t)0x0000002C)
-#define RTC_BKP_DR40                      ((uint32_t)0x0000002D)
-#define RTC_BKP_DR41                      ((uint32_t)0x0000002E)
-#define RTC_BKP_DR42                      ((uint32_t)0x0000002F)
-#endif /* RTC_BKP_NUMBER > 10 */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
-  * @{
-  */
-  
-/**
-  * @brief  Enable the RTC Tamper interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled
-  *          This parameter can be any combination of the following values:
-  *            @arg RTC_IT_TAMP1: Tamper A interrupt
-  * @retval None
-  */   
-#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT(BKP->CSR, (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC Tamper interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled. 
-  *         This parameter can be any combination of the following values:
-  *            @arg RTC_IT_TAMP1: Tamper A interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT(BKP->CSR, (__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP1
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    ((((BKP->CSR) & ((__INTERRUPT__))) != RESET)? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC Tamper's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_TAMP1F      
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)       ((((BKP->CSR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC Tamper's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP1
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)       ((((BKP->CSR) & (BKP_CSR_TEF)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Clear the RTC Tamper's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_TAMP1F  
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)     SET_BIT(BKP->CSR, BKP_CSR_CTE | BKP_CSR_CTI)
-
-/**
-  * @brief  Enable the RTC Second interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled
-  *          This parameter can be any combination of the following values:
-  *            @arg RTC_IT_SEC: Second A interrupt
-  * @retval None
-  */   
-#define __HAL_RTC_SECOND_ENABLE_IT(__HANDLE__, __INTERRUPT__)  SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC Second interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Second interrupt sources to be disabled. 
-  *         This parameter can be any combination of the following values:
-  *            @arg RTC_IT_SEC: Second A interrupt
-  * @retval None
-  */
-#define __HAL_RTC_SECOND_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC Second interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_SEC: Second A interrupt
-  * @retval None
-  */
-#define __HAL_RTC_SECOND_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC Second's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled.
-  *          This parameter can be:
-  *            @arg RTC_FLAG_SEC
-  * @retval None
-  */
-#define __HAL_RTC_SECOND_GET_FLAG(__HANDLE__, __FLAG__)        (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Clear the RTC Second's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_SEC
-  * @retval None
-  */
-#define __HAL_RTC_SECOND_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
-
-/**
-  * @brief  Enable the RTC Overflow interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled
-  *          This parameter can be any combination of the following values:
-  *            @arg RTC_IT_OW: Overflow A interrupt
-  * @retval None
-  */   
-#define __HAL_RTC_OVERFLOW_ENABLE_IT(__HANDLE__, __INTERRUPT__)  SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC Overflow interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Overflow interrupt sources to be disabled. 
-  *         This parameter can be any combination of the following values:
-  *            @arg RTC_IT_OW: Overflow A interrupt
-  * @retval None
-  */
-#define __HAL_RTC_OVERFLOW_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC Overflow interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_OW: Overflow A interrupt
-  * @retval None
-  */
-#define __HAL_RTC_OVERFLOW_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__))) ) != RESET)? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC Overflow's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled.
-  *          This parameter can be:
-  *            @arg RTC_FLAG_OW
-  * @retval None
-  */
-#define __HAL_RTC_OVERFLOW_GET_FLAG(__HANDLE__, __FLAG__)        (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Clear the RTC Overflow's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_OW
-  * @retval None
-  */
-#define __HAL_RTC_OVERFLOW_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
-
-/**
-  * @}
-  */ 
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTCEx_Exported_Functions
-  * @{
-  */
-  
-/* RTC Tamper functions *****************************************/
-/** @addtogroup RTCEx_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
-void              HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-
-/**
-  * @}
-  */
-  
-/* RTC Second functions *****************************************/
-/** @addtogroup RTCEx_Exported_Functions_Group2
-  * @{
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetSecond_IT(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateSecond(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_RTCIRQHandler(RTC_HandleTypeDef* hrtc);
-void              HAL_RTCEx_RTCEventCallback(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_RTCEventErrorCallback(RTC_HandleTypeDef *hrtc);
-
-/**
-  * @}
-  */
-  
-/* Extension Control functions ************************************************/
-/** @addtogroup RTCEx_Exported_Functions_Group3
-  * @{
-  */
-void              HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
-uint32_t          HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
-
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_RTC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_sd.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,709 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_sd.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of SD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_SD_H
-#define __STM32F1xx_HAL_SD_H
-
-#if defined(STM32F103xE) || defined(STM32F103xG)
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_sdmmc.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SD
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup SD_Exported_Types SD Exported Types
-  * @{
-  */
-
-#define SD_InitTypeDef      SDIO_InitTypeDef 
-#define SD_TypeDef          SDIO_TypeDef
-
-/** 
-  * @brief  SDIO Handle Structure definition  
-  */ 
-typedef struct
-{
-  SD_TypeDef                   *Instance;        /*!< SDIO register base address                     */
-  
-  SD_InitTypeDef               Init;             /*!< SD required parameters                         */
-  
-  HAL_LockTypeDef              Lock;             /*!< SD locking object                              */
-  
-  uint32_t                     CardType;         /*!< SD card type                                   */
-  
-  uint32_t                     RCA;              /*!< SD relative card address                       */
-  
-  uint32_t                     CSD[4];           /*!< SD card specific data table                    */
-  
-  uint32_t                     CID[4];           /*!< SD card identification number table            */
-  
-  __IO uint32_t                SdTransferCplt;   /*!< SD transfer complete flag in non blocking mode */
-  
-  __IO uint32_t                SdTransferErr;    /*!< SD transfer error flag in non blocking mode    */
-  
-  __IO uint32_t                DmaTransferCplt;  /*!< SD DMA transfer complete flag                  */
-  
-  __IO uint32_t                SdOperation;      /*!< SD transfer operation (read/write)             */
-  
-  DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters                    */
-  
-  DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters                    */
-  
-}SD_HandleTypeDef;
-
-/** 
-  * @brief  Card Specific Data: CSD Register   
-  */ 
-typedef struct
-{
-  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
-  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
-  __IO uint8_t  Reserved1;            /*!< Reserved                              */
-  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
-  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
-  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
-  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
-  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
-  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
-  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
-  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
-  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
-  __IO uint8_t  Reserved2;            /*!< Reserved                              */
-  __IO uint32_t DeviceSize;           /*!< Device Size                           */
-  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
-  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
-  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
-  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
-  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
-  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
-  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
-  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
-  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
-  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
-  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
-  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
-  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
-  __IO uint8_t  Reserved3;            /*!< Reserved                              */
-  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
-  __IO uint8_t  FileFormatGrouop;     /*!< File format group                     */
-  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
-  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
-  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
-  __IO uint8_t  FileFormat;           /*!< File format                           */
-  __IO uint8_t  ECC;                  /*!< ECC code                              */
-  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
-  __IO uint8_t  Reserved4;            /*!< Always 1                              */
-
-}HAL_SD_CSDTypedef;
-
-/** 
-  * @brief  Card Identification Data: CID Register   
-  */
-typedef struct
-{
-  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
-  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
-  __IO uint32_t ProdName1;       /*!< Product Name part1    */
-  __IO uint8_t  ProdName2;       /*!< Product Name part2    */
-  __IO uint8_t  ProdRev;         /*!< Product Revision      */
-  __IO uint32_t ProdSN;          /*!< Product Serial Number */
-  __IO uint8_t  Reserved1;       /*!< Reserved1             */
-  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
-  __IO uint8_t  CID_CRC;         /*!< CID CRC               */
-  __IO uint8_t  Reserved2;       /*!< Always 1              */
-
-}HAL_SD_CIDTypedef;
-
-/** 
-  * @brief SD Card Status returned by ACMD13  
-  */
-typedef struct
-{
-  __IO uint8_t  DAT_BUS_WIDTH;           /*!< Shows the currently defined data bus width                 */
-  __IO uint8_t  SECURED_MODE;            /*!< Card is in secured mode of operation                       */
-  __IO uint16_t SD_CARD_TYPE;            /*!< Carries information about card type                        */
-  __IO uint32_t SIZE_OF_PROTECTED_AREA;  /*!< Carries information about the capacity of protected area   */
-  __IO uint8_t  SPEED_CLASS;             /*!< Carries information about the speed class of the card      */
-  __IO uint8_t  PERFORMANCE_MOVE;        /*!< Carries information about the card's performance move      */
-  __IO uint8_t  AU_SIZE;                 /*!< Carries information about the card's allocation unit size  */
-  __IO uint16_t ERASE_SIZE;              /*!< Determines the number of AUs to be erased in one operation */
-  __IO uint8_t  ERASE_TIMEOUT;           /*!< Determines the timeout for any number of AU erase          */
-  __IO uint8_t  ERASE_OFFSET;            /*!< Carries information about the erase offset                 */
-
-}HAL_SD_CardStatusTypedef;
-
-/** 
-  * @brief SD Card information structure 
-  */
-typedef struct
-{
-  HAL_SD_CSDTypedef   SD_csd;         /*!< SD card specific data register         */
-  HAL_SD_CIDTypedef   SD_cid;         /*!< SD card identification number register */
-  uint64_t            CardCapacity;   /*!< Card capacity                          */
-  uint32_t            CardBlockSize;  /*!< Card block size                        */
-  uint16_t            RCA;            /*!< SD relative card address               */
-  uint8_t             CardType;       /*!< SD card type                           */
-
-}HAL_SD_CardInfoTypedef;
-
-/** 
-  * @brief  SD Error status enumeration Structure definition  
-  */
-typedef enum
-{
-/** 
-  * @brief  SD specific error defines  
-  */   
-  SD_CMD_CRC_FAIL                    = (1),   /*!< Command response received (but CRC check failed)              */
-  SD_DATA_CRC_FAIL                   = (2),   /*!< Data block sent/received (CRC check failed)                   */
-  SD_CMD_RSP_TIMEOUT                 = (3),   /*!< Command response timeout                                      */
-  SD_DATA_TIMEOUT                    = (4),   /*!< Data timeout                                                  */
-  SD_TX_UNDERRUN                     = (5),   /*!< Transmit FIFO underrun                                        */
-  SD_RX_OVERRUN                      = (6),   /*!< Receive FIFO overrun                                          */
-  SD_START_BIT_ERR                   = (7),   /*!< Start bit not detected on all data signals in wide bus mode   */
-  SD_CMD_OUT_OF_RANGE                = (8),   /*!< Command's argument was out of range.                          */
-  SD_ADDR_MISALIGNED                 = (9),   /*!< Misaligned address                                            */
-  SD_BLOCK_LEN_ERR                   = (10),  /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
-  SD_ERASE_SEQ_ERR                   = (11),  /*!< An error in the sequence of erase command occurs.            */
-  SD_BAD_ERASE_PARAM                 = (12),  /*!< An invalid selection for erase groups                        */
-  SD_WRITE_PROT_VIOLATION            = (13),  /*!< Attempt to program a write protect block                     */
-  SD_LOCK_UNLOCK_FAILED              = (14),  /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
-  SD_COM_CRC_FAILED                  = (15),  /*!< CRC check of the previous command failed                     */
-  SD_ILLEGAL_CMD                     = (16),  /*!< Command is not legal for the card state                      */
-  SD_CARD_ECC_FAILED                 = (17),  /*!< Card internal ECC was applied but failed to correct the data */
-  SD_CC_ERROR                        = (18),  /*!< Internal card controller error                               */
-  SD_GENERAL_UNKNOWN_ERROR           = (19),  /*!< General or unknown error                                     */
-  SD_STREAM_READ_UNDERRUN            = (20),  /*!< The card could not sustain data transfer in stream read operation. */
-  SD_STREAM_WRITE_OVERRUN            = (21),  /*!< The card could not sustain data programming in stream mode   */
-  SD_CID_CSD_OVERWRITE               = (22),  /*!< CID/CSD overwrite error                                      */
-  SD_WP_ERASE_SKIP                   = (23),  /*!< Only partial address space was erased                        */
-  SD_CARD_ECC_DISABLED               = (24),  /*!< Command has been executed without using internal ECC         */
-  SD_ERASE_RESET                     = (25),  /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
-  SD_AKE_SEQ_ERROR                   = (26),  /*!< Error in sequence of authentication.                         */
-  SD_INVALID_VOLTRANGE               = (27),
-  SD_ADDR_OUT_OF_RANGE               = (28),
-  SD_SWITCH_ERROR                    = (29),
-  SD_SDIO_DISABLED                   = (30),
-  SD_SDIO_FUNCTION_BUSY              = (31),
-  SD_SDIO_FUNCTION_FAILED            = (32),
-  SD_SDIO_UNKNOWN_FUNCTION           = (33),
-
-/** 
-  * @brief  Standard error defines   
-  */ 
-  SD_INTERNAL_ERROR                  = (34),
-  SD_NOT_CONFIGURED                  = (35),
-  SD_REQUEST_PENDING                 = (36),
-  SD_REQUEST_NOT_APPLICABLE          = (37),
-  SD_INVALID_PARAMETER               = (38),
-  SD_UNSUPPORTED_FEATURE             = (39),
-  SD_UNSUPPORTED_HW                  = (40),
-  SD_ERROR                           = (41),
-  SD_OK                              = (0) 
-
-}HAL_SD_ErrorTypedef;
-
-/** 
-  * @brief  SD Transfer state enumeration structure
-  */   
-typedef enum
-{
-  SD_TRANSFER_OK    = 0,  /*!< Transfer success      */
-  SD_TRANSFER_BUSY  = 1,  /*!< Transfer is occurring */
-  SD_TRANSFER_ERROR = 2   /*!< Transfer failed       */
-
-}HAL_SD_TransferStateTypedef;
-
-/** 
-  * @brief  SD Card State enumeration structure 
-  */   
-typedef enum
-{
-  SD_CARD_READY                  = ((uint32_t)0x00000001),  /*!< Card state is ready                     */
-  SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002),  /*!< Card is in identification state         */
-  SD_CARD_STANDBY                = ((uint32_t)0x00000003),  /*!< Card is in standby state                */
-  SD_CARD_TRANSFER               = ((uint32_t)0x00000004),  /*!< Card is in transfer state               */  
-  SD_CARD_SENDING                = ((uint32_t)0x00000005),  /*!< Card is sending an operation            */
-  SD_CARD_RECEIVING              = ((uint32_t)0x00000006),  /*!< Card is receiving operation information */
-  SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007),  /*!< Card is in programming state            */
-  SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008),  /*!< Card is disconnected                    */
-  SD_CARD_ERROR                  = ((uint32_t)0x000000FF)   /*!< Card is in error state                  */
-
-}HAL_SD_CardStateTypedef;
-
-/** 
-  * @brief  SD Operation enumeration structure   
-  */   
-typedef enum
-{
-  SD_READ_SINGLE_BLOCK    = 0,  /*!< Read single block operation      */
-  SD_READ_MULTIPLE_BLOCK  = 1,  /*!< Read multiple blocks operation   */
-  SD_WRITE_SINGLE_BLOCK   = 2,  /*!< Write single block operation     */
-  SD_WRITE_MULTIPLE_BLOCK = 3   /*!< Write multiple blocks operation  */
-
-}HAL_SD_OperationTypedef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SD_Exported_Constants SD Exported Constants
-  * @{
-  */
-
-/** 
-  * @brief SD Commands Index 
-  */
-#define SD_CMD_GO_IDLE_STATE                       ((uint8_t)0)   /*!< Resets the SD memory card.                                                               */
-#define SD_CMD_SEND_OP_COND                        ((uint8_t)1)   /*!< Sends host capacity support information and activates the card's initialization process. */
-#define SD_CMD_ALL_SEND_CID                        ((uint8_t)2)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
-#define SD_CMD_SET_REL_ADDR                        ((uint8_t)3)   /*!< Asks the card to publish a new relative address (RCA).                                   */
-#define SD_CMD_SET_DSR                             ((uint8_t)4)   /*!< Programs the DSR of all cards.                                                           */
-#define SD_CMD_SDIO_SEN_OP_COND                    ((uint8_t)5)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its 
-                                                                       operating condition register (OCR) content in the response on the CMD line.              */
-#define SD_CMD_HS_SWITCH                           ((uint8_t)6)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
-#define SD_CMD_SEL_DESEL_CARD                      ((uint8_t)7)   /*!< Selects the card by its own relative address and gets deselected by any other address    */
-#define SD_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information 
-                                                                       and asks the card whether card supports voltage.                                         */
-#define SD_CMD_SEND_CSD                            ((uint8_t)9)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
-#define SD_CMD_SEND_CID                            ((uint8_t)10)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
-#define SD_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11)  /*!< SD card doesn't support it.                                                              */
-#define SD_CMD_STOP_TRANSMISSION                   ((uint8_t)12)  /*!< Forces the card to stop transmission.                                                    */
-#define SD_CMD_SEND_STATUS                         ((uint8_t)13)  /*!< Addressed card sends its status register.                                                */
-#define SD_CMD_HS_BUSTEST_READ                     ((uint8_t)14) 
-#define SD_CMD_GO_INACTIVE_STATE                   ((uint8_t)15)  /*!< Sends an addressed card into the inactive state.                                         */
-#define SD_CMD_SET_BLOCKLEN                        ((uint8_t)16)  /*!< Sets the block length (in bytes for SDSC) for all following block commands 
-                                                                       (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 
-                                                                       for SDHS and SDXC.                                                                       */
-#define SD_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 
-                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */
-#define SD_CMD_READ_MULT_BLOCK                     ((uint8_t)18)  /*!< Continuously transfers data blocks from card to host until interrupted by 
-                                                                       STOP_TRANSMISSION command.                                                               */
-#define SD_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
-#define SD_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20)  /*!< Speed class control command.                                                             */
-#define SD_CMD_SET_BLOCK_COUNT                     ((uint8_t)23)  /*!< Specify block count for CMD18 and CMD25.                                                 */
-#define SD_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 
-                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */
-#define SD_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
-#define SD_CMD_PROG_CID                            ((uint8_t)26)  /*!< Reserved for manufacturers.                                                              */
-#define SD_CMD_PROG_CSD                            ((uint8_t)27)  /*!< Programming of the programmable bits of the CSD.                                         */
-#define SD_CMD_SET_WRITE_PROT                      ((uint8_t)28)  /*!< Sets the write protection bit of the addressed group.                                    */
-#define SD_CMD_CLR_WRITE_PROT                      ((uint8_t)29)  /*!< Clears the write protection bit of the addressed group.                                  */
-#define SD_CMD_SEND_WRITE_PROT                     ((uint8_t)30)  /*!< Asks the card to send the status of the write protection bits.                           */
-#define SD_CMD_SD_ERASE_GRP_START                  ((uint8_t)32)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */
-#define SD_CMD_SD_ERASE_GRP_END                    ((uint8_t)33)  /*!< Sets the address of the last write block of the continuous range to be erased.           */
-#define SD_CMD_ERASE_GRP_START                     ((uint8_t)35)  /*!< Sets the address of the first write block to be erased. Reserved for each command 
-                                                                       system set by switch function command (CMD6).                                            */
-#define SD_CMD_ERASE_GRP_END                       ((uint8_t)36)  /*!< Sets the address of the last write block of the continuous range to be erased. 
-                                                                       Reserved for each command system set by switch function command (CMD6).                  */
-#define SD_CMD_ERASE                               ((uint8_t)38)  /*!< Reserved for SD security applications.                                                   */
-#define SD_CMD_FAST_IO                             ((uint8_t)39)  /*!< SD card doesn't support it (Reserved).                                                   */
-#define SD_CMD_GO_IRQ_STATE                        ((uint8_t)40)  /*!< SD card doesn't support it (Reserved).                                                   */
-#define SD_CMD_LOCK_UNLOCK                         ((uint8_t)42)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by 
-                                                                       the SET_BLOCK_LEN command.                                                               */
-#define SD_CMD_APP_CMD                             ((uint8_t)55)  /*!< Indicates to the card that the next command is an application specific command rather 
-                                                                       than a standard command.                                                                 */
-#define SD_CMD_GEN_CMD                             ((uint8_t)56)  /*!< Used either to transfer a data block to the card or to get a data block from the card 
-                                                                       for general purpose/application specific commands.                                       */
-#define SD_CMD_NO_CMD                              ((uint8_t)64) 
-
-/** 
-  * @brief Following commands are SD Card Specific commands.
-  *        SDIO_APP_CMD should be sent before sending these commands. 
-  */
-#define SD_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus 
-                                                                       widths are given in SCR register.                                                          */
-#define SD_CMD_SD_APP_STATUS                        ((uint8_t)13)  /*!< (ACMD13) Sends the SD status.                                                              */
-#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 
-                                                                       32bit+CRC data block.                                                                      */
-#define SD_CMD_SD_APP_OP_COND                      ((uint8_t)41)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to 
-                                                                       send its operating condition register (OCR) content in the response on the CMD line.       */
-#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42)  /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
-#define SD_CMD_SD_APP_SEND_SCR                     ((uint8_t)51)  /*!< Reads the SD Configuration Register (SCR).                                                 */
-#define SD_CMD_SDIO_RW_DIRECT                      ((uint8_t)52)  /*!< For SD I/O card only, reserved for security specification.                                 */
-#define SD_CMD_SDIO_RW_EXTENDED                    ((uint8_t)53)  /*!< For SD I/O card only, reserved for security specification.                                 */
-
-/** 
-  * @brief Following commands are SD Card Specific security commands.
-  *        SD_CMD_APP_CMD should be sent before sending these commands. 
-  */
-#define SD_CMD_SD_APP_GET_MKB                      ((uint8_t)43)  /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_MID                      ((uint8_t)44)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45)  /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47)  /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38)  /*!< For SD card only */
-#define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48)  /*!< For SD card only */
-
-/** 
-  * @brief Supported SD Memory Cards 
-  */
-#define STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000)
-#define STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001)
-#define HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002)
-#define MULTIMEDIA_CARD                       ((uint32_t)0x00000003)
-#define SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004)
-#define HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005)
-#define SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006)
-#define HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007)
-/**
-  * @}
-  */
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SD_Exported_macros SD Exported Macros
-  * @brief macros to handle interrupts and specific clock configurations
-  * @{
-  */
- 
-/**
-  * @brief  Enable the SD device.
-  * @param  __HANDLE__: SD Handle  
-  * @retval None
-  */ 
-#define __HAL_SD_SDIO_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
-
-/**
-  * @brief  Disable the SD device.
-  * @param  __HANDLE__: SD Handle  
-  * @retval None
-  */
-#define __HAL_SD_SDIO_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
-
-/**
-  * @brief  Enable the SDIO DMA transfer.
-  * @param  __HANDLE__: SD Handle  
-  * @retval None
-  */ 
-#define __HAL_SD_SDIO_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
-
-/**
-  * @brief  Disable the SDIO DMA transfer.
-  * @param  __HANDLE__: SD Handle  
-  * @retval None
-  */
-#define __HAL_SD_SDIO_DMA_DISABLE(__HANDLE__)  __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
- 
-/**
-  * @brief  Enable the SD device interrupt.
-  * @param  __HANDLE__: SD Handle  
-  * @param  __INTERRUPT__: specifies the SDIO interrupt sources to be enabled.
-  *         This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
-  * @retval None
-  */
-#define __HAL_SD_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
-  * @brief  Disable the SD device interrupt.
-  * @param  __HANDLE__: SD Handle   
-  * @param  __INTERRUPT__: specifies the SDIO interrupt sources to be disabled.
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
-  * @retval None
-  */
-#define __HAL_SD_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified SD flag is set or not. 
-  * @param  __HANDLE__: SD Handle   
-  * @param  __FLAG__: specifies the flag to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
-  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
-  *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
-  *            @arg SDIO_FLAG_RXACT:    Data receive in progress
-  *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
-  *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
-  *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
-  *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
-  *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
-  *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
-  *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
-  *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
-  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
-  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
-  * @retval The new state of SD FLAG (SET or RESET).
-  */
-#define __HAL_SD_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
-  * @brief  Clear the SD's pending flags.
-  * @param  __HANDLE__: SD Handle  
-  * @param  __FLAG__: specifies the flag to clear.  
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
-  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
-  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
-  * @retval None
-  */
-#define __HAL_SD_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
-  * @brief  Check whether the specified SD interrupt has occurred or not.
-  * @param  __HANDLE__: SD Handle   
-  * @param  __INTERRUPT__: specifies the SDIO interrupt source to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
-  * @retval The new state of SD IT (SET or RESET).
-  */
-#define __HAL_SD_SDIO_GET_IT  (__HANDLE__, __INTERRUPT__) __SDIO_GET_IT  ((__HANDLE__)->Instance, __INTERRUPT__)
-
-/**
-  * @brief  Clear the SD's interrupt pending bits.
-  * @param  __HANDLE__ : SD Handle
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIO_DCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
-  * @retval None
-  */
-#define __HAL_SD_SDIO_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-/**
-  * @}
-  */
-  
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SD_Exported_Functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  **********************************/
-/** @addtogroup SD_Exported_Functions_Group1
-  * @{
-  */
-HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
-HAL_StatusTypeDef   HAL_SD_DeInit (SD_HandleTypeDef *hsd);
-void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
-void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
-/**
-  * @}
-  */
-
-/* I/O operation functions  *****************************************************/
-/** @addtogroup SD_Exported_Functions_Group2
-  * @{
-  */
-/* Blocking mode: Polling */
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t Startaddr, uint64_t Endaddr);
-
-/* Non-Blocking mode: Interrupt */
-void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
-
-/* Callback in non blocking modes (DMA) */
-void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
-
-/* Non-Blocking mode: DMA */
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
-HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
-/**
-  * @}
-  */
-  
-/* Peripheral Control functions  ************************************************/
-/** @addtogroup SD_Exported_Functions_Group3
-  * @{
-  */
-HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
-HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
-HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
-HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
-/**
-  * @}
-  */
-  
-/* Peripheral State functions  **************************************************/
-/** @addtogroup SD_Exported_Functions_Group4
-  * @{
-  */
-HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
-HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
-HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F103xE || STM32F103xG */
-
-#endif /* __STM32F1xx_HAL_SD_H */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_smartcard.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,671 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_smartcard.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of SMARTCARD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_SMARTCARD_H
-#define __STM32F1xx_HAL_SMARTCARD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SMARTCARD
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
-  * @{
-  */ 
-
-
-/** 
-  * @brief SMARTCARD Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This member configures the SmartCard communication baud rate.
-                                           The baud rate is computed using the following formula:
-                                           - IntegerDivider = ((PCLKx) / (16 * (hsmartcard->Init.BaudRate)))
-                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref SMARTCARD_Word_Length */
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref SMARTCARD_Stop_Bits */
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref SMARTCARD_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits).*/
-
-  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref SMARTCARD_Mode */
-
-  uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
-                                           This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
-
-  uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
-                                           This parameter can be a value of @ref SMARTCARD_Clock_Phase */
-
-  uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
-                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
-                                           This parameter can be a value of @ref SMARTCARD_Last_Bit */
-
-  uint32_t Prescaler;                 /*!< Specifies the SmartCard Prescaler value used for dividing the system clock 
-                                           to provide the smartcard clock. The value given in the register (5 significant bits)
-                                           is multiplied by 2 to give the division factor of the source clock frequency.
-                                           This parameter can be a value of @ref SMARTCARD_Prescaler */
-
-  uint32_t GuardTime;                 /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
-
-  uint32_t NACKState;                 /*!< Specifies the SmartCard NACK Transmission state
-                                           This parameter can be a value of @ref SMARTCARD_NACK_State */
-}SMARTCARD_InitTypeDef;
-
-/** 
-  * @brief HAL State structures definition
-  */
-typedef enum
-{
-  HAL_SMARTCARD_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized */
-  HAL_SMARTCARD_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
-  HAL_SMARTCARD_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing */
-  HAL_SMARTCARD_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing */
-  HAL_SMARTCARD_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing */
-  HAL_SMARTCARD_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */ 
-  HAL_SMARTCARD_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
-  HAL_SMARTCARD_STATE_ERROR             = 0x04     /*!< Error */
-}HAL_SMARTCARD_StateTypeDef;
-
-
-/** 
-  * @brief  SMARTCARD handle Structure definition
-  */
-typedef struct
-{
-  USART_TypeDef                    *Instance;        /*!< USART registers base address */
-
-  SMARTCARD_InitTypeDef            Init;             /*!< SmartCard communication parameters */
-
-  uint8_t                          *pTxBuffPtr;      /*!< Pointer to SmartCard Tx transfer Buffer */
-
-  uint16_t                         TxXferSize;       /*!< SmartCard Tx Transfer size */
-
-  uint16_t                         TxXferCount;      /*!< SmartCard Tx Transfer Counter */
-
-  uint8_t                          *pRxBuffPtr;      /*!< Pointer to SmartCard Rx transfer Buffer */
-
-  uint16_t                         RxXferSize;       /*!< SmartCard Rx Transfer size */
-
-  uint16_t                         RxXferCount;      /*!< SmartCard Rx Transfer Counter */
-
-  DMA_HandleTypeDef                *hdmatx;          /*!< SmartCard Tx DMA Handle parameters */
-
-  DMA_HandleTypeDef                *hdmarx;          /*!< SmartCard Rx DMA Handle parameters */
-
-  HAL_LockTypeDef                  Lock;             /*!< Locking object */
-
-  __IO HAL_SMARTCARD_StateTypeDef  State;            /*!< SmartCard communication state */
-
-  __IO uint32_t  ErrorCode;        /*!< SmartCard Error code */
-}SMARTCARD_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported constants
-  * @{
-  */
-
-/** @defgroup SMARTCARD_Error_Codes SMARTCARD Error Codes
-  * @{
-  */
-#define HAL_SMARTCARD_ERROR_NONE      ((uint32_t)0x00)    /*!< No error            */
-#define HAL_SMARTCARD_ERROR_PE        ((uint32_t)0x01)    /*!< Parity error        */
-#define HAL_SMARTCARD_ERROR_NE        ((uint32_t)0x02)    /*!< Noise error         */
-#define HAL_SMARTCARD_ERROR_FE        ((uint32_t)0x04)    /*!< frame error         */
-#define HAL_SMARTCARD_ERROR_ORE       ((uint32_t)0x08)    /*!< Overrun error       */
-#define HAL_SMARTCARD_ERROR_DMA       ((uint32_t)0x10)     /*!< DMA transfer error  */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
-  * @{
-  */
-#define SMARTCARD_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
-
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
-  * @{
-  */
-#define SMARTCARD_STOPBITS_0_5                   ((uint32_t)USART_CR2_STOP_0)
-#define SMARTCARD_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Parity SMARTCARD Parity
-  * @{
-  */
-#define SMARTCARD_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
-#define SMARTCARD_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Mode SMARTCARD Mode
-  * @{
-  */
-#define SMARTCARD_MODE_RX                        ((uint32_t)USART_CR1_RE)
-#define SMARTCARD_MODE_TX                        ((uint32_t)USART_CR1_TE)
-#define SMARTCARD_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Clock_Polarity  SMARTCARD Clock Polarity
-  * @{
-  */
-#define SMARTCARD_POLARITY_LOW                   ((uint32_t)0x00000000)
-#define SMARTCARD_POLARITY_HIGH                  ((uint32_t)USART_CR2_CPOL)
-/**
-  * @}
-  */ 
-
-/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
-  * @{
-  */
-#define SMARTCARD_PHASE_1EDGE                    ((uint32_t)0x00000000)
-#define SMARTCARD_PHASE_2EDGE                    ((uint32_t)USART_CR2_CPHA)
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Last_Bit  SMARTCARD Last Bit
-  * @{
-  */
-#define SMARTCARD_LASTBIT_DISABLE                ((uint32_t)0x00000000)
-#define SMARTCARD_LASTBIT_ENABLE                 ((uint32_t)USART_CR2_LBCL)
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_NACK_State   SMARTCARD NACK State
-  * @{
-  */
-#define SMARTCARD_NACK_ENABLE                    ((uint32_t)USART_CR3_NACK)
-#define SMARTCARD_NACK_DISABLE                   ((uint32_t)0x00000000)
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests
-  * @{
-  */
-
-#define SMARTCARD_DMAREQ_TX                      ((uint32_t)USART_CR3_DMAT)
-#define SMARTCARD_DMAREQ_RX                      ((uint32_t)USART_CR3_DMAR)
-
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
-  * @{
-  */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV2         ((uint32_t)0x00000001)          /*!< SYSCLK divided by 2 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV4         ((uint32_t)0x00000002)          /*!< SYSCLK divided by 4 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV6         ((uint32_t)0x00000003)          /*!< SYSCLK divided by 6 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV8         ((uint32_t)0x00000004)          /*!< SYSCLK divided by 8 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV10        ((uint32_t)0x00000005)          /*!< SYSCLK divided by 10 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV12        ((uint32_t)0x00000006)          /*!< SYSCLK divided by 12 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV14        ((uint32_t)0x00000007)          /*!< SYSCLK divided by 14 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV16        ((uint32_t)0x00000008)          /*!< SYSCLK divided by 16 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV18        ((uint32_t)0x00000009)          /*!< SYSCLK divided by 18 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV20        ((uint32_t)0x0000000A)          /*!< SYSCLK divided by 20 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV22        ((uint32_t)0x0000000B)          /*!< SYSCLK divided by 22 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV24        ((uint32_t)0x0000000C)          /*!< SYSCLK divided by 24 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV26        ((uint32_t)0x0000000D)          /*!< SYSCLK divided by 26 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV28        ((uint32_t)0x0000000E)          /*!< SYSCLK divided by 28 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV30        ((uint32_t)0x0000000F)          /*!< SYSCLK divided by 30 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV32        ((uint32_t)0x00000010)          /*!< SYSCLK divided by 32 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV34        ((uint32_t)0x00000011)          /*!< SYSCLK divided by 34 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV36        ((uint32_t)0x00000012)          /*!< SYSCLK divided by 36 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV38        ((uint32_t)0x00000013)          /*!< SYSCLK divided by 38 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV40        ((uint32_t)0x00000014)          /*!< SYSCLK divided by 40 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV42        ((uint32_t)0x00000015)          /*!< SYSCLK divided by 42 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV44        ((uint32_t)0x00000016)          /*!< SYSCLK divided by 44 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV46        ((uint32_t)0x00000017)          /*!< SYSCLK divided by 46 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV48        ((uint32_t)0x00000018)          /*!< SYSCLK divided by 48 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV50        ((uint32_t)0x00000019)          /*!< SYSCLK divided by 50 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV52        ((uint32_t)0x0000001A)          /*!< SYSCLK divided by 52 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV54        ((uint32_t)0x0000001B)          /*!< SYSCLK divided by 54 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV56        ((uint32_t)0x0000001C)          /*!< SYSCLK divided by 56 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV58        ((uint32_t)0x0000001D)          /*!< SYSCLK divided by 58 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV60        ((uint32_t)0x0000001E)          /*!< SYSCLK divided by 60 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV62        ((uint32_t)0x0000001F)          /*!< SYSCLK divided by 62 */
-/**
-  * @}
-  */
-
-
-
-/** @defgroup SMARTCARD_Flags    SMARTCARD Flags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the SR register
-  * @{
-  */
-
-#define SMARTCARD_FLAG_TXE                      ((uint32_t)USART_SR_TXE)
-#define SMARTCARD_FLAG_TC                       ((uint32_t)USART_SR_TC)
-#define SMARTCARD_FLAG_RXNE                     ((uint32_t)USART_SR_RXNE)
-#define SMARTCARD_FLAG_IDLE                     ((uint32_t)USART_SR_IDLE)
-#define SMARTCARD_FLAG_ORE                      ((uint32_t)USART_SR_ORE)
-#define SMARTCARD_FLAG_NE                       ((uint32_t)USART_SR_NE)
-#define SMARTCARD_FLAG_FE                       ((uint32_t)USART_SR_FE)
-#define SMARTCARD_FLAG_PE                       ((uint32_t)USART_SR_PE)
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Interrupt_definition     SMARTCARD Interrupts Definition
-  *        Elements values convention: 0xY000XXXX
-  *           - XXXX  : Interrupt mask (16 bits) in the Y register
-  *           - Y  : Interrupt source register (4 bits)
-  *                 - 0001: CR1 register
-  *                 - 0010: CR3 register
-
-  *
-  * @{
-  */
-
-#define SMARTCARD_IT_PE                         ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
-#define SMARTCARD_IT_TXE                        ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
-#define SMARTCARD_IT_TC                         ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
-#define SMARTCARD_IT_RXNE                       ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
-#define SMARTCARD_IT_IDLE                       ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
-#define SMARTCARD_IT_ERR                        ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28 | USART_CR3_EIE))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-    
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
-  * @{
-  */
-
-
-/** @brief Reset SMARTCARD handle state
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
-
-/** @brief  Flush the Smartcard DR register 
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-    
-/** @brief  Check whether the specified Smartcard flag is set or not.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg SMARTCARD_FLAG_TXE:  Transmit data register empty flag
-  *            @arg SMARTCARD_FLAG_TC:   Transmission Complete flag
-  *            @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
-  *            @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag
-  *            @arg SMARTCARD_FLAG_ORE:  OverRun Error flag
-  *            @arg SMARTCARD_FLAG_NE:   Noise Error flag
-  *            @arg SMARTCARD_FLAG_FE:   Framing Error flag
-  *            @arg SMARTCARD_FLAG_PE:   Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the specified Smartcard pending flags.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be any combination of the following values:
-  *            @arg SMARTCARD_FLAG_TC:   Transmission Complete flag.
-  *            @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
-  * @retval None
-  *   
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error) and ORE (OverRun 
-  *          error) flags are cleared by software sequence: a read operation to 
-  *          USART_SR register followed by a read operation to USART_DR register.
-  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to 
-  *          USART_SR register followed by a write operation to USART_DR register.
-  * @note   TXE flag is cleared only by a write to the USART_DR register.
-  *   
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief  Clear the SMARTCARD PE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \
-do{                                                        \
-    __IO uint32_t tmpreg;                                  \
-    tmpreg = (__HANDLE__)->Instance->SR;                   \
-    tmpreg = (__HANDLE__)->Instance->DR;                   \
-    UNUSED(tmpreg);                                        \
-}while(0)  
-
-
-
-/** @brief  Clear the SMARTCARD FE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the SMARTCARD NE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the SMARTCARD ORE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the SMARTCARD IDLE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Enable the specified SmartCard interrupt.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
-  *          This parameter can be one of the following values:
-  *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt
-  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
-  *            @arg SMARTCARD_IT_PE:   Parity Error interrupt
-  *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
-                                                               ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
-
-/** @brief  Disable the specified SmartCard interrupts.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to disable.
-  *          This parameter can be one of the following values:
-  *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt
-  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
-  *            @arg SMARTCARD_IT_PE:   Parity Error interrupt
-  *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  */
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
-                                                               ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
-
-/** @brief  Check whether the specified SmartCard interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __IT__: specifies the SMARTCARD interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
-  *            @arg SMARTCARD_IT_TC:  Transmission complete interrupt
-  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
-  *            @arg SMARTCARD_IT_ERR: Error interrupt
-  *            @arg SMARTCARD_IT_PE: Parity Error interrupt
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
-
-/** @brief  Enable the USART associated to the SMARTCARD Handle
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */ 
-#define __HAL_SMARTCARD_ENABLE(__HANDLE__)               (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
-
-/** @brief  Disable the USART associated to the SMARTCARD Handle
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */ 
-#define __HAL_SMARTCARD_DISABLE(__HANDLE__)              (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
-
-/** @brief  Enable the SmartCard DMA request.
-  * @param  __HANDLE__: specifies the SmartCard Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __REQUEST__: specifies the SmartCard DMA request.
-  *         This parameter can be one of the following values:
-  *            @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
-  *            @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
-  * @retval None
-  */
-#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__)    (SET_BIT((__HANDLE__)->Instance->CR3, (__REQUEST__)))
-
-/** @brief  Disable the SmartCard DMA request.
-  * @param  __HANDLE__: specifies the SmartCard Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __REQUEST__: specifies the SmartCard DMA request.
-  *         This parameter can be one of the following values:
-  *            @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
-  *            @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
-  * @retval None
-  */
-#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__)   (CLEAR_BIT((__HANDLE__)->Instance->CR3, (__REQUEST__)))
-
-
-/**
-  * @}
-  */
-
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Macros   SMARTCARD Private Macros
-  * @{
-  */
-
-#define SMARTCARD_CR1_REG_INDEX                 1    
-#define SMARTCARD_CR3_REG_INDEX                 3    
-
-#define SMARTCARD_DIV(__PCLK__, __BAUD__)                (((__PCLK__)*25)/(4*(__BAUD__)))
-#define SMARTCARD_DIVMANT(__PCLK__, __BAUD__)            (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100)
-#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__)            (((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100)
-/* UART BRR = mantissa + overflow + fraction
-            = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0F) */
-#define SMARTCARD_BRR(_PCLK_, _BAUD_)            (((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4) + \
-                                                  (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0)) + \
-                                                  (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
-
-/** Check the Baud rate range.
-  *         The maximum Baud Rate is derived from the maximum clock on APB (i.e. 72 MHz) 
-  *         divided by the smallest oversampling used on the USART (i.e. 16) 
-  *         __BAUDRATE__: Baud rate set by the configuration function.
-  * Return : TRUE or FALSE
-  */ 
-#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
-
-#define IS_SMARTCARD_WORD_LENGTH(LENGTH)    ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
-
-#define IS_SMARTCARD_STOPBITS(STOPBITS)     (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
-                                             ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
-
-#define IS_SMARTCARD_PARITY(PARITY)         (((PARITY) == SMARTCARD_PARITY_EVEN) || \
-                                             ((PARITY) == SMARTCARD_PARITY_ODD))
-
-#define IS_SMARTCARD_MODE(MODE)             ((((MODE) & (~((uint32_t)SMARTCARD_MODE_TX_RX))) == 0x00) && \
-                                             ((MODE) != (uint32_t)0x00000000))
-
-#define IS_SMARTCARD_POLARITY(CPOL)         (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
-
-#define IS_SMARTCARD_PHASE(CPHA)            (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
-
-#define IS_SMARTCARD_LASTBIT(LASTBIT)       (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
-                                             ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
-
-#define IS_SMARTCARD_NACK_STATE(NACK)       (((NACK) == SMARTCARD_NACK_ENABLE) || \
-                                             ((NACK) == SMARTCARD_NACK_DISABLE))
-
-#define IS_SMARTCARD_PRESCALER(PRESCALER)   (((PRESCALER) >= SMARTCARD_PRESCALER_SYSCLK_DIV2) && \
-                                             ((PRESCALER) <= SMARTCARD_PRESCALER_SYSCLK_DIV62) )
-
-/** SMARTCARD interruptions flag mask
-  * 
-  */ 
-#define SMARTCARD_IT_MASK   ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
-                                        USART_CR1_IDLEIE | USART_CR3_EIE )
-
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
-  * @{
-  */
-  
-/** @addtogroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @{
-  */
-
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
-
-/**
-  * @}
-  */
-
-/** @addtogroup SMARTCARD_Exported_Functions_Group2 IO operation functions 
-  * @{
-  */
-
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
-
-/**
-  * @}
-  */
-
-/** @addtogroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions 
-  * @{
-  */
-
-/* Peripheral State and Errors functions functions  *****************************/
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
-uint32_t                   HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_SMARTCARD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_spi.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,674 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_spi.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of SPI HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_SPI_H
-#define __STM32F1xx_HAL_SPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"  
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SPI
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SPI_Exported_Types SPI Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  SPI Configuration Structure definition  
-  */
-typedef struct
-{
-  uint32_t Mode;               /*!< Specifies the SPI operating mode.
-                                    This parameter can be a value of @ref SPI_mode */
-
-  uint32_t Direction;          /*!< Specifies the SPI Directional mode state.
-                                    This parameter can be a value of @ref SPI_Direction_mode */
-
-  uint32_t DataSize;           /*!< Specifies the SPI data size.
-                                    This parameter can be a value of @ref SPI_data_size */
-
-  uint32_t CLKPolarity;        /*!< Specifies the serial clock steady state.
-                                    This parameter can be a value of @ref SPI_Clock_Polarity */
-
-  uint32_t CLKPhase;           /*!< Specifies the clock active edge for the bit capture.
-                                    This parameter can be a value of @ref SPI_Clock_Phase */
-
-  uint32_t NSS;                /*!< Specifies whether the NSS signal is managed by
-                                    hardware (NSS pin) or by software using the SSI bit.
-                                    This parameter can be a value of @ref SPI_Slave_Select_management */
-
-  uint32_t BaudRatePrescaler;  /*!< Specifies the Baud Rate prescaler value which will be
-                                    used to configure the transmit and receive SCK clock.
-                                    This parameter can be a value of @ref SPI_BaudRate_Prescaler
-                                    @note The communication clock is derived from the master
-                                    clock. The slave clock does not need to be set */
-
-  uint32_t FirstBit;           /*!< Specifies whether data transfers start from MSB or LSB bit.
-                                    This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
-  uint32_t TIMode;             /*!< Specifies if the TI mode is enabled or not.
-                                    This parameter can be a value of @ref SPI_TI_mode */
-
-  uint32_t CRCCalculation;     /*!< Specifies if the CRC calculation is enabled or not.
-                                    This parameter can be a value of @ref SPI_CRC_Calculation */
-
-  uint32_t CRCPolynomial;      /*!< Specifies the polynomial used for the CRC calculation.
-                                    This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
-
-}SPI_InitTypeDef;
-
-/**
-  * @brief  HAL SPI State structure definition
-  */
-typedef enum
-{
-  HAL_SPI_STATE_RESET      = 0x00,  /*!< SPI not yet initialized or disabled                */
-  HAL_SPI_STATE_READY      = 0x01,  /*!< SPI initialized and ready for use                  */
-  HAL_SPI_STATE_BUSY       = 0x02,  /*!< SPI process is ongoing                             */
-  HAL_SPI_STATE_BUSY_TX    = 0x12,  /*!< Data Transmission process is ongoing               */
-  HAL_SPI_STATE_BUSY_RX    = 0x22,  /*!< Data Reception process is ongoing                  */
-  HAL_SPI_STATE_BUSY_TX_RX = 0x32,  /*!< Data Transmission and Reception process is ongoing */
-  HAL_SPI_STATE_ERROR      = 0x03   /*!< SPI error state                                    */
-    
-}HAL_SPI_StateTypeDef;
-
-
-/** 
-  * @brief  SPI handle Structure definition
-  */
-typedef struct __SPI_HandleTypeDef
-{
-  SPI_TypeDef                *Instance;    /*!< SPI registers base address */
-
-  SPI_InitTypeDef            Init;         /*!< SPI communication parameters */
-
-  uint8_t                    *pTxBuffPtr;  /*!< Pointer to SPI Tx transfer Buffer */
-
-  uint16_t                   TxXferSize;   /*!< SPI Tx transfer size */
-  
-  uint16_t                   TxXferCount;  /*!< SPI Tx Transfer Counter */
-
-  uint8_t                    *pRxBuffPtr;  /*!< Pointer to SPI Rx transfer Buffer */
-
-  uint16_t                   RxXferSize;   /*!< SPI Rx transfer size */
-
-  uint16_t                   RxXferCount;  /*!< SPI Rx Transfer Counter */
-
-  DMA_HandleTypeDef          *hdmatx;      /*!< SPI Tx DMA handle parameters */
-
-  DMA_HandleTypeDef          *hdmarx;      /*!< SPI Rx DMA handle parameters */
-
-  void                       (*RxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Rx ISR */
-
-  void                       (*TxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Tx ISR */
-
-  HAL_LockTypeDef            Lock;         /*!< SPI locking object */
-
-  __IO HAL_SPI_StateTypeDef  State;        /*!< SPI communication state */
-
-  __IO uint32_t  ErrorCode;    /*!< SPI Error code */
-
-}SPI_HandleTypeDef;
-/**
-  * @}
-  */
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SPI_Exported_Constants SPI Exported Constants
-  * @{
-  */
-
-/** @defgroup SPI_Error_Codes SPI Error Codes
-  * @{
-  */ 
-#define HAL_SPI_ERROR_NONE      ((uint32_t)0x00)    /*!< No error             */
-#define HAL_SPI_ERROR_MODF      ((uint32_t)0x01)    /*!< MODF error           */
-#define HAL_SPI_ERROR_CRC       ((uint32_t)0x02)    /*!< CRC error            */
-#define HAL_SPI_ERROR_OVR       ((uint32_t)0x04)    /*!< OVR error            */
-#define HAL_SPI_ERROR_DMA       ((uint32_t)0x08)    /*!< DMA transfer error   */
-#define HAL_SPI_ERROR_FLAG      ((uint32_t)0x10)    /*!< Flag: RXNE,TXE, BSY  */
-/**
-  * @}
-  */
-
-
-
-
-/** @defgroup SPI_mode SPI mode
-  * @{
-  */
-#define SPI_MODE_SLAVE                  ((uint32_t)0x00000000)
-#define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Direction_mode SPI Direction mode
-  * @{
-  */
-#define SPI_DIRECTION_2LINES            ((uint32_t)0x00000000)
-#define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
-#define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_data_size SPI data size
-  * @{
-  */
-#define SPI_DATASIZE_8BIT               ((uint32_t)0x00000000)
-#define SPI_DATASIZE_16BIT              SPI_CR1_DFF
-
-/**
-  * @}
-  */ 
-
-/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
-  * @{
-  */
-#define SPI_POLARITY_LOW                ((uint32_t)0x00000000)
-#define SPI_POLARITY_HIGH               SPI_CR1_CPOL
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Clock_Phase SPI Clock Phase
-  * @{
-  */
-#define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000)
-#define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Slave_Select_management SPI Slave Select management
-  * @{
-  */
-#define SPI_NSS_SOFT                    SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000)
-#define SPI_NSS_HARD_OUTPUT             ((uint32_t)(SPI_CR2_SSOE << 16))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
-  * @{
-  */
-#define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000)
-#define SPI_BAUDRATEPRESCALER_4         ((uint32_t)SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_8         ((uint32_t)SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_16        ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_32        ((uint32_t)SPI_CR1_BR_2)
-#define SPI_BAUDRATEPRESCALER_64        ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_128       ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_256       ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
-  * @{
-  */
-#define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000)
-#define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_TI_mode SPI TI mode disable
-  * @brief  SPI TI Mode not supported for STM32F1xx family 
-  * @{
-  */
-#define SPI_TIMODE_DISABLE             ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-  
-/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
-  * @{
-  */
-#define SPI_CRCCALCULATION_DISABLE      ((uint32_t)0x00000000)
-#define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
-  * @{
-  */
-#define SPI_IT_TXE                      SPI_CR2_TXEIE
-#define SPI_IT_RXNE                     SPI_CR2_RXNEIE
-#define SPI_IT_ERR                      SPI_CR2_ERRIE
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Flag_definition SPI Flag definition
-  * @{
-  */
-#define SPI_FLAG_RXNE                   SPI_SR_RXNE
-#define SPI_FLAG_TXE                    SPI_SR_TXE
-#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR
-#define SPI_FLAG_MODF                   SPI_SR_MODF
-#define SPI_FLAG_OVR                    SPI_SR_OVR
-#define SPI_FLAG_BSY                    SPI_SR_BSY
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SPI_Private_Constants SPI Private Constants
-  * @{
-  */
-#define SPI_INVALID_CRC_ERROR     0          /* CRC error wrongly detected */
-#define SPI_VALID_CRC_ERROR       1          /* CRC error is true */
-/**
-  * @}
-  */ 
-
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SPI_Exported_Macros SPI Exported Macros
-  * @{
-  */
-
-/** @brief Reset SPI handle state
-  * @param  __HANDLE__: specifies the SPI handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-
-/** @brief  Enable the specified SPI interrupts.
-  * @param  __HANDLE__: specifies the SPI handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief  Disable the specified SPI interrupts.
-  * @param  __HANDLE__: specifies the SPI handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__: specifies the interrupt source to disable.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief  Check if the specified SPI interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the SPI handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
-  *          This parameter can be one of the following values:
-  *             @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *             @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *             @arg SPI_IT_ERR: Error interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Check whether the specified SPI flag is set or not.
-  * @param  __HANDLE__: specifies the SPI handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
-  *            @arg SPI_FLAG_CRCERR: CRC error flag
-  *            @arg SPI_FLAG_MODF: Mode fault flag
-  *            @arg SPI_FLAG_OVR: Overrun flag
-  *            @arg SPI_FLAG_BSY: Busy flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the SPI CRCERR pending flag.
-  * @param  __HANDLE__: specifies the SPI handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR))
-
-/** @brief  Clear the SPI MODF pending flag.
-  * @param  __HANDLE__: specifies the SPI handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)                      \
-do{                                                               \
-    __IO uint32_t tmpreg;                                         \
-    tmpreg = (__HANDLE__)->Instance->SR;                          \
-    tmpreg = CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
-    UNUSED(tmpreg);                                               \
-}while(0) 
-
-/** @brief  Clear the SPI OVR pending flag.
-  * @param  __HANDLE__: specifies the SPI handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)                \
-do{                                                        \
-    __IO uint32_t tmpreg;                                  \
-    tmpreg = (__HANDLE__)->Instance->DR;                   \
-    tmpreg = (__HANDLE__)->Instance->SR;                   \
-    UNUSED(tmpreg);                                        \
-}while(0)  
-
-
-/** @brief  Enables the SPI.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */                                                 
-#define __HAL_SPI_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-                                                 
-/** @brief  Disables the SPI.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */                                           
-#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
-/**
-  * @}
-  */
-
-
-/* Private macros -----------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros SPI Private Macros
-  * @{
-  */
-
-/** @brief  Checks if SPI Mode parameter is in allowed range.
-  * @param  __MODE__: specifies the SPI Mode.
-  *         This parameter can be a value of @ref SPI_mode
-  * @retval None
-  */
-#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || ((__MODE__) == SPI_MODE_MASTER))
-
-/** @brief  Checks if SPI Direction Mode parameter is in allowed range.
-  * @param  __MODE__: specifies the SPI Direction Mode.
-  *         This parameter can be a value of @ref SPI_Direction_mode
-  * @retval None
-  */
-#define IS_SPI_DIRECTION_MODE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES)        || \
-                                         ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
-                                         ((__MODE__) == SPI_DIRECTION_1LINE))
-
-/** @brief  Checks if SPI Direction Mode parameter is 1 or 2 lines.
-  * @param  __MODE__: specifies the SPI Direction Mode.
-  * @retval None
-  */
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES)  || \
-                                                    ((__MODE__) == SPI_DIRECTION_1LINE))
-
-/** @brief  Checks if SPI Direction Mode parameter is 2 lines.
-  * @param  __MODE__: specifies the SPI Direction Mode.
-  * @retval None
-  */
-#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
-
-/** @brief  Checks if SPI Data Size parameter is in allowed range.
-  * @param  __DATASIZE__: specifies the SPI Data Size.
-  *         This parameter can be a value of @ref SPI_data_size
-  * @retval None
-  */
-#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
-                                       ((__DATASIZE__) == SPI_DATASIZE_8BIT))
-
-/** @brief  Checks if SPI Serial clock steady state parameter is in allowed range.
-  * @param  __CPOL__: specifies the SPI serial clock steady state.
-  *         This parameter can be a value of @ref SPI_Clock_Polarity
-  * @retval None
-  */
-#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
-                               ((__CPOL__) == SPI_POLARITY_HIGH))
-
-/** @brief  Checks if SPI Clock Phase parameter is in allowed range.
-  * @param  __CPHA__: specifies the SPI Clock Phase.
-  *         This parameter can be a value of @ref SPI_Clock_Phase
-  * @retval None
-  */
-#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
-                               ((__CPHA__) == SPI_PHASE_2EDGE))
-
-/** @brief  Checks if SPI Slave select parameter is in allowed range.
-  * @param  __NSS__: specifies the SPI Slave Slelect management parameter.
-  *         This parameter can be a value of @ref SPI_Slave_Select_management
-  * @retval None
-  */
-#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT)       || \
-                             ((__NSS__) == SPI_NSS_HARD_INPUT) || \
-                             ((__NSS__) == SPI_NSS_HARD_OUTPUT))
-
-/** @brief  Checks if SPI Baudrate prescaler parameter is in allowed range.
-  * @param  __PRESCALER__: specifies the SPI Baudrate prescaler.
-  *         This parameter can be a value of @ref SPI_BaudRate_Prescaler
-  * @retval None
-  */
-#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2)   || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4)   || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8)   || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16)  || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32)  || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64)  || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
-
-/** @brief  Checks if SPI MSB LSB transmission parameter is in allowed range.
-  * @param  __BIT__: specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
-  *         This parameter can be a value of @ref SPI_MSB_LSB_transmission
-  * @retval None
-  */
-#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
-                                   ((__BIT__) == SPI_FIRSTBIT_LSB))
-
-/** @brief  Checks if SPI TI mode parameter is in allowed range.
-  * @param  __MODE__: specifies the SPI TI mode.
-  *         This parameter can be a value of @ref SPI_TI_mode
-  * @retval None
-  */
-#define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE)
-
-/** @brief  Checks if SPI CRC calculation enabled state is in allowed range.
-  * @param  __CALCULATION__: specifies the SPI CRC calculation enable state.
-  *         This parameter can be a value of @ref SPI_CRC_Calculation
-  * @retval None
-  */
-#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
-                                                 ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
-
-/** @brief  Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
-  * @param  __POLYNOMIAL__: specifies the SPI polynomial value to be used for the CRC calculation.
-  *         This parameter must be a number between Min_Data = 0 and Max_Data = 65535 
-  * @retval None
-  */
-#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1) && ((__POLYNOMIAL__) <= 0xFFFF))
-
-/** @brief  Sets the SPI transmit-only mode.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_1LINE_TX(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
-
-/** @brief  Sets the SPI receive-only mode.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */               
-#define SPI_1LINE_RX(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) 
-
-/** @brief  Resets the CRC calculation of the SPI.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
-                                     SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0)
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_Exported_Functions
-  * @{
-  */
-
-/* Initialization/de-initialization functions  **********************************/
-/** @addtogroup SPI_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-/* I/O operation functions  *****************************************************/
-/** @addtogroup SPI_Exported_Functions_Group2
-  * @{
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
-
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-
-/* Peripheral State and Control functions  **************************************/
-/** @addtogroup SPI_Exported_Functions_Group3
-  * @{
-  */
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Private functions --------------------------------------------------------*/
-/** @addtogroup SPI_Private_Functions
-  * @{
-  */
-uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi);
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_sram.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,201 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_sram.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of SRAM HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_SRAM_H
-#define __STM32F1xx_HAL_SRAM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_fsmc.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
-
-/** @addtogroup SRAM
-  * @{
-  */ 
-
-/* Exported typedef ----------------------------------------------------------*/
-
-/** @defgroup SRAM_Exported_Types SRAM Exported Types
-  * @{
-  */ 
-/** 
-  * @brief  HAL SRAM State structures definition  
-  */ 
-typedef enum
-{
-  HAL_SRAM_STATE_RESET     = 0x00,  /*!< SRAM not yet initialized or disabled           */
-  HAL_SRAM_STATE_READY     = 0x01,  /*!< SRAM initialized and ready for use             */
-  HAL_SRAM_STATE_BUSY      = 0x02,  /*!< SRAM internal process is ongoing               */
-  HAL_SRAM_STATE_ERROR     = 0x03,  /*!< SRAM error state                               */
-  HAL_SRAM_STATE_PROTECTED = 0x04   /*!< SRAM peripheral NORSRAM device write protected */
-  
-}HAL_SRAM_StateTypeDef;
-
-/** 
-  * @brief  SRAM handle Structure definition  
-  */ 
-typedef struct
-{
-  FSMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */ 
-  
-  FSMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
-  
-  FSMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
-
-  HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */ 
-  
-  __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
-  
-  DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
-  
-}SRAM_HandleTypeDef; 
-
-/**
-  * @}
-  */ 
-
-/* Exported constants --------------------------------------------------------*/ 
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
-  * @{
-  */ 
-
-/** @brief Reset SRAM handle state
-  * @param  __HANDLE__: SRAM handle
-  * @retval None
-  */
-#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
-
-/**
-  * @}
-  */ 
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup SRAM_Exported_Functions
- *  @{
- */
-
-/** @addtogroup SRAM_Exported_Functions_Group1
- *  @{
- */
- 
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
-HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
-void              HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
-void              HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
-
-void              HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
-void              HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup SRAM_Exported_Functions_Group2
- *  @{
- */
- 
-/* I/O operation functions  *****************************************************/
-HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup SRAM_Exported_Functions_Group3
- *  @{
- */
- 
-/* SRAM Control functions  ******************************************************/
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup SRAM_Exported_Functions_Group4
- *  @{
- */
- 
-/* SRAM State functions *********************************************************/
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_SRAM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_tim.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1767 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_tim.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of TIM HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_TIM_H
-#define __STM32F1xx_HAL_TIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup TIM
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIM_Exported_Types TIM Exported Types
-  * @{
-  */
-/**
-  * @brief  TIM Time base Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
-                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t CounterMode;       /*!< Specifies the counter mode.
-                                   This parameter can be a value of @ref TIM_Counter_Mode */
-
-  uint32_t Period;            /*!< Specifies the period value to be loaded into the active
-                                   Auto-Reload Register at the next update event.
-                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
-
-  uint32_t ClockDivision;     /*!< Specifies the clock division.
-                                   This parameter can be a value of @ref TIM_ClockDivision */
-
-  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
-                                    reaches zero, an update event is generated and counting restarts
-                                    from the RCR value (N).
-                                    This means in PWM mode that (N+1) corresponds to:
-                                        - the number of PWM periods in edge-aligned mode
-                                        - the number of half PWM period in center-aligned mode
-                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
-                                     @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_Base_InitTypeDef;
-
-/**
-  * @brief  TIM Output Compare Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t OCMode;        /*!< Specifies the TIM mode.
-                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
-  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
-                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
-  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t OCFastMode;   /*!< Specifies the Fast mode state.
-                               This parameter can be a value of @ref TIM_Output_Fast_State
-                               @note This parameter is valid only in PWM1 and PWM2 mode. */
-
-
-  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_OC_InitTypeDef;
-
-/**
-  * @brief  TIM One Pulse Mode Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t OCMode;        /*!< Specifies the TIM mode.
-                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
-  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
-                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
-  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t ICSelection;   /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t ICFilter;      /*!< Specifies the input capture filter.
-                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_OnePulse_InitTypeDef;
-
-
-/**
-  * @brief  TIM Input Capture Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t  ICPolarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t ICSelection;  /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
-                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t ICFilter;     /*!< Specifies the input capture filter.
-                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_IC_InitTypeDef;
-
-/**
-  * @brief  TIM Encoder Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Encoder_Mode */
-
-  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t IC1Selection;  /*!< Specifies the input.
-                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
-                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t IC1Filter;     /*!< Specifies the input capture filter.
-                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
-  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t IC2Selection;  /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
-                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t IC2Filter;     /*!< Specifies the input capture filter.
-                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_Encoder_InitTypeDef;
-
-
-/**
-  * @brief  TIM Clock Configuration Handle Structure definition
-  */
-typedef struct
-{
-  uint32_t ClockSource;     /*!< TIM clock sources
-                                 This parameter can be a value of @ref TIM_Clock_Source */
-  uint32_t ClockPolarity;   /*!< TIM clock polarity
-                                 This parameter can be a value of @ref TIM_Clock_Polarity */
-  uint32_t ClockPrescaler;  /*!< TIM clock prescaler
-                                 This parameter can be a value of @ref TIM_Clock_Prescaler */
-  uint32_t ClockFilter;    /*!< TIM clock filter
-                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClockConfigTypeDef;
-
-/**
-  * @brief  TIM Clear Input Configuration Handle Structure definition
-  */
-typedef struct
-{
-  uint32_t ClearInputState;      /*!< TIM clear Input state
-                                      This parameter can be ENABLE or DISABLE */
-  uint32_t ClearInputSource;     /*!< TIM clear Input sources
-                                      This parameter can be a value of @ref TIM_ClearInput_Source */
-  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
-                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */
-  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
-                                      This parameter can be a value of @ref TIM_ClearInput_Prescaler */
-  uint32_t ClearInputFilter;    /*!< TIM Clear Input filter
-                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClearInputConfigTypeDef;
-
-/**
-  * @brief  TIM Slave configuration Structure definition
-  */
-typedef struct {
-  uint32_t  SlaveMode;      /*!< Slave mode selection
-                               This parameter can be a value of @ref TIM_Slave_Mode */
-  uint32_t  InputTrigger;      /*!< Input Trigger source
-                                  This parameter can be a value of @ref TIM_Trigger_Selection */
-  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
-                                  This parameter can be a value of @ref TIM_Trigger_Polarity */
-  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
-                                  This parameter can be a value of @ref TIM_Trigger_Prescaler */
-  uint32_t  TriggerFilter;     /*!< Input trigger filter
-                                  This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
-}TIM_SlaveConfigTypeDef;
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_TIM_STATE_RESET             = 0x00,    /*!< Peripheral not yet initialized or disabled  */
-  HAL_TIM_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use    */
-  HAL_TIM_STATE_BUSY              = 0x02,    /*!< An internal process is ongoing              */
-  HAL_TIM_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                               */
-  HAL_TIM_STATE_ERROR             = 0x04     /*!< Reception process is ongoing                */
-}HAL_TIM_StateTypeDef;
-
-/**
-  * @brief  HAL Active channel structures definition
-  */
-typedef enum
-{
-  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01,    /*!< The active channel is 1     */
-  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02,    /*!< The active channel is 2     */
-  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04,    /*!< The active channel is 3     */
-  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08,    /*!< The active channel is 4     */
-  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00    /*!< All active channels cleared */
-}HAL_TIM_ActiveChannel;
-
-/**
-  * @brief  TIM Time Base Handle Structure definition
-  */
-typedef struct
-{
-  TIM_TypeDef              *Instance;     /*!< Register base address             */
-  TIM_Base_InitTypeDef     Init;          /*!< TIM Time Base required parameters */
-  HAL_TIM_ActiveChannel    Channel;       /*!< Active channel                    */
-  DMA_HandleTypeDef        *hdma[7];      /*!< DMA Handlers array
-                                             This array is accessed by a @ref TIM_DMA_Handle_index */
-  HAL_LockTypeDef          Lock;          /*!< Locking object                    */
-  __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
-}TIM_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Constants TIM Exported Constants
-  * @{
-  */
-
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
-  * @{
-  */
-#define  TIM_INPUTCHANNELPOLARITY_RISING      ((uint32_t)0x00000000)            /*!< Polarity for TIx source */
-#define  TIM_INPUTCHANNELPOLARITY_FALLING     (TIM_CCER_CC1P)                   /*!< Polarity for TIx source */
-#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
-  * @{
-  */
-#define TIM_ETRPOLARITY_INVERTED              (TIM_SMCR_ETP)                    /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED           ((uint32_t)0x0000)                /*!< Polarity for ETR source */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
-  * @{
-  */
-#define TIM_ETRPRESCALER_DIV1                 ((uint32_t)0x0000)                /*!< No prescaler is used */
-#define TIM_ETRPRESCALER_DIV2                 (TIM_SMCR_ETPS_0)                 /*!< ETR input source is divided by 2 */
-#define TIM_ETRPRESCALER_DIV4                 (TIM_SMCR_ETPS_1)                 /*!< ETR input source is divided by 4 */
-#define TIM_ETRPRESCALER_DIV8                 (TIM_SMCR_ETPS)                   /*!< ETR input source is divided by 8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Counter_Mode TIM Counter Mode
-  * @{
-  */
-#define TIM_COUNTERMODE_UP                 ((uint32_t)0x0000)
-#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR
-#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0
-#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1
-#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClockDivision TIM ClockDivision
-  * @{
-  */
-#define TIM_CLOCKDIVISION_DIV1                       ((uint32_t)0x0000)
-#define TIM_CLOCKDIVISION_DIV2                       (TIM_CR1_CKD_0)
-#define TIM_CLOCKDIVISION_DIV4                       (TIM_CR1_CKD_1)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
-  * @{
-  */
-#define TIM_OCMODE_TIMING                   ((uint32_t)0x0000)
-#define TIM_OCMODE_ACTIVE                   (TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_INACTIVE                 (TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M)
-#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_FORCED_INACTIVE          (TIM_CCMR1_OC1M_2)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_State TIM Output Compare State
-  * @{
-  */
-#define TIM_OUTPUTSTATE_DISABLE            ((uint32_t)0x0000)
-#define TIM_OUTPUTSTATE_ENABLE             (TIM_CCER_CC1E)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Fast_State TIM Output Fast State
-  * @{
-  */
-#define TIM_OCFAST_DISABLE                ((uint32_t)0x0000)
-#define TIM_OCFAST_ENABLE                 (TIM_CCMR1_OC1FE)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
-  * @{
-  */
-#define TIM_OUTPUTNSTATE_DISABLE            ((uint32_t)0x0000)
-#define TIM_OUTPUTNSTATE_ENABLE             (TIM_CCER_CC1NE)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
-  * @{
-  */
-#define TIM_OCPOLARITY_HIGH                ((uint32_t)0x0000)
-#define TIM_OCPOLARITY_LOW                 (TIM_CCER_CC1P)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
-  * @{
-  */
-#define TIM_OCNPOLARITY_HIGH               ((uint32_t)0x0000)
-#define TIM_OCNPOLARITY_LOW                (TIM_CCER_CC1NP)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
-  * @{
-  */
-#define TIM_OCIDLESTATE_SET                (TIM_CR2_OIS1)
-#define TIM_OCIDLESTATE_RESET              ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
-  * @{
-  */
-#define TIM_OCNIDLESTATE_SET               (TIM_CR2_OIS1N)
-#define TIM_OCNIDLESTATE_RESET             ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Channel TIM Channel
-  * @{
-  */
-#define TIM_CHANNEL_1                      ((uint32_t)0x0000)
-#define TIM_CHANNEL_2                      ((uint32_t)0x0004)
-#define TIM_CHANNEL_3                      ((uint32_t)0x0008)
-#define TIM_CHANNEL_4                      ((uint32_t)0x000C)
-#define TIM_CHANNEL_ALL                    ((uint32_t)0x0018)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
-  * @{
-  */
-#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING
-#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING
-#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
-  * @{
-  */
-#define TIM_ICSELECTION_DIRECTTI           (TIM_CCMR1_CC1S_0)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
-                                                                               connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI         (TIM_CCMR1_CC1S_1)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
-                                                                               connected to IC2, IC1, IC4 or IC3, respectively */
-#define TIM_ICSELECTION_TRC                (TIM_CCMR1_CC1S)     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
-  * @{
-  */
-#define TIM_ICPSC_DIV1                     ((uint32_t)0x0000)                 /*!< Capture performed each time an edge is detected on the capture input */
-#define TIM_ICPSC_DIV2                     (TIM_CCMR1_IC1PSC_0)     /*!< Capture performed once every 2 events */
-#define TIM_ICPSC_DIV4                     (TIM_CCMR1_IC1PSC_1)     /*!< Capture performed once every 4 events */
-#define TIM_ICPSC_DIV8                     (TIM_CCMR1_IC1PSC)       /*!< Capture performed once every 8 events */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
-  * @{
-  */
-#define TIM_OPMODE_SINGLE                  (TIM_CR1_OPM)
-#define TIM_OPMODE_REPETITIVE              ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
-  * @{
-  */
-#define TIM_ENCODERMODE_TI1                (TIM_SMCR_SMS_0)
-#define TIM_ENCODERMODE_TI2                (TIM_SMCR_SMS_1)
-#define TIM_ENCODERMODE_TI12               (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
-  * @{
-  */
-#define TIM_IT_UPDATE           (TIM_DIER_UIE)
-#define TIM_IT_CC1              (TIM_DIER_CC1IE)
-#define TIM_IT_CC2              (TIM_DIER_CC2IE)
-#define TIM_IT_CC3              (TIM_DIER_CC3IE)
-#define TIM_IT_CC4              (TIM_DIER_CC4IE)
-#define TIM_IT_COM              (TIM_DIER_COMIE)
-#define TIM_IT_TRIGGER          (TIM_DIER_TIE)
-#define TIM_IT_BREAK            (TIM_DIER_BIE)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Commutation_Source  TIM Commutation Source
-  * @{
-  */
-#define TIM_COMMUTATION_TRGI              (TIM_CR2_CCUS)
-#define TIM_COMMUTATION_SOFTWARE          ((uint32_t)0x0000)
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_sources TIM DMA Sources
-  * @{
-  */
-#define TIM_DMA_UPDATE                     (TIM_DIER_UDE)
-#define TIM_DMA_CC1                        (TIM_DIER_CC1DE)
-#define TIM_DMA_CC2                        (TIM_DIER_CC2DE)
-#define TIM_DMA_CC3                        (TIM_DIER_CC3DE)
-#define TIM_DMA_CC4                        (TIM_DIER_CC4DE)
-#define TIM_DMA_COM                        (TIM_DIER_COMDE)
-#define TIM_DMA_TRIGGER                    (TIM_DIER_TDE)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Event_Source TIM Event Source
-  * @{
-  */
-#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG
-#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G
-#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G
-#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G
-#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G
-#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG
-#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG
-#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Flag_definition TIM Flag Definition
-  * @{
-  */
-#define TIM_FLAG_UPDATE                    (TIM_SR_UIF)
-#define TIM_FLAG_CC1                       (TIM_SR_CC1IF)
-#define TIM_FLAG_CC2                       (TIM_SR_CC2IF)
-#define TIM_FLAG_CC3                       (TIM_SR_CC3IF)
-#define TIM_FLAG_CC4                       (TIM_SR_CC4IF)
-#define TIM_FLAG_COM                       (TIM_SR_COMIF)
-#define TIM_FLAG_TRIGGER                   (TIM_SR_TIF)
-#define TIM_FLAG_BREAK                     (TIM_SR_BIF)
-#define TIM_FLAG_CC1OF                     (TIM_SR_CC1OF)
-#define TIM_FLAG_CC2OF                     (TIM_SR_CC2OF)
-#define TIM_FLAG_CC3OF                     (TIM_SR_CC3OF)
-#define TIM_FLAG_CC4OF                     (TIM_SR_CC4OF)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Source TIM Clock Source
-  * @{
-  */
-#define	TIM_CLOCKSOURCE_ETRMODE2    (TIM_SMCR_ETPS_1)
-#define	TIM_CLOCKSOURCE_INTERNAL    (TIM_SMCR_ETPS_0)
-#define	TIM_CLOCKSOURCE_ITR0        ((uint32_t)0x0000)
-#define	TIM_CLOCKSOURCE_ITR1        (TIM_SMCR_TS_0)
-#define	TIM_CLOCKSOURCE_ITR2        (TIM_SMCR_TS_1)
-#define	TIM_CLOCKSOURCE_ITR3        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
-#define	TIM_CLOCKSOURCE_TI1ED       (TIM_SMCR_TS_2)
-#define	TIM_CLOCKSOURCE_TI1         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
-#define	TIM_CLOCKSOURCE_TI2         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
-#define	TIM_CLOCKSOURCE_ETRMODE1    (TIM_SMCR_TS)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
-  * @{
-  */
-#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED          /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED       /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING   /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
-  * @{
-  */
-#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
-#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClearInput_Source TIM ClearInput Source
-  * @{
-  */
-#define TIM_CLEARINPUTSOURCE_ETR           ((uint32_t)0x0001)
-#define TIM_CLEARINPUTSOURCE_OCREFCLR      ((uint32_t)0x0002)
-#define TIM_CLEARINPUTSOURCE_NONE          ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
-  * @{
-  */
-#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED                    /*!< Polarity for ETRx pin */
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED                          /*!< Polarity for ETRx pin */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
-  * @{
-  */
-#define TIM_CLEARINPUTPRESCALER_DIV1                    TIM_ETRPRESCALER_DIV1      /*!< No prescaler is used */
-#define TIM_CLEARINPUTPRESCALER_DIV2                    TIM_ETRPRESCALER_DIV2      /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV4                    TIM_ETRPRESCALER_DIV4      /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV8                    TIM_ETRPRESCALER_DIV8        /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
-  * @{
-  */
-#define TIM_OSSR_ENABLE         (TIM_BDTR_OSSR)
-#define TIM_OSSR_DISABLE              ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
-  * @{
-  */
-#define TIM_OSSI_ENABLE	       (TIM_BDTR_OSSI)
-#define TIM_OSSI_DISABLE            ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Lock_level TIM Lock level
-  * @{
-  */
-#define TIM_LOCKLEVEL_OFF	   ((uint32_t)0x0000)
-#define TIM_LOCKLEVEL_1            (TIM_BDTR_LOCK_0)
-#define TIM_LOCKLEVEL_2            (TIM_BDTR_LOCK_1)
-#define TIM_LOCKLEVEL_3            (TIM_BDTR_LOCK)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
-  * @{
-  */
-#define TIM_BREAK_ENABLE          (TIM_BDTR_BKE)
-#define TIM_BREAK_DISABLE         ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
-  * @{
-  */
-#define TIM_BREAKPOLARITY_LOW        ((uint32_t)0x0000)
-#define TIM_BREAKPOLARITY_HIGH       (TIM_BDTR_BKP)
-/**
-  * @}
-  */
-/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
-  * @{
-  */
-#define TIM_AUTOMATICOUTPUT_ENABLE           (TIM_BDTR_AOE)
-#define	TIM_AUTOMATICOUTPUT_DISABLE          ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
-  * @{
-  */
-#define	TIM_TRGO_RESET            ((uint32_t)0x0000)
-#define	TIM_TRGO_ENABLE           (TIM_CR2_MMS_0)
-#define	TIM_TRGO_UPDATE           (TIM_CR2_MMS_1)
-#define	TIM_TRGO_OC1              ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-#define	TIM_TRGO_OC1REF           (TIM_CR2_MMS_2)
-#define	TIM_TRGO_OC2REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
-#define	TIM_TRGO_OC3REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
-#define	TIM_TRGO_OC4REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Slave_Mode TIM Slave Mode
-  * @{
-  */
-#define TIM_SLAVEMODE_DISABLE              ((uint32_t)0x0000)
-#define TIM_SLAVEMODE_RESET                ((uint32_t)0x0004)
-#define TIM_SLAVEMODE_GATED                ((uint32_t)0x0005)
-#define TIM_SLAVEMODE_TRIGGER              ((uint32_t)0x0006)
-#define TIM_SLAVEMODE_EXTERNAL1            ((uint32_t)0x0007)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
-  * @{
-  */
-#define TIM_MASTERSLAVEMODE_ENABLE          ((uint32_t)0x0080)
-#define TIM_MASTERSLAVEMODE_DISABLE         ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
-  * @{
-  */
-#define TIM_TS_ITR0                        ((uint32_t)0x0000)
-#define TIM_TS_ITR1                        ((uint32_t)0x0010)
-#define TIM_TS_ITR2                        ((uint32_t)0x0020)
-#define TIM_TS_ITR3                        ((uint32_t)0x0030)
-#define TIM_TS_TI1F_ED                     ((uint32_t)0x0040)
-#define TIM_TS_TI1FP1                      ((uint32_t)0x0050)
-#define TIM_TS_TI2FP2                      ((uint32_t)0x0060)
-#define TIM_TS_ETRF                        ((uint32_t)0x0070)
-#define TIM_TS_NONE                        ((uint32_t)0xFFFF)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
-  * @{
-  */
-#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
-  * @{
-  */
-#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
-#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
-#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
-#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
-  * @{
-  */
-#define TIM_TI1SELECTION_CH1                ((uint32_t)0x0000)
-#define TIM_TI1SELECTION_XORCOMBINATION     (TIM_CR2_TI1S)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
-  * @{
-  */
-#define TIM_DMABASE_CR1                    (0x00000000)
-#define TIM_DMABASE_CR2                    (0x00000001)
-#define TIM_DMABASE_SMCR                   (0x00000002)
-#define TIM_DMABASE_DIER                   (0x00000003)
-#define TIM_DMABASE_SR                     (0x00000004)
-#define TIM_DMABASE_EGR                    (0x00000005)
-#define TIM_DMABASE_CCMR1                  (0x00000006)
-#define TIM_DMABASE_CCMR2                  (0x00000007)
-#define TIM_DMABASE_CCER                   (0x00000008)
-#define TIM_DMABASE_CNT                    (0x00000009)
-#define TIM_DMABASE_PSC                    (0x0000000A)
-#define TIM_DMABASE_ARR                    (0x0000000B)
-#define TIM_DMABASE_RCR                    (0x0000000C)
-#define TIM_DMABASE_CCR1                   (0x0000000D)
-#define TIM_DMABASE_CCR2                   (0x0000000E)
-#define TIM_DMABASE_CCR3                   (0x0000000F)
-#define TIM_DMABASE_CCR4                   (0x00000010)
-#define TIM_DMABASE_BDTR                   (0x00000011)
-#define TIM_DMABASE_DCR                    (0x00000012)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
-  * @{
-  */
-#define TIM_DMABURSTLENGTH_1TRANSFER           (0x00000000)
-#define TIM_DMABURSTLENGTH_2TRANSFERS          (0x00000100)
-#define TIM_DMABURSTLENGTH_3TRANSFERS          (0x00000200)
-#define TIM_DMABURSTLENGTH_4TRANSFERS          (0x00000300)
-#define TIM_DMABURSTLENGTH_5TRANSFERS          (0x00000400)
-#define TIM_DMABURSTLENGTH_6TRANSFERS          (0x00000500)
-#define TIM_DMABURSTLENGTH_7TRANSFERS          (0x00000600)
-#define TIM_DMABURSTLENGTH_8TRANSFERS          (0x00000700)
-#define TIM_DMABURSTLENGTH_9TRANSFERS          (0x00000800)
-#define TIM_DMABURSTLENGTH_10TRANSFERS         (0x00000900)
-#define TIM_DMABURSTLENGTH_11TRANSFERS         (0x00000A00)
-#define TIM_DMABURSTLENGTH_12TRANSFERS         (0x00000B00)
-#define TIM_DMABURSTLENGTH_13TRANSFERS         (0x00000C00)
-#define TIM_DMABURSTLENGTH_14TRANSFERS         (0x00000D00)
-#define TIM_DMABURSTLENGTH_15TRANSFERS         (0x00000E00)
-#define TIM_DMABURSTLENGTH_16TRANSFERS         (0x00000F00)
-#define TIM_DMABURSTLENGTH_17TRANSFERS         (0x00001000)
-#define TIM_DMABURSTLENGTH_18TRANSFERS         (0x00001100)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
-  * @{
-  */
-#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0)       /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1                   ((uint16_t) 0x1)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2                   ((uint16_t) 0x2)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3                   ((uint16_t) 0x3)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4                   ((uint16_t) 0x4)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x5)       /*!< Index of the DMA handle used for Commutation DMA requests */
-#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x6)       /*!< Index of the DMA handle used for Trigger DMA requests */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
-  * @{
-  */
-#define TIM_CCx_ENABLE                   ((uint32_t)0x0001)
-#define TIM_CCx_DISABLE                  ((uint32_t)0x0000)
-#define TIM_CCxN_ENABLE                  ((uint32_t)0x0004)
-#define TIM_CCxN_DISABLE                 ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private Constants -----------------------------------------------------------*/
-/** @defgroup TIM_Private_Constants TIM Private Constants
-  * @{
-  */
-
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
-   channels have been disabled */
-#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
-
-/**
-  * @}
-  */
-
-/* Private Macros -----------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
- * @{
- */
-
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP)              || \
-                                   ((MODE) == TIM_COUNTERMODE_DOWN)            || \
-                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
-                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
-                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
-
-#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
-                                       ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
-                                       ((DIV) == TIM_CLOCKDIVISION_DIV4))
-
-#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
-                               ((MODE) == TIM_OCMODE_PWM2))
-                              
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING)       || \
-                          ((MODE) == TIM_OCMODE_ACTIVE)           || \
-                          ((MODE) == TIM_OCMODE_INACTIVE)         || \
-                          ((MODE) == TIM_OCMODE_TOGGLE)           || \
-                          ((MODE) == TIM_OCMODE_FORCED_ACTIVE)    || \
-                          ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
-
-#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
-                                  ((STATE) == TIM_OCFAST_ENABLE))
-
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
-                                      ((POLARITY) == TIM_OCPOLARITY_LOW))
-
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
-                                       ((POLARITY) == TIM_OCNPOLARITY_LOW))
-
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
-                                    ((STATE) == TIM_OCIDLESTATE_RESET))
-
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
-                                     ((STATE) == TIM_OCNIDLESTATE_RESET))
-
-#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
-                                  ((CHANNEL) == TIM_CHANNEL_2) || \
-                                  ((CHANNEL) == TIM_CHANNEL_3) || \
-                                  ((CHANNEL) == TIM_CHANNEL_4) || \
-                                  ((CHANNEL) == TIM_CHANNEL_ALL))
-                                 
-#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
-                                      ((CHANNEL) == TIM_CHANNEL_2))                                       
-                                      
-#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
-                                                ((CHANNEL) == TIM_CHANNEL_2) || \
-                                                ((CHANNEL) == TIM_CHANNEL_3))
-
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING)   || \
-                                      ((POLARITY) == TIM_ICPOLARITY_FALLING)  || \
-                                      ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
-
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI)   || \
-                                        ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
-                                        ((SELECTION) == TIM_ICSELECTION_TRC))
-
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV8))
-
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
-                               ((MODE) == TIM_OPMODE_REPETITIVE))
-
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
-                                   ((MODE) == TIM_ENCODERMODE_TI2) || \
-                                   ((MODE) == TIM_ENCODERMODE_TI12))   
-
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
-
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
-
-#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR0)     || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR1)     || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR2)     || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR3)     || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_TI1ED)    || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_TI1)      || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_TI2)      || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
-
-#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED)    || \
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_RISING)      || \
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_FALLING)     || \
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
-
-#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
-                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
-                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
-                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) 
-
-#define IS_TIM_CLOCKFILTER(ICFILTER)       ((ICFILTER) <= 0xF) 
-
-#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)      || \
-                                          ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
-                                          ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
-
-#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
-                                              ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
-
-#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER)   (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
-                                                  ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
-                                                  ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
-                                                  ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
-
-#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
-
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
-                                  ((STATE) == TIM_OSSR_DISABLE))
-
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
-                                  ((STATE) == TIM_OSSI_DISABLE))
-
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
-                                  ((LEVEL) == TIM_LOCKLEVEL_1)   || \
-                                  ((LEVEL) == TIM_LOCKLEVEL_2)   || \
-                                  ((LEVEL) == TIM_LOCKLEVEL_3))
-
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
-                                   ((STATE) == TIM_BREAK_DISABLE))
-
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
-                                         ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
-                                              ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
-
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET)  || \
-                                    ((SOURCE) == TIM_TRGO_ENABLE) || \
-                                    ((SOURCE) == TIM_TRGO_UPDATE) || \
-                                    ((SOURCE) == TIM_TRGO_OC1)    || \
-                                    ((SOURCE) == TIM_TRGO_OC1REF) || \
-                                    ((SOURCE) == TIM_TRGO_OC2REF) || \
-                                    ((SOURCE) == TIM_TRGO_OC3REF) || \
-                                    ((SOURCE) == TIM_TRGO_OC4REF))
-
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
-                                 ((MODE) == TIM_SLAVEMODE_GATED)   || \
-                                 ((MODE) == TIM_SLAVEMODE_RESET)   || \
-                                 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
-                                 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
-
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
-                                 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
-
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0)    || \
-                                             ((SELECTION) == TIM_TS_ITR1)    || \
-                                             ((SELECTION) == TIM_TS_ITR2)    || \
-                                             ((SELECTION) == TIM_TS_ITR3)    || \
-                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
-                                             ((SELECTION) == TIM_TS_TI1FP1)  || \
-                                             ((SELECTION) == TIM_TS_TI2FP2)  || \
-                                             ((SELECTION) == TIM_TS_ETRF))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
-                                                           ((SELECTION) == TIM_TS_ITR1) || \
-                                                           ((SELECTION) == TIM_TS_ITR2) || \
-                                                           ((SELECTION) == TIM_TS_ITR3) || \
-                                                           ((SELECTION) == TIM_TS_NONE))
-
-#define IS_TIM_TRIGGERPOLARITY(POLARITY)     (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_RISING     ) || \
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING    ) || \
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
-
-#define IS_TIM_TRIGGERPRESCALER(PRESCALER)  (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
-                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
-                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
-                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
-
-#define IS_TIM_TRIGGERFILTER(ICFILTER)     ((ICFILTER) <= 0xF)
-
-#define IS_TIM_TI1SELECTION(TI1SELECTION)   (((TI1SELECTION) == TIM_TI1SELECTION_CH1)            || \
-                                             ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
-
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1)   || \
-                               ((BASE) == TIM_DMABASE_CR2)   || \
-                               ((BASE) == TIM_DMABASE_SMCR)  || \
-                               ((BASE) == TIM_DMABASE_DIER)  || \
-                               ((BASE) == TIM_DMABASE_SR)    || \
-                               ((BASE) == TIM_DMABASE_EGR)   || \
-                               ((BASE) == TIM_DMABASE_CCMR1) || \
-                               ((BASE) == TIM_DMABASE_CCMR2) || \
-                               ((BASE) == TIM_DMABASE_CCER)  || \
-                               ((BASE) == TIM_DMABASE_CNT)   || \
-                               ((BASE) == TIM_DMABASE_PSC)   || \
-                               ((BASE) == TIM_DMABASE_ARR)   || \
-                               ((BASE) == TIM_DMABASE_RCR)   || \
-                               ((BASE) == TIM_DMABASE_CCR1)  || \
-                               ((BASE) == TIM_DMABASE_CCR2)  || \
-                               ((BASE) == TIM_DMABASE_CCR3)  || \
-                               ((BASE) == TIM_DMABASE_CCR4)  || \
-                               ((BASE) == TIM_DMABASE_BDTR)  || \
-                               ((BASE) == TIM_DMABASE_DCR))
-
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER)   || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
-
-/** @brief Set TIM IC prescaler
-  * @param  __HANDLE__: TIM handle
-  * @param  __CHANNEL__: specifies TIM Channel
-  * @param  __ICPSC__: specifies the prescaler value.
-  * @retval None
-  */
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
-
-/** @brief Reset TIM IC prescaler
-  * @param  __HANDLE__: TIM handle
-  * @param  __CHANNEL__: specifies TIM Channel
-  * @retval None
-  */
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
-
-
-/** @brief Set TIM IC polarity
-  * @param  __HANDLE__: TIM handle
-  * @param  __CHANNEL__: specifies TIM Channel
-  * @param  __POLARITY__: specifies TIM Channel Polarity
-  * @retval None
-  */
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
-
-/** @brief Reset TIM IC polarity
-  * @param  __HANDLE__: TIM handle
-  * @param  __CHANNEL__: specifies TIM Channel
-  * @retval None
-  */
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
- ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
-
-/**
-  * @}
-  */
-
-/* Private Functions --------------------------------------------------------*/
-/** @addtogroup TIM_Private_Functions
- * @{
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
-void TIM_DMAError(DMA_HandleTypeDef *hdma);
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup TIM_Exported_Macros TIM Exported Macros
-  * @{
-  */
-
-/** @brief  Reset TIM handle state
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
-  */
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
-
-/**
-  * @brief  Enable the TIM peripheral.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
- */
-#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
-
-/**
-  * @brief  Enable the TIM main Output.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
-  */
-#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
-
-/**
-  * @brief  Disable the TIM peripheral.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE(__HANDLE__) \
-                        do { \
-                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
-                            { \
-                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
-                            { \
-                              (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
-                            } \
-                          } \
-                        } while(0)
-/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
-   channels have been disabled */
-/**
-  * @brief  Disable the TIM main Output.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
-  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
-  */
-#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
-                        do { \
-                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
-                          { \
-                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
-                            { \
-                              (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
-                            } \
-                            } \
-                        } while(0)
-
-/**
-  * @brief  Enables the specified TIM interrupt.
-  * @param  __HANDLE__: specifies the TIM Handle.
-  * @param  __INTERRUPT__: specifies the TIM interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_IT_UPDATE: Update interrupt
-  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
-  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
-  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
-  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
-  *            @arg TIM_IT_COM:   Commutation interrupt
-  *            @arg TIM_IT_TRIGGER: Trigger interrupt
-  *            @arg TIM_IT_BREAK: Break interrupt
-  * @retval None
-  */
-#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
-
-/**
-  * @brief  Disables the specified TIM interrupt.
-  * @param  __HANDLE__: specifies the TIM Handle.
-  * @param  __INTERRUPT__: specifies the TIM interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_IT_UPDATE: Update interrupt
-  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
-  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
-  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
-  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
-  *            @arg TIM_IT_COM:   Commutation interrupt
-  *            @arg TIM_IT_TRIGGER: Trigger interrupt
-  *            @arg TIM_IT_BREAK: Break interrupt
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Enables the specified DMA request.
-  * @param  __HANDLE__: specifies the TIM Handle.
-  * @param  __DMA__: specifies the TIM DMA request to enable.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_DMA_UPDATE: Update DMA request
-  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
-  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
-  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
-  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
-  *            @arg TIM_DMA_COM:   Commutation DMA request
-  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
-  * @retval None
-  */
-#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
-
-/**
-  * @brief  Disables the specified DMA request.
-  * @param  __HANDLE__: specifies the TIM Handle.
-  * @param  __DMA__: specifies the TIM DMA request to disable.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_DMA_UPDATE: Update DMA request
-  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
-  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
-  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
-  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
-  *            @arg TIM_DMA_COM:   Commutation DMA request
-  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
-
-/**
-  * @brief  Checks whether the specified TIM interrupt flag is set or not.
-  * @param  __HANDLE__: specifies the TIM Handle.
-  * @param  __FLAG__: specifies the TIM interrupt flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
-  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
-  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
-  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
-  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
-  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
-  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
-  *            @arg TIM_FLAG_BREAK: Break interrupt flag   
-  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
-  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
-  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
-  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief  Clears the specified TIM interrupt flag.
-  * @param  __HANDLE__: specifies the TIM Handle.
-  * @param  __FLAG__: specifies the TIM interrupt flag to clear.
-  *        This parameter can be one of the following values:
-  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
-  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
-  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
-  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
-  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
-  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
-  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
-  *            @arg TIM_FLAG_BREAK: Break interrupt flag   
-  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
-  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
-  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
-  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/**
-  * @brief  Checks whether the specified TIM interrupt has occurred or not.
-  * @param  __HANDLE__: TIM handle
-  * @param  __INTERRUPT__: specifies the TIM interrupt source to check.
-  * @retval The state of TIM_IT (SET or RESET).
-  */
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/**
-  * @brief Clear the TIM interrupt pending bits
-  * @param  __HANDLE__: TIM handle
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
-  * @retval None
-  */
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
-
-/**
-  * @brief  Indicates whether or not the TIM Counter is used as downcounter
-  * @param  __HANDLE__: TIM handle.
-  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
-  * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
-mode.
-  */
-#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)            (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
-
-/**
-  * @brief  Sets the TIM active prescaler register value on update event.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __PRESC__: specifies the active prescaler register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
-
-/**
-  * @brief  Sets the TIM Capture Compare Register value on runtime without
-  *         calling another time ConfigChannel function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __COMPARE__: specifies the Capture Compare register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
-(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
-
-/**
-  * @brief  Gets the TIM Capture Compare Register value on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channel associated with the capture compare register
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
-  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
-  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
-  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
-  * @retval None
-  */
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
-  (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
-
-/**
-  * @brief  Sets the TIM Counter Register value on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __COUNTER__: specifies the Counter register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
-
-/**
-  * @brief  Gets the TIM Counter Register value on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
-  */
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
-   ((__HANDLE__)->Instance->CNT)
-
-/**
-  * @brief  Sets the TIM Autoreload Register value on runtime without calling
-  *         another time any Init function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __AUTORELOAD__: specifies the Counter register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
-                        do{                                                    \
-                              (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
-                              (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
-                          } while(0)
-
-/**
-  * @brief  Gets the TIM Autoreload Register value on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
-  */
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
-   ((__HANDLE__)->Instance->ARR)
-
-/**
-  * @brief  Sets the TIM Clock Division value on runtime without calling
-  *         another time any Init function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CKD__: specifies the clock division value.
-  *          This parameter can be one of the following value:
-  *            @arg TIM_CLOCKDIVISION_DIV1
-  *            @arg TIM_CLOCKDIVISION_DIV2
-  *            @arg TIM_CLOCKDIVISION_DIV4
-  * @retval None
-  */
-#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
-                        do{                                                    \
-                              (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
-                              (__HANDLE__)->Instance->CR1 |= (__CKD__);                   \
-                              (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
-                          } while(0)
-
-/**
-  * @brief  Gets the TIM Clock Division value on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
-  */
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  \
-   ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
-
-/**
-  * @brief  Sets the TIM Input Capture prescaler on runtime without calling
-  *         another time HAL_TIM_IC_ConfigChannel() function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __ICPSC__: specifies the Input Capture4 prescaler new value.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPSC_DIV1: no prescaler
-  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  * @retval None
-  */
-#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
-                        do{                                                    \
-                              TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
-                              TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
-                          } while(0)
-
-/**
-  * @brief  Gets the TIM Input Capture prescaler on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__: TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
-  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
-  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
-  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
-  * @retval None
-  */
-#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
-   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
-
-/**
-  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register
-  * @param  __HANDLE__: TIM handle.
-  * @note  When the USR bit of the TIMx_CR1 register is set, only counter
-  *        overflow/underflow generates an update interrupt or DMA request (if
-  *        enabled)
-  * @retval None
-  */
-#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
-    ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
-
-/**
-  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register
-  * @param  __HANDLE__: TIM handle.
-  * @note  When the USR bit of the TIMx_CR1 register is reset, any of the
-  *        following events generate an update interrupt or DMA request (if
-  *        enabled):
-  *          (+) Counter overflow/underflow
-  *          (+) Setting the UG bit
-  *          (+) Update generation through the slave mode controller
-  * @retval None
-  */
-#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
-      ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
-
-/**
-  * @brief  Sets the TIM Capture x input polarity on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__: TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __POLARITY__: Polarity for TIx source   
-  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
-  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
-  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
-  * @note  The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized  for TIM Channel 4.     
-  * @retval None
-  */
-#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
-        do{                                                                     \
-          TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
-          TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
-        }while(0)
-
-/**
-  * @}
-  */
-
-/* Include TIM HAL Extension module */
-#include "stm32f1xx_hal_tim_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group1
- * @{
- */
-/* Time Base functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group2
- * @{
- */
-/* Timer Output Compare functions **********************************************/
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group3
- * @{
- */
-/* Timer PWM functions *********************************************************/
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group4
- * @{
- */
-/* Timer Input Capture functions ***********************************************/
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group5
- * @{
- */
-/* Timer One Pulse functions ***************************************************/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group6
- * @{
- */
-/* Timer Encoder functions *****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig);
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group7
- * @{
- */
-/* Interrupt Handler functions  **********************************************/
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group8
- * @{
- */
-/* Control functions  *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
-                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
-                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group9
- * @{
- */
-/* Callback in non blocking modes (Interrupt and DMA) *************************/
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group10
- * @{
- */
-/* Peripheral State functions  **************************************************/
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_TIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_tim_ex.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,312 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_tim_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of TIM HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_TIM_EX_H
-#define __STM32F1xx_HAL_TIM_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup TIMEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup TIMEx_Exported_Types TIMEx Exported Types
-  * @{
-  */
-
-
-/** 
-  * @brief  TIM Hall sensor Configuration Structure definition  
-  */
-
-typedef struct
-{
-                                  
-  uint32_t IC1Polarity;            /*!< Specifies the active edge of the input signal.
-                                        This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-                                                                   
-  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
-                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-                                  
-  uint32_t IC1Filter;           /*!< Specifies the input capture filter.
-                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  
-  uint32_t Commutation_Delay;  /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
-                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */                              
-} TIM_HallSensor_InitTypeDef;
-
-
-#if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
-    defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
-    defined (STM32F105xC) || defined (STM32F107xC)
-
-/** 
-  * @brief  TIM Break and Dead time configuration Structure definition  
-  */ 
-typedef struct
-{
-  uint32_t OffStateRunMode;       /*!< TIM off state in run mode
-                                     This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
-  uint32_t OffStateIDLEMode;      /*!< TIM off state in IDLE mode
-                                     This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
-  uint32_t LockLevel;             /*!< TIM Lock level
-                                     This parameter can be a value of @ref TIM_Lock_level */                             
-  uint32_t DeadTime;              /*!< TIM dead Time 
-                                     This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
-  uint32_t BreakState;            /*!< TIM Break State 
-                                     This parameter can be a value of @ref TIM_Break_Input_enable_disable */
-  uint32_t BreakPolarity;         /*!< TIM Break input polarity 
-                                     This parameter can be a value of @ref TIM_Break_Polarity */
-  uint32_t AutomaticOutput;       /*!< TIM Automatic Output Enable state 
-                                     This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */           
-} TIM_BreakDeadTimeConfigTypeDef;
-
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) ||                                                 */
-       /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
-       /* defined(STM32F105xC) || defined(STM32F107xC)                                                    */
-
-/** 
-  * @brief  TIM Master configuration Structure definition  
-  */ 
-typedef struct {
-  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection 
-                                      This parameter can be a value of @ref TIM_Master_Mode_Selection */ 
-  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection 
-                                      This parameter can be a value of @ref TIM_Master_Slave_Mode */
-}TIM_MasterConfigTypeDef;
-
-/**
-  * @}
-  */ 
-
-/* Exported constants --------------------------------------------------------*/
-#if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
-    defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
-    defined (STM32F105xC) || defined (STM32F107xC)
-/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
-  * @{
-  */
-    
-/** @defgroup TIMEx_Clock_Filter TIMEx Clock Filter
-  * @{
-  */
-#define IS_TIM_DEADTIME(DEADTIME)      ((DEADTIME) <= 0xFF)          /*!< BreakDead Time */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) ||                                                 */
-       /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
-       /* defined(STM32F105xC) || defined(STM32F107xC)                                                    */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIMEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group1
-  * @{
- */
-/* Timer Hall Sensor functions  **********************************************/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
-
-void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
-
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-#if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
-    defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
-    defined (STM32F105xC) || defined (STM32F107xC)
-
-/** @addtogroup TIMEx_Exported_Functions_Group2
- * @{
- */
-/* Timer Complementary Output Compare functions  *****************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group3
- * @{
- */
-/* Timer Complementary PWM functions  ****************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group4
- * @{
- */
-/* Timer Complementary One Pulse functions  **********************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/**
-  * @}
-  */
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) ||                                                 */
-       /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
-       /* defined(STM32F105xC) || defined(STM32F107xC)                                                    */
-
-/** @addtogroup TIMEx_Exported_Functions_Group5
- * @{
- */
-/* Extended Control functions  ************************************************/
-#if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
-    defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
-    defined (STM32F105xC) || defined (STM32F107xC)
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) ||                                                 */
-       /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
-       /* defined(STM32F105xC) || defined(STM32F107xC)                                                    */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group6
-  * @{
-  */
-/* Extension Callback *********************************************************/
-void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-#if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
-    defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
-    defined (STM32F105xC) || defined (STM32F107xC)
-/** @addtogroup TIMEx_Exported_Functions_Group7
-  * @{
-  */
-/* Extension Peripheral State functions  **************************************/
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) ||                                                 */
-       /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
-       /* defined(STM32F105xC) || defined(STM32F107xC)                                                    */
-
-/**
-  * @}
-  */ 
-/* End of exported functions -------------------------------------------------*/
-
-/* Private functions----------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
-* @{
-*/
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
-/**
-* @}
-*/ 
-/* End of private functions --------------------------------------------------*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F1xx_HAL_TIM_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_uart.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,751 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_uart.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of UART HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_UART_H
-#define __STM32F1xx_HAL_UART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup UART
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup UART_Exported_Types UART Exported Types
-  * @{
-  */ 
-
-
-/** 
-  * @brief UART Init Structure definition
-  */ 
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
-                                           The baud rate is computed using the following formula:
-                                           - IntegerDivider = ((PCLKx) / (16 * (huart->Init.BaudRate)))
-                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref UART_Word_Length */
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref UART_Stop_Bits */
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref UART_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits). */
- 
-  uint32_t Mode;                      /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref UART_Mode */
-
-  uint32_t HwFlowCtl;                 /*!< Specifies wether the hardware flow control mode is enabled
-                                           or disabled.
-                                           This parameter can be a value of @ref UART_Hardware_Flow_Control */
-  
-  uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
-                                           This parameter can be a value of @ref UART_Over_Sampling. This feature is not available 
-                                           on STM32F1xx family, so OverSampling parameter should always be set to 16. */ 
-}UART_InitTypeDef;
-
-/** 
-  * @brief HAL UART State structures definition  
-  */ 
-typedef enum
-{
-  HAL_UART_STATE_RESET             = 0x00,    /*!< Peripheral is not initialized                      */
-  HAL_UART_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
-  HAL_UART_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */
-  HAL_UART_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */
-  HAL_UART_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
-  HAL_UART_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
-  HAL_UART_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
-  HAL_UART_STATE_ERROR             = 0x04     /*!< Error                                              */
-}HAL_UART_StateTypeDef;
-
-
-/** 
-  * @brief  UART handle Structure definition  
-  */  
-typedef struct
-{
-  USART_TypeDef                 *Instance;        /*!< UART registers base address        */
-
-  UART_InitTypeDef              Init;             /*!< UART communication parameters      */
-
-  uint8_t                       *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */
-
-  uint16_t                      TxXferSize;       /*!< UART Tx Transfer size              */
-
-  uint16_t                      TxXferCount;      /*!< UART Tx Transfer Counter           */
-
-  uint8_t                       *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */
-
-  uint16_t                      RxXferSize;       /*!< UART Rx Transfer size              */
-
-  uint16_t                      RxXferCount;      /*!< UART Rx Transfer Counter           */  
-
-  DMA_HandleTypeDef             *hdmatx;          /*!< UART Tx DMA Handle parameters      */
-
-  DMA_HandleTypeDef             *hdmarx;          /*!< UART Rx DMA Handle parameters      */
-
-  HAL_LockTypeDef               Lock;             /*!< Locking object                     */
-
-  __IO HAL_UART_StateTypeDef    State;            /*!< UART communication state           */
-  
-  __IO uint32_t                 ErrorCode;        /*!< UART Error code                    */
-
-}UART_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UART_Exported_Constants UART Exported constants
-  * @{
-  */
-
-/** @defgroup UART_Error_Codes   UART Error Codes
-  * @{
-  */
-
-#define HAL_UART_ERROR_NONE      ((uint32_t)0x00)    /*!< No error            */
-#define HAL_UART_ERROR_PE        ((uint32_t)0x01)    /*!< Parity error        */
-#define HAL_UART_ERROR_NE        ((uint32_t)0x02)    /*!< Noise error         */
-#define HAL_UART_ERROR_FE        ((uint32_t)0x04)    /*!< frame error         */
-#define HAL_UART_ERROR_ORE       ((uint32_t)0x08)    /*!< Overrun error       */
-#define HAL_UART_ERROR_DMA       ((uint32_t)0x10)    /*!< DMA transfer error  */
-  
-/**
-  * @}
-  */
-
-
-
-
-/** @defgroup UART_Word_Length   UART Word Length
-  * @{
-  */
-#define UART_WORDLENGTH_8B                  ((uint32_t)0x00000000)
-#define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Stop_Bits   UART Number of Stop Bits
-  * @{
-  */
-#define UART_STOPBITS_1                     ((uint32_t)0x00000000)
-#define UART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
-/**
-  * @}
-  */ 
-
-/** @defgroup UART_Parity  UART Parity
-  * @{
-  */ 
-#define UART_PARITY_NONE                    ((uint32_t)0x00000000)
-#define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
-#define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
-/**
-  * @}
-  */ 
-
-/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
-  * @{
-  */ 
-#define UART_HWCONTROL_NONE                  ((uint32_t)0x00000000)
-#define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)
-#define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)
-#define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-/**
-  * @}
-  */
-
-/** @defgroup UART_Mode UART Transfer Mode
-  * @{
-  */ 
-#define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)
-#define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)
-#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-
-/**
-  * @}
-  */
-    
- /** @defgroup UART_State  UART State
-  * @{
-  */ 
-#define UART_STATE_DISABLE                  ((uint32_t)0x00000000)
-#define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Over_Sampling UART Over Sampling
-  * @{
-  */
-#define UART_OVERSAMPLING_16                    ((uint32_t)0x00000000)
-/**
-  * @}
-  */
-
-/** @defgroup UART_LIN_Break_Detection_Length  UART LIN Break Detection Length
-  * @{
-  */  
-#define UART_LINBREAKDETECTLENGTH_10B      ((uint32_t)0x00000000)
-#define UART_LINBREAKDETECTLENGTH_11B      ((uint32_t)USART_CR2_LBDL)
-/**
-  * @}
-  */
-
-/** @defgroup UART_WakeUp_functions UART Wakeup Functions
-  * @{
-  */
-#define UART_WAKEUPMETHOD_IDLELINE                ((uint32_t)0x00000000)
-#define UART_WAKEUPMETHOD_ADDRESSMARK             ((uint32_t)USART_CR1_WAKE)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Flags   UART FLags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the SR register
-  * @{
-  */
-#define UART_FLAG_CTS                       ((uint32_t)USART_SR_CTS)
-#define UART_FLAG_LBD                       ((uint32_t)USART_SR_LBD)
-#define UART_FLAG_TXE                       ((uint32_t)USART_SR_TXE)
-#define UART_FLAG_TC                        ((uint32_t)USART_SR_TC)
-#define UART_FLAG_RXNE                      ((uint32_t)USART_SR_RXNE)
-#define UART_FLAG_IDLE                      ((uint32_t)USART_SR_IDLE)
-#define UART_FLAG_ORE                       ((uint32_t)USART_SR_ORE)
-#define UART_FLAG_NE                        ((uint32_t)USART_SR_NE)
-#define UART_FLAG_FE                        ((uint32_t)USART_SR_FE)
-#define UART_FLAG_PE                        ((uint32_t)USART_SR_PE)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Interrupt_definition  UART Interrupt Definitions
-  *        Elements values convention: 0xY000XXXX
-  *           - XXXX  : Interrupt mask (16 bits) in the Y register
-  *           - Y  : Interrupt source register (2bits)
-  *                 - 0001: CR1 register
-  *                 - 0010: CR2 register
-  *                 - 0011: CR3 register
-  *
-  * @{
-  */ 
-
-#define UART_IT_PE                       ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
-#define UART_IT_TXE                      ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
-#define UART_IT_TC                       ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
-#define UART_IT_RXNE                     ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
-#define UART_IT_IDLE                     ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
-
-#define UART_IT_LBD                      ((uint32_t)(UART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
-
-#define UART_IT_CTS                      ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
-#define UART_IT_ERR                      ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-    
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup UART_Exported_Macros UART Exported Macros
-  * @{
-  */
-
-
-/** @brief Reset UART handle state
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
-
-/** @brief  Flush the UART DR register 
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  */
-#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-
-/** @brief  Check whether the specified UART flag is set or not.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __FLAG__: specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)
-  *            @arg UART_FLAG_LBD:  LIN Break detection flag
-  *            @arg UART_FLAG_TXE:  Transmit data register empty flag
-  *            @arg UART_FLAG_TC:   Transmission Complete flag
-  *            @arg UART_FLAG_RXNE: Receive data register not empty flag
-  *            @arg UART_FLAG_IDLE: Idle Line detection flag
-  *            @arg UART_FLAG_ORE:  OverRun Error flag
-  *            @arg UART_FLAG_NE:   Noise Error flag
-  *            @arg UART_FLAG_FE:   Framing Error flag
-  *            @arg UART_FLAG_PE:   Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))   
-
-/** @brief  Clear the specified UART pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __FLAG__: specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
-  *            @arg UART_FLAG_LBD:  LIN Break detection flag.
-  *            @arg UART_FLAG_TC:   Transmission Complete flag.
-  *            @arg UART_FLAG_RXNE: Receive data register not empty flag.
-  *   
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
-  *          error) and IDLE (Idle line detected) flags are cleared by software 
-  *          sequence: a read operation to USART_SR register followed by a read
-  *          operation to USART_DR register.
-  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to 
-  *          USART_SR register followed by a write operation to USART_DR register.
-  * @note   TXE flag is cleared only by a write to the USART_DR register.
-  *   
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief  Clear the UART PE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \
-do{                                         \
-  __IO uint32_t tmpreg;                     \
-  tmpreg = (__HANDLE__)->Instance->SR;      \
-  tmpreg = (__HANDLE__)->Instance->DR;      \
-  UNUSED(tmpreg);                           \
-}while(0)
-
-
-
-/** @brief  Clear the UART FE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the UART NE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the UART ORE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the UART IDLE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-                                                 
-/** @brief  Enable the specified UART interrupt.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __INTERRUPT__: specifies the UART interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg UART_IT_CTS:  CTS change interrupt
-  *            @arg UART_IT_LBD:  LIN Break detection interrupt
-  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg UART_IT_TC:   Transmission complete interrupt
-  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg UART_IT_PE:   Parity Error interrupt
-  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
-
-
-/** @brief  Disable the specified UART interrupt.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __INTERRUPT__: specifies the UART interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg UART_IT_CTS:  CTS change interrupt
-  *            @arg UART_IT_LBD:  LIN Break detection interrupt
-  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg UART_IT_TC:   Transmission complete interrupt
-  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg UART_IT_PE:   Parity Error interrupt
-  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
-    
-/** @brief  Check whether the specified UART interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __IT__: specifies the UART interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
-  *            @arg UART_IT_LBD: LIN Break detection interrupt
-  *            @arg UART_IT_TXE: Transmit Data Register empty interrupt
-  *            @arg UART_IT_TC:  Transmission complete interrupt
-  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg UART_IT_ERR: Error interrupt
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == UART_CR2_REG_INDEX)? \
-                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
-
-/** @brief  Enable CTS flow control 
-  *         This macro allows to enable CTS hardware flow control for a given UART instance, 
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).                                                                                                                  
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be any USARTx (supporting the HW Flow control feature).
-  *         It is used to select the USART peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
-  do{                                                      \
-    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
-    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
-  } while(0)
-
-/** @brief  Disable CTS flow control 
-  *         This macro allows to disable CTS hardware flow control for a given UART instance, 
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). 
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be any USARTx (supporting the HW Flow control feature).
-  *         It is used to select the USART peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
-  do{                                                       \
-    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
-    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
-  } while(0)
-
-/** @brief  Enable RTS flow control 
-  *         This macro allows to enable RTS hardware flow control for a given UART instance, 
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). 
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be any USARTx (supporting the HW Flow control feature).
-  *         It is used to select the USART peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
-  do{                                                     \
-    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
-    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
-  } while(0)
-
-/** @brief  Disable RTS flow control 
-  *         This macro allows to disable RTS hardware flow control for a given UART instance, 
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). 
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be any USARTx (supporting the HW Flow control feature).
-  *         It is used to select the USART peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
-  do{                                                      \
-    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
-    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
-  } while(0)
-
-
-/** @brief  Enable UART
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */ 
-#define __HAL_UART_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
-
-/** @brief  Disable UART
-  *         UART Handle selects the USARTx or UARTy peripheral 
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_UART_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
-
-/**
-  * @}
-  */
-
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup UART_Private_Macros   UART Private Macros
-  * @{
-  */
-
-#define UART_CR1_REG_INDEX               1    
-#define UART_CR2_REG_INDEX               2    
-#define UART_CR3_REG_INDEX               3    
-
-#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_)         (((_PCLK_)*25)/(4*(_BAUD_)))
-#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_)     (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100)
-#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_)     (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-/* UART BRR = mantissa + overflow + fraction
-            = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0F) */
-#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_)            (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4) + \
-                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0)) + \
-                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F))
-#define IS_UART_WORD_LENGTH(LENGTH)       (((LENGTH) == UART_WORDLENGTH_8B) || \
-                                           ((LENGTH) == UART_WORDLENGTH_9B))
-#define IS_UART_LIN_WORD_LENGTH(LENGTH)   ((LENGTH) == UART_WORDLENGTH_8B)
-
-#define IS_UART_STOPBITS(STOPBITS)     (((STOPBITS) == UART_STOPBITS_1) || \
-                                        ((STOPBITS) == UART_STOPBITS_2))
-
-#define IS_UART_PARITY(PARITY)         (((PARITY) == UART_PARITY_NONE) || \
-                                        ((PARITY) == UART_PARITY_EVEN) || \
-                                        ((PARITY) == UART_PARITY_ODD))
-
-#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
-                                       (((CONTROL) == UART_HWCONTROL_NONE) || \
-                                        ((CONTROL) == UART_HWCONTROL_RTS) || \
-                                        ((CONTROL) == UART_HWCONTROL_CTS) || \
-                                        ((CONTROL) == UART_HWCONTROL_RTS_CTS))
-
-#define IS_UART_MODE(MODE)             ((((MODE) & (~((uint32_t)UART_MODE_TX_RX))) == 0x00) && \
-                                        ((MODE) != (uint32_t)0x00000000))
-
-#define IS_UART_STATE(STATE)           (((STATE) == UART_STATE_DISABLE) || \
-                                        ((STATE) == UART_STATE_ENABLE))
-
-#define IS_UART_OVERSAMPLING(SAMPLING)      ((SAMPLING) == UART_OVERSAMPLING_16)
-#define IS_UART_LIN_OVERSAMPLING(SAMPLING)  ((SAMPLING) == UART_OVERSAMPLING_16)
-
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
-                                                 ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
-
-#define IS_UART_WAKEUPMETHOD(WAKEUP)   (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
-                                        ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
-
-                                
-/** Check UART Baud rate
-  *         __BAUDRATE__: Baudrate specified by the user
-  *         The maximum Baud Rate is derived from the maximum clock on APB (i.e. 72 MHz) 
-  *         divided by the smallest oversampling used on the USART (i.e. 16) 
-  * Retrun : TRUE or FALSE
-  */
-#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
-
-/** Check UART Node Address
-  *         __ADDRESS__: UART Node address specified by the user
-  *         UART Node address is used in Multi processor communication for wakeup 
-  *         with address mark detection. 
-  *         This parameter must be a number between Min_Data = 0 and Max_Data = 15 
-  * Return : TRUE or FALSE
-  */
-#define IS_UART_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
-
-/** UART interruptions flag mask
-  */ 
-#define UART_IT_MASK  ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
-                                  USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup UART_Exported_Functions UART Exported Functions
-  * @{
-  */
-  
-/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
-HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
-void HAL_UART_MspInit(UART_HandleTypeDef *huart);
-void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group2 IO operation functions 
-  * @{
-  */
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
-void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Errors functions 
-  * @{
-  */
-
-/* Peripheral State and Errors functions  **************************************************/
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
-uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_UART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_usart.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,617 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_usart.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of USART HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_USART_H
-#define __STM32F1xx_HAL_USART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup USART
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup USART_Exported_Types USART Exported Types
-  * @{
-  */ 
-
-
-/** 
-  * @brief USART Init Structure definition
-  */ 
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
-                                           The baud rate is computed using the following formula:
-                                           - IntegerDivider = ((PCLKx) / (16 * (husart->Init.BaudRate)))
-                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref USART_Word_Length */
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref USART_Stop_Bits */
-
-  uint32_t Parity;                   /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref USART_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits). */
- 
-  uint32_t Mode;                      /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref USART_Mode */
-
-  uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
-                                           This parameter can be a value of @ref USART_Clock_Polarity */
-
-  uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
-                                           This parameter can be a value of @ref USART_Clock_Phase */
-
-  uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
-                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
-                                           This parameter can be a value of @ref USART_Last_Bit */
-}USART_InitTypeDef;
-
-/** 
-  * @brief HAL State structures definition
-  */ 
-typedef enum
-{
-  HAL_USART_STATE_RESET             = 0x00,    /*!< Peripheral is not initialized   */
-  HAL_USART_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
-  HAL_USART_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing */   
-  HAL_USART_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing */ 
-  HAL_USART_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing */
-  HAL_USART_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission Reception process is ongoing */
-  HAL_USART_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
-  HAL_USART_STATE_ERROR             = 0x04     /*!< Error */
-}HAL_USART_StateTypeDef;
-
-
-/** 
-  * @brief  USART handle Structure definition  
-  */  
-typedef struct
-{
-  USART_TypeDef                 *Instance;        /*!< USART registers base address        */
-  
-  USART_InitTypeDef              Init;            /*!< Usart communication parameters      */
-  
-  uint8_t                       *pTxBuffPtr;      /*!< Pointer to Usart Tx transfer Buffer */
-  
-  uint16_t                       TxXferSize;      /*!< Usart Tx Transfer size              */
-  
-  __IO uint16_t                  TxXferCount;     /*!< Usart Tx Transfer Counter           */
-  
-  uint8_t                       *pRxBuffPtr;      /*!< Pointer to Usart Rx transfer Buffer */
-  
-  uint16_t                       RxXferSize;      /*!< Usart Rx Transfer size              */
- 
-  __IO uint16_t                  RxXferCount;     /*!< Usart Rx Transfer Counter           */  
-  
-  DMA_HandleTypeDef             *hdmatx;          /*!< Usart Tx DMA Handle parameters      */
-    
-  DMA_HandleTypeDef             *hdmarx;          /*!< Usart Rx DMA Handle parameters      */
-  
-  HAL_LockTypeDef                Lock;            /*!< Locking object                      */
-  
-  __IO HAL_USART_StateTypeDef    State;           /*!< Usart communication state           */
-  
-  __IO uint32_t                  ErrorCode;       /*!< USART Error code                    */
-  
-}USART_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_Exported_Constants USART Exported constants
-  * @{
-  */
-
-/** @defgroup USART_Error_Codes USART Error Codes
-  * @{
-  */
-#define HAL_USART_ERROR_NONE      ((uint32_t)0x00)    /*!< No error            */
-#define HAL_USART_ERROR_PE        ((uint32_t)0x01)    /*!< Parity error        */
-#define HAL_USART_ERROR_NE        ((uint32_t)0x02)    /*!< Noise error         */
-#define HAL_USART_ERROR_FE        ((uint32_t)0x04)    /*!< frame error         */
-#define HAL_USART_ERROR_ORE       ((uint32_t)0x08)    /*!< Overrun error       */
-#define HAL_USART_ERROR_DMA       ((uint32_t)0x10)     /*!< DMA transfer error  */
-/**
-  * @}
-  */
-
-/** @defgroup USART_Word_Length USART Word Length
-  * @{
-  */
-#define USART_WORDLENGTH_8B             ((uint32_t)0x00000000)
-#define USART_WORDLENGTH_9B             ((uint32_t)USART_CR1_M)
-/**
-  * @}
-  */
-
-/** @defgroup USART_Stop_Bits USART Number of Stop Bits
-  * @{
-  */
-#define USART_STOPBITS_1                ((uint32_t)0x00000000)
-#define USART_STOPBITS_0_5              ((uint32_t)USART_CR2_STOP_0)
-#define USART_STOPBITS_2                ((uint32_t)USART_CR2_STOP_1)
-#define USART_STOPBITS_1_5              ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Parity USART Parity
-  * @{
-  */ 
-#define USART_PARITY_NONE               ((uint32_t)0x00000000)
-#define USART_PARITY_EVEN               ((uint32_t)USART_CR1_PCE)
-#define USART_PARITY_ODD                ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Mode USART Mode
-  * @{
-  */ 
-#define USART_MODE_RX                   ((uint32_t)USART_CR1_RE)
-#define USART_MODE_TX                   ((uint32_t)USART_CR1_TE)
-#define USART_MODE_TX_RX                ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-
-/**
-  * @}
-  */
-    
-/** @defgroup USART_Clock USART Clock
-  * @{
-  */ 
-#define USART_CLOCK_DISABLE             ((uint32_t)0x00000000)
-#define USART_CLOCK_ENABLE              ((uint32_t)USART_CR2_CLKEN)
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Clock_Polarity USART Clock Polarity
-  * @{
-  */
-#define USART_POLARITY_LOW              ((uint32_t)0x00000000)
-#define USART_POLARITY_HIGH             ((uint32_t)USART_CR2_CPOL)
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Clock_Phase USART Clock Phase
-  * @{
-  */
-#define USART_PHASE_1EDGE               ((uint32_t)0x00000000)
-#define USART_PHASE_2EDGE               ((uint32_t)USART_CR2_CPHA)
-/**
-  * @}
-  */
-
-/** @defgroup USART_Last_Bit USART Last Bit
-  * @{
-  */
-#define USART_LASTBIT_DISABLE           ((uint32_t)0x00000000)
-#define USART_LASTBIT_ENABLE            ((uint32_t)USART_CR2_LBCL)
-/**
-  * @}
-  */
-
-/** @defgroup USART_NACK_State USART NACK State
-  * @{
-  */
-#define USART_NACK_ENABLE               ((uint32_t)USART_CR3_NACK)
-#define USART_NACK_DISABLE              ((uint32_t)0x00000000)
-/**
-  * @}
-  */
-
-/** @defgroup USART_Flags USART Flags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the SR register
-  * @{
-  */
-
-#define USART_FLAG_CTS                  ((uint32_t)USART_SR_CTS)
-#define USART_FLAG_LBD                  ((uint32_t)USART_SR_LBD)
-#define USART_FLAG_TXE                  ((uint32_t)USART_SR_TXE)
-#define USART_FLAG_TC                   ((uint32_t)USART_SR_TC)
-#define USART_FLAG_RXNE                 ((uint32_t)USART_SR_RXNE)
-#define USART_FLAG_IDLE                 ((uint32_t)USART_SR_IDLE)
-#define USART_FLAG_ORE                  ((uint32_t)USART_SR_ORE)
-#define USART_FLAG_NE                   ((uint32_t)USART_SR_NE)
-#define USART_FLAG_FE                   ((uint32_t)USART_SR_FE)
-#define USART_FLAG_PE                   ((uint32_t)USART_SR_PE)
-/**
-  * @}
-  */
-
-/** @defgroup USART_Interrupt_definition USART Interrupts Definition
-  *        Elements values convention: 0xY000XXXX
-  *           - XXXX  : Interrupt mask (16 bits) in the Y register
-  *           - Y  : Interrupt source register (4bits)
-  *                 - 0001: CR1 register
-  *                 - 0010: CR2 register
-  *                 - 0011: CR3 register
-  *
-  * @{
-  */
-
-#define USART_IT_PE                     ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
-#define USART_IT_TXE                    ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
-#define USART_IT_TC                     ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
-#define USART_IT_RXNE                   ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
-#define USART_IT_IDLE                   ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
-
-#define USART_IT_LBD                    ((uint32_t)(USART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
-
-#define USART_IT_CTS                    ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
-#define USART_IT_ERR                    ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-    
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup USART_Exported_Macros USART Exported Macros
-  * @{
-  */
-
-
-/** @brief Reset USART handle state
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
-
-/** @brief  Check whether the specified USART flag is set or not.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __FLAG__: specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg USART_FLAG_TXE:  Transmit data register empty flag
-  *            @arg USART_FLAG_TC:   Transmission Complete flag
-  *            @arg USART_FLAG_RXNE: Receive data register not empty flag
-  *            @arg USART_FLAG_IDLE: Idle Line detection flag
-  *            @arg USART_FLAG_ORE:  OverRun Error flag
-  *            @arg USART_FLAG_NE:   Noise Error flag
-  *            @arg USART_FLAG_FE:   Framing Error flag
-  *            @arg USART_FLAG_PE:   Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-
-#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the specified USART pending flags.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __FLAG__: specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg USART_FLAG_TC:   Transmission Complete flag.
-  *            @arg USART_FLAG_RXNE: Receive data register not empty flag.
-  *   
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
-  *          error) and IDLE (Idle line detected) flags are cleared by software 
-  *          sequence: a read operation to USART_SR register followed by a read
-  *          operation to USART_DR register.
-  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to 
-  *          USART_SR register followed by a write operation to USART_DR register.
-  * @note   TXE flag is cleared only by a write to the USART_DR register.
-  *   
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief  Clear the USART PE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \
-do{                                          \
-  __IO uint32_t tmpreg;                      \
-  tmpreg = (__HANDLE__)->Instance->SR;       \
-  tmpreg = (__HANDLE__)->Instance->DR;       \
-  UNUSED(tmpreg);                            \
-}while(0)
-
-
-/** @brief  Clear the USART FE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the USART NE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the USART ORE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the USART IDLE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Enable the specified Usart interrupts.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __INTERRUPT__: specifies the USART interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg USART_IT_TC:   Transmission complete interrupt
-  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg USART_IT_IDLE: Idle line detection interrupt
-  *            @arg USART_IT_PE:   Parity Error interrupt
-  *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
-                                                            (((__INTERRUPT__) >> 28) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & USART_IT_MASK)): \
-                                                            ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
-
-
-/** @brief  Disable the specified Usart interrupts.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __INTERRUPT__: specifies the USART interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg USART_IT_TC:   Transmission complete interrupt
-  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg USART_IT_IDLE: Idle line detection interrupt
-  *            @arg USART_IT_PE:   Parity Error interrupt
-  *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
-                                                            (((__INTERRUPT__) >> 28) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
-                                                            ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
-
-
-    
-/** @brief  Check whether the specified Usart interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __IT__: specifies the USART interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg USART_IT_TXE: Transmit Data Register empty interrupt
-  *            @arg USART_IT_TC:  Transmission complete interrupt
-  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg USART_IT_IDLE: Idle line detection interrupt
-  *            @arg USART_IT_ERR: Error interrupt
-  *            @arg USART_IT_PE: Parity Error interrupt
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == USART_CR2_REG_INDEX)? \
-                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
-
-/** @brief  Enable USART
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */ 
-#define __HAL_USART_ENABLE(__HANDLE__)               SET_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE)) 
-
-/** @brief  Disable USART
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */ 
-#define __HAL_USART_DISABLE(__HANDLE__)              CLEAR_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE)) 
- 
-
-/**
-  * @}
-  */
-
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup USART_Private_Macros   USART Private Macros
-  * @{
-  */
-
-#define USART_CR1_REG_INDEX             1    
-#define USART_CR2_REG_INDEX             2    
-#define USART_CR3_REG_INDEX             3    
-
-#define USART_DIV(__PCLK__, __BAUD__)                (((__PCLK__)*25)/(4*(__BAUD__)))
-#define USART_DIVMANT(__PCLK__, __BAUD__)            (USART_DIV((__PCLK__), (__BAUD__))/100)
-#define USART_DIVFRAQ(__PCLK__, __BAUD__)            (((USART_DIV((__PCLK__), (__BAUD__)) - (USART_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100)
-#define USART_BRR(__PCLK__, __BAUD__)                ((USART_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(USART_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F))
-
-/** Check USART Baud rate
-  *      __BAUDRATE__: Baudrate specified by the user
-  *                    The maximum Baud Rate is derived from the maximum clock on APB (i.e. 72 MHz) 
-  *                    divided by the smallest oversampling used on the USART (i.e. 16) 
-  * return : TRUE or FALSE
-  */ 
-#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
-
-#define IS_USART_WORD_LENGTH(LENGTH)    (((LENGTH) == USART_WORDLENGTH_8B) || \
-                                         ((LENGTH) == USART_WORDLENGTH_9B))
-
-#define IS_USART_STOPBITS(STOPBITS)     (((STOPBITS) == USART_STOPBITS_1) || \
-                                         ((STOPBITS) == USART_STOPBITS_0_5) || \
-                                         ((STOPBITS) == USART_STOPBITS_1_5) || \
-                                         ((STOPBITS) == USART_STOPBITS_2))
-
-#define IS_USART_PARITY(PARITY)         (((PARITY) == USART_PARITY_NONE) || \
-                                         ((PARITY) == USART_PARITY_EVEN) || \
-                                         ((PARITY) == USART_PARITY_ODD))
-
-#define IS_USART_MODE(MODE)             ((((MODE) & (~((uint32_t)USART_MODE_TX_RX))) == 0x00) && ((MODE) != (uint32_t)0x00000000))
-
-#define IS_USART_CLOCK(CLOCK)           (((CLOCK) == USART_CLOCK_DISABLE) || \
-                                         ((CLOCK) == USART_CLOCK_ENABLE))
-
-#define IS_USART_POLARITY(CPOL)         (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
-
-#define IS_USART_PHASE(CPHA)            (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
-
-#define IS_USART_LASTBIT(LASTBIT)       (((LASTBIT) == USART_LASTBIT_DISABLE) || \
-                                         ((LASTBIT) == USART_LASTBIT_ENABLE))
-
-#define IS_USART_NACK_STATE(NACK)       (((NACK) == USART_NACK_ENABLE) || \
-                                         ((NACK) == USART_NACK_DISABLE))
-
-/** USART interruptions flag mask
-  * 
-  */ 
-#define USART_IT_MASK  ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
-                                   USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup USART_Exported_Functions USART Exported Functions
-  * @{
-  */
-  
-/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ******************************/
-HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
-
-/**
-  * @}
-  */
-
-/** @addtogroup USART_Exported_Functions_Group2 IO operation functions 
-  * @{
-  */
-
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
-void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
-void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
-
-/**
-  * @}
-  */
-
-/* Peripheral Control functions ***********************************************/
-
-/** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Errors functions 
-  * @{
-  */
-
-/* Peripheral State and Error functions ***************************************/
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
-uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_USART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_hal_wwdg.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,332 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_wwdg.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of WWDG HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_WWDG_H
-#define __STM32F1xx_HAL_WWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup WWDG
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Types WWDG Exported Types
-  * @{
-  */
-
-/**
-  * @brief  WWDG HAL State Structure definition
-  */
-typedef enum
-{
-  HAL_WWDG_STATE_RESET     = 0x00,  /*!< WWDG not yet initialized or disabled */
-  HAL_WWDG_STATE_READY     = 0x01,  /*!< WWDG initialized and ready for use   */
-  HAL_WWDG_STATE_BUSY      = 0x02,  /*!< WWDG internal process is ongoing     */
-  HAL_WWDG_STATE_TIMEOUT   = 0x03,  /*!< WWDG timeout state                   */
-  HAL_WWDG_STATE_ERROR     = 0x04   /*!< WWDG error state                     */
-}HAL_WWDG_StateTypeDef;
-
-/** 
-  * @brief  WWDG Init structure definition  
-  */ 
-typedef struct
-{
-  uint32_t Prescaler;  /*!< Specifies the prescaler value of the WWDG.
-                            This parameter can be a value of @ref WWDG_Prescaler */
-  
-  uint32_t Window;     /*!< Specifies the WWDG window value to be compared to the downcounter.
-                            This parameter must be a number lower than Max_Data = 0x80 */ 
-  
-  uint32_t Counter;    /*!< Specifies the WWDG free-running downcounter value.
-                            This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
-
-}WWDG_InitTypeDef;
-
-/** 
-  * @brief  WWDG handle Structure definition  
-  */ 
-typedef struct
-{
-  WWDG_TypeDef                 *Instance;  /*!< Register base address    */
-  
-  WWDG_InitTypeDef             Init;       /*!< WWDG required parameters */
-  
-  HAL_LockTypeDef              Lock;       /*!< WWDG locking object      */
-  
-  __IO HAL_WWDG_StateTypeDef   State;      /*!< WWDG communication state */
-  
-}WWDG_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
-  * @{
-  */
-
-/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
-  * @{
-  */ 
-#define WWDG_IT_EWI                       WWDG_CFR_EWI  /*!< Early wakeup interrupt */
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Flag_definition WWDG Flag definition
-  * @brief WWDG Flag definition
-  * @{
-  */ 
-#define WWDG_FLAG_EWIF                    WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Prescaler WWDG Prescaler
-  * @{
-  */ 
-#define WWDG_PRESCALER_1   ((uint32_t)0x00000000)  /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define WWDG_PRESCALER_2                  WWDG_CFR_WDGTB0  /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define WWDG_PRESCALER_4                  WWDG_CFR_WDGTB1  /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define WWDG_PRESCALER_8                  WWDG_CFR_WDGTB  /*!< WWDG counter clock = (PCLK1/4096)/8 */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Private_Macros WWDG Private Macros
-  * @{
-  */
-#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
-                                          ((__PRESCALER__) == WWDG_PRESCALER_2) || \
-                                          ((__PRESCALER__) == WWDG_PRESCALER_4) || \
-                                          ((__PRESCALER__) == WWDG_PRESCALER_8))
-
-#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F)
-
- 
-#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))
-/**
-  * @}
-  */
-
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
-  * @{
-  */
-
-/** @brief Reset WWDG handle state
-  * @param  __HANDLE__: WWDG handle
-  * @retval None
-  */
-#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
-
-/**
-  * @brief  Enables the WWDG peripheral.
-  * @param  __HANDLE__: WWDG handle
-  * @retval None
-  */
-#define __HAL_WWDG_ENABLE(__HANDLE__)             SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
-
-/**
-  * @brief  Disables the WWDG peripheral.
-  * @param  __HANDLE__: WWDG handle
-  * @note   WARNING: This is a dummy macro for HAL code alignment.
-  *         Once enable, WWDG Peripheral cannot be disabled except by a system reset.
-  * @retval None
-  */
-#define __HAL_WWDG_DISABLE(__HANDLE__)                      /* dummy  macro */
-
-/**
-  * @brief  Enables the WWDG early wakeup interrupt.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __INTERRUPT__: specifies the interrupt to enable.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_IT_EWI: Early wakeup interrupt
-  * @note   Once enabled this interrupt cannot be disabled except by a system reset.
-  * @retval None
-  */
-#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
-
-/**
-  * @brief  Disables the WWDG early wakeup interrupt.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __INTERRUPT__: specifies the interrupt to disable.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_IT_EWI: Early wakeup interrupt
-  * @note   WARNING: This is a dummy macro for HAL code alignment. 
-  *         Once enabled this interrupt cannot be disabled except by a system reset.
-  * @retval None
-  */
-#define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__)                   /* dummy  macro */
-
-/**
-  * @brief  Gets the selected WWDG's it status.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __INTERRUPT__: specifies the it to check.
-  *        This parameter can be one of the following values:
-  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
-  * @retval The new state of WWDG_FLAG (SET or RESET).
-  */
-#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)       __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
-
-/** @brief  Clear the WWDG's interrupt pending bits
-  *         bits to clear the selected interrupt pending bits.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
-  */
-#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)     __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
-
-/**
-  * @brief  Gets the selected WWDG's flag status.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
-  * @retval The new state of WWDG_FLAG (SET or RESET).
-  */
-#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief  Clears the WWDG's pending flags.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __FLAG__: specifies the flag to clear.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
-  * @retval None
-  */
-#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief  Checks if the specified WWDG interrupt source is enabled or disabled.
-  * @param  __HANDLE__: WWDG Handle.
-  * @param  __INTERRUPT__: specifies the WWDG interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg WWDG_IT_EWI: Early Wakeup Interrupt
-  * @retval state of __INTERRUPT__ (TRUE or FALSE).
-  */
-#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @}
-  */ 
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup WWDG_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup WWDG_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
-HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
-
-/**
-  * @}
-  */
-  
-/** @addtogroup WWDG_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg);
-HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg);
-HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter);
-void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
-
-/**
-  * @}
-  */
-
-/** @addtogroup WWDG_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State functions  **************************************************/
-HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_WWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_ll_fsmc.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1077 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_ll_fsmc.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of FSMC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_FSMC_H
-#define __STM32F1xx_LL_FSMC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-#if defined(FSMC_BANK1)
-
-/** @addtogroup FSMC_LL
-  * @{
-  */
-
-/** @addtogroup FSMC_LL_Private_Macros
-  * @{
-  */
-
-#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
-                                        ((__BANK__) == FSMC_NORSRAM_BANK2) || \
-                                        ((__BANK__) == FSMC_NORSRAM_BANK3) || \
-                                        ((__BANK__) == FSMC_NORSRAM_BANK4))
-
-#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
-                              ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
-
-#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
-                                    ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
-                                    ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
-
-#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
-                                                 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
-                                                 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
-
-#define IS_FSMC_WRITE_BURST(__BURST__)          (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
-                                                ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
-
-#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
-                                       ((__MODE__) == FSMC_ACCESS_MODE_B) || \
-                                       ((__MODE__) == FSMC_ACCESS_MODE_C) || \
-                                       ((__MODE__) == FSMC_ACCESS_MODE_D))
-
-#define IS_FSMC_NAND_BANK(__BANK__) (((__BANK__) == FSMC_NAND_BANK2) || \
-                                ((__BANK__) == FSMC_NAND_BANK3))
-
-#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
-                                      ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
-
-#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
-                                         ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
-
-#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
-                                 ((__STATE__) == FSMC_NAND_ECC_ENABLE))
-
-#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \
-                                   ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \
-                                   ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
-                                   ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
-                                   ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
-                                   ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
-
-/** @defgroup FSMC_TCLR_Setup_Time FSMC_TCLR_Setup_Time
-  * @{
-  */
-#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_TAR_Setup_Time FSMC_TAR_Setup_Time
-  * @{
-  */
-#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Setup_Time FSMC_Setup_Time
-  * @{
-  */
-#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wait_Setup_Time FSMC_Wait_Setup_Time
-  * @{
-  */
-#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Hold_Setup_Time FSMC_Hold_Setup_Time
-  * @{
-  */
-#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_HiZ_Setup_Time FSMC_HiZ_Setup_Time
-  * @{
-  */
-#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance
-  * @{
-  */
-
-#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance
-  * @{
-  */
-
-#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_NAND_Device_Instance FSMC NAND Device Instance
-  * @{
-  */
-#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_PCCARD_Device_Instance FSMC PCCARD Device Instance
-  * @{
-  */
-#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
-
-/**
-  * @}
-  */
-#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
-                                      ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
-
-#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
-                                             ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
-
-#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
-                                     ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
-
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
-                                                ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
-
-#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
-                                                ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
-
-#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
-                                          ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
-
-#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
-                                         ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
-
-#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
-                                     ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
-
-#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
-
-/** @defgroup FSMC_Data_Latency FSMC Data Latency
-  * @{
-  */
-#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time
-  * @{
-  */
-#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time
-  * @{
-  */
-#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time
-  * @{
-  */
-#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration
-  * @{
-  */
-#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported typedef ----------------------------------------------------------*/
-
-/** @defgroup FSMC_NORSRAM_Exported_typedef FSMC Low Layer Exported Types
-  * @{
-  */
-
-#define FSMC_NORSRAM_TypeDef            FSMC_Bank1_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TypeDef   FSMC_Bank1E_TypeDef
-#define FSMC_NAND_TypeDef               FSMC_Bank2_3_TypeDef
-#define FSMC_PCCARD_TypeDef             FSMC_Bank4_TypeDef
-
-#define FSMC_NORSRAM_DEVICE             FSMC_Bank1
-#define FSMC_NORSRAM_EXTENDED_DEVICE    FSMC_Bank1E
-#define FSMC_NAND_DEVICE                FSMC_Bank2_3
-#define FSMC_PCCARD_DEVICE              FSMC_Bank4
-
-/**
-  * @brief  FSMC_NORSRAM Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
-                                              This parameter can be a value of @ref FSMC_NORSRAM_Bank                     */
-
-  uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
-                                              multiplexed on the data bus or not.
-                                              This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing    */
-
-  uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
-                                              the corresponding memory device.
-                                              This parameter can be a value of @ref FSMC_Memory_Type                      */
-
-  uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
-                                              This parameter can be a value of @ref FSMC_NORSRAM_Data_Width               */
-
-  uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
-                                              valid only with synchronous burst Flash memories.
-                                              This parameter can be a value of @ref FSMC_Burst_Access_Mode                */
-
-  uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
-                                              the Flash memory in burst mode.
-                                              This parameter can be a value of @ref FSMC_Wait_Signal_Polarity             */
-
-  uint32_t WrapMode;                     /*!< Enables or disables the Wrapped burst access mode for Flash
-                                              memory, valid only when accessing Flash memories in burst mode.
-                                              This parameter can be a value of @ref FSMC_Wrap_Mode                        */
-
-  uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
-                                              clock cycle before the wait state or during the wait state,
-                                              valid only when accessing memories in burst mode.
-                                              This parameter can be a value of @ref FSMC_Wait_Timing                      */
-
-  uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FSMC.
-                                              This parameter can be a value of @ref FSMC_Write_Operation                  */
-
-  uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
-                                              signal, valid for Flash memory access in burst mode.
-                                              This parameter can be a value of @ref FSMC_Wait_Signal                      */
-
-  uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
-                                              This parameter can be a value of @ref FSMC_Extended_Mode                    */
-
-  uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
-                                              valid only with asynchronous Flash memories.
-                                              This parameter can be a value of @ref FSMC_AsynchronousWait                 */
-
-  uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
-                                              This parameter can be a value of @ref FSMC_Write_Burst                      */
-
-}FSMC_NORSRAM_InitTypeDef;
-
-/**
-  * @brief  FSMC_NORSRAM Timing parameters structure definition
-  */
-typedef struct
-{
-  uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
-                                              the duration of the address setup time.
-                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
-                                              @note This parameter is not used with synchronous NOR Flash memories.      */
-
-  uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
-                                              the duration of the address hold time.
-                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15.
-                                              @note This parameter is not used with synchronous NOR Flash memories.      */
-
-  uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
-                                              the duration of the data setup time.
-                                              This parameter can be a value between Min_Data = 1 and Max_Data = 255.
-                                              @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
-                                              NOR Flash memories.                                                        */
-
-  uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
-                                              the duration of the bus turnaround.
-                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
-                                              @note This parameter is only used for multiplexed NOR Flash memories.      */
-
-  uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of
-                                              HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
-                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
-                                              accesses.                                                                  */
-
-  uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
-                                              to the memory before getting the first data.
-                                              The parameter value depends on the memory type as shown below:
-                                              - It must be set to 0 in case of a CRAM
-                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
-                                              - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
-                                                with synchronous burst mode enable                                       */
-
-  uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode.
-                                              This parameter can be a value of @ref FSMC_Access_Mode                      */
-
-}FSMC_NORSRAM_TimingTypeDef;
-
-#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
-/**
-  * @brief  FSMC_NAND Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.
-                                        This parameter can be a value of @ref FSMC_NAND_Bank                    */
-
-  uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.
-                                        This parameter can be any value of @ref FSMC_Wait_feature               */
-
-  uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.
-                                        This parameter can be any value of @ref FSMC_NAND_Data_Width            */
-
-  uint32_t EccComputation;         /*!< Enables or disables the ECC computation.
-                                        This parameter can be any value of @ref FSMC_ECC                        */
-
-  uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.
-                                        This parameter can be any value of @ref FSMC_ECC_Page_Size              */
-
-  uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
-                                        delay between CLE low and RE low.
-                                        This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
-
-  uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
-                                        delay between ALE low and RE low.
-                                        This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
-}FSMC_NAND_InitTypeDef;
-
-/**
-  * @brief  FSMC_NAND_PCCARD Timing parameters structure definition
-  */
-typedef struct
-{
-  uint32_t SetupTime;            /*!< Defines the number of HCLK cycles to setup address before
-                                      the command assertion for NAND-Flash read or write access
-                                      to common/Attribute or I/O memory space (depending on
-                                      the memory space timing to be configured).
-                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255    */
-
-  uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the
-                                      command for NAND-Flash read or write access to
-                                      common/Attribute or I/O memory space (depending on the
-                                      memory space timing to be configured).
-                                      This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
-
-  uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address
-                                      (and data for write access) after the command de-assertion
-                                      for NAND-Flash read or write access to common/Attribute
-                                      or I/O memory space (depending on the memory space timing
-                                      to be configured).
-                                      This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
-
-  uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the
-                                      data bus is kept in HiZ after the start of a NAND-Flash
-                                      write access to common/Attribute or I/O memory space (depending
-                                      on the memory space timing to be configured).
-                                      This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
-
-}FSMC_NAND_PCC_TimingTypeDef;
-
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
-/**
-  * @brief  FSMC_NAND Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the PCCARD Memory device.
-                                        This parameter can be any value of @ref FSMC_Wait_feature               */
-
-  uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
-                                        delay between CLE low and RE low.
-                                        This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
-
-  uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
-                                        delay between ALE low and RE low.
-                                        This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
-}FSMC_PCCARD_InitTypeDef;
-
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FSMC_Exported_Constants FSMC Low Layer Exported Constants
-  * @{
-  */
-
-/** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants
-  * @{
-  */
-
-/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
-  * @{
-  */
-#define FSMC_NORSRAM_BANK1                       ((uint32_t)0x00000000)
-#define FSMC_NORSRAM_BANK2                       ((uint32_t)0x00000002)
-#define FSMC_NORSRAM_BANK3                       ((uint32_t)0x00000004)
-#define FSMC_NORSRAM_BANK4                       ((uint32_t)0x00000006)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
-  * @{
-  */
-
-#define FSMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000)
-#define FSMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)FSMC_BCRx_MUXEN)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Memory_Type FSMC Memory Type
-  * @{
-  */
-
-#define FSMC_MEMORY_TYPE_SRAM                    ((uint32_t)0x00000000)
-#define FSMC_MEMORY_TYPE_PSRAM                   ((uint32_t)FSMC_BCRx_MTYP_0)
-#define FSMC_MEMORY_TYPE_NOR                     ((uint32_t)FSMC_BCRx_MTYP_1)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
-  * @{
-  */
-
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000)
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)FSMC_BCRx_MWID_0)
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)FSMC_BCRx_MWID_1)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
-  * @{
-  */
-
-#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)FSMC_BCRx_FACCEN)
-#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE        ((uint32_t)0x00000000)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
-  * @{
-  */
-
-#define FSMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000)
-#define FSMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)FSMC_BCRx_BURSTEN)
-
-/**
-  * @}
-  */
-
-
-/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
-  * @{
-  */
-
-#define FSMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000)
-#define FSMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)FSMC_BCRx_WAITPOL)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
-  * @{
-  */
-
-#define FSMC_WRAP_MODE_DISABLE                   ((uint32_t)0x00000000)
-#define FSMC_WRAP_MODE_ENABLE                    ((uint32_t)FSMC_BCRx_WRAPMOD)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
-  * @{
-  */
-
-#define FSMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000)
-#define FSMC_WAIT_TIMING_DURING_WS               ((uint32_t)FSMC_BCRx_WAITCFG)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Write_Operation FSMC Write Operation
-  * @{
-  */
-
-#define FSMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000)
-#define FSMC_WRITE_OPERATION_ENABLE              ((uint32_t)FSMC_BCRx_WREN)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
-  * @{
-  */
-
-#define FSMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000)
-#define FSMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)FSMC_BCRx_WAITEN)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
-  * @{
-  */
-
-#define FSMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000)
-#define FSMC_EXTENDED_MODE_ENABLE                ((uint32_t)FSMC_BCRx_EXTMOD)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
-  * @{
-  */
-
-#define FSMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000)
-#define FSMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)FSMC_BCRx_ASYNCWAIT)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Write_Burst FSMC Write Burst
-  * @{
-  */
-
-#define FSMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000)
-#define FSMC_WRITE_BURST_ENABLE                  ((uint32_t)FSMC_BCRx_CBURSTRW)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Access_Mode FSMC Access Mode
-  * @{
-  */
-
-#define FSMC_ACCESS_MODE_A                        ((uint32_t)0x00000000)
-#define FSMC_ACCESS_MODE_B                        ((uint32_t)FSMC_BTRx_ACCMOD_0)
-#define FSMC_ACCESS_MODE_C                        ((uint32_t)FSMC_BTRx_ACCMOD_1)
-#define FSMC_ACCESS_MODE_D                        ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
-/** @defgroup FSMC_NAND_Controller FSMC NAND and PCCARD Controller
-  * @{
-  */
-
-/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
-  * @{
-  */
-#define FSMC_NAND_BANK2                          ((uint32_t)0x00000010)
-#define FSMC_NAND_BANK3                          ((uint32_t)0x00000100)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wait_feature FSMC Wait feature
-  * @{
-  */
-#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE           ((uint32_t)0x00000000)
-#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE            ((uint32_t)FSMC_PCRx_PWAITEN)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
-  * @{
-  */
-#define FSMC_PCR_MEMORY_TYPE_PCCARD        ((uint32_t)0x00000000)
-#define FSMC_PCR_MEMORY_TYPE_NAND          ((uint32_t)FSMC_PCRx_PTYP)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
-  * @{
-  */
-#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8                ((uint32_t)0x00000000)
-#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16               ((uint32_t)FSMC_PCRx_PWID_0)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_ECC FSMC NAND ECC
-  * @{
-  */
-#define FSMC_NAND_ECC_DISABLE                    ((uint32_t)0x00000000)
-#define FSMC_NAND_ECC_ENABLE                     ((uint32_t)FSMC_PCRx_ECCEN)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
-  * @{
-  */
-#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE          ((uint32_t)0x00000000)
-#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE          ((uint32_t)FSMC_PCRx_ECCPS_0)
-#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE         ((uint32_t)FSMC_PCRx_ECCPS_1)
-#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE         ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_1)
-#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE         ((uint32_t)FSMC_PCRx_ECCPS_2)
-#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE         ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_2)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Interrupt_definition FSMC Interrupt definition
-  * @brief FSMC Interrupt definition
-  * @{
-  */
-#define FSMC_IT_RISING_EDGE                ((uint32_t)FSMC_SRx_IREN)
-#define FSMC_IT_LEVEL                      ((uint32_t)FSMC_SRx_ILEN)
-#define FSMC_IT_FALLING_EDGE               ((uint32_t)FSMC_SRx_IFEN)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Flag_definition FSMC Flag definition
-  * @brief FSMC Flag definition
-  * @{
-  */
-#define FSMC_FLAG_RISING_EDGE                    ((uint32_t)FSMC_SRx_IRS)
-#define FSMC_FLAG_LEVEL                          ((uint32_t)FSMC_SRx_ILS)
-#define FSMC_FLAG_FALLING_EDGE                   ((uint32_t)FSMC_SRx_IFS)
-#define FSMC_FLAG_FEMPT                          ((uint32_t)FSMC_SRx_FEMPT)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup FSMC_Exported_Macros FSMC Low Layer Exported Macros
-  * @{
-  */
-
-/** @defgroup FSMC_NOR_Macros FSMC NOR/SRAM Exported Macros
- *  @brief macros to handle NOR device enable/disable and read/write operations
- *  @{
- */
-
-/**
-  * @brief  Enable the NORSRAM device access.
-  * @param  __INSTANCE__ FSMC_NORSRAM Instance
-  * @param  __BANK__ FSMC_NORSRAM Bank
-  * @retval none
-  */
-#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
-
-/**
-  * @brief  Disable the NORSRAM device access.
-  * @param  __INSTANCE__ FSMC_NORSRAM Instance
-  * @param  __BANK__ FSMC_NORSRAM Bank
-  * @retval none
-  */
-#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
-
-/**
-  * @}
-  */
-
-#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
-/** @defgroup FSMC_NAND_Macros FSMC NAND Macros
- *  @brief macros to handle NAND device enable/disable
- *  @{
- */
-
-/**
-  * @brief  Enable the NAND device access.
-  * @param  __INSTANCE__ FSMC_NAND Instance
-  * @param  __BANK__ FSMC_NAND Bank
-  * @retval None
-  */
-#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__)  (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
-                                                    SET_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
-
-/**
-  * @brief  Disable the NAND device access.
-  * @param  __INSTANCE__ FSMC_NAND Instance
-  * @param  __BANK__ FSMC_NAND Bank
-  * @retval None
-  */
-#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
-                                                   CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_PCCARD_Macros FSMC PCCARD Macros
- *  @brief macros to handle PCCARD read/write operations
- *  @{
- */
-
-/**
-  * @brief  Enable the PCCARD device access.
-  * @param  __INSTANCE__ FSMC_PCCARD Instance
-  * @retval None
-  */
-#define __FSMC_PCCARD_ENABLE(__INSTANCE__)  SET_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
-
-/**
-  * @brief  Disable the PCCARD device access.
-  * @param  __INSTANCE__ FSMC_PCCARD Instance
-  * @retval None
-  */
-#define __FSMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Interrupt FSMC Interrupt
- *  @brief macros to handle FSMC interrupts
- * @{
- */
-
-/**
-  * @brief  Enable the NAND device interrupt.
-  * @param  __INSTANCE__  FSMC_NAND Instance
-  * @param  __BANK__      FSMC_NAND Bank
-  * @param  __INTERRUPT__ FSMC_NAND interrupt
-  *         This parameter can be any combination of the following values:
-  *            @arg FSMC_IT_RISING_EDGE Interrupt rising edge.
-  *            @arg FSMC_IT_LEVEL Interrupt level.
-  *            @arg FSMC_IT_FALLING_EDGE Interrupt falling edge.
-  * @retval None
-  */
-#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
-                                                                                                        SET_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
-
-/**
-  * @brief  Disable the NAND device interrupt.
-  * @param  __INSTANCE__  FSMC_NAND Instance
-  * @param  __BANK__      FSMC_NAND Bank
-  * @param  __INTERRUPT__ FSMC_NAND interrupt
-  *         This parameter can be any combination of the following values:
-  *            @arg FSMC_IT_RISING_EDGE Interrupt rising edge.
-  *            @arg FSMC_IT_LEVEL Interrupt level.
-  *            @arg FSMC_IT_FALLING_EDGE Interrupt falling edge.
-  * @retval None
-  */
-#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
-                                                                                                         CLEAR_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
-
-/**
-  * @brief  Get flag status of the NAND device.
-  * @param  __INSTANCE__ FSMC_NAND Instance
-  * @param  __BANK__     FSMC_NAND Bank
-  * @param  __FLAG__ FSMC_NAND flag
-  *         This parameter can be any combination of the following values:
-  *            @arg FSMC_FLAG_RISING_EDGE Interrupt rising edge flag.
-  *            @arg FSMC_FLAG_LEVEL Interrupt level edge flag.
-  *            @arg FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
-  *            @arg FSMC_FLAG_FEMPT FIFO empty flag.
-  * @retval The state of FLAG (SET or RESET).
-  */
-#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
-                                                                                                   (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
-
-/**
-  * @brief  Clear flag status of the NAND device.
-  * @param  __INSTANCE__ FSMC_NAND Instance
-  * @param  __BANK__     FSMC_NAND Bank
-  * @param  __FLAG__ FSMC_NAND flag
-  *         This parameter can be any combination of the following values:
-  *            @arg FSMC_FLAG_RISING_EDGE Interrupt rising edge flag.
-  *            @arg FSMC_FLAG_LEVEL Interrupt level edge flag.
-  *            @arg FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
-  *            @arg FSMC_FLAG_FEMPT FIFO empty flag.
-  * @retval None
-  */
-#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \
-                                                                                                    CLEAR_BIT((__INSTANCE__)->SR3, (__FLAG__)))
-
-/**
-  * @brief  Enable the PCCARD device interrupt.
-  * @param  __INSTANCE__ FSMC_PCCARD Instance
-  * @param  __INTERRUPT__ FSMC_PCCARD interrupt
-  *         This parameter can be any combination of the following values:
-  *            @arg FSMC_IT_RISING_EDGE Interrupt rising edge.
-  *            @arg FSMC_IT_LEVEL Interrupt level.
-  *            @arg FSMC_IT_FALLING_EDGE Interrupt falling edge.
-  * @retval None
-  */
-#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
-
-/**
-  * @brief  Disable the PCCARD device interrupt.
-  * @param  __INSTANCE__ FSMC_PCCARD Instance
-  * @param  __INTERRUPT__ FSMC_PCCARD interrupt
-  *         This parameter can be any combination of the following values:
-  *            @arg FSMC_IT_RISING_EDGE Interrupt rising edge.
-  *            @arg FSMC_IT_LEVEL Interrupt level.
-  *            @arg FSMC_IT_FALLING_EDGE Interrupt falling edge.
-  * @retval None
-  */
-#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
-
-/**
-  * @brief  Get flag status of the PCCARD device.
-  * @param  __INSTANCE__ FSMC_PCCARD Instance
-  * @param  __FLAG__ FSMC_PCCARD flag
-  *         This parameter can be any combination of the following values:
-  *            @arg  FSMC_FLAG_RISING_EDGE Interrupt rising edge flag.
-  *            @arg  FSMC_FLAG_LEVEL Interrupt level edge flag.
-  *            @arg  FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
-  *            @arg  FSMC_FLAG_FEMPT FIFO empty flag.
-  * @retval The state of FLAG (SET or RESET).
-  */
-#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief  Clear flag status of the PCCARD device.
-  * @param  __INSTANCE__ FSMC_PCCARD Instance
-  * @param  __FLAG__ FSMC_PCCARD flag
-  *         This parameter can be any combination of the following values:
-  *            @arg  FSMC_FLAG_RISING_EDGE Interrupt rising edge flag.
-  *            @arg  FSMC_FLAG_LEVEL Interrupt level edge flag.
-  *            @arg  FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
-  *            @arg  FSMC_FLAG_FEMPT FIFO empty flag.
-  * @retval None
-  */
-#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__)  CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__))
-
-/**
-  * @}
-  */
-
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup FSMC_LL_Exported_Functions
- *  @{
- */
-
-/** @addtogroup FSMC_NORSRAM
- *  @{
- */
-
-/** @addtogroup FSMC_NORSRAM_Group1
- *  @{
- */
-
-/* FSMC_NORSRAM Controller functions ******************************************/
-/* Initialization/de-initialization functions */
-HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
-HAL_StatusTypeDef  FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
-HAL_StatusTypeDef  FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
-
-/**
-  * @}
-  */
-
-/** @addtogroup FSMC_NORSRAM_Group2
- *  @{
- */
-
-/* FSMC_NORSRAM Control functions */
-HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
-/** @addtogroup FSMC_NAND
- *  @{
- */
-
-/* FSMC_NAND Controller functions **********************************************/
-/* Initialization/de-initialization functions */
-/** @addtogroup FSMC_NAND_Exported_Functions_Group1
- *  @{
- */
-
-HAL_StatusTypeDef  FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
-HAL_StatusTypeDef  FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef  FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef  FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
-
-/**
-  * @}
-  */
-
-/* FSMC_NAND Control functions */
-/** @addtogroup FSMC_NAND_Exported_Functions_Group2
- *  @{
- */
-
-HAL_StatusTypeDef  FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef  FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef  FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup FSMC_PCCARD
- *  @{
- */
-
-/* FSMC_PCCARD Controller functions ********************************************/
-/* Initialization/de-initialization functions */
-/** @addtogroup FSMC_PCCARD_Exported_Functions_Group1
- *  @{
- */
-
-HAL_StatusTypeDef  FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
-HAL_StatusTypeDef  FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
-HAL_StatusTypeDef  FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
-HAL_StatusTypeDef  FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); 
-HAL_StatusTypeDef  FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* FSMC_BANK1 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_FSMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_ll_sdmmc.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,876 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_ll_sdmmc.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of low layer SDMMC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __stm32f1xx_LL_SD_H
-#define __stm32f1xx_LL_SD_H
-
-#if defined(STM32F103xE) || defined(STM32F103xG)
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SDMMC_LL
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
-  * @{
-  */
-  
-/** 
-  * @brief  SDMMC Configuration Structure definition  
-  */
-typedef struct
-{
-  uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
-                                      This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */
-
-  uint32_t ClockBypass;          /*!< Specifies whether the SDIO Clock divider bypass is
-                                      enabled or disabled.
-                                      This parameter can be a value of @ref SDMMC_LL_Clock_Bypass               */
-
-  uint32_t ClockPowerSave;       /*!< Specifies whether SDIO Clock output is enabled or
-                                      disabled when the bus is idle.
-                                      This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */
-
-  uint32_t BusWide;              /*!< Specifies the SDIO bus width.
-                                      This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */
-
-  uint32_t HardwareFlowControl;  /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
-                                      This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */
-
-  uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDIO controller.
-                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255 */  
-  
-}SDIO_InitTypeDef;
-  
-
-/** 
-  * @brief  SDIO Command Control structure 
-  */
-typedef struct                                                                                            
-{
-  uint32_t Argument;            /*!< Specifies the SDIO command argument which is sent
-                                     to a card as part of a command message. If a command
-                                     contains an argument, it must be loaded into this register
-                                     before writing the command to the command register.              */
-
-  uint32_t CmdIndex;            /*!< Specifies the SDIO command index. It must be Min_Data = 0 and 
-                                     Max_Data = 64                                                    */
-
-  uint32_t Response;            /*!< Specifies the SDIO response type.
-                                     This parameter can be a value of @ref SDMMC_LL_Response_Type         */
-
-  uint32_t WaitForInterrupt;    /*!< Specifies whether SDIO wait for interrupt request is 
-                                     enabled or disabled.
-                                     This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */
-
-  uint32_t CPSM;                /*!< Specifies whether SDIO Command path state machine (CPSM)
-                                     is enabled or disabled.
-                                     This parameter can be a value of @ref SDMMC_LL_CPSM_State            */
-}SDIO_CmdInitTypeDef;
-
-
-/** 
-  * @brief  SDIO Data Control structure 
-  */
-typedef struct
-{
-  uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */
-
-  uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */
- 
-  uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
-                                     This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */
- 
-  uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
-                                     is a read or write.
-                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
- 
-  uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
-                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */
- 
-  uint32_t DPSM;                /*!< Specifies whether SDIO Data path state machine (DPSM)
-                                     is enabled or disabled.
-                                     This parameter can be a value of @ref SDMMC_LL_DPSM_State         */
-}SDIO_DataInitTypeDef;
-
-/**
-  * @}
-  */
-  
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
-  * @{
-  */
-
-/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
-  * @{
-  */
-#define SDIO_CLOCK_EDGE_RISING               ((uint32_t)0x00000000)
-#define SDIO_CLOCK_EDGE_FALLING              SDIO_CLKCR_NEGEDGE
-
-#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
-                                  ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
-  * @{
-  */
-#define SDIO_CLOCK_BYPASS_DISABLE             ((uint32_t)0x00000000)
-#define SDIO_CLOCK_BYPASS_ENABLE              SDIO_CLKCR_BYPASS   
-
-#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
-                                      ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
-/**
-  * @}
-  */ 
-
-/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
-  * @{
-  */
-#define SDIO_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000)
-#define SDIO_CLOCK_POWER_SAVE_ENABLE          SDIO_CLKCR_PWRSAV
-
-#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
-                                        ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Bus_Wide Bus Width
-  * @{
-  */
-#define SDIO_BUS_WIDE_1B                      ((uint32_t)0x00000000)
-#define SDIO_BUS_WIDE_4B                      SDIO_CLKCR_WIDBUS_0
-#define SDIO_BUS_WIDE_8B                      SDIO_CLKCR_WIDBUS_1
-
-#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
-                                ((WIDE) == SDIO_BUS_WIDE_4B) || \
-                                ((WIDE) == SDIO_BUS_WIDE_8B))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
-  * @{
-  */
-#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000)
-#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE     SDIO_CLKCR_HWFC_EN
-
-#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
-                                                ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
-/**
-  * @}
-  */
-  
-/** @defgroup SDMMC_LL_Clock_Division Clock Division
-  * @{
-  */
-#define IS_SDIO_CLKDIV(DIV)   ((DIV) <= 0xFF)
-/**
-  * @}
-  */  
-    
-/** @defgroup SDMMC_LL_Command_Index Command Index
-  * @{
-  */
-#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Response_Type Response Type
-  * @{
-  */
-#define SDIO_RESPONSE_NO                    ((uint32_t)0x00000000)
-#define SDIO_RESPONSE_SHORT                 SDIO_CMD_WAITRESP_0
-#define SDIO_RESPONSE_LONG                  SDIO_CMD_WAITRESP
-
-#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO)    || \
-                                    ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
-                                    ((RESPONSE) == SDIO_RESPONSE_LONG))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
-  * @{
-  */
-#define SDIO_WAIT_NO                        ((uint32_t)0x00000000)
-#define SDIO_WAIT_IT                        SDIO_CMD_WAITINT 
-#define SDIO_WAIT_PEND                      SDIO_CMD_WAITPEND
-
-#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
-                            ((WAIT) == SDIO_WAIT_IT) || \
-                            ((WAIT) == SDIO_WAIT_PEND))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_CPSM_State CPSM State
-  * @{
-  */
-#define SDIO_CPSM_DISABLE                   ((uint32_t)0x00000000)
-#define SDIO_CPSM_ENABLE                    SDIO_CMD_CPSMEN
-
-#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
-                            ((CPSM) == SDIO_CPSM_ENABLE))
-/**
-  * @}
-  */  
-
-/** @defgroup SDMMC_LL_Response_Registers Response Register
-  * @{
-  */
-#define SDIO_RESP1                          ((uint32_t)0x00000000)
-#define SDIO_RESP2                          ((uint32_t)0x00000004)
-#define SDIO_RESP3                          ((uint32_t)0x00000008)
-#define SDIO_RESP4                          ((uint32_t)0x0000000C)
-
-#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
-                            ((RESP) == SDIO_RESP2) || \
-                            ((RESP) == SDIO_RESP3) || \
-                            ((RESP) == SDIO_RESP4))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Data_Length Data Lenght
-  * @{
-  */
-#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Data_Block_Size  Data Block Size
-  * @{
-  */
-#define SDIO_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000)
-#define SDIO_DATABLOCK_SIZE_2B               SDIO_DCTRL_DBLOCKSIZE_0
-#define SDIO_DATABLOCK_SIZE_4B               SDIO_DCTRL_DBLOCKSIZE_1
-#define SDIO_DATABLOCK_SIZE_8B               (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1)
-#define SDIO_DATABLOCK_SIZE_16B              SDIO_DCTRL_DBLOCKSIZE_2
-#define SDIO_DATABLOCK_SIZE_32B              (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2)
-#define SDIO_DATABLOCK_SIZE_64B              (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
-#define SDIO_DATABLOCK_SIZE_128B             (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
-#define SDIO_DATABLOCK_SIZE_256B             SDIO_DCTRL_DBLOCKSIZE_3
-#define SDIO_DATABLOCK_SIZE_512B             (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3)
-#define SDIO_DATABLOCK_SIZE_1024B            (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
-#define SDIO_DATABLOCK_SIZE_2048B            (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) 
-#define SDIO_DATABLOCK_SIZE_4096B            (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
-#define SDIO_DATABLOCK_SIZE_8192B            (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
-#define SDIO_DATABLOCK_SIZE_16384B           (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
-
-#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B)    || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_2B)    || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_4B)    || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_8B)    || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_16B)   || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_32B)   || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_64B)   || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_128B)  || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_256B)  || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_512B)  || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) 
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
-  * @{
-  */
-#define SDIO_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000)
-#define SDIO_TRANSFER_DIR_TO_SDIO            SDIO_DCTRL_DTDIR
-
-#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
-                                   ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
-  * @{
-  */
-#define SDIO_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000)
-#define SDIO_TRANSFER_MODE_STREAM            SDIO_DCTRL_DTMODE
-
-#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
-                                     ((MODE) == SDIO_TRANSFER_MODE_STREAM))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_DPSM_State DPSM State
-  * @{
-  */
-#define SDIO_DPSM_DISABLE                    ((uint32_t)0x00000000)
-#define SDIO_DPSM_ENABLE                     SDIO_DCTRL_DTEN
-
-#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
-                            ((DPSM) == SDIO_DPSM_ENABLE))
-/**
-  * @}
-  */
-  
-/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
-  * @{
-  */
-#define SDIO_READ_WAIT_MODE_DATA2                ((uint32_t)0x00000000)
-#define SDIO_READ_WAIT_MODE_CLK                  (SDIO_DCTRL_RWMOD)
-
-#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
-                                     ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
-/**
-  * @}
-  */  
-
-/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
-  * @{
-  */
-#define SDIO_IT_CCRCFAIL                    SDIO_STA_CCRCFAIL
-#define SDIO_IT_DCRCFAIL                    SDIO_STA_DCRCFAIL
-#define SDIO_IT_CTIMEOUT                    SDIO_STA_CTIMEOUT
-#define SDIO_IT_DTIMEOUT                    SDIO_STA_DTIMEOUT
-#define SDIO_IT_TXUNDERR                    SDIO_STA_TXUNDERR
-#define SDIO_IT_RXOVERR                     SDIO_STA_RXOVERR
-#define SDIO_IT_CMDREND                     SDIO_STA_CMDREND
-#define SDIO_IT_CMDSENT                     SDIO_STA_CMDSENT
-#define SDIO_IT_DATAEND                     SDIO_STA_DATAEND
-#define SDIO_IT_STBITERR                    SDIO_STA_STBITERR
-#define SDIO_IT_DBCKEND                     SDIO_STA_DBCKEND
-#define SDIO_IT_CMDACT                      SDIO_STA_CMDACT
-#define SDIO_IT_TXACT                       SDIO_STA_TXACT
-#define SDIO_IT_RXACT                       SDIO_STA_RXACT
-#define SDIO_IT_TXFIFOHE                    SDIO_STA_TXFIFOHE
-#define SDIO_IT_RXFIFOHF                    SDIO_STA_RXFIFOHF
-#define SDIO_IT_TXFIFOF                     SDIO_STA_TXFIFOF
-#define SDIO_IT_RXFIFOF                     SDIO_STA_RXFIFOF
-#define SDIO_IT_TXFIFOE                     SDIO_STA_TXFIFOE
-#define SDIO_IT_RXFIFOE                     SDIO_STA_RXFIFOE
-#define SDIO_IT_TXDAVL                      SDIO_STA_TXDAVL
-#define SDIO_IT_RXDAVL                      SDIO_STA_RXDAVL
-#define SDIO_IT_SDIOIT                      SDIO_STA_SDIOIT
-#define SDIO_IT_CEATAEND                    SDIO_STA_CEATAEND
-
-/**
-  * @}
-  */ 
-
-/** @defgroup SDMMC_LL_Flags Flags
-  * @{
-  */
-#define SDIO_FLAG_CCRCFAIL                  SDIO_STA_CCRCFAIL
-#define SDIO_FLAG_DCRCFAIL                  SDIO_STA_DCRCFAIL
-#define SDIO_FLAG_CTIMEOUT                  SDIO_STA_CTIMEOUT
-#define SDIO_FLAG_DTIMEOUT                  SDIO_STA_DTIMEOUT
-#define SDIO_FLAG_TXUNDERR                  SDIO_STA_TXUNDERR
-#define SDIO_FLAG_RXOVERR                   SDIO_STA_RXOVERR
-#define SDIO_FLAG_CMDREND                   SDIO_STA_CMDREND
-#define SDIO_FLAG_CMDSENT                   SDIO_STA_CMDSENT
-#define SDIO_FLAG_DATAEND                   SDIO_STA_DATAEND
-#define SDIO_FLAG_STBITERR                  SDIO_STA_STBITERR
-#define SDIO_FLAG_DBCKEND                   SDIO_STA_DBCKEND
-#define SDIO_FLAG_CMDACT                    SDIO_STA_CMDACT
-#define SDIO_FLAG_TXACT                     SDIO_STA_TXACT
-#define SDIO_FLAG_RXACT                     SDIO_STA_RXACT
-#define SDIO_FLAG_TXFIFOHE                  SDIO_STA_TXFIFOHE
-#define SDIO_FLAG_RXFIFOHF                  SDIO_STA_RXFIFOHF
-#define SDIO_FLAG_TXFIFOF                   SDIO_STA_TXFIFOF
-#define SDIO_FLAG_RXFIFOF                   SDIO_STA_RXFIFOF
-#define SDIO_FLAG_TXFIFOE                   SDIO_STA_TXFIFOE
-#define SDIO_FLAG_RXFIFOE                   SDIO_STA_RXFIFOE
-#define SDIO_FLAG_TXDAVL                    SDIO_STA_TXDAVL
-#define SDIO_FLAG_RXDAVL                    SDIO_STA_RXDAVL
-#define SDIO_FLAG_SDIOIT                    SDIO_STA_SDIOIT
-#define SDIO_FLAG_CEATAEND                  SDIO_STA_CEATAEND
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
-  * @{
-  */
-  
-/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
-  * @brief SDMMC_LL registers bit address in the alias region
-  * @{
-  */
-  
-/* ---------------------- SDIO registers bit mask --------------------------- */
-/* --- CLKCR Register ---*/
-/* CLKCR register clear mask */ 
-#define CLKCR_CLEAR_MASK         ((uint32_t)(SDIO_CLKCR_CLKDIV  | SDIO_CLKCR_PWRSAV |\
-                                             SDIO_CLKCR_BYPASS  | SDIO_CLKCR_WIDBUS |\
-                                             SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
-
-/* --- DCTRL Register ---*/
-/* SDIO DCTRL Clear Mask */
-#define DCTRL_CLEAR_MASK         ((uint32_t)(SDIO_DCTRL_DTEN    | SDIO_DCTRL_DTDIR |\
-                                             SDIO_DCTRL_DTMODE  | SDIO_DCTRL_DBLOCKSIZE))
-
-/* --- CMD Register ---*/
-/* CMD Register clear mask */
-#define CMD_CLEAR_MASK           ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
-                                             SDIO_CMD_WAITINT  | SDIO_CMD_WAITPEND |\
-                                             SDIO_CMD_CPSMEN   | SDIO_CMD_SDIOSUSPEND))
-
-/* SDIO RESP Registers Address */
-#define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))
-
-/* SDIO Intialization Frequency (400KHz max) */
-#define SDIO_INIT_CLK_DIV ((uint8_t)0xC3)
-
-/* SDIO Data Transfer Frequency */
-#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x9)
-
-/**
-  * @}
-  */
-  
-/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
-  * @brief macros to handle interrupts and specific clock configurations
-  * @{
-  */
- 
-/**
-  * @brief  Enable the SDIO device.
-  * @param  __INSTANCE__: SDIO Instance  
-  * @retval None
-  */ 
-#define __SDIO_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR |= SDIO_CLKCR_CLKEN)
-
-/**
-  * @brief  Disable the SDIO device.
-  * @param  __INSTANCE__: SDIO Instance  
-  * @retval None
-  */
-#define __SDIO_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR &= ~SDIO_CLKCR_CLKEN)
-
-/**
-  * @brief  Enable the SDIO DMA transfer.
-  * @param  None  
-  * @retval None
-  */ 
-#define __SDIO_DMA_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_DMAEN)
-/**
-  * @brief  Disable the SDIO DMA transfer.
-  * @param  None   
-  * @retval None
-  */
-#define __SDIO_DMA_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_DMAEN)
- 
-/**
-  * @brief  Enable the SDIO device interrupt.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
-  *         This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
-  * @retval None
-  */
-#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the SDIO device interrupt.
-  * @param  __INSTANCE__ : Pointer to SDIO register base   
-  * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
-  * @retval None
-  */
-#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Checks whether the specified SDIO flag is set or not. 
-  * @param  __INSTANCE__ : Pointer to SDIO register base   
-  * @param  __FLAG__: specifies the flag to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
-  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
-  *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
-  *            @arg SDIO_FLAG_RXACT:    Data receive in progress
-  *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
-  *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
-  *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
-  *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
-  *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
-  *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
-  *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
-  *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
-  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
-  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
-  * @retval The new state of SDIO_FLAG (SET or RESET).
-  */
-#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__)   (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
-
-
-/**
-  * @brief  Clears the SDIO pending flags.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @param  __FLAG__: specifies the flag to clear.  
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
-  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
-  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
-  * @retval None
-  */
-#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__)   ((__INSTANCE__)->ICR = (__FLAG__))
-
-/**
-  * @brief  Checks whether the specified SDIO interrupt has occurred or not.
-  * @param  __INSTANCE__ : Pointer to SDIO register base   
-  * @param  __INTERRUPT__: specifies the SDIO interrupt source to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
-  * @retval The new state of SDIO_IT (SET or RESET).
-  */
-#define __SDIO_GET_IT  (__INSTANCE__, __INTERRUPT__)   (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @brief  Clears the SDIO's interrupt pending bits.
-  * @param  __INSTANCE__ : Pointer to SDIO register base 
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIO_DCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
-  * @retval None
-  */
-#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->ICR = (__INTERRUPT__))
-
-/**
-  * @brief  Enable Start the SD I/O Read Wait operation.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @retval None
-  */  
-#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_RWSTART)
-
-/**
-  * @brief  Disable Start the SD I/O Read Wait operations.
-  * @param  __INSTANCE__ : Pointer to SDIO register base   
-  * @retval None
-  */  
-#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_RWSTART)
-
-/**
-  * @brief  Enable Start the SD I/O Read Wait operation.
-  * @param  __INSTANCE__ : Pointer to SDIO register base   
-  * @retval None
-  */  
-#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_RWSTOP)
-
-/**
-  * @brief  Disable Stop the SD I/O Read Wait operations.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @retval None
-  */  
-#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_RWSTOP)
-
-/**
-  * @brief  Enable the SD I/O Mode Operation.
-  * @param  __INSTANCE__ : Pointer to SDIO register base   
-  * @retval None
-  */  
-#define __SDIO_OPERATION_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_SDIOEN) 
-
-/**
-  * @brief  Disable the SD I/O Mode Operation.
-  * @param  __INSTANCE__ : Pointer to SDIO register base 
-  * @retval None
-  */  
-#define __SDIO_OPERATION_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_SDIOEN) 
-
-/**
-  * @brief  Enable the SD I/O Suspend command sending.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @retval None
-  */  
-#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDIO_CMD_SDIOSUSPEND) 
-
-/**
-  * @brief  Disable the SD I/O Suspend command sending.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @retval None
-  */  
-#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDIO_CMD_SDIOSUSPEND) 
-    
-/**
-  * @brief  Enable the command completion signal.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @retval None
-  */    
-#define __SDIO_CEATA_CMD_COMPLETION_ENABLE(__INSTANCE__)   ((__INSTANCE__)->CMD |= SDIO_CMD_ENCMDCOMPL)
-
-/**
-  * @brief  Disable the command completion signal.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @retval None
-  */  
-#define __SDIO_CEATA_CMD_COMPLETION_DISABLE(__INSTANCE__)   ((__INSTANCE__)->CMD &= ~SDIO_CMD_ENCMDCOMPL)
-
-/**
-  * @brief  Enable the CE-ATA interrupt.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @retval None
-  */    
-#define __SDIO_CEATA_ENABLE_IT(__INSTANCE__)   ((__INSTANCE__)->CMD &= ~SDIO_CMD_NIEN)
-
-/**
-  * @brief  Disable the CE-ATA interrupt.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @retval None
-  */  
-#define __SDIO_CEATA_DISABLE_IT(__INSTANCE__)   ((__INSTANCE__)->CMD |= SDIO_CMD_NIEN)
-
-/**
-  * @brief  Enable send CE-ATA command (CMD61).
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @retval None
-  */  
-#define __SDIO_CEATA_SENDCMD_ENABLE(__INSTANCE__)   ((__INSTANCE__)->CMD |= SDIO_CMD_CEATACMD)
-
-/**
-  * @brief  Disable send CE-ATA command (CMD61).
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @retval None
-  */  
-#define __SDIO_CEATA_SENDCMD_DISABLE(__INSTANCE__)   ((__INSTANCE__)->CMD &= ~SDIO_CMD_CEATACMD)
-  
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-  
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SDMMC_LL_Exported_Functions
-  * @{
-  */
-  
-/* Initialization/de-initialization functions  **********************************/
-/** @addtogroup HAL_SDMMC_LL_Group1
-  * @{
-  */
-HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
-/**
-  * @}
-  */
-
-/* I/O operation functions  *****************************************************/
-/** @addtogroup HAL_SDMMC_LL_Group2
-  * @{
-  */
-/* Blocking mode: Polling */
-uint32_t          SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
-HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
-/**
-  * @}
-  */
-  
-/* Peripheral Control functions  ************************************************/
-/** @addtogroup HAL_SDMMC_LL_Group3
-  * @{
-  */
-HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
-HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
-uint32_t          SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
-
-/* Command path state machine (CPSM) management functions */
-HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command);
-uint8_t           SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
-uint32_t          SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
-
-/* Data path state machine (DPSM) management functions */
-HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data);
-uint32_t          SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
-uint32_t          SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
-
-/* SDIO Cards mode management functions */
-HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F103xE || STM32F103xG */
-
-#endif /* __stm32f1xx_LL_SD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/stm32f1xx_ll_usb.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,616 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_ll_usb.h
-  * @author  MCD Application Team
-  * @version V1.0.4
-  * @date    29-April-2016
-  * @brief   Header file of USB Low Layer HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_USB_H
-#define __STM32F1xx_LL_USB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || \
-    defined(STM32F103x6) || defined(STM32F103xB) || \
-    defined(STM32F103xE) || defined(STM32F103xG) || \
-    defined(STM32F105xC) || defined(STM32F107xC)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup USB_LL
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup USB_LL_Exported_Types USB Low Layer Exported Types
-  * @{
-  */
-/** 
-  * @brief  USB Mode definition  
-  */
-typedef enum 
-{
-   USB_DEVICE_MODE  = 0,
-   USB_HOST_MODE    = 1,
-   USB_DRD_MODE     = 2
-}USB_ModeTypeDef;
-
-#if defined (USB_OTG_FS)
-/**
-  * @brief  URB States definition
-  */
-typedef enum {
-  URB_IDLE = 0,
-  URB_DONE,
-  URB_NOTREADY,
-  URB_NYET,
-  URB_ERROR,
-  URB_STALL
-}USB_OTG_URBStateTypeDef;
-
-/** 
-  * @brief  Host channel States  definition
-  */
-typedef enum {
-  HC_IDLE = 0,
-  HC_XFRC,
-  HC_HALTED,
-  HC_NAK,
-  HC_NYET,
-  HC_STALL,
-  HC_XACTERR,  
-  HC_BBLERR,   
-  HC_DATATGLERR
-}USB_OTG_HCStateTypeDef;
-
-/** 
-  * @brief  USB OTG Initialization Structure definition  
-  */
-typedef struct
-{
-  uint32_t dev_endpoints;        /*!< Device Endpoints number.
-                                      This parameter depends on the used USB core.
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-  
-  uint32_t Host_channels;        /*!< Host Channels number.
-                                      This parameter Depends on the used USB core.   
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-  
-  uint32_t speed;                /*!< USB Core speed.
-                                      This parameter can be any value of @ref USB_Core_Speed_                */
-  
-  uint32_t ep0_mps;              /*!< Set the Endpoint 0 Max Packet size. 
-                                      This parameter can be any value of @ref USB_EP0_MPS_                   */
-  
-  uint32_t Sof_enable;           /*!< Enable or disable the output of the SOF signal.                        */
-  
-  uint32_t low_power_enable;     /*!< Enable or disable the low power mode.                                  */
-  
-  uint32_t vbus_sensing_enable;  /*!< Enable or disable the VBUS Sensing feature.                            */
-  
-  uint32_t use_external_vbus;    /*!< Enable or disable the use of the external VBUS.                        */
-}USB_OTG_CfgTypeDef;
-
-typedef struct
-{
-  uint8_t   num;            /*!< Endpoint number
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 15    */
-  
-  uint8_t   is_in;          /*!< Endpoint direction
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
-  
-  uint8_t   is_stall;       /*!< Endpoint stall condition
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
-  
-  uint8_t   type;           /*!< Endpoint type
-                                 This parameter can be any value of @ref USB_EP_Type_                     */
-  
-  uint8_t   data_pid_start; /*!< Initial data PID
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
-  
-  uint8_t   even_odd_frame; /*!< IFrame parity
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
-  
-  uint16_t  tx_fifo_num;    /*!< Transmission FIFO number
-                                 This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
-  
-  uint32_t  maxpacket;      /*!< Endpoint Max packet size
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
-  
-  uint8_t   *xfer_buff;     /*!< Pointer to transfer buffer                                               */
-  
-  uint32_t  dma_addr;       /*!< 32 bits aligned transfer buffer address                                  */
-  
-  uint32_t  xfer_len;       /*!< Current transfer length                                                  */
-  
-  uint32_t  xfer_count;     /*!< Partial transfer length in case of multi packet transfer                 */
-}USB_OTG_EPTypeDef;
-
-typedef struct
-{
-  uint8_t   dev_addr ;     /*!< USB device address.
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 255    */
-  
-  uint8_t   ch_num;        /*!< Host channel number.
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
-  
-  uint8_t   ep_num;        /*!< Endpoint number.
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
-  
-  uint8_t   ep_is_in;      /*!< Endpoint direction
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-  
-  uint8_t   speed;         /*!< USB Host speed.
-                                This parameter can be any value of @ref USB_Core_Speed_                    */
-  
-  uint8_t   do_ping;       /*!< Enable or disable the use of the PING protocol for HS mode.                */
-  
-  uint8_t   process_ping;  /*!< Execute the PING protocol for HS mode.                                     */
-  
-  uint8_t   ep_type;       /*!< Endpoint Type.
-                                This parameter can be any value of @ref USB_EP_Type_                       */
-  
-  uint16_t  max_packet;    /*!< Endpoint Max packet size.
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */
-  
-  uint8_t   data_pid;      /*!< Initial data PID.
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-  
-  uint8_t   *xfer_buff;    /*!< Pointer to transfer buffer.                                                */
-  
-  uint32_t  xfer_len;      /*!< Current transfer length.                                                   */
-  
-  uint32_t  xfer_count;    /*!< Partial transfer length in case of multi packet transfer.                  */
-  
-  uint8_t   toggle_in;     /*!< IN transfer current toggle flag.
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-  
-  uint8_t   toggle_out;    /*!< OUT transfer current toggle flag
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-  
-  uint32_t  dma_addr;      /*!< 32 bits aligned transfer buffer address.                                   */
-  
-  uint32_t  ErrCnt;        /*!< Host channel error count.*/
-  
-  USB_OTG_URBStateTypeDef  urb_state;  /*!< URB state.
-                                           This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
-  
-  USB_OTG_HCStateTypeDef   state;     /*!< Host Channel state.
-                                           This parameter can be any value of @ref USB_OTG_HCStateTypeDef  */
-}USB_OTG_HCTypeDef;
-#endif /* USB_OTG_FS */
-
-#if defined (USB)
-/** 
-  * @brief  USB Initialization Structure definition  
-  */
-typedef struct
-{
-  uint32_t dev_endpoints;        /*!< Device Endpoints number.
-                                      This parameter depends on the used USB core.   
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-  
-  uint32_t speed;                /*!< USB Core speed.
-                                      This parameter can be any value of @ref USB_Core_Speed                 */
-  
-  uint32_t ep0_mps;              /*!< Set the Endpoint 0 Max Packet size. 
-                                      This parameter can be any value of @ref USB_EP0_MPS                    */
-  
-  uint32_t phy_itface;           /*!< Select the used PHY interface.
-                                      This parameter can be any value of @ref USB_Core_PHY                   */
-  
-  uint32_t Sof_enable;           /*!< Enable or disable the output of the SOF signal.                        */
-  
-  uint32_t low_power_enable;       /*!< Enable or disable Low Power mode                                      */
-  
-  uint32_t lpm_enable;             /*!< Enable or disable Battery charging.                                  */
-  
-  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                  */
-} USB_CfgTypeDef;
-
-typedef struct
-{
-  uint8_t   num;            /*!< Endpoint number
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 15    */
-  
-  uint8_t   is_in;          /*!< Endpoint direction
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
-  
-  uint8_t   is_stall;       /*!< Endpoint stall condition
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
-  
-  uint8_t   type;           /*!< Endpoint type
-                                 This parameter can be any value of @ref USB_EP_Type                      */
-  
-  uint16_t  pmaadress;      /*!< PMA Address
-                                 This parameter can be any value between Min_addr = 0 and Max_addr = 1K   */
-  
-  uint16_t  pmaaddr0;       /*!< PMA Address0
-                                 This parameter can be any value between Min_addr = 0 and Max_addr = 1K   */
-  
-  uint16_t  pmaaddr1;        /*!< PMA Address1
-                                 This parameter can be any value between Min_addr = 0 and Max_addr = 1K   */
-  
-  uint8_t   doublebuffer;    /*!< Double buffer enable
-                                 This parameter can be 0 or 1                                             */
-  
-  uint16_t  tx_fifo_num;    /*!< This parameter is not required by USB Device FS peripheral, it is used 
-                                 only by USB OTG FS peripheral    
-                                 This parameter is added to ensure compatibility across USB peripherals   */
-  
-  uint32_t  maxpacket;      /*!< Endpoint Max packet size
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
-  
-  uint8_t   *xfer_buff;     /*!< Pointer to transfer buffer                                               */
-  
-  uint32_t  xfer_len;       /*!< Current transfer length                                                  */
-  
-  uint32_t  xfer_count;     /*!< Partial transfer length in case of multi packet transfer                 */
-
-} USB_EPTypeDef;
-#endif /* USB */
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USB_LL_Exported_Constants USB Low Layer Exported Constants
-  * @{
-  */
-#if defined (USB_OTG_FS)
-/** @defgroup USB_LL_Core_Mode USB Low Layer Core Mode
-  * @{
-  */
-#define USB_OTG_MODE_DEVICE                    0
-#define USB_OTG_MODE_HOST                      1
-#define USB_OTG_MODE_DRD                       2
-/**
-  * @}
-  */
-
-/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
-  * @{
-  */
-#define USB_OTG_SPEED_LOW                      2
-#define USB_OTG_SPEED_FULL                     3
-
-/**
-  * @}
-  */
-
-/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
-  * @{
-  */
-#define USB_OTG_ULPI_PHY                       1
-#define USB_OTG_EMBEDDED_PHY                   2
-/**
-  * @}
-  */
-
-/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
-  * @{
-  */
-#define USB_OTG_FS_MAX_PACKET_SIZE             64
-#define USB_OTG_MAX_EP0_SIZE                   64
-/**
-  * @}
-  */
-
-/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
-  * @{
-  */
-#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1 << 1)
-#define DSTS_ENUMSPD_LS_PHY_6MHZ               (2 << 1)
-#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3 << 1)
-/**
-  * @}
-  */
-
-/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
-  * @{
-  */
-#define DCFG_FRAME_INTERVAL_80                 0
-#define DCFG_FRAME_INTERVAL_85                 1
-#define DCFG_FRAME_INTERVAL_90                 2
-#define DCFG_FRAME_INTERVAL_95                 3
-/**
-  * @}
-  */
-
-/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
-  * @{
-  */
-#define DEP0CTL_MPS_64                         0
-#define DEP0CTL_MPS_32                         1
-#define DEP0CTL_MPS_16                         2
-#define DEP0CTL_MPS_8                          3
-/**
-  * @}
-  */
-
-/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
-  * @{
-  */
-#define EP_SPEED_LOW                           0
-#define EP_SPEED_FULL                          1
-#define EP_SPEED_HIGH                          2
-/**
-  * @}
-  */
-
-/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
-  * @{
-  */
-#define EP_TYPE_CTRL                           0
-#define EP_TYPE_ISOC                           1
-#define EP_TYPE_BULK                           2
-#define EP_TYPE_INTR                           3
-#define EP_TYPE_MSK                            3
-/**
-  * @}
-  */
-
-/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
-  * @{
-  */
-#define STS_GOUT_NAK                           1
-#define STS_DATA_UPDT                          2
-#define STS_XFER_COMP                          3
-#define STS_SETUP_COMP                         4
-#define STS_SETUP_UPDT                         6
-/**
-  * @}
-  */
-
-/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
-  * @{
-  */
-#define HCFG_30_60_MHZ                         0
-#define HCFG_48_MHZ                            1
-#define HCFG_6_MHZ                             2
-/**
-  * @}
-  */
-
-/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
-  * @{
-  */
-#define HPRT0_PRTSPD_HIGH_SPEED                0
-#define HPRT0_PRTSPD_FULL_SPEED                1
-#define HPRT0_PRTSPD_LOW_SPEED                 2
-/**
-  * @}
-  */
-
-#define HCCHAR_CTRL                            0
-#define HCCHAR_ISOC                            1
-#define HCCHAR_BULK                            2
-#define HCCHAR_INTR                            3
-
-#define HC_PID_DATA0                           0
-#define HC_PID_DATA2                           1
-#define HC_PID_DATA1                           2
-#define HC_PID_SETUP                           3
-
-#define GRXSTS_PKTSTS_IN                       2
-#define GRXSTS_PKTSTS_IN_XFER_COMP             3
-#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5
-#define GRXSTS_PKTSTS_CH_HALTED                7
-
-#define USBx_PCGCCTL                           *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
-#define USBx_HPRT0                             *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
-
-#define USBx_DEVICE                            ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE))
-#define USBx_INEP(i)                           ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
-#define USBx_OUTEP(i)                          ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
-#define USBx_DFIFO(i)                          *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
-
-#define USBx_HOST                              ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))
-#define USBx_HC(i)                             ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
-#endif /* USB_OTG_FS */
-
-#if defined (USB)  
-/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
-  * @{
-  */
-#define DEP0CTL_MPS_64                         0
-#define DEP0CTL_MPS_32                         1
-#define DEP0CTL_MPS_16                         2
-#define DEP0CTL_MPS_8                          3
-/**
-  * @}
-  */ 
-
-/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
-  * @{
-  */
-#define EP_TYPE_CTRL                           0
-#define EP_TYPE_ISOC                           1
-#define EP_TYPE_BULK                           2
-#define EP_TYPE_INTR                           3
-#define EP_TYPE_MSK                            3
-/**
-  * @}
-  */ 
-
-#define BTABLE_ADDRESS                         (0x000)
-#endif /* USB */
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
-  * @{
-  */
-#if defined (USB_OTG_FS)
-#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)     ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
-#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
-
-#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__)          (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
-#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
-#endif /* USB_OTG_FS */
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
-  * @{
-  */
-/** @addtogroup USB_LL_Exported_Functions_Group1 Peripheral Control functions
-  * @{
-  */
-#if defined (USB_OTG_FS)
-HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
-HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeDef mode);
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
-HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
-void *            USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup);
-uint8_t           USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
-uint32_t          USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
-void              USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
-
-HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
-uint32_t          USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,  
-                              uint8_t ch_num,
-                              uint8_t epnum,
-                              uint8_t dev_address,
-                              uint8_t speed,
-                              uint8_t ep_type,
-                              uint16_t mps);
-HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc);
-uint32_t          USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
-HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
-#endif /* USB_OTG_FS */
-
-#if defined (USB)
-HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef Init);
-HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef Init);
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode);
-HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx , uint8_t speed);
-HAL_StatusTypeDef USB_FlushRxFifo (USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num );
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
-void *            USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
-HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx , USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx , USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);
-uint32_t          USB_ReadInterrupts (USB_TypeDef *USBx);
-uint32_t          USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx);
-uint32_t          USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum);
-uint32_t          USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx);
-uint32_t          USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum);
-void              USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt);
-
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
-void USB_WritePMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
-void USB_ReadPMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
-#endif /* USB */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#endif /* STM32F102x6 || STM32F102xB || */
-       /* STM32F103x6 || STM32F103xB || */
-       /* STM32F103xE || STM32F103xG || */
-       /* STM32F105xC || STM32F107xC    */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F1xx_LL_USB_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/TARGET_NUCLEO_F103RB/system_stm32f1xx.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,118 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f10x.h
-  * @author  MCD Application Team
-  * @version V4.1.0
-  * @date    29-April-2016
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32F10X_H
-#define __SYSTEM_STM32F10X_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup STM32F10x_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32F10x_System_Exported_types
-  * @{
-  */
-
-extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
-extern const uint8_t  AHBPrescTable[16];  /*!< AHB prescalers table values */
-extern const uint8_t  APBPrescTable[8];   /*!< APB prescalers table values */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Exported_Functions
-  * @{
-  */
-  
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-extern void SetSysClock(void);
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32F10X_H */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/M24SR-DISCOVERY_hardware/mbed/Ticker.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,129 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TICKER_H
-#define MBED_TICKER_H
-
-#include "TimerEvent.h"
-#include "Callback.h"
-
-namespace mbed {
-
-/** A Ticker is used to call a function at a recurring interval
- *
- *  You can use as many seperate Ticker objects as you require.
- *
- * @Note Synchronization level: Interrupt safe
- *
- * Example:
- * @code
- * // Toggle the blinking led after 5 seconds
- *
- * #include "mbed.h"
- *
- * Ticker timer;
- * DigitalOut led1(LED1);
- * DigitalOut led2(LED2);
- *
- * int flip = 0;
- *
- * void attime() {
- *     flip = !flip;
- * }
- *
- * int main() {
- *     timer.attach(&attime, 5);
- *     while(1) {
- *         if(flip == 0) {
- *             led1 = !led1;
- *         } else {
- *             led2 = !led2;
- *         }
- *         wait(0.2);
- *     }
- * }
- * @endcode
- */
-class Ticker : public TimerEvent {
-
-public:
-    Ticker() : TimerEvent() {
-    }
-
-    Ticker(const ticker_data_t *data) : TimerEvent(data) {
-        data->interface->init();
-    }
-
-    /** Attach a function to be called by the Ticker, specifiying the interval in seconds
-     *
-     *  @param func pointer to the function to be called
-     *  @param t the time between calls in seconds
-     */
-    void attach(Callback<void()> func, float t) {
-        attach_us(func, t * 1000000.0f);
-    }
-
-    /** Attach a member function to be called by the Ticker, specifiying the interval in seconds
-     *
-     *  @param obj pointer to the object to call the member function on
-     *  @param method pointer to the member function to be called
-     *  @param t the time between calls in seconds
-     */
-    template<typename T, typename M>
-    void attach(T *obj, M method, float t) {
-        attach(Callback<void()>(obj, method), t);
-    }
-
-    /** Attach a function to be called by the Ticker, specifiying the interval in micro-seconds
-     *
-     *  @param fptr pointer to the function to be called
-     *  @param t the time between calls in micro-seconds
-     */
-    void attach_us(Callback<void()> func, timestamp_t t) {
-        _function.attach(func);
-        setup(t);
-    }
-
-    /** Attach a member function to be called by the Ticker, specifiying the interval in micro-seconds
-     *
-     *  @param tptr pointer to the object to call the member function on
-     *  @param mptr pointer to the member function to be called
-     *  @param t the time between calls in micro-seconds
-     */
-    template<typename T, typename M>
-    void attach_us(T *obj, M method, timestamp_t t) {
-        attach_us(Callback<void()>(obj, method), t);
-    }
-
-    virtual ~Ticker() {
-        detach();
-    }
-
-    /** Detach the function
-     */
-    void detach();
-
-protected:
-    void setup(timestamp_t t);
-    virtual void handler();
-
-protected:
-    timestamp_t         _delay;     /**< Time delay (in microseconds) for re-setting the multi-shot callback. */
-    Callback<void()>    _function;  /**< Callback. */
-};
-
-} // namespace mbed
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/Timeout.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,61 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TIMEOUT_H
-#define MBED_TIMEOUT_H
-
-#include "Ticker.h"
-
-namespace mbed {
-
-/** A Timeout is used to call a function at a point in the future
- *
- * You can use as many seperate Timeout objects as you require.
- *
- * @Note Synchronization level: Interrupt safe
- *
- * Example:
- * @code
- * // Blink until timeout.
- *
- * #include "mbed.h"
- *
- * Timeout timeout;
- * DigitalOut led(LED1);
- *
- * int on = 1;
- *
- * void attimeout() {
- *     on = 0;
- * }
- *
- * int main() {
- *     timeout.attach(&attimeout, 5);
- *     while(on) {
- *         led = !led;
- *         wait(0.2);
- *     }
- * }
- * @endcode
- */
-class Timeout : public Ticker {
-
-protected:
-    virtual void handler();
-};
-
-} // namespace mbed
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/Timer.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,93 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TIMER_H
-#define MBED_TIMER_H
-
-#include "platform.h"
-#include "ticker_api.h"
-
-namespace mbed {
-
-/** A general purpose timer
- *
- * @Note Synchronization level: Interrupt safe
- *
- * Example:
- * @code
- * // Count the time to toggle a LED
- *
- * #include "mbed.h"
- *
- * Timer timer;
- * DigitalOut led(LED1);
- * int begin, end;
- *
- * int main() {
- *     timer.start();
- *     begin = timer.read_us();
- *     led = !led;
- *     end = timer.read_us();
- *     printf("Toggle the led takes %d us", end - begin);
- * }
- * @endcode
- */
-class Timer {
-
-public:
-    Timer();
-    Timer(const ticker_data_t *data);
-
-    /** Start the timer
-     */
-    void start();
-
-    /** Stop the timer
-     */
-    void stop();
-
-    /** Reset the timer to 0.
-     *
-     * If it was already counting, it will continue
-     */
-    void reset();
-
-    /** Get the time passed in seconds
-     */
-    float read();
-
-    /** Get the time passed in mili-seconds
-     */
-    int read_ms();
-
-    /** Get the time passed in micro-seconds
-     */
-    int read_us();
-
-    /** An operator shorthand for read()
-     */
-    operator float();
-
-protected:
-    int slicetime();
-    int _running;          // whether the timer is running
-    unsigned int _start;   // the start time of the latest slice
-    int _time;             // any accumulated time from previous slices
-    const ticker_data_t *_ticker_data;
-};
-
-} // namespace mbed
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/TimerEvent.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,58 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TIMEREVENT_H
-#define MBED_TIMEREVENT_H
-
-#include "ticker_api.h"
-#include "us_ticker_api.h"
-
-namespace mbed {
-
-/** Base abstraction for timer interrupts
- *
- * @Note Synchronization level: Interrupt safe
- */
-class TimerEvent {
-public:
-    TimerEvent();
-    TimerEvent(const ticker_data_t *data);
-
-    /** The handler registered with the underlying timer interrupt
-     */
-    static void irq(uint32_t id);
-
-    /** Destruction removes it...
-     */
-    virtual ~TimerEvent();
-
-protected:
-    // The handler called to service the timer event of the derived class
-    virtual void handler() = 0;
-
-    // insert in to linked list
-    void insert(timestamp_t timestamp);
-
-    // remove from linked list, if in it
-    void remove();
-
-    ticker_event_t event;
-
-    const ticker_data_t *_ticker_data;
-};
-
-} // namespace mbed
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/Transaction.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,75 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TRANSACTION_H
-#define MBED_TRANSACTION_H
-
-#include "platform.h"
-#include "FunctionPointer.h"
-
-namespace mbed {
-
-/** Transaction structure
- */
-typedef struct {
-    void *tx_buffer;           /**< Tx buffer */
-    size_t tx_length;          /**< Length of Tx buffer*/
-    void *rx_buffer;           /**< Rx buffer */
-    size_t rx_length;          /**< Length of Rx buffer */
-    uint32_t event;            /**< Event for a transaction */
-    event_callback_t callback; /**< User's callback */
-    uint8_t width;             /**< Buffer's word width (8, 16, 32, 64) */
-} transaction_t;
-
-/** Transaction class defines a transaction.
- *
- * @Note Synchronization level: Not protected
- */
-template<typename Class>
-class Transaction {
-public:
-    Transaction(Class *tpointer, const transaction_t& transaction) : _obj(tpointer), _data(transaction) {
-    }
-
-    Transaction() : _obj(), _data() {
-    }
-
-    ~Transaction() {
-    }
-
-    /** Get object's instance for the transaction
-     *
-     * @return The object which was stored
-     */
-    Class* get_object() {
-        return _obj;
-    }
-
-    /** Get the transaction
-     *
-     * @return The transaction which was stored
-     */
-    transaction_t* get_transaction() {
-        return &_data;
-    }
-
-private:
-    Class* _obj;
-    transaction_t _data;
-};
-
-}
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/analogin_api.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,66 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGIN_API_H
-#define MBED_ANALOGIN_API_H
-
-#include "device.h"
-
-#if DEVICE_ANALOGIN
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Analogin hal structure. analogin_s is declared in the target's hal
- */
-typedef struct analogin_s analogin_t;
-
-/**
- * \defgroup hal_analogin Analogin hal functions
- * @{
- */
-
-/** Initialize the analogin peripheral
- *
- * Configures the pin used by analogin.
- * @param obj The analogin object to initialize
- * @param pin The analogin pin name
- */
-void analogin_init(analogin_t *obj, PinName pin);
-
-/** Read the input voltage, represented as a float in the range [0.0, 1.0]
- *
- * @param obj The analogin object
- * @return A floating value representing the current input voltage
- */
-float analogin_read(analogin_t *obj);
-
-/** Read the value from analogin pin, represented as an unsigned 16bit value
- *
- * @param obj The analogin object
- * @return An unsigned 16bit value representing the current input voltage
- */
-uint16_t analogin_read_u16(analogin_t *obj);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/analogout_api.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,88 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGOUT_API_H
-#define MBED_ANALOGOUT_API_H
-
-#include "device.h"
-
-#if DEVICE_ANALOGOUT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Analogout hal structure. dac_s is declared in the target's hal
- */
-typedef struct dac_s dac_t;
-
-/**
- * \defgroup hal_analogout Analogout hal functions
- * @{
- */
-
-/** Initialize the analogout peripheral
- *
- * Configures the pin used by analogout.
- * @param obj The analogout object to initialize
- * @param pin The analogout pin name
- */
-void analogout_init(dac_t *obj, PinName pin);
-
-/** Release the analogout object
- *
- * Note: This is not currently used in the mbed-drivers
- * @param obj The analogout object
- */
-void analogout_free(dac_t *obj);
-
-/** Set the output voltage, specified as a percentage (float)
- *
- * @param obj The analogin object
- * @param value The floating-point output voltage to be set
- */
-void analogout_write(dac_t *obj, float value);
-
-/** Set the output voltage, specified as unsigned 16-bit
- *
- * @param obj The analogin object
- * @param value The unsigned 16-bit output voltage to be set
- */
-void analogout_write_u16(dac_t *obj, uint16_t value);
-
-/** Read the current voltage value on the pin
- *
- * @param obj The analogin object
- * @return A floating-point value representing the current voltage on the pin,
- *     measured as a percentage
- */
-float analogout_read(dac_t *obj);
-
-/** Read the current voltage value on the pin, as a normalized unsigned 16bit value
- *
- * @param obj The analogin object
- * @return An unsigned 16-bit value representing the current voltage on the pin
- */
-uint16_t analogout_read_u16(dac_t *obj);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/buffer.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,30 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2014-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_BUFFER_H
-#define MBED_BUFFER_H
-
-#include <stddef.h>
-
-/** Generic buffer structure
- */
-typedef struct buffer_s {
-    void    *buffer; /**< the pointer to a buffer */
-    size_t   length; /**< the buffer length */
-    size_t   pos;    /**< actual buffer position */
-    uint8_t  width;  /**< The buffer unit width (8, 16, 32, 64), used for proper *buffer casting */
-} buffer_t;
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/can_api.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,80 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2016 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CAN_API_H
-#define MBED_CAN_API_H
-
-#include "device.h"
-
-#if DEVICE_CAN
-
-#include "PinNames.h"
-#include "PeripheralNames.h"
-#include "can_helper.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    IRQ_RX,
-    IRQ_TX,
-    IRQ_ERROR,
-    IRQ_OVERRUN,
-    IRQ_WAKEUP,
-    IRQ_PASSIVE,
-    IRQ_ARB,
-    IRQ_BUS,
-    IRQ_READY
-} CanIrqType;
-
-
-typedef enum {
-    MODE_RESET,
-    MODE_NORMAL,
-    MODE_SILENT,
-    MODE_TEST_LOCAL,
-    MODE_TEST_GLOBAL,
-    MODE_TEST_SILENT
-} CanMode;
-
-typedef void (*can_irq_handler)(uint32_t id, CanIrqType type);
-
-typedef struct can_s can_t;
-
-void          can_init     (can_t *obj, PinName rd, PinName td);
-void          can_free     (can_t *obj);
-int           can_frequency(can_t *obj, int hz);
-
-void          can_irq_init (can_t *obj, can_irq_handler handler, uint32_t id);
-void          can_irq_free (can_t *obj);
-void          can_irq_set  (can_t *obj, CanIrqType irq, uint32_t enable);
-
-int           can_write    (can_t *obj, CAN_Message, int cc);
-int           can_read     (can_t *obj, CAN_Message *msg, int handle);
-int           can_mode     (can_t *obj, CanMode mode);
-int           can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle);
-void          can_reset    (can_t *obj);
-unsigned char can_rderror  (can_t *obj);
-unsigned char can_tderror  (can_t *obj);
-void          can_monitor  (can_t *obj, int silent);
-
-#ifdef __cplusplus
-};
-#endif
-
-#endif    // MBED_CAN_API_H
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/can_helper.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CAN_HELPER_H
-#define MBED_CAN_HELPER_H
-
-#if DEVICE_CAN
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-enum CANFormat {
-    CANStandard = 0,
-    CANExtended = 1,
-    CANAny = 2
-};
-typedef enum CANFormat CANFormat;
-
-enum CANType {
-    CANData   = 0,
-    CANRemote = 1
-};
-typedef enum CANType CANType;
-
-struct CAN_Message {
-    unsigned int   id;                 // 29 bit identifier
-    unsigned char  data[8];            // Data field
-    unsigned char  len;                // Length of data field in bytes
-    CANFormat      format;             // 0 - STANDARD, 1- EXTENDED IDENTIFIER
-    CANType        type;               // 0 - DATA FRAME, 1 - REMOTE FRAME
-};
-typedef struct CAN_Message CAN_Message;
-
-#ifdef __cplusplus
-};
-#endif
-
-#endif
-
-#endif // MBED_CAN_HELPER_H

--- a/M24SR-DISCOVERY_hardware/mbed/critical.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,354 +0,0 @@
-/*
- * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __MBED_UTIL_CRITICAL_H__
-#define __MBED_UTIL_CRITICAL_H__
-
-#include <stdbool.h>
-#include <stdint.h>
-#include <stddef.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/** Determine the current interrupts enabled state
-  *
-  * This function can be called to determine whether or not interrupts are currently enabled.
-  * \note
-  * NOTE:
-  * This function works for both cortex-A and cortex-M, although the underlyng implementation
-  * differs.
-  * @return true if interrupts are enabled, false otherwise
-  */
-bool core_util_are_interrupts_enabled(void);
-
-/** Mark the start of a critical section
-  *
-  * This function should be called to mark the start of a critical section of code.
-  * \note
-  * NOTES:
-  * 1) The use of this style of critical section is targetted at C based implementations.
-  * 2) These critical sections can be nested.
-  * 3) The interrupt enable state on entry to the first critical section (of a nested set, or single
-  *    section) will be preserved on exit from the section.
-  * 4) This implementation will currently only work on code running in privileged mode.
-  */
-void core_util_critical_section_enter(void);
-
-/** Mark the end of a critical section
-  *
-  * This function should be called to mark the end of a critical section of code.
-  * \note
-  * NOTES:
-  * 1) The use of this style of critical section is targetted at C based implementations.
-  * 2) These critical sections can be nested.
-  * 3) The interrupt enable state on entry to the first critical section (of a nested set, or single
-  *    section) will be preserved on exit from the section.
-  * 4) This implementation will currently only work on code running in privileged mode.
-  */
-void core_util_critical_section_exit(void);
-
-/**
- * Atomic compare and set. It compares the contents of a memory location to a
- * given value and, only if they are the same, modifies the contents of that
- * memory location to a given new value. This is done as a single atomic
- * operation. The atomicity guarantees that the new value is calculated based on
- * up-to-date information; if the value had been updated by another thread in
- * the meantime, the write would fail due to a mismatched expectedCurrentValue.
- *
- * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
- * you to the article on compare-and swap].
- *
- * @param  ptr                  The target memory location.
- * @param[in,out] expectedCurrentValue A pointer to some location holding the
- *                              expected current value of the data being set atomically.
- *                              The computed 'desiredValue' should be a function of this current value.
- *                              @Note: This is an in-out parameter. In the
- *                              failure case of atomic_cas (where the
- *                              destination isn't set), the pointee of expectedCurrentValue is
- *                              updated with the current value.
- * @param[in] desiredValue      The new value computed based on '*expectedCurrentValue'.
- *
- * @return                      true if the memory location was atomically
- *                              updated with the desired value (after verifying
- *                              that it contained the expectedCurrentValue),
- *                              false otherwise. In the failure case,
- *                              exepctedCurrentValue is updated with the new
- *                              value of the target memory location.
- *
- * pseudocode:
- * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
- *     if *p != *old {
- *         *old = *p
- *         return false
- *     }
- *     *p = new
- *     return true
- * }
- *
- * @Note: In the failure case (where the destination isn't set), the value
- * pointed to by expectedCurrentValue is still updated with the current value.
- * This property helps writing concise code for the following incr:
- *
- * function incr(p : pointer to int, a : int) returns int {
- *     done = false
- *     value = *p // This fetch operation need not be atomic.
- *     while not done {
- *         done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
- *     }
- *     return value + a
- * }
- */
-bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue);
-
-/**
- * Atomic compare and set. It compares the contents of a memory location to a
- * given value and, only if they are the same, modifies the contents of that
- * memory location to a given new value. This is done as a single atomic
- * operation. The atomicity guarantees that the new value is calculated based on
- * up-to-date information; if the value had been updated by another thread in
- * the meantime, the write would fail due to a mismatched expectedCurrentValue.
- *
- * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
- * you to the article on compare-and swap].
- *
- * @param  ptr                  The target memory location.
- * @param[in,out] expectedCurrentValue A pointer to some location holding the
- *                              expected current value of the data being set atomically.
- *                              The computed 'desiredValue' should be a function of this current value.
- *                              @Note: This is an in-out parameter. In the
- *                              failure case of atomic_cas (where the
- *                              destination isn't set), the pointee of expectedCurrentValue is
- *                              updated with the current value.
- * @param[in] desiredValue      The new value computed based on '*expectedCurrentValue'.
- *
- * @return                      true if the memory location was atomically
- *                              updated with the desired value (after verifying
- *                              that it contained the expectedCurrentValue),
- *                              false otherwise. In the failure case,
- *                              exepctedCurrentValue is updated with the new
- *                              value of the target memory location.
- *
- * pseudocode:
- * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
- *     if *p != *old {
- *         *old = *p
- *         return false
- *     }
- *     *p = new
- *     return true
- * }
- *
- * @Note: In the failure case (where the destination isn't set), the value
- * pointed to by expectedCurrentValue is still updated with the current value.
- * This property helps writing concise code for the following incr:
- *
- * function incr(p : pointer to int, a : int) returns int {
- *     done = false
- *     value = *p // This fetch operation need not be atomic.
- *     while not done {
- *         done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
- *     }
- *     return value + a
- * }
- */
-bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue);
-
-/**
- * Atomic compare and set. It compares the contents of a memory location to a
- * given value and, only if they are the same, modifies the contents of that
- * memory location to a given new value. This is done as a single atomic
- * operation. The atomicity guarantees that the new value is calculated based on
- * up-to-date information; if the value had been updated by another thread in
- * the meantime, the write would fail due to a mismatched expectedCurrentValue.
- *
- * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
- * you to the article on compare-and swap].
- *
- * @param  ptr                  The target memory location.
- * @param[in,out] expectedCurrentValue A pointer to some location holding the
- *                              expected current value of the data being set atomically.
- *                              The computed 'desiredValue' should be a function of this current value.
- *                              @Note: This is an in-out parameter. In the
- *                              failure case of atomic_cas (where the
- *                              destination isn't set), the pointee of expectedCurrentValue is
- *                              updated with the current value.
- * @param[in] desiredValue      The new value computed based on '*expectedCurrentValue'.
- *
- * @return                      true if the memory location was atomically
- *                              updated with the desired value (after verifying
- *                              that it contained the expectedCurrentValue),
- *                              false otherwise. In the failure case,
- *                              exepctedCurrentValue is updated with the new
- *                              value of the target memory location.
- *
- * pseudocode:
- * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
- *     if *p != *old {
- *         *old = *p
- *         return false
- *     }
- *     *p = new
- *     return true
- * }
- *
- * @Note: In the failure case (where the destination isn't set), the value
- * pointed to by expectedCurrentValue is still updated with the current value.
- * This property helps writing concise code for the following incr:
- *
- * function incr(p : pointer to int, a : int) returns int {
- *     done = false
- *     value = *p // This fetch operation need not be atomic.
- *     while not done {
- *         done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
- *     }
- *     return value + a
- * }
- */
-bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue);
-
-/**
- * Atomic compare and set. It compares the contents of a memory location to a
- * given value and, only if they are the same, modifies the contents of that
- * memory location to a given new value. This is done as a single atomic
- * operation. The atomicity guarantees that the new value is calculated based on
- * up-to-date information; if the value had been updated by another thread in
- * the meantime, the write would fail due to a mismatched expectedCurrentValue.
- *
- * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
- * you to the article on compare-and swap].
- *
- * @param  ptr                  The target memory location.
- * @param[in,out] expectedCurrentValue A pointer to some location holding the
- *                              expected current value of the data being set atomically.
- *                              The computed 'desiredValue' should be a function of this current value.
- *                              @Note: This is an in-out parameter. In the
- *                              failure case of atomic_cas (where the
- *                              destination isn't set), the pointee of expectedCurrentValue is
- *                              updated with the current value.
- * @param[in] desiredValue      The new value computed based on '*expectedCurrentValue'.
- *
- * @return                      true if the memory location was atomically
- *                              updated with the desired value (after verifying
- *                              that it contained the expectedCurrentValue),
- *                              false otherwise. In the failure case,
- *                              exepctedCurrentValue is updated with the new
- *                              value of the target memory location.
- *
- * pseudocode:
- * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
- *     if *p != *old {
- *         *old = *p
- *         return false
- *     }
- *     *p = new
- *     return true
- * }
- *
- * @Note: In the failure case (where the destination isn't set), the value
- * pointed to by expectedCurrentValue is still updated with the current value.
- * This property helps writing concise code for the following incr:
- *
- * function incr(p : pointer to int, a : int) returns int {
- *     done = false
- *     value = *p // This fetch operation need not be atomic.
- *     while not done {
- *         done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
- *     }
- *     return value + a
- * }
- */
-bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *desiredValue);
-
-/**
- * Atomic increment.
- * @param  valuePtr Target memory location being incremented.
- * @param  delta    The amount being incremented.
- * @return          The new incremented value.
- */
-uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta);
-
-/**
- * Atomic increment.
- * @param  valuePtr Target memory location being incremented.
- * @param  delta    The amount being incremented.
- * @return          The new incremented value.
- */
-uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta);
-
-/**
- * Atomic increment.
- * @param  valuePtr Target memory location being incremented.
- * @param  delta    The amount being incremented.
- * @return          The new incremented value.
- */
-uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta);
-
-/**
- * Atomic increment.
- * @param  valuePtr Target memory location being incremented.
- * @param  delta    The amount being incremented in bytes.
- * @return          The new incremented value.
- *
- * @note The type of the pointer argument is not taken into account
- *       and the pointer is incremented by bytes.
- */
-void *core_util_atomic_incr_ptr(void **valuePtr, ptrdiff_t delta);
-
-/**
- * Atomic decrement.
- * @param  valuePtr Target memory location being decremented.
- * @param  delta    The amount being decremented.
- * @return          The new decremented value.
- */
-uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta);
-
-/**
- * Atomic decrement.
- * @param  valuePtr Target memory location being decremented.
- * @param  delta    The amount being decremented.
- * @return          The new decremented value.
- */
-uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta);
-
-/**
- * Atomic decrement.
- * @param  valuePtr Target memory location being decremented.
- * @param  delta    The amount being decremented.
- * @return          The new decremented value.
- */
-uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta);
-
-/**
- * Atomic decrement.
- * @param  valuePtr Target memory location being decremented.
- * @param  delta    The amount being decremented in bytes.
- * @return          The new decremented value.
- *
- * @note The type of the pointer argument is not taken into account
- *       and the pointer is decremented by bytes
- */
-void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta);
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-
-#endif // __MBED_UTIL_CRITICAL_H__

--- a/M24SR-DISCOVERY_hardware/mbed/dma_api.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2014-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DMA_API_H
-#define MBED_DMA_API_H
-
-#include <stdint.h>
-
-#define DMA_ERROR_OUT_OF_CHANNELS (-1)
-
-typedef enum {
-    DMA_USAGE_NEVER,
-    DMA_USAGE_OPPORTUNISTIC,
-    DMA_USAGE_ALWAYS,
-    DMA_USAGE_TEMPORARY_ALLOCATED,
-    DMA_USAGE_ALLOCATED
-} DMAUsage;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void dma_init(void);
-
-int dma_channel_allocate(uint32_t capabilities);
-
-int dma_channel_free(int channelid);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/ethernet_api.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,63 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ETHERNET_API_H
-#define MBED_ETHERNET_API_H
-
-#include "device.h"
-
-#if DEVICE_ETHERNET
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// Connection constants
-
-int ethernet_init(void);
-void ethernet_free(void);
-
-// write size bytes from data to ethernet buffer
-// return num bytes written
-// or -1 if size is too big
-int ethernet_write(const char *data, int size);
-
-// send ethernet write buffer, returning the packet size sent
-int ethernet_send(void);
-
-// recieve from ethernet buffer, returning packet size, or 0 if no packet
-int ethernet_receive(void);
-
-// read size bytes in to data, return actual num bytes read (0..size)
-// if data == NULL, throw the bytes away
-int ethernet_read(char *data, int size);
-
-// get the ethernet address
-void ethernet_address(char *mac);
-
-// see if the link is up
-int ethernet_link(void);
-
-// force link settings
-void ethernet_set_link(int speed, int duplex);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
-

--- a/M24SR-DISCOVERY_hardware/mbed/gpio_api.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,128 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_API_H
-#define MBED_GPIO_API_H
-
-#include <stdint.h>
-#include "device.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_gpio GPIO HAL functions
- * @{
- */
-
-/** Set the given pin as GPIO
- *
- * @param pin The pin to be set as GPIO
- * @return The GPIO port mask for this pin
- **/
-uint32_t gpio_set(PinName pin);
-/* Checks if gpio object is connected (pin was not initialized with NC)
- * @param pin The pin to be set as GPIO
- * @return 0 if port is initialized with NC
- **/
-int gpio_is_connected(const gpio_t *obj);
-
-/** Initialize the GPIO pin
- *
- * @param obj The GPIO object to initialize
- * @param pin The GPIO pin to initialize
- */
-void gpio_init(gpio_t *obj, PinName pin);
-
-/** Set the input pin mode
- *
- * @param obj  The GPIO object
- * @param mode The pin mode to be set
- */
-void gpio_mode(gpio_t *obj, PinMode mode);
-
-/** Set the pin direction
- *
- * @param obj       The GPIO object
- * @param direction The pin direction to be set
- */
-void gpio_dir(gpio_t *obj, PinDirection direction);
-
-/** Set the output value
- *
- * @param obj   The GPIO object
- * @param value The value to be set
- */
-void gpio_write(gpio_t *obj, int value);
-
-/** Read the input value
- *
- * @param obj The GPIO object
- * @return An integer value 1 or 0
- */
-int gpio_read(gpio_t *obj);
-
-// the following functions are generic and implemented in the common gpio.c file
-// TODO: fix, will be moved to the common gpio header file
-
-/** Init the input pin and set mode to PullDefault
- *
- * @param obj The GPIO object
- * @param pin The pin name
- */
-void gpio_init_in(gpio_t* gpio, PinName pin);
-
-/** Init the input pin and set the mode
- *
- * @param obj  The GPIO object
- * @param pin  The pin name
- * @param mode The pin mode to be set
- */
-void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode);
-
-/** Init the output pin as an output, with predefined output value 0
- *
- * @param obj The GPIO object
- * @param pin The pin name
- * @return An integer value 1 or 0
- */
-void gpio_init_out(gpio_t* gpio, PinName pin);
-
-/** Init the pin as an output and set the output value
- *
- * @param obj   The GPIO object
- * @param pin   The pin name
- * @param value The value to be set
- */
-void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value);
-
-/** Init the pin to be in/out
- *
- * @param obj       The GPIO object
- * @param pin       The pin name
- * @param direction The pin direction to be set
- * @param mode      The pin mode to be set
- * @param value     The value to be set for an output pin
- */
-void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/gpio_irq_api.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,92 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_IRQ_API_H
-#define MBED_GPIO_IRQ_API_H
-
-#include "device.h"
-
-#if DEVICE_INTERRUPTIN
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** GPIO IRQ events
- */
-typedef enum {
-    IRQ_NONE,
-    IRQ_RISE,
-    IRQ_FALL
-} gpio_irq_event;
-
-/** GPIO IRQ HAL structure. gpio_irq_s is declared in the target's HAL
- */
-typedef struct gpio_irq_s gpio_irq_t;
-
-typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);
-
-/**
- * \defgroup hal_gpioirq GPIO IRQ HAL functions
- * @{
- */
-
-/** Initialize the GPIO IRQ pin
- *
- * @param obj     The GPIO object to initialize
- * @param pin     The GPIO pin name
- * @param handler The handler to be attached to GPIO IRQ
- * @param id      The object ID (id != 0, 0 is reserved)
- * @return -1 if pin is NC, 0 otherwise
- */
-int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id);
-
-/** Release the GPIO IRQ PIN
- *
- * @param obj The gpio object
- */
-void gpio_irq_free(gpio_irq_t *obj);
-
-/** Enable/disable pin IRQ event
- *
- * @param obj    The GPIO object
- * @param event  The GPIO IRQ event
- * @param enable The enable flag
- */
-void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable);
-
-/** Enable GPIO IRQ
- *
- * This is target dependent, as it might enable the entire port or just a pin
- * @param obj The GPIO object
- */
-void gpio_irq_enable(gpio_irq_t *obj);
-
-/** Disable GPIO IRQ
- *
- * This is target dependent, as it might disable the entire port or just a pin
- * @param obj The GPIO object
- */
-void gpio_irq_disable(gpio_irq_t *obj);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/i2c_api.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,241 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_I2C_API_H
-#define MBED_I2C_API_H
-
-#include "device.h"
-#include "buffer.h"
-
-#if DEVICE_I2C_ASYNCH
-#include "dma_api.h"
-#endif
-
-#if DEVICE_I2C
-
-/**
- * @defgroup hal_I2CEvents I2C Events Macros
- *
- * @{
- */
-#define I2C_EVENT_ERROR               (1 << 1)
-#define I2C_EVENT_ERROR_NO_SLAVE      (1 << 2)
-#define I2C_EVENT_TRANSFER_COMPLETE   (1 << 3)
-#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4)
-#define I2C_EVENT_ALL                 (I2C_EVENT_ERROR |  I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK)
-
-/**@}*/
-
-#if DEVICE_I2C_ASYNCH
-/** Asynch I2C HAL structure
- */
-typedef struct {
-    struct i2c_s    i2c;     /**< Target specific I2C structure */
-    struct buffer_s tx_buff; /**< Tx buffer */
-    struct buffer_s rx_buff; /**< Rx buffer */
-} i2c_t;
-
-#else
-/** Non-asynch I2C HAL structure
- */
-typedef struct i2c_s i2c_t;
-
-#endif
-
-enum {
-  I2C_ERROR_NO_SLAVE = -1,
-  I2C_ERROR_BUS_BUSY = -2
-};
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_GeneralI2C I2C Configuration Functions
- * @{
- */
-
-/** Initialize the I2C peripheral. It sets the default parameters for I2C
- *  peripheral, and configures its specifieds pins.
- *  
- *  @param obj  The I2C object
- *  @param sda  The sda pin
- *  @param scl  The scl pin
- */
-void i2c_init(i2c_t *obj, PinName sda, PinName scl);
-
-/** Configure the I2C frequency
- *
- *  @param obj The I2C object
- *  @param hz  Frequency in Hz
- */
-void i2c_frequency(i2c_t *obj, int hz);
-
-/** Send START command
- *
- *  @param obj The I2C object
- */
-int  i2c_start(i2c_t *obj);
-
-/** Send STOP command
- *
- *  @param obj The I2C object
- */
-int  i2c_stop(i2c_t *obj);
-
-/** Blocking reading data
- *
- *  @param obj     The I2C object
- *  @param address 7-bit address (last bit is 1)
- *  @param data    The buffer for receiving
- *  @param length  Number of bytes to read
- *  @param stop    Stop to be generated after the transfer is done
- *  @return Number of read bytes
- */
-int i2c_read(i2c_t *obj, int address, char *data, int length, int stop);
-
-/** Blocking sending data
- *
- *  @param obj     The I2C object
- *  @param address 7-bit address (last bit is 0)
- *  @param data    The buffer for sending
- *  @param length  Number of bytes to write
- *  @param stop    Stop to be generated after the transfer is done
- *  @return Number of written bytes
- */
-int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop);
-
-/** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop()
- *
- *  @param obj The I2C object
- */
-void i2c_reset(i2c_t *obj);
-
-/** Read one byte
- *
- *  @param obj The I2C object
- *  @param last Acknoledge
- *  @return The read byte
- */
-int i2c_byte_read(i2c_t *obj, int last);
-
-/** Write one byte
- *
- *  @param obj The I2C object
- *  @param data Byte to be written
- *  @return 0 if NAK was received, 1 if ACK was received, 2 for timeout.
- */
-int i2c_byte_write(i2c_t *obj, int data);
-
-/**@}*/
-
-#if DEVICE_I2CSLAVE
-
-/**
- * \defgroup SynchI2C Synchronous I2C Hardware Abstraction Layer for slave
- * @{
- */
-
-/** Configure I2C as slave or master.
- *  @param obj The I2C object
- *  @return non-zero if a value is available
- */
-void i2c_slave_mode(i2c_t *obj, int enable_slave);
-
-/** Check to see if the I2C slave has been addressed.
- *  @param obj The I2C object
- *  @return The status - 1 - read addresses, 2 - write to all slaves,
- *         3 write addressed, 0 - the slave has not been addressed
- */
-int  i2c_slave_receive(i2c_t *obj);
-
-/** Configure I2C as slave or master.
- *  @param obj The I2C object
- *  @return non-zero if a value is available
- */
-int  i2c_slave_read(i2c_t *obj, char *data, int length);
-
-/** Configure I2C as slave or master.
- *  @param obj The I2C object
- *  @return non-zero if a value is available
- */
-int  i2c_slave_write(i2c_t *obj, const char *data, int length);
-
-/** Configure I2C address.
- *  @param obj     The I2C object
- *  @param idx     Currently not used
- *  @param address The address to be set
- *  @param mask    Currently not used
- */
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
-
-#endif
-
-/**@}*/
-
-#if DEVICE_I2C_ASYNCH
-
-/**
- * \defgroup hal_AsynchI2C Asynchronous I2C Hardware Abstraction Layer
- * @{
- */
-
-/** Start I2C asynchronous transfer
- *
- *  @param obj       The I2C object
- *  @param tx        The transmit buffer
- *  @param tx_length The number of bytes to transmit
- *  @param rx        The receive buffer
- *  @param rx_length The number of bytes to receive
- *  @param address   The address to be set - 7bit or 9bit
- *  @param stop      If true, stop will be generated after the transfer is done
- *  @param handler   The I2C IRQ handler to be set
- *  @param hint      DMA hint usage
- */
-void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint);
-
-/** The asynchronous IRQ handler
- *
- *  @param obj The I2C object which holds the transfer information
- *  @return Event flags if a transfer termination condition was met, otherwise return 0.
- */
-uint32_t i2c_irq_handler_asynch(i2c_t *obj);
-
-/** Attempts to determine if the I2C peripheral is already in use
- *
- *  @param obj The I2C object
- *  @return Non-zero if the I2C module is active or zero if it is not
- */
-uint8_t i2c_active(i2c_t *obj);
-
-/** Abort asynchronous transfer
- *
- *  This function does not perform any check - that should happen in upper layers.
- *  @param obj The I2C object
- */
-void i2c_abort_asynch(i2c_t *obj);
-
-#endif
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/lp_ticker_api.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,82 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_LPTICKER_API_H
-#define MBED_LPTICKER_API_H
-
-#include "device.h"
-
-#if DEVICE_LOWPOWERTIMER
-
-#include "ticker_api.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_LpTicker Low Power Ticker Functions
- * @{
- */
-
-/** Get low power ticker's data
- *
- * @return The low power ticker data
- */
-const ticker_data_t* get_lp_ticker_data(void);
-
-/** The wrapper for ticker_irq_handler, to pass lp ticker's data
- *
- */
-void lp_ticker_irq_handler(void);
-
-/* HAL lp ticker */
-
-/** Initialize the low power ticker
- *
- */
-void lp_ticker_init(void);
-
-/** Read the current counter
- *
- * @return The current timer's counter value in microseconds
- */
-uint32_t lp_ticker_read(void);
-
-/** Set interrupt for specified timestamp
- *
- * @param timestamp The time in microseconds to be set
- */
-void lp_ticker_set_interrupt(timestamp_t timestamp);
-
-/** Disable low power ticker interrupt
- *
- */
-void lp_ticker_disable_interrupt(void);
-
-/** Clear the low power ticker interrupt
- *
- */
-void lp_ticker_clear_interrupt(void);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/mbed.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,83 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_H
-#define MBED_H
-
-#define MBED_LIBRARY_VERSION 125
-
-#if MBED_CONF_RTOS_PRESENT
-#include "rtos/rtos.h"
-#endif
-
-#if MBED_CONF_NSAPI_PRESENT
-#include "network-socket/nsapi.h"
-#endif
-
-#include "toolchain.h"
-#include "platform.h"
-
-// Useful C libraries
-#include <math.h>
-#include <time.h>
-
-// mbed Debug libraries
-#include "mbed_error.h"
-#include "mbed_interface.h"
-#include "mbed_assert.h"
-
-// mbed Peripheral components
-#include "DigitalIn.h"
-#include "DigitalOut.h"
-#include "DigitalInOut.h"
-#include "BusIn.h"
-#include "BusOut.h"
-#include "BusInOut.h"
-#include "PortIn.h"
-#include "PortInOut.h"
-#include "PortOut.h"
-#include "AnalogIn.h"
-#include "AnalogOut.h"
-#include "PwmOut.h"
-#include "Serial.h"
-#include "SPI.h"
-#include "SPISlave.h"
-#include "I2C.h"
-#include "I2CSlave.h"
-#include "Ethernet.h"
-#include "CAN.h"
-#include "RawSerial.h"
-
-// mbed Internal components
-#include "Timer.h"
-#include "Ticker.h"
-#include "Timeout.h"
-#include "LowPowerTimeout.h"
-#include "LowPowerTicker.h"
-#include "LowPowerTimer.h"
-#include "LocalFileSystem.h"
-#include "InterruptIn.h"
-#include "wait_api.h"
-#include "sleep_api.h"
-#include "rtc_time.h"
-
-// mbed Non-hardware components
-#include "Callback.h"
-#include "FunctionPointer.h"
-
-using namespace mbed;
-using namespace std;
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/mbed_assert.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ASSERT_H
-#define MBED_ASSERT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Internal mbed assert function which is invoked when MBED_ASSERT macro failes.
- *  This function is active only if NDEBUG is not defined prior to including this
- *  assert header file.
- *  In case of MBED_ASSERT failing condition, error() is called with the assertation message.
- *  @param expr Expresion to be checked.
- *  @param file File where assertation failed.
- *  @param line Failing assertation line number.
- */
-void mbed_assert_internal(const char *expr, const char *file, int line);
-
-#ifdef __cplusplus
-}
-#endif
-
-#ifdef NDEBUG
-#define MBED_ASSERT(expr) ((void)0)
-
-#else
-#define MBED_ASSERT(expr)                                \
-do {                                                     \
-    if (!(expr)) {                                       \
-        mbed_assert_internal(#expr, __FILE__, __LINE__); \
-    }                                                    \
-} while (0)
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/mbed_debug.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,66 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DEBUG_H
-#define MBED_DEBUG_H
-#include "device.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if DEVICE_STDIO_MESSAGES
-#include <stdio.h>
-#include <stdarg.h>
-
-/** Output a debug message
- *
- * @param format printf-style format string, followed by variables
- */
-static inline void debug(const char *format, ...) {
-    va_list args;
-    va_start(args, format);
-    vfprintf(stderr, format, args);
-    va_end(args);
-}
-
-/** Conditionally output a debug message
- *
- * NOTE: If the condition is constant false (!= 1) and the compiler optimization
- * level is greater than 0, then the whole function will be compiled away.
- *
- * @param condition output only if condition is true (== 1)
- * @param format printf-style format string, followed by variables
- */
-static inline void debug_if(int condition, const char *format, ...) {
-    if (condition == 1) {
-        va_list args;
-        va_start(args, format);
-        vfprintf(stderr, format, args);
-        va_end(args);
-    }
-}
-
-#else
-static inline void debug(const char *format, ...) {}
-static inline void debug_if(int condition, const char *format, ...) {}
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/mbed_error.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,66 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ERROR_H
-#define MBED_ERROR_H
-
-/** To generate a fatal compile-time error, you can use the pre-processor #error directive.
- *
- * @code
- * #error "That shouldn't have happened!"
- * @endcode
- *
- * If the compiler evaluates this line, it will report the error and stop the compile.
- *
- * For example, you could use this to check some user-defined compile-time variables:
- *
- * @code
- * #define NUM_PORTS 7
- * #if (NUM_PORTS > 4)
- *     #error "NUM_PORTS must be less than 4"
- * #endif
- * @endcode
- *
- * Reporting Run-Time Errors:
- * To generate a fatal run-time error, you can use the mbed error() function.
- *
- * @code
- * error("That shouldn't have happened!");
- * @endcode
- *
- * If the mbed running the program executes this function, it will print the
- * message via the USB serial port, and then die with the blue lights of death!
- *
- * The message can use printf-style formatting, so you can report variables in the
- * message too. For example, you could use this to check a run-time condition:
- *
- * @code
- * if(x >= 5) {
- *     error("expected x to be less than 5, but got %d", x);
- * }
- * #endcode
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void error(const char* format, ...);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/mbed_interface.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,130 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_INTERFACE_H
-#define MBED_INTERFACE_H
-
-#include <stdarg.h>
-
-#include "device.h"
-
-/* Mbed interface mac address
- * if MBED_MAC_ADD_x are zero, interface uid sets mac address,
- * otherwise MAC_ADD_x are used.
- */
-#define MBED_MAC_ADDR_INTERFACE 0x00
-#define MBED_MAC_ADDR_0  MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_1  MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_2  MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_3  MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_4  MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_5  MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDRESS_SUM (MBED_MAC_ADDR_0 | MBED_MAC_ADDR_1 | MBED_MAC_ADDR_2 | MBED_MAC_ADDR_3 | MBED_MAC_ADDR_4 | MBED_MAC_ADDR_5)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if DEVICE_SEMIHOST
-
-/** Functions to control the mbed interface
- *
- * mbed Microcontrollers have a built-in interface to provide functionality such as
- * drag-n-drop download, reset, serial-over-usb, and access to the mbed local file
- * system. These functions provide means to control the interface suing semihost
- * calls it supports.
- */
-
-/** Determine whether the mbed interface is connected, based on whether debug is enabled
- *
- *  @returns
- *    1 if interface is connected,
- *    0 otherwise
- */
-int mbed_interface_connected(void);
-
-/** Instruct the mbed interface to reset, as if the reset button had been pressed
- *
- *  @returns
- *    1 if successful,
- *    0 otherwise (e.g. interface not present)
- */
-int mbed_interface_reset(void);
-
-/** This will disconnect the debug aspect of the interface, so semihosting will be disabled.
- * The interface will still support the USB serial aspect
- *
- *  @returns
- *    0 if successful,
- *   -1 otherwise (e.g. interface not present)
- */
-int mbed_interface_disconnect(void);
-
-/** This will disconnect the debug aspect of the interface, and if the USB cable is not
- * connected, also power down the interface. If the USB cable is connected, the interface
- * will remain powered up and visible to the host
- *
- *  @returns
- *    0 if successful,
- *   -1 otherwise (e.g. interface not present)
- */
-int mbed_interface_powerdown(void);
-
-/** This returns a string containing the 32-character UID of the mbed interface
- *  This is a weak function that can be overwritten if required
- *
- *  @param uid A 33-byte array to write the null terminated 32-byte string
- *
- *  @returns
- *    0 if successful,
- *   -1 otherwise (e.g. interface not present)
- */
-int mbed_interface_uid(char *uid);
-
-#endif
-
-/** This returns a unique 6-byte MAC address, based on the interface UID
- * If the interface is not present, it returns a default fixed MAC address (00:02:F7:F0:00:00)
- *
- * This is a weak function that can be overwritten if you want to provide your own mechanism to
- * provide a MAC address.
- *
- *  @param mac A 6-byte array to write the MAC address
- */
-void mbed_mac_address(char *mac);
-
-/** Cause the mbed to flash the BLOD (Blue LEDs Of Death) sequence
- */
-void mbed_die(void);
-
-/** Print out an error message.  This is typically called when
- * hanlding a crash.
- *
- * @Note Synchronization level: Interrupt safe
- */
-void mbed_error_printf(const char* format, ...);
-
-/** Print out an error message.  Similar to mbed_error_printf
- * but uses a va_list.
- *
- * @Note Synchronization level: Interrupt safe
- */
-void mbed_error_vfprintf(const char * format, va_list arg);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/pinmap.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINMAP_H
-#define MBED_PINMAP_H
-
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-    PinName pin;
-    int peripheral;
-    int function;
-} PinMap;
-
-void pin_function(PinName pin, int function);
-void pin_mode    (PinName pin, PinMode mode);
-
-uint32_t pinmap_peripheral(PinName pin, const PinMap* map);
-uint32_t pinmap_function(PinName pin, const PinMap* map);
-uint32_t pinmap_merge     (uint32_t a, uint32_t b);
-void     pinmap_pinout    (PinName pin, const PinMap *map);
-uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map);
-uint32_t pinmap_find_function(PinName pin, const PinMap* map);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/platform.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,28 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PLATFORM_H
-#define MBED_PLATFORM_H
-
-#include "device.h"
-#include "PinNames.h"
-#include "PeripheralNames.h"
-
-#include <cstddef>
-#include <cstdlib>
-#include <cstdio>
-#include <cstring>
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/port_api.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,88 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTMAP_H
-#define MBED_PORTMAP_H
-
-#include "device.h"
-
-#if DEVICE_PORTIN || DEVICE_PORTOUT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Port HAL structure. port_s is declared in the target's HAL
- */
-typedef struct port_s port_t;
-
-/**
- * \defgroup hal_port Port HAL functions
- * @{
- */
-
-/** Get the pin name from the port's pin number
- *
- * @param port  The port name
- * @param pin_n The pin number within the specified port
- * @return The pin name for the port's pin number
- */
-PinName port_pin(PortName port, int pin_n);
-
-/** Initilize the port
- *
- * @param obj  The port object to initialize
- * @param port The port name
- * @param mask The bitmask to identify which bits in the port should be included (0 - ignore)
- * @param dir  The port direction
- */
-void port_init(port_t *obj, PortName port, int mask, PinDirection dir);
-
-/** Set the input port mode
- *
- * @param obj  The port object
- * @param mode THe port mode to be set
- */
-void port_mode(port_t *obj, PinMode mode);
-
-/** Set port direction (in/out)
- *
- * @param obj The port object
- * @param dir The port direction to be set
- */
-void port_dir(port_t *obj, PinDirection dir);
-
-/** Write value to the port
- *
- * @param obj   The port object
- * @param value The value to be set
- */
-void port_write(port_t *obj, int value);
-
-/** Read the current value on the port
- *
- * @param obj The port object
- * @return An integer with each bit corresponding to an associated port pin setting
- */
-int port_read(port_t *obj);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/pwmout_api.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,115 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PWMOUT_API_H
-#define MBED_PWMOUT_API_H
-
-#include "device.h"
-
-#if DEVICE_PWMOUT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Pwmout hal structure. pwmout_s is declared in the target's hal
- */
-typedef struct pwmout_s pwmout_t;
-
-/**
- * \defgroup hal_pwmout Pwmout hal functions
- * @{
- */
-
-/** Initialize the pwm out peripheral and configure the pin
- *
- * @param obj The pwmout object to initialize
- * @param pin The pwmout pin to initialize
- */
-void pwmout_init(pwmout_t *obj, PinName pin);
-
-/** Deinitialize the pwmout object
- *
- * @param obj The pwmout object
- */
-void pwmout_free(pwmout_t *obj);
-
-/** Set the output duty-cycle in range <0.0f, 1.0f>
- *
- * Value 0.0f represents 0 percentage, 1.0f represents 100 percent.
- * @param obj     The pwmout object
- * @param percent The floating-point percentage number
- */
-void pwmout_write(pwmout_t *obj, float percent);
-
-/** Read the current float-point output duty-cycle
- *
- * @param obj The pwmout object
- * @return A floating-point output duty-cycle
- */
-float pwmout_read(pwmout_t *obj);
-
-/** Set the PWM period specified in seconds, keeping the duty cycle the same
- *
- * Periods smaller than microseconds (the lowest resolution) are set to zero.
- * @param obj     The pwmout object
- * @param seconds The floating-point seconds period
- */
-void pwmout_period(pwmout_t *obj, float seconds);
-
-/** Set the PWM period specified in miliseconds, keeping the duty cycle the same
- *
- * @param obj The pwmout object
- * @param ms  The milisecond period
- */
-void pwmout_period_ms(pwmout_t *obj, int ms);
-
-/** Set the PWM period specified in microseconds, keeping the duty cycle the same
- *
- * @param obj The pwmout object
- * @param us  The microsecond period
- */
-void pwmout_period_us(pwmout_t *obj, int us);
-
-/** Set the PWM pulsewidth specified in seconds, keeping the period the same.
- *
- * @param obj     The pwmout object
- * @param seconds The floating-point pulsewidth in seconds
- */
-void pwmout_pulsewidth(pwmout_t *obj, float seconds);
-
-/** Set the PWM pulsewidth specified in miliseconds, keeping the period the same.
- *
- * @param obj The pwmout object
- * @param ms  The floating-point pulsewidth in miliseconds
- */
-void pwmout_pulsewidth_ms(pwmout_t *obj, int ms);
-
-/** Set the PWM pulsewidth specified in microseconds, keeping the period the same.
- *
- * @param obj The pwmout object
- * @param us  The floating-point pulsewidth in microseconds
- */
-void pwmout_pulsewidth_us(pwmout_t *obj, int us);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/rtc_api.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,72 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_RTC_API_H
-#define MBED_RTC_API_H
-
-#include "device.h"
-
-#if DEVICE_RTC
-
-#include <time.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_rtc RTC hal functions
- * @{
- */
-
-/** Initialize the RTC peripheral
- *
- */
-void rtc_init(void);
-
-/** Deinitialize RTC
- *
- * TODO: The function is not used by rtc api in mbed-drivers.
- */
-void rtc_free(void);
-
-/** Get the RTC enable status
- *
- * @retval 0 disabled
- * @retval 1 enabled
- */
-int rtc_isenabled(void);
-
-/** Get the current time from the RTC peripheral
- *
- * @return The current time
- */
-time_t rtc_read(void);
-
-/** Set the current time to the RTC peripheral
- *
- * @param t The current time to be set
- */
-void rtc_write(time_t t);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/rtc_time.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,87 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include <time.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Implementation of the C time.h functions
- *
- * Provides mechanisms to set and read the current time, based
- * on the microcontroller Real-Time Clock (RTC), plus some
- * standard C manipulation and formating functions.
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * int main() {
- *     set_time(1256729737);  // Set RTC time to Wed, 28 Oct 2009 11:35:37
- *
- *     while(1) {
- *         time_t seconds = time(NULL);
- *
- *         printf("Time as seconds since January 1, 1970 = %d\n", seconds);
- *
- *         printf("Time as a basic string = %s", ctime(&seconds));
- *
- *         char buffer[32];
- *         strftime(buffer, 32, "%I:%M %p\n", localtime(&seconds));
- *         printf("Time as a custom formatted string = %s", buffer);
- *
- *         wait(1);
- *     }
- * }
- * @endcode
- */
-
-/** Set the current time
- *
- * Initialises and sets the time of the microcontroller Real-Time Clock (RTC)
- * to the time represented by the number of seconds since January 1, 1970
- * (the UNIX timestamp).
- *
- * @param t Number of seconds since January 1, 1970 (the UNIX timestamp)
- *
- * @Note Synchronization level: Thread safe
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * int main() {
- *     set_time(1256729737); // Set time to Wed, 28 Oct 2009 11:35:37
- * }
- * @endcode
- */
-void set_time(time_t t);
-
-/** Attach an external RTC to be used for the C time functions
- *
- * @Note Synchronization level: Thread safe
- *
- * @param read_rtc pointer to function which returns current UNIX timestamp
- * @param write_rtc pointer to function which sets current UNIX timestamp, can be NULL
- * @param init_rtc pointer to funtion which initializes RTC, can be NULL
- * @param isenabled_rtc pointer to function wich returns if the rtc is enabled, can be NULL
- */
-void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void));
-
-#ifdef __cplusplus
-}
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/semihost_api.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,93 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SEMIHOST_H
-#define MBED_SEMIHOST_H
-
-#include "device.h"
-#include "toolchain.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if DEVICE_SEMIHOST
-
-#ifndef __CC_ARM
-
-#if defined(__ICCARM__)
-static inline int __semihost(int reason, const void *arg) {
-    return __semihosting(reason, (void*)arg);
-}
-#else
-
-#ifdef __thumb__
-#   define AngelSWI            0xAB
-#   define AngelSWIInsn        "bkpt"
-#   define AngelSWIAsm          bkpt
-#else
-#   define AngelSWI            0x123456
-#   define AngelSWIInsn        "swi"
-#   define AngelSWIAsm          swi
-#endif
-
-static inline int __semihost(int reason, const void *arg) {
-    int value;
-
-    asm volatile (
-       "mov r0, %1"          "\n\t"
-       "mov r1, %2"          "\n\t"
-       AngelSWIInsn " %a3"   "\n\t"
-       "mov %0, r0"
-       : "=r" (value)                                         /* output operands             */
-       : "r" (reason), "r" (arg), "i" (AngelSWI)              /* input operands              */
-       : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc"   /* list of clobbered registers */
-    );
-
-    return value;
-}
-#endif
-#endif
-
-#if DEVICE_LOCALFILESYSTEM
-FILEHANDLE semihost_open(const char* name, int openmode);
-int semihost_close (FILEHANDLE fh);
-int semihost_read  (FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode);
-int semihost_write (FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode);
-int semihost_ensure(FILEHANDLE fh);
-long semihost_flen (FILEHANDLE fh);
-int semihost_seek  (FILEHANDLE fh, long position);
-int semihost_istty (FILEHANDLE fh);
-
-int semihost_remove(const char *name);
-int semihost_rename(const char *old_name, const char *new_name);
-#endif
-
-int semihost_uid(char *uid);
-int semihost_reset(void);
-int semihost_vbus(void);
-int semihost_powerdown(void);
-int semihost_exit(void);
-
-int semihost_connected(void);
-int semihost_disabledebug(void);
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/serial_api.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,302 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SERIAL_API_H
-#define MBED_SERIAL_API_H
-
-#include "device.h"
-#include "buffer.h"
-#include "dma_api.h"
-
-#if DEVICE_SERIAL
-
-#define SERIAL_EVENT_TX_SHIFT (2)
-#define SERIAL_EVENT_RX_SHIFT (8)
-
-#define SERIAL_EVENT_TX_MASK (0x00FC)
-#define SERIAL_EVENT_RX_MASK (0x3F00)
-
-#define SERIAL_EVENT_ERROR (1 << 1)
-
-/**
- * @defgroup SerialTXEvents Serial TX Events Macros
- *
- * @{
- */
-#define SERIAL_EVENT_TX_COMPLETE (1 << (SERIAL_EVENT_TX_SHIFT + 0))
-#define SERIAL_EVENT_TX_ALL      (SERIAL_EVENT_TX_COMPLETE)
-/**@}*/
-
-/**
- * @defgroup SerialRXEvents Serial RX Events Macros
- *
- * @{
- */
-#define SERIAL_EVENT_RX_COMPLETE        (1 << (SERIAL_EVENT_RX_SHIFT + 0))
-#define SERIAL_EVENT_RX_OVERRUN_ERROR   (1 << (SERIAL_EVENT_RX_SHIFT + 1))
-#define SERIAL_EVENT_RX_FRAMING_ERROR   (1 << (SERIAL_EVENT_RX_SHIFT + 2))
-#define SERIAL_EVENT_RX_PARITY_ERROR    (1 << (SERIAL_EVENT_RX_SHIFT + 3))
-#define SERIAL_EVENT_RX_OVERFLOW        (1 << (SERIAL_EVENT_RX_SHIFT + 4))
-#define SERIAL_EVENT_RX_CHARACTER_MATCH (1 << (SERIAL_EVENT_RX_SHIFT + 5))
-#define SERIAL_EVENT_RX_ALL             (SERIAL_EVENT_RX_OVERFLOW | SERIAL_EVENT_RX_PARITY_ERROR | \
-                                         SERIAL_EVENT_RX_FRAMING_ERROR | SERIAL_EVENT_RX_OVERRUN_ERROR | \
-                                         SERIAL_EVENT_RX_COMPLETE | SERIAL_EVENT_RX_CHARACTER_MATCH)
-/**@}*/
-
-#define SERIAL_RESERVED_CHAR_MATCH (255)
-
-typedef enum {
-    ParityNone = 0,
-    ParityOdd = 1,
-    ParityEven = 2,
-    ParityForced1 = 3,
-    ParityForced0 = 4
-} SerialParity;
-
-typedef enum {
-    RxIrq,
-    TxIrq
-} SerialIrq;
-
-typedef enum {
-    FlowControlNone,
-    FlowControlRTS,
-    FlowControlCTS,
-    FlowControlRTSCTS
-} FlowControl;
-
-typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);
-
-#if DEVICE_SERIAL_ASYNCH
-/** Asynch serial HAL structure
- */
-typedef struct {
-    struct serial_s serial;  /**< Target specific serial structure */
-    struct buffer_s tx_buff; /**< TX buffer */
-    struct buffer_s rx_buff; /**< RX buffer */
-    uint8_t char_match;      /**< Character to be matched */
-    uint8_t char_found;      /**< State of the matched character */
-} serial_t;
-
-#else
-/** Non-asynch serial HAL structure
- */
-typedef struct serial_s serial_t;
-
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_GeneralSerial Serial Configuration Functions
- * @{
- */
-
-/** Initialize the serial peripheral. It sets the default parameters for serial
- *  peripheral, and configures its specifieds pins.
- *
- * @param obj The serial object
- * @param tx  The TX pin name
- * @param rx  The RX pin name
- */
-void serial_init(serial_t *obj, PinName tx, PinName rx);
-
-/** Release the serial peripheral, not currently invoked. It requires further
- *  resource management.
- *
- * @param obj The serial object
- */
-void serial_free(serial_t *obj);
-
-/** Configure the baud rate
- *
- * @param obj      The serial object
- * @param baudrate The baud rate to be configured
- */
-void serial_baud(serial_t *obj, int baudrate);
-
-/** Configure the format. Set the number of bits, parity and the number of stop bits
- *
- * @param obj       The serial object
- * @param data_bits The number of data bits
- * @param parity    The parity
- * @param stop_bits The number of stop bits
- */
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
-
-/** The serial interrupt handler registration
- *
- * @param obj     The serial object
- * @param handler The interrupt handler which will be invoked when the interrupt fires
- * @param id      The SerialBase object
- */
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id);
-
-/** Configure serial interrupt. This function is used for word-approach
- *
- * @param obj    The serial object
- * @param irq    The serial IRQ type (RX or TX)
- * @param enable Set to non-zero to enable events, or zero to disable them
- */
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable);
-
-/** Get character. This is a blocking call, waiting for a character
- *
- * @param obj The serial object
- */
-int  serial_getc(serial_t *obj);
-
-/** Send a character. This is a blocking call, waiting for a peripheral to be available
- *  for writing
- *
- * @param obj The serial object
- * @param c   The character to be sent
- */
-void serial_putc(serial_t *obj, int c);
-
-/** Check if the serial peripheral is readable
- *
- * @param obj The serial object
- * @return Non-zero value if a character can be read, 0 if nothing to read
- */
-int  serial_readable(serial_t *obj);
-
-/** Check if the serial peripheral is writable
- *
- * @param obj The serial object
- * @return Non-zero value if a character can be written, 0 otherwise.
- */
-int  serial_writable(serial_t *obj);
-
-/** Clear the serial peripheral
- *
- * @param obj The serial object
- */
-void serial_clear(serial_t *obj);
-
-/** Set the break
- *
- * @param obj The serial object
- */
-void serial_break_set(serial_t *obj);
-
-/** Clear the break
- *
- * @param obj The serial object
- */
-void serial_break_clear(serial_t *obj);
-
-/** Configure the TX pin for UART function.
- *
- * @param tx The pin name used for TX
- */
-void serial_pinout_tx(PinName tx);
-
-/** Configure the serial for the flow control. It sets flow control in the hardware
- *  if a serial peripheral supports it, otherwise software emulation is used.
- *
- * @param obj    The serial object
- * @param type   The type of the flow control. Look at the available FlowControl types.
- * @param rxflow The TX pin name
- * @param txflow The RX pin name
- */
-void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow);
-
-#if DEVICE_SERIAL_ASYNCH
-
-/**@}*/
-
-/**
- * \defgroup hal_AsynchSerial Asynchronous Serial Hardware Abstraction Layer
- * @{
- */
-
-/** Begin asynchronous TX transfer. The used buffer is specified in the serial object,
- *  tx_buff
- *
- * @param obj       The serial object
- * @param tx        The transmit buffer
- * @param tx_length The number of bytes to transmit
- * @param tx_width  Deprecated argument
- * @param handler   The serial handler
- * @param event     The logical OR of events to be registered
- * @param hint      A suggestion for how to use DMA with this transfer
- * @return Returns number of data transfered, otherwise returns 0
- */
-int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint);
-
-/** Begin asynchronous RX transfer (enable interrupt for data collecting)
- *  The used buffer is specified in the serial object - rx_buff
- *
- * @param obj        The serial object
- * @param rx         The receive buffer
- * @param rx_length  The number of bytes to receive
- * @param rx_width   Deprecated argument
- * @param handler    The serial handler
- * @param event      The logical OR of events to be registered
- * @param handler    The serial handler
- * @param char_match A character in range 0-254 to be matched
- * @param hint       A suggestion for how to use DMA with this transfer
- */
-void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint);
-
-/** Attempts to determine if the serial peripheral is already in use for TX
- *
- * @param obj The serial object
- * @return Non-zero if the RX transaction is ongoing, 0 otherwise
- */
-uint8_t serial_tx_active(serial_t *obj);
-
-/** Attempts to determine if the serial peripheral is already in use for RX
- *
- * @param obj The serial object
- * @return Non-zero if the RX transaction is ongoing, 0 otherwise
- */
-uint8_t serial_rx_active(serial_t *obj);
-
-/** The asynchronous TX and RX handler.
- *
- * @param obj The serial object
- * @return Returns event flags if an RX transfer termination condition was met; otherwise returns 0
- */
-int serial_irq_handler_asynch(serial_t *obj);
-
-/** Abort the ongoing TX transaction. It disables the enabled interupt for TX and
- *  flushes the TX hardware buffer if TX FIFO is used
- *
- * @param obj The serial object
- */
-void serial_tx_abort_asynch(serial_t *obj);
-
-/** Abort the ongoing RX transaction. It disables the enabled interrupt for RX and
- *  flushes the RX hardware buffer if RX FIFO is used
- *
- * @param obj The serial object
- */
-void serial_rx_abort_asynch(serial_t *obj);
-
-/**@}*/
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/sleep_api.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,64 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SLEEP_API_H
-#define MBED_SLEEP_API_H
-
-#include "device.h"
-
-#if DEVICE_SLEEP
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Send the microcontroller to sleep
- *
- * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
- * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
- * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
- * memory state are maintained, and the peripherals continue to work and can generate interrupts.
- *
- * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
- *
- * @note
- *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
- * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
- * able to access the LocalFileSystem
- */
-void sleep(void);
-
-/** Send the microcontroller to deep sleep
- *
- * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
- * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
- * is still maintained.
- *
- * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
- *
- * @note
- *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
- * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
- * able to access the LocalFileSystem
- */
-void deepsleep(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/spi_api.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,214 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SPI_API_H
-#define MBED_SPI_API_H
-
-#include "device.h"
-#include "dma_api.h"
-#include "buffer.h"
-
-#if DEVICE_SPI
-
-#define SPI_EVENT_ERROR       (1 << 1)
-#define SPI_EVENT_COMPLETE    (1 << 2)
-#define SPI_EVENT_RX_OVERFLOW (1 << 3)
-#define SPI_EVENT_ALL         (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
-
-#define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
-
-#define SPI_FILL_WORD         (0xFFFF)
-
-#if DEVICE_SPI_ASYNCH
-/** Asynch SPI HAL structure
- */
-typedef struct {
-    struct spi_s spi;        /**< Target specific SPI structure */
-    struct buffer_s tx_buff; /**< Tx buffer */
-    struct buffer_s rx_buff; /**< Rx buffer */
-} spi_t;
-
-#else
-/** Non-asynch SPI HAL structure
- */
-typedef struct spi_s spi_t;
-
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_GeneralSPI SPI Configuration Functions
- * @{
- */
-
-/** Initialize the SPI peripheral
- *
- * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
- * @param[out] obj  The SPI object to initialize
- * @param[in]  mosi The pin to use for MOSI
- * @param[in]  miso The pin to use for MISO
- * @param[in]  sclk The pin to use for SCLK
- * @param[in]  ssel The pin to use for SSEL
- */
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
-
-/** Release a SPI object
- *
- * TODO: spi_free is currently unimplemented
- * This will require reference counting at the C++ level to be safe
- *
- * Return the pins owned by the SPI object to their reset state
- * Disable the SPI peripheral
- * Disable the SPI clock
- * @param[in] obj The SPI object to deinitialize
- */
-void spi_free(spi_t *obj);
-
-/** Configure the SPI format
- *
- * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
- * The default bit order is MSB.
- * @param[in,out] obj   The SPI object to configure
- * @param[in]     bits  The number of bits per frame
- * @param[in]     mode  The SPI mode (clock polarity, phase, and shift direction)
- * @param[in]     slave Zero for master mode or non-zero for slave mode
- */
-void spi_format(spi_t *obj, int bits, int mode, int slave);
-
-/** Set the SPI baud rate
- *
- * Actual frequency may differ from the desired frequency due to available dividers and bus clock
- * Configures the SPI peripheral's baud rate
- * @param[in,out] obj The SPI object to configure
- * @param[in]     hz  The baud rate in Hz
- */
-void spi_frequency(spi_t *obj, int hz);
-
-/**@}*/
-/**
- * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
- * @{
- */
-
-/** Write a byte out in master mode and receive a value
- *
- * @param[in] obj   The SPI peripheral to use for sending
- * @param[in] value The value to send
- * @return Returns the value received during send
- */
-int  spi_master_write(spi_t *obj, int value);
-
-/** Check if a value is available to read
- *
- * @param[in] obj The SPI peripheral to check
- * @return non-zero if a value is available
- */
-int  spi_slave_receive(spi_t *obj);
-
-/** Get a received value out of the SPI receive buffer in slave mode
- *
- * Blocks until a value is available
- * @param[in] obj The SPI peripheral to read
- * @return The value received
- */
-int  spi_slave_read(spi_t *obj);
-
-/** Write a value to the SPI peripheral in slave mode
- *
- * Blocks until the SPI peripheral can be written to
- * @param[in] obj   The SPI peripheral to write
- * @param[in] value The value to write
- */
-void spi_slave_write(spi_t *obj, int value);
-
-/** Checks if the specified SPI peripheral is in use
- *
- * @param[in] obj The SPI peripheral to check
- * @return non-zero if the peripheral is currently transmitting
- */
-int  spi_busy(spi_t *obj);
-
-/** Get the module number
- *
- * @param[in] obj The SPI peripheral to check
- * @return The module number
- */
-uint8_t spi_get_module(spi_t *obj);
-
-/**@}*/
-
-#if DEVICE_SPI_ASYNCH
-/**
- * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
- * @{
- */
-
-/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
- *
- * @param[in] obj       The SPI object that holds the transfer information
- * @param[in] tx        The transmit buffer
- * @param[in] tx_length The number of bytes to transmit
- * @param[in] rx        The receive buffer
- * @param[in] rx_length The number of bytes to receive
- * @param[in] bit_width The bit width of buffer words
- * @param[in] event     The logical OR of events to be registered
- * @param[in] handler   SPI interrupt handler
- * @param[in] hint      A suggestion for how to use DMA with this transfer
- */
-void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
-
-/** The asynchronous IRQ handler
- *
- * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
- * conditions, such as buffer overflows or transfer complete.
- * @param[in] obj     The SPI object that holds the transfer information
- * @return Event flags if a transfer termination condition was met; otherwise 0.
- */
-uint32_t spi_irq_handler_asynch(spi_t *obj);
-
-/** Attempts to determine if the SPI peripheral is already in use
- *
- * If a temporary DMA channel has been allocated, peripheral is in use.
- * If a permanent DMA channel has been allocated, check if the DMA channel is in use.  If not, proceed as though no DMA
- * channel were allocated.
- * If no DMA channel is allocated, check whether tx and rx buffers have been assigned.  For each assigned buffer, check
- * if the corresponding buffer position is less than the buffer length.  If buffers do not indicate activity, check if
- * there are any bytes in the FIFOs.
- * @param[in] obj The SPI object to check for activity
- * @return Non-zero if the SPI port is active or zero if it is not.
- */
-uint8_t spi_active(spi_t *obj);
-
-/** Abort an SPI transfer
- *
- * @param obj The SPI peripheral to stop
- */
-void spi_abort_asynch(spi_t *obj);
-
-
-#endif
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif // __cplusplus
-
-#endif // SPI_DEVICE
-
-#endif // MBED_SPI_API_H

--- a/M24SR-DISCOVERY_hardware/mbed/targets.json	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,2038 +0,0 @@
-{
-    "Target": {
-        "core": null,
-        "default_toolchain": "ARM",
-        "supported_toolchains": null,
-        "extra_labels": [],
-        "is_disk_virtual": false,
-        "macros": [],
-        "device_has": [],
-        "features": [],
-        "detect_code": [],
-        "public": false,
-        "default_build": "standard"
-    },
-    "CM4_UARM": {
-        "inherits": ["Target"],
-        "core": "Cortex-M4",
-        "default_toolchain": "uARM",
-        "public": false,
-        "supported_toolchains": ["uARM"],
-        "default_build": "small"
-    },
-    "CM4_ARM": {
-        "inherits": ["Target"],
-        "core": "Cortex-M4",
-        "public": false,
-        "supported_toolchains": ["ARM"]
-    },
-    "CM4F_UARM": {
-        "inherits": ["Target"],
-        "core": "Cortex-M4F",
-        "default_toolchain": "uARM",
-        "public": false,
-        "supported_toolchains": ["uARM"],
-        "default_build": "small"
-    },
-    "CM4F_ARM": {
-        "inherits": ["Target"],
-        "core": "Cortex-M4F",
-        "public": false,
-        "supported_toolchains": ["ARM"]
-    },
-    "LPCTarget": {
-        "inherits": ["Target"],
-        "post_binary_hook": {"function": "LPCTargetCode.lpc_patch"},
-        "public": false
-    },
-    "LPC11C24": {
-        "inherits": ["LPCTarget"],
-        "core": "Cortex-M0",
-        "progen": {"target": "lpc11c24_301"},
-        "extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11CXX"],
-        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
-        "device_has": ["ANALOGIN", "CAN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"]
-    },
-    "LPC1114": {
-        "inherits": ["LPCTarget"],
-        "core": "Cortex-M0",
-        "default_toolchain": "uARM",
-        "extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11XX"],
-        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
-        "progen": {
-            "target": "lpc1114_102"
-        },
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
-        "default_build": "small",
-        "release_versions": ["2"]
-    },
-    "LPC11U24": {
-        "inherits": ["LPCTarget"],
-        "core": "Cortex-M0",
-        "default_toolchain": "uARM",
-        "extra_labels": ["NXP", "LPC11UXX", "LPC11U24_401"],
-        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
-        "progen": {
-            "target": "lpc11u24_201"
-        },
-        "detect_code": ["1040"],
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
-        "default_build": "small",
-        "release_versions": ["2"]
-    },
-    "OC_MBUINO": {
-        "inherits": ["LPC11U24"],
-        "macros": ["TARGET_LPC11U24"],
-        "progen": {
-            "target": "lpc11u24_201"
-        },
-        "extra_labels": ["NXP", "LPC11UXX"],
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
-        "release_versions": ["2"]
-    },
-    "LPC11U24_301": {
-        "inherits": ["LPCTarget"],
-        "core": "Cortex-M0",
-        "extra_labels": ["NXP", "LPC11UXX"],
-        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"]
-    },
-    "LPC11U34_421": {
-        "inherits": ["LPCTarget"],
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-    },
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-    },
-    "TEENSY3_1": {
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-        "post_binary_hook": {
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-        },
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-    },
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-        "public": false
-    },
-    "MCU_NRF51_16K_BOOT_S110": {
-        "inherits": ["MCU_NRF51_S110", "MCU_NRF51_16K_BOOT_BASE"],
-        "public": false
-    },
-    "MCU_NRF51_16K_OTA": {
-        "inherits": ["MCU_NRF51_16K_OTA_BASE"],
-        "extra_labels_add": ["MCU_NRF51_16K_S130"],
-        "macros_add": ["TARGET_MCU_NRF51_16K_S130"],
-        "public": false
-    },
-    "MCU_NRF51_16K_OTA_S110": {
-        "inherits": ["MCU_NRF51_S110", "MCU_NRF51_16K_OTA_BASE"],
-        "public": false
-    },
-    "MCU_NRF51_32K": {
-        "inherits": ["MCU_NRF51"],
-        "extra_labels_add": ["MCU_NORDIC_32K", "MCU_NRF51_32K"],
-        "macros_add": ["TARGET_MCU_NORDIC_32K", "TARGET_MCU_NRF51_32K"],
-        "public": false
-    },
-    "MCU_NRF51_32K_BOOT": {
-        "inherits": ["MCU_NRF51_32K"],
-        "MERGE_BOOTLOADER": true,
-        "extra_labels_add": ["MCU_NRF51_32K_BOOT"],
-        "macros_add": ["TARGET_MCU_NRF51_32K_BOOT", "TARGET_OTA_ENABLED"],
-        "public": false
-    },
-    "MCU_NRF51_32K_OTA": {
-        "inherits": ["MCU_NRF51_32K"],
-        "public": false,
-        "extra_labels_add": ["MCU_NRF51_32K_OTA"],
-        "macros_add": ["TARGET_MCU_NRF51_32K_OTA", "TARGET_OTA_ENABLED"],
-        "MERGE_SOFT_DEVICE": false
-    },
-    "NRF51822": {
-        "inherits": ["MCU_NRF51_16K"],
-        "progen": {"target": "mkit"},
-        "extra_labels_add": ["NRF51822", "NRF51822_MKIT"],
-        "macros_add": ["TARGET_NRF51822_MKIT"],
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
-        "release_versions": ["2"]
-    },
-    "NRF51822_BOOT": {
-        "inherits": ["MCU_NRF51_16K_BOOT"],
-        "extra_labels_add": ["NRF51822", "NRF51822_MKIT"],
-        "macros_add": ["TARGET_NRF51822_MKIT"],
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
-    },
-    "NRF51822_OTA": {
-        "inherits": ["MCU_NRF51_16K_OTA"],
-        "extra_labels_add": ["NRF51822", "NRF51822_MKIT"],
-        "macros_add": ["TARGET_NRF51822_MKIT"],
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
-    },
-    "ARCH_BLE": {
-        "supported_form_factors": ["ARDUINO"],
-        "inherits": ["MCU_NRF51_16K"],
-        "progen": {"target": "arch-ble"},
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
-        "release_versions": ["2"]
-    },
-    "ARCH_BLE_BOOT": {
-        "supported_form_factors": ["ARDUINO"],
-        "inherits": ["MCU_NRF51_16K_BOOT"],
-        "extra_labels_add": ["ARCH_BLE"],
-        "macros_add": ["TARGET_ARCH_BLE"]
-    },
-    "ARCH_BLE_OTA": {
-        "supported_form_factors": ["ARDUINO"],
-        "inherits": ["MCU_NRF51_16K_OTA"],
-        "extra_labels_add": ["ARCH_BLE"],
-        "macros_add": ["TARGET_ARCH_BLE"]
-    },
-    "ARCH_LINK": {
-        "supported_form_factors": ["ARDUINO"],
-        "inherits": ["MCU_NRF51_16K"],
-        "extra_labels_add": ["ARCH_BLE"],
-        "macros_add": ["TARGET_ARCH_BLE"]
-    },
-    "ARCH_LINK_BOOT": {
-        "supported_form_factors": ["ARDUINO"],
-        "inherits": ["MCU_NRF51_16K_BOOT"],
-        "extra_labels_add": ["ARCH_BLE", "ARCH_LINK"],
-        "macros_add": ["TARGET_ARCH_BLE", "TARGET_ARCH_LINK"]
-    },
-    "ARCH_LINK_OTA": {
-        "supported_form_factors": ["ARDUINO"],
-        "inherits": ["MCU_NRF51_16K_OTA"],
-        "extra_labels_add": ["ARCH_BLE", "ARCH_LINK"],
-        "macros_add": ["TARGET_ARCH_BLE", "TARGET_ARCH_LINK"]
-    },
-    "SEEED_TINY_BLE": {
-        "inherits": ["MCU_NRF51_16K"],
-        "progen": {"target": "seed-tinyble"},
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
-        "release_versions": ["2"]
-    },
-    "SEEED_TINY_BLE_BOOT": {
-        "inherits": ["MCU_NRF51_16K_BOOT"],
-        "extra_labels_add": ["SEEED_TINY_BLE"],
-        "macros_add": ["TARGET_SEEED_TINY_BLE"]
-    },
-    "SEEED_TINY_BLE_OTA": {
-        "inherits": ["MCU_NRF51_16K_OTA"],
-        "extra_labels_add": ["SEEED_TINY_BLE"],
-        "macros_add": ["TARGET_SEEED_TINY_BLE"]
-    },
-    "HRM1017": {
-        "inherits": ["MCU_NRF51_16K"],
-        "progen": {"target": "hrm1017"},
-        "macros_add": ["TARGET_NRF_LFCLK_RC"],
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
-        "release_versions": ["2"]
-    },
-    "HRM1017_BOOT": {
-        "inherits": ["MCU_NRF51_16K_BOOT"],
-        "extra_labels_add": ["HRM1017"],
-        "macros_add": ["TARGET_HRM1017", "TARGET_NRF_LFCLK_RC"]
-    },
-    "HRM1017_OTA": {
-        "inherits": ["MCU_NRF51_16K_OTA"],
-        "extra_labels_add": ["HRM1017"],
-        "macros_add": ["TARGET_HRM1017", "TARGET_NRF_LFCLK_RC"]
-    },
-    "RBLAB_NRF51822": {
-        "supported_form_factors": ["ARDUINO"],
-        "inherits": ["MCU_NRF51_16K"],
-        "progen": {"target": "rblab-nrf51822"},
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
-        "release_versions": ["2"]
-    },
-    "RBLAB_NRF51822_BOOT": {
-        "supported_form_factors": ["ARDUINO"],
-        "inherits": ["MCU_NRF51_16K_BOOT"],
-        "extra_labels_add": ["RBLAB_NRF51822"],
-        "macros_add": ["TARGET_RBLAB_NRF51822"]
-    },
-    "RBLAB_NRF51822_OTA": {
-        "supported_form_factors": ["ARDUINO"],
-        "inherits": ["MCU_NRF51_16K_OTA"],
-        "extra_labels_add": ["RBLAB_NRF51822"],
-        "macros_add": ["TARGET_RBLAB_NRF51822"]
-    },
-    "RBLAB_BLENANO": {
-        "inherits": ["MCU_NRF51_16K"],
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
-        "release_versions": ["2"]
-    },
-    "RBLAB_BLENANO_BOOT": {
-        "inherits": ["MCU_NRF51_16K_BOOT"],
-        "extra_labels_add": ["RBLAB_BLENANO"],
-        "macros_add": ["TARGET_RBLAB_BLENANO"]
-    },
-    "RBLAB_BLENANO_OTA": {
-        "inherits": ["MCU_NRF51_16K_OTA"],
-        "extra_labels_add": ["RBLAB_BLENANO"],
-        "macros_add": ["TARGET_RBLAB_BLENANO"]
-    },
-    "NRF51822_Y5_MBUG": {
-        "inherits": ["MCU_NRF51_16K"],
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
-    },
-    "WALLBOT_BLE": {
-        "inherits": ["MCU_NRF51_16K"],
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
-        "release_versions": ["2"]
-    },
-    "WALLBOT_BLE_BOOT": {
-        "inherits": ["MCU_NRF51_16K_BOOT"],
-        "extra_labels_add": ["WALLBOT_BLE"],
-        "macros_add": ["TARGET_WALLBOT_BLE"]
-    },
-    "WALLBOT_BLE_OTA": {
-        "inherits": ["MCU_NRF51_16K_OTA"],
-        "extra_labels_add": ["WALLBOT_BLE"],
-        "macros_add": ["TARGET_WALLBOT_BLE"]
-    },
-    "DELTA_DFCM_NNN40": {
-        "inherits": ["MCU_NRF51_32K"],
-        "program_cycle_s": 10,
-        "progen": {"target": "dfcm-nnn40"},
-        "macros_add": ["TARGET_NRF_LFCLK_RC"],
-        "device_has": ["ANALOGIN", "DEBUG_AWARENESS", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
-        "release_versions": ["2"]
-    },
-    "DELTA_DFCM_NNN40_BOOT": {
-        "inherits": ["MCU_NRF51_32K_BOOT"],
-        "program_cycle_s": 10,
-        "extra_labels_add": ["DELTA_DFCM_NNN40"],
-        "macros_add": ["TARGET_DELTA_DFCM_NNN40", "TARGET_NRF_LFCLK_RC"]
-    },
-    "DELTA_DFCM_NNN40_OTA": {
-        "inherits": ["MCU_NRF51_32K_OTA"],
-        "program_cycle_s": 10,
-        "extra_labels_add": ["DELTA_DFCM_NNN40"],
-        "macros_add": ["TARGET_DELTA_DFCM_NNN40", "TARGET_NRF_LFCLK_RC"]
-    },
-    "NRF51_DK_LEGACY": {
-        "supported_form_factors": ["ARDUINO"],
-        "inherits": ["MCU_NRF51_32K"],
-        "progen": {"target": "nrf51-dk"},
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
-    },
-    "NRF51_DK_BOOT": {
-        "supported_form_factors": ["ARDUINO"],
-        "inherits": ["MCU_NRF51_32K_BOOT"],
-        "extra_labels_add": ["NRF51_DK"],
-        "macros_add": ["TARGET_NRF51_DK"]
-    },
-    "NRF51_DK_OTA": {
-        "supported_form_factors": ["ARDUINO"],
-        "inherits": ["MCU_NRF51_32K_OTA"],
-        "extra_labels_add": ["NRF51_DK"],
-        "macros_add": ["TARGET_NRF51_DK"]
-    },
-    "NRF51_DONGLE": {
-        "inherits": ["MCU_NRF51_32K"],
-        "progen": {"target": "nrf51-dongle"},
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
-        "release_versions": ["2"]
-    },
-    "NRF51_DONGLE_BOOT": {
-        "inherits": ["MCU_NRF51_32K_BOOT"],
-        "extra_labels_add": ["NRF51_DONGLE"],
-        "macros_add": ["TARGET_NRF51_DONGLE"]
-    },
-    "NRF51_DONGLE_OTA": {
-        "inherits": ["MCU_NRF51_32K_OTA"],
-        "extra_labels_add": ["NRF51_DONGLE"],
-        "macros_add": ["TARGET_NRF51_DONGLE"]
-    },
-    "NRF51_MICROBIT": {
-        "inherits": ["MCU_NRF51_16K_S110"],
-        "macros_add": ["TARGET_NRF_LFCLK_RC"],
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
-        "release_versions": ["2"]
-    },
-    "NRF51_MICROBIT_BOOT": {
-        "inherits": ["MCU_NRF51_16K_BOOT_S110"],
-        "extra_labels_add": ["NRF51_MICROBIT"],
-        "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
-    },
-    "NRF51_MICROBIT_OTA": {
-        "inherits": ["MCU_NRF51_16K_OTA_S110"],
-        "extra_labels_add": ["NRF51_MICROBIT"],
-        "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
-    },
-    "NRF51_MICROBIT_B": {
-        "inherits": ["MCU_NRF51_16K"],
-        "extra_labels_add": ["NRF51_MICROBIT"],
-        "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"],
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
-        "release_versions": ["2"]
-    },
-    "NRF51_MICROBIT_B_BOOT": {
-        "inherits": ["MCU_NRF51_16K_BOOT"],
-        "extra_labels_add": ["NRF51_MICROBIT"],
-        "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
-    },
-    "NRF51_MICROBIT_B_OTA": {
-        "inherits": ["MCU_NRF51_16K_OTA"],
-        "extra_labels_add": ["NRF51_MICROBIT"],
-        "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
-    },
-
-    "TY51822R3": {
-        "inherits": ["MCU_NRF51_32K_UNIFIED"],
-        "macros_add": ["TARGET_NRF_32MHZ_XTAL"],
-        "progen": {"target": "ty51822r3"},
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
-        "detect_code": ["1019"],
-        "release_versions": ["2", "5"],
-        "overrides": { "uart_hwfc": 0 }
-    },
-    "TY51822R3_BOOT": {
-        "inherits": ["MCU_NRF51_32K_BOOT"],
-        "extra_labels_add": ["TY51822R3"],
-        "macros_add": ["TARGET_TY51822R3", "TARGET_NRF_32MHZ_XTAL"]
-    },
-    "TY51822R3_OTA": {
-        "inherits": ["MCU_NRF51_32K_OTA"],
-        "extra_labels_add": ["NRF51_DK"],
-        "macros_add": ["TARGET_TY51822R3", "TARGET_NRF_32MHZ_XTAL"]
-    },
-    "ARM_MPS2_Target": {
-        "inherits": ["Target"],
-        "public": false,
-        "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"]
-    },
-    "ARM_MPS2_M0": {
-        "inherits": ["ARM_MPS2_Target"],
-        "core": "Cortex-M0",
-        "supported_toolchains": ["ARM"],
-        "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M0"],
-        "macros": ["CMSDK_CM0"],
-        "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
-        "release_versions": ["2"]
-    },
-    "ARM_MPS2_M0P": {
-        "inherits": ["ARM_MPS2_Target"],
-        "core": "Cortex-M0+",
-        "supported_toolchains": ["ARM"],
-        "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M0P"],
-        "macros": ["CMSDK_CM0plus"],
-        "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
-        "release_versions": ["2"]
-    },
-    "ARM_MPS2_M1": {
-        "inherits": ["ARM_MPS2_Target"],
-        "core": "Cortex-M1",
-        "supported_toolchains": ["ARM"],
-        "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M1"],
-        "macros": ["CMSDK_CM1"],
-        "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"]
-    },
-    "ARM_MPS2_M3": {
-        "inherits": ["ARM_MPS2_Target"],
-        "core": "Cortex-M3",
-        "supported_toolchains": ["ARM"],
-        "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M3"],
-        "macros": ["CMSDK_CM3"],
-        "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
-        "release_versions": ["2"]
-    },
-    "ARM_MPS2_M4": {
-        "inherits": ["ARM_MPS2_Target"],
-        "core": "Cortex-M4F",
-        "supported_toolchains": ["ARM"],
-        "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M4"],
-        "macros": ["CMSDK_CM4"],
-        "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
-        "release_versions": ["2"]
-    },
-    "ARM_MPS2_M7": {
-        "inherits": ["ARM_MPS2_Target"],
-        "core": "Cortex-M7",
-        "supported_toolchains": ["ARM"],
-        "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M7"],
-        "macros": ["CMSDK_CM7"],
-        "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
-        "release_versions": ["2"]
-    },
-    "ARM_IOTSS_Target": {
-        "inherits": ["Target"],
-        "public": false,
-        "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"]
-    },
-    "ARM_IOTSS_BEID": {
-        "inherits": ["ARM_IOTSS_Target"],
-        "core": "Cortex-M3",
-        "supported_toolchains": ["ARM"],
-        "extra_labels": ["ARM_SSG", "IOTSS", "IOTSS_BEID"],
-        "macros": ["CMSDK_BEID"],
-        "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
-        "release_versions": ["2"]
-    },
-    "ARM_BEETLE_SOC": {
-        "inherits": ["ARM_IOTSS_Target"],
-        "core": "Cortex-M3",
-        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
-        "default_toolchain": "ARM",
-        "extra_labels": ["ARM_SSG", "BEETLE"],
-        "macros": ["CMSDK_BEETLE", "WSF_MS_PER_TICK=20", "WSF_TOKEN_ENABLED=FALSE", "WSF_TRACE_ENABLED=TRUE", "WSF_ASSERT_ENABLED=FALSE", "WSF_PRINTF_MAX_LEN=128", "ASIC", "CONFIG_HOST_REV=0x20", "CONFIG_ALLOW_DEEP_SLEEP=FALSE", "HCI_VS_TARGET", "CONFIG_ALLOW_SETTING_WRITE=TRUE", "WSF_MAX_HANDLERS=20", "NO_LEDS"],
-        "progen": {
-            "target": "beetle",
-            "uvision5": {
-                "template": ["uvision5_arm_beetle_soc.uvproj.tmpl"]
-            }
-        },
-        "device_has": ["ANALOGIN", "CLCD", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "SPI"],
-        "features": ["BLE"],
-        "release_versions": ["2", "5"]
-    },
-    "RZ_A1H": {
-        "supported_form_factors": ["ARDUINO"],
-        "core": "Cortex-A9",
-        "program_cycle_s": 2,
-        "extra_labels": ["RENESAS", "MBRZA1H"],
-        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
-        "inherits": ["Target"],
-        "progen": {
-            "target": "gr-peach",
-            "iar": {
-                "template": ["iar_rz_a1h.ewp.tmpl"]
-            }
-        },
-        "device_has": ["ANALOGIN", "CAN", "ERROR_PATTERN", "ETHERNET", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
-        "features": ["IPV4"],
-        "release_versions": ["2", "5"]
-    },
-    "VK_RZ_A1H": {
-        "inherits": ["Target"],
-        "core": "Cortex-A9",
-        "extra_labels": ["RENESAS", "VKRZA1H"],
-        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
-        "default_toolchain": "ARM",
-        "progen": {
-            "target": "vk-rza1h",
-            "iar": {
-                "template": ["iar_rz_a1h.ewp.tmpl"]
-            }
-        },
-        "program_cycle_s": 2,
-        "device_has": ["ANALOGIN", "CAN", "ERROR_PATTERN", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
-        "features": ["IPV4"],
-        "default_build": "standard",
-        "release_versions": ["2", "5"]
-    },
-    "MAXWSNENV": {
-        "inherits": ["Target"],
-        "core": "Cortex-M3",
-        "macros": ["__SYSTEM_HFX=24000000"],
-        "extra_labels": ["Maxim", "MAX32610"],
-        "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
-        "progen": {"target": "maxwsnenv"},
-        "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
-        "release_versions": ["2", "5"]
-    },
-    "MAX32600MBED": {
-        "inherits": ["Target"],
-        "core": "Cortex-M3",
-        "macros": ["__SYSTEM_HFX=24000000"],
-        "extra_labels": ["Maxim", "MAX32600"],
-        "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
-        "progen": {"target": "max32600mbed"},
-        "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
-        "release_versions": ["2", "5"]
-    },
-    "MAX32620HSP": {
-        "inherits": ["Target"],
-        "core": "Cortex-M4F",
-        "extra_labels": ["Maxim", "MAX32620"],
-        "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
-        "progen": {"target": "max32620hsp"},
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "STDIO_MESSAGES"],
-        "release_versions": ["2", "5"]
-    },
-    "EFM32GG_STK3700": {
-        "inherits": ["Target"],
-        "core": "Cortex-M3",
-        "macros": ["EFM32GG990F1024"],
-        "extra_labels": ["Silicon_Labs", "EFM32"],
-        "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
-        "progen": {"target": "efm32gg-stk"},
-        "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
-        "forced_reset_timeout": 2,
-        "release_versions": ["2"]
-    },
-    "EFM32LG_STK3600": {
-        "inherits": ["Target"],
-        "core": "Cortex-M3",
-        "macros": ["EFM32LG990F256"],
-        "extra_labels": ["Silicon_Labs", "EFM32"],
-        "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
-        "progen": {"target": "efm32lg-stk"},
-        "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
-        "forced_reset_timeout": 2,
-        "release_versions": ["2"]
-    },
-    "EFM32WG_STK3800": {
-        "inherits": ["Target"],
-        "core": "Cortex-M4F",
-        "macros": ["EFM32WG990F256"],
-        "extra_labels": ["Silicon_Labs", "EFM32"],
-        "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
-        "progen": {"target": "efm32wg-stk"},
-        "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
-        "forced_reset_timeout": 2,
-        "release_versions": ["2"]
-    },
-    "EFM32ZG_STK3200": {
-        "inherits": ["Target"],
-        "core": "Cortex-M0+",
-        "default_toolchain": "uARM",
-        "supported_toolchains": ["GCC_ARM", "uARM"],
-        "extra_labels": ["Silicon_Labs", "EFM32"],
-        "macros": ["EFM32ZG222F32"],
-        "progen": {
-            "target": "efm32zg-stk"
-        },
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
-        "default_build": "small",
-        "forced_reset_timeout": 2,
-        "release_versions": ["2"]
-    },
-    "EFM32HG_STK3400": {
-        "inherits": ["Target"],
-        "core": "Cortex-M0+",
-        "default_toolchain": "uARM",
-        "supported_toolchains": ["GCC_ARM", "uARM"],
-        "extra_labels": ["Silicon_Labs", "EFM32"],
-        "macros": ["EFM32HG322F64"],
-        "progen": {
-            "target": "efm32hg-stk"
-        },
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
-        "default_build": "small",
-        "forced_reset_timeout": 2,
-        "release_versions": ["2"]
-    },
-    "EFM32PG_STK3401": {
-        "inherits": ["Target"],
-        "core": "Cortex-M4F",
-        "macros": ["EFM32PG1B200F256GM48"],
-        "extra_labels": ["Silicon_Labs", "EFM32"],
-        "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
-        "progen": {"target": "efm32pg-stk"},
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
-        "forced_reset_timeout": 2,
-        "release_versions": ["2", "5"]
-    },
-    "WIZWIKI_W7500": {
-        "supported_form_factors": ["ARDUINO"],
-        "core": "Cortex-M0",
-        "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500"],
-        "supported_toolchains": ["uARM", "ARM"],
-        "inherits": ["Target"],
-        "progen": {"target": "wizwiki-w7500"},
-        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
-        "release_versions": ["2"]
-    },
-    "WIZWIKI_W7500P": {
-        "supported_form_factors": ["ARDUINO"],
-        "core": "Cortex-M0",
-        "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500P"],
-        "supported_toolchains": ["uARM", "ARM"],
-        "inherits": ["Target"],
-        "progen": {"target": "wizwiki-w7500p"},
-        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
-        "release_versions": ["2"]
-    },
-    "WIZWIKI_W7500ECO": {
-        "inherits": ["Target"],
-        "core": "Cortex-M0",
-        "progen": {"target": "wizwiki_w7500eco"},
-        "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500ECO"],
-        "supported_toolchains": ["uARM", "ARM"],
-        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
-        "release_versions": ["2"]
-    },
-    "SAMR21G18A": {
-        "inherits": ["Target"],
-        "core": "Cortex-M0+",
-        "macros": ["__SAMR21G18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
-        "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMR21"],
-        "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
-        "progen": {"target": "samr21g18a"},
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
-        "release_versions": ["2"]
-    },
-    "SAMD21J18A": {
-        "inherits": ["Target"],
-        "core": "Cortex-M0+",
-        "macros": ["__SAMD21J18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
-        "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMD21"],
-        "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
-        "progen": {"target": "samd21j18a"},
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
-        "release_versions": ["2"]
-    },
-    "SAMD21G18A": {
-        "inherits": ["Target"],
-        "core": "Cortex-M0+",
-        "macros": ["__SAMD21G18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
-        "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMD21"],
-        "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
-        "progen": {"target": "samd21g18a"},
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
-        "release_versions": ["2"]
-    },
-    "SAML21J18A": {
-        "inherits": ["Target"],
-        "core": "Cortex-M0+",
-        "macros": ["__SAML21J18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
-        "extra_labels": ["Atmel", "SAM_CortexM0P", "SAML21"],
-        "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
-        "progen": {"target": "samr21j18a"},
-        "progen_target": "samr21j18a",
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"]
-    },
-    "SAMG55J19": {
-        "inherits": ["Target"],
-        "core": "Cortex-M4",
-        "extra_labels": ["Atmel", "SAM_CortexM4", "SAMG55"],
-        "macros": ["__SAMG55J19__", "BOARD=75", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
-        "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
-        "default_toolchain": "ARM",
-        "progen": {"target": "samg55j19"},
-        "progen_target": "samg55j19",
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
-        "default_build": "standard"
-    },
-    "MCU_NRF51_UNIFIED": {
-        "inherits": ["Target"],
-        "core": "Cortex-M0",
-        "OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex",
-        "macros": [
-            "NRF51",
-            "TARGET_NRF51822",
-            "BLE_STACK_SUPPORT_REQD",
-            "SOFTDEVICE_PRESENT",
-            "S130",
-            "TARGET_MCU_NRF51822"
-        ],
-        "MERGE_BOOTLOADER": false,
-        "extra_labels": ["NORDIC", "MCU_NRF51", "MCU_NRF51822_UNIFIED", "NRF5"],
-        "OUTPUT_EXT": "hex",
-        "is_disk_virtual": true,
-        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
-        "public": false,
-        "MERGE_SOFT_DEVICE": true,
-        "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
-            {
-                "boot": "",
-                "name": "s130_nrf51_2.0.0_softdevice.hex",
-                "offset": 110592
-            }
-        ],
-        "detect_code": ["1070"],
-        "post_binary_hook": {
-            "function": "MCU_NRF51Code.binary_hook",
-            "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
-        },
-        "program_cycle_s": 6,
-        "features": ["BLE"],
-        "config":{
-            "lf_clock_src": {
-                "value": "NRF_LF_SRC_XTAL",
-                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC"
-            },
-            "uart_hwfc": {
-                "help": "Value: 1 for enable, 0 for disable",
-                "value": 1,
-                "macro_name": "MBED_CONF_NORDIC_UART_HWFC"
-            }
-        }
-    },
-    "MCU_NRF51_32K_UNIFIED": {
-        "inherits": ["MCU_NRF51_UNIFIED"],
-        "extra_labels_add": ["MCU_NORDIC_32K", "MCU_NRF51_32K"],
-        "macros_add": ["TARGET_MCU_NORDIC_32K", "TARGET_MCU_NRF51_32K"],
-        "public": false
-    },
-    "NRF51_DK": {
-        "supported_form_factors": ["ARDUINO"],
-        "inherits": ["MCU_NRF51_32K_UNIFIED"],
-        "progen": {"target": "nrf51-dk"},
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
-        "release_versions": ["2", "5"]
-    },
-    "MCU_NRF52": {
-        "inherits": ["Target"],
-        "core": "Cortex-M4F",
-        "macros": ["NRF52", "TARGET_NRF52832", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S132"],
-        "extra_labels": ["NORDIC", "MCU_NRF52", "MCU_NRF52832", "NRF5"],
-        "OUTPUT_EXT": "hex",
-        "is_disk_virtual": true,
-        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
-        "public": false,
-        "detect_code": ["1101"],
-        "program_cycle_s": 6,
-        "MERGE_SOFT_DEVICE": true,
-        "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
-            {
-                "boot": "",
-                "name": "s132_nrf52_2.0.0_softdevice.hex",
-                "offset": 114688
-            }
-        ],
-        "post_binary_hook": {
-            "function": "MCU_NRF51Code.binary_hook",
-            "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
-        },
-        "MERGE_BOOTLOADER": false,
-        "features": ["BLE"],
-        "config":{
-            "lf_clock_src": {
-                "value": "NRF_LF_SRC_XTAL",
-                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC"
-            },
-            "uart_hwfc": {
-                "help": "Value: 1 for enable, 0 for disable",
-                "value": 1,
-                "macro_name": "MBED_CONF_NORDIC_UART_HWFC"
-            }
-        }
-    },
-    "NRF52_DK": {
-        "supported_form_factors": ["ARDUINO"],
-        "inherits": ["MCU_NRF52"],
-        "progen": {"target": "nrf52-dk"},
-        "macros_add": [
-            "BOARD_PCA10040",
-            "NRF52_PAN_12",
-            "NRF52_PAN_15",
-            "NRF52_PAN_58",
-            "NRF52_PAN_55",
-            "NRF52_PAN_54",
-            "NRF52_PAN_31",
-            "NRF52_PAN_30",
-            "NRF52_PAN_51",
-            "NRF52_PAN_36",
-            "NRF52_PAN_53",
-            "S132",
-            "CONFIG_GPIO_AS_PINRESET",
-            "BLE_STACK_SUPPORT_REQD",
-            "SWI_DISABLE0",
-            "NRF52_PAN_20",
-            "NRF52_PAN_64",
-            "NRF52_PAN_62",
-            "NRF52_PAN_63"
-        ],
-        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
-        "release_versions": ["2", "5"]
-    },
-    "BLUEPILL_F103C8": {
-        "core": "Cortex-M3",
-        "default_toolchain": "GCC_ARM",
-        "extra_labels": ["STM", "STM32F1", "STM32F103C8"],
-        "supported_toolchains": ["GCC_ARM"],
-        "inherits": ["Target"],
-        "progen": {"target": "bluepill-f103c8"},
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
-    },
-    "NUMAKER_PFM_NUC472": {
-        "core": "Cortex-M4F",
-        "default_toolchain": "ARM",
-        "extra_labels": ["NUVOTON", "NUC472", "NUMAKER_PFM_NUC472"],
-		"macros": ["MBEDTLS_ENTROPY_HARDWARE_ALT"],
-        "is_disk_virtual": true,
-        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
-        "inherits": ["Target"],
-        "progen": {"target": "numaker-pfm-nuc472"},
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
-        "features": ["IPV4"],
-        "release_versions": ["2", "5"]
-    },    
-    "NCS36510": {
-        "inherits": ["Target"],
-        "core": "Cortex-M3",
-        "extra_labels": ["ONSEMI"],
-        "post_binary_hook": {"function": "NCS36510TargetCode.ncs36510_addfib"},
-        "macros": ["REVD", "CM3", "CPU_NCS36510", "TARGET_NCS36510"],
-        "progen": {"target": "ncs36510"},
-        "progen_target": "ncs36510",
-        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
-        "device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI"],
-        "release_versions": ["2", "5"]
-    }
-}

--- a/M24SR-DISCOVERY_hardware/mbed/ticker_api.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,116 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TICKER_API_H
-#define MBED_TICKER_API_H
-
-#include <stdint.h>
-#include "device.h"
-
-typedef uint32_t timestamp_t;
-
-/** Ticker's event structure
- */
-typedef struct ticker_event_s {
-    timestamp_t            timestamp; /**< Event's timestamp */
-    uint32_t               id;        /**< TimerEvent object */
-    struct ticker_event_s *next;      /**< Next event in the queue */
-} ticker_event_t;
-
-typedef void (*ticker_event_handler)(uint32_t id);
-
-/** Ticker's interface structure - required API for a ticker
- */
-typedef struct {
-    void (*init)(void);                           /**< Init function */
-    uint32_t (*read)(void);                       /**< Read function */
-    void (*disable_interrupt)(void);              /**< Disable interrupt function */
-    void (*clear_interrupt)(void);                /**< Clear interrupt function */
-    void (*set_interrupt)(timestamp_t timestamp); /**< Set interrupt function */
-} ticker_interface_t;
-
-/** Ticker's event queue structure
- */
-typedef struct {
-    ticker_event_handler event_handler; /**< Event handler */
-    ticker_event_t *head;               /**< A pointer to head */
-} ticker_event_queue_t;
-
-/** Ticker's data structure
- */
-typedef struct {
-    const ticker_interface_t *interface; /**< Ticker's interface */
-    ticker_event_queue_t *queue;         /**< Ticker's event queue */
-} ticker_data_t;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_ticker Ticker HAL functions
- * @{
- */
-
-/** Initialize a ticker and set the event handler
- *
- * @param data    The ticker's data
- * @param handler A handler to be set
- */
-void ticker_set_handler(const ticker_data_t *const data, ticker_event_handler handler);
-
-/** IRQ handler that goes through the events to trigger overdue events.
- *
- * @param data    The ticker's data
- */
-void ticker_irq_handler(const ticker_data_t *const data);
-
-/** Remove an event from the queue
- *
- * @param data The ticker's data
- * @param obj  The event object to be removed from the queue
- */
-void ticker_remove_event(const ticker_data_t *const data, ticker_event_t *obj);
-
-/** Insert an event to the queue
- *
- * @param data      The ticker's data
- * @param obj       The event object to be inserted to the queue
- * @param timestamp The event's timestamp
- * @param id        The event object
- */
-void ticker_insert_event(const ticker_data_t *const data, ticker_event_t *obj, timestamp_t timestamp, uint32_t id);
-
-/** Read the current ticker's timestamp
- *
- * @param data The ticker's data
- * @return The current timestamp
- */
-timestamp_t ticker_read(const ticker_data_t *const data);
-
-/** Read the next event's timestamp
- *
- * @param data The ticker's data
- * @return 1 if timestamp is pending event, 0 if there's no event pending
- */
-int ticker_get_next_timestamp(const ticker_data_t *const data, timestamp_t *timestamp);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/toolchain.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,266 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TOOLCHAIN_H
-#define MBED_TOOLCHAIN_H
-
-
-// Warning for unsupported compilers
-#if !defined(__GNUC__)   /* GCC        */ \
- && !defined(__CC_ARM)   /* ARMCC      */ \
- && !defined(__clang__)  /* LLVM/Clang */ \
- && !defined(__ICCARM__) /* IAR        */
-#warning "This compiler is not yet supported."
-#endif
-
-
-// Attributes
-
-/** MBED_PACKED
- *  Pack a structure, preventing any padding from being added between fields.
- *
- *  @code
- *  #include "toolchain.h"
- *
- *  MBED_PACKED(struct) foo {
- *      char x;
- *      int y;
- *  };
- *  @endcode
- */
-#ifndef MBED_PACKED
-#if defined(__ICCARM__)
-#define MBED_PACKED(struct) __packed struct
-#else
-#define MBED_PACKED(struct) struct __attribute__((packed))
-#endif
-#endif
-
-/** MBED_ALIGN(N)
- *  Declare a variable to be aligned on an N-byte boundary.
- *
- *  @note
- *  IAR does not support alignment greater than word size on the stack
- *  
- *  @code
- *  #include "toolchain.h"
- *
- *  MBED_ALIGN(16) char a;
- *  @endcode
- */
-#ifndef MBED_ALIGN
-#if defined(__ICCARM__)
-#define _MBED_ALIGN(N) _Pragma(#N)
-#define MBED_ALIGN(N) _MBED_ALIGN(data_alignment=N)
-#else
-#define MBED_ALIGN(N) __attribute__((aligned(N)))
-#endif
-#endif
-
-/** MBED_UNUSED
- *  Declare a function argument to be unused, suppressing compiler warnings
- *
- *  @code
- *  #include "toolchain.h"
- *
- *  void foo(MBED_UNUSED int arg) {
- *
- *  }
- *  @endcode
- */
-#ifndef MBED_UNUSED
-#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
-#define MBED_UNUSED __attribute__((__unused__))
-#else
-#define MBED_UNUSED
-#endif
-#endif
-
-/** MBED_WEAK
- *  Mark a function as being weak.
- *  
- *  @note
- *  weak functions are not friendly to making code re-usable, as they can only
- *  be overridden once (and if they are multiply overridden the linker will emit
- *  no warning). You should not normally use weak symbols as part of the API to
- *  re-usable modules.
- *  
- *  @code
- *  #include "toolchain.h"
- *  
- *  MBED_WEAK void foo() {
- *      // a weak implementation of foo that can be overriden by a definition
- *      // without  __weak
- *  }
- *  @endcode
- */
-#ifndef MBED_WEAK
-#if defined(__ICCARM__)
-#define MBED_WEAK __weak
-#else
-#define MBED_WEAK __attribute__((weak))
-#endif
-#endif
-
-/** MBED_PURE
- *  Hint to the compiler that a function depends only on parameters
- *
- *  @code
- *  #include "toolchain.h"
- *
- *  MBED_PURE int foo(int arg){
- *      // no access to global variables
- *  }
- *  @endcode
- */
-#ifndef MBED_PURE
-#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
-#define MBED_PURE __attribute__((const))
-#else
-#define MBED_PURE
-#endif
-#endif
-
-/** MBED_FORCEINLINE
- *  Declare a function that must always be inlined. Failure to inline
- *  such a function will result in an error.
- *
- *  @code
- *  #include "toolchain.h"
- *  
- *  MBED_FORCEINLINE void foo() {
- *  
- *  }
- *  @endcode
- */
-#ifndef MBED_FORCEINLINE
-#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
-#define MBED_FORCEINLINE static inline __attribute__((always_inline))
-#elif defined(__ICCARM__)
-#define MBED_FORCEINLINE _Pragma("inline=forced") static
-#else
-#define MBED_FORCEINLINE static inline
-#endif
-#endif
-
-/** MBED_NORETURN
- *  Declare a function that will never return.
- *
- *  @code
- *  #include "toolchain.h"
- *  
- *  MBED_NORETURN void foo() {
- *      // must never return
- *      while (1) {}
- *  }
- *  @endcode
- */
-#ifndef MBED_NORETURN
-#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
-#define MBED_NORETURN __attribute__((noreturn))
-#elif defined(__ICCARM__)
-#define MBED_NORETURN __noreturn
-#else
-#define MBED_NORETURN
-#endif
-#endif
-
-/** MBED_UNREACHABLE
- *  An unreachable statement. If the statement is reached,
- *  behaviour is undefined. Useful in situations where the compiler
- *  cannot deduce the unreachability of code.
- *
- *  @code
- *  #include "toolchain.h"
- *
- *  void foo(int arg) {
- *      switch (arg) {
- *          case 1: return 1;
- *          case 2: return 2;
- *          ...
- *      }
- *      MBED_UNREACHABLE;
- *  }
- *  @endcode
- */
-#ifndef MBED_UNREACHABLE
-#if (defined(__GNUC__) || defined(__clang__)) && !defined(__CC_ARM)
-#define MBED_UNREACHABLE __builtin_unreachable()
-#else
-#define MBED_UNREACHABLE while (1)
-#endif
-#endif
-
-/** MBED_DEPRECATED("message string")
- *  Mark a function declaration as deprecated, if it used then a warning will be
- *  issued by the compiler possibly including the provided message. Note that not
- *  all compilers are able to display the message.
- *
- *  @code
- *  #include "toolchain.h"
- *  
- *  MBED_DEPRECATED("don't foo any more, bar instead")
- *  void foo(int arg);
- *  @endcode
- */
-#ifndef MBED_DEPRECATED
-#if defined(__GNUC__) || defined(__clang__)
-#define MBED_DEPRECATED(M) __attribute__((deprecated(M)))
-#elif defined(__CC_ARM)
-#define MBED_DEPRECATED(M) __attribute__((deprecated))
-#else
-#define MBED_DEPRECATED(M)
-#endif
-#endif
-
-/** MBED_DEPRECATED_SINCE("version", "message string")
- *  Mark a function declaration as deprecated, noting that the declaration was
- *  deprecated on the specified version. If the function is used then a warning
- *  will be issued by the compiler possibly including the provided message.
- *  Note that not all compilers are able to display this message.
- *
- *  @code
- *  #include "toolchain.h"
- *
- *  MBED_DEPRECATED_SINCE("mbed-os-5.1", "don't foo any more, bar instead")
- *  void foo(int arg);
- *  @endcode
- */
-#define MBED_DEPRECATED_SINCE(D, M) MBED_DEPRECATED(M " [since " D "]")
-
-
-// FILEHANDLE declaration
-#if defined(TOOLCHAIN_ARM)
-#include <rt_sys.h>
-#endif
-
-#ifndef FILEHANDLE
-typedef int FILEHANDLE;
-#endif
-
-// Backwards compatibility
-#ifndef WEAK
-#define WEAK MBED_WEAK
-#endif
-
-#ifndef PACKED
-#define PACKED MBED_PACKED()
-#endif
-
-#ifndef EXTERN
-#define EXTERN extern
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/us_ticker_api.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,78 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_US_TICKER_API_H
-#define MBED_US_TICKER_API_H
-
-#include <stdint.h>
-#include "ticker_api.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_UsTicker Microseconds Ticker Functions
- * @{
- */
-
-/** Get ticker's data
- *
- * @return The low power ticker data
- */
-const ticker_data_t* get_us_ticker_data(void);
-
-
-/** The wrapper for ticker_irq_handler, to pass us ticker's data
- *
- */
-void us_ticker_irq_handler(void);
-
-/* HAL us ticker */
-
-/** Initialize the ticker
- *
- */
-void us_ticker_init(void);
-
-/** Read the current counter
- *
- * @return The current timer's counter value in microseconds
- */
-uint32_t us_ticker_read(void);
-
-/** Set interrupt for specified timestamp
- *
- * @param timestamp The time in microseconds to be set
- */
-void us_ticker_set_interrupt(timestamp_t timestamp);
-
-/** Disable us ticker interrupt
- *
- */
-void us_ticker_disable_interrupt(void);
-
-/** Clear us ticker interrupt
- *
- */
-void us_ticker_clear_interrupt(void);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed/wait_api.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,66 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_WAIT_API_H
-#define MBED_WAIT_API_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Generic wait functions.
- *
- * These provide simple NOP type wait capabilities.
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * DigitalOut heartbeat(LED1);
- *
- * int main() {
- *     while (1) {
- *         heartbeat = 1;
- *         wait(0.5);
- *         heartbeat = 0;
- *         wait(0.5);
- *     }
- * }
- */
-
-/** Waits for a number of seconds, with microsecond resolution (within
- *  the accuracy of single precision floating point).
- *
- *  @param s number of seconds to wait
- */
-void wait(float s);
-
-/** Waits a number of milliseconds.
- *
- *  @param ms the whole number of milliseconds to wait
- */
-void wait_ms(int ms);
-
-/** Waits a number of microseconds.
- *
- *  @param us the whole number of microseconds to wait
- */
-void wait_us(int us);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/M24SR-DISCOVERY_hardware/mbed_config.h	Thu Sep 22 10:43:55 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,8 +0,0 @@
-// Automatically generated configuration file.
-// DO NOT EDIT, content will be overwritten.
-
-#ifndef __MBED_CONFIG_DATA__
-#define __MBED_CONFIG_DATA__
-
-
-#endif