The official mbed C/C SDK provides the software platform and libraries to build your applications.
Fork of mbed by
core_cmFunc.h
00001 /**************************************************************************//** 00002 * @file core_cmFunc.h 00003 * @brief CMSIS Cortex-M Core Function Access Header File 00004 * @version V3.02 00005 * @date 24. May 2012 00006 * 00007 * @note 00008 * Copyright (C) 2009-2012 ARM Limited. All rights reserved. 00009 * 00010 * @par 00011 * ARM Limited (ARM) is supplying this software for use with Cortex-M 00012 * processor based microcontrollers. This file can be freely distributed 00013 * within development tools that are supporting such ARM based processors. 00014 * 00015 * @par 00016 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 00017 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 00018 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 00019 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 00020 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 00021 * 00022 ******************************************************************************/ 00023 00024 #ifndef __CORE_CMFUNC_H 00025 #define __CORE_CMFUNC_H 00026 00027 00028 /* ########################### Core Function Access ########################### */ 00029 /** \ingroup CMSIS_Core_FunctionInterface 00030 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 00031 @{ 00032 */ 00033 00034 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ 00035 /* ARM armcc specific functions */ 00036 00037 #if (__ARMCC_VERSION < 400677) 00038 #error "Please use ARM Compiler Toolchain V4.0.677 or later!" 00039 #endif 00040 00041 /* intrinsic void __enable_irq(); */ 00042 /* intrinsic void __disable_irq(); */ 00043 00044 /** \brief Get Control Register 00045 00046 This function returns the content of the Control Register. 00047 00048 \return Control Register value 00049 */ 00050 __STATIC_INLINE uint32_t __get_CONTROL(void) 00051 { 00052 register uint32_t __regControl __ASM("control"); 00053 return(__regControl); 00054 } 00055 00056 00057 /** \brief Set Control Register 00058 00059 This function writes the given value to the Control Register. 00060 00061 \param [in] control Control Register value to set 00062 */ 00063 __STATIC_INLINE void __set_CONTROL(uint32_t control) 00064 { 00065 register uint32_t __regControl __ASM("control"); 00066 __regControl = control; 00067 } 00068 00069 00070 /** \brief Get IPSR Register 00071 00072 This function returns the content of the IPSR Register. 00073 00074 \return IPSR Register value 00075 */ 00076 __STATIC_INLINE uint32_t __get_IPSR(void) 00077 { 00078 register uint32_t __regIPSR __ASM("ipsr"); 00079 return(__regIPSR); 00080 } 00081 00082 00083 /** \brief Get APSR Register 00084 00085 This function returns the content of the APSR Register. 00086 00087 \return APSR Register value 00088 */ 00089 __STATIC_INLINE uint32_t __get_APSR(void) 00090 { 00091 register uint32_t __regAPSR __ASM("apsr"); 00092 return(__regAPSR); 00093 } 00094 00095 00096 /** \brief Get xPSR Register 00097 00098 This function returns the content of the xPSR Register. 00099 00100 \return xPSR Register value 00101 */ 00102 __STATIC_INLINE uint32_t __get_xPSR(void) 00103 { 00104 register uint32_t __regXPSR __ASM("xpsr"); 00105 return(__regXPSR); 00106 } 00107 00108 00109 /** \brief Get Process Stack Pointer 00110 00111 This function returns the current value of the Process Stack Pointer (PSP). 00112 00113 \return PSP Register value 00114 */ 00115 __STATIC_INLINE uint32_t __get_PSP(void) 00116 { 00117 register uint32_t __regProcessStackPointer __ASM("psp"); 00118 return(__regProcessStackPointer); 00119 } 00120 00121 00122 /** \brief Set Process Stack Pointer 00123 00124 This function assigns the given value to the Process Stack Pointer (PSP). 00125 00126 \param [in] topOfProcStack Process Stack Pointer value to set 00127 */ 00128 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) 00129 { 00130 register uint32_t __regProcessStackPointer __ASM("psp"); 00131 __regProcessStackPointer = topOfProcStack; 00132 } 00133 00134 00135 /** \brief Get Main Stack Pointer 00136 00137 This function returns the current value of the Main Stack Pointer (MSP). 00138 00139 \return MSP Register value 00140 */ 00141 __STATIC_INLINE uint32_t __get_MSP(void) 00142 { 00143 register uint32_t __regMainStackPointer __ASM("msp"); 00144 return(__regMainStackPointer); 00145 } 00146 00147 00148 /** \brief Set Main Stack Pointer 00149 00150 This function assigns the given value to the Main Stack Pointer (MSP). 00151 00152 \param [in] topOfMainStack Main Stack Pointer value to set 00153 */ 00154 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) 00155 { 00156 register uint32_t __regMainStackPointer __ASM("msp"); 00157 __regMainStackPointer = topOfMainStack; 00158 } 00159 00160 00161 /** \brief Get Priority Mask 00162 00163 This function returns the current state of the priority mask bit from the Priority Mask Register. 00164 00165 \return Priority Mask value 00166 */ 00167 __STATIC_INLINE uint32_t __get_PRIMASK(void) 00168 { 00169 register uint32_t __regPriMask __ASM("primask"); 00170 return(__regPriMask); 00171 } 00172 00173 00174 /** \brief Set Priority Mask 00175 00176 This function assigns the given value to the Priority Mask Register. 00177 00178 \param [in] priMask Priority Mask 00179 */ 00180 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) 00181 { 00182 register uint32_t __regPriMask __ASM("primask"); 00183 __regPriMask = (priMask); 00184 } 00185 00186 00187 #if (__CORTEX_M >= 0x03) 00188 00189 /** \brief Enable FIQ 00190 00191 This function enables FIQ interrupts by clearing the F-bit in the CPSR. 00192 Can only be executed in Privileged modes. 00193 */ 00194 #define __enable_fault_irq __enable_fiq 00195 00196 00197 /** \brief Disable FIQ 00198 00199 This function disables FIQ interrupts by setting the F-bit in the CPSR. 00200 Can only be executed in Privileged modes. 00201 */ 00202 #define __disable_fault_irq __disable_fiq 00203 00204 00205 /** \brief Get Base Priority 00206 00207 This function returns the current value of the Base Priority register. 00208 00209 \return Base Priority register value 00210 */ 00211 __STATIC_INLINE uint32_t __get_BASEPRI(void) 00212 { 00213 register uint32_t __regBasePri __ASM("basepri"); 00214 return(__regBasePri); 00215 } 00216 00217 00218 /** \brief Set Base Priority 00219 00220 This function assigns the given value to the Base Priority register. 00221 00222 \param [in] basePri Base Priority value to set 00223 */ 00224 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) 00225 { 00226 register uint32_t __regBasePri __ASM("basepri"); 00227 __regBasePri = (basePri & 0xff); 00228 } 00229 00230 00231 /** \brief Get Fault Mask 00232 00233 This function returns the current value of the Fault Mask register. 00234 00235 \return Fault Mask register value 00236 */ 00237 __STATIC_INLINE uint32_t __get_FAULTMASK(void) 00238 { 00239 register uint32_t __regFaultMask __ASM("faultmask"); 00240 return(__regFaultMask); 00241 } 00242 00243 00244 /** \brief Set Fault Mask 00245 00246 This function assigns the given value to the Fault Mask register. 00247 00248 \param [in] faultMask Fault Mask value to set 00249 */ 00250 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) 00251 { 00252 register uint32_t __regFaultMask __ASM("faultmask"); 00253 __regFaultMask = (faultMask & (uint32_t)1); 00254 } 00255 00256 #endif /* (__CORTEX_M >= 0x03) */ 00257 00258 00259 #if (__CORTEX_M == 0x04) 00260 00261 /** \brief Get FPSCR 00262 00263 This function returns the current value of the Floating Point Status/Control register. 00264 00265 \return Floating Point Status/Control register value 00266 */ 00267 __STATIC_INLINE uint32_t __get_FPSCR(void) 00268 { 00269 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 00270 register uint32_t __regfpscr __ASM("fpscr"); 00271 return(__regfpscr); 00272 #else 00273 return(0); 00274 #endif 00275 } 00276 00277 00278 /** \brief Set FPSCR 00279 00280 This function assigns the given value to the Floating Point Status/Control register. 00281 00282 \param [in] fpscr Floating Point Status/Control value to set 00283 */ 00284 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) 00285 { 00286 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 00287 register uint32_t __regfpscr __ASM("fpscr"); 00288 __regfpscr = (fpscr); 00289 #endif 00290 } 00291 00292 #endif /* (__CORTEX_M == 0x04) */ 00293 00294 00295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ 00296 /* IAR iccarm specific functions */ 00297 00298 #include <cmsis_iar.h> 00299 00300 00301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ 00302 /* TI CCS specific functions */ 00303 00304 #include <cmsis_ccs.h> 00305 00306 00307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ 00308 /* GNU gcc specific functions */ 00309 00310 /** \brief Enable IRQ Interrupts 00311 00312 This function enables IRQ interrupts by clearing the I-bit in the CPSR. 00313 Can only be executed in Privileged modes. 00314 */ 00315 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) 00316 { 00317 __ASM volatile ("cpsie i" : : : "memory"); 00318 } 00319 00320 00321 /** \brief Disable IRQ Interrupts 00322 00323 This function disables IRQ interrupts by setting the I-bit in the CPSR. 00324 Can only be executed in Privileged modes. 00325 */ 00326 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) 00327 { 00328 __ASM volatile ("cpsid i" : : : "memory"); 00329 } 00330 00331 00332 /** \brief Get Control Register 00333 00334 This function returns the content of the Control Register. 00335 00336 \return Control Register value 00337 */ 00338 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) 00339 { 00340 uint32_t result; 00341 00342 __ASM volatile ("MRS %0, control" : "=r" (result) ); 00343 return(result); 00344 } 00345 00346 00347 /** \brief Set Control Register 00348 00349 This function writes the given value to the Control Register. 00350 00351 \param [in] control Control Register value to set 00352 */ 00353 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) 00354 { 00355 __ASM volatile ("MSR control, %0" : : "r" (control) ); 00356 } 00357 00358 00359 /** \brief Get IPSR Register 00360 00361 This function returns the content of the IPSR Register. 00362 00363 \return IPSR Register value 00364 */ 00365 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) 00366 { 00367 uint32_t result; 00368 00369 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 00370 return(result); 00371 } 00372 00373 00374 /** \brief Get APSR Register 00375 00376 This function returns the content of the APSR Register. 00377 00378 \return APSR Register value 00379 */ 00380 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) 00381 { 00382 uint32_t result; 00383 00384 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); 00385 return(result); 00386 } 00387 00388 00389 /** \brief Get xPSR Register 00390 00391 This function returns the content of the xPSR Register. 00392 00393 \return xPSR Register value 00394 */ 00395 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) 00396 { 00397 uint32_t result; 00398 00399 __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); 00400 return(result); 00401 } 00402 00403 00404 /** \brief Get Process Stack Pointer 00405 00406 This function returns the current value of the Process Stack Pointer (PSP). 00407 00408 \return PSP Register value 00409 */ 00410 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) 00411 { 00412 register uint32_t result; 00413 00414 __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); 00415 return(result); 00416 } 00417 00418 00419 /** \brief Set Process Stack Pointer 00420 00421 This function assigns the given value to the Process Stack Pointer (PSP). 00422 00423 \param [in] topOfProcStack Process Stack Pointer value to set 00424 */ 00425 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) 00426 { 00427 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); 00428 } 00429 00430 00431 /** \brief Get Main Stack Pointer 00432 00433 This function returns the current value of the Main Stack Pointer (MSP). 00434 00435 \return MSP Register value 00436 */ 00437 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) 00438 { 00439 register uint32_t result; 00440 00441 __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); 00442 return(result); 00443 } 00444 00445 00446 /** \brief Set Main Stack Pointer 00447 00448 This function assigns the given value to the Main Stack Pointer (MSP). 00449 00450 \param [in] topOfMainStack Main Stack Pointer value to set 00451 */ 00452 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) 00453 { 00454 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); 00455 } 00456 00457 00458 /** \brief Get Priority Mask 00459 00460 This function returns the current state of the priority mask bit from the Priority Mask Register. 00461 00462 \return Priority Mask value 00463 */ 00464 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) 00465 { 00466 uint32_t result; 00467 00468 __ASM volatile ("MRS %0, primask" : "=r" (result) ); 00469 return(result); 00470 } 00471 00472 00473 /** \brief Set Priority Mask 00474 00475 This function assigns the given value to the Priority Mask Register. 00476 00477 \param [in] priMask Priority Mask 00478 */ 00479 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) 00480 { 00481 __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); 00482 } 00483 00484 00485 #if (__CORTEX_M >= 0x03) 00486 00487 /** \brief Enable FIQ 00488 00489 This function enables FIQ interrupts by clearing the F-bit in the CPSR. 00490 Can only be executed in Privileged modes. 00491 */ 00492 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) 00493 { 00494 __ASM volatile ("cpsie f" : : : "memory"); 00495 } 00496 00497 00498 /** \brief Disable FIQ 00499 00500 This function disables FIQ interrupts by setting the F-bit in the CPSR. 00501 Can only be executed in Privileged modes. 00502 */ 00503 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) 00504 { 00505 __ASM volatile ("cpsid f" : : : "memory"); 00506 } 00507 00508 00509 /** \brief Get Base Priority 00510 00511 This function returns the current value of the Base Priority register. 00512 00513 \return Base Priority register value 00514 */ 00515 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) 00516 { 00517 uint32_t result; 00518 00519 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); 00520 return(result); 00521 } 00522 00523 00524 /** \brief Set Base Priority 00525 00526 This function assigns the given value to the Base Priority register. 00527 00528 \param [in] basePri Base Priority value to set 00529 */ 00530 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) 00531 { 00532 __ASM volatile ("MSR basepri, %0" : : "r" (value) ); 00533 } 00534 00535 00536 /** \brief Get Fault Mask 00537 00538 This function returns the current value of the Fault Mask register. 00539 00540 \return Fault Mask register value 00541 */ 00542 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) 00543 { 00544 uint32_t result; 00545 00546 __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 00547 return(result); 00548 } 00549 00550 00551 /** \brief Set Fault Mask 00552 00553 This function assigns the given value to the Fault Mask register. 00554 00555 \param [in] faultMask Fault Mask value to set 00556 */ 00557 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) 00558 { 00559 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); 00560 } 00561 00562 #endif /* (__CORTEX_M >= 0x03) */ 00563 00564 00565 #if (__CORTEX_M == 0x04) 00566 00567 /** \brief Get FPSCR 00568 00569 This function returns the current value of the Floating Point Status/Control register. 00570 00571 \return Floating Point Status/Control register value 00572 */ 00573 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) 00574 { 00575 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 00576 uint32_t result; 00577 00578 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); 00579 return(result); 00580 #else 00581 return(0); 00582 #endif 00583 } 00584 00585 00586 /** \brief Set FPSCR 00587 00588 This function assigns the given value to the Floating Point Status/Control register. 00589 00590 \param [in] fpscr Floating Point Status/Control value to set 00591 */ 00592 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) 00593 { 00594 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 00595 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); 00596 #endif 00597 } 00598 00599 #endif /* (__CORTEX_M == 0x04) */ 00600 00601 00602 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ 00603 /* TASKING carm specific functions */ 00604 00605 /* 00606 * The CMSIS functions have been implemented as intrinsics in the compiler. 00607 * Please use "carm -?i" to get an up to date list of all instrinsics, 00608 * Including the CMSIS ones. 00609 */ 00610 00611 #endif 00612 00613 /*@} end of CMSIS_Core_RegAccFunctions */ 00614 00615 00616 #endif /* __CORE_CMFUNC_H */
Generated on Tue Jul 12 2022 21:08:34 by 1.7.2