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core_cm3.h
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00001 /**************************************************************************//** 00002 * @file core_cm3.h 00003 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File 00004 * @version V3.02 00005 * @date 16. July 2012 00006 * 00007 * @note 00008 * Copyright (C) 2009-2012 ARM Limited. All rights reserved. 00009 * 00010 * @par 00011 * ARM Limited (ARM) is supplying this software for use with Cortex-M 00012 * processor based microcontrollers. This file can be freely distributed 00013 * within development tools that are supporting such ARM based processors. 00014 * 00015 * @par 00016 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 00017 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 00018 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 00019 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 00020 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 00021 * 00022 ******************************************************************************/ 00023 #if defined ( __ICCARM__ ) 00024 #pragma system_include /* treat file as system include file for MISRA check */ 00025 #endif 00026 00027 #ifdef __cplusplus 00028 extern "C" { 00029 #endif 00030 00031 #ifndef __CORE_CM3_H_GENERIC 00032 #define __CORE_CM3_H_GENERIC 00033 00034 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00035 CMSIS violates the following MISRA-C:2004 rules: 00036 00037 \li Required Rule 8.5, object/function definition in header file.<br> 00038 Function definitions in header files are used to allow 'inlining'. 00039 00040 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00041 Unions are used for effective representation of core registers. 00042 00043 \li Advisory Rule 19.7, Function-like macro defined.<br> 00044 Function-like macros are used to allow more efficient code. 00045 */ 00046 00047 00048 /******************************************************************************* 00049 * CMSIS definitions 00050 ******************************************************************************/ 00051 /** \ingroup Cortex_M3 00052 @{ 00053 */ 00054 00055 /* CMSIS CM3 definitions */ 00056 #define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ 00057 #define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ 00058 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ 00059 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 00060 00061 #define __CORTEX_M (0x03) /*!< Cortex-M Core */ 00062 00063 00064 #if defined ( __CC_ARM ) 00065 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00066 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00067 #define __STATIC_INLINE static __inline 00068 00069 #elif defined ( __ICCARM__ ) 00070 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00071 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 00072 #define __STATIC_INLINE static inline 00073 00074 #elif defined ( __TMS470__ ) 00075 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 00076 #define __STATIC_INLINE static inline 00077 00078 #elif defined ( __GNUC__ ) 00079 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00080 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00081 #define __STATIC_INLINE static inline 00082 00083 #elif defined ( __TASKING__ ) 00084 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00085 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00086 #define __STATIC_INLINE static inline 00087 00088 #endif 00089 00090 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all 00091 */ 00092 #define __FPU_USED 0 00093 00094 #if defined ( __CC_ARM ) 00095 #if defined __TARGET_FPU_VFP 00096 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00097 #endif 00098 00099 #elif defined ( __ICCARM__ ) 00100 #if defined __ARMVFP__ 00101 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00102 #endif 00103 00104 #elif defined ( __TMS470__ ) 00105 #if defined __TI__VFP_SUPPORT____ 00106 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00107 #endif 00108 00109 #elif defined ( __GNUC__ ) 00110 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00111 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00112 #endif 00113 00114 #elif defined ( __TASKING__ ) 00115 #if defined __FPU_VFP__ 00116 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00117 #endif 00118 #endif 00119 00120 #include <stdint.h> /* standard types definitions */ 00121 #include <core_cmInstr.h> /* Core Instruction Access */ 00122 #include <core_cmFunc.h> /* Core Function Access */ 00123 00124 #endif /* __CORE_CM3_H_GENERIC */ 00125 00126 #ifndef __CMSIS_GENERIC 00127 00128 #ifndef __CORE_CM3_H_DEPENDANT 00129 #define __CORE_CM3_H_DEPENDANT 00130 00131 /* check device defines and use defaults */ 00132 #if defined __CHECK_DEVICE_DEFINES 00133 #ifndef __CM3_REV 00134 #define __CM3_REV 0x0200 00135 #warning "__CM3_REV not defined in device header file; using default!" 00136 #endif 00137 00138 #ifndef __MPU_PRESENT 00139 #define __MPU_PRESENT 0 00140 #warning "__MPU_PRESENT not defined in device header file; using default!" 00141 #endif 00142 00143 #ifndef __NVIC_PRIO_BITS 00144 #define __NVIC_PRIO_BITS 4 00145 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00146 #endif 00147 00148 #ifndef __Vendor_SysTickConfig 00149 #define __Vendor_SysTickConfig 0 00150 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00151 #endif 00152 #endif 00153 00154 /* IO definitions (access restrictions to peripheral registers) */ 00155 /** 00156 \defgroup CMSIS_glob_defs CMSIS Global Defines 00157 00158 <strong>IO Type Qualifiers</strong> are used 00159 \li to specify the access to peripheral variables. 00160 \li for automatic generation of peripheral register debug information. 00161 */ 00162 #ifdef __cplusplus 00163 #define __I volatile /*!< Defines 'read only' permissions */ 00164 #else 00165 #define __I volatile const /*!< Defines 'read only' permissions */ 00166 #endif 00167 #define __O volatile /*!< Defines 'write only' permissions */ 00168 #define __IO volatile /*!< Defines 'read / write' permissions */ 00169 00170 /*@} end of group Cortex_M3 */ 00171 00172 00173 00174 /******************************************************************************* 00175 * Register Abstraction 00176 Core Register contain: 00177 - Core Register 00178 - Core NVIC Register 00179 - Core SCB Register 00180 - Core SysTick Register 00181 - Core Debug Register 00182 - Core MPU Register 00183 ******************************************************************************/ 00184 /** \defgroup CMSIS_core_register Defines and Type Definitions 00185 \brief Type definitions and defines for Cortex-M processor based devices. 00186 */ 00187 00188 /** \ingroup CMSIS_core_register 00189 \defgroup CMSIS_CORE Status and Control Registers 00190 \brief Core Register type definitions. 00191 @{ 00192 */ 00193 00194 /** \brief Union type to access the Application Program Status Register (APSR). 00195 */ 00196 typedef union 00197 { 00198 struct 00199 { 00200 #if (__CORTEX_M != 0x04) 00201 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ 00202 #else 00203 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00204 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00205 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00206 #endif 00207 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00208 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00209 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00210 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00211 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00212 } b; /*!< Structure used for bit access */ 00213 uint32_t w ; /*!< Type used for word access */ 00214 } APSR_Type; 00215 00216 00217 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 00218 */ 00219 typedef union 00220 { 00221 struct 00222 { 00223 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00224 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00225 } b; /*!< Structure used for bit access */ 00226 uint32_t w ; /*!< Type used for word access */ 00227 } IPSR_Type; 00228 00229 00230 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00231 */ 00232 typedef union 00233 { 00234 struct 00235 { 00236 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00237 #if (__CORTEX_M != 0x04) 00238 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00239 #else 00240 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 00241 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00242 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00243 #endif 00244 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00245 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 00246 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00247 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00248 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00249 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00250 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00251 } b; /*!< Structure used for bit access */ 00252 uint32_t w ; /*!< Type used for word access */ 00253 } xPSR_Type; 00254 00255 00256 /** \brief Union type to access the Control Registers (CONTROL). 00257 */ 00258 typedef union 00259 { 00260 struct 00261 { 00262 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00263 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00264 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 00265 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 00266 } b; /*!< Structure used for bit access */ 00267 uint32_t w ; /*!< Type used for word access */ 00268 } CONTROL_Type; 00269 00270 /*@} end of group CMSIS_CORE */ 00271 00272 00273 /** \ingroup CMSIS_core_register 00274 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00275 \brief Type definitions for the NVIC Registers 00276 @{ 00277 */ 00278 00279 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00280 */ 00281 typedef struct 00282 { 00283 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00284 uint32_t RESERVED0[24]; 00285 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00286 uint32_t RSERVED1[24]; 00287 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00288 uint32_t RESERVED2[24]; 00289 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00290 uint32_t RESERVED3[24]; 00291 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 00292 uint32_t RESERVED4[56]; 00293 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 00294 uint32_t RESERVED5[644]; 00295 __O uint32_t STIR ; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 00296 } NVIC_Type; 00297 00298 /* Software Triggered Interrupt Register Definitions */ 00299 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ 00300 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ 00301 00302 /*@} end of group CMSIS_NVIC */ 00303 00304 00305 /** \ingroup CMSIS_core_register 00306 \defgroup CMSIS_SCB System Control Block (SCB) 00307 \brief Type definitions for the System Control Block Registers 00308 @{ 00309 */ 00310 00311 /** \brief Structure type to access the System Control Block (SCB). 00312 */ 00313 typedef struct 00314 { 00315 __I uint32_t CPUID ; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00316 __IO uint32_t ICSR ; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00317 __IO uint32_t VTOR ; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00318 __IO uint32_t AIRCR ; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00319 __IO uint32_t SCR ; /*!< Offset: 0x010 (R/W) System Control Register */ 00320 __IO uint32_t CCR ; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00321 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 00322 __IO uint32_t SHCSR ; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00323 __IO uint32_t CFSR ; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 00324 __IO uint32_t HFSR ; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 00325 __IO uint32_t DFSR ; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 00326 __IO uint32_t MMFAR ; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 00327 __IO uint32_t BFAR ; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 00328 __IO uint32_t AFSR ; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 00329 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 00330 __I uint32_t DFR ; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 00331 __I uint32_t ADR ; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 00332 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 00333 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 00334 uint32_t RESERVED0[5]; 00335 __IO uint32_t CPACR ; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 00336 } SCB_Type; 00337 00338 /* SCB CPUID Register Definitions */ 00339 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 00340 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00341 00342 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 00343 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00344 00345 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 00346 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00347 00348 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 00349 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00350 00351 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 00352 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ 00353 00354 /* SCB Interrupt Control State Register Definitions */ 00355 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 00356 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00357 00358 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 00359 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00360 00361 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 00362 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00363 00364 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 00365 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00366 00367 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 00368 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00369 00370 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 00371 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00372 00373 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 00374 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00375 00376 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 00377 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00378 00379 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ 00380 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 00381 00382 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 00383 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ 00384 00385 /* SCB Vector Table Offset Register Definitions */ 00386 #if (__CM3_REV < 0x0201) /* core r2p1 */ 00387 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ 00388 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ 00389 00390 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ 00391 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00392 #else 00393 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ 00394 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00395 #endif 00396 00397 /* SCB Application Interrupt and Reset Control Register Definitions */ 00398 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 00399 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00400 00401 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 00402 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00403 00404 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 00405 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00406 00407 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ 00408 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 00409 00410 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 00411 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00412 00413 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00414 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00415 00416 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ 00417 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ 00418 00419 /* SCB System Control Register Definitions */ 00420 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 00421 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00422 00423 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 00424 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00425 00426 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 00427 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00428 00429 /* SCB Configuration Control Register Definitions */ 00430 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 00431 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00432 00433 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ 00434 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 00435 00436 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ 00437 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 00438 00439 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 00440 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00441 00442 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ 00443 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 00444 00445 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ 00446 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ 00447 00448 /* SCB System Handler Control and State Register Definitions */ 00449 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ 00450 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 00451 00452 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ 00453 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 00454 00455 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ 00456 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 00457 00458 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 00459 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00460 00461 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ 00462 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 00463 00464 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ 00465 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 00466 00467 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ 00468 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 00469 00470 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ 00471 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 00472 00473 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ 00474 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 00475 00476 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ 00477 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 00478 00479 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ 00480 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 00481 00482 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ 00483 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 00484 00485 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ 00486 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 00487 00488 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ 00489 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ 00490 00491 /* SCB Configurable Fault Status Registers Definitions */ 00492 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ 00493 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 00494 00495 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ 00496 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 00497 00498 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 00499 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 00500 00501 /* SCB Hard Fault Status Registers Definitions */ 00502 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ 00503 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 00504 00505 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ 00506 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 00507 00508 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ 00509 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 00510 00511 /* SCB Debug Fault Status Register Definitions */ 00512 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ 00513 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 00514 00515 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ 00516 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 00517 00518 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ 00519 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 00520 00521 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ 00522 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 00523 00524 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ 00525 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ 00526 00527 /*@} end of group CMSIS_SCB */ 00528 00529 00530 /** \ingroup CMSIS_core_register 00531 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 00532 \brief Type definitions for the System Control and ID Register not in the SCB 00533 @{ 00534 */ 00535 00536 /** \brief Structure type to access the System Control and ID Register not in the SCB. 00537 */ 00538 typedef struct 00539 { 00540 uint32_t RESERVED0[1]; 00541 __I uint32_t ICTR ; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 00542 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) 00543 __IO uint32_t ACTLR ; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 00544 #else 00545 uint32_t RESERVED1[1]; 00546 #endif 00547 } SCnSCB_Type; 00548 00549 /* Interrupt Controller Type Register Definitions */ 00550 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ 00551 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ 00552 00553 /* Auxiliary Control Register Definitions */ 00554 00555 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ 00556 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ 00557 00558 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ 00559 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ 00560 00561 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ 00562 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ 00563 00564 /*@} end of group CMSIS_SCnotSCB */ 00565 00566 00567 /** \ingroup CMSIS_core_register 00568 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00569 \brief Type definitions for the System Timer Registers. 00570 @{ 00571 */ 00572 00573 /** \brief Structure type to access the System Timer (SysTick). 00574 */ 00575 typedef struct 00576 { 00577 __IO uint32_t CTRL ; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00578 __IO uint32_t LOAD ; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00579 __IO uint32_t VAL ; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00580 __I uint32_t CALIB ; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00581 } SysTick_Type; 00582 00583 /* SysTick Control / Status Register Definitions */ 00584 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 00585 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00586 00587 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 00588 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00589 00590 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 00591 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00592 00593 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 00594 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ 00595 00596 /* SysTick Reload Register Definitions */ 00597 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 00598 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ 00599 00600 /* SysTick Current Register Definitions */ 00601 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 00602 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ 00603 00604 /* SysTick Calibration Register Definitions */ 00605 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 00606 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00607 00608 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 00609 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00610 00611 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 00612 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ 00613 00614 /*@} end of group CMSIS_SysTick */ 00615 00616 00617 /** \ingroup CMSIS_core_register 00618 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 00619 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 00620 @{ 00621 */ 00622 00623 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 00624 */ 00625 typedef struct 00626 { 00627 __O union 00628 { 00629 __O uint8_t u8 ; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 00630 __O uint16_t u16 ; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 00631 __O uint32_t u32 ; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 00632 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 00633 uint32_t RESERVED0[864]; 00634 __IO uint32_t TER ; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 00635 uint32_t RESERVED1[15]; 00636 __IO uint32_t TPR ; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 00637 uint32_t RESERVED2[15]; 00638 __IO uint32_t TCR ; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 00639 uint32_t RESERVED3[29]; 00640 __O uint32_t IWR ; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ 00641 __I uint32_t IRR ; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 00642 __IO uint32_t IMCR ; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ 00643 uint32_t RESERVED4[43]; 00644 __O uint32_t LAR ; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 00645 __I uint32_t LSR ; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 00646 uint32_t RESERVED5[6]; 00647 __I uint32_t PID4 ; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 00648 __I uint32_t PID5 ; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 00649 __I uint32_t PID6 ; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 00650 __I uint32_t PID7 ; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 00651 __I uint32_t PID0 ; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 00652 __I uint32_t PID1 ; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 00653 __I uint32_t PID2 ; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 00654 __I uint32_t PID3 ; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 00655 __I uint32_t CID0 ; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 00656 __I uint32_t CID1 ; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 00657 __I uint32_t CID2 ; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 00658 __I uint32_t CID3 ; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 00659 } ITM_Type; 00660 00661 /* ITM Trace Privilege Register Definitions */ 00662 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ 00663 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ 00664 00665 /* ITM Trace Control Register Definitions */ 00666 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ 00667 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 00668 00669 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ 00670 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ 00671 00672 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ 00673 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 00674 00675 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ 00676 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 00677 00678 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ 00679 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 00680 00681 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ 00682 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 00683 00684 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ 00685 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 00686 00687 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ 00688 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 00689 00690 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ 00691 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ 00692 00693 /* ITM Integration Write Register Definitions */ 00694 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ 00695 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ 00696 00697 /* ITM Integration Read Register Definitions */ 00698 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ 00699 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ 00700 00701 /* ITM Integration Mode Control Register Definitions */ 00702 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ 00703 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ 00704 00705 /* ITM Lock Status Register Definitions */ 00706 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ 00707 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 00708 00709 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ 00710 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 00711 00712 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ 00713 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ 00714 00715 /*@}*/ /* end of group CMSIS_ITM */ 00716 00717 00718 /** \ingroup CMSIS_core_register 00719 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 00720 \brief Type definitions for the Data Watchpoint and Trace (DWT) 00721 @{ 00722 */ 00723 00724 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 00725 */ 00726 typedef struct 00727 { 00728 __IO uint32_t CTRL ; /*!< Offset: 0x000 (R/W) Control Register */ 00729 __IO uint32_t CYCCNT ; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 00730 __IO uint32_t CPICNT ; /*!< Offset: 0x008 (R/W) CPI Count Register */ 00731 __IO uint32_t EXCCNT ; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 00732 __IO uint32_t SLEEPCNT ; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 00733 __IO uint32_t LSUCNT ; /*!< Offset: 0x014 (R/W) LSU Count Register */ 00734 __IO uint32_t FOLDCNT ; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 00735 __I uint32_t PCSR ; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 00736 __IO uint32_t COMP0 ; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 00737 __IO uint32_t MASK0 ; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 00738 __IO uint32_t FUNCTION0 ; /*!< Offset: 0x028 (R/W) Function Register 0 */ 00739 uint32_t RESERVED0[1]; 00740 __IO uint32_t COMP1 ; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 00741 __IO uint32_t MASK1 ; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 00742 __IO uint32_t FUNCTION1 ; /*!< Offset: 0x038 (R/W) Function Register 1 */ 00743 uint32_t RESERVED1[1]; 00744 __IO uint32_t COMP2 ; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 00745 __IO uint32_t MASK2 ; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 00746 __IO uint32_t FUNCTION2 ; /*!< Offset: 0x048 (R/W) Function Register 2 */ 00747 uint32_t RESERVED2[1]; 00748 __IO uint32_t COMP3 ; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 00749 __IO uint32_t MASK3 ; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 00750 __IO uint32_t FUNCTION3 ; /*!< Offset: 0x058 (R/W) Function Register 3 */ 00751 } DWT_Type; 00752 00753 /* DWT Control Register Definitions */ 00754 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ 00755 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 00756 00757 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ 00758 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 00759 00760 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ 00761 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 00762 00763 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ 00764 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 00765 00766 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ 00767 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 00768 00769 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ 00770 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 00771 00772 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ 00773 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 00774 00775 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ 00776 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 00777 00778 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ 00779 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 00780 00781 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ 00782 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 00783 00784 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ 00785 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 00786 00787 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ 00788 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 00789 00790 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ 00791 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 00792 00793 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ 00794 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 00795 00796 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ 00797 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 00798 00799 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ 00800 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 00801 00802 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ 00803 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 00804 00805 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ 00806 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ 00807 00808 /* DWT CPI Count Register Definitions */ 00809 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ 00810 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ 00811 00812 /* DWT Exception Overhead Count Register Definitions */ 00813 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ 00814 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ 00815 00816 /* DWT Sleep Count Register Definitions */ 00817 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ 00818 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 00819 00820 /* DWT LSU Count Register Definitions */ 00821 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ 00822 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ 00823 00824 /* DWT Folded-instruction Count Register Definitions */ 00825 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ 00826 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ 00827 00828 /* DWT Comparator Mask Register Definitions */ 00829 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ 00830 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ 00831 00832 /* DWT Comparator Function Register Definitions */ 00833 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ 00834 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 00835 00836 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ 00837 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ 00838 00839 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ 00840 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ 00841 00842 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ 00843 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 00844 00845 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ 00846 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ 00847 00848 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ 00849 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ 00850 00851 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ 00852 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ 00853 00854 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ 00855 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ 00856 00857 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ 00858 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ 00859 00860 /*@}*/ /* end of group CMSIS_DWT */ 00861 00862 00863 /** \ingroup CMSIS_core_register 00864 \defgroup CMSIS_TPI Trace Port Interface (TPI) 00865 \brief Type definitions for the Trace Port Interface (TPI) 00866 @{ 00867 */ 00868 00869 /** \brief Structure type to access the Trace Port Interface Register (TPI). 00870 */ 00871 typedef struct 00872 { 00873 __IO uint32_t SSPSR ; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 00874 __IO uint32_t CSPSR ; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 00875 uint32_t RESERVED0[2]; 00876 __IO uint32_t ACPR ; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 00877 uint32_t RESERVED1[55]; 00878 __IO uint32_t SPPR ; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 00879 uint32_t RESERVED2[131]; 00880 __I uint32_t FFSR ; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 00881 __IO uint32_t FFCR ; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 00882 __I uint32_t FSCR ; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 00883 uint32_t RESERVED3[759]; 00884 __I uint32_t TRIGGER ; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ 00885 __I uint32_t FIFO0 ; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 00886 __I uint32_t ITATBCTR2 ; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 00887 uint32_t RESERVED4[1]; 00888 __I uint32_t ITATBCTR0 ; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 00889 __I uint32_t FIFO1 ; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 00890 __IO uint32_t ITCTRL ; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 00891 uint32_t RESERVED5[39]; 00892 __IO uint32_t CLAIMSET ; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 00893 __IO uint32_t CLAIMCLR ; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 00894 uint32_t RESERVED7[8]; 00895 __I uint32_t DEVID ; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 00896 __I uint32_t DEVTYPE ; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 00897 } TPI_Type; 00898 00899 /* TPI Asynchronous Clock Prescaler Register Definitions */ 00900 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ 00901 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ 00902 00903 /* TPI Selected Pin Protocol Register Definitions */ 00904 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ 00905 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ 00906 00907 /* TPI Formatter and Flush Status Register Definitions */ 00908 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ 00909 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 00910 00911 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ 00912 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 00913 00914 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ 00915 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 00916 00917 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ 00918 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ 00919 00920 /* TPI Formatter and Flush Control Register Definitions */ 00921 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ 00922 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 00923 00924 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ 00925 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 00926 00927 /* TPI TRIGGER Register Definitions */ 00928 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ 00929 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ 00930 00931 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 00932 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ 00933 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 00934 00935 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ 00936 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 00937 00938 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ 00939 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 00940 00941 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ 00942 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 00943 00944 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ 00945 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 00946 00947 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ 00948 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 00949 00950 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ 00951 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ 00952 00953 /* TPI ITATBCTR2 Register Definitions */ 00954 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ 00955 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ 00956 00957 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 00958 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ 00959 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 00960 00961 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ 00962 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 00963 00964 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ 00965 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 00966 00967 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ 00968 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 00969 00970 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ 00971 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 00972 00973 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ 00974 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 00975 00976 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ 00977 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ 00978 00979 /* TPI ITATBCTR0 Register Definitions */ 00980 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ 00981 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ 00982 00983 /* TPI Integration Mode Control Register Definitions */ 00984 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ 00985 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ 00986 00987 /* TPI DEVID Register Definitions */ 00988 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ 00989 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 00990 00991 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ 00992 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 00993 00994 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ 00995 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 00996 00997 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ 00998 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 00999 01000 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ 01001 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 01002 01003 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ 01004 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ 01005 01006 /* TPI DEVTYPE Register Definitions */ 01007 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ 01008 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ 01009 01010 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ 01011 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 01012 01013 /*@}*/ /* end of group CMSIS_TPI */ 01014 01015 01016 #if (__MPU_PRESENT == 1) 01017 /** \ingroup CMSIS_core_register 01018 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 01019 \brief Type definitions for the Memory Protection Unit (MPU) 01020 @{ 01021 */ 01022 01023 /** \brief Structure type to access the Memory Protection Unit (MPU). 01024 */ 01025 typedef struct 01026 { 01027 __I uint32_t TYPE ; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 01028 __IO uint32_t CTRL ; /*!< Offset: 0x004 (R/W) MPU Control Register */ 01029 __IO uint32_t RNR ; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 01030 __IO uint32_t RBAR ; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 01031 __IO uint32_t RASR ; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 01032 __IO uint32_t RBAR_A1 ; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 01033 __IO uint32_t RASR_A1 ; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ 01034 __IO uint32_t RBAR_A2 ; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ 01035 __IO uint32_t RASR_A2 ; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ 01036 __IO uint32_t RBAR_A3 ; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ 01037 __IO uint32_t RASR_A3 ; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ 01038 } MPU_Type; 01039 01040 /* MPU Type Register */ 01041 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ 01042 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 01043 01044 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ 01045 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 01046 01047 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ 01048 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ 01049 01050 /* MPU Control Register */ 01051 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ 01052 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 01053 01054 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ 01055 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 01056 01057 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ 01058 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ 01059 01060 /* MPU Region Number Register */ 01061 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ 01062 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ 01063 01064 /* MPU Region Base Address Register */ 01065 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ 01066 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 01067 01068 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ 01069 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 01070 01071 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ 01072 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ 01073 01074 /* MPU Region Attribute and Size Register */ 01075 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ 01076 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 01077 01078 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ 01079 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 01080 01081 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ 01082 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 01083 01084 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ 01085 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 01086 01087 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ 01088 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 01089 01090 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ 01091 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 01092 01093 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ 01094 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 01095 01096 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ 01097 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 01098 01099 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ 01100 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 01101 01102 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ 01103 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ 01104 01105 /*@} end of group CMSIS_MPU */ 01106 #endif 01107 01108 01109 /** \ingroup CMSIS_core_register 01110 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 01111 \brief Type definitions for the Core Debug Registers 01112 @{ 01113 */ 01114 01115 /** \brief Structure type to access the Core Debug Register (CoreDebug). 01116 */ 01117 typedef struct 01118 { 01119 __IO uint32_t DHCSR ; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 01120 __O uint32_t DCRSR ; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 01121 __IO uint32_t DCRDR ; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 01122 __IO uint32_t DEMCR ; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 01123 } CoreDebug_Type; 01124 01125 /* Debug Halting Control and Status Register */ 01126 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ 01127 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 01128 01129 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ 01130 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 01131 01132 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 01133 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 01134 01135 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ 01136 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 01137 01138 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ 01139 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 01140 01141 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ 01142 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 01143 01144 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ 01145 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 01146 01147 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 01148 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 01149 01150 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ 01151 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 01152 01153 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ 01154 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 01155 01156 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ 01157 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 01158 01159 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 01160 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 01161 01162 /* Debug Core Register Selector Register */ 01163 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ 01164 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 01165 01166 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ 01167 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ 01168 01169 /* Debug Exception and Monitor Control Register */ 01170 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ 01171 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 01172 01173 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ 01174 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 01175 01176 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ 01177 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 01178 01179 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ 01180 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 01181 01182 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ 01183 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 01184 01185 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ 01186 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 01187 01188 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ 01189 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 01190 01191 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ 01192 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 01193 01194 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ 01195 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 01196 01197 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ 01198 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 01199 01200 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 01201 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 01202 01203 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ 01204 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 01205 01206 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ 01207 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 01208 01209 /*@} end of group CMSIS_CoreDebug */ 01210 01211 01212 /** \ingroup CMSIS_core_register 01213 \defgroup CMSIS_core_base Core Definitions 01214 \brief Definitions for base addresses, unions, and structures. 01215 @{ 01216 */ 01217 01218 /* Memory mapping of Cortex-M3 Hardware */ 01219 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 01220 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 01221 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 01222 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 01223 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 01224 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 01225 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 01226 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 01227 01228 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 01229 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 01230 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 01231 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 01232 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 01233 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 01234 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 01235 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 01236 01237 #if (__MPU_PRESENT == 1) 01238 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 01239 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 01240 #endif 01241 01242 /*@} */ 01243 01244 01245 01246 /******************************************************************************* 01247 * Hardware Abstraction Layer 01248 Core Function Interface contains: 01249 - Core NVIC Functions 01250 - Core SysTick Functions 01251 - Core Debug Functions 01252 - Core Register Access Functions 01253 ******************************************************************************/ 01254 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 01255 */ 01256 01257 01258 01259 /* ########################## NVIC functions #################################### */ 01260 /** \ingroup CMSIS_Core_FunctionInterface 01261 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 01262 \brief Functions that manage interrupts and exceptions via the NVIC. 01263 @{ 01264 */ 01265 01266 /** \brief Set Priority Grouping 01267 01268 The function sets the priority grouping field using the required unlock sequence. 01269 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 01270 Only values from 0..7 are used. 01271 In case of a conflict between priority grouping and available 01272 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01273 01274 \param [in] PriorityGroup Priority grouping field. 01275 */ 01276 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 01277 { 01278 uint32_t reg_value; 01279 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ 01280 01281 reg_value = SCB->AIRCR; /* read old register configuration */ 01282 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ 01283 reg_value = (reg_value | 01284 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | 01285 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ 01286 SCB->AIRCR = reg_value; 01287 } 01288 01289 01290 /** \brief Get Priority Grouping 01291 01292 The function reads the priority grouping field from the NVIC Interrupt Controller. 01293 01294 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 01295 */ 01296 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) 01297 { 01298 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ 01299 } 01300 01301 01302 /** \brief Enable External Interrupt 01303 01304 The function enables a device-specific interrupt in the NVIC interrupt controller. 01305 01306 \param [in] IRQn External interrupt number. Value cannot be negative. 01307 */ 01308 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn ) 01309 { 01310 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn ) & 0x1F)); /* enable interrupt */ 01311 } 01312 01313 01314 /** \brief Disable External Interrupt 01315 01316 The function disables a device-specific interrupt in the NVIC interrupt controller. 01317 01318 \param [in] IRQn External interrupt number. Value cannot be negative. 01319 */ 01320 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn ) 01321 { 01322 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn ) & 0x1F)); /* disable interrupt */ 01323 } 01324 01325 01326 /** \brief Get Pending Interrupt 01327 01328 The function reads the pending register in the NVIC and returns the pending bit 01329 for the specified interrupt. 01330 01331 \param [in] IRQn Interrupt number. 01332 01333 \return 0 Interrupt status is not pending. 01334 \return 1 Interrupt status is pending. 01335 */ 01336 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn ) 01337 { 01338 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ 01339 } 01340 01341 01342 /** \brief Set Pending Interrupt 01343 01344 The function sets the pending bit of an external interrupt. 01345 01346 \param [in] IRQn Interrupt number. Value cannot be negative. 01347 */ 01348 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn ) 01349 { 01350 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn ) & 0x1F)); /* set interrupt pending */ 01351 } 01352 01353 01354 /** \brief Clear Pending Interrupt 01355 01356 The function clears the pending bit of an external interrupt. 01357 01358 \param [in] IRQn External interrupt number. Value cannot be negative. 01359 */ 01360 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn ) 01361 { 01362 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn ) & 0x1F)); /* Clear pending interrupt */ 01363 } 01364 01365 01366 /** \brief Get Active Interrupt 01367 01368 The function reads the active register in NVIC and returns the active bit. 01369 01370 \param [in] IRQn Interrupt number. 01371 01372 \return 0 Interrupt status is not active. 01373 \return 1 Interrupt status is active. 01374 */ 01375 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn ) 01376 { 01377 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ 01378 } 01379 01380 01381 /** \brief Set Interrupt Priority 01382 01383 The function sets the priority of an interrupt. 01384 01385 \note The priority cannot be set for every core interrupt. 01386 01387 \param [in] IRQn Interrupt number. 01388 \param [in] priority Priority to set. 01389 */ 01390 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn , uint32_t priority) 01391 { 01392 if(IRQn < 0) { 01393 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ 01394 else { 01395 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ 01396 } 01397 01398 01399 /** \brief Get Interrupt Priority 01400 01401 The function reads the priority of an interrupt. The interrupt 01402 number can be positive to specify an external (device specific) 01403 interrupt, or negative to specify an internal (core) interrupt. 01404 01405 01406 \param [in] IRQn Interrupt number. 01407 \return Interrupt Priority. Value is aligned automatically to the implemented 01408 priority bits of the microcontroller. 01409 */ 01410 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn ) 01411 { 01412 01413 if(IRQn < 0) { 01414 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ 01415 else { 01416 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 01417 } 01418 01419 01420 /** \brief Encode Priority 01421 01422 The function encodes the priority for an interrupt with the given priority group, 01423 preemptive priority value, and subpriority value. 01424 In case of a conflict between priority grouping and available 01425 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. 01426 01427 \param [in] PriorityGroup Used priority group. 01428 \param [in] PreemptPriority Preemptive priority value (starting from 0). 01429 \param [in] SubPriority Subpriority value (starting from 0). 01430 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 01431 */ 01432 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 01433 { 01434 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 01435 uint32_t PreemptPriorityBits; 01436 uint32_t SubPriorityBits; 01437 01438 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 01439 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 01440 01441 return ( 01442 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | 01443 ((SubPriority & ((1 << (SubPriorityBits )) - 1))) 01444 ); 01445 } 01446 01447 01448 /** \brief Decode Priority 01449 01450 The function decodes an interrupt priority value with a given priority group to 01451 preemptive priority value and subpriority value. 01452 In case of a conflict between priority grouping and available 01453 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. 01454 01455 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 01456 \param [in] PriorityGroup Used priority group. 01457 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 01458 \param [out] pSubPriority Subpriority value (starting from 0). 01459 */ 01460 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) 01461 { 01462 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 01463 uint32_t PreemptPriorityBits; 01464 uint32_t SubPriorityBits; 01465 01466 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 01467 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 01468 01469 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); 01470 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); 01471 } 01472 01473 01474 /** \brief System Reset 01475 01476 The function initiates a system reset request to reset the MCU. 01477 */ 01478 __STATIC_INLINE void NVIC_SystemReset(void) 01479 { 01480 __DSB(); /* Ensure all outstanding memory accesses included 01481 buffered write are completed before reset */ 01482 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | 01483 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 01484 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ 01485 __DSB(); /* Ensure completion of memory access */ 01486 while(1); /* wait until reset */ 01487 } 01488 01489 /*@} end of CMSIS_Core_NVICFunctions */ 01490 01491 01492 01493 /* ################################## SysTick function ############################################ */ 01494 /** \ingroup CMSIS_Core_FunctionInterface 01495 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 01496 \brief Functions that configure the System. 01497 @{ 01498 */ 01499 01500 #if (__Vendor_SysTickConfig == 0) 01501 01502 /** \brief System Tick Configuration 01503 01504 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 01505 Counter is in free running mode to generate periodic interrupts. 01506 01507 \param [in] ticks Number of ticks between two interrupts. 01508 01509 \return 0 Function succeeded. 01510 \return 1 Function failed. 01511 01512 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 01513 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 01514 must contain a vendor-specific implementation of this function. 01515 01516 */ 01517 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 01518 { 01519 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 01520 01521 SysTick->LOAD = ticks - 1; /* set reload register */ 01522 NVIC_SetPriority (SysTick_IRQn , (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ 01523 SysTick->VAL = 0; /* Load the SysTick Counter Value */ 01524 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 01525 SysTick_CTRL_TICKINT_Msk | 01526 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 01527 return (0); /* Function successful */ 01528 } 01529 01530 #endif 01531 01532 /*@} end of CMSIS_Core_SysTickFunctions */ 01533 01534 01535 01536 /* ##################################### Debug In/Output function ########################################### */ 01537 /** \ingroup CMSIS_Core_FunctionInterface 01538 \defgroup CMSIS_core_DebugFunctions ITM Functions 01539 \brief Functions that access the ITM debug interface. 01540 @{ 01541 */ 01542 01543 extern volatile int32_t ITM_RxBuffer ; /*!< External variable to receive characters. */ 01544 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 01545 01546 01547 /** \brief ITM Send Character 01548 01549 The function transmits a character via the ITM channel 0, and 01550 \li Just returns when no debugger is connected that has booked the output. 01551 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 01552 01553 \param [in] ch Character to transmit. 01554 01555 \returns Character to transmit. 01556 */ 01557 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 01558 { 01559 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ 01560 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ 01561 { 01562 while (ITM->PORT[0].u32 == 0); 01563 ITM->PORT[0].u8 = (uint8_t) ch; 01564 } 01565 return (ch); 01566 } 01567 01568 01569 /** \brief ITM Receive Character 01570 01571 The function inputs a character via the external variable \ref ITM_RxBuffer. 01572 01573 \return Received character. 01574 \return -1 No character pending. 01575 */ 01576 __STATIC_INLINE int32_t ITM_ReceiveChar (void) { 01577 int32_t ch = -1; /* no character available */ 01578 01579 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { 01580 ch = ITM_RxBuffer ; 01581 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 01582 } 01583 01584 return (ch); 01585 } 01586 01587 01588 /** \brief ITM Check Character 01589 01590 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 01591 01592 \return 0 No character available. 01593 \return 1 Character available. 01594 */ 01595 __STATIC_INLINE int32_t ITM_CheckChar (void) { 01596 01597 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { 01598 return (0); /* no character available */ 01599 } else { 01600 return (1); /* character available */ 01601 } 01602 } 01603 01604 /*@} end of CMSIS_core_DebugFunctions */ 01605 01606 #endif /* __CORE_CM3_H_DEPENDANT */ 01607 01608 #endif /* __CMSIS_GENERIC */ 01609 01610 #ifdef __cplusplus 01611 } 01612 #endif
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