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LPC1768/core_cmFunc.h@64:75c1708b266b, 2013-07-05 (annotated)

Committer:
ldyz
Date:
Fri Jul 05 13:16:13 2013 +0000
Revision:
64:75c1708b266b
Parent:
46:890817bdcffb 
test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 40:976df7c37ad5 1 /**************************************************************************//**
emilmont 40:976df7c37ad5 2 * @file core_cmFunc.h
emilmont 40:976df7c37ad5 3 * @brief CMSIS Cortex-M Core Function Access Header File
emimon01 46:890817bdcffb 4 * @version V3.02
emimon01 46:890817bdcffb 5 * @date 24. May 2012
emilmont 40:976df7c37ad5 6 *
emilmont 40:976df7c37ad5 7 * @note
emimon01 46:890817bdcffb 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
emilmont 40:976df7c37ad5 9 *
emilmont 40:976df7c37ad5 10 * @par
emimon01 46:890817bdcffb 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emimon01 46:890817bdcffb 12 * processor based microcontrollers. This file can be freely distributed
emimon01 46:890817bdcffb 13 * within development tools that are supporting such ARM based processors.
emilmont 40:976df7c37ad5 14 *
emilmont 40:976df7c37ad5 15 * @par
emilmont 40:976df7c37ad5 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 40:976df7c37ad5 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 40:976df7c37ad5 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 40:976df7c37ad5 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 40:976df7c37ad5 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 40:976df7c37ad5 21 *
emilmont 40:976df7c37ad5 22 ******************************************************************************/
emilmont 40:976df7c37ad5 23
emilmont 40:976df7c37ad5 24 #ifndef __CORE_CMFUNC_H
emilmont 40:976df7c37ad5 25 #define __CORE_CMFUNC_H
emilmont 40:976df7c37ad5 26
emilmont 40:976df7c37ad5 27
emilmont 40:976df7c37ad5 28 /* ########################### Core Function Access ########################### */
emimon01 46:890817bdcffb 29 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 40:976df7c37ad5 30 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
emilmont 40:976df7c37ad5 31 @{
emilmont 40:976df7c37ad5 32 */
emilmont 40:976df7c37ad5 33
emilmont 40:976df7c37ad5 34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 40:976df7c37ad5 35 /* ARM armcc specific functions */
emilmont 40:976df7c37ad5 36
emilmont 40:976df7c37ad5 37 #if (__ARMCC_VERSION < 400677)
emilmont 40:976df7c37ad5 38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
emilmont 40:976df7c37ad5 39 #endif
emilmont 40:976df7c37ad5 40
emilmont 40:976df7c37ad5 41 /* intrinsic void __enable_irq(); */
emilmont 40:976df7c37ad5 42 /* intrinsic void __disable_irq(); */
emilmont 40:976df7c37ad5 43
emilmont 40:976df7c37ad5 44 /** \brief Get Control Register
emilmont 40:976df7c37ad5 45
emilmont 40:976df7c37ad5 46 This function returns the content of the Control Register.
emilmont 40:976df7c37ad5 47
emilmont 40:976df7c37ad5 48 \return Control Register value
emilmont 40:976df7c37ad5 49 */
emimon01 46:890817bdcffb 50 __STATIC_INLINE uint32_t __get_CONTROL(void)
emilmont 40:976df7c37ad5 51 {
emilmont 40:976df7c37ad5 52 register uint32_t __regControl __ASM("control");
emilmont 40:976df7c37ad5 53 return(__regControl);
emilmont 40:976df7c37ad5 54 }
emilmont 40:976df7c37ad5 55
emilmont 40:976df7c37ad5 56
emilmont 40:976df7c37ad5 57 /** \brief Set Control Register
emilmont 40:976df7c37ad5 58
emilmont 40:976df7c37ad5 59 This function writes the given value to the Control Register.
emilmont 40:976df7c37ad5 60
emilmont 40:976df7c37ad5 61 \param [in] control Control Register value to set
emilmont 40:976df7c37ad5 62 */
emimon01 46:890817bdcffb 63 __STATIC_INLINE void __set_CONTROL(uint32_t control)
emilmont 40:976df7c37ad5 64 {
emilmont 40:976df7c37ad5 65 register uint32_t __regControl __ASM("control");
emilmont 40:976df7c37ad5 66 __regControl = control;
emilmont 40:976df7c37ad5 67 }
emilmont 40:976df7c37ad5 68
emilmont 40:976df7c37ad5 69
emilmont 40:976df7c37ad5 70 /** \brief Get IPSR Register
emilmont 40:976df7c37ad5 71
emilmont 40:976df7c37ad5 72 This function returns the content of the IPSR Register.
emilmont 40:976df7c37ad5 73
emilmont 40:976df7c37ad5 74 \return IPSR Register value
emilmont 40:976df7c37ad5 75 */
emimon01 46:890817bdcffb 76 __STATIC_INLINE uint32_t __get_IPSR(void)
emilmont 40:976df7c37ad5 77 {
emilmont 40:976df7c37ad5 78 register uint32_t __regIPSR __ASM("ipsr");
emilmont 40:976df7c37ad5 79 return(__regIPSR);
emilmont 40:976df7c37ad5 80 }
emilmont 40:976df7c37ad5 81
emilmont 40:976df7c37ad5 82
emilmont 40:976df7c37ad5 83 /** \brief Get APSR Register
emilmont 40:976df7c37ad5 84
emilmont 40:976df7c37ad5 85 This function returns the content of the APSR Register.
emilmont 40:976df7c37ad5 86
emilmont 40:976df7c37ad5 87 \return APSR Register value
emilmont 40:976df7c37ad5 88 */
emimon01 46:890817bdcffb 89 __STATIC_INLINE uint32_t __get_APSR(void)
emilmont 40:976df7c37ad5 90 {
emilmont 40:976df7c37ad5 91 register uint32_t __regAPSR __ASM("apsr");
emilmont 40:976df7c37ad5 92 return(__regAPSR);
emilmont 40:976df7c37ad5 93 }
emilmont 40:976df7c37ad5 94
emilmont 40:976df7c37ad5 95
emilmont 40:976df7c37ad5 96 /** \brief Get xPSR Register
emilmont 40:976df7c37ad5 97
emilmont 40:976df7c37ad5 98 This function returns the content of the xPSR Register.
emilmont 40:976df7c37ad5 99
emilmont 40:976df7c37ad5 100 \return xPSR Register value
emilmont 40:976df7c37ad5 101 */
emimon01 46:890817bdcffb 102 __STATIC_INLINE uint32_t __get_xPSR(void)
emilmont 40:976df7c37ad5 103 {
emilmont 40:976df7c37ad5 104 register uint32_t __regXPSR __ASM("xpsr");
emilmont 40:976df7c37ad5 105 return(__regXPSR);
emilmont 40:976df7c37ad5 106 }
emilmont 40:976df7c37ad5 107
emilmont 40:976df7c37ad5 108
emilmont 40:976df7c37ad5 109 /** \brief Get Process Stack Pointer
emilmont 40:976df7c37ad5 110
emilmont 40:976df7c37ad5 111 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 40:976df7c37ad5 112
emilmont 40:976df7c37ad5 113 \return PSP Register value
emilmont 40:976df7c37ad5 114 */
emimon01 46:890817bdcffb 115 __STATIC_INLINE uint32_t __get_PSP(void)
emilmont 40:976df7c37ad5 116 {
emilmont 40:976df7c37ad5 117 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 40:976df7c37ad5 118 return(__regProcessStackPointer);
emilmont 40:976df7c37ad5 119 }
emilmont 40:976df7c37ad5 120
emilmont 40:976df7c37ad5 121
emilmont 40:976df7c37ad5 122 /** \brief Set Process Stack Pointer
emilmont 40:976df7c37ad5 123
emilmont 40:976df7c37ad5 124 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 40:976df7c37ad5 125
emilmont 40:976df7c37ad5 126 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 40:976df7c37ad5 127 */
emimon01 46:890817bdcffb 128 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 40:976df7c37ad5 129 {
emilmont 40:976df7c37ad5 130 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 40:976df7c37ad5 131 __regProcessStackPointer = topOfProcStack;
emilmont 40:976df7c37ad5 132 }
emilmont 40:976df7c37ad5 133
emilmont 40:976df7c37ad5 134
emilmont 40:976df7c37ad5 135 /** \brief Get Main Stack Pointer
emilmont 40:976df7c37ad5 136
emilmont 40:976df7c37ad5 137 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 40:976df7c37ad5 138
emilmont 40:976df7c37ad5 139 \return MSP Register value
emilmont 40:976df7c37ad5 140 */
emimon01 46:890817bdcffb 141 __STATIC_INLINE uint32_t __get_MSP(void)
emilmont 40:976df7c37ad5 142 {
emilmont 40:976df7c37ad5 143 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 40:976df7c37ad5 144 return(__regMainStackPointer);
emilmont 40:976df7c37ad5 145 }
emilmont 40:976df7c37ad5 146
emilmont 40:976df7c37ad5 147
emilmont 40:976df7c37ad5 148 /** \brief Set Main Stack Pointer
emilmont 40:976df7c37ad5 149
emilmont 40:976df7c37ad5 150 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 40:976df7c37ad5 151
emilmont 40:976df7c37ad5 152 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 40:976df7c37ad5 153 */
emimon01 46:890817bdcffb 154 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 40:976df7c37ad5 155 {
emilmont 40:976df7c37ad5 156 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 40:976df7c37ad5 157 __regMainStackPointer = topOfMainStack;
emilmont 40:976df7c37ad5 158 }
emilmont 40:976df7c37ad5 159
emilmont 40:976df7c37ad5 160
emilmont 40:976df7c37ad5 161 /** \brief Get Priority Mask
emilmont 40:976df7c37ad5 162
emilmont 40:976df7c37ad5 163 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 40:976df7c37ad5 164
emilmont 40:976df7c37ad5 165 \return Priority Mask value
emilmont 40:976df7c37ad5 166 */
emimon01 46:890817bdcffb 167 __STATIC_INLINE uint32_t __get_PRIMASK(void)
emilmont 40:976df7c37ad5 168 {
emilmont 40:976df7c37ad5 169 register uint32_t __regPriMask __ASM("primask");
emilmont 40:976df7c37ad5 170 return(__regPriMask);
emilmont 40:976df7c37ad5 171 }
emilmont 40:976df7c37ad5 172
emilmont 40:976df7c37ad5 173
emilmont 40:976df7c37ad5 174 /** \brief Set Priority Mask
emilmont 40:976df7c37ad5 175
emilmont 40:976df7c37ad5 176 This function assigns the given value to the Priority Mask Register.
emilmont 40:976df7c37ad5 177
emilmont 40:976df7c37ad5 178 \param [in] priMask Priority Mask
emilmont 40:976df7c37ad5 179 */
emimon01 46:890817bdcffb 180 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 40:976df7c37ad5 181 {
emilmont 40:976df7c37ad5 182 register uint32_t __regPriMask __ASM("primask");
emilmont 40:976df7c37ad5 183 __regPriMask = (priMask);
emilmont 40:976df7c37ad5 184 }
emimon01 46:890817bdcffb 185
emilmont 40:976df7c37ad5 186
emilmont 40:976df7c37ad5 187 #if (__CORTEX_M >= 0x03)
emilmont 40:976df7c37ad5 188
emilmont 40:976df7c37ad5 189 /** \brief Enable FIQ
emilmont 40:976df7c37ad5 190
emilmont 40:976df7c37ad5 191 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 40:976df7c37ad5 192 Can only be executed in Privileged modes.
emilmont 40:976df7c37ad5 193 */
emilmont 40:976df7c37ad5 194 #define __enable_fault_irq __enable_fiq
emilmont 40:976df7c37ad5 195
emilmont 40:976df7c37ad5 196
emilmont 40:976df7c37ad5 197 /** \brief Disable FIQ
emilmont 40:976df7c37ad5 198
emilmont 40:976df7c37ad5 199 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 40:976df7c37ad5 200 Can only be executed in Privileged modes.
emilmont 40:976df7c37ad5 201 */
emilmont 40:976df7c37ad5 202 #define __disable_fault_irq __disable_fiq
emilmont 40:976df7c37ad5 203
emilmont 40:976df7c37ad5 204
emilmont 40:976df7c37ad5 205 /** \brief Get Base Priority
emilmont 40:976df7c37ad5 206
emilmont 40:976df7c37ad5 207 This function returns the current value of the Base Priority register.
emilmont 40:976df7c37ad5 208
emilmont 40:976df7c37ad5 209 \return Base Priority register value
emilmont 40:976df7c37ad5 210 */
emimon01 46:890817bdcffb 211 __STATIC_INLINE uint32_t __get_BASEPRI(void)
emilmont 40:976df7c37ad5 212 {
emilmont 40:976df7c37ad5 213 register uint32_t __regBasePri __ASM("basepri");
emilmont 40:976df7c37ad5 214 return(__regBasePri);
emilmont 40:976df7c37ad5 215 }
emilmont 40:976df7c37ad5 216
emilmont 40:976df7c37ad5 217
emilmont 40:976df7c37ad5 218 /** \brief Set Base Priority
emilmont 40:976df7c37ad5 219
emilmont 40:976df7c37ad5 220 This function assigns the given value to the Base Priority register.
emilmont 40:976df7c37ad5 221
emilmont 40:976df7c37ad5 222 \param [in] basePri Base Priority value to set
emilmont 40:976df7c37ad5 223 */
emimon01 46:890817bdcffb 224 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
emilmont 40:976df7c37ad5 225 {
emilmont 40:976df7c37ad5 226 register uint32_t __regBasePri __ASM("basepri");
emilmont 40:976df7c37ad5 227 __regBasePri = (basePri & 0xff);
emilmont 40:976df7c37ad5 228 }
emimon01 46:890817bdcffb 229
emilmont 40:976df7c37ad5 230
emilmont 40:976df7c37ad5 231 /** \brief Get Fault Mask
emilmont 40:976df7c37ad5 232
emilmont 40:976df7c37ad5 233 This function returns the current value of the Fault Mask register.
emilmont 40:976df7c37ad5 234
emilmont 40:976df7c37ad5 235 \return Fault Mask register value
emilmont 40:976df7c37ad5 236 */
emimon01 46:890817bdcffb 237 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
emilmont 40:976df7c37ad5 238 {
emilmont 40:976df7c37ad5 239 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 40:976df7c37ad5 240 return(__regFaultMask);
emilmont 40:976df7c37ad5 241 }
emilmont 40:976df7c37ad5 242
emilmont 40:976df7c37ad5 243
emilmont 40:976df7c37ad5 244 /** \brief Set Fault Mask
emilmont 40:976df7c37ad5 245
emilmont 40:976df7c37ad5 246 This function assigns the given value to the Fault Mask register.
emilmont 40:976df7c37ad5 247
emilmont 40:976df7c37ad5 248 \param [in] faultMask Fault Mask value to set
emilmont 40:976df7c37ad5 249 */
emimon01 46:890817bdcffb 250 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 40:976df7c37ad5 251 {
emilmont 40:976df7c37ad5 252 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 40:976df7c37ad5 253 __regFaultMask = (faultMask & (uint32_t)1);
emilmont 40:976df7c37ad5 254 }
emilmont 40:976df7c37ad5 255
emilmont 40:976df7c37ad5 256 #endif /* (__CORTEX_M >= 0x03) */
emilmont 40:976df7c37ad5 257
emilmont 40:976df7c37ad5 258
emilmont 40:976df7c37ad5 259 #if (__CORTEX_M == 0x04)
emilmont 40:976df7c37ad5 260
emilmont 40:976df7c37ad5 261 /** \brief Get FPSCR
emilmont 40:976df7c37ad5 262
emilmont 40:976df7c37ad5 263 This function returns the current value of the Floating Point Status/Control register.
emilmont 40:976df7c37ad5 264
emilmont 40:976df7c37ad5 265 \return Floating Point Status/Control register value
emilmont 40:976df7c37ad5 266 */
emimon01 46:890817bdcffb 267 __STATIC_INLINE uint32_t __get_FPSCR(void)
emilmont 40:976df7c37ad5 268 {
emilmont 40:976df7c37ad5 269 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 40:976df7c37ad5 270 register uint32_t __regfpscr __ASM("fpscr");
emilmont 40:976df7c37ad5 271 return(__regfpscr);
emilmont 40:976df7c37ad5 272 #else
emilmont 40:976df7c37ad5 273 return(0);
emilmont 40:976df7c37ad5 274 #endif
emilmont 40:976df7c37ad5 275 }
emilmont 40:976df7c37ad5 276
emilmont 40:976df7c37ad5 277
emilmont 40:976df7c37ad5 278 /** \brief Set FPSCR
emilmont 40:976df7c37ad5 279
emilmont 40:976df7c37ad5 280 This function assigns the given value to the Floating Point Status/Control register.
emilmont 40:976df7c37ad5 281
emilmont 40:976df7c37ad5 282 \param [in] fpscr Floating Point Status/Control value to set
emilmont 40:976df7c37ad5 283 */
emimon01 46:890817bdcffb 284 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 40:976df7c37ad5 285 {
emilmont 40:976df7c37ad5 286 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 40:976df7c37ad5 287 register uint32_t __regfpscr __ASM("fpscr");
emilmont 40:976df7c37ad5 288 __regfpscr = (fpscr);
emilmont 40:976df7c37ad5 289 #endif
emilmont 40:976df7c37ad5 290 }
emilmont 40:976df7c37ad5 291
emilmont 40:976df7c37ad5 292 #endif /* (__CORTEX_M == 0x04) */
emilmont 40:976df7c37ad5 293
emilmont 40:976df7c37ad5 294
emilmont 40:976df7c37ad5 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emilmont 40:976df7c37ad5 296 /* IAR iccarm specific functions */
emilmont 40:976df7c37ad5 297
emilmont 40:976df7c37ad5 298 #include <cmsis_iar.h>
emilmont 40:976df7c37ad5 299
emimon01 46:890817bdcffb 300
emimon01 46:890817bdcffb 301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
emimon01 46:890817bdcffb 302 /* TI CCS specific functions */
emimon01 46:890817bdcffb 303
emimon01 46:890817bdcffb 304 #include <cmsis_ccs.h>
emimon01 46:890817bdcffb 305
emimon01 46:890817bdcffb 306
emilmont 40:976df7c37ad5 307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 40:976df7c37ad5 308 /* GNU gcc specific functions */
emilmont 40:976df7c37ad5 309
emilmont 40:976df7c37ad5 310 /** \brief Enable IRQ Interrupts
emilmont 40:976df7c37ad5 311
emilmont 40:976df7c37ad5 312 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
emilmont 40:976df7c37ad5 313 Can only be executed in Privileged modes.
emilmont 40:976df7c37ad5 314 */
emimon01 46:890817bdcffb 315 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
emilmont 40:976df7c37ad5 316 {
emimon01 46:890817bdcffb 317 __ASM volatile ("cpsie i" : : : "memory");
emilmont 40:976df7c37ad5 318 }
emilmont 40:976df7c37ad5 319
emilmont 40:976df7c37ad5 320
emilmont 40:976df7c37ad5 321 /** \brief Disable IRQ Interrupts
emilmont 40:976df7c37ad5 322
emilmont 40:976df7c37ad5 323 This function disables IRQ interrupts by setting the I-bit in the CPSR.
emilmont 40:976df7c37ad5 324 Can only be executed in Privileged modes.
emilmont 40:976df7c37ad5 325 */
emimon01 46:890817bdcffb 326 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
emilmont 40:976df7c37ad5 327 {
emimon01 46:890817bdcffb 328 __ASM volatile ("cpsid i" : : : "memory");
emilmont 40:976df7c37ad5 329 }
emilmont 40:976df7c37ad5 330
emilmont 40:976df7c37ad5 331
emilmont 40:976df7c37ad5 332 /** \brief Get Control Register
emilmont 40:976df7c37ad5 333
emilmont 40:976df7c37ad5 334 This function returns the content of the Control Register.
emilmont 40:976df7c37ad5 335
emilmont 40:976df7c37ad5 336 \return Control Register value
emilmont 40:976df7c37ad5 337 */
emimon01 46:890817bdcffb 338 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
emilmont 40:976df7c37ad5 339 {
emilmont 40:976df7c37ad5 340 uint32_t result;
emilmont 40:976df7c37ad5 341
emilmont 40:976df7c37ad5 342 __ASM volatile ("MRS %0, control" : "=r" (result) );
emilmont 40:976df7c37ad5 343 return(result);
emilmont 40:976df7c37ad5 344 }
emilmont 40:976df7c37ad5 345
emilmont 40:976df7c37ad5 346
emilmont 40:976df7c37ad5 347 /** \brief Set Control Register
emilmont 40:976df7c37ad5 348
emilmont 40:976df7c37ad5 349 This function writes the given value to the Control Register.
emilmont 40:976df7c37ad5 350
emilmont 40:976df7c37ad5 351 \param [in] control Control Register value to set
emilmont 40:976df7c37ad5 352 */
emimon01 46:890817bdcffb 353 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
emilmont 40:976df7c37ad5 354 {
emilmont 40:976df7c37ad5 355 __ASM volatile ("MSR control, %0" : : "r" (control) );
emilmont 40:976df7c37ad5 356 }
emilmont 40:976df7c37ad5 357
emilmont 40:976df7c37ad5 358
emilmont 40:976df7c37ad5 359 /** \brief Get IPSR Register
emilmont 40:976df7c37ad5 360
emilmont 40:976df7c37ad5 361 This function returns the content of the IPSR Register.
emilmont 40:976df7c37ad5 362
emilmont 40:976df7c37ad5 363 \return IPSR Register value
emilmont 40:976df7c37ad5 364 */
emimon01 46:890817bdcffb 365 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
emilmont 40:976df7c37ad5 366 {
emilmont 40:976df7c37ad5 367 uint32_t result;
emilmont 40:976df7c37ad5 368
emilmont 40:976df7c37ad5 369 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
emilmont 40:976df7c37ad5 370 return(result);
emilmont 40:976df7c37ad5 371 }
emilmont 40:976df7c37ad5 372
emilmont 40:976df7c37ad5 373
emilmont 40:976df7c37ad5 374 /** \brief Get APSR Register
emilmont 40:976df7c37ad5 375
emilmont 40:976df7c37ad5 376 This function returns the content of the APSR Register.
emilmont 40:976df7c37ad5 377
emilmont 40:976df7c37ad5 378 \return APSR Register value
emilmont 40:976df7c37ad5 379 */
emimon01 46:890817bdcffb 380 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
emilmont 40:976df7c37ad5 381 {
emilmont 40:976df7c37ad5 382 uint32_t result;
emilmont 40:976df7c37ad5 383
emilmont 40:976df7c37ad5 384 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
emilmont 40:976df7c37ad5 385 return(result);
emilmont 40:976df7c37ad5 386 }
emilmont 40:976df7c37ad5 387
emilmont 40:976df7c37ad5 388
emilmont 40:976df7c37ad5 389 /** \brief Get xPSR Register
emilmont 40:976df7c37ad5 390
emilmont 40:976df7c37ad5 391 This function returns the content of the xPSR Register.
emilmont 40:976df7c37ad5 392
emilmont 40:976df7c37ad5 393 \return xPSR Register value
emilmont 40:976df7c37ad5 394 */
emimon01 46:890817bdcffb 395 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
emilmont 40:976df7c37ad5 396 {
emilmont 40:976df7c37ad5 397 uint32_t result;
emilmont 40:976df7c37ad5 398
emilmont 40:976df7c37ad5 399 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
emilmont 40:976df7c37ad5 400 return(result);
emilmont 40:976df7c37ad5 401 }
emilmont 40:976df7c37ad5 402
emilmont 40:976df7c37ad5 403
emilmont 40:976df7c37ad5 404 /** \brief Get Process Stack Pointer
emilmont 40:976df7c37ad5 405
emilmont 40:976df7c37ad5 406 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 40:976df7c37ad5 407
emilmont 40:976df7c37ad5 408 \return PSP Register value
emilmont 40:976df7c37ad5 409 */
emimon01 46:890817bdcffb 410 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
emilmont 40:976df7c37ad5 411 {
emilmont 40:976df7c37ad5 412 register uint32_t result;
emilmont 40:976df7c37ad5 413
emilmont 40:976df7c37ad5 414 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
emilmont 40:976df7c37ad5 415 return(result);
emilmont 40:976df7c37ad5 416 }
emimon01 46:890817bdcffb 417
emilmont 40:976df7c37ad5 418
emilmont 40:976df7c37ad5 419 /** \brief Set Process Stack Pointer
emilmont 40:976df7c37ad5 420
emilmont 40:976df7c37ad5 421 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 40:976df7c37ad5 422
emilmont 40:976df7c37ad5 423 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 40:976df7c37ad5 424 */
emimon01 46:890817bdcffb 425 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 40:976df7c37ad5 426 {
emilmont 40:976df7c37ad5 427 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
emilmont 40:976df7c37ad5 428 }
emilmont 40:976df7c37ad5 429
emilmont 40:976df7c37ad5 430
emilmont 40:976df7c37ad5 431 /** \brief Get Main Stack Pointer
emilmont 40:976df7c37ad5 432
emilmont 40:976df7c37ad5 433 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 40:976df7c37ad5 434
emilmont 40:976df7c37ad5 435 \return MSP Register value
emilmont 40:976df7c37ad5 436 */
emimon01 46:890817bdcffb 437 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
emilmont 40:976df7c37ad5 438 {
emilmont 40:976df7c37ad5 439 register uint32_t result;
emilmont 40:976df7c37ad5 440
emilmont 40:976df7c37ad5 441 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
emilmont 40:976df7c37ad5 442 return(result);
emilmont 40:976df7c37ad5 443 }
emimon01 46:890817bdcffb 444
emilmont 40:976df7c37ad5 445
emilmont 40:976df7c37ad5 446 /** \brief Set Main Stack Pointer
emilmont 40:976df7c37ad5 447
emilmont 40:976df7c37ad5 448 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 40:976df7c37ad5 449
emilmont 40:976df7c37ad5 450 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 40:976df7c37ad5 451 */
emimon01 46:890817bdcffb 452 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 40:976df7c37ad5 453 {
emilmont 40:976df7c37ad5 454 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
emilmont 40:976df7c37ad5 455 }
emilmont 40:976df7c37ad5 456
emilmont 40:976df7c37ad5 457
emilmont 40:976df7c37ad5 458 /** \brief Get Priority Mask
emilmont 40:976df7c37ad5 459
emilmont 40:976df7c37ad5 460 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 40:976df7c37ad5 461
emilmont 40:976df7c37ad5 462 \return Priority Mask value
emilmont 40:976df7c37ad5 463 */
emimon01 46:890817bdcffb 464 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
emilmont 40:976df7c37ad5 465 {
emilmont 40:976df7c37ad5 466 uint32_t result;
emilmont 40:976df7c37ad5 467
emilmont 40:976df7c37ad5 468 __ASM volatile ("MRS %0, primask" : "=r" (result) );
emilmont 40:976df7c37ad5 469 return(result);
emilmont 40:976df7c37ad5 470 }
emilmont 40:976df7c37ad5 471
emilmont 40:976df7c37ad5 472
emilmont 40:976df7c37ad5 473 /** \brief Set Priority Mask
emilmont 40:976df7c37ad5 474
emilmont 40:976df7c37ad5 475 This function assigns the given value to the Priority Mask Register.
emilmont 40:976df7c37ad5 476
emilmont 40:976df7c37ad5 477 \param [in] priMask Priority Mask
emilmont 40:976df7c37ad5 478 */
emimon01 46:890817bdcffb 479 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 40:976df7c37ad5 480 {
emilmont 40:976df7c37ad5 481 __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
emilmont 40:976df7c37ad5 482 }
emimon01 46:890817bdcffb 483
emilmont 40:976df7c37ad5 484
emilmont 40:976df7c37ad5 485 #if (__CORTEX_M >= 0x03)
emilmont 40:976df7c37ad5 486
emilmont 40:976df7c37ad5 487 /** \brief Enable FIQ
emilmont 40:976df7c37ad5 488
emilmont 40:976df7c37ad5 489 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 40:976df7c37ad5 490 Can only be executed in Privileged modes.
emilmont 40:976df7c37ad5 491 */
emimon01 46:890817bdcffb 492 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
emilmont 40:976df7c37ad5 493 {
emimon01 46:890817bdcffb 494 __ASM volatile ("cpsie f" : : : "memory");
emilmont 40:976df7c37ad5 495 }
emilmont 40:976df7c37ad5 496
emilmont 40:976df7c37ad5 497
emilmont 40:976df7c37ad5 498 /** \brief Disable FIQ
emilmont 40:976df7c37ad5 499
emilmont 40:976df7c37ad5 500 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 40:976df7c37ad5 501 Can only be executed in Privileged modes.
emilmont 40:976df7c37ad5 502 */
emimon01 46:890817bdcffb 503 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
emilmont 40:976df7c37ad5 504 {
emimon01 46:890817bdcffb 505 __ASM volatile ("cpsid f" : : : "memory");
emilmont 40:976df7c37ad5 506 }
emilmont 40:976df7c37ad5 507
emilmont 40:976df7c37ad5 508
emilmont 40:976df7c37ad5 509 /** \brief Get Base Priority
emilmont 40:976df7c37ad5 510
emilmont 40:976df7c37ad5 511 This function returns the current value of the Base Priority register.
emilmont 40:976df7c37ad5 512
emilmont 40:976df7c37ad5 513 \return Base Priority register value
emilmont 40:976df7c37ad5 514 */
emimon01 46:890817bdcffb 515 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
emilmont 40:976df7c37ad5 516 {
emilmont 40:976df7c37ad5 517 uint32_t result;
emimon01 46:890817bdcffb 518
emilmont 40:976df7c37ad5 519 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
emilmont 40:976df7c37ad5 520 return(result);
emilmont 40:976df7c37ad5 521 }
emilmont 40:976df7c37ad5 522
emilmont 40:976df7c37ad5 523
emilmont 40:976df7c37ad5 524 /** \brief Set Base Priority
emilmont 40:976df7c37ad5 525
emilmont 40:976df7c37ad5 526 This function assigns the given value to the Base Priority register.
emilmont 40:976df7c37ad5 527
emilmont 40:976df7c37ad5 528 \param [in] basePri Base Priority value to set
emilmont 40:976df7c37ad5 529 */
emimon01 46:890817bdcffb 530 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
emilmont 40:976df7c37ad5 531 {
emilmont 40:976df7c37ad5 532 __ASM volatile ("MSR basepri, %0" : : "r" (value) );
emilmont 40:976df7c37ad5 533 }
emilmont 40:976df7c37ad5 534
emilmont 40:976df7c37ad5 535
emilmont 40:976df7c37ad5 536 /** \brief Get Fault Mask
emilmont 40:976df7c37ad5 537
emilmont 40:976df7c37ad5 538 This function returns the current value of the Fault Mask register.
emilmont 40:976df7c37ad5 539
emilmont 40:976df7c37ad5 540 \return Fault Mask register value
emilmont 40:976df7c37ad5 541 */
emimon01 46:890817bdcffb 542 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
emilmont 40:976df7c37ad5 543 {
emilmont 40:976df7c37ad5 544 uint32_t result;
emimon01 46:890817bdcffb 545
emilmont 40:976df7c37ad5 546 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
emilmont 40:976df7c37ad5 547 return(result);
emilmont 40:976df7c37ad5 548 }
emilmont 40:976df7c37ad5 549
emilmont 40:976df7c37ad5 550
emilmont 40:976df7c37ad5 551 /** \brief Set Fault Mask
emilmont 40:976df7c37ad5 552
emilmont 40:976df7c37ad5 553 This function assigns the given value to the Fault Mask register.
emilmont 40:976df7c37ad5 554
emilmont 40:976df7c37ad5 555 \param [in] faultMask Fault Mask value to set
emilmont 40:976df7c37ad5 556 */
emimon01 46:890817bdcffb 557 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 40:976df7c37ad5 558 {
emilmont 40:976df7c37ad5 559 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
emilmont 40:976df7c37ad5 560 }
emilmont 40:976df7c37ad5 561
emilmont 40:976df7c37ad5 562 #endif /* (__CORTEX_M >= 0x03) */
emilmont 40:976df7c37ad5 563
emilmont 40:976df7c37ad5 564
emilmont 40:976df7c37ad5 565 #if (__CORTEX_M == 0x04)
emilmont 40:976df7c37ad5 566
emilmont 40:976df7c37ad5 567 /** \brief Get FPSCR
emilmont 40:976df7c37ad5 568
emilmont 40:976df7c37ad5 569 This function returns the current value of the Floating Point Status/Control register.
emilmont 40:976df7c37ad5 570
emilmont 40:976df7c37ad5 571 \return Floating Point Status/Control register value
emilmont 40:976df7c37ad5 572 */
emimon01 46:890817bdcffb 573 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
emilmont 40:976df7c37ad5 574 {
emilmont 40:976df7c37ad5 575 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 40:976df7c37ad5 576 uint32_t result;
emilmont 40:976df7c37ad5 577
emilmont 40:976df7c37ad5 578 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
emilmont 40:976df7c37ad5 579 return(result);
emilmont 40:976df7c37ad5 580 #else
emilmont 40:976df7c37ad5 581 return(0);
emilmont 40:976df7c37ad5 582 #endif
emilmont 40:976df7c37ad5 583 }
emilmont 40:976df7c37ad5 584
emilmont 40:976df7c37ad5 585
emilmont 40:976df7c37ad5 586 /** \brief Set FPSCR
emilmont 40:976df7c37ad5 587
emilmont 40:976df7c37ad5 588 This function assigns the given value to the Floating Point Status/Control register.
emilmont 40:976df7c37ad5 589
emilmont 40:976df7c37ad5 590 \param [in] fpscr Floating Point Status/Control value to set
emilmont 40:976df7c37ad5 591 */
emimon01 46:890817bdcffb 592 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 40:976df7c37ad5 593 {
emilmont 40:976df7c37ad5 594 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 40:976df7c37ad5 595 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
emilmont 40:976df7c37ad5 596 #endif
emilmont 40:976df7c37ad5 597 }
emilmont 40:976df7c37ad5 598
emilmont 40:976df7c37ad5 599 #endif /* (__CORTEX_M == 0x04) */
emilmont 40:976df7c37ad5 600
emilmont 40:976df7c37ad5 601
emilmont 40:976df7c37ad5 602 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 40:976df7c37ad5 603 /* TASKING carm specific functions */
emilmont 40:976df7c37ad5 604
emilmont 40:976df7c37ad5 605 /*
emilmont 40:976df7c37ad5 606 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 40:976df7c37ad5 607 * Please use "carm -?i" to get an up to date list of all instrinsics,
emilmont 40:976df7c37ad5 608 * Including the CMSIS ones.
emilmont 40:976df7c37ad5 609 */
emilmont 40:976df7c37ad5 610
emilmont 40:976df7c37ad5 611 #endif
emilmont 40:976df7c37ad5 612
emilmont 40:976df7c37ad5 613 /*@} end of CMSIS_Core_RegAccFunctions */
emilmont 40:976df7c37ad5 614
emilmont 40:976df7c37ad5 615
emilmont 40:976df7c37ad5 616 #endif /* __CORE_CMFUNC_H */