arm_power_q31.c

00001 /* ----------------------------------------------------------------------    
00002 * Copyright (C) 2010-2013 ARM Limited. All rights reserved.    
00003 *    
00004 * $Date:        17. January 2013
00005 * $Revision:    V1.4.1  
00006 *    
00007 * Project:      CMSIS DSP Library    
00008 * Title:        arm_power_q31.c    
00009 *    
00010 * Description:  Sum of the squares of the elements of a Q31 vector.   
00011 *    
00012 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
00013 *  
00014 * Redistribution and use in source and binary forms, with or without 
00015 * modification, are permitted provided that the following conditions
00016 * are met:
00017 *   - Redistributions of source code must retain the above copyright
00018 *     notice, this list of conditions and the following disclaimer.
00019 *   - Redistributions in binary form must reproduce the above copyright
00020 *     notice, this list of conditions and the following disclaimer in
00021 *     the documentation and/or other materials provided with the 
00022 *     distribution.
00023 *   - Neither the name of ARM LIMITED nor the names of its contributors
00024 *     may be used to endorse or promote products derived from this
00025 *     software without specific prior written permission.
00026 *
00027 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
00028 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00029 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00030 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
00031 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00032 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00033 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00034 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
00036 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
00037 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00038 * POSSIBILITY OF SUCH DAMAGE.  
00039 * -------------------------------------------------------------------- */
00040 
00041 #include "arm_math.h"
00042 
00043 /**    
00044  * @ingroup groupStats    
00045  */
00046 
00047 /**    
00048  * @addtogroup power    
00049  * @{    
00050  */
00051 
00052 /**    
00053  * @brief Sum of the squares of the elements of a Q31 vector.    
00054  * @param[in]       *pSrc points to the input vector    
00055  * @param[in]       blockSize length of the input vector    
00056  * @param[out]      *pResult sum of the squares value returned here    
00057  * @return none.    
00058  *    
00059  * @details    
00060  * <b>Scaling and Overflow Behavior:</b>    
00061  *    
00062  * \par    
00063  * The function is implemented using a 64-bit internal accumulator.    
00064  * The input is represented in 1.31 format.    
00065  * Intermediate multiplication yields a 2.62 format, and this    
00066  * result is truncated to 2.48 format by discarding the lower 14 bits.    
00067  * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.    
00068  * With 15 guard bits in the accumulator, there is no risk of overflow, and the    
00069  * full precision of the intermediate multiplication is preserved.    
00070  * Finally, the return result is in 16.48 format.     
00071  *    
00072  */
00073 
00074 void arm_power_q31(
00075   q31_t * pSrc,
00076   uint32_t blockSize,
00077   q63_t * pResult)
00078 {
00079   q63_t sum = 0;                                 /* Temporary result storage */
00080   q31_t in;
00081   uint32_t blkCnt;                               /* loop counter */
00082 
00083 
00084 #ifndef ARM_MATH_CM0_FAMILY
00085 
00086   /* Run the below code for Cortex-M4 and Cortex-M3 */
00087 
00088   /*loop Unrolling */
00089   blkCnt = blockSize >> 2u;
00090 
00091   /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
00092    ** a second loop below computes the remaining 1 to 3 samples. */
00093   while(blkCnt > 0u)
00094   {
00095     /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
00096     /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */
00097     in = *pSrc++;
00098     sum += ((q63_t) in * in) >> 14u;
00099 
00100     in = *pSrc++;
00101     sum += ((q63_t) in * in) >> 14u;
00102 
00103     in = *pSrc++;
00104     sum += ((q63_t) in * in) >> 14u;
00105 
00106     in = *pSrc++;
00107     sum += ((q63_t) in * in) >> 14u;
00108 
00109     /* Decrement the loop counter */
00110     blkCnt--;
00111   }
00112 
00113   /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
00114    ** No loop unrolling is used. */
00115   blkCnt = blockSize % 0x4u;
00116 
00117 #else
00118 
00119   /* Run the below code for Cortex-M0 */
00120 
00121   /* Loop over blockSize number of values */
00122   blkCnt = blockSize;
00123 
00124 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
00125 
00126   while(blkCnt > 0u)
00127   {
00128     /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
00129     /* Compute Power and then store the result in a temporary variable, sum. */
00130     in = *pSrc++;
00131     sum += ((q63_t) in * in) >> 14u;
00132 
00133     /* Decrement the loop counter */
00134     blkCnt--;
00135   }
00136 
00137   /* Store the results in 16.48 format  */
00138   *pResult = sum;
00139 }
00140 
00141 /**    
00142  * @} end of power group    
00143  */