arm_add_q7.c

00001 /* ----------------------------------------------------------------------    
00002 * Copyright (C) 2010-2013 ARM Limited. All rights reserved.    
00003 *    
00004 * $Date:        17. January 2013
00005 * $Revision:    V1.4.1
00006 *    
00007 * Project:      CMSIS DSP Library    
00008 * Title:        arm_add_q7.c    
00009 *    
00010 * Description:  Q7 vector addition.    
00011 *    
00012 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
00013 *  
00014 * Redistribution and use in source and binary forms, with or without 
00015 * modification, are permitted provided that the following conditions
00016 * are met:
00017 *   - Redistributions of source code must retain the above copyright
00018 *     notice, this list of conditions and the following disclaimer.
00019 *   - Redistributions in binary form must reproduce the above copyright
00020 *     notice, this list of conditions and the following disclaimer in
00021 *     the documentation and/or other materials provided with the 
00022 *     distribution.
00023 *   - Neither the name of ARM LIMITED nor the names of its contributors
00024 *     may be used to endorse or promote products derived from this
00025 *     software without specific prior written permission.
00026 *
00027 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
00028 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00029 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00030 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
00031 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00032 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00033 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00034 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
00036 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
00037 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00038 * POSSIBILITY OF SUCH DAMAGE.
00039 * -------------------------------------------------------------------- */
00040 
00041 #include "arm_math.h"
00042 
00043 /**    
00044  * @ingroup groupMath    
00045  */
00046 
00047 /**    
00048  * @addtogroup BasicAdd    
00049  * @{    
00050  */
00051 
00052 /**    
00053  * @brief Q7 vector addition.    
00054  * @param[in]       *pSrcA points to the first input vector    
00055  * @param[in]       *pSrcB points to the second input vector    
00056  * @param[out]      *pDst points to the output vector    
00057  * @param[in]       blockSize number of samples in each vector    
00058  * @return none.    
00059  *    
00060  * <b>Scaling and Overflow Behavior:</b>    
00061  * \par    
00062  * The function uses saturating arithmetic.    
00063  * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.    
00064  */
00065 
00066 void arm_add_q7(
00067   q7_t * pSrcA,
00068   q7_t * pSrcB,
00069   q7_t * pDst,
00070   uint32_t blockSize)
00071 {
00072   uint32_t blkCnt;                               /* loop counter */
00073 
00074 #ifndef ARM_MATH_CM0_FAMILY
00075 
00076 /* Run the below code for Cortex-M4 and Cortex-M3 */
00077 
00078 
00079   /*loop Unrolling */
00080   blkCnt = blockSize >> 2u;
00081 
00082   /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
00083    ** a second loop below computes the remaining 1 to 3 samples. */
00084   while(blkCnt > 0u)
00085   {
00086     /* C = A + B */
00087     /* Add and then store the results in the destination buffer. */
00088     *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
00089 
00090     /* Decrement the loop counter */
00091     blkCnt--;
00092   }
00093 
00094   /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
00095    ** No loop unrolling is used. */
00096   blkCnt = blockSize % 0x4u;
00097 
00098   while(blkCnt > 0u)
00099   {
00100     /* C = A + B */
00101     /* Add and then store the results in the destination buffer. */
00102     *pDst++ = (q7_t) __SSAT(*pSrcA++ + *pSrcB++, 8);
00103 
00104     /* Decrement the loop counter */
00105     blkCnt--;
00106   }
00107 
00108 #else
00109 
00110   /* Run the below code for Cortex-M0 */
00111 
00112 
00113 
00114   /* Initialize blkCnt with number of samples */
00115   blkCnt = blockSize;
00116 
00117   while(blkCnt > 0u)
00118   {
00119     /* C = A + B */
00120     /* Add and then store the results in the destination buffer. */
00121     *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ + *pSrcB++, 8);
00122 
00123     /* Decrement the loop counter */
00124     blkCnt--;
00125   }
00126 
00127 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
00128 
00129 
00130 }
00131 
00132 /**    
00133  * @} end of BasicAdd group    
00134  */