MAX11410.h

00001 #ifndef __MAX11410_H__
00002 #define __MAX11410_H__
00003 
00004 #include "mbed.h"
00005 
00006 //#define DEBUG //if you want to print stuff
00007 
00008 //HW definition
00009 
00010 
00011 #define CONV_DELAY_MS  1
00012 
00013 // SPI interface configuration
00014 #define MAX11410_SPI_MODE 0
00015 
00016 //8 bit registers
00017 #define SPI_READ 1<<7
00018 #define SPI_WRITE 0<<7
00019 #define REG_PD 0x0
00020 #define REG_CONV_START 0x01
00021 #define REG_SEQ_START 0x02
00022 #define REG_CAL_START 0x03
00023 #define REG_GP0_CTRL 0x04
00024 #define REG_GP1_CTRL 0x05
00025 #define REG_GP_CONV 0x06
00026 #define REG_GP_SEQ 0x07
00027 #define REG_FILTER 0x08
00028 #define REG_CTRL 0x09
00029 #define REG_SOURCE 0x0A
00030 #define REG_MUX_CTRL0 0x0B
00031 #define REG_MUX_CTRL1 0x0C
00032 #define REG_MUX_CTRL2 0x0D
00033 #define REG_PGA 0x0E
00034 #define REG_WAIT_EXT 0x0F
00035 #define REG_WAIT_START 0x10
00036 
00037 //24 big registers
00038 #define REG_PART_ID 0x11
00039 #define REG_SYSC_SEL 0x12
00040 #define REG_SYS_OFF_A 0x13
00041 #define REG_SYS_OFF_B 0x14
00042 #define REG_SYS_GAIN_A 0x15
00043 #define REG_SYS_GAIN_B 0x16
00044 #define REG_SELF_OFF 0x17
00045 #define REG_SELF_GAIN_1 0x18
00046 #define REG_SELF_GAIN_2 0x19
00047 #define REG_SELF_GAIN_4 0x1A
00048 #define REG_SELF_GAIN_8 0x1B
00049 #define REG_SELF_GAIN_16 0x1C
00050 #define REG_SELF_GAIN_32 0x1D
00051 #define REG_SELF_GAIN_64 0x1E
00052 #define REG_SELF_GAIN_128 0x1F
00053 #define REG_LTHRESH0 0x20
00054 #define REG_LTHRESH1 0x21
00055 #define REG_LTHRESH2 0x22
00056 #define REG_LTHRESH3 0x23
00057 #define REG_LTHRESH4 0x24
00058 #define REG_LTHRESH5 0x25
00059 #define REG_LTHRESH6 0x26
00060 #define REG_LTHRESH7 0x27
00061 #define REG_UTHRESH0 0x28
00062 #define REG_UTHRESH1 0x29
00063 #define REG_UTHRESH2 0x2A
00064 #define REG_UTHRESH3 0x2B
00065 #define REG_UTHRESH4 0x2C
00066 #define REG_UTHRESH5 0x2D
00067 #define REG_UTHRESH6 0x2E
00068 #define REG_UTHRESH7 0x2F
00069 #define REG_DATA0 0x30
00070 #define REG_DATA1 0x31
00071 #define REG_DATA2 0x32
00072 #define REG_DATA3 0x33
00073 #define REG_DATA4 0x34
00074 #define REG_DATA5 0x35
00075 #define REG_DATA6 0x36
00076 #define REG_DATA7 0x37
00077 #define REG_STATUS 0x38
00078 #define REG_STATUS_IE 0x39
00079 
00080 //16 bit registers for sequencer
00081 #define REG_UC0 0x3A
00082 #define REG_UCADDR 0x6F
00083 
00084 // Read/Write
00085 #define _WRITE(x)  (SPI_WRITE | x)  
00086 #define _READ(x)   (SPI_READ | x)
00087 
00088 //PD bits
00089 #define MODE_NORMAL 0
00090 #define MODE_STANDBY 1 //shut down analog, except LDO
00091 #define MODE_SLEEP 2 //shut down analog including LDO(default)
00092 #define MODE_RESET 3 //POR
00093 
00094 //CONV_START bits
00095 #define _DEST(x) x<<4 //where x = 0:7 is the destination data register
00096 #define SINGLE_CONV 0 //single conversion
00097 #define CONT_CONV 1 //continuous conversions
00098 #define DUTY_CONV 2 //25% duty cycle for lower power consumption
00099  
00100 //CAL_START bits
00101 #define SELF_CAL 0
00102 #define PGA_CAL 1
00103 #define SYS_OFF_A_CAL 4
00104 #define SYS_GAIN_A_CAL 5
00105 #define SYS_OFF_B_CAL 6
00106 #define SYS_GAIN_B_CAL 7
00107 
00108 //GP0_CTRL bits
00109 //GP1_CTRL bits
00110 //GP_CONV bits
00111 //GP_SEQ_ADDR bit
00112 
00113 //FILTER bits
00114 #define FIR_FIFTYSIXTY 0<<4 //default
00115 #define FIR_FIFTY 1<<4
00116 #define FIR_SIXTY 2<<4
00117 #define SINC4 3<<4
00118 
00119 #define _RATE(x) x //where x is 0 to 7
00120 
00121 //CTRL bits
00122 #define EXT_CLOCK 1<<7
00123 #define INT_CLOCK 0<<7 //default
00124 
00125 #define UNIPOLAR 1<<6
00126 #define BIPOLAR 0<<6 //default
00127 
00128 #define TWOS_COMP 0<<5 //default
00129 #define OFFSET_BIN 1<<5
00130 
00131 #define _PBUF_EN(x) x<<4
00132 #define _NBUF_EN(x) x<<3
00133 
00134 #define REF_AIN01 0
00135 #define REF1 1
00136 #define REF2 2
00137 #define REF_AVDD 3
00138 #define REF_UNI_AIN 4
00139 #define REF_UNI_REF1 5
00140 #define REF_UNI_REF2 6
00141 
00142 //SOURCE bits
00143 #define VBIAS_ACTIVE 0<<6 //default
00144 #define VBIAS_HIGH 1<<6
00145 #define VBIAS_LOW 2<<6
00146 
00147 #define BRN_OFF 0<<4 //default
00148 #define BRN_0P5UA 1<<4
00149 #define BRN_1UA 2<<4
00150 #define BRN_10UA 3<<4
00151 
00152 #define _IDAC(x) x //0 defaul, where x is 0x00 to 0x0F 10-1600uA
00153 
00154 //MUX_CTRL0 bits
00155 #define _AINP(x) x<<4 //where x is x0,1,2,3,4,5,6,7,8,9 for ecah of the ten inputs or xA for VDD, xF for disconnnected (default)
00156 #define _AINN(x) x //where x is x0,1,2,3,4,5,6,7,8,9 for ecah of the ten inputs or xA for GND, xF for disconnected (default)
00157 
00158 //MUX_CTRL1 bits
00159 #define _IDAC1(x) x<<4 //where IDAC1 is connect ed to x = x0,1,2,3,4,5,6,7,8,9 for ecah of the ten inputs or xA for VDD, xF for disconnnected (default)
00160 #define _IDAC0(x) x //where IDAC0 is connect ed to x = x0,1,2,3,4,5,6,7,8,9 for ecah of the ten inputs or xA for VDD, xF for disconnnected (default)
00161 
00162 //MUX_CTRL2 bits
00163 #define _VDD_2_INPUT(x) 1<<x
00164 #define _VDD_OFF_INPUT(x) 0<<x
00165 
00166 //PGA bits
00167 #define BUFFER_ON 0<<4 //default
00168 #define BYPASS 1<<4 //no buffer (saves a tiny amount of power)
00169 #define PGA 2<<4 //use progammable gain
00170 
00171 #define _GAIN_EXP(x) x //gain is 2^x (exponent)
00172 
00173 //Status interrupt enbable (REG_STATUS_IE) bits
00174 #define DATA_RDY_INT 0x00000010
00175 #define CAL_RDY_INT  0x00000004
00176 #define CONV_RDY_INT 0x00000001 //default
00177 
00178 //WAIT_EXT
00179 //WAIT_START
00180 
00181 
00182 class MAX11410
00183 {
00184     SPI *spi;
00185     DigitalOut *cs;
00186     
00187     public:
00188         MAX11410(SPI *, DigitalOut *);
00189         void reset();
00190         void write8bitReg(char, char);
00191         void write24bitReg(char, uint32_t);
00192         char read8bits(char regAddr, bool *);
00193         uint32_t read24bits(char regAddr, bool *);
00194         int32_t read24bitsSigned(char regAddr, bool *);
00195         int32_t readInterrupts(bool *);
00196         bool interrupt();
00197         void calOffset();
00198         void calGain();
00199         uint32_t readStatus(bool *); 
00200 
00201 };
00202 
00203 #endif /*__MAX11410_H__*/
00204