micro_ops.h

00001 /* Copyright 2019 The TensorFlow Authors. All Rights Reserved.
00002 
00003 Licensed under the Apache License, Version 2.0 (the "License");
00004 you may not use this file except in compliance with the License.
00005 You may obtain a copy of the License at
00006 
00007     http://www.apache.org/licenses/LICENSE-2.0
00008 
00009 Unless required by applicable law or agreed to in writing, software
00010 distributed under the License is distributed on an "AS IS" BASIS,
00011 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00012 See the License for the specific language governing permissions and
00013 limitations under the License.
00014 ==============================================================================*/
00015 #ifndef TENSORFLOW_LITE_EXPERIMENTAL_MICRO_KERNELS_MICRO_OPS_H_
00016 #define TENSORFLOW_LITE_EXPERIMENTAL_MICRO_KERNELS_MICRO_OPS_H_
00017 
00018 #include "tensorflow/lite/c/c_api_internal.h"
00019 
00020 namespace tflite {
00021 namespace ops {
00022 namespace micro {
00023 
00024 // Forward declaration of all micro op kernel registration methods. These
00025 // registrations are included with the standard `BuiltinOpResolver`.
00026 //
00027 // This header is particularly useful in cases where only a subset of ops are
00028 // needed. In such cases, the client can selectively add only the registrations
00029 // their model requires, using a custom `(Micro)MutableOpResolver`. Selective
00030 // registration in turn allows the linker to strip unused kernels.
00031 
00032 TfLiteRegistration* Register_ABS();
00033 TfLiteRegistration* Register_ADD();
00034 TfLiteRegistration* Register_ARG_MAX();
00035 TfLiteRegistration* Register_ARG_MIN();
00036 TfLiteRegistration* Register_AVERAGE_POOL_2D();
00037 TfLiteRegistration* Register_CEIL();
00038 TfLiteRegistration* Register_CONV_2D();
00039 TfLiteRegistration* Register_COS();
00040 TfLiteRegistration* Register_DEPTHWISE_CONV_2D();
00041 TfLiteRegistration* Register_DEQUANTIZE();
00042 TfLiteRegistration* Register_EQUAL();
00043 TfLiteRegistration* Register_FLOOR();
00044 TfLiteRegistration* Register_FULLY_CONNECTED();
00045 TfLiteRegistration* Register_GREATER();
00046 TfLiteRegistration* Register_GREATER_EQUAL();
00047 TfLiteRegistration* Register_LESS();
00048 TfLiteRegistration* Register_LESS_EQUAL();
00049 TfLiteRegistration* Register_LOG();
00050 TfLiteRegistration* Register_LOGICAL_AND();
00051 TfLiteRegistration* Register_LOGICAL_NOT();
00052 TfLiteRegistration* Register_LOGICAL_OR();
00053 TfLiteRegistration* Register_LOGISTIC();
00054 TfLiteRegistration* Register_MAXIMUM();
00055 TfLiteRegistration* Register_MAX_POOL_2D();
00056 TfLiteRegistration* Register_MINIMUM();
00057 TfLiteRegistration* Register_NEG();
00058 TfLiteRegistration* Register_NOT_EQUAL();
00059 TfLiteRegistration* Register_PACK();
00060 TfLiteRegistration* Register_PRELU();
00061 TfLiteRegistration* Register_QUANTIZE();
00062 TfLiteRegistration* Register_RELU();
00063 TfLiteRegistration* Register_RELU6();
00064 TfLiteRegistration* Register_RESHAPE();
00065 TfLiteRegistration* Register_ROUND();
00066 TfLiteRegistration* Register_RSQRT();
00067 TfLiteRegistration* Register_SIN();
00068 TfLiteRegistration* Register_SOFTMAX();
00069 TfLiteRegistration* Register_SPLIT();
00070 TfLiteRegistration* Register_SQRT();
00071 TfLiteRegistration* Register_SQUARE();
00072 TfLiteRegistration* Register_STRIDED_SLICE();
00073 TfLiteRegistration* Register_SVDF();
00074 TfLiteRegistration* Register_UNPACK();
00075 
00076 }  // namespace micro
00077 }  // namespace ops
00078 }  // namespace tflite
00079 
00080 #endif  // TENSORFLOW_LITE_EXPERIMENTAL_MICRO_KERNELS_MICRO_OPS_H_