detect_platform.h

00001 // Copyright 2018 The Gemmlowp Authors. All Rights Reserved.
00002 //
00003 // Licensed under the Apache License, Version 2.0 (the "License");
00004 // you may not use this file except in compliance with the License.
00005 // You may obtain a copy of the License at
00006 //
00007 //     http://www.apache.org/licenses/LICENSE-2.0
00008 //
00009 // Unless required by applicable law or agreed to in writing, software
00010 // distributed under the License is distributed on an "AS IS" BASIS,
00011 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00012 // See the License for the specific language governing permissions and
00013 // limitations under the License.
00014 
00015 // detect_platform.h: Sets up macros that control architecture-specific
00016 // features of gemmlowp's implementation.
00017 
00018 #ifndef GEMMLOWP_INTERNAL_DETECT_PLATFORM_H_
00019 #define GEMMLOWP_INTERNAL_DETECT_PLATFORM_H_
00020 
00021 // Our inline assembly path assume GCC/Clang syntax.
00022 // Native Client doesn't seem to support inline assembly(?).
00023 #if defined(__GNUC__) && !defined(__native_client__)
00024 #define GEMMLOWP_ALLOW_INLINE_ASM
00025 #endif
00026 
00027 // Define macro statement that avoids inlining for GCC.
00028 // For non-GCC, define as empty macro.
00029 #if defined(__GNUC__)
00030 #define GEMMLOWP_NOINLINE __attribute__((noinline))
00031 #else
00032 #define GEMMLOWP_NOINLINE
00033 #endif
00034 
00035 // Detect ARM, 32-bit or 64-bit
00036 #ifdef __arm__
00037 #define GEMMLOWP_ARM_32
00038 #endif
00039 
00040 #ifdef __aarch64__
00041 #define GEMMLOWP_ARM_64
00042 #endif
00043 
00044 #if defined(GEMMLOWP_ARM_32) || defined(GEMMLOWP_ARM_64)
00045 #define GEMMLOWP_ARM
00046 #endif
00047 
00048 // Detect MIPS, 32-bit or 64-bit
00049 #if defined(__mips) && !defined(__LP64__)
00050 #define GEMMLOWP_MIPS_32
00051 #endif
00052 
00053 #if defined(__mips) && defined(__LP64__)
00054 #define GEMMLOWP_MIPS_64
00055 #endif
00056 
00057 #if defined(GEMMLOWP_MIPS_32) || defined(GEMMLOWP_MIPS_64)
00058 #define GEMMLOWP_MIPS
00059 #endif
00060 
00061 // Detect x86, 32-bit or 64-bit
00062 #if defined(__i386__) || defined(_M_IX86) || defined(_X86_) || defined(__i386)
00063 #define GEMMLOWP_X86_32
00064 #endif
00065 
00066 #if defined(__x86_64__) || defined(_M_X64) || defined(__amd64)
00067 #define GEMMLOWP_X86_64
00068 #endif
00069 
00070 #if defined(GEMMLOWP_X86_32) || defined(GEMMLOWP_X86_64)
00071 #define GEMMLOWP_X86
00072 #endif
00073 
00074 // Some of our optimized paths use inline assembly and for
00075 // now we don't bother enabling some other optimized paths using intrinddics
00076 // where we can't use inline assembly paths.
00077 #ifdef GEMMLOWP_ALLOW_INLINE_ASM
00078 
00079 // Detect NEON. It's important to check for both tokens.
00080 #if (defined __ARM_NEON) || (defined __ARM_NEON__)
00081 #define GEMMLOWP_NEON
00082 #endif
00083 
00084 // Convenience NEON tokens for 32-bit or 64-bit
00085 #if defined(GEMMLOWP_NEON) && defined(GEMMLOWP_ARM_32)
00086 #define GEMMLOWP_NEON_32
00087 #endif
00088 
00089 #if defined(GEMMLOWP_NEON) && defined(GEMMLOWP_ARM_64)
00090 #define GEMMLOWP_NEON_64
00091 #endif
00092 
00093 // Detect MIPS MSA.
00094 // Limit MSA optimizations to little-endian CPUs for now.
00095 // TODO: Perhaps, eventually support MSA optimizations on big-endian CPUs?
00096 #if defined(GEMMLOWP_MIPS) && (__mips_isa_rev >= 5) && defined(__mips_msa) && \
00097     defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)
00098 #define GEMMLOWP_MSA
00099 #endif
00100 
00101 // Convenience MIPS MSA tokens for 32-bit or 64-bit.
00102 #if defined(GEMMLOWP_MSA) && defined(GEMMLOWP_MIPS_32)
00103 #define GEMMLOWP_MSA_32
00104 #endif
00105 
00106 #if defined(GEMMLOWP_MSA) && defined(GEMMLOWP_MIPS_64)
00107 #define GEMMLOWP_MSA_64
00108 #endif
00109 
00110 // compiler define for AVX2 -D GEMMLOWP_ENABLE_AVX2
00111 // Detect AVX2
00112 #if defined(__AVX2__) && defined(GEMMLOWP_ENABLE_AVX2)
00113 #define GEMMLOWP_AVX2
00114 // Detect SSE4.
00115 // MSVC does not have __SSE4_1__ macro, but will enable SSE4
00116 // when AVX is turned on.
00117 #elif defined(__SSE4_1__) || (defined(_MSC_VER) && defined(__AVX__))
00118 #define GEMMLOWP_SSE4
00119 // Detect SSE3.
00120 #elif defined(__SSE3__)
00121 #define GEMMLOWP_SSE3
00122 #endif
00123 
00124 // Convenience SSE4 tokens for 32-bit or 64-bit
00125 #if defined(GEMMLOWP_SSE4) && defined(GEMMLOWP_X86_32) && \
00126     !defined(GEMMLOWP_DISABLE_SSE4)
00127 #define GEMMLOWP_SSE4_32
00128 #endif
00129 
00130 #if defined(GEMMLOWP_SSE3) && defined(GEMMLOWP_X86_32)
00131 #define GEMMLOWP_SSE3_32
00132 #endif
00133 
00134 #if defined(GEMMLOWP_SSE4) && defined(GEMMLOWP_X86_64) && \
00135     !defined(GEMMLOWP_DISABLE_SSE4)
00136 #define GEMMLOWP_SSE4_64
00137 #endif
00138 
00139 #if defined(GEMMLOWP_SSE3) && defined(GEMMLOWP_X86_64)
00140 #define GEMMLOWP_SSE3_64
00141 #endif
00142 
00143 #if defined(GEMMLOWP_AVX2) && defined(GEMMLOWP_X86_64)
00144 #define GEMMLOWP_AVX2_64
00145 #endif
00146 
00147 #if defined(__has_feature)
00148 #if __has_feature(memory_sanitizer)
00149 #include <sanitizer/msan_interface.h>
00150 #define GEMMLOWP_MARK_MEMORY_AS_INITIALIZED __msan_unpoison
00151 #elif __has_feature(address_sanitizer)
00152 #include <sanitizer/asan_interface.h>
00153 #define GEMMLOWP_MARK_MEMORY_AS_INITIALIZED __asan_unpoison_memory_region
00154 #endif
00155 #endif
00156 
00157 #endif  // GEMMLOWP_ALLOW_INLINE_ASM
00158 
00159 // Detect Android. Don't conflate with ARM - we care about tuning
00160 // for non-ARM Android devices too. This can be used in conjunction
00161 // with x86 to tune differently for mobile x86 CPUs (Atom) vs. desktop x86 CPUs.
00162 #if defined(__ANDROID__) || defined(ANDROID)
00163 #define GEMMLOWP_ANDROID
00164 #endif
00165 
00166 #endif  // GEMMLOWP_INTERNAL_DETECT_PLATFORM_H_