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targets/TARGET_Maxim/TARGET_MAX32630/device/i2cs_regs.h@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:
<>
Date:
Thu Feb 02 17:01:33 2017 +0000
Revision:
157:ff67d9f36b67
This updates the lib to the mbed lib v135

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief Registers, Bit Masks and Bit Positions for the I2CS Peripheral Module.
<> 157:ff67d9f36b67 4 */
<> 157:ff67d9f36b67 5 /* ****************************************************************************
<> 157:ff67d9f36b67 6 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 7 *
<> 157:ff67d9f36b67 8 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 9 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 10 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 12 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 13 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 14 *
<> 157:ff67d9f36b67 15 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 16 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 17 *
<> 157:ff67d9f36b67 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 21 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 22 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 24 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 25 *
<> 157:ff67d9f36b67 26 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 27 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 28 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 29 *
<> 157:ff67d9f36b67 30 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 31 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 32 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 33 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 34 * ownership rights.
<> 157:ff67d9f36b67 35 *
<> 157:ff67d9f36b67 36 * $Date: 2016-10-10 18:59:48 -0500 (Mon, 10 Oct 2016) $
<> 157:ff67d9f36b67 37 * $Revision: 24661 $
<> 157:ff67d9f36b67 38 *
<> 157:ff67d9f36b67 39 *************************************************************************** */
<> 157:ff67d9f36b67 40
<> 157:ff67d9f36b67 41 /* Define to prevent redundant inclusion */
<> 157:ff67d9f36b67 42 #ifndef _MXC_I2CS_REGS_H_
<> 157:ff67d9f36b67 43 #define _MXC_I2CS_REGS_H_
<> 157:ff67d9f36b67 44
<> 157:ff67d9f36b67 45 /* **** Includes **** */
<> 157:ff67d9f36b67 46 #include <stdint.h>
<> 157:ff67d9f36b67 47
<> 157:ff67d9f36b67 48 #ifdef __cplusplus
<> 157:ff67d9f36b67 49 extern "C" {
<> 157:ff67d9f36b67 50 #endif
<> 157:ff67d9f36b67 51
<> 157:ff67d9f36b67 52
<> 157:ff67d9f36b67 53 ///@cond
<> 157:ff67d9f36b67 54 /*
<> 157:ff67d9f36b67 55 If types are not defined elsewhere (CMSIS) define them here
<> 157:ff67d9f36b67 56 */
<> 157:ff67d9f36b67 57 #ifndef __IO
<> 157:ff67d9f36b67 58 #define __IO volatile
<> 157:ff67d9f36b67 59 #endif
<> 157:ff67d9f36b67 60 #ifndef __I
<> 157:ff67d9f36b67 61 #define __I volatile const
<> 157:ff67d9f36b67 62 #endif
<> 157:ff67d9f36b67 63 #ifndef __O
<> 157:ff67d9f36b67 64 #define __O volatile
<> 157:ff67d9f36b67 65 #endif
<> 157:ff67d9f36b67 66 #ifndef __RO
<> 157:ff67d9f36b67 67 #define __RO volatile const
<> 157:ff67d9f36b67 68 #endif
<> 157:ff67d9f36b67 69 ///@endcond
<> 157:ff67d9f36b67 70
<> 157:ff67d9f36b67 71 /**
<> 157:ff67d9f36b67 72 * @ingroup i2cs
<> 157:ff67d9f36b67 73 * @defgroup i2cs_registers Registers
<> 157:ff67d9f36b67 74 * @brief Registers, Bit Masks and Bit Positions for the I2CS Peripheral Module.
<> 157:ff67d9f36b67 75 * @{
<> 157:ff67d9f36b67 76 */
<> 157:ff67d9f36b67 77
<> 157:ff67d9f36b67 78 /**
<> 157:ff67d9f36b67 79 * Structure type to access the I2CS Peripheral Module Registers
<> 157:ff67d9f36b67 80 */
<> 157:ff67d9f36b67 81 typedef struct {
<> 157:ff67d9f36b67 82 __IO uint32_t clk_div; /**< <tt>\b 0x0000:</tt> I2CS_CLK_DIV Register - Clock Divisor Control */
<> 157:ff67d9f36b67 83 __IO uint32_t dev_id; /**< <tt>\b 0x0004:</tt> I2CS_DEV_ID Register - Device ID Register */
<> 157:ff67d9f36b67 84 __IO uint32_t intfl; /**< <tt>\b 0x0008:</tt> I2CS_INTFL Register - Interrupt Flags */
<> 157:ff67d9f36b67 85 __IO uint32_t inten; /**< <tt>\b 0x000C:</tt> I2CS_INTEN Register - Interrupt Enable */
<> 157:ff67d9f36b67 86 __IO uint32_t data_byte[32]; /**< <tt>\b 0x0010-0x008C:</tt> I2CS_DATA_BYTE - Data Byte */
<> 157:ff67d9f36b67 87 } mxc_i2cs_regs_t;
<> 157:ff67d9f36b67 88 /**@} end of i2cs_registers */
<> 157:ff67d9f36b67 89
<> 157:ff67d9f36b67 90
<> 157:ff67d9f36b67 91 /*
<> 157:ff67d9f36b67 92 Register offsets for module I2CS.
<> 157:ff67d9f36b67 93 */
<> 157:ff67d9f36b67 94 /**
<> 157:ff67d9f36b67 95 * @ingroup i2cs_registers
<> 157:ff67d9f36b67 96 * @defgroup I2CS_Register_Offsets Register Offsets
<> 157:ff67d9f36b67 97 * @brief I2C Slave Register Offsets from the I2CS Base Peripheral Address.
<> 157:ff67d9f36b67 98 * @{
<> 157:ff67d9f36b67 99 */
<> 157:ff67d9f36b67 100 #define MXC_R_I2CS_OFFS_CLK_DIV ((uint32_t)0x00000000UL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x0000</tt> */
<> 157:ff67d9f36b67 101 #define MXC_R_I2CS_OFFS_DEV_ID ((uint32_t)0x00000004UL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x0004</tt> */
<> 157:ff67d9f36b67 102 #define MXC_R_I2CS_OFFS_INTFL ((uint32_t)0x00000008UL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x0008</tt> */
<> 157:ff67d9f36b67 103 #define MXC_R_I2CS_OFFS_INTEN ((uint32_t)0x0000000CUL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x000C</tt> */
<> 157:ff67d9f36b67 104 #define MXC_R_I2CS_OFFS_DATA_BYTE ((uint32_t)0x00000010UL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x0010-0x008C</tt> */
<> 157:ff67d9f36b67 105 /**@} I2CS_Register_Offsets */
<> 157:ff67d9f36b67 106 /*
<> 157:ff67d9f36b67 107 Field positions and masks for module I2CS.
<> 157:ff67d9f36b67 108 */
<> 157:ff67d9f36b67 109 /**
<> 157:ff67d9f36b67 110 * @ingroup i2cs_registers
<> 157:ff67d9f36b67 111 * @defgroup I2CS_CLK_DIV_Register I2CS_CLK_DIV
<> 157:ff67d9f36b67 112 * @brief Field Positions and Bit Masks for the I2CS_CLK_DIV register
<> 157:ff67d9f36b67 113 * @{
<> 157:ff67d9f36b67 114 */
<> 157:ff67d9f36b67 115 #define MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS 0 /**< FS_FILTER_CLOCK_DIV Position */
<> 157:ff67d9f36b67 116 #define MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS)) /**< FS_FILTER_CLOCK_DIV Mask */
<> 157:ff67d9f36b67 117 /**@} end group I2CS_CLK_DIV */
<> 157:ff67d9f36b67 118 /**
<> 157:ff67d9f36b67 119 * @ingroup i2cs_registers
<> 157:ff67d9f36b67 120 * @defgroup I2CS_DEV_ID_Register I2CS_DEV_ID
<> 157:ff67d9f36b67 121 * @brief Field Positions and Bit Masks for the I2CS_DEV_ID register
<> 157:ff67d9f36b67 122 * @{
<> 157:ff67d9f36b67 123 */
<> 157:ff67d9f36b67 124 #define MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS 0 /**< SLAVE_DEV_ID Position */
<> 157:ff67d9f36b67 125 #define MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID ((uint32_t)(0x000003FFUL << MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS)) /**< SLAVE_DEV_ID Mask */
<> 157:ff67d9f36b67 126 #define MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE_POS 12 /**< TEN_BIT_ID_MODE Position */
<> 157:ff67d9f36b67 127 #define MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE ((uint32_t)(0x00000001UL << MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE_POS)) /**< TEN_BIT_ID_MODE Mask */
<> 157:ff67d9f36b67 128 #define MXC_F_I2CS_DEV_ID_SLAVE_RESET_POS 14 /**< SLAVE_RESET Position */
<> 157:ff67d9f36b67 129 #define MXC_F_I2CS_DEV_ID_SLAVE_RESET ((uint32_t)(0x00000001UL << MXC_F_I2CS_DEV_ID_SLAVE_RESET_POS)) /**< SLAVE_RESET Mask */
<> 157:ff67d9f36b67 130 /**@} end group I2CS_DEV_ID */
<> 157:ff67d9f36b67 131 /**
<> 157:ff67d9f36b67 132 * @ingroup i2cs_registers
<> 157:ff67d9f36b67 133 * @defgroup I2CS_INTFL_Register I2CS_INTFL
<> 157:ff67d9f36b67 134 * @brief Field Positions and Bit Masks for the I2CS_INTFL register
<> 157:ff67d9f36b67 135 * @{
<> 157:ff67d9f36b67 136 */
<> 157:ff67d9f36b67 137 #define MXC_F_I2CS_INTFL_BYTE0_POS 0 /**< BYTE0 Position */
<> 157:ff67d9f36b67 138 #define MXC_F_I2CS_INTFL_BYTE0 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE0_POS)) /**< BYTE0 Mask */
<> 157:ff67d9f36b67 139 #define MXC_F_I2CS_INTFL_BYTE1_POS 1 /**< BYTE1 Position */
<> 157:ff67d9f36b67 140 #define MXC_F_I2CS_INTFL_BYTE1 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE1_POS)) /**< BYTE1 Mask */
<> 157:ff67d9f36b67 141 #define MXC_F_I2CS_INTFL_BYTE2_POS 2 /**< BYTE2 Position */
<> 157:ff67d9f36b67 142 #define MXC_F_I2CS_INTFL_BYTE2 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE2_POS)) /**< BYTE2 Mask */
<> 157:ff67d9f36b67 143 #define MXC_F_I2CS_INTFL_BYTE3_POS 3 /**< BYTE3 Position */
<> 157:ff67d9f36b67 144 #define MXC_F_I2CS_INTFL_BYTE3 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE3_POS)) /**< BYTE3 Mask */
<> 157:ff67d9f36b67 145 #define MXC_F_I2CS_INTFL_BYTE4_POS 4 /**< BYTE4 Position */
<> 157:ff67d9f36b67 146 #define MXC_F_I2CS_INTFL_BYTE4 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE4_POS)) /**< BYTE4 Mask */
<> 157:ff67d9f36b67 147 #define MXC_F_I2CS_INTFL_BYTE5_POS 5 /**< BYTE5 Position */
<> 157:ff67d9f36b67 148 #define MXC_F_I2CS_INTFL_BYTE5 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE5_POS)) /**< BYTE5 Mask */
<> 157:ff67d9f36b67 149 #define MXC_F_I2CS_INTFL_BYTE6_POS 6 /**< BYTE6 Position */
<> 157:ff67d9f36b67 150 #define MXC_F_I2CS_INTFL_BYTE6 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE6_POS)) /**< BYTE6 Mask */
<> 157:ff67d9f36b67 151 #define MXC_F_I2CS_INTFL_BYTE7_POS 7 /**< BYTE7 Position */
<> 157:ff67d9f36b67 152 #define MXC_F_I2CS_INTFL_BYTE7 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE7_POS)) /**< BYTE7 Mask */
<> 157:ff67d9f36b67 153 #define MXC_F_I2CS_INTFL_BYTE8_POS 8 /**< BYTE8 Position */
<> 157:ff67d9f36b67 154 #define MXC_F_I2CS_INTFL_BYTE8 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE8_POS)) /**< BYTE8 Mask */
<> 157:ff67d9f36b67 155 #define MXC_F_I2CS_INTFL_BYTE9_POS 9 /**< BYTE9 Position */
<> 157:ff67d9f36b67 156 #define MXC_F_I2CS_INTFL_BYTE9 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE9_POS)) /**< BYTE9 Mask */
<> 157:ff67d9f36b67 157 #define MXC_F_I2CS_INTFL_BYTE10_POS 10 /**< BYTE10 Position */
<> 157:ff67d9f36b67 158 #define MXC_F_I2CS_INTFL_BYTE10 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE10_POS)) /**< BYTE10 Mask */
<> 157:ff67d9f36b67 159 #define MXC_F_I2CS_INTFL_BYTE11_POS 11 /**< BYTE11 Position */
<> 157:ff67d9f36b67 160 #define MXC_F_I2CS_INTFL_BYTE11 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE11_POS)) /**< BYTE11 Mask */
<> 157:ff67d9f36b67 161 #define MXC_F_I2CS_INTFL_BYTE12_POS 12 /**< BYTE12 Position */
<> 157:ff67d9f36b67 162 #define MXC_F_I2CS_INTFL_BYTE12 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE12_POS)) /**< BYTE12 Mask */
<> 157:ff67d9f36b67 163 #define MXC_F_I2CS_INTFL_BYTE13_POS 13 /**< BYTE13 Position */
<> 157:ff67d9f36b67 164 #define MXC_F_I2CS_INTFL_BYTE13 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE13_POS)) /**< BYTE13 Mask */
<> 157:ff67d9f36b67 165 #define MXC_F_I2CS_INTFL_BYTE14_POS 14 /**< BYTE14 Position */
<> 157:ff67d9f36b67 166 #define MXC_F_I2CS_INTFL_BYTE14 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE14_POS)) /**< BYTE14 Mask */
<> 157:ff67d9f36b67 167 #define MXC_F_I2CS_INTFL_BYTE15_POS 15 /**< BYTE15 Position */
<> 157:ff67d9f36b67 168 #define MXC_F_I2CS_INTFL_BYTE15 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE15_POS)) /**< BYTE15 Mask */
<> 157:ff67d9f36b67 169 #define MXC_F_I2CS_INTFL_BYTE16_POS 16 /**< BYTE16 Position */
<> 157:ff67d9f36b67 170 #define MXC_F_I2CS_INTFL_BYTE16 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE16_POS)) /**< BYTE16 Mask */
<> 157:ff67d9f36b67 171 #define MXC_F_I2CS_INTFL_BYTE17_POS 17 /**< BYTE17 Position */
<> 157:ff67d9f36b67 172 #define MXC_F_I2CS_INTFL_BYTE17 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE17_POS)) /**< BYTE17 Mask */
<> 157:ff67d9f36b67 173 #define MXC_F_I2CS_INTFL_BYTE18_POS 18 /**< BYTE18 Position */
<> 157:ff67d9f36b67 174 #define MXC_F_I2CS_INTFL_BYTE18 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE18_POS)) /**< BYTE18 Mask */
<> 157:ff67d9f36b67 175 #define MXC_F_I2CS_INTFL_BYTE19_POS 19 /**< BYTE19 Position */
<> 157:ff67d9f36b67 176 #define MXC_F_I2CS_INTFL_BYTE19 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE19_POS)) /**< BYTE19 Mask */
<> 157:ff67d9f36b67 177 #define MXC_F_I2CS_INTFL_BYTE20_POS 20 /**< BYTE20 Position */
<> 157:ff67d9f36b67 178 #define MXC_F_I2CS_INTFL_BYTE20 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE20_POS)) /**< BYTE20 Mask */
<> 157:ff67d9f36b67 179 #define MXC_F_I2CS_INTFL_BYTE21_POS 21 /**< BYTE21 Position */
<> 157:ff67d9f36b67 180 #define MXC_F_I2CS_INTFL_BYTE21 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE21_POS)) /**< BYTE21 Mask */
<> 157:ff67d9f36b67 181 #define MXC_F_I2CS_INTFL_BYTE22_POS 22 /**< BYTE22 Position */
<> 157:ff67d9f36b67 182 #define MXC_F_I2CS_INTFL_BYTE22 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE22_POS)) /**< BYTE22 Mask */
<> 157:ff67d9f36b67 183 #define MXC_F_I2CS_INTFL_BYTE23_POS 23 /**< BYTE23 Position */
<> 157:ff67d9f36b67 184 #define MXC_F_I2CS_INTFL_BYTE23 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE23_POS)) /**< BYTE23 Mask */
<> 157:ff67d9f36b67 185 #define MXC_F_I2CS_INTFL_BYTE24_POS 24 /**< BYTE24 Position */
<> 157:ff67d9f36b67 186 #define MXC_F_I2CS_INTFL_BYTE24 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE24_POS)) /**< BYTE24 Mask */
<> 157:ff67d9f36b67 187 #define MXC_F_I2CS_INTFL_BYTE25_POS 25 /**< BYTE25 Position */
<> 157:ff67d9f36b67 188 #define MXC_F_I2CS_INTFL_BYTE25 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE25_POS)) /**< BYTE25 Mask */
<> 157:ff67d9f36b67 189 #define MXC_F_I2CS_INTFL_BYTE26_POS 26 /**< BYTE26 Position */
<> 157:ff67d9f36b67 190 #define MXC_F_I2CS_INTFL_BYTE26 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE26_POS)) /**< BYTE26 Mask */
<> 157:ff67d9f36b67 191 #define MXC_F_I2CS_INTFL_BYTE27_POS 27 /**< BYTE27 Position */
<> 157:ff67d9f36b67 192 #define MXC_F_I2CS_INTFL_BYTE27 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE27_POS)) /**< BYTE27 Mask */
<> 157:ff67d9f36b67 193 #define MXC_F_I2CS_INTFL_BYTE28_POS 28 /**< BYTE28 Position */
<> 157:ff67d9f36b67 194 #define MXC_F_I2CS_INTFL_BYTE28 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE28_POS)) /**< BYTE28 Mask */
<> 157:ff67d9f36b67 195 #define MXC_F_I2CS_INTFL_BYTE29_POS 29 /**< BYTE29 Position */
<> 157:ff67d9f36b67 196 #define MXC_F_I2CS_INTFL_BYTE29 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE29_POS)) /**< BYTE29 Mask */
<> 157:ff67d9f36b67 197 #define MXC_F_I2CS_INTFL_BYTE30_POS 30 /**< BYTE30 Position */
<> 157:ff67d9f36b67 198 #define MXC_F_I2CS_INTFL_BYTE30 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE30_POS)) /**< BYTE30 Mask */
<> 157:ff67d9f36b67 199 #define MXC_F_I2CS_INTFL_BYTE31_POS 31 /**< BYTE31 Position */
<> 157:ff67d9f36b67 200 #define MXC_F_I2CS_INTFL_BYTE31 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE31_POS)) /**< BYTE31 Mask */
<> 157:ff67d9f36b67 201 /**@} end group I2CS_INTFL */
<> 157:ff67d9f36b67 202 /**
<> 157:ff67d9f36b67 203 * @ingroup i2cs_registers
<> 157:ff67d9f36b67 204 * @defgroup I2CS_INTEN_Register I2CS_INTEN
<> 157:ff67d9f36b67 205 * @brief Field Positions and Bit Masks for the I2CS_INTEN register
<> 157:ff67d9f36b67 206 * @{
<> 157:ff67d9f36b67 207 */
<> 157:ff67d9f36b67 208 #define MXC_F_I2CS_INTEN_BYTE0_POS 0 /**< BYTE0 Position */
<> 157:ff67d9f36b67 209 #define MXC_F_I2CS_INTEN_BYTE0 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE0_POS)) /**< BYTE0 Mask */
<> 157:ff67d9f36b67 210 #define MXC_F_I2CS_INTEN_BYTE1_POS 1 /**< BYTE1 Position */
<> 157:ff67d9f36b67 211 #define MXC_F_I2CS_INTEN_BYTE1 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE1_POS)) /**< BYTE1 Mask */
<> 157:ff67d9f36b67 212 #define MXC_F_I2CS_INTEN_BYTE2_POS 2 /**< BYTE2 Position */
<> 157:ff67d9f36b67 213 #define MXC_F_I2CS_INTEN_BYTE2 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE2_POS)) /**< BYTE2 Mask */
<> 157:ff67d9f36b67 214 #define MXC_F_I2CS_INTEN_BYTE3_POS 3 /**< BYTE3 Position */
<> 157:ff67d9f36b67 215 #define MXC_F_I2CS_INTEN_BYTE3 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE3_POS)) /**< BYTE3 Mask */
<> 157:ff67d9f36b67 216 #define MXC_F_I2CS_INTEN_BYTE4_POS 4 /**< BYTE4 Position */
<> 157:ff67d9f36b67 217 #define MXC_F_I2CS_INTEN_BYTE4 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE4_POS)) /**< BYTE4 Mask */
<> 157:ff67d9f36b67 218 #define MXC_F_I2CS_INTEN_BYTE5_POS 5 /**< BYTE5 Position */
<> 157:ff67d9f36b67 219 #define MXC_F_I2CS_INTEN_BYTE5 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE5_POS)) /**< BYTE5 Mask */
<> 157:ff67d9f36b67 220 #define MXC_F_I2CS_INTEN_BYTE6_POS 6 /**< BYTE6 Position */
<> 157:ff67d9f36b67 221 #define MXC_F_I2CS_INTEN_BYTE6 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE6_POS)) /**< BYTE6 Mask */
<> 157:ff67d9f36b67 222 #define MXC_F_I2CS_INTEN_BYTE7_POS 7 /**< BYTE7 Position */
<> 157:ff67d9f36b67 223 #define MXC_F_I2CS_INTEN_BYTE7 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE7_POS)) /**< BYTE7 Mask */
<> 157:ff67d9f36b67 224 #define MXC_F_I2CS_INTEN_BYTE8_POS 8 /**< BYTE8 Position */
<> 157:ff67d9f36b67 225 #define MXC_F_I2CS_INTEN_BYTE8 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE8_POS)) /**< BYTE8 Mask */
<> 157:ff67d9f36b67 226 #define MXC_F_I2CS_INTEN_BYTE9_POS 9 /**< BYTE9 Position */
<> 157:ff67d9f36b67 227 #define MXC_F_I2CS_INTEN_BYTE9 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE9_POS)) /**< BYTE9 Mask */
<> 157:ff67d9f36b67 228 #define MXC_F_I2CS_INTEN_BYTE10_POS 10 /**< BYTE10 Position */
<> 157:ff67d9f36b67 229 #define MXC_F_I2CS_INTEN_BYTE10 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE10_POS)) /**< BYTE10 Mask */
<> 157:ff67d9f36b67 230 #define MXC_F_I2CS_INTEN_BYTE11_POS 11 /**< BYTE11 Position */
<> 157:ff67d9f36b67 231 #define MXC_F_I2CS_INTEN_BYTE11 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE11_POS)) /**< BYTE11 Mask */
<> 157:ff67d9f36b67 232 #define MXC_F_I2CS_INTEN_BYTE12_POS 12 /**< BYTE12 Position */
<> 157:ff67d9f36b67 233 #define MXC_F_I2CS_INTEN_BYTE12 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE12_POS)) /**< BYTE12 Mask */
<> 157:ff67d9f36b67 234 #define MXC_F_I2CS_INTEN_BYTE13_POS 13 /**< BYTE13 Position */
<> 157:ff67d9f36b67 235 #define MXC_F_I2CS_INTEN_BYTE13 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE13_POS)) /**< BYTE13 Mask */
<> 157:ff67d9f36b67 236 #define MXC_F_I2CS_INTEN_BYTE14_POS 14 /**< BYTE14 Position */
<> 157:ff67d9f36b67 237 #define MXC_F_I2CS_INTEN_BYTE14 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE14_POS)) /**< BYTE14 Mask */
<> 157:ff67d9f36b67 238 #define MXC_F_I2CS_INTEN_BYTE15_POS 15 /**< BYTE15 Position */
<> 157:ff67d9f36b67 239 #define MXC_F_I2CS_INTEN_BYTE15 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE15_POS)) /**< BYTE15 Mask */
<> 157:ff67d9f36b67 240 #define MXC_F_I2CS_INTEN_BYTE16_POS 16 /**< BYTE16 Position */
<> 157:ff67d9f36b67 241 #define MXC_F_I2CS_INTEN_BYTE16 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE16_POS)) /**< BYTE16 Mask */
<> 157:ff67d9f36b67 242 #define MXC_F_I2CS_INTEN_BYTE17_POS 17 /**< BYTE17 Position */
<> 157:ff67d9f36b67 243 #define MXC_F_I2CS_INTEN_BYTE17 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE17_POS)) /**< BYTE17 Mask */
<> 157:ff67d9f36b67 244 #define MXC_F_I2CS_INTEN_BYTE18_POS 18 /**< BYTE18 Position */
<> 157:ff67d9f36b67 245 #define MXC_F_I2CS_INTEN_BYTE18 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE18_POS)) /**< BYTE18 Mask */
<> 157:ff67d9f36b67 246 #define MXC_F_I2CS_INTEN_BYTE19_POS 19 /**< BYTE19 Position */
<> 157:ff67d9f36b67 247 #define MXC_F_I2CS_INTEN_BYTE19 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE19_POS)) /**< BYTE19 Mask */
<> 157:ff67d9f36b67 248 #define MXC_F_I2CS_INTEN_BYTE20_POS 20 /**< BYTE20 Position */
<> 157:ff67d9f36b67 249 #define MXC_F_I2CS_INTEN_BYTE20 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE20_POS)) /**< BYTE20 Mask */
<> 157:ff67d9f36b67 250 #define MXC_F_I2CS_INTEN_BYTE21_POS 21 /**< BYTE21 Position */
<> 157:ff67d9f36b67 251 #define MXC_F_I2CS_INTEN_BYTE21 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE21_POS)) /**< BYTE21 Mask */
<> 157:ff67d9f36b67 252 #define MXC_F_I2CS_INTEN_BYTE22_POS 22 /**< BYTE22 Position */
<> 157:ff67d9f36b67 253 #define MXC_F_I2CS_INTEN_BYTE22 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE22_POS)) /**< BYTE22 Mask */
<> 157:ff67d9f36b67 254 #define MXC_F_I2CS_INTEN_BYTE23_POS 23 /**< BYTE23 Position */
<> 157:ff67d9f36b67 255 #define MXC_F_I2CS_INTEN_BYTE23 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE23_POS)) /**< BYTE23 Mask */
<> 157:ff67d9f36b67 256 #define MXC_F_I2CS_INTEN_BYTE24_POS 24 /**< BYTE24 Position */
<> 157:ff67d9f36b67 257 #define MXC_F_I2CS_INTEN_BYTE24 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE24_POS)) /**< BYTE24 Mask */
<> 157:ff67d9f36b67 258 #define MXC_F_I2CS_INTEN_BYTE25_POS 25 /**< BYTE25 Position */
<> 157:ff67d9f36b67 259 #define MXC_F_I2CS_INTEN_BYTE25 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE25_POS)) /**< BYTE25 Mask */
<> 157:ff67d9f36b67 260 #define MXC_F_I2CS_INTEN_BYTE26_POS 26 /**< BYTE26 Position */
<> 157:ff67d9f36b67 261 #define MXC_F_I2CS_INTEN_BYTE26 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE26_POS)) /**< BYTE26 Mask */
<> 157:ff67d9f36b67 262 #define MXC_F_I2CS_INTEN_BYTE27_POS 27 /**< BYTE27 Position */
<> 157:ff67d9f36b67 263 #define MXC_F_I2CS_INTEN_BYTE27 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE27_POS)) /**< BYTE27 Mask */
<> 157:ff67d9f36b67 264 #define MXC_F_I2CS_INTEN_BYTE28_POS 28 /**< BYTE28 Position */
<> 157:ff67d9f36b67 265 #define MXC_F_I2CS_INTEN_BYTE28 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE28_POS)) /**< BYTE28 Mask */
<> 157:ff67d9f36b67 266 #define MXC_F_I2CS_INTEN_BYTE29_POS 29 /**< BYTE29 Position */
<> 157:ff67d9f36b67 267 #define MXC_F_I2CS_INTEN_BYTE29 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE29_POS)) /**< BYTE29 Mask */
<> 157:ff67d9f36b67 268 #define MXC_F_I2CS_INTEN_BYTE30_POS 30 /**< BYTE30 Position */
<> 157:ff67d9f36b67 269 #define MXC_F_I2CS_INTEN_BYTE30 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE30_POS)) /**< BYTE30 Mask */
<> 157:ff67d9f36b67 270 #define MXC_F_I2CS_INTEN_BYTE31_POS 31 /**< BYTE31 Position */
<> 157:ff67d9f36b67 271 #define MXC_F_I2CS_INTEN_BYTE31 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE31_POS)) /**< BYTE31 Mask */
<> 157:ff67d9f36b67 272 /**@} end group I2CS_INTEN */
<> 157:ff67d9f36b67 273 /**
<> 157:ff67d9f36b67 274 * @ingroup i2cs_registers
<> 157:ff67d9f36b67 275 * @defgroup I2CS_DATA_BYTE_Register I2CS_DATA_BYTE
<> 157:ff67d9f36b67 276 * @brief Field Positions and Bit Masks for the I2CS_DATA_BYTE register
<> 157:ff67d9f36b67 277 * @{
<> 157:ff67d9f36b67 278 */
<> 157:ff67d9f36b67 279 #define MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS 0 /**< DATA_FIELD Position */
<> 157:ff67d9f36b67 280 #define MXC_F_I2CS_DATA_BYTE_DATA_FIELD ((uint32_t)(0x000000FFUL << MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS)) /**< DATA_FIELD */
<> 157:ff67d9f36b67 281 #define MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL_POS 8 /**< READ_ONLY_FL Position */
<> 157:ff67d9f36b67 282 #define MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL ((uint32_t)(0x00000001UL << MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL_POS)) /**< READ_ONLY_FL */
<> 157:ff67d9f36b67 283 #define MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL_POS 9 /**< DATA_UPDATED_FL Position */
<> 157:ff67d9f36b67 284 #define MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL ((uint32_t)(0x00000001UL << MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL_POS)) /**< DATA_UPDATED_FL */
<> 157:ff67d9f36b67 285 /**@} end group I2CS_DATA_BYTE */
<> 157:ff67d9f36b67 286
<> 157:ff67d9f36b67 287 #ifdef __cplusplus
<> 157:ff67d9f36b67 288 }
<> 157:ff67d9f36b67 289 #endif
<> 157:ff67d9f36b67 290
<> 157:ff67d9f36b67 291 #endif /* _MXC_I2CS_REGS_H_ */