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targets/TARGET_Maxim/TARGET_MAX32630/device/flc_regs.h@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:
<>
Date:
Thu Feb 02 17:01:33 2017 +0000
Revision:
157:ff67d9f36b67
This updates the lib to the mbed lib v135

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief registers, bit masks and bit positions for the Flash
<> 157:ff67d9f36b67 4 * Controller (FLC) peripheral module.
<> 157:ff67d9f36b67 5 */
<> 157:ff67d9f36b67 6
<> 157:ff67d9f36b67 7 /* ****************************************************************************
<> 157:ff67d9f36b67 8 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 9 *
<> 157:ff67d9f36b67 10 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 11 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 12 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 13 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 14 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 15 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 16 *
<> 157:ff67d9f36b67 17 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 18 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 19 *
<> 157:ff67d9f36b67 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 23 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 24 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 26 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 27 *
<> 157:ff67d9f36b67 28 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 29 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 30 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 31 *
<> 157:ff67d9f36b67 32 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 33 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 34 * trademarks, Maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 35 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 36 * ownership rights.
<> 157:ff67d9f36b67 37 *
<> 157:ff67d9f36b67 38 * $Date: 2016-10-10 18:54:04 -0500 (Mon, 10 Oct 2016) $
<> 157:ff67d9f36b67 39 * $Revision: 24658 $
<> 157:ff67d9f36b67 40 *
<> 157:ff67d9f36b67 41 *************************************************************************** */
<> 157:ff67d9f36b67 42
<> 157:ff67d9f36b67 43 /* Define to prevent redundant inclusion */
<> 157:ff67d9f36b67 44 #ifndef _MXC_FLC_REGS_H_
<> 157:ff67d9f36b67 45 #define _MXC_FLC_REGS_H_
<> 157:ff67d9f36b67 46
<> 157:ff67d9f36b67 47 /* **** Includes **** */
<> 157:ff67d9f36b67 48 #include <stdint.h>
<> 157:ff67d9f36b67 49
<> 157:ff67d9f36b67 50 #ifdef __cplusplus
<> 157:ff67d9f36b67 51 extern "C" {
<> 157:ff67d9f36b67 52 #endif
<> 157:ff67d9f36b67 53
<> 157:ff67d9f36b67 54 /// @cond
<> 157:ff67d9f36b67 55 /*
<> 157:ff67d9f36b67 56 If types are not defined elsewhere (CMSIS) define them here
<> 157:ff67d9f36b67 57 */
<> 157:ff67d9f36b67 58 #ifndef __IO
<> 157:ff67d9f36b67 59 #define __IO volatile
<> 157:ff67d9f36b67 60 #endif
<> 157:ff67d9f36b67 61 #ifndef __I
<> 157:ff67d9f36b67 62 #define __I volatile const
<> 157:ff67d9f36b67 63 #endif
<> 157:ff67d9f36b67 64 #ifndef __O
<> 157:ff67d9f36b67 65 #define __O volatile
<> 157:ff67d9f36b67 66 #endif
<> 157:ff67d9f36b67 67 #ifndef __RO
<> 157:ff67d9f36b67 68 #define __RO volatile const
<> 157:ff67d9f36b67 69 #endif
<> 157:ff67d9f36b67 70 /// @endcond
<> 157:ff67d9f36b67 71 /**
<> 157:ff67d9f36b67 72 * @ingroup flc
<> 157:ff67d9f36b67 73 * @defgroup flc_registers Registers
<> 157:ff67d9f36b67 74 * @brief Registers, Bit Masks, Bit Positions and Values for the FLC Peripheral Module.
<> 157:ff67d9f36b67 75 */
<> 157:ff67d9f36b67 76 /* **** Definitions **** */
<> 157:ff67d9f36b67 77 /**
<> 157:ff67d9f36b67 78 * @ingroup flc_registers
<> 157:ff67d9f36b67 79 * @defgroup flc_special_codes Flash Controller Codes/Keys.
<> 157:ff67d9f36b67 80 * @brief Required values to pass to the flash controller to perform restricted
<> 157:ff67d9f36b67 81 * operations.
<> 157:ff67d9f36b67 82 * @{
<> 157:ff67d9f36b67 83 */
<> 157:ff67d9f36b67 84 #define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55) /**< Page Erase Code required to perform a page erase operation */
<> 157:ff67d9f36b67 85 #define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA) /**< Mass Erase Code required to perform a page erase operation */
<> 157:ff67d9f36b67 86 #define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2) /**< Unlock Code required to unlock the flash for erase and write functions */
<> 157:ff67d9f36b67 87 /**@} end of flc_special_codes */
<> 157:ff67d9f36b67 88
<> 157:ff67d9f36b67 89
<> 157:ff67d9f36b67 90 /*
<> 157:ff67d9f36b67 91 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 157:ff67d9f36b67 92 access to each register in module.
<> 157:ff67d9f36b67 93 */
<> 157:ff67d9f36b67 94
<> 157:ff67d9f36b67 95 /**
<> 157:ff67d9f36b67 96 * @ingroup flc_registers
<> 157:ff67d9f36b67 97 * @brief Structure type to access the Flash Controller registers with
<> 157:ff67d9f36b67 98 * direct 32-bit access to each.
<> 157:ff67d9f36b67 99 */
<> 157:ff67d9f36b67 100 typedef struct {
<> 157:ff67d9f36b67 101 __IO uint32_t faddr; /**< <tt>\b 0x0000: </tt> FLC_FADDR Register - Flash Operation Address */
<> 157:ff67d9f36b67 102 __IO uint32_t fckdiv; /**< <tt>\b 0x0004: </tt> FLC_FCKDIV Register - Flash Clock Pulse Divisor */
<> 157:ff67d9f36b67 103 __IO uint32_t ctrl; /**< <tt>\b 0x0008: </tt> FLC_CTRL Register - Flash Control Register */
<> 157:ff67d9f36b67 104 __RO uint32_t rsv00C[6]; /**< <tt>\b 0x000C-0x0020:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
<> 157:ff67d9f36b67 105 __IO uint32_t intr; /**< <tt>\b 0x0024: </tt> FLC_INTR Register - Flash Controller Interrupt Flags and Enable/Disable 0 */
<> 157:ff67d9f36b67 106 __RO uint32_t rsv028[2]; /**< <tt>\b 0x0028-0x002C:</tt> RESERVED */
<> 157:ff67d9f36b67 107 __IO uint32_t fdata; /**< <tt>\b 0x0030: </tt> FLC_FDATA Register - Flash Operation Data Register */
<> 157:ff67d9f36b67 108 __RO uint32_t rsv034[7]; /**< <tt>\b 0x0034-0x004C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
<> 157:ff67d9f36b67 109 __IO uint32_t perform; /**< <tt>\b 0x0050: </tt> FLC_PERFORM Register - Flash Performance Settings */
<> 157:ff67d9f36b67 110 __IO uint32_t tacc; /**< <tt>\b 0x0054: </tt> FLC_TACC Register - Flash Read Cycle Config */
<> 157:ff67d9f36b67 111 __IO uint32_t tprog; /**< <tt>\b 0x0058: </tt> FLC_TPROG Register - Flash Write Cycle Config */
<> 157:ff67d9f36b67 112 __RO uint32_t rsv05C[9]; /**< <tt>\b 0x005C-0x007C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
<> 157:ff67d9f36b67 113 __IO uint32_t status; /**< <tt>\b 0x0080: </tt> FLC_STATUS Register - Security Status Flags */
<> 157:ff67d9f36b67 114 __RO uint32_t rsv084; /**< <tt>\b 0x0084: </tt> RESERVED \warning Do Not Modify Reserved Locations! */
<> 157:ff67d9f36b67 115 __IO uint32_t security; /**< <tt>\b 0x0088: </tt> FLC_SECURITY Register - Flash Controller Security Settings */
<> 157:ff67d9f36b67 116 __RO uint32_t rsv08C[4]; /**< <tt>\b 0x008C-0x0098:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
<> 157:ff67d9f36b67 117 __IO uint32_t bypass; /**< <tt>\b 0x009C: </tt> FLC_BYPASS Register - Status Flags for DSB Operations */
<> 157:ff67d9f36b67 118 __RO uint32_t rsv0A0[24]; /**< <tt>\b 0x00A0-0x00FC:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
<> 157:ff67d9f36b67 119 __IO uint32_t user_option; /**< <tt>\b 0x0100: </tt> FLC_USER_OPTION Register - Used to set DSB Access code and Auto-Lock in info block */
<> 157:ff67d9f36b67 120 __RO uint32_t rsv104[15]; /**< <tt>\b 0x0104-0x013C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
<> 157:ff67d9f36b67 121 __IO uint32_t ctrl2; /**< <tt>\b 0x0140: </tt> FLC_CTRL2 Register - Flash Control Register 2 */
<> 157:ff67d9f36b67 122 __IO uint32_t intfl1; /**< <tt>\b 0x0144: </tt> FLC_INTFL1 Register - Interrupt Flags Register 1 */
<> 157:ff67d9f36b67 123 __IO uint32_t inten1; /**< <tt>\b 0x0148: </tt> FLC_INTEN1 Register - Interrupt Enable/Disable Register 1 */
<> 157:ff67d9f36b67 124 __RO uint32_t rsv14C[9]; /**< <tt>\b 0x014C-0x016C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
<> 157:ff67d9f36b67 125 __IO uint32_t bl_ctrl; /**< <tt>\b 0x0170: </tt> FLC_BL_CTRL Register - Bootloader Control Register */
<> 157:ff67d9f36b67 126 __IO uint32_t twk; /**< <tt>\b 0x0174: </tt> FLC_TWK Register - PDM33 Register */
<> 157:ff67d9f36b67 127 __RO uint32_t rsv178; /**< <tt>\b 0x0178: </tt> RESERVED \warning Do Not Modify Reserved Locations! */
<> 157:ff67d9f36b67 128 __IO uint32_t slm; /**< <tt>\b 0x017C: </tt> FLC_SLM Register - Sleep Mode Register */
<> 157:ff67d9f36b67 129 __RO uint32_t rsv180[32]; /**< <tt>\b 0x0180-0x01FC:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
<> 157:ff67d9f36b67 130 __IO uint32_t disable_xr0; /**< <tt>\b 0x0200: </tt> FLC_DISABLE_XR0 Register - Disable Flash Page Exec/Read Register 0 */
<> 157:ff67d9f36b67 131 __IO uint32_t disable_xr1; /**< <tt>\b 0x0204: </tt> FLC_DISABLE_XR1 Register - Disable Flash Page Exec/Read Register 1 */
<> 157:ff67d9f36b67 132 __IO uint32_t disable_xr2; /**< <tt>\b 0x0208: </tt> FLC_DISABLE_XR2 Register - Disable Flash Page Exec/Read Register 2 */
<> 157:ff67d9f36b67 133 __IO uint32_t disable_xr3; /**< <tt>\b 0x020C: </tt> FLC_DISABLE_XR3 Register - Disable Flash Page Exec/Read Register 3 */
<> 157:ff67d9f36b67 134 __IO uint32_t disable_xr4; /**< <tt>\b 0x0210: </tt> FLC_DISABLE_XR4 Register - Disable Flash Page Exec/Read Register 4 */
<> 157:ff67d9f36b67 135 __IO uint32_t disable_xr5; /**< <tt>\b 0x0214: </tt> FLC_DISABLE_XR5 Register - Disable Flash Page Exec/Read Register 5 */
<> 157:ff67d9f36b67 136 __IO uint32_t disable_xr6; /**< <tt>\b 0x0218: </tt> FLC_DISABLE_XR6 Register - Disable Flash Page Exec/Read Register 6 */
<> 157:ff67d9f36b67 137 __IO uint32_t disable_xr7; /**< <tt>\b 0x021C: </tt> FLC_DISABLE_XR7 Register - Disable Flash Page Exec/Read Register 7 */
<> 157:ff67d9f36b67 138 __RO uint32_t rsv220[56]; /**< <tt>\b 0x0220-0x02FC:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
<> 157:ff67d9f36b67 139 __IO uint32_t disable_we0; /**< <tt>\b 0x0300: </tt> FLC_DISABLE_WE0 Register - Disable Flash Page Write/Erase Register 0 */
<> 157:ff67d9f36b67 140 __IO uint32_t disable_we1; /**< <tt>\b 0x0304: </tt> FLC_DISABLE_WE1 Register - Disable Flash Page Write/Erase Register 1 */
<> 157:ff67d9f36b67 141 __IO uint32_t disable_we2; /**< <tt>\b 0x0308: </tt> FLC_DISABLE_WE2 Register - Disable Flash Page Write/Erase Register 2 */
<> 157:ff67d9f36b67 142 __IO uint32_t disable_we3; /**< <tt>\b 0x030C: </tt> FLC_DISABLE_WE3 Register - Disable Flash Page Write/Erase Register 3 */
<> 157:ff67d9f36b67 143 __IO uint32_t disable_we4; /**< <tt>\b 0x0310: </tt> FLC_DISABLE_WE4 Register - Disable Flash Page Write/Erase Register 4 */
<> 157:ff67d9f36b67 144 __IO uint32_t disable_we5; /**< <tt>\b 0x0314: </tt> FLC_DISABLE_WE5 Register - Disable Flash Page Write/Erase Register 5 */
<> 157:ff67d9f36b67 145 __IO uint32_t disable_we6; /**< <tt>\b 0x0318: </tt> FLC_DISABLE_WE6 Register - Disable Flash Page Write/Erase Register 6 */
<> 157:ff67d9f36b67 146 __IO uint32_t disable_we7; /**< <tt>\b 0x031C: </tt> FLC_DISABLE_WE7 Register - Disable Flash Page Write/Erase Register 7 */
<> 157:ff67d9f36b67 147 } mxc_flc_regs_t;
<> 157:ff67d9f36b67 148 /*
<> 157:ff67d9f36b67 149 Register offsets for module FLC.
<> 157:ff67d9f36b67 150 */
<> 157:ff67d9f36b67 151
<> 157:ff67d9f36b67 152 /**
<> 157:ff67d9f36b67 153 * @ingroup flc_registers
<> 157:ff67d9f36b67 154 * @defgroup FLC_Register_Offsets Register Offsets
<> 157:ff67d9f36b67 155 * @brief Flash Controller Register Offsets from the FLC Base Peripheral Address.
<> 157:ff67d9f36b67 156 * @{
<> 157:ff67d9f36b67 157 */
<> 157:ff67d9f36b67 158 #define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt>\b 0x0000</tt> */
<> 157:ff67d9f36b67 159 #define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt>\b 0x0004</tt> */
<> 157:ff67d9f36b67 160 #define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt>\b 0x0008</tt> */
<> 157:ff67d9f36b67 161 #define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt>\b 0x0024</tt> */
<> 157:ff67d9f36b67 162 #define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt>\b 0x0030</tt> */
<> 157:ff67d9f36b67 163 #define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL) /**< Offset from FLC Base Address: <tt>\b 0x0050</tt> */
<> 157:ff67d9f36b67 164 #define MXC_R_FLC_OFFS_TACC ((uint32_t)0x00000054UL) /**< Offset from FLC Base Address: <tt>\b 0x0054</tt> */
<> 157:ff67d9f36b67 165 #define MXC_R_FLC_OFFS_TPROG ((uint32_t)0x00000058UL) /**< Offset from FLC Base Address: <tt>\b 0x0058</tt> */
<> 157:ff67d9f36b67 166 #define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL) /**< Offset from FLC Base Address: <tt>\b 0x0080</tt> */
<> 157:ff67d9f36b67 167 #define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL) /**< Offset from FLC Base Address: <tt>\b 0x0088</tt> */
<> 157:ff67d9f36b67 168 #define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL) /**< Offset from FLC Base Address: <tt>\b 0x009C</tt> */
<> 157:ff67d9f36b67 169 #define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL) /**< Offset from FLC Base Address: <tt>\b 0x0100</tt> */
<> 157:ff67d9f36b67 170 #define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL) /**< Offset from FLC Base Address: <tt>\b 0x0140</tt> */
<> 157:ff67d9f36b67 171 #define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL) /**< Offset from FLC Base Address: <tt>\b 0x0144</tt> */
<> 157:ff67d9f36b67 172 #define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL) /**< Offset from FLC Base Address: <tt>\b 0x0148</tt> */
<> 157:ff67d9f36b67 173 #define MXC_R_FLC_OFFS_BL_CTRL ((uint32_t)0x00000170UL) /**< Offset from FLC Base Address: <tt>\b 0x0170</tt> */
<> 157:ff67d9f36b67 174 #define MXC_R_FLC_OFFS_TWK ((uint32_t)0x00000174UL) /**< Offset from FLC Base Address: <tt>\b 0x0174</tt> */
<> 157:ff67d9f36b67 175 #define MXC_R_FLC_OFFS_SLM ((uint32_t)0x0000017CUL) /**< Offset from FLC Base Address: <tt>\b 0x017C</tt> */
<> 157:ff67d9f36b67 176 #define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000200UL) /**< Offset from FLC Base Address: <tt>\b 0x0200</tt> */
<> 157:ff67d9f36b67 177 #define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000204UL) /**< Offset from FLC Base Address: <tt>\b 0x0204</tt> */
<> 157:ff67d9f36b67 178 #define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000208UL) /**< Offset from FLC Base Address: <tt>\b 0x0208</tt> */
<> 157:ff67d9f36b67 179 #define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000020CUL) /**< Offset from FLC Base Address: <tt>\b 0x020C</tt> */
<> 157:ff67d9f36b67 180 #define MXC_R_FLC_OFFS_DISABLE_XR4 ((uint32_t)0x00000210UL) /**< Offset from FLC Base Address: <tt>\b 0x0210</tt> */
<> 157:ff67d9f36b67 181 #define MXC_R_FLC_OFFS_DISABLE_XR5 ((uint32_t)0x00000214UL) /**< Offset from FLC Base Address: <tt>\b 0x0214</tt> */
<> 157:ff67d9f36b67 182 #define MXC_R_FLC_OFFS_DISABLE_XR6 ((uint32_t)0x00000218UL) /**< Offset from FLC Base Address: <tt>\b 0x0218</tt> */
<> 157:ff67d9f36b67 183 #define MXC_R_FLC_OFFS_DISABLE_XR7 ((uint32_t)0x0000021CUL) /**< Offset from FLC Base Address: <tt>\b 0x021C</tt> */
<> 157:ff67d9f36b67 184 #define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000300UL) /**< Offset from FLC Base Address: <tt>\b 0x0300</tt> */
<> 157:ff67d9f36b67 185 #define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000304UL) /**< Offset from FLC Base Address: <tt>\b 0x0304</tt> */
<> 157:ff67d9f36b67 186 #define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000308UL) /**< Offset from FLC Base Address: <tt>\b 0x0308</tt> */
<> 157:ff67d9f36b67 187 #define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000030CUL) /**< Offset from FLC Base Address: <tt>\b 0x030C</tt> */
<> 157:ff67d9f36b67 188 #define MXC_R_FLC_OFFS_DISABLE_WE4 ((uint32_t)0x00000310UL) /**< Offset from FLC Base Address: <tt>\b 0x0310</tt> */
<> 157:ff67d9f36b67 189 #define MXC_R_FLC_OFFS_DISABLE_WE5 ((uint32_t)0x00000314UL) /**< Offset from FLC Base Address: <tt>\b 0x0314</tt> */
<> 157:ff67d9f36b67 190 #define MXC_R_FLC_OFFS_DISABLE_WE6 ((uint32_t)0x00000318UL) /**< Offset from FLC Base Address: <tt>\b 0x0318</tt> */
<> 157:ff67d9f36b67 191 #define MXC_R_FLC_OFFS_DISABLE_WE7 ((uint32_t)0x0000031CUL) /**< Offset from FLC Base Address: <tt>\b 0x031C</tt> */
<> 157:ff67d9f36b67 192 /**@} end of group FLC_Register_Offsets */
<> 157:ff67d9f36b67 193
<> 157:ff67d9f36b67 194 /**
<> 157:ff67d9f36b67 195 * @ingroup flc_registers
<> 157:ff67d9f36b67 196 * @defgroup FLC_FADDR_Register FLC_FADDR
<> 157:ff67d9f36b67 197 * @brief Field Positions and Bit Masks for the FLC_FADDR register.
<> 157:ff67d9f36b67 198 * @{
<> 157:ff67d9f36b67 199 */
<> 157:ff67d9f36b67 200 #define MXC_F_FLC_FADDR_FADDR_POS 0 /**< FADDR Position */
<> 157:ff67d9f36b67 201 #define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x003FFFFFUL << MXC_F_FLC_FADDR_FADDR_POS)) /**< FADDR Mask */
<> 157:ff67d9f36b67 202 /**@} end of group FLC_FADDR */
<> 157:ff67d9f36b67 203 /**
<> 157:ff67d9f36b67 204 * @ingroup flc_registers
<> 157:ff67d9f36b67 205 * @defgroup FLC_FCKDIV_Register FLC_FCKDIV
<> 157:ff67d9f36b67 206 * @brief Field Positions and Bit Masks for the FLC_FCKDIV register.
<> 157:ff67d9f36b67 207 * @{
<> 157:ff67d9f36b67 208 */
<> 157:ff67d9f36b67 209 #define MXC_F_FLC_FCKDIV_FCKDIV_POS /**< FCKDIV Position */
<> 157:ff67d9f36b67 210 #define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000007FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS)) /**< FCKDIV Mask */
<> 157:ff67d9f36b67 211 #define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS 16 /**< AUTO_FCKDIV_RESULT Position */
<> 157:ff67d9f36b67 212 #define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS)) /**< AUTO_FCKDIV_RESULT Mask */
<> 157:ff67d9f36b67 213 /**@} end of group FLC_FCKDIV */
<> 157:ff67d9f36b67 214 /**
<> 157:ff67d9f36b67 215 * @ingroup flc_registers
<> 157:ff67d9f36b67 216 * @defgroup FLC_CTRL_Register FLC_CTRL
<> 157:ff67d9f36b67 217 * @brief Field Positions and Bit Masks for the FLC_CTRL register.
<> 157:ff67d9f36b67 218 * @{
<> 157:ff67d9f36b67 219 */
<> 157:ff67d9f36b67 220 #define MXC_F_FLC_CTRL_WRITE_POS 0 /**< WRITE Position */
<> 157:ff67d9f36b67 221 #define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS)) /**< WRITE Mask */
<> 157:ff67d9f36b67 222 #define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 /**< MASS_ERASE Position */
<> 157:ff67d9f36b67 223 #define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) /**< MASS_ERASE Mask */
<> 157:ff67d9f36b67 224 #define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 /**< PAGE_ERASE Position */
<> 157:ff67d9f36b67 225 #define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) /**< PAGE_ERASE Mask */
<> 157:ff67d9f36b67 226 #define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< ERASE_CODE Position */
<> 157:ff67d9f36b67 227 #define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< ERASE_CODE Mask */
<> 157:ff67d9f36b67 228 #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16 /**< INFO_BLOCK_UNLOCK Position */
<> 157:ff67d9f36b67 229 #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS)) /**< INFO_BLOCK_UNLOCK Mask */
<> 157:ff67d9f36b67 230 #define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17 /**< WRITE_ENABLE Position */
<> 157:ff67d9f36b67 231 #define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS)) /**< WRITE_ENABLE Mask */
<> 157:ff67d9f36b67 232 #define MXC_F_FLC_CTRL_PENDING_POS 24 /**< PENDING Position */
<> 157:ff67d9f36b67 233 #define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS)) /**< PENDING Mask */
<> 157:ff67d9f36b67 234 #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25 /**< INFO_BLOCK_VALID Position */
<> 157:ff67d9f36b67 235 #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS)) /**< INFO_BLOCK_VALID Mask */
<> 157:ff67d9f36b67 236 #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27 /**< AUTO_INCRE_MODE Position */
<> 157:ff67d9f36b67 237 #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS)) /**< AUTO_INCRE_MODE Mask */
<> 157:ff67d9f36b67 238 #define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28 /**< FLSH_UNLOCK Position */
<> 157:ff67d9f36b67 239 #define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS)) /**< FLSH_UNLOCK Mask */
<> 157:ff67d9f36b67 240 /**@} end of group FLC_CTRL */
<> 157:ff67d9f36b67 241 /**
<> 157:ff67d9f36b67 242 * @ingroup flc_registers
<> 157:ff67d9f36b67 243 * @defgroup FLC_INTR_Register FLC_INTR
<> 157:ff67d9f36b67 244 * @brief Field Positions and Bit Masks for the FLC_INTR register.
<> 157:ff67d9f36b67 245 * @{
<> 157:ff67d9f36b67 246 */
<> 157:ff67d9f36b67 247 #define MXC_F_FLC_INTR_FINISHED_IF_POS 0 /**< FINISHED_IF Position */
<> 157:ff67d9f36b67 248 #define MXC_F_FLC_INTR_FINISHED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IF_POS)) /**< FINISHED_IF Mask */
<> 157:ff67d9f36b67 249 #define MXC_F_FLC_INTR_FAILED_IF_POS 1 /**< FAILED_IF Position */
<> 157:ff67d9f36b67 250 #define MXC_F_FLC_INTR_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IF_POS)) /**< FAILED_IF Mask */
<> 157:ff67d9f36b67 251 #define MXC_F_FLC_INTR_FINISHED_IE_POS 8 /**< FINISHED_IE Position */
<> 157:ff67d9f36b67 252 #define MXC_F_FLC_INTR_FINISHED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IE_POS)) /**< FINISHED_IE Mask */
<> 157:ff67d9f36b67 253 #define MXC_F_FLC_INTR_FAILED_IE_POS 9 /**< FAILED_IE Position */
<> 157:ff67d9f36b67 254 #define MXC_F_FLC_INTR_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IE_POS)) /**< FAILED_IE Mask */
<> 157:ff67d9f36b67 255 #define MXC_F_FLC_INTR_FAIL_FLAGS_POS 16 /**< FAIL_FLAGS Position */
<> 157:ff67d9f36b67 256 #define MXC_F_FLC_INTR_FAIL_FLAGS ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_INTR_FAIL_FLAGS_POS)) /**< FAIL_FLAGS Mask */
<> 157:ff67d9f36b67 257 /**@} end of group FLC_INTR */
<> 157:ff67d9f36b67 258 /**
<> 157:ff67d9f36b67 259 * @ingroup flc_registers
<> 157:ff67d9f36b67 260 * @defgroup FLC_PERFORM_Register FLC_PERFORM
<> 157:ff67d9f36b67 261 * @brief Field Positions and Bit Masks for the FLC_PERFORM register.
<> 157:ff67d9f36b67 262 * @{
<> 157:ff67d9f36b67 263 */
<> 157:ff67d9f36b67 264 #define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0 /**< DELAY_SE_EN Position */
<> 157:ff67d9f36b67 265 #define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS)) /**< DELAY_SE_EN Mask */
<> 157:ff67d9f36b67 266 #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8 /**< FAST_READ_MODE_EN Position */
<> 157:ff67d9f36b67 267 #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS)) /**< FAST_READ_MODE_EN Mask */
<> 157:ff67d9f36b67 268 #define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS 12 /**< EN_PREVENT_FAIL Position */
<> 157:ff67d9f36b67 269 #define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS)) /**< EN_PREVENT_FAIL Mask */
<> 157:ff67d9f36b67 270 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS 16 /**< EN_BACK2BACK_RDS Position */
<> 157:ff67d9f36b67 271 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS)) /**< EN_BACK2BACK_RDS Mask */
<> 157:ff67d9f36b67 272 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS 20 /**< EN_BACK2BACK_WRS Position */
<> 157:ff67d9f36b67 273 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS)) /**< EN_BACK2BACK_WRS Mask */
<> 157:ff67d9f36b67 274 #define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS 24 /**< EN_MERGE_GRAB_GNT Position */
<> 157:ff67d9f36b67 275 #define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS)) /**< EN_MERGE_GRAB_GNT Mask */
<> 157:ff67d9f36b67 276 #define MXC_F_FLC_PERFORM_AUTO_TACC_POS 28 /**< AUTO_TACC Position */
<> 157:ff67d9f36b67 277 #define MXC_F_FLC_PERFORM_AUTO_TACC ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_TACC_POS)) /**< AUTO_TACC Mask */
<> 157:ff67d9f36b67 278 #define MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS 29 /**< AUTO_CLKDIV Position */
<> 157:ff67d9f36b67 279 #define MXC_F_FLC_PERFORM_AUTO_CLKDIV ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS)) /**< AUTO_CLKDIV Mask */
<> 157:ff67d9f36b67 280 /**@} end of group FLC_PERFORM */
<> 157:ff67d9f36b67 281 /**
<> 157:ff67d9f36b67 282 * @ingroup flc_registers
<> 157:ff67d9f36b67 283 * @defgroup FLC_STATUS_Register FLC_STATUS
<> 157:ff67d9f36b67 284 * @brief Field Positions and Bit Masks for the FLC_STATUS register.
<> 157:ff67d9f36b67 285 * @{
<> 157:ff67d9f36b67 286 */
<> 157:ff67d9f36b67 287 #define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS 0 /**< JTAG_LOCK_WINDOW Position */
<> 157:ff67d9f36b67 288 #define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS)) /**< JTAG_LOCK_WINDOW Mask */
<> 157:ff67d9f36b67 289 #define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS 1 /**< JTAG_LOCK_STATIC Position */
<> 157:ff67d9f36b67 290 #define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS)) /**< JTAG_LOCK_STATIC Mask */
<> 157:ff67d9f36b67 291 #define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3 /**< AUTO_LOCK Position */
<> 157:ff67d9f36b67 292 #define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS)) /**< AUTO_LOCK Mask */
<> 157:ff67d9f36b67 293 #define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS 29 /**< TRIM_UPDATE_DONE Position */
<> 157:ff67d9f36b67 294 #define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */
<> 157:ff67d9f36b67 295 #define MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS 30 /**< INFO_BLOCK_VALID Position */
<> 157:ff67d9f36b67 296 #define MXC_F_FLC_STATUS_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS)) /**< INFO_BLOCK_VALID Mask */
<> 157:ff67d9f36b67 297 /**@} end of group FLC_STATUS*/
<> 157:ff67d9f36b67 298 /**
<> 157:ff67d9f36b67 299 * @ingroup flc_registers
<> 157:ff67d9f36b67 300 * @defgroup FLC_SECURITY_Register FLC_SECURITY
<> 157:ff67d9f36b67 301 * @brief Field Positions and Bit Masks for the FLC_SECURITY register.
<> 157:ff67d9f36b67 302 * @{
<> 157:ff67d9f36b67 303 */
<> 157:ff67d9f36b67 304 #define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0 /**< DEBUG_DISABLE Position */
<> 157:ff67d9f36b67 305 #define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS)) /**< DEBUG_DISABLE Mask */
<> 157:ff67d9f36b67 306 #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8 /**< MASS_ERASE_LOCK Position */
<> 157:ff67d9f36b67 307 #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS)) /**< MASS_ERASE_LOCK Mask */
<> 157:ff67d9f36b67 308 #define MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS 16 /**< DISABLE_AHB_WR Position */
<> 157:ff67d9f36b67 309 #define MXC_F_FLC_SECURITY_DISABLE_AHB_WR ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS)) /**< DISABLE_AHB_WR Mask */
<> 157:ff67d9f36b67 310 #define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS 24 /**< FLC_SETTINGS_LOCK Position */
<> 157:ff67d9f36b67 311 #define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS)) /**< FLC_SETTINGS_LOCK Mask */
<> 157:ff67d9f36b67 312 #define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 28 /**< SECURITY_LOCK Position */
<> 157:ff67d9f36b67 313 #define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS)) /**< SECURITY_LOCK Mask */
<> 157:ff67d9f36b67 314 /**@} end of group FLC_SECURITY */
<> 157:ff67d9f36b67 315 /**
<> 157:ff67d9f36b67 316 * @ingroup flc_registers
<> 157:ff67d9f36b67 317 * @defgroup FLC_BYPASS_Register FLC_BYPASS
<> 157:ff67d9f36b67 318 * @brief Field Positions and Bit Masks for the FLC_BYPASS register.
<> 157:ff67d9f36b67 319 * @{
<> 157:ff67d9f36b67 320 */
<> 157:ff67d9f36b67 321 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0 /**< DESTRUCT_BYPASS_ERASE Position */
<> 157:ff67d9f36b67 322 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS)) /**< DESTRUCT_BYPASS_ERASE Mask */
<> 157:ff67d9f36b67 323 #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1 /**< SUPERWIPE_ERASE Position */
<> 157:ff67d9f36b67 324 #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS)) /**< SUPERWIPE_ERASE Mask */
<> 157:ff67d9f36b67 325 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2 /**< DESTRUCT_BYPASS_COMPLETE Position */
<> 157:ff67d9f36b67 326 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS)) /**< DESTRUCT_BYPASS_COMPLETE Mask */
<> 157:ff67d9f36b67 327 #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3 /**< SUPERWIPE_COMPLETE Position */
<> 157:ff67d9f36b67 328 #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS)) /**< SUPERWIPE_COMPLETE Mask */
<> 157:ff67d9f36b67 329 /**@} end of group FLC_BYPASS*/
<> 157:ff67d9f36b67 330 /**
<> 157:ff67d9f36b67 331 * @ingroup flc_registers
<> 157:ff67d9f36b67 332 * @defgroup FLC_CTRL2_Register FLC_CTRL2
<> 157:ff67d9f36b67 333 * @brief Field Positions and Bit Masks for the FLC_CTRL2 register.
<> 157:ff67d9f36b67 334 * @{
<> 157:ff67d9f36b67 335 */
<> 157:ff67d9f36b67 336 #define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0 /**< FLASH_LVE Position */
<> 157:ff67d9f36b67 337 #define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FLASH_LVE_POS)) /**< FLASH_LVE Mask */
<> 157:ff67d9f36b67 338 #define MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS 1 /**< FRC_FCLK1_ON Position */
<> 157:ff67d9f36b67 339 #define MXC_F_FLC_CTRL2_FRC_FCLK1_ON ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS)) /**< FRC_FCLK1_ON Mask */
<> 157:ff67d9f36b67 340 #define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS 3 /**< EN_WRITE_ALL_ZEROES Position */
<> 157:ff67d9f36b67 341 #define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS)) /**< EN_WRITE_ALL_ZEROES Mask */
<> 157:ff67d9f36b67 342 #define MXC_F_FLC_CTRL2_EN_CHANGE_POS 4 /**< EN_CHANGE Position */
<> 157:ff67d9f36b67 343 #define MXC_F_FLC_CTRL2_EN_CHANGE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_CHANGE_POS)) /**< EN_CHANGE Mask */
<> 157:ff67d9f36b67 344 #define MXC_F_FLC_CTRL2_SLOW_CLK_POS 5 /**< SLOW_CLK Position */
<> 157:ff67d9f36b67 345 #define MXC_F_FLC_CTRL2_SLOW_CLK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_SLOW_CLK_POS)) /**< SLOW_CLK Mask */
<> 157:ff67d9f36b67 346 #define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS 6 /**< ENABLE_RAM_HRESP Position */
<> 157:ff67d9f36b67 347 #define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS)) /**< ENABLE_RAM_HRESP Mask */
<> 157:ff67d9f36b67 348 #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8 /**< BYPASS_AHB_FAIL Position */
<> 157:ff67d9f36b67 349 #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS)) /**< BYPASS_AHB_FAIL Mask */
<> 157:ff67d9f36b67 350 /**@} end of group FLC_CTRL2*/
<> 157:ff67d9f36b67 351 /**
<> 157:ff67d9f36b67 352 * @ingroup flc_registers
<> 157:ff67d9f36b67 353 * @defgroup FLC_INTFL1_Register FLC_INTFL1
<> 157:ff67d9f36b67 354 * @brief Field Positions and Bit Masks for the FLC_INTFL1 register.
<> 157:ff67d9f36b67 355 * @{
<> 157:ff67d9f36b67 356 */
<> 157:ff67d9f36b67 357 #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0 /**< SRAM_ADDR_WRAPPED Position */
<> 157:ff67d9f36b67 358 #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS)) /**< SRAM_ADDR_WRAPPED Mask */
<> 157:ff67d9f36b67 359 #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1 /**< INVALID_FLASH_ADDR Position */
<> 157:ff67d9f36b67 360 #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS)) /**< INVALID_FLASH_ADDR Mask */
<> 157:ff67d9f36b67 361 #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2 /**< FLASH_READ_LOCKED Position */
<> 157:ff67d9f36b67 362 #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS)) /**< FLASH_READ_LOCKED Mask */
<> 157:ff67d9f36b67 363 #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3 /**< TRIM_UPDATE_DONE Position */
<> 157:ff67d9f36b67 364 #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */
<> 157:ff67d9f36b67 365 #define MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS 4 /**< FLC_STATE_DONE Position */
<> 157:ff67d9f36b67 366 #define MXC_F_FLC_INTFL1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS)) /**< FLC_STATE_DONE Mask */
<> 157:ff67d9f36b67 367 #define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS 5 /**< FLC_PROG_COMPLETE Position */
<> 157:ff67d9f36b67 368 #define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS)) /**< FLC_PROG_COMPLETE Mask */
<> 157:ff67d9f36b67 369 /**@} end of group FLC_INTFL1 */
<> 157:ff67d9f36b67 370 /**
<> 157:ff67d9f36b67 371 * @ingroup flc_registers
<> 157:ff67d9f36b67 372 * @defgroup FLC_INTEN1_Register FLC_INTEN1
<> 157:ff67d9f36b67 373 * @brief Field Positions and Bit Masks for the FLC_INTEN1 register.
<> 157:ff67d9f36b67 374 * @{
<> 157:ff67d9f36b67 375 */
<> 157:ff67d9f36b67 376 #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0 /**< SRAM_ADDR_WRAPPED Position */
<> 157:ff67d9f36b67 377 #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS)) /**< SRAM_ADDR_WRAPPED Mask */
<> 157:ff67d9f36b67 378 #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1 /**< INVALID_FLASH_ADDR Position */
<> 157:ff67d9f36b67 379 #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS)) /**< INVALID_FLASH_ADDR Mask */
<> 157:ff67d9f36b67 380 #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2 /**< FLASH_READ_LOCKED Position */
<> 157:ff67d9f36b67 381 #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS)) /**< FLASH_READ_LOCKED Mask */
<> 157:ff67d9f36b67 382 #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3 /**< TRIM_UPDATE_DONE Position */
<> 157:ff67d9f36b67 383 #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */
<> 157:ff67d9f36b67 384 #define MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS 4 /**< FLC_STATE_DONE Position */
<> 157:ff67d9f36b67 385 #define MXC_F_FLC_INTEN1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS)) /**< FLC_STATE_DONE Mask */
<> 157:ff67d9f36b67 386 #define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS 5 /**< FLC_PROG_COMPLETE Position */
<> 157:ff67d9f36b67 387 #define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS)) /**< FLC_PROG_COMPLETE Mask */
<> 157:ff67d9f36b67 388 /**@} end of group FLC_INTEN1*/
<> 157:ff67d9f36b67 389
<> 157:ff67d9f36b67 390 #ifdef __cplusplus
<> 157:ff67d9f36b67 391 }
<> 157:ff67d9f36b67 392 #endif
<> 157:ff67d9f36b67 393
<> 157:ff67d9f36b67 394 #endif /* _MXC_FLC_REGS_H_ */
<> 157:ff67d9f36b67 395