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targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/system_stm32l0xx.c@153:fa9ff456f731, 2016-12-20 (annotated)

Committer:
<>
Date:
Tue Dec 20 17:27:56 2016 +0000
Revision:
153:fa9ff456f731
Parent:
151:5eaa88a5bcc7 
This updates the lib to the mbed lib v132

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file system_stm32l0xx.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 151:5eaa88a5bcc7 5 * @version V1.7.0
<> 151:5eaa88a5bcc7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides two functions and one global variable to be called from
<> 144:ef7eb2e8f9f7 10 * user application:
<> 144:ef7eb2e8f9f7 11 * - SystemInit(): This function is called at startup just after reset and
<> 144:ef7eb2e8f9f7 12 * before branch to main program. This call is made inside
<> 144:ef7eb2e8f9f7 13 * the "startup_stm32l0xx.s" file.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
<> 144:ef7eb2e8f9f7 16 * by the user application to setup the SysTick
<> 144:ef7eb2e8f9f7 17 * timer or configure other parameters.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
<> 144:ef7eb2e8f9f7 20 * be called whenever the core clock is changed
<> 144:ef7eb2e8f9f7 21 * during program execution.
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * This file configures the system clock as follows:
<> 144:ef7eb2e8f9f7 24 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
<> 144:ef7eb2e8f9f7 26 * | (external 8 MHz clock) | (internal 16 MHz)
<> 144:ef7eb2e8f9f7 27 * | 2- PLL_HSE_XTAL |
<> 144:ef7eb2e8f9f7 28 * | (external 8 MHz xtal) |
<> 144:ef7eb2e8f9f7 29 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30 * SYSCLK(MHz) | 32 | 32
<> 144:ef7eb2e8f9f7 31 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 32 * AHBCLK (MHz) | 32 | 32
<> 144:ef7eb2e8f9f7 33 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 34 * APB1CLK (MHz) | 32 | 32
<> 144:ef7eb2e8f9f7 35 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 36 * APB2CLK (MHz) | 32 | 32
<> 144:ef7eb2e8f9f7 37 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 38 * USB capable (48 MHz precise clock) | YES | YES
<> 144:ef7eb2e8f9f7 39 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 40 ******************************************************************************
<> 144:ef7eb2e8f9f7 41 * @attention
<> 144:ef7eb2e8f9f7 42 *
<> 151:5eaa88a5bcc7 43 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 44 *
<> 144:ef7eb2e8f9f7 45 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 46 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 47 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 48 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 49 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 50 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 51 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 52 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 53 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 54 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 55 *
<> 144:ef7eb2e8f9f7 56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 63 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 66 *
<> 144:ef7eb2e8f9f7 67 ******************************************************************************
<> 144:ef7eb2e8f9f7 68 */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /** @addtogroup CMSIS
<> 144:ef7eb2e8f9f7 71 * @{
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /** @addtogroup stm32l0xx_system
<> 144:ef7eb2e8f9f7 75 * @{
<> 144:ef7eb2e8f9f7 76 */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /** @addtogroup STM32L0xx_System_Private_Includes
<> 144:ef7eb2e8f9f7 79 * @{
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 #include "stm32l0xx.h"
<> 144:ef7eb2e8f9f7 83 #include "hal_tick.h"
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 #if !defined (HSE_VALUE)
<> 151:5eaa88a5bcc7 86 #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
<> 144:ef7eb2e8f9f7 87 #endif /* HSE_VALUE */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 #if !defined (MSI_VALUE)
<> 151:5eaa88a5bcc7 90 #define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
<> 144:ef7eb2e8f9f7 91 #endif /* MSI_VALUE */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 #if !defined (HSI_VALUE)
<> 151:5eaa88a5bcc7 94 #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
<> 144:ef7eb2e8f9f7 95 #endif /* HSI_VALUE */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /**
<> 144:ef7eb2e8f9f7 99 * @}
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /** @addtogroup STM32L0xx_System_Private_TypesDefinitions
<> 144:ef7eb2e8f9f7 103 * @{
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /**
<> 144:ef7eb2e8f9f7 107 * @}
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /** @addtogroup STM32L0xx_System_Private_Defines
<> 144:ef7eb2e8f9f7 111 * @{
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113 /************************* Miscellaneous Configuration ************************/
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /*!< Uncomment the following line if you need to relocate your vector Table in
<> 144:ef7eb2e8f9f7 116 Internal SRAM. */
<> 144:ef7eb2e8f9f7 117 /* #define VECT_TAB_SRAM */
<> 151:5eaa88a5bcc7 118 #define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
<> 151:5eaa88a5bcc7 119 This value must be a multiple of 0x100. */
<> 144:ef7eb2e8f9f7 120 /******************************************************************************/
<> 144:ef7eb2e8f9f7 121 /**
<> 144:ef7eb2e8f9f7 122 * @}
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /** @addtogroup STM32L0xx_System_Private_Macros
<> 144:ef7eb2e8f9f7 126 * @{
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
<> 144:ef7eb2e8f9f7 130 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
<> 144:ef7eb2e8f9f7 131 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /**
<> 144:ef7eb2e8f9f7 134 * @}
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /** @addtogroup STM32L0xx_System_Private_Variables
<> 144:ef7eb2e8f9f7 138 * @{
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140 /* This variable is updated in three ways:
<> 144:ef7eb2e8f9f7 141 1) by calling CMSIS function SystemCoreClockUpdate()
<> 144:ef7eb2e8f9f7 142 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
<> 144:ef7eb2e8f9f7 143 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
<> 144:ef7eb2e8f9f7 144 Note: If you use this function to configure the system clock; then there
<> 144:ef7eb2e8f9f7 145 is no need to call the 2 first functions listed above, since SystemCoreClock
<> 144:ef7eb2e8f9f7 146 variable is updated automatically.
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148 uint32_t SystemCoreClock = 32000000;
<> 151:5eaa88a5bcc7 149 const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
<> 151:5eaa88a5bcc7 150 const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
<> 151:5eaa88a5bcc7 151 const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /**
<> 144:ef7eb2e8f9f7 154 * @}
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
<> 144:ef7eb2e8f9f7 158 * @{
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
<> 144:ef7eb2e8f9f7 162 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
<> 144:ef7eb2e8f9f7 163 #endif
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 uint8_t SetSysClock_PLL_HSI(void);
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /**
<> 144:ef7eb2e8f9f7 168 * @}
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /** @addtogroup STM32L0xx_System_Private_Functions
<> 144:ef7eb2e8f9f7 172 * @{
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /**
<> 144:ef7eb2e8f9f7 176 * @brief Setup the microcontroller system.
<> 144:ef7eb2e8f9f7 177 * @param None
<> 144:ef7eb2e8f9f7 178 * @retval None
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180 void SystemInit (void)
<> 144:ef7eb2e8f9f7 181 {
<> 144:ef7eb2e8f9f7 182 /*!< Set MSION bit */
<> 151:5eaa88a5bcc7 183 RCC->CR |= (uint32_t)0x00000100U;
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
<> 151:5eaa88a5bcc7 186 RCC->CFGR &= (uint32_t) 0x88FF400CU;
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
<> 151:5eaa88a5bcc7 189 RCC->CR &= (uint32_t)0xFEF6FFF6U;
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /*!< Reset HSI48ON bit */
<> 151:5eaa88a5bcc7 192 RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /*!< Reset HSEBYP bit */
<> 151:5eaa88a5bcc7 195 RCC->CR &= (uint32_t)0xFFFBFFFFU;
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
<> 151:5eaa88a5bcc7 198 RCC->CFGR &= (uint32_t)0xFF02FFFFU;
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /*!< Disable all interrupts */
<> 151:5eaa88a5bcc7 201 RCC->CIER = 0x00000000U;
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /* Configure the Vector Table location add offset address ------------------*/
<> 144:ef7eb2e8f9f7 204 #ifdef VECT_TAB_SRAM
<> 144:ef7eb2e8f9f7 205 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
<> 144:ef7eb2e8f9f7 206 #else
<> 144:ef7eb2e8f9f7 207 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
<> 144:ef7eb2e8f9f7 208 #endif
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /* Configure the Cube driver */
<> 144:ef7eb2e8f9f7 211 SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
<> 144:ef7eb2e8f9f7 212 HAL_Init();
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* Configure the System clock source, PLL Multiplier and Divider factors,
<> 144:ef7eb2e8f9f7 215 AHB/APBx prescalers and Flash settings */
<> 144:ef7eb2e8f9f7 216 SetSysClock();
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /* Reset the timer to avoid issues after the RAM initialization */
<> 144:ef7eb2e8f9f7 219 TIM_MST_RESET_ON;
<> 144:ef7eb2e8f9f7 220 TIM_MST_RESET_OFF;
<> 144:ef7eb2e8f9f7 221 }
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @brief Update SystemCoreClock according to Clock Register Values
<> 144:ef7eb2e8f9f7 225 * The SystemCoreClock variable contains the core clock (HCLK), it can
<> 144:ef7eb2e8f9f7 226 * be used by the user application to setup the SysTick timer or configure
<> 144:ef7eb2e8f9f7 227 * other parameters.
<> 144:ef7eb2e8f9f7 228 *
<> 144:ef7eb2e8f9f7 229 * @note Each time the core clock (HCLK) changes, this function must be called
<> 144:ef7eb2e8f9f7 230 * to update SystemCoreClock variable value. Otherwise, any configuration
<> 144:ef7eb2e8f9f7 231 * based on this variable will be incorrect.
<> 144:ef7eb2e8f9f7 232 *
<> 144:ef7eb2e8f9f7 233 * @note - The system frequency computed by this function is not the real
<> 144:ef7eb2e8f9f7 234 * frequency in the chip. It is calculated based on the predefined
<> 144:ef7eb2e8f9f7 235 * constant and the selected clock source:
<> 144:ef7eb2e8f9f7 236 *
<> 144:ef7eb2e8f9f7 237 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
<> 144:ef7eb2e8f9f7 238 * value as defined by the MSI range.
<> 144:ef7eb2e8f9f7 239 *
<> 144:ef7eb2e8f9f7 240 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
<> 144:ef7eb2e8f9f7 241 *
<> 144:ef7eb2e8f9f7 242 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 243 *
<> 144:ef7eb2e8f9f7 244 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 245 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
<> 144:ef7eb2e8f9f7 246 *
<> 144:ef7eb2e8f9f7 247 * (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
<> 144:ef7eb2e8f9f7 248 * 16 MHz) but the real value may vary depending on the variations
<> 144:ef7eb2e8f9f7 249 * in voltage and temperature.
<> 144:ef7eb2e8f9f7 250 *
<> 144:ef7eb2e8f9f7 251 * (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
<> 144:ef7eb2e8f9f7 252 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
<> 144:ef7eb2e8f9f7 253 * frequency of the crystal used. Otherwise, this function may
<> 144:ef7eb2e8f9f7 254 * have wrong result.
<> 144:ef7eb2e8f9f7 255 *
<> 144:ef7eb2e8f9f7 256 * - The result of this function could be not correct when using fractional
<> 144:ef7eb2e8f9f7 257 * value for HSE crystal.
<> 144:ef7eb2e8f9f7 258 * @param None
<> 144:ef7eb2e8f9f7 259 * @retval None
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261 void SystemCoreClockUpdate (void)
<> 144:ef7eb2e8f9f7 262 {
<> 151:5eaa88a5bcc7 263 uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /* Get SYSCLK source -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 266 tmp = RCC->CFGR & RCC_CFGR_SWS;
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 switch (tmp)
<> 144:ef7eb2e8f9f7 269 {
<> 151:5eaa88a5bcc7 270 case 0x00U: /* MSI used as system clock */
<> 151:5eaa88a5bcc7 271 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
<> 151:5eaa88a5bcc7 272 SystemCoreClock = (32768U * (1U << (msirange + 1U)));
<> 144:ef7eb2e8f9f7 273 break;
<> 151:5eaa88a5bcc7 274 case 0x04U: /* HSI used as system clock */
<> 144:ef7eb2e8f9f7 275 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 276 break;
<> 151:5eaa88a5bcc7 277 case 0x08U: /* HSE used as system clock */
<> 144:ef7eb2e8f9f7 278 SystemCoreClock = HSE_VALUE;
<> 144:ef7eb2e8f9f7 279 break;
<> 151:5eaa88a5bcc7 280 case 0x0CU: /* PLL used as system clock */
<> 144:ef7eb2e8f9f7 281 /* Get PLL clock source and multiplication factor ----------------------*/
<> 144:ef7eb2e8f9f7 282 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
<> 144:ef7eb2e8f9f7 283 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
<> 151:5eaa88a5bcc7 284 pllmul = PLLMulTable[(pllmul >> 18U)];
<> 151:5eaa88a5bcc7 285 plldiv = (plldiv >> 22U) + 1U;
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
<> 144:ef7eb2e8f9f7 288
<> 151:5eaa88a5bcc7 289 if (pllsource == 0x00U)
<> 144:ef7eb2e8f9f7 290 {
<> 144:ef7eb2e8f9f7 291 /* HSI oscillator clock selected as PLL clock entry */
<> 144:ef7eb2e8f9f7 292 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
<> 144:ef7eb2e8f9f7 293 }
<> 144:ef7eb2e8f9f7 294 else
<> 144:ef7eb2e8f9f7 295 {
<> 144:ef7eb2e8f9f7 296 /* HSE selected as PLL clock entry */
<> 144:ef7eb2e8f9f7 297 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
<> 144:ef7eb2e8f9f7 298 }
<> 144:ef7eb2e8f9f7 299 break;
<> 144:ef7eb2e8f9f7 300 default: /* MSI used as system clock */
<> 151:5eaa88a5bcc7 301 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
<> 151:5eaa88a5bcc7 302 SystemCoreClock = (32768U * (1U << (msirange + 1U)));
<> 144:ef7eb2e8f9f7 303 break;
<> 144:ef7eb2e8f9f7 304 }
<> 144:ef7eb2e8f9f7 305 /* Compute HCLK clock frequency --------------------------------------------*/
<> 144:ef7eb2e8f9f7 306 /* Get HCLK prescaler */
<> 151:5eaa88a5bcc7 307 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
<> 144:ef7eb2e8f9f7 308 /* HCLK clock frequency */
<> 144:ef7eb2e8f9f7 309 SystemCoreClock >>= tmp;
<> 144:ef7eb2e8f9f7 310 }
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /**
<> 144:ef7eb2e8f9f7 313 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
<> 144:ef7eb2e8f9f7 314 * AHB/APBx prescalers and Flash settings
<> 144:ef7eb2e8f9f7 315 * @note This function should be called only once the RCC clock configuration
<> 144:ef7eb2e8f9f7 316 * is reset to the default reset state (done in SystemInit() function).
<> 144:ef7eb2e8f9f7 317 * @param None
<> 144:ef7eb2e8f9f7 318 * @retval None
<> 144:ef7eb2e8f9f7 319 */
<> 144:ef7eb2e8f9f7 320 void SetSysClock(void)
<> 144:ef7eb2e8f9f7 321 {
<> 144:ef7eb2e8f9f7 322 /* 1- Try to start with HSE and external clock */
<> 144:ef7eb2e8f9f7 323 #if USE_PLL_HSE_EXTC != 0
<> 144:ef7eb2e8f9f7 324 if (SetSysClock_PLL_HSE(1) == 0)
<> 144:ef7eb2e8f9f7 325 #endif
<> 144:ef7eb2e8f9f7 326 {
<> 144:ef7eb2e8f9f7 327 /* 2- If fail try to start with HSE and external xtal */
<> 144:ef7eb2e8f9f7 328 #if USE_PLL_HSE_XTAL != 0
<> 144:ef7eb2e8f9f7 329 if (SetSysClock_PLL_HSE(0) == 0)
<> 144:ef7eb2e8f9f7 330 #endif
<> 144:ef7eb2e8f9f7 331 {
<> 144:ef7eb2e8f9f7 332 /* 3- If fail start with HSI clock */
<> 144:ef7eb2e8f9f7 333 if (SetSysClock_PLL_HSI() == 0)
<> 144:ef7eb2e8f9f7 334 {
<> 144:ef7eb2e8f9f7 335 while(1)
<> 144:ef7eb2e8f9f7 336 {
<> 144:ef7eb2e8f9f7 337 // [TODO] Put something here to tell the user that a problem occured...
<> 144:ef7eb2e8f9f7 338 }
<> 144:ef7eb2e8f9f7 339 }
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341 }
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /* Output clock on MCO1 pin(PA8) for debugging purpose */
<> 144:ef7eb2e8f9f7 344 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
<> 144:ef7eb2e8f9f7 345 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
<> 144:ef7eb2e8f9f7 346 }
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
<> 144:ef7eb2e8f9f7 349 /******************************************************************************/
<> 144:ef7eb2e8f9f7 350 /* PLL (clocked by HSE) used as System clock source */
<> 144:ef7eb2e8f9f7 351 /******************************************************************************/
<> 144:ef7eb2e8f9f7 352 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
<> 144:ef7eb2e8f9f7 353 {
<> 144:ef7eb2e8f9f7 354 RCC_ClkInitTypeDef RCC_ClkInitStruct;
<> 144:ef7eb2e8f9f7 355 RCC_OscInitTypeDef RCC_OscInitStruct;
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* Used to gain time after DeepSleep in case HSI is used */
<> 144:ef7eb2e8f9f7 358 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
<> 144:ef7eb2e8f9f7 359 {
<> 144:ef7eb2e8f9f7 360 return 0;
<> 144:ef7eb2e8f9f7 361 }
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /* The voltage scaling allows optimizing the power consumption when the device is
<> 144:ef7eb2e8f9f7 364 clocked below the maximum system frequency, to update the voltage scaling value
<> 144:ef7eb2e8f9f7 365 regarding system frequency refer to product datasheet. */
<> 144:ef7eb2e8f9f7 366 __PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 367 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
<> 153:fa9ff456f731 370 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
<> 144:ef7eb2e8f9f7 371 if (bypass == 0)
<> 144:ef7eb2e8f9f7 372 {
<> 144:ef7eb2e8f9f7 373 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
<> 144:ef7eb2e8f9f7 374 }
<> 144:ef7eb2e8f9f7 375 else
<> 144:ef7eb2e8f9f7 376 {
<> 144:ef7eb2e8f9f7 377 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
<> 144:ef7eb2e8f9f7 378 }
<> 144:ef7eb2e8f9f7 379 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
<> 144:ef7eb2e8f9f7 380 #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \
<> 144:ef7eb2e8f9f7 381 !defined (STM32L011xx) && !defined (STM32L021xx)
<> 144:ef7eb2e8f9f7 382 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
<> 144:ef7eb2e8f9f7 383 #endif
<> 144:ef7eb2e8f9f7 384 // PLLCLK = (8 MHz * 8)/2 = 32 MHz
<> 144:ef7eb2e8f9f7 385 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 386 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
<> 144:ef7eb2e8f9f7 387 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_8;
<> 144:ef7eb2e8f9f7 388 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
<> 144:ef7eb2e8f9f7 389 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
<> 144:ef7eb2e8f9f7 390 {
<> 144:ef7eb2e8f9f7 391 return 0; // FAIL
<> 144:ef7eb2e8f9f7 392 }
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
<> 144:ef7eb2e8f9f7 395 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
<> 144:ef7eb2e8f9f7 396 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
<> 144:ef7eb2e8f9f7 397 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
<> 144:ef7eb2e8f9f7 398 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
<> 144:ef7eb2e8f9f7 399 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
<> 144:ef7eb2e8f9f7 400 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
<> 144:ef7eb2e8f9f7 401 {
<> 144:ef7eb2e8f9f7 402 return 0; // FAIL
<> 144:ef7eb2e8f9f7 403 }
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /* Output clock on MCO1 pin(PA8) for debugging purpose */
<> 144:ef7eb2e8f9f7 406 //if (bypass == 0)
<> 144:ef7eb2e8f9f7 407 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
<> 144:ef7eb2e8f9f7 408 //else
<> 144:ef7eb2e8f9f7 409 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 return 1; // OK
<> 144:ef7eb2e8f9f7 412 }
<> 144:ef7eb2e8f9f7 413 #endif
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /******************************************************************************/
<> 144:ef7eb2e8f9f7 416 /* PLL (clocked by HSI) used as System clock source */
<> 144:ef7eb2e8f9f7 417 /******************************************************************************/
<> 144:ef7eb2e8f9f7 418 uint8_t SetSysClock_PLL_HSI(void)
<> 144:ef7eb2e8f9f7 419 {
<> 144:ef7eb2e8f9f7 420 RCC_ClkInitTypeDef RCC_ClkInitStruct;
<> 144:ef7eb2e8f9f7 421 RCC_OscInitTypeDef RCC_OscInitStruct;
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /* The voltage scaling allows optimizing the power consumption when the device is
<> 144:ef7eb2e8f9f7 424 clocked below the maximum system frequency, to update the voltage scaling value
<> 144:ef7eb2e8f9f7 425 regarding system frequency refer to product datasheet. */
<> 144:ef7eb2e8f9f7 426 __PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 427 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
<> 153:fa9ff456f731 430 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
<> 144:ef7eb2e8f9f7 431 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
<> 144:ef7eb2e8f9f7 432 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
<> 144:ef7eb2e8f9f7 433 #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \
<> 144:ef7eb2e8f9f7 434 !defined (STM32L011xx) && !defined (STM32L021xx)
<> 144:ef7eb2e8f9f7 435 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
<> 144:ef7eb2e8f9f7 436 #endif
<> 144:ef7eb2e8f9f7 437 // PLLCLK = (16 MHz * 4)/2 = 32 MHz
<> 144:ef7eb2e8f9f7 438 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 439 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
<> 144:ef7eb2e8f9f7 440 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
<> 144:ef7eb2e8f9f7 441 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
<> 144:ef7eb2e8f9f7 442 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
<> 144:ef7eb2e8f9f7 443 {
<> 144:ef7eb2e8f9f7 444 return 0; // FAIL
<> 144:ef7eb2e8f9f7 445 }
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
<> 144:ef7eb2e8f9f7 448 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
<> 144:ef7eb2e8f9f7 449 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
<> 144:ef7eb2e8f9f7 450 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
<> 144:ef7eb2e8f9f7 451 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
<> 144:ef7eb2e8f9f7 452 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
<> 144:ef7eb2e8f9f7 453 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
<> 144:ef7eb2e8f9f7 454 {
<> 144:ef7eb2e8f9f7 455 return 0; // FAIL
<> 144:ef7eb2e8f9f7 456 }
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /* Output clock on MCO1 pin(PA8) for debugging purpose */
<> 144:ef7eb2e8f9f7 459 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 return 1; // OK
<> 144:ef7eb2e8f9f7 462 }
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /**
<> 144:ef7eb2e8f9f7 465 * @}
<> 144:ef7eb2e8f9f7 466 */
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /**
<> 144:ef7eb2e8f9f7 469 * @}
<> 144:ef7eb2e8f9f7 470 */
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /**
<> 144:ef7eb2e8f9f7 473 * @}
<> 144:ef7eb2e8f9f7 474 */
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/