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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.c@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:
<>
Date:
Wed Jan 04 16:58:05 2017 +0000
Revision:
154:37f96f9d4de2
Parent:
149:156823d33999
Child:
165:e614a9f1c9e2
This updates the lib to the mbed lib v133

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_dac.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 154:37f96f9d4de2 5 * @version V1.0.5
<> 154:37f96f9d4de2 6 * @date 06-December-2016
<> 144:ef7eb2e8f9f7 7 * @brief DAC HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Digital to Analog Converter (DAC) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 @verbatim
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 ##### DAC Peripheral features #####
<> 144:ef7eb2e8f9f7 19 ==============================================================================
<> 144:ef7eb2e8f9f7 20 [..]
<> 144:ef7eb2e8f9f7 21 *** DAC Channels ***
<> 144:ef7eb2e8f9f7 22 ====================
<> 144:ef7eb2e8f9f7 23 [..]
<> 144:ef7eb2e8f9f7 24 The device integrates two 12-bit Digital Analog Converters that can
<> 144:ef7eb2e8f9f7 25 be used independently or simultaneously (dual mode):
<> 144:ef7eb2e8f9f7 26 (#) DAC channel1 with DAC_OUT1 (PA4) as output
<> 144:ef7eb2e8f9f7 27 (#) DAC channel2 with DAC_OUT2 (PA5) as output
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 *** DAC Triggers ***
<> 144:ef7eb2e8f9f7 30 ====================
<> 144:ef7eb2e8f9f7 31 [..]
<> 144:ef7eb2e8f9f7 32 Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
<> 144:ef7eb2e8f9f7 33 and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
<> 144:ef7eb2e8f9f7 34 [..]
<> 144:ef7eb2e8f9f7 35 Digital to Analog conversion can be triggered by:
<> 144:ef7eb2e8f9f7 36 (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
<> 144:ef7eb2e8f9f7 37 The used pin (GPIOx_PIN_9) must be configured in input mode.
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 (#) Timers TRGO: TIM2, TIM4, TIM6, TIM7
<> 144:ef7eb2e8f9f7 40 For STM32F10x connectivity line devices and STM32F100x devices: TIM3
<> 144:ef7eb2e8f9f7 41 For STM32F10x high-density and XL-density devices: TIM8
<> 144:ef7eb2e8f9f7 42 For STM32F100x high-density value line devices: TIM15 as
<> 144:ef7eb2e8f9f7 43 replacement of TIM5.
<> 144:ef7eb2e8f9f7 44 (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 (#) Software using DAC_TRIGGER_SOFTWARE
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 *** DAC Buffer mode feature ***
<> 144:ef7eb2e8f9f7 49 ===============================
<> 144:ef7eb2e8f9f7 50 [..]
<> 144:ef7eb2e8f9f7 51 Each DAC channel integrates an output buffer that can be used to
<> 144:ef7eb2e8f9f7 52 reduce the output impedance, and to drive external loads directly
<> 144:ef7eb2e8f9f7 53 without having to add an external operational amplifier.
<> 144:ef7eb2e8f9f7 54 To enable, the output buffer use
<> 144:ef7eb2e8f9f7 55 sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
<> 144:ef7eb2e8f9f7 56 [..]
<> 144:ef7eb2e8f9f7 57 (@) Refer to the device datasheet for more details about output
<> 144:ef7eb2e8f9f7 58 impedance value with and without output buffer.
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 *** DAC connect feature ***
<> 144:ef7eb2e8f9f7 61 ===============================
<> 144:ef7eb2e8f9f7 62 [..]
<> 144:ef7eb2e8f9f7 63 Each DAC channel can be connected internally.
<> 144:ef7eb2e8f9f7 64 To connect, use
<> 144:ef7eb2e8f9f7 65 sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE;
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 *** GPIO configurations guidelines ***
<> 144:ef7eb2e8f9f7 68 =====================
<> 144:ef7eb2e8f9f7 69 [..]
<> 144:ef7eb2e8f9f7 70 When a DAC channel is used (ex channel1 on PA4) and the other is not
<> 144:ef7eb2e8f9f7 71 (ex channel1 on PA5 is configured in Analog and disabled).
<> 144:ef7eb2e8f9f7 72 Channel1 may disturb channel2 as coupling effect.
<> 144:ef7eb2e8f9f7 73 Note that there is no coupling on channel2 as soon as channel2 is turned on.
<> 144:ef7eb2e8f9f7 74 Coupling on adjacent channel could be avoided as follows:
<> 144:ef7eb2e8f9f7 75 when unused PA5 is configured as INPUT PULL-UP or DOWN.
<> 144:ef7eb2e8f9f7 76 PA5 is configured in ANALOG just before it is turned on.
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 *** DAC wave generation feature ***
<> 144:ef7eb2e8f9f7 79 ===================================
<> 144:ef7eb2e8f9f7 80 [..]
<> 144:ef7eb2e8f9f7 81 Both DAC channels can be used to generate
<> 144:ef7eb2e8f9f7 82 (#) Noise wave using HAL_DACEx_NoiseWaveGenerate()
<> 144:ef7eb2e8f9f7 83 (#) Triangle wave using HAL_DACEx_TriangleWaveGenerate()
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 *** DAC data format ***
<> 144:ef7eb2e8f9f7 86 =======================
<> 144:ef7eb2e8f9f7 87 [..]
<> 144:ef7eb2e8f9f7 88 The DAC data format can be:
<> 144:ef7eb2e8f9f7 89 (#) 8-bit right alignment using DAC_ALIGN_8B_R
<> 144:ef7eb2e8f9f7 90 (#) 12-bit left alignment using DAC_ALIGN_12B_L
<> 144:ef7eb2e8f9f7 91 (#) 12-bit right alignment using DAC_ALIGN_12B_R
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 *** DAC data value to voltage correspondance ***
<> 144:ef7eb2e8f9f7 94 ================================================
<> 144:ef7eb2e8f9f7 95 [..]
<> 144:ef7eb2e8f9f7 96 The analog output voltage on each DAC channel pin is determined
<> 144:ef7eb2e8f9f7 97 by the following equation:
<> 144:ef7eb2e8f9f7 98 [..]
<> 144:ef7eb2e8f9f7 99 DAC_OUTx = VREF+ * DOR / 4095
<> 144:ef7eb2e8f9f7 100 (+) with DOR is the Data Output Register
<> 144:ef7eb2e8f9f7 101 [..]
<> 144:ef7eb2e8f9f7 102 VEF+ is the input voltage reference (refer to the device datasheet)
<> 144:ef7eb2e8f9f7 103 [..]
<> 144:ef7eb2e8f9f7 104 e.g. To set DAC_OUT1 to 0.7V, use
<> 144:ef7eb2e8f9f7 105 (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 *** DMA requests ***
<> 144:ef7eb2e8f9f7 108 =====================
<> 144:ef7eb2e8f9f7 109 [..]
<> 144:ef7eb2e8f9f7 110 A DMA1 request can be generated when an external trigger (but not
<> 144:ef7eb2e8f9f7 111 a software trigger) occurs if DMA1 requests are enabled using
<> 144:ef7eb2e8f9f7 112 HAL_DAC_Start_DMA()
<> 144:ef7eb2e8f9f7 113 [..]
<> 144:ef7eb2e8f9f7 114 DMA requests are mapped as following:
<> 144:ef7eb2e8f9f7 115 (#) DAC channel1 :
<> 144:ef7eb2e8f9f7 116 For STM32F100x low-density, medium-density, high-density with DAC
<> 144:ef7eb2e8f9f7 117 DMA remap:
<> 144:ef7eb2e8f9f7 118 mapped on DMA1 channel3 which must be
<> 144:ef7eb2e8f9f7 119 already configured
<> 144:ef7eb2e8f9f7 120 For STM32F100x high-density without DAC DMA remap and other
<> 144:ef7eb2e8f9f7 121 STM32F1 devices:
<> 144:ef7eb2e8f9f7 122 mapped on DMA2 channel3 which must be
<> 144:ef7eb2e8f9f7 123 already configured
<> 144:ef7eb2e8f9f7 124 (#) DAC channel2 :
<> 144:ef7eb2e8f9f7 125 For STM32F100x low-density, medium-density, high-density with DAC
<> 144:ef7eb2e8f9f7 126 DMA remap:
<> 144:ef7eb2e8f9f7 127 mapped on DMA1 channel4 which must be
<> 144:ef7eb2e8f9f7 128 already configured
<> 144:ef7eb2e8f9f7 129 For STM32F100x high-density without DAC DMA remap and other
<> 144:ef7eb2e8f9f7 130 STM32F1 devices:
<> 144:ef7eb2e8f9f7 131 mapped on DMA2 channel4 which must be
<> 144:ef7eb2e8f9f7 132 already configured
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 135 ==============================================================================
<> 144:ef7eb2e8f9f7 136 [..]
<> 144:ef7eb2e8f9f7 137 (+) DAC APB clock must be enabled to get write access to DAC
<> 144:ef7eb2e8f9f7 138 registers using HAL_DAC_Init()
<> 144:ef7eb2e8f9f7 139 (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
<> 144:ef7eb2e8f9f7 140 (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
<> 144:ef7eb2e8f9f7 141 (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 144 =================================
<> 144:ef7eb2e8f9f7 145 [..]
<> 144:ef7eb2e8f9f7 146 (+) Start the DAC peripheral using HAL_DAC_Start()
<> 144:ef7eb2e8f9f7 147 (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
<> 144:ef7eb2e8f9f7 148 (+) Stop the DAC peripheral using HAL_DAC_Stop()
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 151 ==============================
<> 144:ef7eb2e8f9f7 152 [..]
<> 144:ef7eb2e8f9f7 153 (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
<> 144:ef7eb2e8f9f7 154 of data to be transferred at each end of conversion
<> 144:ef7eb2e8f9f7 155 (+) At the middle of data transfer HAL_DACEx_ConvHalfCpltCallbackCh1()or HAL_DACEx_ConvHalfCpltCallbackCh2()
<> 144:ef7eb2e8f9f7 156 function is executed and user can add his own code by customization of function pointer
<> 144:ef7eb2e8f9f7 157 HAL_DAC_ConvHalfCpltCallbackCh1 or HAL_DAC_ConvHalfCpltCallbackCh2
<> 144:ef7eb2e8f9f7 158 (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
<> 144:ef7eb2e8f9f7 159 function is executed and user can add his own code by customization of function pointer
<> 144:ef7eb2e8f9f7 160 HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
<> 144:ef7eb2e8f9f7 161 (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() or HAL_DACEx_ErrorCallbackCh2() function is executed and user can
<> 144:ef7eb2e8f9f7 162 add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 or HAL_DACEx_ErrorCallbackCh2
<> 144:ef7eb2e8f9f7 163 (+) For STM32F100x devices with specific feature: DMA underrun.
<> 144:ef7eb2e8f9f7 164 In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
<> 144:ef7eb2e8f9f7 165 HAL_DAC_DMAUnderrunCallbackCh1()or HAL_DACEx_DMAUnderrunCallbackCh2()
<> 144:ef7eb2e8f9f7 166 function is executed and user can add his own code by customization of function pointer
<> 144:ef7eb2e8f9f7 167 HAL_DAC_DMAUnderrunCallbackCh1 or HAL_DACEx_DMAUnderrunCallbackCh2
<> 144:ef7eb2e8f9f7 168 add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
<> 144:ef7eb2e8f9f7 169 (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 *** DAC HAL driver macros list ***
<> 144:ef7eb2e8f9f7 172 =============================================
<> 144:ef7eb2e8f9f7 173 [..]
<> 144:ef7eb2e8f9f7 174 Below the list of most used macros in DAC HAL driver.
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 (+) __HAL_DAC_ENABLE : Enable the DAC peripheral (For STM32F100x devices with specific feature: DMA underrun)
<> 144:ef7eb2e8f9f7 177 (+) __HAL_DAC_DISABLE : Disable the DAC peripheral (For STM32F100x devices with specific feature: DMA underrun)
<> 144:ef7eb2e8f9f7 178 (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags (For STM32F100x devices with specific feature: DMA underrun)
<> 144:ef7eb2e8f9f7 179 (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status (For STM32F100x devices with specific feature: DMA underrun)
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 [..]
<> 144:ef7eb2e8f9f7 182 (@) You can refer to the DAC HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 @endverbatim
<> 144:ef7eb2e8f9f7 185 ******************************************************************************
<> 144:ef7eb2e8f9f7 186 * @attention
<> 144:ef7eb2e8f9f7 187 *
<> 144:ef7eb2e8f9f7 188 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 189 *
<> 144:ef7eb2e8f9f7 190 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 191 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 192 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 193 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 194 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 195 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 196 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 197 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 198 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 199 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 200 *
<> 144:ef7eb2e8f9f7 201 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 202 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 203 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 204 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 205 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 206 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 207 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 208 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 209 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 210 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 211 *
<> 144:ef7eb2e8f9f7 212 ******************************************************************************
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 217 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 220 * @{
<> 144:ef7eb2e8f9f7 221 */
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /** @defgroup DAC DAC
<> 144:ef7eb2e8f9f7 224 * @brief DAC driver modules
<> 144:ef7eb2e8f9f7 225 * @{
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 #ifdef HAL_DAC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 229 #if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 232 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 233 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 234 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 235 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 236 /* Exported functions -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /** @defgroup DAC_Exported_Functions DAC Exported Functions
<> 144:ef7eb2e8f9f7 239 * @{
<> 144:ef7eb2e8f9f7 240 */
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 243 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 244 *
<> 144:ef7eb2e8f9f7 245 @verbatim
<> 144:ef7eb2e8f9f7 246 ==============================================================================
<> 144:ef7eb2e8f9f7 247 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 248 ==============================================================================
<> 144:ef7eb2e8f9f7 249 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 250 (+) Initialize and configure the DAC.
<> 144:ef7eb2e8f9f7 251 (+) De-initialize the DAC.
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 @endverbatim
<> 144:ef7eb2e8f9f7 254 * @{
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /**
<> 144:ef7eb2e8f9f7 258 * @brief Initializes the DAC peripheral according to the specified parameters
<> 144:ef7eb2e8f9f7 259 * in the DAC_InitStruct.
<> 144:ef7eb2e8f9f7 260 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 261 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 262 * @retval HAL status
<> 144:ef7eb2e8f9f7 263 */
<> 144:ef7eb2e8f9f7 264 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 265 {
<> 144:ef7eb2e8f9f7 266 /* Check DAC handle */
<> 144:ef7eb2e8f9f7 267 if(hdac == NULL)
<> 144:ef7eb2e8f9f7 268 {
<> 144:ef7eb2e8f9f7 269 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 270 }
<> 144:ef7eb2e8f9f7 271 /* Check the parameters */
<> 144:ef7eb2e8f9f7 272 assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 if(hdac->State == HAL_DAC_STATE_RESET)
<> 144:ef7eb2e8f9f7 275 {
<> 144:ef7eb2e8f9f7 276 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 277 hdac->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 280 HAL_DAC_MspInit(hdac);
<> 144:ef7eb2e8f9f7 281 }
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /* Initialize the DAC state*/
<> 144:ef7eb2e8f9f7 284 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /* Set DAC error code to none */
<> 144:ef7eb2e8f9f7 287 hdac->ErrorCode = HAL_DAC_ERROR_NONE;
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /* Initialize the DAC state*/
<> 144:ef7eb2e8f9f7 290 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /* Return function status */
<> 144:ef7eb2e8f9f7 293 return HAL_OK;
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /**
<> 144:ef7eb2e8f9f7 297 * @brief Deinitializes the DAC peripheral registers to their default reset values.
<> 144:ef7eb2e8f9f7 298 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 299 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 300 * @retval HAL status
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 303 {
<> 144:ef7eb2e8f9f7 304 /* Check DAC handle */
<> 144:ef7eb2e8f9f7 305 if(hdac == NULL)
<> 144:ef7eb2e8f9f7 306 {
<> 144:ef7eb2e8f9f7 307 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 308 }
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /* Check the parameters */
<> 144:ef7eb2e8f9f7 311 assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /* Change DAC state */
<> 144:ef7eb2e8f9f7 314 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 317 HAL_DAC_MspDeInit(hdac);
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /* Set DAC error code to none */
<> 144:ef7eb2e8f9f7 320 hdac->ErrorCode = HAL_DAC_ERROR_NONE;
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* Change DAC state */
<> 144:ef7eb2e8f9f7 323 hdac->State = HAL_DAC_STATE_RESET;
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /* Release Lock */
<> 144:ef7eb2e8f9f7 326 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /* Return function status */
<> 144:ef7eb2e8f9f7 329 return HAL_OK;
<> 144:ef7eb2e8f9f7 330 }
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /**
<> 144:ef7eb2e8f9f7 333 * @brief Initializes the DAC MSP.
<> 144:ef7eb2e8f9f7 334 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 335 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 336 * @retval None
<> 144:ef7eb2e8f9f7 337 */
<> 144:ef7eb2e8f9f7 338 __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 339 {
<> 144:ef7eb2e8f9f7 340 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 341 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 342 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 343 the HAL_DAC_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345 }
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /**
<> 144:ef7eb2e8f9f7 348 * @brief DeInitializes the DAC MSP.
<> 144:ef7eb2e8f9f7 349 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 350 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 351 * @retval None
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 354 {
<> 144:ef7eb2e8f9f7 355 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 356 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 357 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 358 the HAL_DAC_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 359 */
<> 144:ef7eb2e8f9f7 360 }
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /**
<> 144:ef7eb2e8f9f7 363 * @}
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /** @defgroup DAC_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 367 * @brief IO operation functions
<> 144:ef7eb2e8f9f7 368 *
<> 144:ef7eb2e8f9f7 369 @verbatim
<> 144:ef7eb2e8f9f7 370 ==============================================================================
<> 144:ef7eb2e8f9f7 371 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 372 ==============================================================================
<> 144:ef7eb2e8f9f7 373 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 374 (+) Start conversion.
<> 144:ef7eb2e8f9f7 375 (+) Stop conversion.
<> 144:ef7eb2e8f9f7 376 (+) Start conversion and enable DMA transfer.
<> 144:ef7eb2e8f9f7 377 (+) Stop conversion and disable DMA transfer.
<> 144:ef7eb2e8f9f7 378 (+) Get result of conversion.
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 @endverbatim
<> 144:ef7eb2e8f9f7 381 * @{
<> 144:ef7eb2e8f9f7 382 */
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /**
<> 144:ef7eb2e8f9f7 385 * @brief Enables DAC and starts conversion of channel.
<> 144:ef7eb2e8f9f7 386 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 387 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 388 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 389 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 390 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 391 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 392 * @retval HAL status
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 395 {
<> 144:ef7eb2e8f9f7 396 /* Check the parameters */
<> 144:ef7eb2e8f9f7 397 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /* Process locked */
<> 144:ef7eb2e8f9f7 400 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 /* Change DAC state */
<> 144:ef7eb2e8f9f7 403 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 406 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 409 {
<> 144:ef7eb2e8f9f7 410 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 411 if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
<> 144:ef7eb2e8f9f7 412 {
<> 144:ef7eb2e8f9f7 413 /* Enable the selected DAC software conversion */
<> 144:ef7eb2e8f9f7 414 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
<> 144:ef7eb2e8f9f7 415 }
<> 144:ef7eb2e8f9f7 416 }
<> 144:ef7eb2e8f9f7 417 else
<> 144:ef7eb2e8f9f7 418 {
<> 144:ef7eb2e8f9f7 419 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 420 if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2))
<> 144:ef7eb2e8f9f7 421 {
<> 144:ef7eb2e8f9f7 422 /* Enable the selected DAC software conversion*/
<> 144:ef7eb2e8f9f7 423 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
<> 144:ef7eb2e8f9f7 424 }
<> 144:ef7eb2e8f9f7 425 }
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /* Change DAC state */
<> 144:ef7eb2e8f9f7 428 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /* Process unlocked */
<> 144:ef7eb2e8f9f7 431 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /* Return function status */
<> 144:ef7eb2e8f9f7 434 return HAL_OK;
<> 144:ef7eb2e8f9f7 435 }
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /**
<> 144:ef7eb2e8f9f7 438 * @brief Disables DAC and stop conversion of channel.
<> 144:ef7eb2e8f9f7 439 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 440 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 441 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 442 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 443 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 444 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 445 * @retval HAL status
<> 144:ef7eb2e8f9f7 446 */
<> 144:ef7eb2e8f9f7 447 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 448 {
<> 144:ef7eb2e8f9f7 449 /* Check the parameters */
<> 144:ef7eb2e8f9f7 450 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 453 __HAL_DAC_DISABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /* Change DAC state */
<> 144:ef7eb2e8f9f7 456 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /* Return function status */
<> 144:ef7eb2e8f9f7 459 return HAL_OK;
<> 144:ef7eb2e8f9f7 460 }
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /**
<> 144:ef7eb2e8f9f7 463 * @brief Enables DAC and starts conversion of channel.
<> 144:ef7eb2e8f9f7 464 * Note: For STM32F100x devices with specific feature: DMA underrun.
<> 144:ef7eb2e8f9f7 465 * On these devices, this function enables the interruption of DMA
<> 144:ef7eb2e8f9f7 466 * underrun.
<> 144:ef7eb2e8f9f7 467 * (refer to redefinition of this function in DAC extended file)
<> 144:ef7eb2e8f9f7 468 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 469 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 470 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 471 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 472 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 473 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 474 * @param pData: The destination peripheral Buffer address.
<> 144:ef7eb2e8f9f7 475 * @param Length: The length of data to be transferred from memory to DAC peripheral
<> 144:ef7eb2e8f9f7 476 * @param Alignment: Specifies the data alignment for DAC channel.
<> 144:ef7eb2e8f9f7 477 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 478 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 479 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 480 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 481 * @retval HAL status
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483 __weak HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
<> 144:ef7eb2e8f9f7 484 {
<> 144:ef7eb2e8f9f7 485 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /* Check the parameters */
<> 144:ef7eb2e8f9f7 488 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 489 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /* Process locked */
<> 144:ef7eb2e8f9f7 492 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /* Change DAC state */
<> 144:ef7eb2e8f9f7 495 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 498 {
<> 144:ef7eb2e8f9f7 499 /* Set the DMA transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 500 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /* Set the DMA half transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 503 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /* Set the DMA error callback for channel1 */
<> 144:ef7eb2e8f9f7 506 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /* Enable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 509 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /* Case of use of channel 1 */
<> 144:ef7eb2e8f9f7 512 switch(Alignment)
<> 144:ef7eb2e8f9f7 513 {
<> 144:ef7eb2e8f9f7 514 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 515 /* Get DHR12R1 address */
<> 144:ef7eb2e8f9f7 516 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
<> 144:ef7eb2e8f9f7 517 break;
<> 144:ef7eb2e8f9f7 518 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 519 /* Get DHR12L1 address */
<> 144:ef7eb2e8f9f7 520 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
<> 144:ef7eb2e8f9f7 521 break;
<> 144:ef7eb2e8f9f7 522 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 523 /* Get DHR8R1 address */
<> 144:ef7eb2e8f9f7 524 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
<> 144:ef7eb2e8f9f7 525 break;
<> 144:ef7eb2e8f9f7 526 default:
<> 144:ef7eb2e8f9f7 527 break;
<> 144:ef7eb2e8f9f7 528 }
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530 else
<> 144:ef7eb2e8f9f7 531 {
<> 144:ef7eb2e8f9f7 532 /* Set the DMA transfer complete callback for channel2 */
<> 144:ef7eb2e8f9f7 533 hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /* Set the DMA half transfer complete callback for channel2 */
<> 144:ef7eb2e8f9f7 536 hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /* Set the DMA error callback for channel2 */
<> 144:ef7eb2e8f9f7 539 hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /* Enable the selected DAC channel2 DMA request */
<> 144:ef7eb2e8f9f7 542 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /* Case of use of channel 2 */
<> 144:ef7eb2e8f9f7 545 switch(Alignment)
<> 144:ef7eb2e8f9f7 546 {
<> 144:ef7eb2e8f9f7 547 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 548 /* Get DHR12R2 address */
<> 144:ef7eb2e8f9f7 549 tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
<> 144:ef7eb2e8f9f7 550 break;
<> 144:ef7eb2e8f9f7 551 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 552 /* Get DHR12L2 address */
<> 144:ef7eb2e8f9f7 553 tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
<> 144:ef7eb2e8f9f7 554 break;
<> 144:ef7eb2e8f9f7 555 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 556 /* Get DHR8R2 address */
<> 144:ef7eb2e8f9f7 557 tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
<> 144:ef7eb2e8f9f7 558 break;
<> 144:ef7eb2e8f9f7 559 default:
<> 144:ef7eb2e8f9f7 560 break;
<> 144:ef7eb2e8f9f7 561 }
<> 144:ef7eb2e8f9f7 562 }
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 565 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 566 {
<> 144:ef7eb2e8f9f7 567 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 568 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 569 }
<> 144:ef7eb2e8f9f7 570 else
<> 144:ef7eb2e8f9f7 571 {
<> 144:ef7eb2e8f9f7 572 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 573 HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 574 }
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 577 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 580 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 /* Return function status */
<> 144:ef7eb2e8f9f7 583 return HAL_OK;
<> 144:ef7eb2e8f9f7 584 }
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /**
<> 144:ef7eb2e8f9f7 587 * @brief Disables DAC and stop conversion of channel.
<> 144:ef7eb2e8f9f7 588 * Note: For STM32F100x devices with specific feature: DMA underrun.
<> 144:ef7eb2e8f9f7 589 * On these devices, this function disables the interruption of DMA
<> 144:ef7eb2e8f9f7 590 * underrun.
<> 144:ef7eb2e8f9f7 591 * (refer to redefinition of this function in DAC extended file)
<> 144:ef7eb2e8f9f7 592 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 593 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 594 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 595 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 596 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 597 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 598 * @retval HAL status
<> 144:ef7eb2e8f9f7 599 */
<> 144:ef7eb2e8f9f7 600 __weak HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 601 {
<> 144:ef7eb2e8f9f7 602 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /* Check the parameters */
<> 144:ef7eb2e8f9f7 605 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /* Disable the selected DAC channel DMA request */
<> 144:ef7eb2e8f9f7 608 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1 << Channel);
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /* Disable the Peripharal */
<> 144:ef7eb2e8f9f7 611 __HAL_DAC_DISABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 /* Disable the DMA Channel */
<> 144:ef7eb2e8f9f7 614 /* Channel1 is used */
<> 144:ef7eb2e8f9f7 615 if (Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 616 {
<> 144:ef7eb2e8f9f7 617 status = HAL_DMA_Abort(hdac->DMA_Handle1);
<> 144:ef7eb2e8f9f7 618 }
<> 144:ef7eb2e8f9f7 619 else /* Channel2 is used for */
<> 144:ef7eb2e8f9f7 620 {
<> 144:ef7eb2e8f9f7 621 status = HAL_DMA_Abort(hdac->DMA_Handle2);
<> 144:ef7eb2e8f9f7 622 }
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* Check if DMA Channel effectively disabled */
<> 144:ef7eb2e8f9f7 625 if (status != HAL_OK)
<> 144:ef7eb2e8f9f7 626 {
<> 144:ef7eb2e8f9f7 627 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 628 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 629 }
<> 144:ef7eb2e8f9f7 630 else
<> 144:ef7eb2e8f9f7 631 {
<> 144:ef7eb2e8f9f7 632 /* Change DAC state */
<> 144:ef7eb2e8f9f7 633 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 634 }
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /* Return function status */
<> 144:ef7eb2e8f9f7 637 return status;
<> 144:ef7eb2e8f9f7 638 }
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /**
<> 144:ef7eb2e8f9f7 641 * @brief Returns the last data output value of the selected DAC channel.
<> 144:ef7eb2e8f9f7 642 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 643 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 644 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 645 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 646 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 647 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 648 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 649 */
<> 144:ef7eb2e8f9f7 650 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 651 {
<> 144:ef7eb2e8f9f7 652 /* Check the parameters */
<> 144:ef7eb2e8f9f7 653 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 /* Returns the DAC channel data output register value */
<> 144:ef7eb2e8f9f7 656 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 657 {
<> 144:ef7eb2e8f9f7 658 return hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 659 }
<> 144:ef7eb2e8f9f7 660 else
<> 144:ef7eb2e8f9f7 661 {
<> 144:ef7eb2e8f9f7 662 return hdac->Instance->DOR2;
<> 144:ef7eb2e8f9f7 663 }
<> 144:ef7eb2e8f9f7 664 }
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /**
<> 144:ef7eb2e8f9f7 667 * @brief Conversion complete callback in non blocking mode for Channel1
<> 144:ef7eb2e8f9f7 668 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 669 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 670 * @retval None
<> 144:ef7eb2e8f9f7 671 */
<> 144:ef7eb2e8f9f7 672 __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 673 {
<> 144:ef7eb2e8f9f7 674 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 675 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 676 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 677 the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
<> 144:ef7eb2e8f9f7 678 */
<> 144:ef7eb2e8f9f7 679 }
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /**
<> 144:ef7eb2e8f9f7 682 * @brief Conversion half DMA transfer callback in non blocking mode for Channel1
<> 144:ef7eb2e8f9f7 683 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 684 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 685 * @retval None
<> 144:ef7eb2e8f9f7 686 */
<> 144:ef7eb2e8f9f7 687 __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 688 {
<> 144:ef7eb2e8f9f7 689 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 690 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 691 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 692 the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
<> 144:ef7eb2e8f9f7 693 */
<> 144:ef7eb2e8f9f7 694 }
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 /**
<> 144:ef7eb2e8f9f7 697 * @brief Error DAC callback for Channel1.
<> 144:ef7eb2e8f9f7 698 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 699 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 700 * @retval None
<> 144:ef7eb2e8f9f7 701 */
<> 144:ef7eb2e8f9f7 702 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 703 {
<> 144:ef7eb2e8f9f7 704 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 705 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 706 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 707 the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
<> 144:ef7eb2e8f9f7 708 */
<> 144:ef7eb2e8f9f7 709 }
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 /**
<> 144:ef7eb2e8f9f7 712 * @}
<> 144:ef7eb2e8f9f7 713 */
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 716 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 717 *
<> 144:ef7eb2e8f9f7 718 @verbatim
<> 144:ef7eb2e8f9f7 719 ==============================================================================
<> 144:ef7eb2e8f9f7 720 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 721 ==============================================================================
<> 144:ef7eb2e8f9f7 722 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 723 (+) Configure channels.
<> 144:ef7eb2e8f9f7 724 (+) Set the specified data holding register value for DAC channel.
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 @endverbatim
<> 144:ef7eb2e8f9f7 727 * @{
<> 144:ef7eb2e8f9f7 728 */
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 /**
<> 144:ef7eb2e8f9f7 731 * @brief Configures the selected DAC channel.
<> 144:ef7eb2e8f9f7 732 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 733 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 734 * @param sConfig: DAC configuration structure.
<> 144:ef7eb2e8f9f7 735 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 736 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 737 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 738 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 739 * @retval HAL status
<> 144:ef7eb2e8f9f7 740 */
<> 144:ef7eb2e8f9f7 741 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 742 {
<> 144:ef7eb2e8f9f7 743 uint32_t tmpreg1 = 0;
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 /* Check the DAC parameters */
<> 144:ef7eb2e8f9f7 746 assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
<> 144:ef7eb2e8f9f7 747 assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
<> 144:ef7eb2e8f9f7 748 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /* Process locked */
<> 144:ef7eb2e8f9f7 751 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /* Change DAC state */
<> 144:ef7eb2e8f9f7 754 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 /* Configure for the selected DAC channel: buffer output, trigger */
<> 144:ef7eb2e8f9f7 757 /* Set TSELx and TENx bits according to DAC_Trigger value */
<> 144:ef7eb2e8f9f7 758 /* Set BOFFx bit according to DAC_OutputBuffer value */
<> 144:ef7eb2e8f9f7 759 SET_BIT(tmpreg1, (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer));
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
<> 144:ef7eb2e8f9f7 762 /* Calculate CR register value depending on DAC_Channel */
<> 144:ef7eb2e8f9f7 763 MODIFY_REG(hdac->Instance->CR,
<> 144:ef7eb2e8f9f7 764 ((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel,
<> 144:ef7eb2e8f9f7 765 tmpreg1 << Channel);
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /* Disable wave generation */
<> 144:ef7eb2e8f9f7 768 hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 /* Change DAC state */
<> 144:ef7eb2e8f9f7 771 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 /* Process unlocked */
<> 144:ef7eb2e8f9f7 774 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 /* Return function status */
<> 144:ef7eb2e8f9f7 777 return HAL_OK;
<> 144:ef7eb2e8f9f7 778 }
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 /**
<> 144:ef7eb2e8f9f7 781 * @brief Set the specified data holding register value for DAC channel.
<> 144:ef7eb2e8f9f7 782 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 783 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 784 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 785 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 786 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 787 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 788 * @param Alignment: Specifies the data alignment.
<> 144:ef7eb2e8f9f7 789 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 790 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 791 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 792 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 793 * @param Data: Data to be loaded in the selected data holding register.
<> 144:ef7eb2e8f9f7 794 * @retval HAL status
<> 144:ef7eb2e8f9f7 795 */
<> 144:ef7eb2e8f9f7 796 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
<> 144:ef7eb2e8f9f7 797 {
<> 144:ef7eb2e8f9f7 798 __IO uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 /* Check the parameters */
<> 144:ef7eb2e8f9f7 801 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 802 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 803 assert_param(IS_DAC_DATA(Data));
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 tmp = (uint32_t)hdac->Instance;
<> 144:ef7eb2e8f9f7 806 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 807 {
<> 144:ef7eb2e8f9f7 808 tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
<> 144:ef7eb2e8f9f7 809 }
<> 144:ef7eb2e8f9f7 810 else
<> 144:ef7eb2e8f9f7 811 {
<> 144:ef7eb2e8f9f7 812 tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
<> 144:ef7eb2e8f9f7 813 }
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 /* Set the DAC channel selected data holding register */
<> 144:ef7eb2e8f9f7 816 *(__IO uint32_t *) tmp = Data;
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 /* Return function status */
<> 144:ef7eb2e8f9f7 819 return HAL_OK;
<> 144:ef7eb2e8f9f7 820 }
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /**
<> 144:ef7eb2e8f9f7 823 * @}
<> 144:ef7eb2e8f9f7 824 */
<> 144:ef7eb2e8f9f7 825
<> 144:ef7eb2e8f9f7 826 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 827 * @brief Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 828 *
<> 144:ef7eb2e8f9f7 829 @verbatim
<> 144:ef7eb2e8f9f7 830 ==============================================================================
<> 144:ef7eb2e8f9f7 831 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 832 ==============================================================================
<> 144:ef7eb2e8f9f7 833 [..]
<> 144:ef7eb2e8f9f7 834 This subsection provides functions allowing to
<> 144:ef7eb2e8f9f7 835 (+) Check the DAC state.
<> 144:ef7eb2e8f9f7 836 (+) Check the DAC Errors.
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 @endverbatim
<> 144:ef7eb2e8f9f7 839 * @{
<> 144:ef7eb2e8f9f7 840 */
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 /**
<> 144:ef7eb2e8f9f7 843 * @brief return the DAC state
<> 144:ef7eb2e8f9f7 844 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 845 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 846 * @retval HAL state
<> 144:ef7eb2e8f9f7 847 */
<> 144:ef7eb2e8f9f7 848 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 849 {
<> 144:ef7eb2e8f9f7 850 /* Return DAC state */
<> 144:ef7eb2e8f9f7 851 return hdac->State;
<> 144:ef7eb2e8f9f7 852 }
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 /**
<> 144:ef7eb2e8f9f7 856 * @brief Return the DAC error code
<> 144:ef7eb2e8f9f7 857 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 858 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 859 * @retval DAC Error Code
<> 144:ef7eb2e8f9f7 860 */
<> 144:ef7eb2e8f9f7 861 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 862 {
<> 144:ef7eb2e8f9f7 863 return hdac->ErrorCode;
<> 144:ef7eb2e8f9f7 864 }
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 /**
<> 144:ef7eb2e8f9f7 867 * @}
<> 144:ef7eb2e8f9f7 868 */
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 /**
<> 144:ef7eb2e8f9f7 871 * @}
<> 144:ef7eb2e8f9f7 872 */
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /** @addtogroup DAC_Private_Functions
<> 144:ef7eb2e8f9f7 875 * @{
<> 144:ef7eb2e8f9f7 876 */
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 /**
<> 144:ef7eb2e8f9f7 879 * @brief DMA conversion complete callback.
<> 144:ef7eb2e8f9f7 880 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 881 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 882 * @retval None
<> 144:ef7eb2e8f9f7 883 */
<> 144:ef7eb2e8f9f7 884 void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 885 {
<> 144:ef7eb2e8f9f7 886 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 HAL_DAC_ConvCpltCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 891 }
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 /**
<> 144:ef7eb2e8f9f7 894 * @brief DMA half transfer complete callback.
<> 144:ef7eb2e8f9f7 895 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 896 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 897 * @retval None
<> 144:ef7eb2e8f9f7 898 */
<> 144:ef7eb2e8f9f7 899 void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 900 {
<> 144:ef7eb2e8f9f7 901 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 902 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 903 HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 904 }
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906 /**
<> 144:ef7eb2e8f9f7 907 * @brief DMA error callback
<> 144:ef7eb2e8f9f7 908 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 909 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 910 * @retval None
<> 144:ef7eb2e8f9f7 911 */
<> 144:ef7eb2e8f9f7 912 void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 913 {
<> 144:ef7eb2e8f9f7 914 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 915
<> 144:ef7eb2e8f9f7 916 /* Set DAC error code to DMA error */
<> 144:ef7eb2e8f9f7 917 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 HAL_DAC_ErrorCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 922 }
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /**
<> 144:ef7eb2e8f9f7 925 * @}
<> 144:ef7eb2e8f9f7 926 */
<> 144:ef7eb2e8f9f7 927
<> 144:ef7eb2e8f9f7 928 #endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 929 #endif /* HAL_DAC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 930
<> 144:ef7eb2e8f9f7 931 /**
<> 144:ef7eb2e8f9f7 932 * @}
<> 144:ef7eb2e8f9f7 933 */
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /**
<> 144:ef7eb2e8f9f7 936 * @}
<> 144:ef7eb2e8f9f7 937 */
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/