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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.c@167:356ef919c855, 2017-06-20 (annotated)

Committer:
kkado
Date:
Tue Jun 20 11:06:37 2017 +0000
Revision:
167:356ef919c855
Parent:
149:156823d33999 
Build 137 with reduced HSE timeout

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_ll_spi.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.1
<> 144:ef7eb2e8f9f7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief SPI LL module driver.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37 #if defined(USE_FULL_LL_DRIVER)
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 40 #include "stm32l4xx_ll_spi.h"
<> 144:ef7eb2e8f9f7 41 #include "stm32l4xx_ll_bus.h"
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 #ifdef USE_FULL_ASSERT
<> 144:ef7eb2e8f9f7 44 #include "stm32_assert.h"
<> 144:ef7eb2e8f9f7 45 #else
<> 144:ef7eb2e8f9f7 46 #define assert_param(expr) ((void)0U)
<> 144:ef7eb2e8f9f7 47 #endif
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32L4xx_LL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @addtogroup SPI_LL
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 63 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
<> 144:ef7eb2e8f9f7 64 * @{
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 /* SPI registers Masks */
<> 144:ef7eb2e8f9f7 67 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
<> 144:ef7eb2e8f9f7 68 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
<> 144:ef7eb2e8f9f7 69 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
<> 144:ef7eb2e8f9f7 70 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
<> 144:ef7eb2e8f9f7 71 SPI_CR1_BIDIMODE)
<> 144:ef7eb2e8f9f7 72 /**
<> 144:ef7eb2e8f9f7 73 * @}
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 77 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
<> 144:ef7eb2e8f9f7 78 * @{
<> 144:ef7eb2e8f9f7 79 */
<> 144:ef7eb2e8f9f7 80 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
<> 144:ef7eb2e8f9f7 81 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
<> 144:ef7eb2e8f9f7 82 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
<> 144:ef7eb2e8f9f7 83 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
<> 144:ef7eb2e8f9f7 86 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
<> 144:ef7eb2e8f9f7 89 || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
<> 144:ef7eb2e8f9f7 90 || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
<> 144:ef7eb2e8f9f7 91 || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
<> 144:ef7eb2e8f9f7 92 || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
<> 144:ef7eb2e8f9f7 93 || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
<> 144:ef7eb2e8f9f7 94 || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
<> 144:ef7eb2e8f9f7 95 || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
<> 144:ef7eb2e8f9f7 96 || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
<> 144:ef7eb2e8f9f7 97 || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
<> 144:ef7eb2e8f9f7 98 || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
<> 144:ef7eb2e8f9f7 99 || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
<> 144:ef7eb2e8f9f7 100 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
<> 144:ef7eb2e8f9f7 103 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
<> 144:ef7eb2e8f9f7 106 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
<> 144:ef7eb2e8f9f7 109 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
<> 144:ef7eb2e8f9f7 110 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
<> 144:ef7eb2e8f9f7 113 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
<> 144:ef7eb2e8f9f7 114 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
<> 144:ef7eb2e8f9f7 115 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
<> 144:ef7eb2e8f9f7 116 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
<> 144:ef7eb2e8f9f7 117 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
<> 144:ef7eb2e8f9f7 118 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
<> 144:ef7eb2e8f9f7 119 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
<> 144:ef7eb2e8f9f7 122 || ((__VALUE__) == LL_SPI_MSB_FIRST))
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
<> 144:ef7eb2e8f9f7 125 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /**
<> 144:ef7eb2e8f9f7 130 * @}
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 136 /** @addtogroup SPI_LL_Exported_Functions
<> 144:ef7eb2e8f9f7 137 * @{
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /** @addtogroup SPI_LL_EF_Init
<> 144:ef7eb2e8f9f7 141 * @{
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /**
<> 144:ef7eb2e8f9f7 145 * @brief De-initialize the SPI registers to their default reset values.
<> 144:ef7eb2e8f9f7 146 * @param SPIx SPI Instance
<> 144:ef7eb2e8f9f7 147 * @retval An ErrorStatus enumeration value:
<> 144:ef7eb2e8f9f7 148 * - SUCCESS: SPI registers are de-initialized
<> 144:ef7eb2e8f9f7 149 * - ERROR: SPI registers are not de-initialized
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
<> 144:ef7eb2e8f9f7 152 {
<> 144:ef7eb2e8f9f7 153 ErrorStatus status = ERROR;
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /* Check the parameters */
<> 144:ef7eb2e8f9f7 156 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 #if defined(SPI1)
<> 144:ef7eb2e8f9f7 159 if (SPIx == SPI1)
<> 144:ef7eb2e8f9f7 160 {
<> 144:ef7eb2e8f9f7 161 /* Force reset of SPI clock */
<> 144:ef7eb2e8f9f7 162 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* Release reset of SPI clock */
<> 144:ef7eb2e8f9f7 165 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 status = SUCCESS;
<> 144:ef7eb2e8f9f7 168 }
<> 144:ef7eb2e8f9f7 169 #endif /* SPI1 */
<> 144:ef7eb2e8f9f7 170 #if defined(SPI2)
<> 144:ef7eb2e8f9f7 171 if (SPIx == SPI2)
<> 144:ef7eb2e8f9f7 172 {
<> 144:ef7eb2e8f9f7 173 /* Force reset of SPI clock */
<> 144:ef7eb2e8f9f7 174 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /* Release reset of SPI clock */
<> 144:ef7eb2e8f9f7 177 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 status = SUCCESS;
<> 144:ef7eb2e8f9f7 180 }
<> 144:ef7eb2e8f9f7 181 #endif /* SPI2 */
<> 144:ef7eb2e8f9f7 182 #if defined(SPI3)
<> 144:ef7eb2e8f9f7 183 if (SPIx == SPI3)
<> 144:ef7eb2e8f9f7 184 {
<> 144:ef7eb2e8f9f7 185 /* Force reset of SPI clock */
<> 144:ef7eb2e8f9f7 186 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /* Release reset of SPI clock */
<> 144:ef7eb2e8f9f7 189 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 status = SUCCESS;
<> 144:ef7eb2e8f9f7 192 }
<> 144:ef7eb2e8f9f7 193 #endif /* SPI3 */
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 return status;
<> 144:ef7eb2e8f9f7 196 }
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /**
<> 144:ef7eb2e8f9f7 199 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
<> 144:ef7eb2e8f9f7 200 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
<> 144:ef7eb2e8f9f7 201 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
<> 144:ef7eb2e8f9f7 202 * @param SPIx SPI Instance
<> 144:ef7eb2e8f9f7 203 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
<> 144:ef7eb2e8f9f7 204 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
<> 144:ef7eb2e8f9f7 205 */
<> 144:ef7eb2e8f9f7 206 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
<> 144:ef7eb2e8f9f7 207 {
<> 144:ef7eb2e8f9f7 208 ErrorStatus status = ERROR;
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /* Check the SPI Instance SPIx*/
<> 144:ef7eb2e8f9f7 211 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* Check the SPI parameters from SPI_InitStruct*/
<> 144:ef7eb2e8f9f7 214 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
<> 144:ef7eb2e8f9f7 215 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
<> 144:ef7eb2e8f9f7 216 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
<> 144:ef7eb2e8f9f7 217 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
<> 144:ef7eb2e8f9f7 218 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
<> 144:ef7eb2e8f9f7 219 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
<> 144:ef7eb2e8f9f7 220 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
<> 144:ef7eb2e8f9f7 221 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
<> 144:ef7eb2e8f9f7 222 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
<> 144:ef7eb2e8f9f7 225 {
<> 144:ef7eb2e8f9f7 226 /*---------------------------- SPIx CR1 Configuration ------------------------
<> 144:ef7eb2e8f9f7 227 * Configure SPIx CR1 with parameters:
<> 144:ef7eb2e8f9f7 228 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
<> 144:ef7eb2e8f9f7 229 * - Master/Slave Mode: SPI_CR1_MSTR bit
<> 144:ef7eb2e8f9f7 230 * - ClockPolarity: SPI_CR1_CPOL bit
<> 144:ef7eb2e8f9f7 231 * - ClockPhase: SPI_CR1_CPHA bit
<> 144:ef7eb2e8f9f7 232 * - NSS management: SPI_CR1_SSM bit
<> 144:ef7eb2e8f9f7 233 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
<> 144:ef7eb2e8f9f7 234 * - BitOrder: SPI_CR1_LSBFIRST bit
<> 144:ef7eb2e8f9f7 235 * - CRCCalculation: SPI_CR1_CRCEN bit
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237 MODIFY_REG(SPIx->CR1,
<> 144:ef7eb2e8f9f7 238 SPI_CR1_CLEAR_MASK,
<> 144:ef7eb2e8f9f7 239 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
<> 144:ef7eb2e8f9f7 240 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
<> 144:ef7eb2e8f9f7 241 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
<> 144:ef7eb2e8f9f7 242 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /*---------------------------- SPIx CR2 Configuration ------------------------
<> 144:ef7eb2e8f9f7 245 * Configure SPIx CR2 with parameters:
<> 144:ef7eb2e8f9f7 246 * - DataWidth: DS[3:0] bits
<> 144:ef7eb2e8f9f7 247 * - NSS management: SSOE bit
<> 144:ef7eb2e8f9f7 248 */
<> 144:ef7eb2e8f9f7 249 MODIFY_REG(SPIx->CR2,
<> 144:ef7eb2e8f9f7 250 SPI_CR2_DS | SPI_CR2_SSOE,
<> 144:ef7eb2e8f9f7 251 SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /*---------------------------- SPIx CRCPR Configuration ----------------------
<> 144:ef7eb2e8f9f7 254 * Configure SPIx CRCPR with parameters:
<> 144:ef7eb2e8f9f7 255 * - CRCPoly: CRCPOLY[15:0] bits
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 258 {
<> 144:ef7eb2e8f9f7 259 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
<> 144:ef7eb2e8f9f7 260 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
<> 144:ef7eb2e8f9f7 261 }
<> 144:ef7eb2e8f9f7 262 status = SUCCESS;
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 return status;
<> 144:ef7eb2e8f9f7 266 }
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /**
<> 144:ef7eb2e8f9f7 269 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
<> 144:ef7eb2e8f9f7 270 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
<> 144:ef7eb2e8f9f7 271 * whose fields will be set to default values.
<> 144:ef7eb2e8f9f7 272 * @retval None
<> 144:ef7eb2e8f9f7 273 */
<> 144:ef7eb2e8f9f7 274 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
<> 144:ef7eb2e8f9f7 275 {
<> 144:ef7eb2e8f9f7 276 /* Set SPI_InitStruct fields to default values */
<> 144:ef7eb2e8f9f7 277 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
<> 144:ef7eb2e8f9f7 278 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
<> 144:ef7eb2e8f9f7 279 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
<> 144:ef7eb2e8f9f7 280 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
<> 144:ef7eb2e8f9f7 281 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
<> 144:ef7eb2e8f9f7 282 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
<> 144:ef7eb2e8f9f7 283 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
<> 144:ef7eb2e8f9f7 284 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
<> 144:ef7eb2e8f9f7 285 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
<> 144:ef7eb2e8f9f7 286 SPI_InitStruct->CRCPoly = 7U;
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /**
<> 144:ef7eb2e8f9f7 290 * @}
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /**
<> 144:ef7eb2e8f9f7 294 * @}
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /**
<> 144:ef7eb2e8f9f7 298 * @}
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /**
<> 144:ef7eb2e8f9f7 304 * @}
<> 144:ef7eb2e8f9f7 305 */
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 #endif /* USE_FULL_LL_DRIVER */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/