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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.h@167:356ef919c855, 2017-06-20 (annotated)

Committer:
kkado
Date:
Tue Jun 20 11:06:37 2017 +0000
Revision:
167:356ef919c855
Parent:
154:37f96f9d4de2
Child:
165:e614a9f1c9e2
Build 137 with reduced HSE timeout

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_adc.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 154:37f96f9d4de2 5 * @version V1.0.5
<> 154:37f96f9d4de2 6 * @date 06-December-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file containing functions prototypes of ADC HAL library.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F1xx_HAL_ADC_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F1xx_HAL_ADC_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 49 * @{
<> 144:ef7eb2e8f9f7 50 */
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /** @addtogroup ADC
<> 144:ef7eb2e8f9f7 53 * @{
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 57 /** @defgroup ADC_Exported_Types ADC Exported Types
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /**
<> 144:ef7eb2e8f9f7 62 * @brief Structure definition of ADC and regular group initialization
<> 144:ef7eb2e8f9f7 63 * @note Parameters of this structure are shared within 2 scopes:
<> 144:ef7eb2e8f9f7 64 * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
<> 144:ef7eb2e8f9f7 65 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
<> 144:ef7eb2e8f9f7 66 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 67 * ADC can be either disabled or enabled without conversion on going on regular group.
<> 144:ef7eb2e8f9f7 68 */
<> 144:ef7eb2e8f9f7 69 typedef struct
<> 144:ef7eb2e8f9f7 70 {
<> 144:ef7eb2e8f9f7 71 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
<> 144:ef7eb2e8f9f7 72 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
<> 144:ef7eb2e8f9f7 73 This parameter can be a value of @ref ADC_Data_align */
<> 144:ef7eb2e8f9f7 74 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
<> 144:ef7eb2e8f9f7 75 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
<> 144:ef7eb2e8f9f7 76 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
<> 144:ef7eb2e8f9f7 77 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
<> 144:ef7eb2e8f9f7 78 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
<> 144:ef7eb2e8f9f7 79 Scan direction is upward: from rank1 to rank 'n'.
<> 144:ef7eb2e8f9f7 80 This parameter can be a value of @ref ADC_Scan_mode
<> 144:ef7eb2e8f9f7 81 Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1)
<> 144:ef7eb2e8f9f7 82 or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
<> 144:ef7eb2e8f9f7 83 the last conversion of the sequence. All previous conversions would be overwritten by the last one.
<> 144:ef7eb2e8f9f7 84 Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
<> 144:ef7eb2e8f9f7 85 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
<> 144:ef7eb2e8f9f7 86 after the selected trigger occurred (software start or external trigger).
<> 144:ef7eb2e8f9f7 87 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 88 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
<> 144:ef7eb2e8f9f7 89 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<> 144:ef7eb2e8f9f7 90 This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
<> 144:ef7eb2e8f9f7 91 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
<> 144:ef7eb2e8f9f7 92 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
<> 144:ef7eb2e8f9f7 93 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
<> 144:ef7eb2e8f9f7 94 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 95 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
<> 144:ef7eb2e8f9f7 96 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
<> 144:ef7eb2e8f9f7 97 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
<> 144:ef7eb2e8f9f7 98 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
<> 144:ef7eb2e8f9f7 99 If set to ADC_SOFTWARE_START, external triggers are disabled.
<> 144:ef7eb2e8f9f7 100 If set to external trigger source, triggering is on event rising edge.
<> 144:ef7eb2e8f9f7 101 This parameter can be a value of @ref ADC_External_trigger_source_Regular */
<> 144:ef7eb2e8f9f7 102 }ADC_InitTypeDef;
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /**
<> 144:ef7eb2e8f9f7 105 * @brief Structure definition of ADC channel for regular group
<> 144:ef7eb2e8f9f7 106 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 107 * ADC can be either disabled or enabled without conversion on going on regular group.
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109 typedef struct
<> 144:ef7eb2e8f9f7 110 {
<> 144:ef7eb2e8f9f7 111 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
<> 144:ef7eb2e8f9f7 112 This parameter can be a value of @ref ADC_channels
<> 144:ef7eb2e8f9f7 113 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
<> 144:ef7eb2e8f9f7 114 Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
<> 144:ef7eb2e8f9f7 115 Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
<> 144:ef7eb2e8f9f7 116 It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
<> 144:ef7eb2e8f9f7 117 Refer to errata sheet of these devices for more details. */
<> 144:ef7eb2e8f9f7 118 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer
<> 144:ef7eb2e8f9f7 119 This parameter can be a value of @ref ADC_regular_rank
<> 144:ef7eb2e8f9f7 120 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
<> 144:ef7eb2e8f9f7 121 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
<> 144:ef7eb2e8f9f7 122 Unit: ADC clock cycles
<> 144:ef7eb2e8f9f7 123 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
<> 144:ef7eb2e8f9f7 124 This parameter can be a value of @ref ADC_sampling_times
<> 144:ef7eb2e8f9f7 125 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
<> 144:ef7eb2e8f9f7 126 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
<> 144:ef7eb2e8f9f7 127 Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
<> 144:ef7eb2e8f9f7 128 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
<> 144:ef7eb2e8f9f7 129 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
<> 144:ef7eb2e8f9f7 130 }ADC_ChannelConfTypeDef;
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /**
<> 144:ef7eb2e8f9f7 133 * @brief ADC Configuration analog watchdog definition
<> 144:ef7eb2e8f9f7 134 * @note The setting of these parameters with function is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 135 * ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137 typedef struct
<> 144:ef7eb2e8f9f7 138 {
<> 144:ef7eb2e8f9f7 139 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
<> 144:ef7eb2e8f9f7 140 This parameter can be a value of @ref ADC_analog_watchdog_mode. */
<> 144:ef7eb2e8f9f7 141 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
<> 144:ef7eb2e8f9f7 142 This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
<> 144:ef7eb2e8f9f7 143 This parameter can be a value of @ref ADC_channels. */
<> 144:ef7eb2e8f9f7 144 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
<> 144:ef7eb2e8f9f7 145 This parameter can be set to ENABLE or DISABLE */
<> 144:ef7eb2e8f9f7 146 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<> 144:ef7eb2e8f9f7 147 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
<> 144:ef7eb2e8f9f7 148 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<> 144:ef7eb2e8f9f7 149 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
<> 144:ef7eb2e8f9f7 150 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
<> 144:ef7eb2e8f9f7 151 }ADC_AnalogWDGConfTypeDef;
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /**
<> 144:ef7eb2e8f9f7 154 * @brief HAL ADC state machine: ADC states definition (bitfields)
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156 /* States of ADC global scope */
<> 144:ef7eb2e8f9f7 157 #define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
<> 144:ef7eb2e8f9f7 158 #define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
<> 144:ef7eb2e8f9f7 159 #define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */
<> 144:ef7eb2e8f9f7 160 #define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /* States of ADC errors */
<> 144:ef7eb2e8f9f7 163 #define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
<> 144:ef7eb2e8f9f7 164 #define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
<> 144:ef7eb2e8f9f7 165 #define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /* States of ADC group regular */
<> 144:ef7eb2e8f9f7 168 #define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
<> 144:ef7eb2e8f9f7 169 external trigger, low power auto power-on, multimode ADC master control) */
<> 144:ef7eb2e8f9f7 170 #define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
<> 144:ef7eb2e8f9f7 171 #define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Not available on STM32F1 device: Overrun occurrence */
<> 144:ef7eb2e8f9f7 172 #define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32F1 device: End Of Sampling flag raised */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /* States of ADC group injected */
<> 144:ef7eb2e8f9f7 175 #define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
<> 144:ef7eb2e8f9f7 176 external trigger, low power auto power-on, multimode ADC master control) */
<> 144:ef7eb2e8f9f7 177 #define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */
<> 144:ef7eb2e8f9f7 178 #define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32F1 device: Injected queue overflow occurrence */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* States of ADC analog watchdogs */
<> 144:ef7eb2e8f9f7 181 #define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */
<> 144:ef7eb2e8f9f7 182 #define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */
<> 144:ef7eb2e8f9f7 183 #define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /* States of ADC multi-mode */
<> 144:ef7eb2e8f9f7 186 #define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< ADC in multimode slave state, controlled by another ADC master ( */
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /**
<> 144:ef7eb2e8f9f7 190 * @brief ADC handle Structure definition
<> 144:ef7eb2e8f9f7 191 */
<> 144:ef7eb2e8f9f7 192 typedef struct
<> 144:ef7eb2e8f9f7 193 {
<> 144:ef7eb2e8f9f7 194 ADC_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 ADC_InitTypeDef Init; /*!< ADC required parameters */
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 HAL_LockTypeDef Lock; /*!< ADC locking object */
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 __IO uint32_t ErrorCode; /*!< ADC Error code */
<> 144:ef7eb2e8f9f7 205 }ADC_HandleTypeDef;
<> 144:ef7eb2e8f9f7 206 /**
<> 144:ef7eb2e8f9f7 207 * @}
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /** @defgroup ADC_Exported_Constants ADC Exported Constants
<> 144:ef7eb2e8f9f7 215 * @{
<> 144:ef7eb2e8f9f7 216 */
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /** @defgroup ADC_Error_Code ADC Error Code
<> 144:ef7eb2e8f9f7 219 * @{
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221 #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
<> 144:ef7eb2e8f9f7 222 #define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
<> 144:ef7eb2e8f9f7 223 enable/disable, erroneous state */
<> 144:ef7eb2e8f9f7 224 #define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */
<> 144:ef7eb2e8f9f7 225 #define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /**
<> 144:ef7eb2e8f9f7 228 * @}
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /** @defgroup ADC_Data_align ADC data alignment
<> 144:ef7eb2e8f9f7 233 * @{
<> 144:ef7eb2e8f9f7 234 */
<> 144:ef7eb2e8f9f7 235 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 236 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
<> 144:ef7eb2e8f9f7 237 /**
<> 144:ef7eb2e8f9f7 238 * @}
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /** @defgroup ADC_Scan_mode ADC scan mode
<> 144:ef7eb2e8f9f7 242 * @{
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244 /* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */
<> 144:ef7eb2e8f9f7 245 /* compatibility with other STM32 devices having a sequencer with */
<> 144:ef7eb2e8f9f7 246 /* additional options. */
<> 144:ef7eb2e8f9f7 247 #define ADC_SCAN_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 248 #define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
<> 144:ef7eb2e8f9f7 249 /**
<> 144:ef7eb2e8f9f7 250 * @}
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
<> 144:ef7eb2e8f9f7 254 * @{
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256 #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 257 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
<> 144:ef7eb2e8f9f7 258 /**
<> 144:ef7eb2e8f9f7 259 * @}
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /** @defgroup ADC_channels ADC channels
<> 144:ef7eb2e8f9f7 263 * @{
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265 /* Note: Depending on devices, some channels may not be available on package */
<> 144:ef7eb2e8f9f7 266 /* pins. Refer to device datasheet for channels availability. */
<> 144:ef7eb2e8f9f7 267 #define ADC_CHANNEL_0 ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 268 #define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0))
<> 144:ef7eb2e8f9f7 269 #define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 ))
<> 144:ef7eb2e8f9f7 270 #define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
<> 144:ef7eb2e8f9f7 271 #define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 ))
<> 144:ef7eb2e8f9f7 272 #define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
<> 144:ef7eb2e8f9f7 273 #define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 ))
<> 144:ef7eb2e8f9f7 274 #define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
<> 144:ef7eb2e8f9f7 275 #define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 ))
<> 144:ef7eb2e8f9f7 276 #define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))
<> 144:ef7eb2e8f9f7 277 #define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 ))
<> 144:ef7eb2e8f9f7 278 #define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
<> 144:ef7eb2e8f9f7 279 #define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 ))
<> 144:ef7eb2e8f9f7 280 #define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
<> 144:ef7eb2e8f9f7 281 #define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 ))
<> 144:ef7eb2e8f9f7 282 #define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
<> 144:ef7eb2e8f9f7 283 #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 ))
<> 144:ef7eb2e8f9f7 284 #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */
<> 144:ef7eb2e8f9f7 287 #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */
<> 144:ef7eb2e8f9f7 288 /**
<> 144:ef7eb2e8f9f7 289 * @}
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /** @defgroup ADC_sampling_times ADC sampling times
<> 144:ef7eb2e8f9f7 293 * @{
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295 #define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */
<> 144:ef7eb2e8f9f7 296 #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 297 #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /*!< Sampling time 13.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 298 #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 299 #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 )) /*!< Sampling time 41.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 300 #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 301 #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 )) /*!< Sampling time 71.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 302 #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 303 /**
<> 144:ef7eb2e8f9f7 304 * @}
<> 144:ef7eb2e8f9f7 305 */
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /** @defgroup ADC_regular_rank ADC rank into regular group
<> 144:ef7eb2e8f9f7 308 * @{
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310 #define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 311 #define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 312 #define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
<> 144:ef7eb2e8f9f7 313 #define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 314 #define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
<> 144:ef7eb2e8f9f7 315 #define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
<> 144:ef7eb2e8f9f7 316 #define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
<> 144:ef7eb2e8f9f7 317 #define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
<> 144:ef7eb2e8f9f7 318 #define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
<> 144:ef7eb2e8f9f7 319 #define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
<> 144:ef7eb2e8f9f7 320 #define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
<> 144:ef7eb2e8f9f7 321 #define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
<> 144:ef7eb2e8f9f7 322 #define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
<> 144:ef7eb2e8f9f7 323 #define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
<> 144:ef7eb2e8f9f7 324 #define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
<> 144:ef7eb2e8f9f7 325 #define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
<> 144:ef7eb2e8f9f7 326 /**
<> 144:ef7eb2e8f9f7 327 * @}
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
<> 144:ef7eb2e8f9f7 331 * @{
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333 #define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 334 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
<> 144:ef7eb2e8f9f7 335 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
<> 144:ef7eb2e8f9f7 336 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
<> 144:ef7eb2e8f9f7 337 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN)
<> 144:ef7eb2e8f9f7 338 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN)
<> 144:ef7eb2e8f9f7 339 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
<> 144:ef7eb2e8f9f7 340 /**
<> 144:ef7eb2e8f9f7 341 * @}
<> 144:ef7eb2e8f9f7 342 */
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /** @defgroup ADC_conversion_group ADC conversion group
<> 144:ef7eb2e8f9f7 345 * @{
<> 144:ef7eb2e8f9f7 346 */
<> 144:ef7eb2e8f9f7 347 #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
<> 144:ef7eb2e8f9f7 348 #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
<> 144:ef7eb2e8f9f7 349 #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
<> 144:ef7eb2e8f9f7 350 /**
<> 144:ef7eb2e8f9f7 351 * @}
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /** @defgroup ADC_Event_type ADC Event type
<> 144:ef7eb2e8f9f7 355 * @{
<> 144:ef7eb2e8f9f7 356 */
<> 144:ef7eb2e8f9f7 357 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 #define ADC_AWD1_EVENT ADC_AWD_EVENT /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */
<> 144:ef7eb2e8f9f7 360 /**
<> 144:ef7eb2e8f9f7 361 * @}
<> 144:ef7eb2e8f9f7 362 */
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /** @defgroup ADC_interrupts_definition ADC interrupts definition
<> 144:ef7eb2e8f9f7 365 * @{
<> 144:ef7eb2e8f9f7 366 */
<> 144:ef7eb2e8f9f7 367 #define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */
<> 144:ef7eb2e8f9f7 368 #define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */
<> 144:ef7eb2e8f9f7 369 #define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */
<> 144:ef7eb2e8f9f7 370 /**
<> 144:ef7eb2e8f9f7 371 * @}
<> 144:ef7eb2e8f9f7 372 */
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /** @defgroup ADC_flags_definition ADC flags definition
<> 144:ef7eb2e8f9f7 375 * @{
<> 144:ef7eb2e8f9f7 376 */
<> 144:ef7eb2e8f9f7 377 #define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */
<> 144:ef7eb2e8f9f7 378 #define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */
<> 144:ef7eb2e8f9f7 379 #define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */
<> 144:ef7eb2e8f9f7 380 #define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */
<> 144:ef7eb2e8f9f7 381 #define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */
<> 144:ef7eb2e8f9f7 382 /**
<> 144:ef7eb2e8f9f7 383 * @}
<> 144:ef7eb2e8f9f7 384 */
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /**
<> 144:ef7eb2e8f9f7 388 * @}
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /** @addtogroup ADC_Private_Constants ADC Private Constants
<> 144:ef7eb2e8f9f7 394 * @{
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /** @defgroup ADC_conversion_cycles ADC conversion cycles
<> 144:ef7eb2e8f9f7 398 * @{
<> 144:ef7eb2e8f9f7 399 */
<> 144:ef7eb2e8f9f7 400 /* ADC conversion cycles (unit: ADC clock cycles) */
<> 144:ef7eb2e8f9f7 401 /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
<> 144:ef7eb2e8f9f7 402 /* resolution 12 bits) */
<> 144:ef7eb2e8f9f7 403 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ((uint32_t) 14)
<> 144:ef7eb2e8f9f7 404 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ((uint32_t) 20)
<> 144:ef7eb2e8f9f7 405 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ((uint32_t) 26)
<> 144:ef7eb2e8f9f7 406 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ((uint32_t) 41)
<> 144:ef7eb2e8f9f7 407 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ((uint32_t) 54)
<> 144:ef7eb2e8f9f7 408 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ((uint32_t) 68)
<> 144:ef7eb2e8f9f7 409 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ((uint32_t) 84)
<> 144:ef7eb2e8f9f7 410 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 ((uint32_t)252)
<> 144:ef7eb2e8f9f7 411 /**
<> 144:ef7eb2e8f9f7 412 * @}
<> 144:ef7eb2e8f9f7 413 */
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
<> 144:ef7eb2e8f9f7 416 * @{
<> 144:ef7eb2e8f9f7 417 */
<> 144:ef7eb2e8f9f7 418 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
<> 144:ef7eb2e8f9f7 419 (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \
<> 144:ef7eb2e8f9f7 420 ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \
<> 144:ef7eb2e8f9f7 421 ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
<> 144:ef7eb2e8f9f7 422 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
<> 144:ef7eb2e8f9f7 423 (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \
<> 144:ef7eb2e8f9f7 424 ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 )
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
<> 144:ef7eb2e8f9f7 427 (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \
<> 144:ef7eb2e8f9f7 428 ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \
<> 144:ef7eb2e8f9f7 429 ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
<> 144:ef7eb2e8f9f7 430 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
<> 144:ef7eb2e8f9f7 431 (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \
<> 144:ef7eb2e8f9f7 432 ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 )
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
<> 144:ef7eb2e8f9f7 435 (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \
<> 144:ef7eb2e8f9f7 436 ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \
<> 144:ef7eb2e8f9f7 437 ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
<> 144:ef7eb2e8f9f7 438 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
<> 144:ef7eb2e8f9f7 439 (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \
<> 144:ef7eb2e8f9f7 440 ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 #define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 443 #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
<> 144:ef7eb2e8f9f7 444 #define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
<> 144:ef7eb2e8f9f7 445 #define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
<> 144:ef7eb2e8f9f7 446 #define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
<> 144:ef7eb2e8f9f7 447 #define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
<> 144:ef7eb2e8f9f7 448 #define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
<> 144:ef7eb2e8f9f7 449 #define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 #define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 452 #define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
<> 144:ef7eb2e8f9f7 453 #define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
<> 144:ef7eb2e8f9f7 454 #define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
<> 144:ef7eb2e8f9f7 455 #define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
<> 144:ef7eb2e8f9f7 456 #define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
<> 144:ef7eb2e8f9f7 457 #define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
<> 144:ef7eb2e8f9f7 458 #define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
<> 144:ef7eb2e8f9f7 459 /**
<> 144:ef7eb2e8f9f7 460 * @}
<> 144:ef7eb2e8f9f7 461 */
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
<> 144:ef7eb2e8f9f7 464 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD )
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /**
<> 144:ef7eb2e8f9f7 467 * @}
<> 144:ef7eb2e8f9f7 468 */
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 /** @defgroup ADC_Exported_Macros ADC Exported Macros
<> 144:ef7eb2e8f9f7 474 * @{
<> 144:ef7eb2e8f9f7 475 */
<> 144:ef7eb2e8f9f7 476 /* Macro for internal HAL driver usage, and possibly can be used into code of */
<> 144:ef7eb2e8f9f7 477 /* final user. */
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /**
<> 144:ef7eb2e8f9f7 480 * @brief Enable the ADC peripheral
<> 144:ef7eb2e8f9f7 481 * @note ADC enable requires a delay for ADC stabilization time
<> 144:ef7eb2e8f9f7 482 * (refer to device datasheet, parameter tSTAB)
<> 144:ef7eb2e8f9f7 483 * @note On STM32F1, if ADC is already enabled this macro trigs a conversion
<> 144:ef7eb2e8f9f7 484 * SW start on regular group.
<> 144:ef7eb2e8f9f7 485 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 486 * @retval None
<> 144:ef7eb2e8f9f7 487 */
<> 144:ef7eb2e8f9f7 488 #define __HAL_ADC_ENABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 489 (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /**
<> 144:ef7eb2e8f9f7 492 * @brief Disable the ADC peripheral
<> 144:ef7eb2e8f9f7 493 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 494 * @retval None
<> 144:ef7eb2e8f9f7 495 */
<> 144:ef7eb2e8f9f7 496 #define __HAL_ADC_DISABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 497 (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /** @brief Enable the ADC end of conversion interrupt.
<> 144:ef7eb2e8f9f7 500 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 501 * @param __INTERRUPT__: ADC Interrupt
<> 144:ef7eb2e8f9f7 502 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 503 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<> 144:ef7eb2e8f9f7 504 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<> 144:ef7eb2e8f9f7 505 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<> 144:ef7eb2e8f9f7 506 * @retval None
<> 144:ef7eb2e8f9f7 507 */
<> 144:ef7eb2e8f9f7 508 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
<> 144:ef7eb2e8f9f7 509 (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /** @brief Disable the ADC end of conversion interrupt.
<> 144:ef7eb2e8f9f7 512 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 513 * @param __INTERRUPT__: ADC Interrupt
<> 144:ef7eb2e8f9f7 514 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 515 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<> 144:ef7eb2e8f9f7 516 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<> 144:ef7eb2e8f9f7 517 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<> 144:ef7eb2e8f9f7 518 * @retval None
<> 144:ef7eb2e8f9f7 519 */
<> 144:ef7eb2e8f9f7 520 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
<> 144:ef7eb2e8f9f7 521 (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /** @brief Checks if the specified ADC interrupt source is enabled or disabled.
<> 144:ef7eb2e8f9f7 524 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 525 * @param __INTERRUPT__: ADC interrupt source to check
<> 144:ef7eb2e8f9f7 526 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 527 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<> 144:ef7eb2e8f9f7 528 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<> 144:ef7eb2e8f9f7 529 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<> 144:ef7eb2e8f9f7 530 * @retval None
<> 144:ef7eb2e8f9f7 531 */
<> 144:ef7eb2e8f9f7 532 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
<> 144:ef7eb2e8f9f7 533 (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /** @brief Get the selected ADC's flag status.
<> 144:ef7eb2e8f9f7 536 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 537 * @param __FLAG__: ADC flag
<> 144:ef7eb2e8f9f7 538 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 539 * @arg ADC_FLAG_STRT: ADC Regular group start flag
<> 144:ef7eb2e8f9f7 540 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag
<> 144:ef7eb2e8f9f7 541 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
<> 144:ef7eb2e8f9f7 542 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
<> 144:ef7eb2e8f9f7 543 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
<> 144:ef7eb2e8f9f7 544 * @retval None
<> 144:ef7eb2e8f9f7 545 */
<> 144:ef7eb2e8f9f7 546 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
<> 144:ef7eb2e8f9f7 547 ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /** @brief Clear the ADC's pending flags
<> 144:ef7eb2e8f9f7 550 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 551 * @param __FLAG__: ADC flag
<> 144:ef7eb2e8f9f7 552 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 553 * @arg ADC_FLAG_STRT: ADC Regular group start flag
<> 144:ef7eb2e8f9f7 554 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag
<> 144:ef7eb2e8f9f7 555 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
<> 144:ef7eb2e8f9f7 556 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
<> 144:ef7eb2e8f9f7 557 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
<> 144:ef7eb2e8f9f7 558 * @retval None
<> 144:ef7eb2e8f9f7 559 */
<> 144:ef7eb2e8f9f7 560 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
<> 144:ef7eb2e8f9f7 561 (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /** @brief Reset ADC handle state
<> 144:ef7eb2e8f9f7 564 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 565 * @retval None
<> 144:ef7eb2e8f9f7 566 */
<> 144:ef7eb2e8f9f7 567 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 568 ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /**
<> 144:ef7eb2e8f9f7 571 * @}
<> 144:ef7eb2e8f9f7 572 */
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /* Private macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 /** @defgroup ADC_Private_Macros ADC Private Macros
<> 144:ef7eb2e8f9f7 577 * @{
<> 144:ef7eb2e8f9f7 578 */
<> 144:ef7eb2e8f9f7 579 /* Macro reserved for internal HAL driver usage, not intended to be used in */
<> 144:ef7eb2e8f9f7 580 /* code of final user. */
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 /**
<> 144:ef7eb2e8f9f7 583 * @brief Verification of ADC state: enabled or disabled
<> 144:ef7eb2e8f9f7 584 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 585 * @retval SET (ADC enabled) or RESET (ADC disabled)
<> 144:ef7eb2e8f9f7 586 */
<> 144:ef7eb2e8f9f7 587 #define ADC_IS_ENABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 588 ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \
<> 144:ef7eb2e8f9f7 589 ) ? SET : RESET)
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /**
<> 144:ef7eb2e8f9f7 592 * @brief Test if conversion trigger of regular group is software start
<> 144:ef7eb2e8f9f7 593 * or external trigger.
<> 144:ef7eb2e8f9f7 594 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 595 * @retval SET (software start) or RESET (external trigger)
<> 144:ef7eb2e8f9f7 596 */
<> 144:ef7eb2e8f9f7 597 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
<> 144:ef7eb2e8f9f7 598 (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 /**
<> 144:ef7eb2e8f9f7 601 * @brief Test if conversion trigger of injected group is software start
<> 144:ef7eb2e8f9f7 602 * or external trigger.
<> 144:ef7eb2e8f9f7 603 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 604 * @retval SET (software start) or RESET (external trigger)
<> 144:ef7eb2e8f9f7 605 */
<> 144:ef7eb2e8f9f7 606 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
<> 144:ef7eb2e8f9f7 607 (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /**
<> 144:ef7eb2e8f9f7 610 * @brief Simultaneously clears and sets specific bits of the handle State
<> 144:ef7eb2e8f9f7 611 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
<> 144:ef7eb2e8f9f7 612 * the first parameter is the ADC handle State, the second parameter is the
<> 144:ef7eb2e8f9f7 613 * bit field to clear, the third and last parameter is the bit field to set.
<> 144:ef7eb2e8f9f7 614 * @retval None
<> 144:ef7eb2e8f9f7 615 */
<> 144:ef7eb2e8f9f7 616 #define ADC_STATE_CLR_SET MODIFY_REG
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /**
<> 144:ef7eb2e8f9f7 619 * @brief Clear ADC error code (set it to error code: "no error")
<> 144:ef7eb2e8f9f7 620 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 621 * @retval None
<> 144:ef7eb2e8f9f7 622 */
<> 144:ef7eb2e8f9f7 623 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 624 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 /**
<> 144:ef7eb2e8f9f7 627 * @brief Set ADC number of conversions into regular channel sequence length.
<> 144:ef7eb2e8f9f7 628 * @param _NbrOfConversion_: Regular channel sequence length
<> 144:ef7eb2e8f9f7 629 * @retval None
<> 144:ef7eb2e8f9f7 630 */
<> 144:ef7eb2e8f9f7 631 #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
<> 144:ef7eb2e8f9f7 632 (((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L))
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /**
<> 144:ef7eb2e8f9f7 635 * @brief Set the ADC's sample time for channel numbers between 10 and 18.
<> 144:ef7eb2e8f9f7 636 * @param _SAMPLETIME_: Sample time parameter.
<> 144:ef7eb2e8f9f7 637 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 638 * @retval None
<> 144:ef7eb2e8f9f7 639 */
<> 144:ef7eb2e8f9f7 640 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
<> 144:ef7eb2e8f9f7 641 ((_SAMPLETIME_) << (POSITION_VAL(ADC_SMPR1_SMP11) * ((_CHANNELNB_) - 10)))
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /**
<> 144:ef7eb2e8f9f7 644 * @brief Set the ADC's sample time for channel numbers between 0 and 9.
<> 144:ef7eb2e8f9f7 645 * @param _SAMPLETIME_: Sample time parameter.
<> 144:ef7eb2e8f9f7 646 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 647 * @retval None
<> 144:ef7eb2e8f9f7 648 */
<> 144:ef7eb2e8f9f7 649 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
<> 144:ef7eb2e8f9f7 650 ((_SAMPLETIME_) << (POSITION_VAL(ADC_SMPR2_SMP1) * (_CHANNELNB_)))
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 /**
<> 144:ef7eb2e8f9f7 653 * @brief Set the selected regular channel rank for rank between 1 and 6.
<> 144:ef7eb2e8f9f7 654 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 655 * @param _RANKNB_: Rank number.
<> 144:ef7eb2e8f9f7 656 * @retval None
<> 144:ef7eb2e8f9f7 657 */
<> 144:ef7eb2e8f9f7 658 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
<> 144:ef7eb2e8f9f7 659 ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR3_SQ2) * ((_RANKNB_) - 1)))
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /**
<> 144:ef7eb2e8f9f7 662 * @brief Set the selected regular channel rank for rank between 7 and 12.
<> 144:ef7eb2e8f9f7 663 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 664 * @param _RANKNB_: Rank number.
<> 144:ef7eb2e8f9f7 665 * @retval None
<> 144:ef7eb2e8f9f7 666 */
<> 144:ef7eb2e8f9f7 667 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
<> 144:ef7eb2e8f9f7 668 ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR2_SQ8) * ((_RANKNB_) - 7)))
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /**
<> 144:ef7eb2e8f9f7 671 * @brief Set the selected regular channel rank for rank between 13 and 16.
<> 144:ef7eb2e8f9f7 672 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 673 * @param _RANKNB_: Rank number.
<> 144:ef7eb2e8f9f7 674 * @retval None
<> 144:ef7eb2e8f9f7 675 */
<> 144:ef7eb2e8f9f7 676 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
<> 144:ef7eb2e8f9f7 677 ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR1_SQ14) * ((_RANKNB_) - 13)))
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /**
<> 144:ef7eb2e8f9f7 680 * @brief Set the injected sequence length.
<> 144:ef7eb2e8f9f7 681 * @param _JSQR_JL_: Sequence length.
<> 144:ef7eb2e8f9f7 682 * @retval None
<> 144:ef7eb2e8f9f7 683 */
<> 144:ef7eb2e8f9f7 684 #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \
<> 144:ef7eb2e8f9f7 685 (((_JSQR_JL_) -1) << POSITION_VAL(ADC_JSQR_JL))
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /**
<> 144:ef7eb2e8f9f7 688 * @brief Set the selected injected channel rank
<> 144:ef7eb2e8f9f7 689 * Note: on STM32F1 devices, channel rank position in JSQR register
<> 144:ef7eb2e8f9f7 690 * is depending on total number of ranks selected into
<> 144:ef7eb2e8f9f7 691 * injected sequencer (ranks sequence starting from 4-JL)
<> 144:ef7eb2e8f9f7 692 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 693 * @param _RANKNB_: Rank number.
<> 144:ef7eb2e8f9f7 694 * @param _JSQR_JL_: Sequence length.
<> 144:ef7eb2e8f9f7 695 * @retval None
<> 144:ef7eb2e8f9f7 696 */
<> 144:ef7eb2e8f9f7 697 #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
<> 144:ef7eb2e8f9f7 698 ((_CHANNELNB_) << (POSITION_VAL(ADC_JSQR_JSQ2) * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /**
<> 144:ef7eb2e8f9f7 701 * @brief Enable ADC continuous conversion mode.
<> 144:ef7eb2e8f9f7 702 * @param _CONTINUOUS_MODE_: Continuous mode.
<> 144:ef7eb2e8f9f7 703 * @retval None
<> 144:ef7eb2e8f9f7 704 */
<> 144:ef7eb2e8f9f7 705 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
<> 144:ef7eb2e8f9f7 706 ((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT))
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /**
<> 144:ef7eb2e8f9f7 709 * @brief Configures the number of discontinuous conversions for the regular group channels.
<> 144:ef7eb2e8f9f7 710 * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
<> 144:ef7eb2e8f9f7 711 * @retval None
<> 144:ef7eb2e8f9f7 712 */
<> 144:ef7eb2e8f9f7 713 #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
<> 144:ef7eb2e8f9f7 714 (((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716 /**
<> 144:ef7eb2e8f9f7 717 * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
<> 144:ef7eb2e8f9f7 718 * @param _SCAN_MODE_: Scan conversion mode.
<> 144:ef7eb2e8f9f7 719 * @retval None
<> 144:ef7eb2e8f9f7 720 */
<> 144:ef7eb2e8f9f7 721 /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
<> 144:ef7eb2e8f9f7 722 /* is equivalent to ADC_SCAN_ENABLE. */
<> 144:ef7eb2e8f9f7 723 #define ADC_CR1_SCAN_SET(_SCAN_MODE_) \
<> 144:ef7eb2e8f9f7 724 (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \
<> 144:ef7eb2e8f9f7 725 )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
<> 144:ef7eb2e8f9f7 726 )
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 /**
<> 144:ef7eb2e8f9f7 729 * @brief Get the maximum ADC conversion cycles on all channels.
<> 144:ef7eb2e8f9f7 730 * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
<> 144:ef7eb2e8f9f7 731 * Approximation of sampling time within 4 ranges, returns the highest value:
<> 144:ef7eb2e8f9f7 732 * below 7.5 cycles {1.5 cycle; 7.5 cycles},
<> 144:ef7eb2e8f9f7 733 * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
<> 144:ef7eb2e8f9f7 734 * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
<> 144:ef7eb2e8f9f7 735 * equal to 239.5 cycles
<> 144:ef7eb2e8f9f7 736 * Unit: ADC clock cycles
<> 144:ef7eb2e8f9f7 737 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 738 * @retval ADC conversion cycles on all channels
<> 144:ef7eb2e8f9f7 739 */
<> 144:ef7eb2e8f9f7 740 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 741 (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \
<> 144:ef7eb2e8f9f7 742 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \
<> 144:ef7eb2e8f9f7 743 \
<> 144:ef7eb2e8f9f7 744 (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
<> 144:ef7eb2e8f9f7 745 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \
<> 144:ef7eb2e8f9f7 746 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \
<> 144:ef7eb2e8f9f7 747 : \
<> 144:ef7eb2e8f9f7 748 ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
<> 144:ef7eb2e8f9f7 749 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \
<> 144:ef7eb2e8f9f7 750 ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \
<> 144:ef7eb2e8f9f7 751 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \
<> 144:ef7eb2e8f9f7 752 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
<> 144:ef7eb2e8f9f7 753 )
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
<> 144:ef7eb2e8f9f7 756 ((ALIGN) == ADC_DATAALIGN_LEFT) )
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
<> 144:ef7eb2e8f9f7 759 ((SCAN_MODE) == ADC_SCAN_ENABLE) )
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
<> 144:ef7eb2e8f9f7 762 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) )
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
<> 144:ef7eb2e8f9f7 765 ((CHANNEL) == ADC_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 766 ((CHANNEL) == ADC_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 767 ((CHANNEL) == ADC_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 768 ((CHANNEL) == ADC_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 769 ((CHANNEL) == ADC_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 770 ((CHANNEL) == ADC_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 771 ((CHANNEL) == ADC_CHANNEL_7) || \
<> 144:ef7eb2e8f9f7 772 ((CHANNEL) == ADC_CHANNEL_8) || \
<> 144:ef7eb2e8f9f7 773 ((CHANNEL) == ADC_CHANNEL_9) || \
<> 144:ef7eb2e8f9f7 774 ((CHANNEL) == ADC_CHANNEL_10) || \
<> 144:ef7eb2e8f9f7 775 ((CHANNEL) == ADC_CHANNEL_11) || \
<> 144:ef7eb2e8f9f7 776 ((CHANNEL) == ADC_CHANNEL_12) || \
<> 144:ef7eb2e8f9f7 777 ((CHANNEL) == ADC_CHANNEL_13) || \
<> 144:ef7eb2e8f9f7 778 ((CHANNEL) == ADC_CHANNEL_14) || \
<> 144:ef7eb2e8f9f7 779 ((CHANNEL) == ADC_CHANNEL_15) || \
<> 144:ef7eb2e8f9f7 780 ((CHANNEL) == ADC_CHANNEL_16) || \
<> 144:ef7eb2e8f9f7 781 ((CHANNEL) == ADC_CHANNEL_17) )
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
<> 144:ef7eb2e8f9f7 784 ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
<> 144:ef7eb2e8f9f7 785 ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \
<> 144:ef7eb2e8f9f7 786 ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \
<> 144:ef7eb2e8f9f7 787 ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \
<> 144:ef7eb2e8f9f7 788 ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \
<> 144:ef7eb2e8f9f7 789 ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \
<> 144:ef7eb2e8f9f7 790 ((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
<> 144:ef7eb2e8f9f7 793 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
<> 144:ef7eb2e8f9f7 794 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
<> 144:ef7eb2e8f9f7 795 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
<> 144:ef7eb2e8f9f7 796 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
<> 144:ef7eb2e8f9f7 797 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
<> 144:ef7eb2e8f9f7 798 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
<> 144:ef7eb2e8f9f7 799 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
<> 144:ef7eb2e8f9f7 800 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
<> 144:ef7eb2e8f9f7 801 ((CHANNEL) == ADC_REGULAR_RANK_10) || \
<> 144:ef7eb2e8f9f7 802 ((CHANNEL) == ADC_REGULAR_RANK_11) || \
<> 144:ef7eb2e8f9f7 803 ((CHANNEL) == ADC_REGULAR_RANK_12) || \
<> 144:ef7eb2e8f9f7 804 ((CHANNEL) == ADC_REGULAR_RANK_13) || \
<> 144:ef7eb2e8f9f7 805 ((CHANNEL) == ADC_REGULAR_RANK_14) || \
<> 144:ef7eb2e8f9f7 806 ((CHANNEL) == ADC_REGULAR_RANK_15) || \
<> 144:ef7eb2e8f9f7 807 ((CHANNEL) == ADC_REGULAR_RANK_16) )
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
<> 144:ef7eb2e8f9f7 810 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
<> 144:ef7eb2e8f9f7 811 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
<> 144:ef7eb2e8f9f7 812 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
<> 144:ef7eb2e8f9f7 813 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
<> 144:ef7eb2e8f9f7 814 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
<> 144:ef7eb2e8f9f7 815 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \
<> 144:ef7eb2e8f9f7 818 ((CONVERSION) == ADC_INJECTED_GROUP) || \
<> 144:ef7eb2e8f9f7 819 ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 #define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 /** @defgroup ADC_range_verification ADC range verification
<> 144:ef7eb2e8f9f7 825 * For a unique ADC resolution: 12 bits
<> 144:ef7eb2e8f9f7 826 * @{
<> 144:ef7eb2e8f9f7 827 */
<> 144:ef7eb2e8f9f7 828 #define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= ((uint32_t)0x0FFF))
<> 144:ef7eb2e8f9f7 829 /**
<> 144:ef7eb2e8f9f7 830 * @}
<> 144:ef7eb2e8f9f7 831 */
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 /** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification
<> 144:ef7eb2e8f9f7 834 * @{
<> 144:ef7eb2e8f9f7 835 */
<> 144:ef7eb2e8f9f7 836 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
<> 144:ef7eb2e8f9f7 837 /**
<> 144:ef7eb2e8f9f7 838 * @}
<> 144:ef7eb2e8f9f7 839 */
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification
<> 144:ef7eb2e8f9f7 842 * @{
<> 144:ef7eb2e8f9f7 843 */
<> 144:ef7eb2e8f9f7 844 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
<> 144:ef7eb2e8f9f7 845 /**
<> 144:ef7eb2e8f9f7 846 * @}
<> 144:ef7eb2e8f9f7 847 */
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 /**
<> 144:ef7eb2e8f9f7 850 * @}
<> 144:ef7eb2e8f9f7 851 */
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 /* Include ADC HAL Extension module */
<> 144:ef7eb2e8f9f7 854 #include "stm32f1xx_hal_adc_ex.h"
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 857 /** @addtogroup ADC_Exported_Functions
<> 144:ef7eb2e8f9f7 858 * @{
<> 144:ef7eb2e8f9f7 859 */
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /** @addtogroup ADC_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 862 * @{
<> 144:ef7eb2e8f9f7 863 */
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 /* Initialization and de-initialization functions **********************************/
<> 144:ef7eb2e8f9f7 867 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 868 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
<> 144:ef7eb2e8f9f7 869 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 870 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 871 /**
<> 144:ef7eb2e8f9f7 872 * @}
<> 144:ef7eb2e8f9f7 873 */
<> 144:ef7eb2e8f9f7 874
<> 144:ef7eb2e8f9f7 875 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 /** @addtogroup ADC_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 878 * @{
<> 144:ef7eb2e8f9f7 879 */
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 883 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 884 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 885 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 886 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /* Non-blocking mode: Interruption */
<> 144:ef7eb2e8f9f7 889 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 890 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 /* Non-blocking mode: DMA */
<> 144:ef7eb2e8f9f7 893 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
<> 144:ef7eb2e8f9f7 894 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896 /* ADC retrieve conversion value intended to be used with polling or interruption */
<> 144:ef7eb2e8f9f7 897 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
<> 144:ef7eb2e8f9f7 900 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 901 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 902 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 903 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 904 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
<> 144:ef7eb2e8f9f7 905 /**
<> 144:ef7eb2e8f9f7 906 * @}
<> 144:ef7eb2e8f9f7 907 */
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 911 /** @addtogroup ADC_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 912 * @{
<> 144:ef7eb2e8f9f7 913 */
<> 144:ef7eb2e8f9f7 914 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
<> 144:ef7eb2e8f9f7 915 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
<> 144:ef7eb2e8f9f7 916 /**
<> 144:ef7eb2e8f9f7 917 * @}
<> 144:ef7eb2e8f9f7 918 */
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /* Peripheral State functions *************************************************/
<> 144:ef7eb2e8f9f7 922 /** @addtogroup ADC_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 923 * @{
<> 144:ef7eb2e8f9f7 924 */
<> 144:ef7eb2e8f9f7 925 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 926 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
<> 144:ef7eb2e8f9f7 927 /**
<> 144:ef7eb2e8f9f7 928 * @}
<> 144:ef7eb2e8f9f7 929 */
<> 144:ef7eb2e8f9f7 930
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 /**
<> 144:ef7eb2e8f9f7 933 * @}
<> 144:ef7eb2e8f9f7 934 */
<> 144:ef7eb2e8f9f7 935
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 /* Internal HAL driver functions **********************************************/
<> 144:ef7eb2e8f9f7 938 /** @addtogroup ADC_Private_Functions
<> 144:ef7eb2e8f9f7 939 * @{
<> 144:ef7eb2e8f9f7 940 */
<> 144:ef7eb2e8f9f7 941 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 942 HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 943 void ADC_StabilizationTime(uint32_t DelayUs);
<> 144:ef7eb2e8f9f7 944 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 945 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 946 void ADC_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 947 /**
<> 144:ef7eb2e8f9f7 948 * @}
<> 144:ef7eb2e8f9f7 949 */
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951
<> 144:ef7eb2e8f9f7 952 /**
<> 144:ef7eb2e8f9f7 953 * @}
<> 144:ef7eb2e8f9f7 954 */
<> 144:ef7eb2e8f9f7 955
<> 144:ef7eb2e8f9f7 956 /**
<> 144:ef7eb2e8f9f7 957 * @}
<> 144:ef7eb2e8f9f7 958 */
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 961 }
<> 144:ef7eb2e8f9f7 962 #endif
<> 144:ef7eb2e8f9f7 963
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 #endif /* __STM32F1xx_HAL_ADC_H */
<> 144:ef7eb2e8f9f7 966
<> 144:ef7eb2e8f9f7 967 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/