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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_dspi.h@167:356ef919c855, 2017-06-20 (annotated)

Committer:
kkado
Date:
Tue Jun 20 11:06:37 2017 +0000
Revision:
167:356ef919c855
Parent:
154:37f96f9d4de2 
Build 137 with reduced HSE timeout

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30 #ifndef _FSL_DSPI_H_
<> 154:37f96f9d4de2 31 #define _FSL_DSPI_H_
<> 154:37f96f9d4de2 32
<> 154:37f96f9d4de2 33 #include "fsl_common.h"
<> 154:37f96f9d4de2 34
<> 154:37f96f9d4de2 35 /*!
<> 154:37f96f9d4de2 36 * @addtogroup dspi_driver
<> 154:37f96f9d4de2 37 * @{
<> 154:37f96f9d4de2 38 */
<> 154:37f96f9d4de2 39
<> 154:37f96f9d4de2 40
<> 154:37f96f9d4de2 41 /**********************************************************************************************************************
<> 154:37f96f9d4de2 42 * Definitions
<> 154:37f96f9d4de2 43 *********************************************************************************************************************/
<> 154:37f96f9d4de2 44
<> 154:37f96f9d4de2 45 /*! @name Driver version */
<> 154:37f96f9d4de2 46 /*@{*/
<> 154:37f96f9d4de2 47 /*! @brief DSPI driver version 2.1.1. */
<> 154:37f96f9d4de2 48 #define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
<> 154:37f96f9d4de2 49 /*@}*/
<> 154:37f96f9d4de2 50
<> 154:37f96f9d4de2 51 /*! @brief DSPI dummy data if no Tx data.*/
<> 154:37f96f9d4de2 52 #define DSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for tx if there is not txData. */
<> 154:37f96f9d4de2 53
<> 154:37f96f9d4de2 54 /*! @brief Status for the DSPI driver.*/
<> 154:37f96f9d4de2 55 enum _dspi_status
<> 154:37f96f9d4de2 56 {
<> 154:37f96f9d4de2 57 kStatus_DSPI_Busy = MAKE_STATUS(kStatusGroup_DSPI, 0), /*!< DSPI transfer is busy.*/
<> 154:37f96f9d4de2 58 kStatus_DSPI_Error = MAKE_STATUS(kStatusGroup_DSPI, 1), /*!< DSPI driver error. */
<> 154:37f96f9d4de2 59 kStatus_DSPI_Idle = MAKE_STATUS(kStatusGroup_DSPI, 2), /*!< DSPI is idle.*/
<> 154:37f96f9d4de2 60 kStatus_DSPI_OutOfRange = MAKE_STATUS(kStatusGroup_DSPI, 3) /*!< DSPI transfer out Of range. */
<> 154:37f96f9d4de2 61 };
<> 154:37f96f9d4de2 62
<> 154:37f96f9d4de2 63 /*! @brief DSPI status flags in SPIx_SR register.*/
<> 154:37f96f9d4de2 64 enum _dspi_flags
<> 154:37f96f9d4de2 65 {
<> 154:37f96f9d4de2 66 kDSPI_TxCompleteFlag = SPI_SR_TCF_MASK, /*!< Transfer Complete Flag. */
<> 154:37f96f9d4de2 67 kDSPI_EndOfQueueFlag = SPI_SR_EOQF_MASK, /*!< End of Queue Flag.*/
<> 154:37f96f9d4de2 68 kDSPI_TxFifoUnderflowFlag = SPI_SR_TFUF_MASK, /*!< Transmit FIFO Underflow Flag.*/
<> 154:37f96f9d4de2 69 kDSPI_TxFifoFillRequestFlag = SPI_SR_TFFF_MASK, /*!< Transmit FIFO Fill Flag.*/
<> 154:37f96f9d4de2 70 kDSPI_RxFifoOverflowFlag = SPI_SR_RFOF_MASK, /*!< Receive FIFO Overflow Flag.*/
<> 154:37f96f9d4de2 71 kDSPI_RxFifoDrainRequestFlag = SPI_SR_RFDF_MASK, /*!< Receive FIFO Drain Flag.*/
<> 154:37f96f9d4de2 72 kDSPI_TxAndRxStatusFlag = SPI_SR_TXRXS_MASK, /*!< The module is in Stopped/Running state.*/
<> 154:37f96f9d4de2 73 kDSPI_AllStatusFlag = SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TFFF_MASK | SPI_SR_RFOF_MASK |
<> 154:37f96f9d4de2 74 SPI_SR_RFDF_MASK | SPI_SR_TXRXS_MASK /*!< All status above.*/
<> 154:37f96f9d4de2 75 };
<> 154:37f96f9d4de2 76
<> 154:37f96f9d4de2 77 /*! @brief DSPI interrupt source.*/
<> 154:37f96f9d4de2 78 enum _dspi_interrupt_enable
<> 154:37f96f9d4de2 79 {
<> 154:37f96f9d4de2 80 kDSPI_TxCompleteInterruptEnable = SPI_RSER_TCF_RE_MASK, /*!< TCF interrupt enable.*/
<> 154:37f96f9d4de2 81 kDSPI_EndOfQueueInterruptEnable = SPI_RSER_EOQF_RE_MASK, /*!< EOQF interrupt enable.*/
<> 154:37f96f9d4de2 82 kDSPI_TxFifoUnderflowInterruptEnable = SPI_RSER_TFUF_RE_MASK, /*!< TFUF interrupt enable.*/
<> 154:37f96f9d4de2 83 kDSPI_TxFifoFillRequestInterruptEnable = SPI_RSER_TFFF_RE_MASK, /*!< TFFF interrupt enable, DMA disable.*/
<> 154:37f96f9d4de2 84 kDSPI_RxFifoOverflowInterruptEnable = SPI_RSER_RFOF_RE_MASK, /*!< RFOF interrupt enable.*/
<> 154:37f96f9d4de2 85 kDSPI_RxFifoDrainRequestInterruptEnable = SPI_RSER_RFDF_RE_MASK, /*!< RFDF interrupt enable, DMA disable.*/
<> 154:37f96f9d4de2 86 kDSPI_AllInterruptEnable = SPI_RSER_TCF_RE_MASK | SPI_RSER_EOQF_RE_MASK | SPI_RSER_TFUF_RE_MASK |
<> 154:37f96f9d4de2 87 SPI_RSER_TFFF_RE_MASK | SPI_RSER_RFOF_RE_MASK | SPI_RSER_RFDF_RE_MASK
<> 154:37f96f9d4de2 88 /*!< All above interrupts enable.*/
<> 154:37f96f9d4de2 89 };
<> 154:37f96f9d4de2 90
<> 154:37f96f9d4de2 91 /*! @brief DSPI DMA source.*/
<> 154:37f96f9d4de2 92 enum _dspi_dma_enable
<> 154:37f96f9d4de2 93 {
<> 154:37f96f9d4de2 94 kDSPI_TxDmaEnable = (SPI_RSER_TFFF_RE_MASK | SPI_RSER_TFFF_DIRS_MASK), /*!< TFFF flag generates DMA requests.
<> 154:37f96f9d4de2 95 No Tx interrupt request. */
<> 154:37f96f9d4de2 96 kDSPI_RxDmaEnable = (SPI_RSER_RFDF_RE_MASK | SPI_RSER_RFDF_DIRS_MASK) /*!< RFDF flag generates DMA requests.
<> 154:37f96f9d4de2 97 No Rx interrupt request. */
<> 154:37f96f9d4de2 98 };
<> 154:37f96f9d4de2 99
<> 154:37f96f9d4de2 100 /*! @brief DSPI master or slave mode configuration.*/
<> 154:37f96f9d4de2 101 typedef enum _dspi_master_slave_mode
<> 154:37f96f9d4de2 102 {
<> 154:37f96f9d4de2 103 kDSPI_Master = 1U, /*!< DSPI peripheral operates in master mode.*/
<> 154:37f96f9d4de2 104 kDSPI_Slave = 0U /*!< DSPI peripheral operates in slave mode.*/
<> 154:37f96f9d4de2 105 } dspi_master_slave_mode_t;
<> 154:37f96f9d4de2 106
<> 154:37f96f9d4de2 107 /*!
<> 154:37f96f9d4de2 108 * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in Modified Transfer Format. This field is valid
<> 154:37f96f9d4de2 109 * only when CPHA bit in CTAR register is 0.
<> 154:37f96f9d4de2 110 */
<> 154:37f96f9d4de2 111 typedef enum _dspi_master_sample_point
<> 154:37f96f9d4de2 112 {
<> 154:37f96f9d4de2 113 kDSPI_SckToSin0Clock = 0U, /*!< 0 system clocks between SCK edge and SIN sample.*/
<> 154:37f96f9d4de2 114 kDSPI_SckToSin1Clock = 1U, /*!< 1 system clock between SCK edge and SIN sample.*/
<> 154:37f96f9d4de2 115 kDSPI_SckToSin2Clock = 2U /*!< 2 system clocks between SCK edge and SIN sample.*/
<> 154:37f96f9d4de2 116 } dspi_master_sample_point_t;
<> 154:37f96f9d4de2 117
<> 154:37f96f9d4de2 118 /*! @brief DSPI Peripheral Chip Select (Pcs) configuration (which Pcs to configure).*/
<> 154:37f96f9d4de2 119 typedef enum _dspi_which_pcs_config
<> 154:37f96f9d4de2 120 {
<> 154:37f96f9d4de2 121 kDSPI_Pcs0 = 1U << 0, /*!< Pcs[0] */
<> 154:37f96f9d4de2 122 kDSPI_Pcs1 = 1U << 1, /*!< Pcs[1] */
<> 154:37f96f9d4de2 123 kDSPI_Pcs2 = 1U << 2, /*!< Pcs[2] */
<> 154:37f96f9d4de2 124 kDSPI_Pcs3 = 1U << 3, /*!< Pcs[3] */
<> 154:37f96f9d4de2 125 kDSPI_Pcs4 = 1U << 4, /*!< Pcs[4] */
<> 154:37f96f9d4de2 126 kDSPI_Pcs5 = 1U << 5 /*!< Pcs[5] */
<> 154:37f96f9d4de2 127 } dspi_which_pcs_t;
<> 154:37f96f9d4de2 128
<> 154:37f96f9d4de2 129 /*! @brief DSPI Peripheral Chip Select (Pcs) Polarity configuration.*/
<> 154:37f96f9d4de2 130 typedef enum _dspi_pcs_polarity_config
<> 154:37f96f9d4de2 131 {
<> 154:37f96f9d4de2 132 kDSPI_PcsActiveHigh = 0U, /*!< Pcs Active High (idles low). */
<> 154:37f96f9d4de2 133 kDSPI_PcsActiveLow = 1U /*!< Pcs Active Low (idles high). */
<> 154:37f96f9d4de2 134 } dspi_pcs_polarity_config_t;
<> 154:37f96f9d4de2 135
<> 154:37f96f9d4de2 136 /*! @brief DSPI Peripheral Chip Select (Pcs) Polarity.*/
<> 154:37f96f9d4de2 137 enum _dspi_pcs_polarity
<> 154:37f96f9d4de2 138 {
<> 154:37f96f9d4de2 139 kDSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */
<> 154:37f96f9d4de2 140 kDSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */
<> 154:37f96f9d4de2 141 kDSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */
<> 154:37f96f9d4de2 142 kDSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */
<> 154:37f96f9d4de2 143 kDSPI_Pcs4ActiveLow = 1U << 4, /*!< Pcs4 Active Low (idles high). */
<> 154:37f96f9d4de2 144 kDSPI_Pcs5ActiveLow = 1U << 5, /*!< Pcs5 Active Low (idles high). */
<> 154:37f96f9d4de2 145 kDSPI_PcsAllActiveLow = 0xFFU /*!< Pcs0 to Pcs5 Active Low (idles high). */
<> 154:37f96f9d4de2 146 };
<> 154:37f96f9d4de2 147
<> 154:37f96f9d4de2 148 /*! @brief DSPI clock polarity configuration for a given CTAR.*/
<> 154:37f96f9d4de2 149 typedef enum _dspi_clock_polarity
<> 154:37f96f9d4de2 150 {
<> 154:37f96f9d4de2 151 kDSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high DSPI clock (idles low).*/
<> 154:37f96f9d4de2 152 kDSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low DSPI clock (idles high).*/
<> 154:37f96f9d4de2 153 } dspi_clock_polarity_t;
<> 154:37f96f9d4de2 154
<> 154:37f96f9d4de2 155 /*! @brief DSPI clock phase configuration for a given CTAR.*/
<> 154:37f96f9d4de2 156 typedef enum _dspi_clock_phase
<> 154:37f96f9d4de2 157 {
<> 154:37f96f9d4de2 158 kDSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the
<> 154:37f96f9d4de2 159 following edge.*/
<> 154:37f96f9d4de2 160 kDSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the
<> 154:37f96f9d4de2 161 following edge.*/
<> 154:37f96f9d4de2 162 } dspi_clock_phase_t;
<> 154:37f96f9d4de2 163
<> 154:37f96f9d4de2 164 /*! @brief DSPI data shifter direction options for a given CTAR.*/
<> 154:37f96f9d4de2 165 typedef enum _dspi_shift_direction
<> 154:37f96f9d4de2 166 {
<> 154:37f96f9d4de2 167 kDSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/
<> 154:37f96f9d4de2 168 kDSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit.*/
<> 154:37f96f9d4de2 169 } dspi_shift_direction_t;
<> 154:37f96f9d4de2 170
<> 154:37f96f9d4de2 171 /*! @brief DSPI delay type selection.*/
<> 154:37f96f9d4de2 172 typedef enum _dspi_delay_type
<> 154:37f96f9d4de2 173 {
<> 154:37f96f9d4de2 174 kDSPI_PcsToSck = 1U, /*!< Pcs-to-SCK delay. */
<> 154:37f96f9d4de2 175 kDSPI_LastSckToPcs, /*!< Last SCK edge to Pcs delay. */
<> 154:37f96f9d4de2 176 kDSPI_BetweenTransfer /*!< Delay between transfers. */
<> 154:37f96f9d4de2 177 } dspi_delay_type_t;
<> 154:37f96f9d4de2 178
<> 154:37f96f9d4de2 179 /*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection.*/
<> 154:37f96f9d4de2 180 typedef enum _dspi_ctar_selection
<> 154:37f96f9d4de2 181 {
<> 154:37f96f9d4de2 182 kDSPI_Ctar0 = 0U, /*!< CTAR0 selection option for master or slave mode, note that CTAR0 and CTAR0_SLAVE are the
<> 154:37f96f9d4de2 183 same register address. */
<> 154:37f96f9d4de2 184 kDSPI_Ctar1 = 1U, /*!< CTAR1 selection option for master mode only. */
<> 154:37f96f9d4de2 185 kDSPI_Ctar2 = 2U, /*!< CTAR2 selection option for master mode only , note that some device do not support CTAR2. */
<> 154:37f96f9d4de2 186 kDSPI_Ctar3 = 3U, /*!< CTAR3 selection option for master mode only , note that some device do not support CTAR3. */
<> 154:37f96f9d4de2 187 kDSPI_Ctar4 = 4U, /*!< CTAR4 selection option for master mode only , note that some device do not support CTAR4. */
<> 154:37f96f9d4de2 188 kDSPI_Ctar5 = 5U, /*!< CTAR5 selection option for master mode only , note that some device do not support CTAR5. */
<> 154:37f96f9d4de2 189 kDSPI_Ctar6 = 6U, /*!< CTAR6 selection option for master mode only , note that some device do not support CTAR6. */
<> 154:37f96f9d4de2 190 kDSPI_Ctar7 = 7U /*!< CTAR7 selection option for master mode only , note that some device do not support CTAR7. */
<> 154:37f96f9d4de2 191 } dspi_ctar_selection_t;
<> 154:37f96f9d4de2 192
<> 154:37f96f9d4de2 193 #define DSPI_MASTER_CTAR_SHIFT (0U) /*!< DSPI master CTAR shift macro , internal used. */
<> 154:37f96f9d4de2 194 #define DSPI_MASTER_CTAR_MASK (0x0FU) /*!< DSPI master CTAR mask macro , internal used. */
<> 154:37f96f9d4de2 195 #define DSPI_MASTER_PCS_SHIFT (4U) /*!< DSPI master PCS shift macro , internal used. */
<> 154:37f96f9d4de2 196 #define DSPI_MASTER_PCS_MASK (0xF0U) /*!< DSPI master PCS mask macro , internal used. */
<> 154:37f96f9d4de2 197 /*! @brief Can use this enumeration for DSPI master transfer configFlags. */
<> 154:37f96f9d4de2 198 enum _dspi_transfer_config_flag_for_master
<> 154:37f96f9d4de2 199 {
<> 154:37f96f9d4de2 200 kDSPI_MasterCtar0 = 0U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR0 setting. */
<> 154:37f96f9d4de2 201 kDSPI_MasterCtar1 = 1U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR1 setting. */
<> 154:37f96f9d4de2 202 kDSPI_MasterCtar2 = 2U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR2 setting. */
<> 154:37f96f9d4de2 203 kDSPI_MasterCtar3 = 3U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR3 setting. */
<> 154:37f96f9d4de2 204 kDSPI_MasterCtar4 = 4U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR4 setting. */
<> 154:37f96f9d4de2 205 kDSPI_MasterCtar5 = 5U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR5 setting. */
<> 154:37f96f9d4de2 206 kDSPI_MasterCtar6 = 6U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR6 setting. */
<> 154:37f96f9d4de2 207 kDSPI_MasterCtar7 = 7U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR7 setting. */
<> 154:37f96f9d4de2 208
<> 154:37f96f9d4de2 209 kDSPI_MasterPcs0 = 0U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS0 signal. */
<> 154:37f96f9d4de2 210 kDSPI_MasterPcs1 = 1U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS1 signal. */
<> 154:37f96f9d4de2 211 kDSPI_MasterPcs2 = 2U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS2 signal.*/
<> 154:37f96f9d4de2 212 kDSPI_MasterPcs3 = 3U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS3 signal. */
<> 154:37f96f9d4de2 213 kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS4 signal. */
<> 154:37f96f9d4de2 214 kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS5 signal. */
<> 154:37f96f9d4de2 215
<> 154:37f96f9d4de2 216 kDSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous. */
<> 154:37f96f9d4de2 217 kDSPI_MasterActiveAfterTransfer = 1U << 21, /*!< Is PCS signal active after last frame transfer.*/
<> 154:37f96f9d4de2 218 };
<> 154:37f96f9d4de2 219
<> 154:37f96f9d4de2 220 #define DSPI_SLAVE_CTAR_SHIFT (0U) /*!< DSPI slave CTAR shift macro , internal used. */
<> 154:37f96f9d4de2 221 #define DSPI_SLAVE_CTAR_MASK (0x07U) /*!< DSPI slave CTAR mask macro , internal used. */
<> 154:37f96f9d4de2 222 /*! @brief Can use this enum for DSPI slave transfer configFlags. */
<> 154:37f96f9d4de2 223 enum _dspi_transfer_config_flag_for_slave
<> 154:37f96f9d4de2 224 {
<> 154:37f96f9d4de2 225 kDSPI_SlaveCtar0 = 0U << DSPI_SLAVE_CTAR_SHIFT, /*!< DSPI slave transfer use CTAR0 setting. */
<> 154:37f96f9d4de2 226 /*!< DSPI slave can only use PCS0. */
<> 154:37f96f9d4de2 227 };
<> 154:37f96f9d4de2 228
<> 154:37f96f9d4de2 229 /*! @brief DSPI transfer state, which is used for DSPI transactional API state machine. */
<> 154:37f96f9d4de2 230 enum _dspi_transfer_state
<> 154:37f96f9d4de2 231 {
<> 154:37f96f9d4de2 232 kDSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */
<> 154:37f96f9d4de2 233 kDSPI_Busy, /*!< Transfer queue is not finished. */
<> 154:37f96f9d4de2 234 kDSPI_Error /*!< Transfer error. */
<> 154:37f96f9d4de2 235 };
<> 154:37f96f9d4de2 236
<> 154:37f96f9d4de2 237 /*! @brief DSPI master command date configuration used for SPIx_PUSHR.*/
<> 154:37f96f9d4de2 238 typedef struct _dspi_command_data_config
<> 154:37f96f9d4de2 239 {
<> 154:37f96f9d4de2 240 bool isPcsContinuous; /*!< Option to enable the continuous assertion of chip select between transfers.*/
<> 154:37f96f9d4de2 241 dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes
<> 154:37f96f9d4de2 242 Register (CTAR) to use for CTAS.*/
<> 154:37f96f9d4de2 243 dspi_which_pcs_t whichPcs; /*!< The desired PCS signal to use for the data transfer.*/
<> 154:37f96f9d4de2 244 bool isEndOfQueue; /*!< Signals that the current transfer is the last in the queue.*/
<> 154:37f96f9d4de2 245 bool clearTransferCount; /*!< Clears SPI Transfer Counter (SPI_TCNT) before transmission starts.*/
<> 154:37f96f9d4de2 246 } dspi_command_data_config_t;
<> 154:37f96f9d4de2 247
<> 154:37f96f9d4de2 248 /*! @brief DSPI master ctar configuration structure.*/
<> 154:37f96f9d4de2 249 typedef struct _dspi_master_ctar_config
<> 154:37f96f9d4de2 250 {
<> 154:37f96f9d4de2 251 uint32_t baudRate; /*!< Baud Rate for DSPI. */
<> 154:37f96f9d4de2 252 uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16.*/
<> 154:37f96f9d4de2 253 dspi_clock_polarity_t cpol; /*!< Clock polarity. */
<> 154:37f96f9d4de2 254 dspi_clock_phase_t cpha; /*!< Clock phase. */
<> 154:37f96f9d4de2 255 dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */
<> 154:37f96f9d4de2 256
<> 154:37f96f9d4de2 257 uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time with nanosecond , set to 0 sets the minimum
<> 154:37f96f9d4de2 258 delay. It sets the boundary value if out of range that can be set.*/
<> 154:37f96f9d4de2 259 uint32_t lastSckToPcsDelayInNanoSec; /*!< Last SCK to PCS delay time with nanosecond , set to 0 sets the
<> 154:37f96f9d4de2 260 minimum delay.It sets the boundary value if out of range that can be
<> 154:37f96f9d4de2 261 set.*/
<> 154:37f96f9d4de2 262 uint32_t betweenTransferDelayInNanoSec; /*!< After SCK delay time with nanosecond , set to 0 sets the minimum
<> 154:37f96f9d4de2 263 delay.It sets the boundary value if out of range that can be set.*/
<> 154:37f96f9d4de2 264 } dspi_master_ctar_config_t;
<> 154:37f96f9d4de2 265
<> 154:37f96f9d4de2 266 /*! @brief DSPI master configuration structure.*/
<> 154:37f96f9d4de2 267 typedef struct _dspi_master_config
<> 154:37f96f9d4de2 268 {
<> 154:37f96f9d4de2 269 dspi_ctar_selection_t whichCtar; /*!< Desired CTAR to use. */
<> 154:37f96f9d4de2 270 dspi_master_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */
<> 154:37f96f9d4de2 271
<> 154:37f96f9d4de2 272 dspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (pcs). */
<> 154:37f96f9d4de2 273 dspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low. */
<> 154:37f96f9d4de2 274
<> 154:37f96f9d4de2 275 bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable . Note that continuous SCK is only
<> 154:37f96f9d4de2 276 supported for CPHA = 1.*/
<> 154:37f96f9d4de2 277 bool enableRxFifoOverWrite; /*!< ROOE, Receive FIFO overflow overwrite enable. ROOE = 0, the incoming
<> 154:37f96f9d4de2 278 data is ignored, the data from the transfer that generated the overflow
<> 154:37f96f9d4de2 279 is either ignored. ROOE = 1, the incoming data is shifted in to the
<> 154:37f96f9d4de2 280 shift to the shift register. */
<> 154:37f96f9d4de2 281
<> 154:37f96f9d4de2 282 bool enableModifiedTimingFormat; /*!< Enables a modified transfer format to be used if it's true.*/
<> 154:37f96f9d4de2 283 dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in Modified Transfer
<> 154:37f96f9d4de2 284 Format. It's valid only when CPHA=0. */
<> 154:37f96f9d4de2 285 } dspi_master_config_t;
<> 154:37f96f9d4de2 286
<> 154:37f96f9d4de2 287 /*! @brief DSPI slave ctar configuration structure.*/
<> 154:37f96f9d4de2 288 typedef struct _dspi_slave_ctar_config
<> 154:37f96f9d4de2 289 {
<> 154:37f96f9d4de2 290 uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16.*/
<> 154:37f96f9d4de2 291 dspi_clock_polarity_t cpol; /*!< Clock polarity. */
<> 154:37f96f9d4de2 292 dspi_clock_phase_t cpha; /*!< Clock phase. */
<> 154:37f96f9d4de2 293 /*!< Slave only supports MSB , does not support LSB.*/
<> 154:37f96f9d4de2 294 } dspi_slave_ctar_config_t;
<> 154:37f96f9d4de2 295
<> 154:37f96f9d4de2 296 /*! @brief DSPI slave configuration structure.*/
<> 154:37f96f9d4de2 297 typedef struct _dspi_slave_config
<> 154:37f96f9d4de2 298 {
<> 154:37f96f9d4de2 299 dspi_ctar_selection_t whichCtar; /*!< Desired CTAR to use. */
<> 154:37f96f9d4de2 300 dspi_slave_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */
<> 154:37f96f9d4de2 301
<> 154:37f96f9d4de2 302 bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable. Note that continuous SCK is only
<> 154:37f96f9d4de2 303 supported for CPHA = 1.*/
<> 154:37f96f9d4de2 304 bool enableRxFifoOverWrite; /*!< ROOE, Receive FIFO overflow overwrite enable. ROOE = 0, the incoming
<> 154:37f96f9d4de2 305 data is ignored, the data from the transfer that generated the overflow
<> 154:37f96f9d4de2 306 is either ignored. ROOE = 1, the incoming data is shifted in to the
<> 154:37f96f9d4de2 307 shift to the shift register. */
<> 154:37f96f9d4de2 308 bool enableModifiedTimingFormat; /*!< Enables a modified transfer format to be used if it's true.*/
<> 154:37f96f9d4de2 309 dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in Modified Transfer
<> 154:37f96f9d4de2 310 Format. It's valid only when CPHA=0. */
<> 154:37f96f9d4de2 311 } dspi_slave_config_t;
<> 154:37f96f9d4de2 312
<> 154:37f96f9d4de2 313 /*!
<> 154:37f96f9d4de2 314 * @brief Forward declaration of the _dspi_master_handle typedefs.
<> 154:37f96f9d4de2 315 */
<> 154:37f96f9d4de2 316 typedef struct _dspi_master_handle dspi_master_handle_t;
<> 154:37f96f9d4de2 317
<> 154:37f96f9d4de2 318 /*!
<> 154:37f96f9d4de2 319 * @brief Forward declaration of the _dspi_slave_handle typedefs.
<> 154:37f96f9d4de2 320 */
<> 154:37f96f9d4de2 321 typedef struct _dspi_slave_handle dspi_slave_handle_t;
<> 154:37f96f9d4de2 322
<> 154:37f96f9d4de2 323 /*!
<> 154:37f96f9d4de2 324 * @brief Completion callback function pointer type.
<> 154:37f96f9d4de2 325 *
<> 154:37f96f9d4de2 326 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 327 * @param handle Pointer to the handle for the DSPI master.
<> 154:37f96f9d4de2 328 * @param status Success or error code describing whether the transfer completed.
<> 154:37f96f9d4de2 329 * @param userData Arbitrary pointer-dataSized value passed from the application.
<> 154:37f96f9d4de2 330 */
<> 154:37f96f9d4de2 331 typedef void (*dspi_master_transfer_callback_t)(SPI_Type *base,
<> 154:37f96f9d4de2 332 dspi_master_handle_t *handle,
<> 154:37f96f9d4de2 333 status_t status,
<> 154:37f96f9d4de2 334 void *userData);
<> 154:37f96f9d4de2 335 /*!
<> 154:37f96f9d4de2 336 * @brief Completion callback function pointer type.
<> 154:37f96f9d4de2 337 *
<> 154:37f96f9d4de2 338 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 339 * @param handle Pointer to the handle for the DSPI slave.
<> 154:37f96f9d4de2 340 * @param status Success or error code describing whether the transfer completed.
<> 154:37f96f9d4de2 341 * @param userData Arbitrary pointer-dataSized value passed from the application.
<> 154:37f96f9d4de2 342 */
<> 154:37f96f9d4de2 343 typedef void (*dspi_slave_transfer_callback_t)(SPI_Type *base,
<> 154:37f96f9d4de2 344 dspi_slave_handle_t *handle,
<> 154:37f96f9d4de2 345 status_t status,
<> 154:37f96f9d4de2 346 void *userData);
<> 154:37f96f9d4de2 347
<> 154:37f96f9d4de2 348 /*! @brief DSPI master/slave transfer structure.*/
<> 154:37f96f9d4de2 349 typedef struct _dspi_transfer
<> 154:37f96f9d4de2 350 {
<> 154:37f96f9d4de2 351 uint8_t *txData; /*!< Send buffer. */
<> 154:37f96f9d4de2 352 uint8_t *rxData; /*!< Receive buffer. */
<> 154:37f96f9d4de2 353 volatile size_t dataSize; /*!< Transfer bytes. */
<> 154:37f96f9d4de2 354
<> 154:37f96f9d4de2 355 uint32_t
<> 154:37f96f9d4de2 356 configFlags; /*!< Transfer transfer configuration flags , set from _dspi_transfer_config_flag_for_master if the
<> 154:37f96f9d4de2 357 transfer is used for master or _dspi_transfer_config_flag_for_slave enumeration if the transfer
<> 154:37f96f9d4de2 358 is used for slave.*/
<> 154:37f96f9d4de2 359 } dspi_transfer_t;
<> 154:37f96f9d4de2 360
<> 154:37f96f9d4de2 361 /*! @brief DSPI master transfer handle structure used for transactional API. */
<> 154:37f96f9d4de2 362 struct _dspi_master_handle
<> 154:37f96f9d4de2 363 {
<> 154:37f96f9d4de2 364 uint32_t bitsPerFrame; /*!< Desired number of bits per frame. */
<> 154:37f96f9d4de2 365 volatile uint32_t command; /*!< Desired data command. */
<> 154:37f96f9d4de2 366 volatile uint32_t lastCommand; /*!< Desired last data command. */
<> 154:37f96f9d4de2 367
<> 154:37f96f9d4de2 368 uint8_t fifoSize; /*!< FIFO dataSize. */
<> 154:37f96f9d4de2 369
<> 154:37f96f9d4de2 370 volatile bool isPcsActiveAfterTransfer; /*!< Is PCS signal keep active after the last frame transfer.*/
<> 154:37f96f9d4de2 371 volatile bool isThereExtraByte; /*!< Is there extra byte.*/
<> 154:37f96f9d4de2 372
<> 154:37f96f9d4de2 373 uint8_t *volatile txData; /*!< Send buffer. */
<> 154:37f96f9d4de2 374 uint8_t *volatile rxData; /*!< Receive buffer. */
<> 154:37f96f9d4de2 375 volatile size_t remainingSendByteCount; /*!< Number of bytes remaining to send.*/
<> 154:37f96f9d4de2 376 volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
<> 154:37f96f9d4de2 377 size_t totalByteCount; /*!< Number of transfer bytes*/
<> 154:37f96f9d4de2 378
<> 154:37f96f9d4de2 379 volatile uint8_t state; /*!< DSPI transfer state , _dspi_transfer_state.*/
<> 154:37f96f9d4de2 380
<> 154:37f96f9d4de2 381 dspi_master_transfer_callback_t callback; /*!< Completion callback. */
<> 154:37f96f9d4de2 382 void *userData; /*!< Callback user data. */
<> 154:37f96f9d4de2 383 };
<> 154:37f96f9d4de2 384
<> 154:37f96f9d4de2 385 /*! @brief DSPI slave transfer handle structure used for transactional API. */
<> 154:37f96f9d4de2 386 struct _dspi_slave_handle
<> 154:37f96f9d4de2 387 {
<> 154:37f96f9d4de2 388 uint32_t bitsPerFrame; /*!< Desired number of bits per frame. */
<> 154:37f96f9d4de2 389 volatile bool isThereExtraByte; /*!< Is there extra byte.*/
<> 154:37f96f9d4de2 390
<> 154:37f96f9d4de2 391 uint8_t *volatile txData; /*!< Send buffer. */
<> 154:37f96f9d4de2 392 uint8_t *volatile rxData; /*!< Receive buffer. */
<> 154:37f96f9d4de2 393 volatile size_t remainingSendByteCount; /*!< Number of bytes remaining to send.*/
<> 154:37f96f9d4de2 394 volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
<> 154:37f96f9d4de2 395 size_t totalByteCount; /*!< Number of transfer bytes*/
<> 154:37f96f9d4de2 396
<> 154:37f96f9d4de2 397 volatile uint8_t state; /*!< DSPI transfer state.*/
<> 154:37f96f9d4de2 398
<> 154:37f96f9d4de2 399 volatile uint32_t errorCount; /*!< Error count for slave transfer.*/
<> 154:37f96f9d4de2 400
<> 154:37f96f9d4de2 401 dspi_slave_transfer_callback_t callback; /*!< Completion callback. */
<> 154:37f96f9d4de2 402 void *userData; /*!< Callback user data. */
<> 154:37f96f9d4de2 403 };
<> 154:37f96f9d4de2 404
<> 154:37f96f9d4de2 405 /**********************************************************************************************************************
<> 154:37f96f9d4de2 406 * API
<> 154:37f96f9d4de2 407 *********************************************************************************************************************/
<> 154:37f96f9d4de2 408 #if defined(__cplusplus)
<> 154:37f96f9d4de2 409 extern "C" {
<> 154:37f96f9d4de2 410 #endif /*_cplusplus*/
<> 154:37f96f9d4de2 411
<> 154:37f96f9d4de2 412 /*!
<> 154:37f96f9d4de2 413 * @name Initialization and deinitialization
<> 154:37f96f9d4de2 414 * @{
<> 154:37f96f9d4de2 415 */
<> 154:37f96f9d4de2 416
<> 154:37f96f9d4de2 417 /*!
<> 154:37f96f9d4de2 418 * @brief Initializes the DSPI master.
<> 154:37f96f9d4de2 419 *
<> 154:37f96f9d4de2 420 * This function initializes the DSPI master configuration. An example use case is as follows:
<> 154:37f96f9d4de2 421 * @code
<> 154:37f96f9d4de2 422 * dspi_master_config_t masterConfig;
<> 154:37f96f9d4de2 423 * masterConfig.whichCtar = kDSPI_Ctar0;
<> 154:37f96f9d4de2 424 * masterConfig.ctarConfig.baudRate = 500000000;
<> 154:37f96f9d4de2 425 * masterConfig.ctarConfig.bitsPerFrame = 8;
<> 154:37f96f9d4de2 426 * masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
<> 154:37f96f9d4de2 427 * masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
<> 154:37f96f9d4de2 428 * masterConfig.ctarConfig.direction = kDSPI_MsbFirst;
<> 154:37f96f9d4de2 429 * masterConfig.ctarConfig.pcsToSckDelayInNanoSec = 1000000000 / masterConfig.ctarConfig.baudRate ;
<> 154:37f96f9d4de2 430 * masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig.ctarConfig.baudRate ;
<> 154:37f96f9d4de2 431 * masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.ctarConfig.baudRate ;
<> 154:37f96f9d4de2 432 * masterConfig.whichPcs = kDSPI_Pcs0;
<> 154:37f96f9d4de2 433 * masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow;
<> 154:37f96f9d4de2 434 * masterConfig.enableContinuousSCK = false;
<> 154:37f96f9d4de2 435 * masterConfig.enableRxFifoOverWrite = false;
<> 154:37f96f9d4de2 436 * masterConfig.enableModifiedTimingFormat = false;
<> 154:37f96f9d4de2 437 * masterConfig.samplePoint = kDSPI_SckToSin0Clock;
<> 154:37f96f9d4de2 438 * DSPI_MasterInit(base, &masterConfig, srcClock_Hz);
<> 154:37f96f9d4de2 439 * @endcode
<> 154:37f96f9d4de2 440 *
<> 154:37f96f9d4de2 441 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 442 * @param masterConfig Pointer to structure dspi_master_config_t.
<> 154:37f96f9d4de2 443 * @param srcClock_Hz Module source input clock in Hertz
<> 154:37f96f9d4de2 444 */
<> 154:37f96f9d4de2 445 void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz);
<> 154:37f96f9d4de2 446
<> 154:37f96f9d4de2 447 /*!
<> 154:37f96f9d4de2 448 * @brief Sets the dspi_master_config_t structure to default values.
<> 154:37f96f9d4de2 449 *
<> 154:37f96f9d4de2 450 * The purpose of this API is to get the configuration structure initialized for the DSPI_MasterInit().
<> 154:37f96f9d4de2 451 * User may use the initialized structure unchanged in DSPI_MasterInit() or modify the structure
<> 154:37f96f9d4de2 452 * before calling DSPI_MasterInit().
<> 154:37f96f9d4de2 453 * Example:
<> 154:37f96f9d4de2 454 * @code
<> 154:37f96f9d4de2 455 * dspi_master_config_t masterConfig;
<> 154:37f96f9d4de2 456 * DSPI_MasterGetDefaultConfig(&masterConfig);
<> 154:37f96f9d4de2 457 * @endcode
<> 154:37f96f9d4de2 458 * @param masterConfig pointer to dspi_master_config_t structure
<> 154:37f96f9d4de2 459 */
<> 154:37f96f9d4de2 460 void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig);
<> 154:37f96f9d4de2 461
<> 154:37f96f9d4de2 462 /*!
<> 154:37f96f9d4de2 463 * @brief DSPI slave configuration.
<> 154:37f96f9d4de2 464 *
<> 154:37f96f9d4de2 465 * This function initializes the DSPI slave configuration. An example use case is as follows:
<> 154:37f96f9d4de2 466 * @code
<> 154:37f96f9d4de2 467 * dspi_slave_config_t slaveConfig;
<> 154:37f96f9d4de2 468 * slaveConfig->whichCtar = kDSPI_Ctar0;
<> 154:37f96f9d4de2 469 * slaveConfig->ctarConfig.bitsPerFrame = 8;
<> 154:37f96f9d4de2 470 * slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
<> 154:37f96f9d4de2 471 * slaveConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
<> 154:37f96f9d4de2 472 * slaveConfig->enableContinuousSCK = false;
<> 154:37f96f9d4de2 473 * slaveConfig->enableRxFifoOverWrite = false;
<> 154:37f96f9d4de2 474 * slaveConfig->enableModifiedTimingFormat = false;
<> 154:37f96f9d4de2 475 * slaveConfig->samplePoint = kDSPI_SckToSin0Clock;
<> 154:37f96f9d4de2 476 * DSPI_SlaveInit(base, &slaveConfig);
<> 154:37f96f9d4de2 477 * @endcode
<> 154:37f96f9d4de2 478 *
<> 154:37f96f9d4de2 479 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 480 * @param slaveConfig Pointer to structure dspi_master_config_t.
<> 154:37f96f9d4de2 481 */
<> 154:37f96f9d4de2 482 void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig);
<> 154:37f96f9d4de2 483
<> 154:37f96f9d4de2 484 /*!
<> 154:37f96f9d4de2 485 * @brief Sets the dspi_slave_config_t structure to default values.
<> 154:37f96f9d4de2 486 *
<> 154:37f96f9d4de2 487 * The purpose of this API is to get the configuration structure initialized for the DSPI_SlaveInit().
<> 154:37f96f9d4de2 488 * User may use the initialized structure unchanged in DSPI_SlaveInit(), or modify the structure
<> 154:37f96f9d4de2 489 * before calling DSPI_SlaveInit().
<> 154:37f96f9d4de2 490 * Example:
<> 154:37f96f9d4de2 491 * @code
<> 154:37f96f9d4de2 492 * dspi_slave_config_t slaveConfig;
<> 154:37f96f9d4de2 493 * DSPI_SlaveGetDefaultConfig(&slaveConfig);
<> 154:37f96f9d4de2 494 * @endcode
<> 154:37f96f9d4de2 495 * @param slaveConfig pointer to dspi_slave_config_t structure.
<> 154:37f96f9d4de2 496 */
<> 154:37f96f9d4de2 497 void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig);
<> 154:37f96f9d4de2 498
<> 154:37f96f9d4de2 499 /*!
<> 154:37f96f9d4de2 500 * @brief De-initializes the DSPI peripheral. Call this API to disable the DSPI clock.
<> 154:37f96f9d4de2 501 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 502 */
<> 154:37f96f9d4de2 503 void DSPI_Deinit(SPI_Type *base);
<> 154:37f96f9d4de2 504
<> 154:37f96f9d4de2 505 /*!
<> 154:37f96f9d4de2 506 * @brief Enables the DSPI peripheral and sets the MCR MDIS to 0.
<> 154:37f96f9d4de2 507 *
<> 154:37f96f9d4de2 508 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 509 * @param enable pass true to enable module, false to disable module.
<> 154:37f96f9d4de2 510 */
<> 154:37f96f9d4de2 511 static inline void DSPI_Enable(SPI_Type *base, bool enable)
<> 154:37f96f9d4de2 512 {
<> 154:37f96f9d4de2 513 if (enable)
<> 154:37f96f9d4de2 514 {
<> 154:37f96f9d4de2 515 base->MCR &= ~SPI_MCR_MDIS_MASK;
<> 154:37f96f9d4de2 516 }
<> 154:37f96f9d4de2 517 else
<> 154:37f96f9d4de2 518 {
<> 154:37f96f9d4de2 519 base->MCR |= SPI_MCR_MDIS_MASK;
<> 154:37f96f9d4de2 520 }
<> 154:37f96f9d4de2 521 }
<> 154:37f96f9d4de2 522
<> 154:37f96f9d4de2 523 /*!
<> 154:37f96f9d4de2 524 *@}
<> 154:37f96f9d4de2 525 */
<> 154:37f96f9d4de2 526
<> 154:37f96f9d4de2 527 /*!
<> 154:37f96f9d4de2 528 * @name Status
<> 154:37f96f9d4de2 529 * @{
<> 154:37f96f9d4de2 530 */
<> 154:37f96f9d4de2 531
<> 154:37f96f9d4de2 532 /*!
<> 154:37f96f9d4de2 533 * @brief Gets the DSPI status flag state.
<> 154:37f96f9d4de2 534 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 535 * @return The DSPI status(in SR register).
<> 154:37f96f9d4de2 536 */
<> 154:37f96f9d4de2 537 static inline uint32_t DSPI_GetStatusFlags(SPI_Type *base)
<> 154:37f96f9d4de2 538 {
<> 154:37f96f9d4de2 539 return (base->SR);
<> 154:37f96f9d4de2 540 }
<> 154:37f96f9d4de2 541
<> 154:37f96f9d4de2 542 /*!
<> 154:37f96f9d4de2 543 * @brief Clears the DSPI status flag.
<> 154:37f96f9d4de2 544 *
<> 154:37f96f9d4de2 545 * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the
<> 154:37f96f9d4de2 546 * desired status bit to clear. The list of status bits is defined in the dspi_status_and_interrupt_request_t. The
<> 154:37f96f9d4de2 547 * function uses these bit positions in its algorithm to clear the desired flag state.
<> 154:37f96f9d4de2 548 * Example usage:
<> 154:37f96f9d4de2 549 * @code
<> 154:37f96f9d4de2 550 * DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag|kDSPI_EndOfQueueFlag);
<> 154:37f96f9d4de2 551 * @endcode
<> 154:37f96f9d4de2 552 *
<> 154:37f96f9d4de2 553 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 554 * @param statusFlags The status flag , used from type dspi_flags.
<> 154:37f96f9d4de2 555 */
<> 154:37f96f9d4de2 556 static inline void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags)
<> 154:37f96f9d4de2 557 {
<> 154:37f96f9d4de2 558 base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/
<> 154:37f96f9d4de2 559 }
<> 154:37f96f9d4de2 560
<> 154:37f96f9d4de2 561 /*!
<> 154:37f96f9d4de2 562 *@}
<> 154:37f96f9d4de2 563 */
<> 154:37f96f9d4de2 564
<> 154:37f96f9d4de2 565 /*!
<> 154:37f96f9d4de2 566 * @name Interrupts
<> 154:37f96f9d4de2 567 * @{
<> 154:37f96f9d4de2 568 */
<> 154:37f96f9d4de2 569
<> 154:37f96f9d4de2 570 /*!
<> 154:37f96f9d4de2 571 * @brief Enables the DSPI interrupts.
<> 154:37f96f9d4de2 572 *
<> 154:37f96f9d4de2 573 * This function configures the various interrupt masks of the DSPI. The parameters are base and an interrupt mask.
<> 154:37f96f9d4de2 574 * Note, for Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request.
<> 154:37f96f9d4de2 575 *
<> 154:37f96f9d4de2 576 * @code
<> 154:37f96f9d4de2 577 * DSPI_EnableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable );
<> 154:37f96f9d4de2 578 * @endcode
<> 154:37f96f9d4de2 579 *
<> 154:37f96f9d4de2 580 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 581 * @param mask The interrupt mask, can use the enum _dspi_interrupt_enable.
<> 154:37f96f9d4de2 582 */
<> 154:37f96f9d4de2 583 void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask);
<> 154:37f96f9d4de2 584
<> 154:37f96f9d4de2 585 /*!
<> 154:37f96f9d4de2 586 * @brief Disables the DSPI interrupts.
<> 154:37f96f9d4de2 587 *
<> 154:37f96f9d4de2 588 * @code
<> 154:37f96f9d4de2 589 * DSPI_DisableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable );
<> 154:37f96f9d4de2 590 * @endcode
<> 154:37f96f9d4de2 591 *
<> 154:37f96f9d4de2 592 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 593 * @param mask The interrupt mask, can use the enum _dspi_interrupt_enable.
<> 154:37f96f9d4de2 594 */
<> 154:37f96f9d4de2 595 static inline void DSPI_DisableInterrupts(SPI_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 596 {
<> 154:37f96f9d4de2 597 base->RSER &= ~mask;
<> 154:37f96f9d4de2 598 }
<> 154:37f96f9d4de2 599
<> 154:37f96f9d4de2 600 /*!
<> 154:37f96f9d4de2 601 *@}
<> 154:37f96f9d4de2 602 */
<> 154:37f96f9d4de2 603
<> 154:37f96f9d4de2 604 /*!
<> 154:37f96f9d4de2 605 * @name DMA Control
<> 154:37f96f9d4de2 606 * @{
<> 154:37f96f9d4de2 607 */
<> 154:37f96f9d4de2 608
<> 154:37f96f9d4de2 609 /*!
<> 154:37f96f9d4de2 610 * @brief Enables the DSPI DMA request.
<> 154:37f96f9d4de2 611 *
<> 154:37f96f9d4de2 612 * This function configures the Rx and Tx DMA mask of the DSPI. The parameters are base and a DMA mask.
<> 154:37f96f9d4de2 613 * @code
<> 154:37f96f9d4de2 614 * DSPI_EnableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable);
<> 154:37f96f9d4de2 615 * @endcode
<> 154:37f96f9d4de2 616 *
<> 154:37f96f9d4de2 617 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 618 * @param mask The interrupt mask can use the enum dspi_dma_enable.
<> 154:37f96f9d4de2 619 */
<> 154:37f96f9d4de2 620 static inline void DSPI_EnableDMA(SPI_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 621 {
<> 154:37f96f9d4de2 622 base->RSER |= mask;
<> 154:37f96f9d4de2 623 }
<> 154:37f96f9d4de2 624
<> 154:37f96f9d4de2 625 /*!
<> 154:37f96f9d4de2 626 * @brief Disables the DSPI DMA request.
<> 154:37f96f9d4de2 627 *
<> 154:37f96f9d4de2 628 * This function configures the Rx and Tx DMA mask of the DSPI. The parameters are base and a DMA mask.
<> 154:37f96f9d4de2 629 * @code
<> 154:37f96f9d4de2 630 * SPI_DisableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable);
<> 154:37f96f9d4de2 631 * @endcode
<> 154:37f96f9d4de2 632 *
<> 154:37f96f9d4de2 633 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 634 * @param mask The interrupt mask can use the enum dspi_dma_enable.
<> 154:37f96f9d4de2 635 */
<> 154:37f96f9d4de2 636 static inline void DSPI_DisableDMA(SPI_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 637 {
<> 154:37f96f9d4de2 638 base->RSER &= ~mask;
<> 154:37f96f9d4de2 639 }
<> 154:37f96f9d4de2 640
<> 154:37f96f9d4de2 641 /*!
<> 154:37f96f9d4de2 642 * @brief Gets the DSPI master PUSHR data register address for the DMA operation.
<> 154:37f96f9d4de2 643 *
<> 154:37f96f9d4de2 644 * This function gets the DSPI master PUSHR data register address because this value is needed for the DMA operation.
<> 154:37f96f9d4de2 645 *
<> 154:37f96f9d4de2 646 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 647 * @return The DSPI master PUSHR data register address.
<> 154:37f96f9d4de2 648 */
<> 154:37f96f9d4de2 649 static inline uint32_t DSPI_MasterGetTxRegisterAddress(SPI_Type *base)
<> 154:37f96f9d4de2 650 {
<> 154:37f96f9d4de2 651 return (uint32_t) & (base->PUSHR);
<> 154:37f96f9d4de2 652 }
<> 154:37f96f9d4de2 653
<> 154:37f96f9d4de2 654 /*!
<> 154:37f96f9d4de2 655 * @brief Gets the DSPI slave PUSHR data register address for the DMA operation.
<> 154:37f96f9d4de2 656 *
<> 154:37f96f9d4de2 657 * This function gets the DSPI slave PUSHR data register address as this value is needed for the DMA operation.
<> 154:37f96f9d4de2 658 *
<> 154:37f96f9d4de2 659 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 660 * @return The DSPI slave PUSHR data register address.
<> 154:37f96f9d4de2 661 */
<> 154:37f96f9d4de2 662 static inline uint32_t DSPI_SlaveGetTxRegisterAddress(SPI_Type *base)
<> 154:37f96f9d4de2 663 {
<> 154:37f96f9d4de2 664 return (uint32_t) & (base->PUSHR_SLAVE);
<> 154:37f96f9d4de2 665 }
<> 154:37f96f9d4de2 666
<> 154:37f96f9d4de2 667 /*!
<> 154:37f96f9d4de2 668 * @brief Gets the DSPI POPR data register address for the DMA operation.
<> 154:37f96f9d4de2 669 *
<> 154:37f96f9d4de2 670 * This function gets the DSPI POPR data register address as this value is needed for the DMA operation.
<> 154:37f96f9d4de2 671 *
<> 154:37f96f9d4de2 672 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 673 * @return The DSPI POPR data register address.
<> 154:37f96f9d4de2 674 */
<> 154:37f96f9d4de2 675 static inline uint32_t DSPI_GetRxRegisterAddress(SPI_Type *base)
<> 154:37f96f9d4de2 676 {
<> 154:37f96f9d4de2 677 return (uint32_t) & (base->POPR);
<> 154:37f96f9d4de2 678 }
<> 154:37f96f9d4de2 679
<> 154:37f96f9d4de2 680 /*!
<> 154:37f96f9d4de2 681 *@}
<> 154:37f96f9d4de2 682 */
<> 154:37f96f9d4de2 683
<> 154:37f96f9d4de2 684 /*!
<> 154:37f96f9d4de2 685 * @name Bus Operations
<> 154:37f96f9d4de2 686 * @{
<> 154:37f96f9d4de2 687 */
<> 154:37f96f9d4de2 688
<> 154:37f96f9d4de2 689 /*!
<> 154:37f96f9d4de2 690 * @brief Configures the DSPI for master or slave.
<> 154:37f96f9d4de2 691 *
<> 154:37f96f9d4de2 692 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 693 * @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t.
<> 154:37f96f9d4de2 694 */
<> 154:37f96f9d4de2 695 static inline void DSPI_SetMasterSlaveMode(SPI_Type *base, dspi_master_slave_mode_t mode)
<> 154:37f96f9d4de2 696 {
<> 154:37f96f9d4de2 697 base->MCR = (base->MCR & (~SPI_MCR_MSTR_MASK)) | SPI_MCR_MSTR(mode);
<> 154:37f96f9d4de2 698 }
<> 154:37f96f9d4de2 699
<> 154:37f96f9d4de2 700 /*!
<> 154:37f96f9d4de2 701 * @brief Returns whether the DSPI module is in master mode.
<> 154:37f96f9d4de2 702 *
<> 154:37f96f9d4de2 703 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 704 * @return Returns true if the module is in master mode or false if the module is in slave mode.
<> 154:37f96f9d4de2 705 */
<> 154:37f96f9d4de2 706 static inline bool DSPI_IsMaster(SPI_Type *base)
<> 154:37f96f9d4de2 707 {
<> 154:37f96f9d4de2 708 return (bool)((base->MCR) & SPI_MCR_MSTR_MASK);
<> 154:37f96f9d4de2 709 }
<> 154:37f96f9d4de2 710 /*!
<> 154:37f96f9d4de2 711 * @brief Starts the DSPI transfers and clears HALT bit in MCR.
<> 154:37f96f9d4de2 712 *
<> 154:37f96f9d4de2 713 * This function sets the module to begin data transfer in either master or slave mode.
<> 154:37f96f9d4de2 714 *
<> 154:37f96f9d4de2 715 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 716 */
<> 154:37f96f9d4de2 717 static inline void DSPI_StartTransfer(SPI_Type *base)
<> 154:37f96f9d4de2 718 {
<> 154:37f96f9d4de2 719 base->MCR &= ~SPI_MCR_HALT_MASK;
<> 154:37f96f9d4de2 720 }
<> 154:37f96f9d4de2 721 /*!
<> 154:37f96f9d4de2 722 * @brief Stops (halts) DSPI transfers and sets HALT bit in MCR.
<> 154:37f96f9d4de2 723 *
<> 154:37f96f9d4de2 724 * This function stops data transfers in either master or slave mode.
<> 154:37f96f9d4de2 725 *
<> 154:37f96f9d4de2 726 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 727 */
<> 154:37f96f9d4de2 728 static inline void DSPI_StopTransfer(SPI_Type *base)
<> 154:37f96f9d4de2 729 {
<> 154:37f96f9d4de2 730 base->MCR |= SPI_MCR_HALT_MASK;
<> 154:37f96f9d4de2 731 }
<> 154:37f96f9d4de2 732
<> 154:37f96f9d4de2 733 /*!
<> 154:37f96f9d4de2 734 * @brief Enables (or disables) the DSPI FIFOs.
<> 154:37f96f9d4de2 735 *
<> 154:37f96f9d4de2 736 * This function allows the caller to disable/enable the Tx and Rx FIFOs (independently).
<> 154:37f96f9d4de2 737 * Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO configuration. To enable,
<> 154:37f96f9d4de2 738 * the caller must pass in a logic 1 (true).
<> 154:37f96f9d4de2 739 *
<> 154:37f96f9d4de2 740 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 741 * @param enableTxFifo Disables (false) the TX FIFO, else enables (true) the TX FIFO
<> 154:37f96f9d4de2 742 * @param enableRxFifo Disables (false) the RX FIFO, else enables (true) the RX FIFO
<> 154:37f96f9d4de2 743 */
<> 154:37f96f9d4de2 744 static inline void DSPI_SetFifoEnable(SPI_Type *base, bool enableTxFifo, bool enableRxFifo)
<> 154:37f96f9d4de2 745 {
<> 154:37f96f9d4de2 746 base->MCR = (base->MCR & (~(SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK))) | SPI_MCR_DIS_TXF(!enableTxFifo) |
<> 154:37f96f9d4de2 747 SPI_MCR_DIS_RXF(!enableRxFifo);
<> 154:37f96f9d4de2 748 }
<> 154:37f96f9d4de2 749
<> 154:37f96f9d4de2 750 /*!
<> 154:37f96f9d4de2 751 * @brief Flushes the DSPI FIFOs.
<> 154:37f96f9d4de2 752 *
<> 154:37f96f9d4de2 753 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 754 * @param flushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO
<> 154:37f96f9d4de2 755 * @param flushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO
<> 154:37f96f9d4de2 756 */
<> 154:37f96f9d4de2 757 static inline void DSPI_FlushFifo(SPI_Type *base, bool flushTxFifo, bool flushRxFifo)
<> 154:37f96f9d4de2 758 {
<> 154:37f96f9d4de2 759 base->MCR = (base->MCR & (~(SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK))) | SPI_MCR_CLR_TXF(flushTxFifo) |
<> 154:37f96f9d4de2 760 SPI_MCR_CLR_RXF(flushRxFifo);
<> 154:37f96f9d4de2 761 }
<> 154:37f96f9d4de2 762
<> 154:37f96f9d4de2 763 /*!
<> 154:37f96f9d4de2 764 * @brief Configures the DSPI peripheral chip select polarity simultaneously.
<> 154:37f96f9d4de2 765 * For example, PCS0 and PCS1 set to active low and other PCS set to active high. Note that the number of
<> 154:37f96f9d4de2 766 * PCSs is specific to the device.
<> 154:37f96f9d4de2 767 * @code
<> 154:37f96f9d4de2 768 * DSPI_SetAllPcsPolarity(base, kDSPI_Pcs0ActiveLow | kDSPI_Pcs1ActiveLow);
<> 154:37f96f9d4de2 769 @endcode
<> 154:37f96f9d4de2 770 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 771 * @param mask The PCS polarity mask , can use the enum _dspi_pcs_polarity.
<> 154:37f96f9d4de2 772 */
<> 154:37f96f9d4de2 773 static inline void DSPI_SetAllPcsPolarity(SPI_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 774 {
<> 154:37f96f9d4de2 775 base->MCR = (base->MCR & ~SPI_MCR_PCSIS_MASK) | SPI_MCR_PCSIS(mask);
<> 154:37f96f9d4de2 776 }
<> 154:37f96f9d4de2 777
<> 154:37f96f9d4de2 778 /*!
<> 154:37f96f9d4de2 779 * @brief Sets the DSPI baud rate in bits per second.
<> 154:37f96f9d4de2 780 *
<> 154:37f96f9d4de2 781 * This function takes in the desired baudRate_Bps (baud rate) and calculates the nearest possible baud rate without
<> 154:37f96f9d4de2 782 * exceeding the desired baud rate, and returns the calculated baud rate in bits-per-second. It requires that the
<> 154:37f96f9d4de2 783 * caller also provide the frequency of the module source clock (in Hertz).
<> 154:37f96f9d4de2 784 *
<> 154:37f96f9d4de2 785 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 786 * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type dspi_ctar_selection_t
<> 154:37f96f9d4de2 787 * @param baudRate_Bps The desired baud rate in bits per second
<> 154:37f96f9d4de2 788 * @param srcClock_Hz Module source input clock in Hertz
<> 154:37f96f9d4de2 789 * @return The actual calculated baud rate
<> 154:37f96f9d4de2 790 */
<> 154:37f96f9d4de2 791 uint32_t DSPI_MasterSetBaudRate(SPI_Type *base,
<> 154:37f96f9d4de2 792 dspi_ctar_selection_t whichCtar,
<> 154:37f96f9d4de2 793 uint32_t baudRate_Bps,
<> 154:37f96f9d4de2 794 uint32_t srcClock_Hz);
<> 154:37f96f9d4de2 795
<> 154:37f96f9d4de2 796 /*!
<> 154:37f96f9d4de2 797 * @brief Manually configures the delay prescaler and scaler for a particular CTAR.
<> 154:37f96f9d4de2 798 *
<> 154:37f96f9d4de2 799 * This function configures the PCS to SCK delay pre-scalar (PcsSCK) and scalar (CSSCK), after SCK delay pre-scalar
<> 154:37f96f9d4de2 800 * (PASC) and scalar (ASC), and the delay after transfer pre-scalar (PDT)and scalar (DT).
<> 154:37f96f9d4de2 801 *
<> 154:37f96f9d4de2 802 * These delay names are available in type dspi_delay_type_t.
<> 154:37f96f9d4de2 803 *
<> 154:37f96f9d4de2 804 * The user passes the delay to configure along with the prescaler and scaler value.
<> 154:37f96f9d4de2 805 * This allows the user to directly set the prescaler/scaler values if they have pre-calculated them or if they simply
<> 154:37f96f9d4de2 806 * wish to manually increment either value.
<> 154:37f96f9d4de2 807 *
<> 154:37f96f9d4de2 808 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 809 * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t.
<> 154:37f96f9d4de2 810 * @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3).
<> 154:37f96f9d4de2 811 * @param scaler The scaler delay value (can be any integer between 0 to 15).
<> 154:37f96f9d4de2 812 * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
<> 154:37f96f9d4de2 813 */
<> 154:37f96f9d4de2 814 void DSPI_MasterSetDelayScaler(
<> 154:37f96f9d4de2 815 SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay);
<> 154:37f96f9d4de2 816
<> 154:37f96f9d4de2 817 /*!
<> 154:37f96f9d4de2 818 * @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds.
<> 154:37f96f9d4de2 819 *
<> 154:37f96f9d4de2 820 * This function calculates the values for:
<> 154:37f96f9d4de2 821 * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or
<> 154:37f96f9d4de2 822 * After SCK delay pre-scalar (PASC) and scalar (ASC), or
<> 154:37f96f9d4de2 823 * Delay after transfer pre-scalar (PDT)and scalar (DT).
<> 154:37f96f9d4de2 824 *
<> 154:37f96f9d4de2 825 * These delay names are available in type dspi_delay_type_t.
<> 154:37f96f9d4de2 826 *
<> 154:37f96f9d4de2 827 * The user passes which delay they want to configure along with the desired delay value in nanoseconds. The function
<> 154:37f96f9d4de2 828 * calculates the values needed for the prescaler and scaler and returning the actual calculated delay as an exact
<> 154:37f96f9d4de2 829 * delay match may not be possible. In this case, the closest match is calculated without going below the desired
<> 154:37f96f9d4de2 830 * delay value input.
<> 154:37f96f9d4de2 831 * It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum
<> 154:37f96f9d4de2 832 * supported delay is returned. The higher-level peripheral driver alerts the user of an out of range delay
<> 154:37f96f9d4de2 833 * input.
<> 154:37f96f9d4de2 834 *
<> 154:37f96f9d4de2 835 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 836 * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t.
<> 154:37f96f9d4de2 837 * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
<> 154:37f96f9d4de2 838 * @param srcClock_Hz Module source input clock in Hertz
<> 154:37f96f9d4de2 839 * @param delayTimeInNanoSec The desired delay value in nanoseconds.
<> 154:37f96f9d4de2 840 * @return The actual calculated delay value.
<> 154:37f96f9d4de2 841 */
<> 154:37f96f9d4de2 842 uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base,
<> 154:37f96f9d4de2 843 dspi_ctar_selection_t whichCtar,
<> 154:37f96f9d4de2 844 dspi_delay_type_t whichDelay,
<> 154:37f96f9d4de2 845 uint32_t srcClock_Hz,
<> 154:37f96f9d4de2 846 uint32_t delayTimeInNanoSec);
<> 154:37f96f9d4de2 847
<> 154:37f96f9d4de2 848 /*!
<> 154:37f96f9d4de2 849 * @brief Writes data into the data buffer for master mode.
<> 154:37f96f9d4de2 850 *
<> 154:37f96f9d4de2 851 * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
<> 154:37f96f9d4de2 852 * provides characteristics of the data such as the optional continuous chip select
<> 154:37f96f9d4de2 853 * operation between transfers, the desired Clock and Transfer Attributes register to use for the
<> 154:37f96f9d4de2 854 * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
<> 154:37f96f9d4de2 855 * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
<> 154:37f96f9d4de2 856 * sending the first frame of a data packet). This is an example:
<> 154:37f96f9d4de2 857 * @code
<> 154:37f96f9d4de2 858 * dspi_command_data_config_t commandConfig;
<> 154:37f96f9d4de2 859 * commandConfig.isPcsContinuous = true;
<> 154:37f96f9d4de2 860 * commandConfig.whichCtar = kDSPICtar0;
<> 154:37f96f9d4de2 861 * commandConfig.whichPcs = kDSPIPcs0;
<> 154:37f96f9d4de2 862 * commandConfig.clearTransferCount = false;
<> 154:37f96f9d4de2 863 * commandConfig.isEndOfQueue = false;
<> 154:37f96f9d4de2 864 * DSPI_MasterWriteData(base, &commandConfig, dataWord);
<> 154:37f96f9d4de2 865 @endcode
<> 154:37f96f9d4de2 866 *
<> 154:37f96f9d4de2 867 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 868 * @param command Pointer to command structure.
<> 154:37f96f9d4de2 869 * @param data The data word to be sent.
<> 154:37f96f9d4de2 870 */
<> 154:37f96f9d4de2 871 static inline void DSPI_MasterWriteData(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data)
<> 154:37f96f9d4de2 872 {
<> 154:37f96f9d4de2 873 base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) |
<> 154:37f96f9d4de2 874 SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) |
<> 154:37f96f9d4de2 875 SPI_PUSHR_CTCNT(command->clearTransferCount) | SPI_PUSHR_TXDATA(data);
<> 154:37f96f9d4de2 876 }
<> 154:37f96f9d4de2 877
<> 154:37f96f9d4de2 878 /*!
<> 154:37f96f9d4de2 879 * @brief Sets the dspi_command_data_config_t structure to default values.
<> 154:37f96f9d4de2 880 *
<> 154:37f96f9d4de2 881 * The purpose of this API is to get the configuration structure initialized for use in the DSPI_MasterWrite_xx().
<> 154:37f96f9d4de2 882 * User may use the initialized structure unchanged in DSPI_MasterWrite_xx() or modify the structure
<> 154:37f96f9d4de2 883 * before calling DSPI_MasterWrite_xx().
<> 154:37f96f9d4de2 884 * Example:
<> 154:37f96f9d4de2 885 * @code
<> 154:37f96f9d4de2 886 * dspi_command_data_config_t command;
<> 154:37f96f9d4de2 887 * DSPI_GetDefaultDataCommandConfig(&command);
<> 154:37f96f9d4de2 888 * @endcode
<> 154:37f96f9d4de2 889 * @param command pointer to dspi_command_data_config_t structure.
<> 154:37f96f9d4de2 890 */
<> 154:37f96f9d4de2 891 void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command);
<> 154:37f96f9d4de2 892
<> 154:37f96f9d4de2 893 /*!
<> 154:37f96f9d4de2 894 * @brief Writes data into the data buffer master mode and waits till complete to return.
<> 154:37f96f9d4de2 895 *
<> 154:37f96f9d4de2 896 * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
<> 154:37f96f9d4de2 897 * provides characteristics of the data such as the optional continuous chip select
<> 154:37f96f9d4de2 898 * operation between transfers, the desired Clock and Transfer Attributes register to use for the
<> 154:37f96f9d4de2 899 * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
<> 154:37f96f9d4de2 900 * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
<> 154:37f96f9d4de2 901 * sending the first frame of a data packet). This is an example:
<> 154:37f96f9d4de2 902 * @code
<> 154:37f96f9d4de2 903 * dspi_command_config_t commandConfig;
<> 154:37f96f9d4de2 904 * commandConfig.isPcsContinuous = true;
<> 154:37f96f9d4de2 905 * commandConfig.whichCtar = kDSPICtar0;
<> 154:37f96f9d4de2 906 * commandConfig.whichPcs = kDSPIPcs1;
<> 154:37f96f9d4de2 907 * commandConfig.clearTransferCount = false;
<> 154:37f96f9d4de2 908 * commandConfig.isEndOfQueue = false;
<> 154:37f96f9d4de2 909 * DSPI_MasterWriteDataBlocking(base, &commandConfig, dataWord);
<> 154:37f96f9d4de2 910 * @endcode
<> 154:37f96f9d4de2 911 *
<> 154:37f96f9d4de2 912 * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be
<> 154:37f96f9d4de2 913 * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). Because the SPI is a synchronous protocol,
<> 154:37f96f9d4de2 914 * receive data is available when transmit completes.
<> 154:37f96f9d4de2 915 *
<> 154:37f96f9d4de2 916 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 917 * @param command Pointer to command structure.
<> 154:37f96f9d4de2 918 * @param data The data word to be sent.
<> 154:37f96f9d4de2 919 */
<> 154:37f96f9d4de2 920 void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data);
<> 154:37f96f9d4de2 921
<> 154:37f96f9d4de2 922 /*!
<> 154:37f96f9d4de2 923 * @brief Returns the DSPI command word formatted to the PUSHR data register bit field.
<> 154:37f96f9d4de2 924 *
<> 154:37f96f9d4de2 925 * This function allows the caller to pass in the data command structure and returns the command word formatted
<> 154:37f96f9d4de2 926 * according to the DSPI PUSHR register bit field placement. The user can then "OR" the returned command word with the
<> 154:37f96f9d4de2 927 * desired data to send and use the function DSPI_HAL_WriteCommandDataMastermode or
<> 154:37f96f9d4de2 928 * DSPI_HAL_WriteCommandDataMastermodeBlocking to write the entire 32-bit command data word to the PUSHR. This helps
<> 154:37f96f9d4de2 929 * improve performance in cases where the command structure is constant. For example, the user calls this function
<> 154:37f96f9d4de2 930 * before starting a transfer to generate the command word. When they are ready to transmit the data, they OR
<> 154:37f96f9d4de2 931 * this formatted command word with the desired data to transmit. This process increases transmit performance when
<> 154:37f96f9d4de2 932 * compared to calling send functions such as DSPI_HAL_WriteDataMastermode which format the command word each time a
<> 154:37f96f9d4de2 933 * data word is to be sent.
<> 154:37f96f9d4de2 934 *
<> 154:37f96f9d4de2 935 * @param command Pointer to command structure.
<> 154:37f96f9d4de2 936 * @return The command word formatted to the PUSHR data register bit field.
<> 154:37f96f9d4de2 937 */
<> 154:37f96f9d4de2 938 static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t *command)
<> 154:37f96f9d4de2 939 {
<> 154:37f96f9d4de2 940 /* Format the 16-bit command word according to the PUSHR data register bit field*/
<> 154:37f96f9d4de2 941 return (uint32_t)(SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) |
<> 154:37f96f9d4de2 942 SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) |
<> 154:37f96f9d4de2 943 SPI_PUSHR_CTCNT(command->clearTransferCount));
<> 154:37f96f9d4de2 944 }
<> 154:37f96f9d4de2 945
<> 154:37f96f9d4de2 946 /*!
<> 154:37f96f9d4de2 947 * @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data
<> 154:37f96f9d4de2 948 * buffer, master mode and waits till complete to return.
<> 154:37f96f9d4de2 949 *
<> 154:37f96f9d4de2 950 * In this function, the user must append the 16-bit data to the 16-bit command info then provide the total 32-bit word
<> 154:37f96f9d4de2 951 * as the data to send.
<> 154:37f96f9d4de2 952 * The command portion provides characteristics of the data such as the optional continuous chip select operation
<> 154:37f96f9d4de2 953 * between
<> 154:37f96f9d4de2 954 * transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the desired PCS
<> 154:37f96f9d4de2 955 * signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the
<> 154:37f96f9d4de2 956 * transfer count (normally needed when sending the first frame of a data packet). The user is responsible for
<> 154:37f96f9d4de2 957 * appending this command with the data to send. This is an example:
<> 154:37f96f9d4de2 958 * @code
<> 154:37f96f9d4de2 959 * dataWord = <16-bit command> | <16-bit data>;
<> 154:37f96f9d4de2 960 * DSPI_HAL_WriteCommandDataMastermodeBlocking(base, dataWord);
<> 154:37f96f9d4de2 961 * @endcode
<> 154:37f96f9d4de2 962 *
<> 154:37f96f9d4de2 963 * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be
<> 154:37f96f9d4de2 964 * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0).
<> 154:37f96f9d4de2 965 * Because the SPI is a synchronous protocol, the receive data is available when transmit completes.
<> 154:37f96f9d4de2 966 *
<> 154:37f96f9d4de2 967 * For a blocking polling transfer, see methods below.
<> 154:37f96f9d4de2 968 * Option 1:
<> 154:37f96f9d4de2 969 * uint32_t command_to_send = DSPI_MasterGetFormattedCommand(&command);
<> 154:37f96f9d4de2 970 * uint32_t data0 = command_to_send | data_need_to_send_0;
<> 154:37f96f9d4de2 971 * uint32_t data1 = command_to_send | data_need_to_send_1;
<> 154:37f96f9d4de2 972 * uint32_t data2 = command_to_send | data_need_to_send_2;
<> 154:37f96f9d4de2 973 *
<> 154:37f96f9d4de2 974 * DSPI_MasterWriteCommandDataBlocking(base,data0);
<> 154:37f96f9d4de2 975 * DSPI_MasterWriteCommandDataBlocking(base,data1);
<> 154:37f96f9d4de2 976 * DSPI_MasterWriteCommandDataBlocking(base,data2);
<> 154:37f96f9d4de2 977 *
<> 154:37f96f9d4de2 978 * Option 2:
<> 154:37f96f9d4de2 979 * DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_0);
<> 154:37f96f9d4de2 980 * DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_1);
<> 154:37f96f9d4de2 981 * DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_2);
<> 154:37f96f9d4de2 982 *
<> 154:37f96f9d4de2 983 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 984 * @param data The data word (command and data combined) to be sent
<> 154:37f96f9d4de2 985 */
<> 154:37f96f9d4de2 986 void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data);
<> 154:37f96f9d4de2 987
<> 154:37f96f9d4de2 988 /*!
<> 154:37f96f9d4de2 989 * @brief Writes data into the data buffer in slave mode.
<> 154:37f96f9d4de2 990 *
<> 154:37f96f9d4de2 991 * In slave mode, up to 16-bit words may be written.
<> 154:37f96f9d4de2 992 *
<> 154:37f96f9d4de2 993 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 994 * @param data The data to send.
<> 154:37f96f9d4de2 995 */
<> 154:37f96f9d4de2 996 static inline void DSPI_SlaveWriteData(SPI_Type *base, uint32_t data)
<> 154:37f96f9d4de2 997 {
<> 154:37f96f9d4de2 998 base->PUSHR_SLAVE = data;
<> 154:37f96f9d4de2 999 }
<> 154:37f96f9d4de2 1000
<> 154:37f96f9d4de2 1001 /*!
<> 154:37f96f9d4de2 1002 * @brief Writes data into the data buffer in slave mode, waits till data was transmitted, and returns.
<> 154:37f96f9d4de2 1003 *
<> 154:37f96f9d4de2 1004 * In slave mode, up to 16-bit words may be written. The function first clears the transmit complete flag, writes data
<> 154:37f96f9d4de2 1005 * into data register, and finally waits until the data is transmitted.
<> 154:37f96f9d4de2 1006 *
<> 154:37f96f9d4de2 1007 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 1008 * @param data The data to send.
<> 154:37f96f9d4de2 1009 */
<> 154:37f96f9d4de2 1010 void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data);
<> 154:37f96f9d4de2 1011
<> 154:37f96f9d4de2 1012 /*!
<> 154:37f96f9d4de2 1013 * @brief Reads data from the data buffer.
<> 154:37f96f9d4de2 1014 *
<> 154:37f96f9d4de2 1015 * @param base DSPI peripheral address.
<> 154:37f96f9d4de2 1016 * @return The data from the read data buffer.
<> 154:37f96f9d4de2 1017 */
<> 154:37f96f9d4de2 1018 static inline uint32_t DSPI_ReadData(SPI_Type *base)
<> 154:37f96f9d4de2 1019 {
<> 154:37f96f9d4de2 1020 return (base->POPR);
<> 154:37f96f9d4de2 1021 }
<> 154:37f96f9d4de2 1022
<> 154:37f96f9d4de2 1023 /*!
<> 154:37f96f9d4de2 1024 *@}
<> 154:37f96f9d4de2 1025 */
<> 154:37f96f9d4de2 1026
<> 154:37f96f9d4de2 1027 /*!
<> 154:37f96f9d4de2 1028 * @name Transactional
<> 154:37f96f9d4de2 1029 * @{
<> 154:37f96f9d4de2 1030 */
<> 154:37f96f9d4de2 1031 /*Transactional APIs*/
<> 154:37f96f9d4de2 1032
<> 154:37f96f9d4de2 1033 /*!
<> 154:37f96f9d4de2 1034 * @brief Initializes the DSPI master handle.
<> 154:37f96f9d4de2 1035 *
<> 154:37f96f9d4de2 1036 * This function initializes the DSPI handle which can be used for other DSPI transactional APIs. Usually, for a
<> 154:37f96f9d4de2 1037 * specified DSPI instance, call this API once to get the initialized handle.
<> 154:37f96f9d4de2 1038 *
<> 154:37f96f9d4de2 1039 * @param base DSPI peripheral base address.
<> 154:37f96f9d4de2 1040 * @param handle DSPI handle pointer to dspi_master_handle_t.
<> 154:37f96f9d4de2 1041 * @param callback dspi callback.
<> 154:37f96f9d4de2 1042 * @param userData callback function parameter.
<> 154:37f96f9d4de2 1043 */
<> 154:37f96f9d4de2 1044 void DSPI_MasterTransferCreateHandle(SPI_Type *base,
<> 154:37f96f9d4de2 1045 dspi_master_handle_t *handle,
<> 154:37f96f9d4de2 1046 dspi_master_transfer_callback_t callback,
<> 154:37f96f9d4de2 1047 void *userData);
<> 154:37f96f9d4de2 1048
<> 154:37f96f9d4de2 1049 /*!
<> 154:37f96f9d4de2 1050 * @brief DSPI master transfer data using polling.
<> 154:37f96f9d4de2 1051 *
<> 154:37f96f9d4de2 1052 * This function transfers data with polling. This is a blocking function, which does not return until all transfers
<> 154:37f96f9d4de2 1053 * have been
<> 154:37f96f9d4de2 1054 * completed.
<> 154:37f96f9d4de2 1055 *
<> 154:37f96f9d4de2 1056 * @param base DSPI peripheral base address.
<> 154:37f96f9d4de2 1057 * @param transfer pointer to dspi_transfer_t structure.
<> 154:37f96f9d4de2 1058 * @return status of status_t.
<> 154:37f96f9d4de2 1059 */
<> 154:37f96f9d4de2 1060 status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer);
<> 154:37f96f9d4de2 1061
<> 154:37f96f9d4de2 1062 /*!
<> 154:37f96f9d4de2 1063 * @brief DSPI master transfer data using interrupts.
<> 154:37f96f9d4de2 1064 *
<> 154:37f96f9d4de2 1065 * This function transfers data using interrupts. This is a non-blocking function, which returns right away. When all
<> 154:37f96f9d4de2 1066 data
<> 154:37f96f9d4de2 1067 * have been transferred, the callback function is called.
<> 154:37f96f9d4de2 1068
<> 154:37f96f9d4de2 1069 * @param base DSPI peripheral base address.
<> 154:37f96f9d4de2 1070 * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
<> 154:37f96f9d4de2 1071 * @param transfer pointer to dspi_transfer_t structure.
<> 154:37f96f9d4de2 1072 * @return status of status_t.
<> 154:37f96f9d4de2 1073 */
<> 154:37f96f9d4de2 1074 status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer);
<> 154:37f96f9d4de2 1075
<> 154:37f96f9d4de2 1076 /*!
<> 154:37f96f9d4de2 1077 * @brief Gets the master transfer count.
<> 154:37f96f9d4de2 1078 *
<> 154:37f96f9d4de2 1079 * This function gets the master transfer count.
<> 154:37f96f9d4de2 1080 *
<> 154:37f96f9d4de2 1081 * @param base DSPI peripheral base address.
<> 154:37f96f9d4de2 1082 * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
<> 154:37f96f9d4de2 1083 * @param count Number of bytes transferred so far by the non-blocking transaction.
<> 154:37f96f9d4de2 1084 * @return status of status_t.
<> 154:37f96f9d4de2 1085 */
<> 154:37f96f9d4de2 1086 status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count);
<> 154:37f96f9d4de2 1087
<> 154:37f96f9d4de2 1088 /*!
<> 154:37f96f9d4de2 1089 * @brief DSPI master aborts transfer using an interrupt.
<> 154:37f96f9d4de2 1090 *
<> 154:37f96f9d4de2 1091 * This function aborts a transfer using an interrupt.
<> 154:37f96f9d4de2 1092 *
<> 154:37f96f9d4de2 1093 * @param base DSPI peripheral base address.
<> 154:37f96f9d4de2 1094 * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
<> 154:37f96f9d4de2 1095 */
<> 154:37f96f9d4de2 1096 void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle);
<> 154:37f96f9d4de2 1097
<> 154:37f96f9d4de2 1098 /*!
<> 154:37f96f9d4de2 1099 * @brief DSPI Master IRQ handler function.
<> 154:37f96f9d4de2 1100 *
<> 154:37f96f9d4de2 1101 * This function processes the DSPI transmit and receive IRQ.
<> 154:37f96f9d4de2 1102
<> 154:37f96f9d4de2 1103 * @param base DSPI peripheral base address.
<> 154:37f96f9d4de2 1104 * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
<> 154:37f96f9d4de2 1105 */
<> 154:37f96f9d4de2 1106 void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle);
<> 154:37f96f9d4de2 1107
<> 154:37f96f9d4de2 1108 /*!
<> 154:37f96f9d4de2 1109 * @brief Initializes the DSPI slave handle.
<> 154:37f96f9d4de2 1110 *
<> 154:37f96f9d4de2 1111 * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a
<> 154:37f96f9d4de2 1112 * specified DSPI instance, call this API once to get the initialized handle.
<> 154:37f96f9d4de2 1113 *
<> 154:37f96f9d4de2 1114 * @param handle DSPI handle pointer to dspi_slave_handle_t.
<> 154:37f96f9d4de2 1115 * @param base DSPI peripheral base address.
<> 154:37f96f9d4de2 1116 * @param callback DSPI callback.
<> 154:37f96f9d4de2 1117 * @param userData callback function parameter.
<> 154:37f96f9d4de2 1118 */
<> 154:37f96f9d4de2 1119 void DSPI_SlaveTransferCreateHandle(SPI_Type *base,
<> 154:37f96f9d4de2 1120 dspi_slave_handle_t *handle,
<> 154:37f96f9d4de2 1121 dspi_slave_transfer_callback_t callback,
<> 154:37f96f9d4de2 1122 void *userData);
<> 154:37f96f9d4de2 1123
<> 154:37f96f9d4de2 1124 /*!
<> 154:37f96f9d4de2 1125 * @brief DSPI slave transfers data using an interrupt.
<> 154:37f96f9d4de2 1126 *
<> 154:37f96f9d4de2 1127 * This function transfers data using an interrupt. This is a non-blocking function, which returns right away. When all
<> 154:37f96f9d4de2 1128 * data
<> 154:37f96f9d4de2 1129 * have been transferred, the callback function is called.
<> 154:37f96f9d4de2 1130 *
<> 154:37f96f9d4de2 1131 * @param base DSPI peripheral base address.
<> 154:37f96f9d4de2 1132 * @param handle pointer to dspi_slave_handle_t structure which stores the transfer state.
<> 154:37f96f9d4de2 1133 * @param transfer pointer to dspi_transfer_t structure.
<> 154:37f96f9d4de2 1134 * @return status of status_t.
<> 154:37f96f9d4de2 1135 */
<> 154:37f96f9d4de2 1136 status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer);
<> 154:37f96f9d4de2 1137
<> 154:37f96f9d4de2 1138 /*!
<> 154:37f96f9d4de2 1139 * @brief Gets the slave transfer count.
<> 154:37f96f9d4de2 1140 *
<> 154:37f96f9d4de2 1141 * This function gets the slave transfer count.
<> 154:37f96f9d4de2 1142 *
<> 154:37f96f9d4de2 1143 * @param base DSPI peripheral base address.
<> 154:37f96f9d4de2 1144 * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
<> 154:37f96f9d4de2 1145 * @param count Number of bytes transferred so far by the non-blocking transaction.
<> 154:37f96f9d4de2 1146 * @return status of status_t.
<> 154:37f96f9d4de2 1147 */
<> 154:37f96f9d4de2 1148 status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count);
<> 154:37f96f9d4de2 1149
<> 154:37f96f9d4de2 1150 /*!
<> 154:37f96f9d4de2 1151 * @brief DSPI slave aborts a transfer using an interrupt.
<> 154:37f96f9d4de2 1152 *
<> 154:37f96f9d4de2 1153 * This function aborts transfer using an interrupt.
<> 154:37f96f9d4de2 1154 *
<> 154:37f96f9d4de2 1155 * @param base DSPI peripheral base address.
<> 154:37f96f9d4de2 1156 * @param handle pointer to dspi_slave_handle_t structure which stores the transfer state.
<> 154:37f96f9d4de2 1157 */
<> 154:37f96f9d4de2 1158 void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle);
<> 154:37f96f9d4de2 1159
<> 154:37f96f9d4de2 1160 /*!
<> 154:37f96f9d4de2 1161 * @brief DSPI Master IRQ handler function.
<> 154:37f96f9d4de2 1162 *
<> 154:37f96f9d4de2 1163 * This function processes the DSPI transmit and receive IRQ.
<> 154:37f96f9d4de2 1164 *
<> 154:37f96f9d4de2 1165 * @param base DSPI peripheral base address.
<> 154:37f96f9d4de2 1166 * @param handle pointer to dspi_slave_handle_t structure which stores the transfer state.
<> 154:37f96f9d4de2 1167 */
<> 154:37f96f9d4de2 1168 void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle);
<> 154:37f96f9d4de2 1169
<> 154:37f96f9d4de2 1170 /*!
<> 154:37f96f9d4de2 1171 *@}
<> 154:37f96f9d4de2 1172 */
<> 154:37f96f9d4de2 1173
<> 154:37f96f9d4de2 1174 #if defined(__cplusplus)
<> 154:37f96f9d4de2 1175 }
<> 154:37f96f9d4de2 1176 #endif /*_cplusplus*/
<> 154:37f96f9d4de2 1177 /*!
<> 154:37f96f9d4de2 1178 *@}
<> 154:37f96f9d4de2 1179 */
<> 154:37f96f9d4de2 1180
<> 154:37f96f9d4de2 1181 #endif /*_FSL_DSPI_H_*/