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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.c@144:ef7eb2e8f9f7
Child:
157:ff67d9f36b67
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_dma2d.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief DMA2D HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the DMA2D peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 [..]
<> 144:ef7eb2e8f9f7 20 (#) Program the required configuration through the following parameters:
<> 144:ef7eb2e8f9f7 21 the transfer mode, the output color mode and the output offset using
<> 144:ef7eb2e8f9f7 22 HAL_DMA2D_Init() function.
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 (#) Program the required configuration through the following parameters:
<> 144:ef7eb2e8f9f7 25 the input color mode, the input color, the input alpha value, the alpha mode,
<> 144:ef7eb2e8f9f7 26 the red/blue swap mode, the inverted alpha mode and the input offset using
<> 144:ef7eb2e8f9f7 27 HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 30 =================================
<> 144:ef7eb2e8f9f7 31 [..]
<> 144:ef7eb2e8f9f7 32 (#) Configure pdata parameter (explained hereafter), destination and data length
<> 144:ef7eb2e8f9f7 33 and enable the transfer using HAL_DMA2D_Start().
<> 144:ef7eb2e8f9f7 34 (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
<> 144:ef7eb2e8f9f7 35 user can specify the value of timeout according to his end application.
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 38 ===================================
<> 144:ef7eb2e8f9f7 39 [..]
<> 144:ef7eb2e8f9f7 40 (#) Configure pdata parameter, destination and data length and enable
<> 144:ef7eb2e8f9f7 41 the transfer using HAL_DMA2D_Start_IT().
<> 144:ef7eb2e8f9f7 42 (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
<> 144:ef7eb2e8f9f7 43 (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
<> 144:ef7eb2e8f9f7 44 add his own function by customization of function pointer XferCpltCallback (member
<> 144:ef7eb2e8f9f7 45 of DMA2D handle structure).
<> 144:ef7eb2e8f9f7 46 (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback
<> 144:ef7eb2e8f9f7 47 XferErrorCallback.
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 -@- In Register-to-Memory transfer mode, pdata parameter is the register
<> 144:ef7eb2e8f9f7 50 color, in Memory-to-memory or Memory-to-Memory with pixel format
<> 144:ef7eb2e8f9f7 51 conversion pdata is the source address.
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 -@- Configure the foreground source address, the background source address,
<> 144:ef7eb2e8f9f7 54 the destination and data length then Enable the transfer using
<> 144:ef7eb2e8f9f7 55 HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
<> 144:ef7eb2e8f9f7 56 in interrupt mode.
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
<> 144:ef7eb2e8f9f7 59 are used if the memory to memory with blending transfer mode is selected.
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
<> 144:ef7eb2e8f9f7 62 mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
<> 144:ef7eb2e8f9f7 67 consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
<> 144:ef7eb2e8f9f7 68 and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or
<> 144:ef7eb2e8f9f7 69 HAL_DMA2D_DisableDeadTime().
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 (#) The transfer can be suspended, resumed and aborted using the following
<> 144:ef7eb2e8f9f7 72 functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 (#) The CLUT loading can be suspended, resumed and aborted using the following
<> 144:ef7eb2e8f9f7 75 functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
<> 144:ef7eb2e8f9f7 76 HAL_DMA2D_CLUTLoading_Abort().
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 *** DMA2D HAL driver macros list ***
<> 144:ef7eb2e8f9f7 83 =============================================
<> 144:ef7eb2e8f9f7 84 [..]
<> 144:ef7eb2e8f9f7 85 Below the list of most used macros in DMA2D HAL driver :
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
<> 144:ef7eb2e8f9f7 88 (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
<> 144:ef7eb2e8f9f7 89 (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
<> 144:ef7eb2e8f9f7 90 (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
<> 144:ef7eb2e8f9f7 91 (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
<> 144:ef7eb2e8f9f7 92 (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 [..]
<> 144:ef7eb2e8f9f7 95 (@) You can refer to the DMA2D HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 @endverbatim
<> 144:ef7eb2e8f9f7 98 ******************************************************************************
<> 144:ef7eb2e8f9f7 99 * @attention
<> 144:ef7eb2e8f9f7 100 *
<> 144:ef7eb2e8f9f7 101 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 102 *
<> 144:ef7eb2e8f9f7 103 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 104 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 105 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 106 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 108 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 109 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 111 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 112 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 113 *
<> 144:ef7eb2e8f9f7 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 124 *
<> 144:ef7eb2e8f9f7 125 ******************************************************************************
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 129 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /** @defgroup DMA2D DMA2D
<> 144:ef7eb2e8f9f7 136 * @brief DMA2D HAL module driver
<> 144:ef7eb2e8f9f7 137 * @{
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 #ifdef HAL_DMA2D_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 143 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 144 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
<> 144:ef7eb2e8f9f7 145 * @{
<> 144:ef7eb2e8f9f7 146 */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /** @defgroup DMA2D_TimeOut DMA2D Time Out
<> 144:ef7eb2e8f9f7 149 * @{
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151 #define DMA2D_TIMEOUT_ABORT ((uint32_t)1000) /*!< 1s */
<> 144:ef7eb2e8f9f7 152 #define DMA2D_TIMEOUT_SUSPEND ((uint32_t)1000) /*!< 1s */
<> 144:ef7eb2e8f9f7 153 /**
<> 144:ef7eb2e8f9f7 154 * @}
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /** @defgroup DMA2D_Shifts DMA2D Shifts
<> 144:ef7eb2e8f9f7 158 * @{
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160 #define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS) /*!< Required left shift to set foreground CLUT size */
<> 144:ef7eb2e8f9f7 161 #define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS) /*!< Required left shift to set background CLUT size */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 #define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM) /*!< Required left shift to set foreground CLUT color mode */
<> 144:ef7eb2e8f9f7 164 #define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM) /*!< Required left shift to set background CLUT color mode */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 #define DMA2D_POSITION_OPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_OPFCCR_AI) /*!< Required left shift to set output alpha inversion */
<> 144:ef7eb2e8f9f7 167 #define DMA2D_POSITION_FGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AI) /*!< Required left shift to set foreground alpha inversion */
<> 144:ef7eb2e8f9f7 168 #define DMA2D_POSITION_BGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AI) /*!< Required left shift to set background alpha inversion */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 #define DMA2D_POSITION_OPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_OPFCCR_RBS) /*!< Required left shift to set output Red/Blue swap */
<> 144:ef7eb2e8f9f7 171 #define DMA2D_POSITION_FGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_RBS) /*!< Required left shift to set foreground Red/Blue swap */
<> 144:ef7eb2e8f9f7 172 #define DMA2D_POSITION_BGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_RBS) /*!< Required left shift to set background Red/Blue swap */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 #define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT) /*!< Required left shift to set deadtime value */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 #define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM) /*!< Required left shift to set foreground alpha mode */
<> 144:ef7eb2e8f9f7 177 #define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM) /*!< Required left shift to set background alpha mode */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 #define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */
<> 144:ef7eb2e8f9f7 180 #define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 #define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL) /*!< Required left shift to set pixels per lines value */
<> 144:ef7eb2e8f9f7 183 /**
<> 144:ef7eb2e8f9f7 184 * @}
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /**
<> 144:ef7eb2e8f9f7 188 * @}
<> 144:ef7eb2e8f9f7 189 */
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 192 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 193 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 194 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 195 /** @addtogroup DMA2D_Private_Functions_Prototypes
<> 144:ef7eb2e8f9f7 196 * @{
<> 144:ef7eb2e8f9f7 197 */
<> 144:ef7eb2e8f9f7 198 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
<> 144:ef7eb2e8f9f7 199 /**
<> 144:ef7eb2e8f9f7 200 * @}
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 204 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 205 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
<> 144:ef7eb2e8f9f7 206 * @{
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 210 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 211 *
<> 144:ef7eb2e8f9f7 212 @verbatim
<> 144:ef7eb2e8f9f7 213 ===============================================================================
<> 144:ef7eb2e8f9f7 214 ##### Initialization and Configuration functions #####
<> 144:ef7eb2e8f9f7 215 ===============================================================================
<> 144:ef7eb2e8f9f7 216 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 217 (+) Initialize and configure the DMA2D
<> 144:ef7eb2e8f9f7 218 (+) De-initialize the DMA2D
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 @endverbatim
<> 144:ef7eb2e8f9f7 221 * @{
<> 144:ef7eb2e8f9f7 222 */
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /**
<> 144:ef7eb2e8f9f7 225 * @brief Initialize the DMA2D according to the specified
<> 144:ef7eb2e8f9f7 226 * parameters in the DMA2D_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 227 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 228 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 229 * @retval HAL status
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 232 {
<> 144:ef7eb2e8f9f7 233 /* Check the DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 234 if(hdma2d == NULL)
<> 144:ef7eb2e8f9f7 235 {
<> 144:ef7eb2e8f9f7 236 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 237 }
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /* Check the parameters */
<> 144:ef7eb2e8f9f7 240 assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
<> 144:ef7eb2e8f9f7 241 assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
<> 144:ef7eb2e8f9f7 242 assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
<> 144:ef7eb2e8f9f7 243 assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 if(hdma2d->State == HAL_DMA2D_STATE_RESET)
<> 144:ef7eb2e8f9f7 246 {
<> 144:ef7eb2e8f9f7 247 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 248 hdma2d->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 249 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 250 HAL_DMA2D_MspInit(hdma2d);
<> 144:ef7eb2e8f9f7 251 }
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 254 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* DMA2D CR register configuration -------------------------------------------*/
<> 144:ef7eb2e8f9f7 257 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /* DMA2D OPFCCR register configuration ---------------------------------------*/
<> 144:ef7eb2e8f9f7 260 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /* DMA2D OOR register configuration ------------------------------------------*/
<> 144:ef7eb2e8f9f7 263 MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 #if defined (DMA2D_OPFCCR_AI)
<> 144:ef7eb2e8f9f7 266 /* DMA2D OPFCCR AI fields setting (Output Alpha Inversion)*/
<> 144:ef7eb2e8f9f7 267 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_AI, (hdma2d->Init.AlphaInverted << DMA2D_POSITION_OPFCCR_AI));
<> 144:ef7eb2e8f9f7 268 #endif /* DMA2D_OPFCCR_AI */
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 #if defined (DMA2D_OPFCCR_RBS)
<> 144:ef7eb2e8f9f7 271 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_RBS,(hdma2d->Init.RedBlueSwap << DMA2D_POSITION_OPFCCR_RBS));
<> 144:ef7eb2e8f9f7 272 #endif /* DMA2D_OPFCCR_RBS */
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /* Update error code */
<> 144:ef7eb2e8f9f7 276 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /* Initialize the DMA2D state*/
<> 144:ef7eb2e8f9f7 279 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 return HAL_OK;
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /**
<> 144:ef7eb2e8f9f7 285 * @brief Deinitializes the DMA2D peripheral registers to their default reset
<> 144:ef7eb2e8f9f7 286 * values.
<> 144:ef7eb2e8f9f7 287 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 288 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 289 * @retval None
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 293 {
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /* Check the DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 296 if(hdma2d == NULL)
<> 144:ef7eb2e8f9f7 297 {
<> 144:ef7eb2e8f9f7 298 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 299 }
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /* Before aborting any DMA2D transfer or CLUT loading, check
<> 144:ef7eb2e8f9f7 302 first whether or not DMA2D clock is enabled */
<> 144:ef7eb2e8f9f7 303 if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 /* Abort DMA2D transfer if any */
<> 144:ef7eb2e8f9f7 306 if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
<> 144:ef7eb2e8f9f7 307 {
<> 144:ef7eb2e8f9f7 308 if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
<> 144:ef7eb2e8f9f7 309 {
<> 144:ef7eb2e8f9f7 310 /* Issue when aborting DMA2D transfer */
<> 144:ef7eb2e8f9f7 311 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314 else
<> 144:ef7eb2e8f9f7 315 {
<> 144:ef7eb2e8f9f7 316 /* Abort background CLUT loading if any */
<> 144:ef7eb2e8f9f7 317 if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0) != HAL_OK)
<> 144:ef7eb2e8f9f7 320 {
<> 144:ef7eb2e8f9f7 321 /* Issue when aborting background CLUT loading */
<> 144:ef7eb2e8f9f7 322 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324 }
<> 144:ef7eb2e8f9f7 325 else
<> 144:ef7eb2e8f9f7 326 {
<> 144:ef7eb2e8f9f7 327 /* Abort foreground CLUT loading if any */
<> 144:ef7eb2e8f9f7 328 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
<> 144:ef7eb2e8f9f7 329 {
<> 144:ef7eb2e8f9f7 330 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1) != HAL_OK)
<> 144:ef7eb2e8f9f7 331 {
<> 144:ef7eb2e8f9f7 332 /* Issue when aborting foreground CLUT loading */
<> 144:ef7eb2e8f9f7 333 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 334 }
<> 144:ef7eb2e8f9f7 335 }
<> 144:ef7eb2e8f9f7 336 }
<> 144:ef7eb2e8f9f7 337 }
<> 144:ef7eb2e8f9f7 338 }
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /* Carry on with de-initialization of low level hardware */
<> 144:ef7eb2e8f9f7 342 HAL_DMA2D_MspDeInit(hdma2d);
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /* Reset DMA2D control registers*/
<> 144:ef7eb2e8f9f7 345 hdma2d->Instance->CR = 0;
<> 144:ef7eb2e8f9f7 346 hdma2d->Instance->FGOR = 0;
<> 144:ef7eb2e8f9f7 347 hdma2d->Instance->BGOR = 0;
<> 144:ef7eb2e8f9f7 348 hdma2d->Instance->FGPFCCR = 0;
<> 144:ef7eb2e8f9f7 349 hdma2d->Instance->BGPFCCR = 0;
<> 144:ef7eb2e8f9f7 350 hdma2d->Instance->OPFCCR = 0;
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /* Update error code */
<> 144:ef7eb2e8f9f7 353 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /* Initialize the DMA2D state*/
<> 144:ef7eb2e8f9f7 356 hdma2d->State = HAL_DMA2D_STATE_RESET;
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /* Release Lock */
<> 144:ef7eb2e8f9f7 359 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 return HAL_OK;
<> 144:ef7eb2e8f9f7 362 }
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /**
<> 144:ef7eb2e8f9f7 365 * @brief Initializes the DMA2D MSP.
<> 144:ef7eb2e8f9f7 366 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 367 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 368 * @retval None
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
<> 144:ef7eb2e8f9f7 371 {
<> 144:ef7eb2e8f9f7 372 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 373 UNUSED(hdma2d);
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 376 the HAL_DMA2D_MspInit can be implemented in the user file.
<> 144:ef7eb2e8f9f7 377 */
<> 144:ef7eb2e8f9f7 378 }
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /**
<> 144:ef7eb2e8f9f7 381 * @brief DeInitializes the DMA2D MSP.
<> 144:ef7eb2e8f9f7 382 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 383 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 384 * @retval None
<> 144:ef7eb2e8f9f7 385 */
<> 144:ef7eb2e8f9f7 386 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
<> 144:ef7eb2e8f9f7 387 {
<> 144:ef7eb2e8f9f7 388 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 389 UNUSED(hdma2d);
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 392 the HAL_DMA2D_MspDeInit can be implemented in the user file.
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394 }
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /**
<> 144:ef7eb2e8f9f7 397 * @}
<> 144:ef7eb2e8f9f7 398 */
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 402 * @brief IO operation functions
<> 144:ef7eb2e8f9f7 403 *
<> 144:ef7eb2e8f9f7 404 @verbatim
<> 144:ef7eb2e8f9f7 405 ===============================================================================
<> 144:ef7eb2e8f9f7 406 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 407 ===============================================================================
<> 144:ef7eb2e8f9f7 408 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 409 (+) Configure the pdata, destination address and data size then
<> 144:ef7eb2e8f9f7 410 start the DMA2D transfer.
<> 144:ef7eb2e8f9f7 411 (+) Configure the source for foreground and background, destination address
<> 144:ef7eb2e8f9f7 412 and data size then start a MultiBuffer DMA2D transfer.
<> 144:ef7eb2e8f9f7 413 (+) Configure the pdata, destination address and data size then
<> 144:ef7eb2e8f9f7 414 start the DMA2D transfer with interrupt.
<> 144:ef7eb2e8f9f7 415 (+) Configure the source for foreground and background, destination address
<> 144:ef7eb2e8f9f7 416 and data size then start a MultiBuffer DMA2D transfer with interrupt.
<> 144:ef7eb2e8f9f7 417 (+) Abort DMA2D transfer.
<> 144:ef7eb2e8f9f7 418 (+) Suspend DMA2D transfer.
<> 144:ef7eb2e8f9f7 419 (+) Resume DMA2D transfer.
<> 144:ef7eb2e8f9f7 420 (+) Enable CLUT transfer.
<> 144:ef7eb2e8f9f7 421 (+) Configure CLUT loading then start transfer in polling mode.
<> 144:ef7eb2e8f9f7 422 (+) Configure CLUT loading then start transfer in interrupt mode.
<> 144:ef7eb2e8f9f7 423 (+) Abort DMA2D CLUT loading.
<> 144:ef7eb2e8f9f7 424 (+) Suspend DMA2D CLUT loading.
<> 144:ef7eb2e8f9f7 425 (+) Resume DMA2D CLUT loading.
<> 144:ef7eb2e8f9f7 426 (+) Poll for transfer complete.
<> 144:ef7eb2e8f9f7 427 (+) handle DMA2D interrupt request.
<> 144:ef7eb2e8f9f7 428 (+) Transfer watermark callback.
<> 144:ef7eb2e8f9f7 429 (+) CLUT Transfer Complete callback.
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 @endverbatim
<> 144:ef7eb2e8f9f7 433 * @{
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 /**
<> 144:ef7eb2e8f9f7 437 * @brief Start the DMA2D Transfer.
<> 144:ef7eb2e8f9f7 438 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 439 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 440 * @param pdata: Configure the source memory Buffer address if
<> 144:ef7eb2e8f9f7 441 * Memory-to-Memory or Memory-to-Memory with pixel format
<> 144:ef7eb2e8f9f7 442 * conversion mode is selected, or configure
<> 144:ef7eb2e8f9f7 443 * the color value if Register-to-Memory mode is selected.
<> 144:ef7eb2e8f9f7 444 * @param DstAddress: The destination memory Buffer address.
<> 144:ef7eb2e8f9f7 445 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
<> 144:ef7eb2e8f9f7 446 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
<> 144:ef7eb2e8f9f7 447 * @retval HAL status
<> 144:ef7eb2e8f9f7 448 */
<> 144:ef7eb2e8f9f7 449 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
<> 144:ef7eb2e8f9f7 450 {
<> 144:ef7eb2e8f9f7 451 /* Check the parameters */
<> 144:ef7eb2e8f9f7 452 assert_param(IS_DMA2D_LINE(Height));
<> 144:ef7eb2e8f9f7 453 assert_param(IS_DMA2D_PIXEL(Width));
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /* Process locked */
<> 144:ef7eb2e8f9f7 456 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 459 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /* Configure the source, destination address and the data size */
<> 144:ef7eb2e8f9f7 462 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 465 __HAL_DMA2D_ENABLE(hdma2d);
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 return HAL_OK;
<> 144:ef7eb2e8f9f7 468 }
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /**
<> 144:ef7eb2e8f9f7 471 * @brief Start the DMA2D Transfer with interrupt enabled.
<> 144:ef7eb2e8f9f7 472 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 473 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 474 * @param pdata: Configure the source memory Buffer address if
<> 144:ef7eb2e8f9f7 475 * the Memory-to-Memory or Memory-to-Memory with pixel format
<> 144:ef7eb2e8f9f7 476 * conversion mode is selected, or configure
<> 144:ef7eb2e8f9f7 477 * the color value if Register-to-Memory mode is selected.
<> 144:ef7eb2e8f9f7 478 * @param DstAddress: The destination memory Buffer address.
<> 144:ef7eb2e8f9f7 479 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
<> 144:ef7eb2e8f9f7 480 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
<> 144:ef7eb2e8f9f7 481 * @retval HAL status
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
<> 144:ef7eb2e8f9f7 484 {
<> 144:ef7eb2e8f9f7 485 /* Check the parameters */
<> 144:ef7eb2e8f9f7 486 assert_param(IS_DMA2D_LINE(Height));
<> 144:ef7eb2e8f9f7 487 assert_param(IS_DMA2D_PIXEL(Width));
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /* Process locked */
<> 144:ef7eb2e8f9f7 490 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 493 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /* Configure the source, destination address and the data size */
<> 144:ef7eb2e8f9f7 496 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 /* Enable the transfer complete, transfer error and configuration error interrupts */
<> 144:ef7eb2e8f9f7 499 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 502 __HAL_DMA2D_ENABLE(hdma2d);
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 return HAL_OK;
<> 144:ef7eb2e8f9f7 505 }
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /**
<> 144:ef7eb2e8f9f7 508 * @brief Start the multi-source DMA2D Transfer.
<> 144:ef7eb2e8f9f7 509 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 510 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 511 * @param SrcAddress1: The source memory Buffer address for the foreground layer.
<> 144:ef7eb2e8f9f7 512 * @param SrcAddress2: The source memory Buffer address for the background layer.
<> 144:ef7eb2e8f9f7 513 * @param DstAddress: The destination memory Buffer address.
<> 144:ef7eb2e8f9f7 514 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
<> 144:ef7eb2e8f9f7 515 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
<> 144:ef7eb2e8f9f7 516 * @retval HAL status
<> 144:ef7eb2e8f9f7 517 */
<> 144:ef7eb2e8f9f7 518 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
<> 144:ef7eb2e8f9f7 519 {
<> 144:ef7eb2e8f9f7 520 /* Check the parameters */
<> 144:ef7eb2e8f9f7 521 assert_param(IS_DMA2D_LINE(Height));
<> 144:ef7eb2e8f9f7 522 assert_param(IS_DMA2D_PIXEL(Width));
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /* Process locked */
<> 144:ef7eb2e8f9f7 525 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 528 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /* Configure DMA2D Stream source2 address */
<> 144:ef7eb2e8f9f7 531 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /* Configure the source, destination address and the data size */
<> 144:ef7eb2e8f9f7 534 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 537 __HAL_DMA2D_ENABLE(hdma2d);
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 return HAL_OK;
<> 144:ef7eb2e8f9f7 540 }
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /**
<> 144:ef7eb2e8f9f7 543 * @brief Start the multi-source DMA2D Transfer with interrupt enabled.
<> 144:ef7eb2e8f9f7 544 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 545 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 546 * @param SrcAddress1: The source memory Buffer address for the foreground layer.
<> 144:ef7eb2e8f9f7 547 * @param SrcAddress2: The source memory Buffer address for the background layer.
<> 144:ef7eb2e8f9f7 548 * @param DstAddress: The destination memory Buffer address.
<> 144:ef7eb2e8f9f7 549 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
<> 144:ef7eb2e8f9f7 550 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
<> 144:ef7eb2e8f9f7 551 * @retval HAL status
<> 144:ef7eb2e8f9f7 552 */
<> 144:ef7eb2e8f9f7 553 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
<> 144:ef7eb2e8f9f7 554 {
<> 144:ef7eb2e8f9f7 555 /* Check the parameters */
<> 144:ef7eb2e8f9f7 556 assert_param(IS_DMA2D_LINE(Height));
<> 144:ef7eb2e8f9f7 557 assert_param(IS_DMA2D_PIXEL(Width));
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /* Process locked */
<> 144:ef7eb2e8f9f7 560 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 563 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /* Configure DMA2D Stream source2 address */
<> 144:ef7eb2e8f9f7 566 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /* Configure the source, destination address and the data size */
<> 144:ef7eb2e8f9f7 569 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /* Enable the transfer complete, transfer error and configuration error interrupts */
<> 144:ef7eb2e8f9f7 572 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 575 __HAL_DMA2D_ENABLE(hdma2d);
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 return HAL_OK;
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /**
<> 144:ef7eb2e8f9f7 581 * @brief Abort the DMA2D Transfer.
<> 144:ef7eb2e8f9f7 582 * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 583 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 584 * @retval HAL status
<> 144:ef7eb2e8f9f7 585 */
<> 144:ef7eb2e8f9f7 586 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 587 {
<> 144:ef7eb2e8f9f7 588 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 /* Abort the DMA2D transfer */
<> 144:ef7eb2e8f9f7 591 /* START bit is reset to make sure not to set it again, in the event the HW clears it
<> 144:ef7eb2e8f9f7 592 between the register read and the register write by the CPU (writing ‘0’ has no
<> 144:ef7eb2e8f9f7 593 effect on START bitvalue). */
<> 144:ef7eb2e8f9f7 594 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /* Get tick */
<> 144:ef7eb2e8f9f7 597 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /* Check if the DMA2D is effectively disabled */
<> 144:ef7eb2e8f9f7 600 while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
<> 144:ef7eb2e8f9f7 601 {
<> 144:ef7eb2e8f9f7 602 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
<> 144:ef7eb2e8f9f7 603 {
<> 144:ef7eb2e8f9f7 604 /* Update error code */
<> 144:ef7eb2e8f9f7 605 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /* Change the DMA2D state */
<> 144:ef7eb2e8f9f7 608 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 611 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 614 }
<> 144:ef7eb2e8f9f7 615 }
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
<> 144:ef7eb2e8f9f7 618 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /* Change the DMA2D state*/
<> 144:ef7eb2e8f9f7 621 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 624 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 return HAL_OK;
<> 144:ef7eb2e8f9f7 627 }
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /**
<> 144:ef7eb2e8f9f7 630 * @brief Suspend the DMA2D Transfer.
<> 144:ef7eb2e8f9f7 631 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 632 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 633 * @retval HAL status
<> 144:ef7eb2e8f9f7 634 */
<> 144:ef7eb2e8f9f7 635 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 636 {
<> 144:ef7eb2e8f9f7 637 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /* Suspend the DMA2D transfer */
<> 144:ef7eb2e8f9f7 640 /* START bit is reset to make sure not to set it again, in the event the HW clears it
<> 144:ef7eb2e8f9f7 641 between the register read and the register write by the CPU (writing ‘0’ has no
<> 144:ef7eb2e8f9f7 642 effect on START bitvalue). */
<> 144:ef7eb2e8f9f7 643 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 /* Get tick */
<> 144:ef7eb2e8f9f7 646 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /* Check if the DMA2D is effectively suspended */
<> 144:ef7eb2e8f9f7 649 while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
<> 144:ef7eb2e8f9f7 650 && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))
<> 144:ef7eb2e8f9f7 651 {
<> 144:ef7eb2e8f9f7 652 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
<> 144:ef7eb2e8f9f7 653 {
<> 144:ef7eb2e8f9f7 654 /* Update error code */
<> 144:ef7eb2e8f9f7 655 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /* Change the DMA2D state */
<> 144:ef7eb2e8f9f7 658 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 661 }
<> 144:ef7eb2e8f9f7 662 }
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
<> 144:ef7eb2e8f9f7 665 if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
<> 144:ef7eb2e8f9f7 666 {
<> 144:ef7eb2e8f9f7 667 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
<> 144:ef7eb2e8f9f7 668 }
<> 144:ef7eb2e8f9f7 669 else
<> 144:ef7eb2e8f9f7 670 {
<> 144:ef7eb2e8f9f7 671 /* Make sure SUSP bit is cleared since it is meaningless
<> 144:ef7eb2e8f9f7 672 when no tranfer is on-going */
<> 144:ef7eb2e8f9f7 673 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
<> 144:ef7eb2e8f9f7 674 }
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 return HAL_OK;
<> 144:ef7eb2e8f9f7 677 }
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /**
<> 144:ef7eb2e8f9f7 680 * @brief Resume the DMA2D Transfer.
<> 144:ef7eb2e8f9f7 681 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 682 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 683 * @retval HAL status
<> 144:ef7eb2e8f9f7 684 */
<> 144:ef7eb2e8f9f7 685 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 686 {
<> 144:ef7eb2e8f9f7 687 /* Check the SUSP and START bits */
<> 144:ef7eb2e8f9f7 688 if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
<> 144:ef7eb2e8f9f7 689 {
<> 144:ef7eb2e8f9f7 690 /* Ongoing transfer is suspended: change the DMA2D state before resuming */
<> 144:ef7eb2e8f9f7 691 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 692 }
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /* Resume the DMA2D transfer */
<> 144:ef7eb2e8f9f7 695 /* START bit is reset to make sure not to set it again, in the event the HW clears it
<> 144:ef7eb2e8f9f7 696 between the register read and the register write by the CPU (writing ‘0’ has no
<> 144:ef7eb2e8f9f7 697 effect on START bitvalue). */
<> 144:ef7eb2e8f9f7 698 CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 return HAL_OK;
<> 144:ef7eb2e8f9f7 701 }
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 /**
<> 144:ef7eb2e8f9f7 705 * @brief Enable the DMA2D CLUT Transfer.
<> 144:ef7eb2e8f9f7 706 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 707 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 708 * @param LayerIdx: DMA2D Layer index.
<> 144:ef7eb2e8f9f7 709 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 710 * 0(background) / 1(foreground)
<> 144:ef7eb2e8f9f7 711 * @retval HAL status
<> 144:ef7eb2e8f9f7 712 */
<> 144:ef7eb2e8f9f7 713 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
<> 144:ef7eb2e8f9f7 714 {
<> 144:ef7eb2e8f9f7 715 /* Check the parameters */
<> 144:ef7eb2e8f9f7 716 assert_param(IS_DMA2D_LAYER(LayerIdx));
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 /* Process locked */
<> 144:ef7eb2e8f9f7 719 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 722 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 if(LayerIdx == 0)
<> 144:ef7eb2e8f9f7 725 {
<> 144:ef7eb2e8f9f7 726 /* Enable the background CLUT loading */
<> 144:ef7eb2e8f9f7 727 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
<> 144:ef7eb2e8f9f7 728 }
<> 144:ef7eb2e8f9f7 729 else
<> 144:ef7eb2e8f9f7 730 {
<> 144:ef7eb2e8f9f7 731 /* Enable the foreground CLUT loading */
<> 144:ef7eb2e8f9f7 732 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
<> 144:ef7eb2e8f9f7 733 }
<> 144:ef7eb2e8f9f7 734
<> 144:ef7eb2e8f9f7 735 return HAL_OK;
<> 144:ef7eb2e8f9f7 736 }
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /**
<> 144:ef7eb2e8f9f7 740 * @brief Start DMA2D CLUT Loading.
<> 144:ef7eb2e8f9f7 741 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 742 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 743 * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
<> 144:ef7eb2e8f9f7 744 * the configuration information for the color look up table.
<> 144:ef7eb2e8f9f7 745 * @param LayerIdx: DMA2D Layer index.
<> 144:ef7eb2e8f9f7 746 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 747 * 0(background) / 1(foreground)
<> 144:ef7eb2e8f9f7 748 * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
<> 144:ef7eb2e8f9f7 749 * @retval HAL status
<> 144:ef7eb2e8f9f7 750 */
<> 144:ef7eb2e8f9f7 751 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
<> 144:ef7eb2e8f9f7 752 {
<> 144:ef7eb2e8f9f7 753 /* Check the parameters */
<> 144:ef7eb2e8f9f7 754 assert_param(IS_DMA2D_LAYER(LayerIdx));
<> 144:ef7eb2e8f9f7 755 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
<> 144:ef7eb2e8f9f7 756 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 /* Process locked */
<> 144:ef7eb2e8f9f7 759 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 762 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /* Configure the CLUT of the background DMA2D layer */
<> 144:ef7eb2e8f9f7 765 if(LayerIdx == 0)
<> 144:ef7eb2e8f9f7 766 {
<> 144:ef7eb2e8f9f7 767 /* Write background CLUT memory address */
<> 144:ef7eb2e8f9f7 768 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 /* Write background CLUT size and CLUT color mode */
<> 144:ef7eb2e8f9f7 771 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
<> 144:ef7eb2e8f9f7 772 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 /* Enable the CLUT loading for the background */
<> 144:ef7eb2e8f9f7 775 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
<> 144:ef7eb2e8f9f7 776 }
<> 144:ef7eb2e8f9f7 777 /* Configure the CLUT of the foreground DMA2D layer */
<> 144:ef7eb2e8f9f7 778 else
<> 144:ef7eb2e8f9f7 779 {
<> 144:ef7eb2e8f9f7 780 /* Write foreground CLUT memory address */
<> 144:ef7eb2e8f9f7 781 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 /* Write foreground CLUT size and CLUT color mode */
<> 144:ef7eb2e8f9f7 784 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
<> 144:ef7eb2e8f9f7 785 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /* Enable the CLUT loading for the foreground */
<> 144:ef7eb2e8f9f7 788 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
<> 144:ef7eb2e8f9f7 789 }
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 return HAL_OK;
<> 144:ef7eb2e8f9f7 792 }
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794 /**
<> 144:ef7eb2e8f9f7 795 * @brief Start DMA2D CLUT Loading with interrupt enabled.
<> 144:ef7eb2e8f9f7 796 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 797 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 798 * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
<> 144:ef7eb2e8f9f7 799 * the configuration information for the color look up table.
<> 144:ef7eb2e8f9f7 800 * @param LayerIdx: DMA2D Layer index.
<> 144:ef7eb2e8f9f7 801 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 802 * 0(background) / 1(foreground)
<> 144:ef7eb2e8f9f7 803 * @retval HAL status
<> 144:ef7eb2e8f9f7 804 */
<> 144:ef7eb2e8f9f7 805 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
<> 144:ef7eb2e8f9f7 806 {
<> 144:ef7eb2e8f9f7 807 /* Check the parameters */
<> 144:ef7eb2e8f9f7 808 assert_param(IS_DMA2D_LAYER(LayerIdx));
<> 144:ef7eb2e8f9f7 809 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
<> 144:ef7eb2e8f9f7 810 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 /* Process locked */
<> 144:ef7eb2e8f9f7 813 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 816 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 /* Configure the CLUT of the background DMA2D layer */
<> 144:ef7eb2e8f9f7 819 if(LayerIdx == 0)
<> 144:ef7eb2e8f9f7 820 {
<> 144:ef7eb2e8f9f7 821 /* Write background CLUT memory address */
<> 144:ef7eb2e8f9f7 822 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 /* Write background CLUT size and CLUT color mode */
<> 144:ef7eb2e8f9f7 825 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
<> 144:ef7eb2e8f9f7 826 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
<> 144:ef7eb2e8f9f7 829 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /* Enable the CLUT loading for the background */
<> 144:ef7eb2e8f9f7 832 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
<> 144:ef7eb2e8f9f7 833 }
<> 144:ef7eb2e8f9f7 834 /* Configure the CLUT of the foreground DMA2D layer */
<> 144:ef7eb2e8f9f7 835 else
<> 144:ef7eb2e8f9f7 836 {
<> 144:ef7eb2e8f9f7 837 /* Write foreground CLUT memory address */
<> 144:ef7eb2e8f9f7 838 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 /* Write foreground CLUT size and CLUT color mode */
<> 144:ef7eb2e8f9f7 841 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
<> 144:ef7eb2e8f9f7 842 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
<> 144:ef7eb2e8f9f7 845 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /* Enable the CLUT loading for the foreground */
<> 144:ef7eb2e8f9f7 848 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
<> 144:ef7eb2e8f9f7 849 }
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 return HAL_OK;
<> 144:ef7eb2e8f9f7 852 }
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 /**
<> 144:ef7eb2e8f9f7 855 * @brief Abort the DMA2D CLUT loading.
<> 144:ef7eb2e8f9f7 856 * @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 857 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 858 * @param LayerIdx: DMA2D Layer index.
<> 144:ef7eb2e8f9f7 859 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 860 * 0(background) / 1(foreground)
<> 144:ef7eb2e8f9f7 861 * @retval HAL status
<> 144:ef7eb2e8f9f7 862 */
<> 144:ef7eb2e8f9f7 863 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
<> 144:ef7eb2e8f9f7 864 {
<> 144:ef7eb2e8f9f7 865 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 866 __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 /* Abort the CLUT loading */
<> 144:ef7eb2e8f9f7 869 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 /* If foreground CLUT loading is considered, update local variables */
<> 144:ef7eb2e8f9f7 872 if(LayerIdx == 1)
<> 144:ef7eb2e8f9f7 873 {
<> 144:ef7eb2e8f9f7 874 reg = &(hdma2d->Instance->FGPFCCR);
<> 144:ef7eb2e8f9f7 875 }
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 /* Get tick */
<> 144:ef7eb2e8f9f7 879 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 /* Check if the CLUT loading is aborted */
<> 144:ef7eb2e8f9f7 882 while((*reg & DMA2D_BGPFCCR_START) != RESET)
<> 144:ef7eb2e8f9f7 883 {
<> 144:ef7eb2e8f9f7 884 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
<> 144:ef7eb2e8f9f7 885 {
<> 144:ef7eb2e8f9f7 886 /* Update error code */
<> 144:ef7eb2e8f9f7 887 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 888
<> 144:ef7eb2e8f9f7 889 /* Change the DMA2D state */
<> 144:ef7eb2e8f9f7 890 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 893 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 896 }
<> 144:ef7eb2e8f9f7 897 }
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
<> 144:ef7eb2e8f9f7 900 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
<> 144:ef7eb2e8f9f7 901
<> 144:ef7eb2e8f9f7 902 /* Change the DMA2D state*/
<> 144:ef7eb2e8f9f7 903 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 906 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 907
<> 144:ef7eb2e8f9f7 908 return HAL_OK;
<> 144:ef7eb2e8f9f7 909 }
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 /**
<> 144:ef7eb2e8f9f7 912 * @brief Suspend the DMA2D CLUT loading.
<> 144:ef7eb2e8f9f7 913 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 914 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 915 * @param LayerIdx: DMA2D Layer index.
<> 144:ef7eb2e8f9f7 916 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 917 * 0(background) / 1(foreground)
<> 144:ef7eb2e8f9f7 918 * @retval HAL status
<> 144:ef7eb2e8f9f7 919 */
<> 144:ef7eb2e8f9f7 920 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
<> 144:ef7eb2e8f9f7 921 {
<> 144:ef7eb2e8f9f7 922 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 923 __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 /* Suspend the CLUT loading */
<> 144:ef7eb2e8f9f7 926 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
<> 144:ef7eb2e8f9f7 927
<> 144:ef7eb2e8f9f7 928 /* If foreground CLUT loading is considered, update local variables */
<> 144:ef7eb2e8f9f7 929 if(LayerIdx == 1)
<> 144:ef7eb2e8f9f7 930 {
<> 144:ef7eb2e8f9f7 931 reg = &(hdma2d->Instance->FGPFCCR);
<> 144:ef7eb2e8f9f7 932 }
<> 144:ef7eb2e8f9f7 933
<> 144:ef7eb2e8f9f7 934 /* Get tick */
<> 144:ef7eb2e8f9f7 935 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 /* Check if the CLUT loading is suspended */
<> 144:ef7eb2e8f9f7 938 while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
<> 144:ef7eb2e8f9f7 939 && ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
<> 144:ef7eb2e8f9f7 940 {
<> 144:ef7eb2e8f9f7 941 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
<> 144:ef7eb2e8f9f7 942 {
<> 144:ef7eb2e8f9f7 943 /* Update error code */
<> 144:ef7eb2e8f9f7 944 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 945
<> 144:ef7eb2e8f9f7 946 /* Change the DMA2D state */
<> 144:ef7eb2e8f9f7 947 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 948
<> 144:ef7eb2e8f9f7 949 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 950 }
<> 144:ef7eb2e8f9f7 951 }
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
<> 144:ef7eb2e8f9f7 954 if ((*reg & DMA2D_BGPFCCR_START) != RESET)
<> 144:ef7eb2e8f9f7 955 {
<> 144:ef7eb2e8f9f7 956 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
<> 144:ef7eb2e8f9f7 957 }
<> 144:ef7eb2e8f9f7 958 else
<> 144:ef7eb2e8f9f7 959 {
<> 144:ef7eb2e8f9f7 960 /* Make sure SUSP bit is cleared since it is meaningless
<> 144:ef7eb2e8f9f7 961 when no tranfer is on-going */
<> 144:ef7eb2e8f9f7 962 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
<> 144:ef7eb2e8f9f7 963 }
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 return HAL_OK;
<> 144:ef7eb2e8f9f7 966 }
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 /**
<> 144:ef7eb2e8f9f7 969 * @brief Resume the DMA2D CLUT loading.
<> 144:ef7eb2e8f9f7 970 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 971 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 972 * @param LayerIdx: DMA2D Layer index.
<> 144:ef7eb2e8f9f7 973 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 974 * 0(background) / 1(foreground)
<> 144:ef7eb2e8f9f7 975 * @retval HAL status
<> 144:ef7eb2e8f9f7 976 */
<> 144:ef7eb2e8f9f7 977 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
<> 144:ef7eb2e8f9f7 978 {
<> 144:ef7eb2e8f9f7 979 /* Check the SUSP and START bits for background or foreground CLUT loading */
<> 144:ef7eb2e8f9f7 980 if(LayerIdx == 0)
<> 144:ef7eb2e8f9f7 981 {
<> 144:ef7eb2e8f9f7 982 /* Background CLUT loading suspension check */
<> 144:ef7eb2e8f9f7 983 if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
<> 144:ef7eb2e8f9f7 984 && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
<> 144:ef7eb2e8f9f7 985 {
<> 144:ef7eb2e8f9f7 986 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
<> 144:ef7eb2e8f9f7 987 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 988 }
<> 144:ef7eb2e8f9f7 989 }
<> 144:ef7eb2e8f9f7 990 else
<> 144:ef7eb2e8f9f7 991 {
<> 144:ef7eb2e8f9f7 992 /* Foreground CLUT loading suspension check */
<> 144:ef7eb2e8f9f7 993 if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
<> 144:ef7eb2e8f9f7 994 && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))
<> 144:ef7eb2e8f9f7 995 {
<> 144:ef7eb2e8f9f7 996 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
<> 144:ef7eb2e8f9f7 997 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 998 }
<> 144:ef7eb2e8f9f7 999 }
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 /* Resume the CLUT loading */
<> 144:ef7eb2e8f9f7 1002 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
<> 144:ef7eb2e8f9f7 1003
<> 144:ef7eb2e8f9f7 1004 return HAL_OK;
<> 144:ef7eb2e8f9f7 1005 }
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007
<> 144:ef7eb2e8f9f7 1008 /**
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 * @brief Polling for transfer complete or CLUT loading.
<> 144:ef7eb2e8f9f7 1011 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1012 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 1013 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 1014 * @retval HAL status
<> 144:ef7eb2e8f9f7 1015 */
<> 144:ef7eb2e8f9f7 1016 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1017 {
<> 144:ef7eb2e8f9f7 1018 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1019 __IO uint32_t isrflags = 0x0;
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 /* Polling for DMA2D transfer */
<> 144:ef7eb2e8f9f7 1022 if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
<> 144:ef7eb2e8f9f7 1023 {
<> 144:ef7eb2e8f9f7 1024 /* Get tick */
<> 144:ef7eb2e8f9f7 1025 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
<> 144:ef7eb2e8f9f7 1028 {
<> 144:ef7eb2e8f9f7 1029 isrflags = READ_REG(hdma2d->Instance->ISR);
<> 144:ef7eb2e8f9f7 1030 if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
<> 144:ef7eb2e8f9f7 1031 {
<> 144:ef7eb2e8f9f7 1032 if ((isrflags & DMA2D_FLAG_CE) != RESET)
<> 144:ef7eb2e8f9f7 1033 {
<> 144:ef7eb2e8f9f7 1034 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
<> 144:ef7eb2e8f9f7 1035 }
<> 144:ef7eb2e8f9f7 1036 if ((isrflags & DMA2D_FLAG_TE) != RESET)
<> 144:ef7eb2e8f9f7 1037 {
<> 144:ef7eb2e8f9f7 1038 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
<> 144:ef7eb2e8f9f7 1039 }
<> 144:ef7eb2e8f9f7 1040 /* Clear the transfer and configuration error flags */
<> 144:ef7eb2e8f9f7 1041 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 /* Change DMA2D state */
<> 144:ef7eb2e8f9f7 1044 hdma2d->State = HAL_DMA2D_STATE_ERROR;
<> 144:ef7eb2e8f9f7 1045
<> 144:ef7eb2e8f9f7 1046 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1047 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1048
<> 144:ef7eb2e8f9f7 1049 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1050 }
<> 144:ef7eb2e8f9f7 1051 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1052 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1053 {
<> 144:ef7eb2e8f9f7 1054 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1055 {
<> 144:ef7eb2e8f9f7 1056 /* Update error code */
<> 144:ef7eb2e8f9f7 1057 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 /* Change the DMA2D state */
<> 144:ef7eb2e8f9f7 1060 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1061
<> 144:ef7eb2e8f9f7 1062 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1063 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1064
<> 144:ef7eb2e8f9f7 1065 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1066 }
<> 144:ef7eb2e8f9f7 1067 }
<> 144:ef7eb2e8f9f7 1068 }
<> 144:ef7eb2e8f9f7 1069 }
<> 144:ef7eb2e8f9f7 1070 /* Polling for CLUT loading (foreground or background) */
<> 144:ef7eb2e8f9f7 1071 if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) ||
<> 144:ef7eb2e8f9f7 1072 ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))
<> 144:ef7eb2e8f9f7 1073 {
<> 144:ef7eb2e8f9f7 1074 /* Get tick */
<> 144:ef7eb2e8f9f7 1075 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1076
<> 144:ef7eb2e8f9f7 1077 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
<> 144:ef7eb2e8f9f7 1078 {
<> 144:ef7eb2e8f9f7 1079 isrflags = READ_REG(hdma2d->Instance->ISR);
<> 144:ef7eb2e8f9f7 1080 if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
<> 144:ef7eb2e8f9f7 1081 {
<> 144:ef7eb2e8f9f7 1082 if ((isrflags & DMA2D_FLAG_CAE) != RESET)
<> 144:ef7eb2e8f9f7 1083 {
<> 144:ef7eb2e8f9f7 1084 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
<> 144:ef7eb2e8f9f7 1085 }
<> 144:ef7eb2e8f9f7 1086 if ((isrflags & DMA2D_FLAG_CE) != RESET)
<> 144:ef7eb2e8f9f7 1087 {
<> 144:ef7eb2e8f9f7 1088 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
<> 144:ef7eb2e8f9f7 1089 }
<> 144:ef7eb2e8f9f7 1090 if ((isrflags & DMA2D_FLAG_TE) != RESET)
<> 144:ef7eb2e8f9f7 1091 {
<> 144:ef7eb2e8f9f7 1092 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
<> 144:ef7eb2e8f9f7 1093 }
<> 144:ef7eb2e8f9f7 1094 /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
<> 144:ef7eb2e8f9f7 1095 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
<> 144:ef7eb2e8f9f7 1096
<> 144:ef7eb2e8f9f7 1097 /* Change DMA2D state */
<> 144:ef7eb2e8f9f7 1098 hdma2d->State= HAL_DMA2D_STATE_ERROR;
<> 144:ef7eb2e8f9f7 1099
<> 144:ef7eb2e8f9f7 1100 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1101 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1102
<> 144:ef7eb2e8f9f7 1103 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1104 }
<> 144:ef7eb2e8f9f7 1105 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1106 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1107 {
<> 144:ef7eb2e8f9f7 1108 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1109 {
<> 144:ef7eb2e8f9f7 1110 /* Update error code */
<> 144:ef7eb2e8f9f7 1111 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 /* Change the DMA2D state */
<> 144:ef7eb2e8f9f7 1114 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1115
<> 144:ef7eb2e8f9f7 1116 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1117 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1118
<> 144:ef7eb2e8f9f7 1119 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1120 }
<> 144:ef7eb2e8f9f7 1121 }
<> 144:ef7eb2e8f9f7 1122 }
<> 144:ef7eb2e8f9f7 1123 }
<> 144:ef7eb2e8f9f7 1124
<> 144:ef7eb2e8f9f7 1125 /* Clear the transfer complete and CLUT loading flags */
<> 144:ef7eb2e8f9f7 1126 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
<> 144:ef7eb2e8f9f7 1127
<> 144:ef7eb2e8f9f7 1128 /* Change DMA2D state */
<> 144:ef7eb2e8f9f7 1129 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 1130
<> 144:ef7eb2e8f9f7 1131 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1132 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1133
<> 144:ef7eb2e8f9f7 1134 return HAL_OK;
<> 144:ef7eb2e8f9f7 1135 }
<> 144:ef7eb2e8f9f7 1136 /**
<> 144:ef7eb2e8f9f7 1137 * @brief Handle DMA2D interrupt request.
<> 144:ef7eb2e8f9f7 1138 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1139 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 1140 * @retval HAL status
<> 144:ef7eb2e8f9f7 1141 */
<> 144:ef7eb2e8f9f7 1142 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 1143 {
<> 144:ef7eb2e8f9f7 1144 uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
<> 144:ef7eb2e8f9f7 1145 uint32_t crflags = READ_REG(hdma2d->Instance->CR);
<> 144:ef7eb2e8f9f7 1146
<> 144:ef7eb2e8f9f7 1147 /* Transfer Error Interrupt management ***************************************/
<> 144:ef7eb2e8f9f7 1148 if ((isrflags & DMA2D_FLAG_TE) != RESET)
<> 144:ef7eb2e8f9f7 1149 {
<> 144:ef7eb2e8f9f7 1150 if ((crflags & DMA2D_IT_TE) != RESET)
<> 144:ef7eb2e8f9f7 1151 {
<> 144:ef7eb2e8f9f7 1152 /* Disable the transfer Error interrupt */
<> 144:ef7eb2e8f9f7 1153 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /* Update error code */
<> 144:ef7eb2e8f9f7 1156 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 /* Clear the transfer error flag */
<> 144:ef7eb2e8f9f7 1159 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 /* Change DMA2D state */
<> 144:ef7eb2e8f9f7 1162 hdma2d->State = HAL_DMA2D_STATE_ERROR;
<> 144:ef7eb2e8f9f7 1163
<> 144:ef7eb2e8f9f7 1164 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1165 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1166
<> 144:ef7eb2e8f9f7 1167 if(hdma2d->XferErrorCallback != NULL)
<> 144:ef7eb2e8f9f7 1168 {
<> 144:ef7eb2e8f9f7 1169 /* Transfer error Callback */
<> 144:ef7eb2e8f9f7 1170 hdma2d->XferErrorCallback(hdma2d);
<> 144:ef7eb2e8f9f7 1171 }
<> 144:ef7eb2e8f9f7 1172 }
<> 144:ef7eb2e8f9f7 1173 }
<> 144:ef7eb2e8f9f7 1174 /* Configuration Error Interrupt management **********************************/
<> 144:ef7eb2e8f9f7 1175 if ((isrflags & DMA2D_FLAG_CE) != RESET)
<> 144:ef7eb2e8f9f7 1176 {
<> 144:ef7eb2e8f9f7 1177 if ((crflags & DMA2D_IT_CE) != RESET)
<> 144:ef7eb2e8f9f7 1178 {
<> 144:ef7eb2e8f9f7 1179 /* Disable the Configuration Error interrupt */
<> 144:ef7eb2e8f9f7 1180 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 /* Clear the Configuration error flag */
<> 144:ef7eb2e8f9f7 1183 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
<> 144:ef7eb2e8f9f7 1184
<> 144:ef7eb2e8f9f7 1185 /* Update error code */
<> 144:ef7eb2e8f9f7 1186 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
<> 144:ef7eb2e8f9f7 1187
<> 144:ef7eb2e8f9f7 1188 /* Change DMA2D state */
<> 144:ef7eb2e8f9f7 1189 hdma2d->State = HAL_DMA2D_STATE_ERROR;
<> 144:ef7eb2e8f9f7 1190
<> 144:ef7eb2e8f9f7 1191 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1192 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1193
<> 144:ef7eb2e8f9f7 1194 if(hdma2d->XferErrorCallback != NULL)
<> 144:ef7eb2e8f9f7 1195 {
<> 144:ef7eb2e8f9f7 1196 /* Transfer error Callback */
<> 144:ef7eb2e8f9f7 1197 hdma2d->XferErrorCallback(hdma2d);
<> 144:ef7eb2e8f9f7 1198 }
<> 144:ef7eb2e8f9f7 1199 }
<> 144:ef7eb2e8f9f7 1200 }
<> 144:ef7eb2e8f9f7 1201 /* CLUT access Error Interrupt management ***********************************/
<> 144:ef7eb2e8f9f7 1202 if ((isrflags & DMA2D_FLAG_CAE) != RESET)
<> 144:ef7eb2e8f9f7 1203 {
<> 144:ef7eb2e8f9f7 1204 if ((crflags & DMA2D_IT_CAE) != RESET)
<> 144:ef7eb2e8f9f7 1205 {
<> 144:ef7eb2e8f9f7 1206 /* Disable the CLUT access error interrupt */
<> 144:ef7eb2e8f9f7 1207 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /* Clear the CLUT access error flag */
<> 144:ef7eb2e8f9f7 1210 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
<> 144:ef7eb2e8f9f7 1211
<> 144:ef7eb2e8f9f7 1212 /* Update error code */
<> 144:ef7eb2e8f9f7 1213 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
<> 144:ef7eb2e8f9f7 1214
<> 144:ef7eb2e8f9f7 1215 /* Change DMA2D state */
<> 144:ef7eb2e8f9f7 1216 hdma2d->State = HAL_DMA2D_STATE_ERROR;
<> 144:ef7eb2e8f9f7 1217
<> 144:ef7eb2e8f9f7 1218 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1219 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1220
<> 144:ef7eb2e8f9f7 1221 if(hdma2d->XferErrorCallback != NULL)
<> 144:ef7eb2e8f9f7 1222 {
<> 144:ef7eb2e8f9f7 1223 /* Transfer error Callback */
<> 144:ef7eb2e8f9f7 1224 hdma2d->XferErrorCallback(hdma2d);
<> 144:ef7eb2e8f9f7 1225 }
<> 144:ef7eb2e8f9f7 1226 }
<> 144:ef7eb2e8f9f7 1227 }
<> 144:ef7eb2e8f9f7 1228 /* Transfer watermark Interrupt management **********************************/
<> 144:ef7eb2e8f9f7 1229 if ((isrflags & DMA2D_FLAG_TW) != RESET)
<> 144:ef7eb2e8f9f7 1230 {
<> 144:ef7eb2e8f9f7 1231 if ((crflags & DMA2D_IT_TW) != RESET)
<> 144:ef7eb2e8f9f7 1232 {
<> 144:ef7eb2e8f9f7 1233 /* Disable the transfer watermark interrupt */
<> 144:ef7eb2e8f9f7 1234 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
<> 144:ef7eb2e8f9f7 1235
<> 144:ef7eb2e8f9f7 1236 /* Clear the transfer watermark flag */
<> 144:ef7eb2e8f9f7 1237 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
<> 144:ef7eb2e8f9f7 1238
<> 144:ef7eb2e8f9f7 1239 /* Transfer watermark Callback */
<> 144:ef7eb2e8f9f7 1240 HAL_DMA2D_LineEventCallback(hdma2d);
<> 144:ef7eb2e8f9f7 1241 }
<> 144:ef7eb2e8f9f7 1242 }
<> 144:ef7eb2e8f9f7 1243 /* Transfer Complete Interrupt management ************************************/
<> 144:ef7eb2e8f9f7 1244 if ((isrflags & DMA2D_FLAG_TC) != RESET)
<> 144:ef7eb2e8f9f7 1245 {
<> 144:ef7eb2e8f9f7 1246 if ((crflags & DMA2D_IT_TC) != RESET)
<> 144:ef7eb2e8f9f7 1247 {
<> 144:ef7eb2e8f9f7 1248 /* Disable the transfer complete interrupt */
<> 144:ef7eb2e8f9f7 1249 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
<> 144:ef7eb2e8f9f7 1250
<> 144:ef7eb2e8f9f7 1251 /* Clear the transfer complete flag */
<> 144:ef7eb2e8f9f7 1252 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
<> 144:ef7eb2e8f9f7 1253
<> 144:ef7eb2e8f9f7 1254 /* Update error code */
<> 144:ef7eb2e8f9f7 1255 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1256
<> 144:ef7eb2e8f9f7 1257 /* Change DMA2D state */
<> 144:ef7eb2e8f9f7 1258 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 1259
<> 144:ef7eb2e8f9f7 1260 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1261 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 if(hdma2d->XferCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 1264 {
<> 144:ef7eb2e8f9f7 1265 /* Transfer complete Callback */
<> 144:ef7eb2e8f9f7 1266 hdma2d->XferCpltCallback(hdma2d);
<> 144:ef7eb2e8f9f7 1267 }
<> 144:ef7eb2e8f9f7 1268 }
<> 144:ef7eb2e8f9f7 1269 }
<> 144:ef7eb2e8f9f7 1270 /* CLUT Transfer Complete Interrupt management ******************************/
<> 144:ef7eb2e8f9f7 1271 if ((isrflags & DMA2D_FLAG_CTC) != RESET)
<> 144:ef7eb2e8f9f7 1272 {
<> 144:ef7eb2e8f9f7 1273 if ((crflags & DMA2D_IT_CTC) != RESET)
<> 144:ef7eb2e8f9f7 1274 {
<> 144:ef7eb2e8f9f7 1275 /* Disable the CLUT transfer complete interrupt */
<> 144:ef7eb2e8f9f7 1276 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
<> 144:ef7eb2e8f9f7 1277
<> 144:ef7eb2e8f9f7 1278 /* Clear the CLUT transfer complete flag */
<> 144:ef7eb2e8f9f7 1279 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
<> 144:ef7eb2e8f9f7 1280
<> 144:ef7eb2e8f9f7 1281 /* Update error code */
<> 144:ef7eb2e8f9f7 1282 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1283
<> 144:ef7eb2e8f9f7 1284 /* Change DMA2D state */
<> 144:ef7eb2e8f9f7 1285 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 1286
<> 144:ef7eb2e8f9f7 1287 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1288 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1289
<> 144:ef7eb2e8f9f7 1290 /* CLUT Transfer complete Callback */
<> 144:ef7eb2e8f9f7 1291 HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
<> 144:ef7eb2e8f9f7 1292 }
<> 144:ef7eb2e8f9f7 1293 }
<> 144:ef7eb2e8f9f7 1294
<> 144:ef7eb2e8f9f7 1295 }
<> 144:ef7eb2e8f9f7 1296
<> 144:ef7eb2e8f9f7 1297 /**
<> 144:ef7eb2e8f9f7 1298 * @brief Transfer watermark callback.
<> 144:ef7eb2e8f9f7 1299 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1300 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 1301 * @retval None
<> 144:ef7eb2e8f9f7 1302 */
<> 144:ef7eb2e8f9f7 1303 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 1304 {
<> 144:ef7eb2e8f9f7 1305 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1306 UNUSED(hdma2d);
<> 144:ef7eb2e8f9f7 1307
<> 144:ef7eb2e8f9f7 1308 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 1309 the HAL_DMA2D_LineEventCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1310 */
<> 144:ef7eb2e8f9f7 1311 }
<> 144:ef7eb2e8f9f7 1312
<> 144:ef7eb2e8f9f7 1313 /**
<> 144:ef7eb2e8f9f7 1314 * @brief CLUT Transfer Complete callback.
<> 144:ef7eb2e8f9f7 1315 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1316 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 1317 * @retval None
<> 144:ef7eb2e8f9f7 1318 */
<> 144:ef7eb2e8f9f7 1319 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 1320 {
<> 144:ef7eb2e8f9f7 1321 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1322 UNUSED(hdma2d);
<> 144:ef7eb2e8f9f7 1323
<> 144:ef7eb2e8f9f7 1324 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 1325 the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1326 */
<> 144:ef7eb2e8f9f7 1327 }
<> 144:ef7eb2e8f9f7 1328
<> 144:ef7eb2e8f9f7 1329 /**
<> 144:ef7eb2e8f9f7 1330 * @}
<> 144:ef7eb2e8f9f7 1331 */
<> 144:ef7eb2e8f9f7 1332
<> 144:ef7eb2e8f9f7 1333 /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 1334 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 1335 *
<> 144:ef7eb2e8f9f7 1336 @verbatim
<> 144:ef7eb2e8f9f7 1337 ===============================================================================
<> 144:ef7eb2e8f9f7 1338 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1339 ===============================================================================
<> 144:ef7eb2e8f9f7 1340 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1341 (+) Configure the DMA2D foreground or background layer parameters.
<> 144:ef7eb2e8f9f7 1342 (+) Configure the DMA2D CLUT transfer.
<> 144:ef7eb2e8f9f7 1343 (+) Configure the line watermark
<> 144:ef7eb2e8f9f7 1344 (+) Configure the dead time value.
<> 144:ef7eb2e8f9f7 1345 (+) Enable or disable the dead time value functionality.
<> 144:ef7eb2e8f9f7 1346
<> 144:ef7eb2e8f9f7 1347
<> 144:ef7eb2e8f9f7 1348 @endverbatim
<> 144:ef7eb2e8f9f7 1349 * @{
<> 144:ef7eb2e8f9f7 1350 */
<> 144:ef7eb2e8f9f7 1351
<> 144:ef7eb2e8f9f7 1352 /**
<> 144:ef7eb2e8f9f7 1353 * @brief Configure the DMA2D Layer according to the specified
<> 144:ef7eb2e8f9f7 1354 * parameters in the DMA2D_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 1355 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1356 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 1357 * @param LayerIdx: DMA2D Layer index.
<> 144:ef7eb2e8f9f7 1358 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1359 * 0(background) / 1(foreground)
<> 144:ef7eb2e8f9f7 1360 * @retval HAL status
<> 144:ef7eb2e8f9f7 1361 */
<> 144:ef7eb2e8f9f7 1362 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
<> 144:ef7eb2e8f9f7 1363 {
<> 144:ef7eb2e8f9f7 1364 DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
<> 144:ef7eb2e8f9f7 1365
<> 144:ef7eb2e8f9f7 1366 uint32_t regMask = 0, regValue = 0;
<> 144:ef7eb2e8f9f7 1367
<> 144:ef7eb2e8f9f7 1368 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1369 assert_param(IS_DMA2D_LAYER(LayerIdx));
<> 144:ef7eb2e8f9f7 1370 assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
<> 144:ef7eb2e8f9f7 1371 if(hdma2d->Init.Mode != DMA2D_R2M)
<> 144:ef7eb2e8f9f7 1372 {
<> 144:ef7eb2e8f9f7 1373 assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
<> 144:ef7eb2e8f9f7 1374 if(hdma2d->Init.Mode != DMA2D_M2M)
<> 144:ef7eb2e8f9f7 1375 {
<> 144:ef7eb2e8f9f7 1376 assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
<> 144:ef7eb2e8f9f7 1377 }
<> 144:ef7eb2e8f9f7 1378 }
<> 144:ef7eb2e8f9f7 1379
<> 144:ef7eb2e8f9f7 1380 /* Process locked */
<> 144:ef7eb2e8f9f7 1381 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1382
<> 144:ef7eb2e8f9f7 1383 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 1384 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1385
<> 144:ef7eb2e8f9f7 1386 /* DMA2D BGPFCR register configuration -----------------------------------*/
<> 144:ef7eb2e8f9f7 1387 /* Prepare the value to be written to the BGPFCCR register */
<> 144:ef7eb2e8f9f7 1388
<> 144:ef7eb2e8f9f7 1389 regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM);
<> 144:ef7eb2e8f9f7 1390 regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
<> 144:ef7eb2e8f9f7 1391
<> 144:ef7eb2e8f9f7 1392 #if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)
<> 144:ef7eb2e8f9f7 1393 regValue |= (pLayerCfg->AlphaInverted << DMA2D_POSITION_BGPFCCR_AI);
<> 144:ef7eb2e8f9f7 1394 regMask |= DMA2D_BGPFCCR_AI;
<> 144:ef7eb2e8f9f7 1395 #endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */
<> 144:ef7eb2e8f9f7 1396
<> 144:ef7eb2e8f9f7 1397 #if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)
<> 144:ef7eb2e8f9f7 1398 regValue |= (pLayerCfg->RedBlueSwap << DMA2D_POSITION_BGPFCCR_RBS);
<> 144:ef7eb2e8f9f7 1399 regMask |= DMA2D_BGPFCCR_RBS;
<> 144:ef7eb2e8f9f7 1400 #endif
<> 144:ef7eb2e8f9f7 1401
<> 144:ef7eb2e8f9f7 1402 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
<> 144:ef7eb2e8f9f7 1403 {
<> 144:ef7eb2e8f9f7 1404 regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
<> 144:ef7eb2e8f9f7 1405 }
<> 144:ef7eb2e8f9f7 1406 else
<> 144:ef7eb2e8f9f7 1407 {
<> 144:ef7eb2e8f9f7 1408 regValue |= (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA);
<> 144:ef7eb2e8f9f7 1409 }
<> 144:ef7eb2e8f9f7 1410
<> 144:ef7eb2e8f9f7 1411 /* Configure the background DMA2D layer */
<> 144:ef7eb2e8f9f7 1412 if(LayerIdx == 0)
<> 144:ef7eb2e8f9f7 1413 {
<> 144:ef7eb2e8f9f7 1414 /* Write DMA2D BGPFCCR register */
<> 144:ef7eb2e8f9f7 1415 MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
<> 144:ef7eb2e8f9f7 1416
<> 144:ef7eb2e8f9f7 1417 /* DMA2D BGOR register configuration -------------------------------------*/
<> 144:ef7eb2e8f9f7 1418 WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
<> 144:ef7eb2e8f9f7 1419
<> 144:ef7eb2e8f9f7 1420 /* DMA2D BGCOLR register configuration -------------------------------------*/
<> 144:ef7eb2e8f9f7 1421 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
<> 144:ef7eb2e8f9f7 1422 {
<> 144:ef7eb2e8f9f7 1423 WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
<> 144:ef7eb2e8f9f7 1424 }
<> 144:ef7eb2e8f9f7 1425 }
<> 144:ef7eb2e8f9f7 1426 /* Configure the foreground DMA2D layer */
<> 144:ef7eb2e8f9f7 1427 else
<> 144:ef7eb2e8f9f7 1428 {
<> 144:ef7eb2e8f9f7 1429 /* Write DMA2D FGPFCCR register */
<> 144:ef7eb2e8f9f7 1430 MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
<> 144:ef7eb2e8f9f7 1431
<> 144:ef7eb2e8f9f7 1432 /* DMA2D FGOR register configuration -------------------------------------*/
<> 144:ef7eb2e8f9f7 1433 WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
<> 144:ef7eb2e8f9f7 1434
<> 144:ef7eb2e8f9f7 1435 /* DMA2D FGCOLR register configuration -------------------------------------*/
<> 144:ef7eb2e8f9f7 1436 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
<> 144:ef7eb2e8f9f7 1437 {
<> 144:ef7eb2e8f9f7 1438 WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
<> 144:ef7eb2e8f9f7 1439 }
<> 144:ef7eb2e8f9f7 1440 }
<> 144:ef7eb2e8f9f7 1441 /* Initialize the DMA2D state*/
<> 144:ef7eb2e8f9f7 1442 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 1443
<> 144:ef7eb2e8f9f7 1444 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1445 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1446
<> 144:ef7eb2e8f9f7 1447 return HAL_OK;
<> 144:ef7eb2e8f9f7 1448 }
<> 144:ef7eb2e8f9f7 1449
<> 144:ef7eb2e8f9f7 1450 /**
<> 144:ef7eb2e8f9f7 1451 * @brief Configure the DMA2D CLUT Transfer.
<> 144:ef7eb2e8f9f7 1452 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1453 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 1454 * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1455 * the configuration information for the color look up table.
<> 144:ef7eb2e8f9f7 1456 * @param LayerIdx: DMA2D Layer index.
<> 144:ef7eb2e8f9f7 1457 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1458 * 0(background) / 1(foreground)
<> 144:ef7eb2e8f9f7 1459 * @retval HAL status
<> 144:ef7eb2e8f9f7 1460 */
<> 144:ef7eb2e8f9f7 1461 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
<> 144:ef7eb2e8f9f7 1462 {
<> 144:ef7eb2e8f9f7 1463 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1464 assert_param(IS_DMA2D_LAYER(LayerIdx));
<> 144:ef7eb2e8f9f7 1465 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
<> 144:ef7eb2e8f9f7 1466 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
<> 144:ef7eb2e8f9f7 1467
<> 144:ef7eb2e8f9f7 1468 /* Process locked */
<> 144:ef7eb2e8f9f7 1469 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1470
<> 144:ef7eb2e8f9f7 1471 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 1472 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1473
<> 144:ef7eb2e8f9f7 1474 /* Configure the CLUT of the background DMA2D layer */
<> 144:ef7eb2e8f9f7 1475 if(LayerIdx == 0)
<> 144:ef7eb2e8f9f7 1476 {
<> 144:ef7eb2e8f9f7 1477 /* Write background CLUT memory address */
<> 144:ef7eb2e8f9f7 1478 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
<> 144:ef7eb2e8f9f7 1479
<> 144:ef7eb2e8f9f7 1480 /* Write background CLUT size and CLUT color mode */
<> 144:ef7eb2e8f9f7 1481 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
<> 144:ef7eb2e8f9f7 1482 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
<> 144:ef7eb2e8f9f7 1483 }
<> 144:ef7eb2e8f9f7 1484 /* Configure the CLUT of the foreground DMA2D layer */
<> 144:ef7eb2e8f9f7 1485 else
<> 144:ef7eb2e8f9f7 1486 {
<> 144:ef7eb2e8f9f7 1487 /* Write foreground CLUT memory address */
<> 144:ef7eb2e8f9f7 1488 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
<> 144:ef7eb2e8f9f7 1489
<> 144:ef7eb2e8f9f7 1490 /* Write foreground CLUT size and CLUT color mode */
<> 144:ef7eb2e8f9f7 1491 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
<> 144:ef7eb2e8f9f7 1492 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
<> 144:ef7eb2e8f9f7 1493 }
<> 144:ef7eb2e8f9f7 1494
<> 144:ef7eb2e8f9f7 1495 /* Set the DMA2D state to Ready*/
<> 144:ef7eb2e8f9f7 1496 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 1497
<> 144:ef7eb2e8f9f7 1498 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1499 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1500
<> 144:ef7eb2e8f9f7 1501 return HAL_OK;
<> 144:ef7eb2e8f9f7 1502 }
<> 144:ef7eb2e8f9f7 1503
<> 144:ef7eb2e8f9f7 1504
<> 144:ef7eb2e8f9f7 1505 /**
<> 144:ef7eb2e8f9f7 1506 * @brief Configure the line watermark.
<> 144:ef7eb2e8f9f7 1507 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1508 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 1509 * @param Line: Line Watermark configuration (maximum 16-bit long value expected).
<> 144:ef7eb2e8f9f7 1510 * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
<> 144:ef7eb2e8f9f7 1511 * @note The transfer watermark interrupt is disabled once it has occurred.
<> 144:ef7eb2e8f9f7 1512 * @retval HAL status
<> 144:ef7eb2e8f9f7 1513 */
<> 144:ef7eb2e8f9f7 1514
<> 144:ef7eb2e8f9f7 1515 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
<> 144:ef7eb2e8f9f7 1516 {
<> 144:ef7eb2e8f9f7 1517 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1518 assert_param(IS_DMA2D_LINEWATERMARK(Line));
<> 144:ef7eb2e8f9f7 1519
<> 144:ef7eb2e8f9f7 1520 if (Line > DMA2D_LWR_LW)
<> 144:ef7eb2e8f9f7 1521 {
<> 144:ef7eb2e8f9f7 1522 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1523 }
<> 144:ef7eb2e8f9f7 1524 else
<> 144:ef7eb2e8f9f7 1525 {
<> 144:ef7eb2e8f9f7 1526 /* Process locked */
<> 144:ef7eb2e8f9f7 1527 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1528
<> 144:ef7eb2e8f9f7 1529 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 1530 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1531
<> 144:ef7eb2e8f9f7 1532 /* Sets the Line watermark configuration */
<> 144:ef7eb2e8f9f7 1533 WRITE_REG(hdma2d->Instance->LWR, Line);
<> 144:ef7eb2e8f9f7 1534
<> 144:ef7eb2e8f9f7 1535 /* Enable the Line interrupt */
<> 144:ef7eb2e8f9f7 1536 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
<> 144:ef7eb2e8f9f7 1537
<> 144:ef7eb2e8f9f7 1538 /* Initialize the DMA2D state*/
<> 144:ef7eb2e8f9f7 1539 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 1540
<> 144:ef7eb2e8f9f7 1541 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1542 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1543
<> 144:ef7eb2e8f9f7 1544 return HAL_OK;
<> 144:ef7eb2e8f9f7 1545 }
<> 144:ef7eb2e8f9f7 1546 }
<> 144:ef7eb2e8f9f7 1547
<> 144:ef7eb2e8f9f7 1548 /**
<> 144:ef7eb2e8f9f7 1549 * @brief Enable DMA2D dead time feature.
<> 144:ef7eb2e8f9f7 1550 * @param hdma2d: DMA2D handle.
<> 144:ef7eb2e8f9f7 1551 * @retval HAL status
<> 144:ef7eb2e8f9f7 1552 */
<> 144:ef7eb2e8f9f7 1553 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 1554 {
<> 144:ef7eb2e8f9f7 1555 /* Process Locked */
<> 144:ef7eb2e8f9f7 1556 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1557
<> 144:ef7eb2e8f9f7 1558 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1559
<> 144:ef7eb2e8f9f7 1560 /* Set DMA2D_AMTCR EN bit */
<> 144:ef7eb2e8f9f7 1561 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
<> 144:ef7eb2e8f9f7 1562
<> 144:ef7eb2e8f9f7 1563 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 1564
<> 144:ef7eb2e8f9f7 1565 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1566 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1567
<> 144:ef7eb2e8f9f7 1568 return HAL_OK;
<> 144:ef7eb2e8f9f7 1569 }
<> 144:ef7eb2e8f9f7 1570
<> 144:ef7eb2e8f9f7 1571 /**
<> 144:ef7eb2e8f9f7 1572 * @brief Disable DMA2D dead time feature.
<> 144:ef7eb2e8f9f7 1573 * @param hdma2d: DMA2D handle.
<> 144:ef7eb2e8f9f7 1574 * @retval HAL status
<> 144:ef7eb2e8f9f7 1575 */
<> 144:ef7eb2e8f9f7 1576 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 1577 {
<> 144:ef7eb2e8f9f7 1578 /* Process Locked */
<> 144:ef7eb2e8f9f7 1579 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1580
<> 144:ef7eb2e8f9f7 1581 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1582
<> 144:ef7eb2e8f9f7 1583 /* Clear DMA2D_AMTCR EN bit */
<> 144:ef7eb2e8f9f7 1584 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
<> 144:ef7eb2e8f9f7 1585
<> 144:ef7eb2e8f9f7 1586 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 1587
<> 144:ef7eb2e8f9f7 1588 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1589 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1590
<> 144:ef7eb2e8f9f7 1591 return HAL_OK;
<> 144:ef7eb2e8f9f7 1592 }
<> 144:ef7eb2e8f9f7 1593
<> 144:ef7eb2e8f9f7 1594 /**
<> 144:ef7eb2e8f9f7 1595 * @brief Configure dead time.
<> 144:ef7eb2e8f9f7 1596 * @note The dead time value represents the guaranteed minimum number of cycles between
<> 144:ef7eb2e8f9f7 1597 * two consecutive transactions on the AHB bus.
<> 144:ef7eb2e8f9f7 1598 * @param hdma2d: DMA2D handle.
<> 144:ef7eb2e8f9f7 1599 * @param DeadTime: dead time value.
<> 144:ef7eb2e8f9f7 1600 * @retval HAL status
<> 144:ef7eb2e8f9f7 1601 */
<> 144:ef7eb2e8f9f7 1602 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
<> 144:ef7eb2e8f9f7 1603 {
<> 144:ef7eb2e8f9f7 1604 /* Process Locked */
<> 144:ef7eb2e8f9f7 1605 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1606
<> 144:ef7eb2e8f9f7 1607 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1608
<> 144:ef7eb2e8f9f7 1609 /* Set DMA2D_AMTCR DT field */
<> 144:ef7eb2e8f9f7 1610 MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));
<> 144:ef7eb2e8f9f7 1611
<> 144:ef7eb2e8f9f7 1612 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 1613
<> 144:ef7eb2e8f9f7 1614 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1615 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1616
<> 144:ef7eb2e8f9f7 1617 return HAL_OK;
<> 144:ef7eb2e8f9f7 1618 }
<> 144:ef7eb2e8f9f7 1619
<> 144:ef7eb2e8f9f7 1620 /**
<> 144:ef7eb2e8f9f7 1621 * @}
<> 144:ef7eb2e8f9f7 1622 */
<> 144:ef7eb2e8f9f7 1623
<> 144:ef7eb2e8f9f7 1624
<> 144:ef7eb2e8f9f7 1625 /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 1626 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 1627 *
<> 144:ef7eb2e8f9f7 1628 @verbatim
<> 144:ef7eb2e8f9f7 1629 ===============================================================================
<> 144:ef7eb2e8f9f7 1630 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 1631 ===============================================================================
<> 144:ef7eb2e8f9f7 1632 [..]
<> 144:ef7eb2e8f9f7 1633 This subsection provides functions allowing to :
<> 144:ef7eb2e8f9f7 1634 (+) Get the DMA2D state
<> 144:ef7eb2e8f9f7 1635 (+) Get the DMA2D error code
<> 144:ef7eb2e8f9f7 1636
<> 144:ef7eb2e8f9f7 1637 @endverbatim
<> 144:ef7eb2e8f9f7 1638 * @{
<> 144:ef7eb2e8f9f7 1639 */
<> 144:ef7eb2e8f9f7 1640
<> 144:ef7eb2e8f9f7 1641 /**
<> 144:ef7eb2e8f9f7 1642 * @brief Return the DMA2D state
<> 144:ef7eb2e8f9f7 1643 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1644 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 1645 * @retval HAL state
<> 144:ef7eb2e8f9f7 1646 */
<> 144:ef7eb2e8f9f7 1647 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 1648 {
<> 144:ef7eb2e8f9f7 1649 return hdma2d->State;
<> 144:ef7eb2e8f9f7 1650 }
<> 144:ef7eb2e8f9f7 1651
<> 144:ef7eb2e8f9f7 1652 /**
<> 144:ef7eb2e8f9f7 1653 * @brief Return the DMA2D error code
<> 144:ef7eb2e8f9f7 1654 * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1655 * the configuration information for DMA2D.
<> 144:ef7eb2e8f9f7 1656 * @retval DMA2D Error Code
<> 144:ef7eb2e8f9f7 1657 */
<> 144:ef7eb2e8f9f7 1658 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 1659 {
<> 144:ef7eb2e8f9f7 1660 return hdma2d->ErrorCode;
<> 144:ef7eb2e8f9f7 1661 }
<> 144:ef7eb2e8f9f7 1662
<> 144:ef7eb2e8f9f7 1663 /**
<> 144:ef7eb2e8f9f7 1664 * @}
<> 144:ef7eb2e8f9f7 1665 */
<> 144:ef7eb2e8f9f7 1666
<> 144:ef7eb2e8f9f7 1667 /**
<> 144:ef7eb2e8f9f7 1668 * @}
<> 144:ef7eb2e8f9f7 1669 */
<> 144:ef7eb2e8f9f7 1670
<> 144:ef7eb2e8f9f7 1671
<> 144:ef7eb2e8f9f7 1672 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
<> 144:ef7eb2e8f9f7 1673 * @{
<> 144:ef7eb2e8f9f7 1674 */
<> 144:ef7eb2e8f9f7 1675
<> 144:ef7eb2e8f9f7 1676 /**
<> 144:ef7eb2e8f9f7 1677 * @brief Set the DMA2D transfer parameters.
<> 144:ef7eb2e8f9f7 1678 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1679 * the configuration information for the specified DMA2D.
<> 144:ef7eb2e8f9f7 1680 * @param pdata: The source memory Buffer address
<> 144:ef7eb2e8f9f7 1681 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 1682 * @param Width: The width of data to be transferred from source to destination.
<> 144:ef7eb2e8f9f7 1683 * @param Height: The height of data to be transferred from source to destination.
<> 144:ef7eb2e8f9f7 1684 * @retval HAL status
<> 144:ef7eb2e8f9f7 1685 */
<> 144:ef7eb2e8f9f7 1686 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
<> 144:ef7eb2e8f9f7 1687 {
<> 144:ef7eb2e8f9f7 1688 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 1689 uint32_t tmp1 = 0;
<> 144:ef7eb2e8f9f7 1690 uint32_t tmp2 = 0;
<> 144:ef7eb2e8f9f7 1691 uint32_t tmp3 = 0;
<> 144:ef7eb2e8f9f7 1692 uint32_t tmp4 = 0;
<> 144:ef7eb2e8f9f7 1693
<> 144:ef7eb2e8f9f7 1694 /* Configure DMA2D data size */
<> 144:ef7eb2e8f9f7 1695 MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL)));
<> 144:ef7eb2e8f9f7 1696
<> 144:ef7eb2e8f9f7 1697 /* Configure DMA2D destination address */
<> 144:ef7eb2e8f9f7 1698 WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
<> 144:ef7eb2e8f9f7 1699
<> 144:ef7eb2e8f9f7 1700 /* Register to memory DMA2D mode selected */
<> 144:ef7eb2e8f9f7 1701 if (hdma2d->Init.Mode == DMA2D_R2M)
<> 144:ef7eb2e8f9f7 1702 {
<> 144:ef7eb2e8f9f7 1703 tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
<> 144:ef7eb2e8f9f7 1704 tmp2 = pdata & DMA2D_OCOLR_RED_1;
<> 144:ef7eb2e8f9f7 1705 tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
<> 144:ef7eb2e8f9f7 1706 tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
<> 144:ef7eb2e8f9f7 1707
<> 144:ef7eb2e8f9f7 1708 /* Prepare the value to be written to the OCOLR register according to the color mode */
<> 144:ef7eb2e8f9f7 1709 if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
<> 144:ef7eb2e8f9f7 1710 {
<> 144:ef7eb2e8f9f7 1711 tmp = (tmp3 | tmp2 | tmp1| tmp4);
<> 144:ef7eb2e8f9f7 1712 }
<> 144:ef7eb2e8f9f7 1713 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
<> 144:ef7eb2e8f9f7 1714 {
<> 144:ef7eb2e8f9f7 1715 tmp = (tmp3 | tmp2 | tmp4);
<> 144:ef7eb2e8f9f7 1716 }
<> 144:ef7eb2e8f9f7 1717 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
<> 144:ef7eb2e8f9f7 1718 {
<> 144:ef7eb2e8f9f7 1719 tmp2 = (tmp2 >> 19);
<> 144:ef7eb2e8f9f7 1720 tmp3 = (tmp3 >> 10);
<> 144:ef7eb2e8f9f7 1721 tmp4 = (tmp4 >> 3 );
<> 144:ef7eb2e8f9f7 1722 tmp = ((tmp3 << 5) | (tmp2 << 11) | tmp4);
<> 144:ef7eb2e8f9f7 1723 }
<> 144:ef7eb2e8f9f7 1724 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
<> 144:ef7eb2e8f9f7 1725 {
<> 144:ef7eb2e8f9f7 1726 tmp1 = (tmp1 >> 31);
<> 144:ef7eb2e8f9f7 1727 tmp2 = (tmp2 >> 19);
<> 144:ef7eb2e8f9f7 1728 tmp3 = (tmp3 >> 11);
<> 144:ef7eb2e8f9f7 1729 tmp4 = (tmp4 >> 3 );
<> 144:ef7eb2e8f9f7 1730 tmp = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4);
<> 144:ef7eb2e8f9f7 1731 }
<> 144:ef7eb2e8f9f7 1732 else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
<> 144:ef7eb2e8f9f7 1733 {
<> 144:ef7eb2e8f9f7 1734 tmp1 = (tmp1 >> 28);
<> 144:ef7eb2e8f9f7 1735 tmp2 = (tmp2 >> 20);
<> 144:ef7eb2e8f9f7 1736 tmp3 = (tmp3 >> 12);
<> 144:ef7eb2e8f9f7 1737 tmp4 = (tmp4 >> 4 );
<> 144:ef7eb2e8f9f7 1738 tmp = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4);
<> 144:ef7eb2e8f9f7 1739 }
<> 144:ef7eb2e8f9f7 1740 /* Write to DMA2D OCOLR register */
<> 144:ef7eb2e8f9f7 1741 WRITE_REG(hdma2d->Instance->OCOLR, tmp);
<> 144:ef7eb2e8f9f7 1742 }
<> 144:ef7eb2e8f9f7 1743 else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
<> 144:ef7eb2e8f9f7 1744 {
<> 144:ef7eb2e8f9f7 1745 /* Configure DMA2D source address */
<> 144:ef7eb2e8f9f7 1746 WRITE_REG(hdma2d->Instance->FGMAR, pdata);
<> 144:ef7eb2e8f9f7 1747 }
<> 144:ef7eb2e8f9f7 1748 }
<> 144:ef7eb2e8f9f7 1749
<> 144:ef7eb2e8f9f7 1750 /**
<> 144:ef7eb2e8f9f7 1751 * @}
<> 144:ef7eb2e8f9f7 1752 */
<> 144:ef7eb2e8f9f7 1753 #endif /* HAL_DMA2D_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1754 /**
<> 144:ef7eb2e8f9f7 1755 * @}
<> 144:ef7eb2e8f9f7 1756 */
<> 144:ef7eb2e8f9f7 1757
<> 144:ef7eb2e8f9f7 1758 /**
<> 144:ef7eb2e8f9f7 1759 * @}
<> 144:ef7eb2e8f9f7 1760 */
<> 144:ef7eb2e8f9f7 1761
<> 144:ef7eb2e8f9f7 1762 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/