Kevin Kadooka / mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
83:a036322b8637 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_sdram.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief SDRAM HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides a generic firmware to drive SDRAM memories mounted
<> 144:ef7eb2e8f9f7 9 * as external device.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 [..]
<> 144:ef7eb2e8f9f7 16 This driver is a generic layered driver which contains a set of APIs used to
<> 144:ef7eb2e8f9f7 17 control SDRAM memories. It uses the FMC layer functions to interface
<> 144:ef7eb2e8f9f7 18 with SDRAM devices.
<> 144:ef7eb2e8f9f7 19 The following sequence should be followed to configure the FMC to interface
<> 144:ef7eb2e8f9f7 20 with SDRAM memories:
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
<> 144:ef7eb2e8f9f7 23 SDRAM_HandleTypeDef hdsram
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
<> 144:ef7eb2e8f9f7 26 values of the structure member.
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
<> 144:ef7eb2e8f9f7 29 base register instance for NOR or SDRAM device
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
<> 144:ef7eb2e8f9f7 32 FMC_SDRAM_TimingTypeDef Timing;
<> 144:ef7eb2e8f9f7 33 and fill its fields with the allowed values of the structure member.
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
<> 144:ef7eb2e8f9f7 36 performs the following sequence:
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
<> 144:ef7eb2e8f9f7 39 (##) Control register configuration using the FMC SDRAM interface function
<> 144:ef7eb2e8f9f7 40 FMC_SDRAM_Init()
<> 144:ef7eb2e8f9f7 41 (##) Timing register configuration using the FMC SDRAM interface function
<> 144:ef7eb2e8f9f7 42 FMC_SDRAM_Timing_Init()
<> 144:ef7eb2e8f9f7 43 (##) Program the SDRAM external device by applying its initialization sequence
<> 144:ef7eb2e8f9f7 44 according to the device plugged in your hardware. This step is mandatory
<> 144:ef7eb2e8f9f7 45 for accessing the SDRAM device.
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 (#) At this stage you can perform read/write accesses from/to the memory connected
<> 144:ef7eb2e8f9f7 48 to the SDRAM Bank. You can perform either polling or DMA transfer using the
<> 144:ef7eb2e8f9f7 49 following APIs:
<> 144:ef7eb2e8f9f7 50 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
<> 144:ef7eb2e8f9f7 51 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
<> 144:ef7eb2e8f9f7 54 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
<> 144:ef7eb2e8f9f7 55 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
<> 144:ef7eb2e8f9f7 56 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
<> 144:ef7eb2e8f9f7 57 structure.
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 (#) You can continuously monitor the SDRAM device HAL state by calling the function
<> 144:ef7eb2e8f9f7 60 HAL_SDRAM_GetState()
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 @endverbatim
<> 144:ef7eb2e8f9f7 63 ******************************************************************************
<> 144:ef7eb2e8f9f7 64 * @attention
<> 144:ef7eb2e8f9f7 65 *
<> 144:ef7eb2e8f9f7 66 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 67 *
<> 144:ef7eb2e8f9f7 68 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 69 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 70 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 71 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 72 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 73 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 74 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 75 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 76 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 77 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 78 *
<> 144:ef7eb2e8f9f7 79 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 80 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 82 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 85 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 86 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 87 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 88 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 89 *
<> 144:ef7eb2e8f9f7 90 ******************************************************************************
<> 144:ef7eb2e8f9f7 91 */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 94 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 97 * @{
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /** @defgroup SDRAM SDRAM
<> 144:ef7eb2e8f9f7 101 * @brief SDRAM driver modules
<> 144:ef7eb2e8f9f7 102 * @{
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104 #ifdef HAL_SDRAM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 107 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 108 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 109 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 110 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 111 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 112 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
<> 144:ef7eb2e8f9f7 113 * @{
<> 144:ef7eb2e8f9f7 114 */
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 117 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 118 *
<> 144:ef7eb2e8f9f7 119 @verbatim
<> 144:ef7eb2e8f9f7 120 ==============================================================================
<> 144:ef7eb2e8f9f7 121 ##### SDRAM Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 122 ==============================================================================
<> 144:ef7eb2e8f9f7 123 [..]
<> 144:ef7eb2e8f9f7 124 This section provides functions allowing to initialize/de-initialize
<> 144:ef7eb2e8f9f7 125 the SDRAM memory
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 @endverbatim
<> 144:ef7eb2e8f9f7 128 * @{
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /**
<> 144:ef7eb2e8f9f7 132 * @brief Performs the SDRAM device initialization sequence.
<> 144:ef7eb2e8f9f7 133 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 134 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 135 * @param Timing: Pointer to SDRAM control timing structure
<> 144:ef7eb2e8f9f7 136 * @retval HAL status
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
<> 144:ef7eb2e8f9f7 139 {
<> 144:ef7eb2e8f9f7 140 /* Check the SDRAM handle parameter */
<> 144:ef7eb2e8f9f7 141 if(hsdram == NULL)
<> 144:ef7eb2e8f9f7 142 {
<> 144:ef7eb2e8f9f7 143 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 144 }
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 if(hsdram->State == HAL_SDRAM_STATE_RESET)
<> 144:ef7eb2e8f9f7 147 {
<> 144:ef7eb2e8f9f7 148 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 149 hsdram->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 150 /* Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 151 HAL_SDRAM_MspInit(hsdram);
<> 144:ef7eb2e8f9f7 152 }
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /* Initialize the SDRAM controller state */
<> 144:ef7eb2e8f9f7 155 hsdram->State = HAL_SDRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /* Initialize SDRAM control Interface */
<> 144:ef7eb2e8f9f7 158 FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Initialize SDRAM timing Interface */
<> 144:ef7eb2e8f9f7 161 FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /* Update the SDRAM controller state */
<> 144:ef7eb2e8f9f7 164 hsdram->State = HAL_SDRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 return HAL_OK;
<> 144:ef7eb2e8f9f7 167 }
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /**
<> 144:ef7eb2e8f9f7 170 * @brief Perform the SDRAM device initialization sequence.
<> 144:ef7eb2e8f9f7 171 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 172 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 173 * @retval HAL status
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
<> 144:ef7eb2e8f9f7 176 {
<> 144:ef7eb2e8f9f7 177 /* Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 178 HAL_SDRAM_MspDeInit(hsdram);
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* Configure the SDRAM registers with their reset values */
<> 144:ef7eb2e8f9f7 181 FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /* Reset the SDRAM controller state */
<> 144:ef7eb2e8f9f7 184 hsdram->State = HAL_SDRAM_STATE_RESET;
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Release Lock */
<> 144:ef7eb2e8f9f7 187 __HAL_UNLOCK(hsdram);
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 return HAL_OK;
<> 144:ef7eb2e8f9f7 190 }
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /**
<> 144:ef7eb2e8f9f7 193 * @brief SDRAM MSP Init.
<> 144:ef7eb2e8f9f7 194 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 195 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 196 * @retval None
<> 144:ef7eb2e8f9f7 197 */
<> 144:ef7eb2e8f9f7 198 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
<> 144:ef7eb2e8f9f7 199 {
<> 144:ef7eb2e8f9f7 200 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 201 UNUSED(hsdram);
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 204 the HAL_SDRAM_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 205 */
<> 144:ef7eb2e8f9f7 206 }
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /**
<> 144:ef7eb2e8f9f7 209 * @brief SDRAM MSP DeInit.
<> 144:ef7eb2e8f9f7 210 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 211 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 212 * @retval None
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
<> 144:ef7eb2e8f9f7 215 {
<> 144:ef7eb2e8f9f7 216 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 217 UNUSED(hsdram);
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 220 the HAL_SDRAM_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 221 */
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /**
<> 144:ef7eb2e8f9f7 225 * @brief This function handles SDRAM refresh error interrupt request.
<> 144:ef7eb2e8f9f7 226 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 227 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 228 * @retval HAL status
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 /* Check SDRAM interrupt Rising edge flag */
<> 144:ef7eb2e8f9f7 233 if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 /* SDRAM refresh error interrupt callback */
<> 144:ef7eb2e8f9f7 236 HAL_SDRAM_RefreshErrorCallback(hsdram);
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /* Clear SDRAM refresh error interrupt pending bit */
<> 144:ef7eb2e8f9f7 239 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
<> 144:ef7eb2e8f9f7 240 }
<> 144:ef7eb2e8f9f7 241 }
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /**
<> 144:ef7eb2e8f9f7 244 * @brief SDRAM Refresh error callback.
<> 144:ef7eb2e8f9f7 245 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 246 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 247 * @retval None
<> 144:ef7eb2e8f9f7 248 */
<> 144:ef7eb2e8f9f7 249 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
<> 144:ef7eb2e8f9f7 250 {
<> 144:ef7eb2e8f9f7 251 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 252 UNUSED(hsdram);
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 255 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257 }
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /**
<> 144:ef7eb2e8f9f7 260 * @brief DMA transfer complete callback.
<> 144:ef7eb2e8f9f7 261 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 262 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 263 * @retval None
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 268 UNUSED(hdma);
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 271 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273 }
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /**
<> 144:ef7eb2e8f9f7 276 * @brief DMA transfer complete error callback.
<> 144:ef7eb2e8f9f7 277 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 278 * @retval None
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 281 {
<> 144:ef7eb2e8f9f7 282 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 283 UNUSED(hdma);
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 286 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288 }
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /**
<> 144:ef7eb2e8f9f7 291 * @}
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
<> 144:ef7eb2e8f9f7 295 * @brief Input Output and memory control functions
<> 144:ef7eb2e8f9f7 296 *
<> 144:ef7eb2e8f9f7 297 @verbatim
<> 144:ef7eb2e8f9f7 298 ==============================================================================
<> 144:ef7eb2e8f9f7 299 ##### SDRAM Input and Output functions #####
<> 144:ef7eb2e8f9f7 300 ==============================================================================
<> 144:ef7eb2e8f9f7 301 [..]
<> 144:ef7eb2e8f9f7 302 This section provides functions allowing to use and control the SDRAM memory
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 @endverbatim
<> 144:ef7eb2e8f9f7 305 * @{
<> 144:ef7eb2e8f9f7 306 */
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /**
<> 144:ef7eb2e8f9f7 309 * @brief Reads 8-bit data buffer from the SDRAM memory.
<> 144:ef7eb2e8f9f7 310 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 311 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 312 * @param pAddress: Pointer to read start address
<> 144:ef7eb2e8f9f7 313 * @param pDstBuffer: Pointer to destination buffer
<> 144:ef7eb2e8f9f7 314 * @param BufferSize: Size of the buffer to read from memory
<> 144:ef7eb2e8f9f7 315 * @retval HAL status
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /* Process Locked */
<> 144:ef7eb2e8f9f7 322 __HAL_LOCK(hsdram);
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /* Check the SDRAM controller state */
<> 144:ef7eb2e8f9f7 325 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
<> 144:ef7eb2e8f9f7 326 {
<> 144:ef7eb2e8f9f7 327 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 328 }
<> 144:ef7eb2e8f9f7 329 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
<> 144:ef7eb2e8f9f7 330 {
<> 144:ef7eb2e8f9f7 331 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 332 }
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* Read data from source */
<> 144:ef7eb2e8f9f7 335 for(; BufferSize != 0; BufferSize--)
<> 144:ef7eb2e8f9f7 336 {
<> 144:ef7eb2e8f9f7 337 *pDstBuffer = *(__IO uint8_t *)pSdramAddress;
<> 144:ef7eb2e8f9f7 338 pDstBuffer++;
<> 144:ef7eb2e8f9f7 339 pSdramAddress++;
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 343 __HAL_UNLOCK(hsdram);
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 return HAL_OK;
<> 144:ef7eb2e8f9f7 346 }
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /**
<> 144:ef7eb2e8f9f7 350 * @brief Writes 8-bit data buffer to SDRAM memory.
<> 144:ef7eb2e8f9f7 351 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 352 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 353 * @param pAddress: Pointer to write start address
<> 144:ef7eb2e8f9f7 354 * @param pSrcBuffer: Pointer to source buffer to write
<> 144:ef7eb2e8f9f7 355 * @param BufferSize: Size of the buffer to write to memory
<> 144:ef7eb2e8f9f7 356 * @retval HAL status
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 359 {
<> 144:ef7eb2e8f9f7 360 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
<> 144:ef7eb2e8f9f7 361 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /* Process Locked */
<> 144:ef7eb2e8f9f7 364 __HAL_LOCK(hsdram);
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /* Check the SDRAM controller state */
<> 144:ef7eb2e8f9f7 367 tmp = hsdram->State;
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 if(tmp == HAL_SDRAM_STATE_BUSY)
<> 144:ef7eb2e8f9f7 370 {
<> 144:ef7eb2e8f9f7 371 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 372 }
<> 144:ef7eb2e8f9f7 373 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
<> 144:ef7eb2e8f9f7 374 {
<> 144:ef7eb2e8f9f7 375 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 376 }
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /* Write data to memory */
<> 144:ef7eb2e8f9f7 379 for(; BufferSize != 0; BufferSize--)
<> 144:ef7eb2e8f9f7 380 {
<> 144:ef7eb2e8f9f7 381 *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
<> 144:ef7eb2e8f9f7 382 pSrcBuffer++;
<> 144:ef7eb2e8f9f7 383 pSdramAddress++;
<> 144:ef7eb2e8f9f7 384 }
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 387 __HAL_UNLOCK(hsdram);
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 return HAL_OK;
<> 144:ef7eb2e8f9f7 390 }
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /**
<> 144:ef7eb2e8f9f7 394 * @brief Reads 16-bit data buffer from the SDRAM memory.
<> 144:ef7eb2e8f9f7 395 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 396 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 397 * @param pAddress: Pointer to read start address
<> 144:ef7eb2e8f9f7 398 * @param pDstBuffer: Pointer to destination buffer
<> 144:ef7eb2e8f9f7 399 * @param BufferSize: Size of the buffer to read from memory
<> 144:ef7eb2e8f9f7 400 * @retval HAL status
<> 144:ef7eb2e8f9f7 401 */
<> 144:ef7eb2e8f9f7 402 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /* Process Locked */
<> 144:ef7eb2e8f9f7 407 __HAL_LOCK(hsdram);
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /* Check the SDRAM controller state */
<> 144:ef7eb2e8f9f7 410 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
<> 144:ef7eb2e8f9f7 411 {
<> 144:ef7eb2e8f9f7 412 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 413 }
<> 144:ef7eb2e8f9f7 414 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
<> 144:ef7eb2e8f9f7 415 {
<> 144:ef7eb2e8f9f7 416 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 417 }
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Read data from source */
<> 144:ef7eb2e8f9f7 420 for(; BufferSize != 0; BufferSize--)
<> 144:ef7eb2e8f9f7 421 {
<> 144:ef7eb2e8f9f7 422 *pDstBuffer = *(__IO uint16_t *)pSdramAddress;
<> 144:ef7eb2e8f9f7 423 pDstBuffer++;
<> 144:ef7eb2e8f9f7 424 pSdramAddress++;
<> 144:ef7eb2e8f9f7 425 }
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 428 __HAL_UNLOCK(hsdram);
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 return HAL_OK;
<> 144:ef7eb2e8f9f7 431 }
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /**
<> 144:ef7eb2e8f9f7 434 * @brief Writes 16-bit data buffer to SDRAM memory.
<> 144:ef7eb2e8f9f7 435 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 436 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 437 * @param pAddress: Pointer to write start address
<> 144:ef7eb2e8f9f7 438 * @param pSrcBuffer: Pointer to source buffer to write
<> 144:ef7eb2e8f9f7 439 * @param BufferSize: Size of the buffer to write to memory
<> 144:ef7eb2e8f9f7 440 * @retval HAL status
<> 144:ef7eb2e8f9f7 441 */
<> 144:ef7eb2e8f9f7 442 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 443 {
<> 144:ef7eb2e8f9f7 444 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
<> 144:ef7eb2e8f9f7 445 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /* Process Locked */
<> 144:ef7eb2e8f9f7 448 __HAL_LOCK(hsdram);
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /* Check the SDRAM controller state */
<> 144:ef7eb2e8f9f7 451 tmp = hsdram->State;
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 if(tmp == HAL_SDRAM_STATE_BUSY)
<> 144:ef7eb2e8f9f7 454 {
<> 144:ef7eb2e8f9f7 455 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 456 }
<> 144:ef7eb2e8f9f7 457 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
<> 144:ef7eb2e8f9f7 458 {
<> 144:ef7eb2e8f9f7 459 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 460 }
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /* Write data to memory */
<> 144:ef7eb2e8f9f7 463 for(; BufferSize != 0; BufferSize--)
<> 144:ef7eb2e8f9f7 464 {
<> 144:ef7eb2e8f9f7 465 *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
<> 144:ef7eb2e8f9f7 466 pSrcBuffer++;
<> 144:ef7eb2e8f9f7 467 pSdramAddress++;
<> 144:ef7eb2e8f9f7 468 }
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 471 __HAL_UNLOCK(hsdram);
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 return HAL_OK;
<> 144:ef7eb2e8f9f7 474 }
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /**
<> 144:ef7eb2e8f9f7 477 * @brief Reads 32-bit data buffer from the SDRAM memory.
<> 144:ef7eb2e8f9f7 478 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 479 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 480 * @param pAddress: Pointer to read start address
<> 144:ef7eb2e8f9f7 481 * @param pDstBuffer: Pointer to destination buffer
<> 144:ef7eb2e8f9f7 482 * @param BufferSize: Size of the buffer to read from memory
<> 144:ef7eb2e8f9f7 483 * @retval HAL status
<> 144:ef7eb2e8f9f7 484 */
<> 144:ef7eb2e8f9f7 485 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 486 {
<> 144:ef7eb2e8f9f7 487 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /* Process Locked */
<> 144:ef7eb2e8f9f7 490 __HAL_LOCK(hsdram);
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 /* Check the SDRAM controller state */
<> 144:ef7eb2e8f9f7 493 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
<> 144:ef7eb2e8f9f7 494 {
<> 144:ef7eb2e8f9f7 495 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 496 }
<> 144:ef7eb2e8f9f7 497 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
<> 144:ef7eb2e8f9f7 498 {
<> 144:ef7eb2e8f9f7 499 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 500 }
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /* Read data from source */
<> 144:ef7eb2e8f9f7 503 for(; BufferSize != 0; BufferSize--)
<> 144:ef7eb2e8f9f7 504 {
<> 144:ef7eb2e8f9f7 505 *pDstBuffer = *(__IO uint32_t *)pSdramAddress;
<> 144:ef7eb2e8f9f7 506 pDstBuffer++;
<> 144:ef7eb2e8f9f7 507 pSdramAddress++;
<> 144:ef7eb2e8f9f7 508 }
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 511 __HAL_UNLOCK(hsdram);
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 return HAL_OK;
<> 144:ef7eb2e8f9f7 514 }
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 /**
<> 144:ef7eb2e8f9f7 517 * @brief Writes 32-bit data buffer to SDRAM memory.
<> 144:ef7eb2e8f9f7 518 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 519 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 520 * @param pAddress: Pointer to write start address
<> 144:ef7eb2e8f9f7 521 * @param pSrcBuffer: Pointer to source buffer to write
<> 144:ef7eb2e8f9f7 522 * @param BufferSize: Size of the buffer to write to memory
<> 144:ef7eb2e8f9f7 523 * @retval HAL status
<> 144:ef7eb2e8f9f7 524 */
<> 144:ef7eb2e8f9f7 525 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 526 {
<> 144:ef7eb2e8f9f7 527 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
<> 144:ef7eb2e8f9f7 528 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /* Process Locked */
<> 144:ef7eb2e8f9f7 531 __HAL_LOCK(hsdram);
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /* Check the SDRAM controller state */
<> 144:ef7eb2e8f9f7 534 tmp = hsdram->State;
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 if(tmp == HAL_SDRAM_STATE_BUSY)
<> 144:ef7eb2e8f9f7 537 {
<> 144:ef7eb2e8f9f7 538 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 539 }
<> 144:ef7eb2e8f9f7 540 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
<> 144:ef7eb2e8f9f7 541 {
<> 144:ef7eb2e8f9f7 542 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 543 }
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /* Write data to memory */
<> 144:ef7eb2e8f9f7 546 for(; BufferSize != 0; BufferSize--)
<> 144:ef7eb2e8f9f7 547 {
<> 144:ef7eb2e8f9f7 548 *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
<> 144:ef7eb2e8f9f7 549 pSrcBuffer++;
<> 144:ef7eb2e8f9f7 550 pSdramAddress++;
<> 144:ef7eb2e8f9f7 551 }
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 554 __HAL_UNLOCK(hsdram);
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 return HAL_OK;
<> 144:ef7eb2e8f9f7 557 }
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /**
<> 144:ef7eb2e8f9f7 560 * @brief Reads a Words data from the SDRAM memory using DMA transfer.
<> 144:ef7eb2e8f9f7 561 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 562 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 563 * @param pAddress: Pointer to read start address
<> 144:ef7eb2e8f9f7 564 * @param pDstBuffer: Pointer to destination buffer
<> 144:ef7eb2e8f9f7 565 * @param BufferSize: Size of the buffer to read from memory
<> 144:ef7eb2e8f9f7 566 * @retval HAL status
<> 144:ef7eb2e8f9f7 567 */
<> 144:ef7eb2e8f9f7 568 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 569 {
<> 144:ef7eb2e8f9f7 570 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /* Process Locked */
<> 144:ef7eb2e8f9f7 573 __HAL_LOCK(hsdram);
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /* Check the SDRAM controller state */
<> 144:ef7eb2e8f9f7 576 tmp = hsdram->State;
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 if(tmp == HAL_SDRAM_STATE_BUSY)
<> 144:ef7eb2e8f9f7 579 {
<> 144:ef7eb2e8f9f7 580 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 581 }
<> 144:ef7eb2e8f9f7 582 else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
<> 144:ef7eb2e8f9f7 583 {
<> 144:ef7eb2e8f9f7 584 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 /* Configure DMA user callbacks */
<> 144:ef7eb2e8f9f7 588 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
<> 144:ef7eb2e8f9f7 589 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 592 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 595 __HAL_UNLOCK(hsdram);
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 return HAL_OK;
<> 144:ef7eb2e8f9f7 598 }
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 /**
<> 144:ef7eb2e8f9f7 601 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
<> 144:ef7eb2e8f9f7 602 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 603 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 604 * @param pAddress: Pointer to write start address
<> 144:ef7eb2e8f9f7 605 * @param pSrcBuffer: Pointer to source buffer to write
<> 144:ef7eb2e8f9f7 606 * @param BufferSize: Size of the buffer to write to memory
<> 144:ef7eb2e8f9f7 607 * @retval HAL status
<> 144:ef7eb2e8f9f7 608 */
<> 144:ef7eb2e8f9f7 609 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 610 {
<> 144:ef7eb2e8f9f7 611 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 /* Process Locked */
<> 144:ef7eb2e8f9f7 614 __HAL_LOCK(hsdram);
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /* Check the SDRAM controller state */
<> 144:ef7eb2e8f9f7 617 tmp = hsdram->State;
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 if(tmp == HAL_SDRAM_STATE_BUSY)
<> 144:ef7eb2e8f9f7 620 {
<> 144:ef7eb2e8f9f7 621 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 622 }
<> 144:ef7eb2e8f9f7 623 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
<> 144:ef7eb2e8f9f7 624 {
<> 144:ef7eb2e8f9f7 625 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 626 }
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /* Configure DMA user callbacks */
<> 144:ef7eb2e8f9f7 629 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
<> 144:ef7eb2e8f9f7 630 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 633 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 636 __HAL_UNLOCK(hsdram);
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 return HAL_OK;
<> 144:ef7eb2e8f9f7 639 }
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /**
<> 144:ef7eb2e8f9f7 642 * @}
<> 144:ef7eb2e8f9f7 643 */
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
<> 144:ef7eb2e8f9f7 646 * @brief management functions
<> 144:ef7eb2e8f9f7 647 *
<> 144:ef7eb2e8f9f7 648 @verbatim
<> 144:ef7eb2e8f9f7 649 ==============================================================================
<> 144:ef7eb2e8f9f7 650 ##### SDRAM Control functions #####
<> 144:ef7eb2e8f9f7 651 ==============================================================================
<> 144:ef7eb2e8f9f7 652 [..]
<> 144:ef7eb2e8f9f7 653 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 654 the SDRAM interface.
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 @endverbatim
<> 144:ef7eb2e8f9f7 657 * @{
<> 144:ef7eb2e8f9f7 658 */
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 /**
<> 144:ef7eb2e8f9f7 661 * @brief Enables dynamically SDRAM write protection.
<> 144:ef7eb2e8f9f7 662 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 663 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 664 * @retval HAL status
<> 144:ef7eb2e8f9f7 665 */
<> 144:ef7eb2e8f9f7 666 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
<> 144:ef7eb2e8f9f7 667 {
<> 144:ef7eb2e8f9f7 668 /* Check the SDRAM controller state */
<> 144:ef7eb2e8f9f7 669 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
<> 144:ef7eb2e8f9f7 670 {
<> 144:ef7eb2e8f9f7 671 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 672 }
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /* Update the SDRAM state */
<> 144:ef7eb2e8f9f7 675 hsdram->State = HAL_SDRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /* Enable write protection */
<> 144:ef7eb2e8f9f7 678 FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 /* Update the SDRAM state */
<> 144:ef7eb2e8f9f7 681 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 return HAL_OK;
<> 144:ef7eb2e8f9f7 684 }
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 /**
<> 144:ef7eb2e8f9f7 687 * @brief Disables dynamically SDRAM write protection.
<> 144:ef7eb2e8f9f7 688 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 689 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 690 * @retval HAL status
<> 144:ef7eb2e8f9f7 691 */
<> 144:ef7eb2e8f9f7 692 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
<> 144:ef7eb2e8f9f7 693 {
<> 144:ef7eb2e8f9f7 694 /* Check the SDRAM controller state */
<> 144:ef7eb2e8f9f7 695 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
<> 144:ef7eb2e8f9f7 696 {
<> 144:ef7eb2e8f9f7 697 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 698 }
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /* Update the SDRAM state */
<> 144:ef7eb2e8f9f7 701 hsdram->State = HAL_SDRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /* Disable write protection */
<> 144:ef7eb2e8f9f7 704 FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 /* Update the SDRAM state */
<> 144:ef7eb2e8f9f7 707 hsdram->State = HAL_SDRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 return HAL_OK;
<> 144:ef7eb2e8f9f7 710 }
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 /**
<> 144:ef7eb2e8f9f7 713 * @brief Sends Command to the SDRAM bank.
<> 144:ef7eb2e8f9f7 714 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 715 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 716 * @param Command: SDRAM command structure
<> 144:ef7eb2e8f9f7 717 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 718 * @retval HAL status
<> 144:ef7eb2e8f9f7 719 */
<> 144:ef7eb2e8f9f7 720 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 721 {
<> 144:ef7eb2e8f9f7 722 /* Check the SDRAM controller state */
<> 144:ef7eb2e8f9f7 723 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
<> 144:ef7eb2e8f9f7 724 {
<> 144:ef7eb2e8f9f7 725 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 726 }
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 /* Update the SDRAM state */
<> 144:ef7eb2e8f9f7 729 hsdram->State = HAL_SDRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 /* Send SDRAM command */
<> 144:ef7eb2e8f9f7 732 FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /* Update the SDRAM controller state state */
<> 144:ef7eb2e8f9f7 735 if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
<> 144:ef7eb2e8f9f7 736 {
<> 144:ef7eb2e8f9f7 737 hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
<> 144:ef7eb2e8f9f7 738 }
<> 144:ef7eb2e8f9f7 739 else
<> 144:ef7eb2e8f9f7 740 {
<> 144:ef7eb2e8f9f7 741 hsdram->State = HAL_SDRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 742 }
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744 return HAL_OK;
<> 144:ef7eb2e8f9f7 745 }
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 /**
<> 144:ef7eb2e8f9f7 748 * @brief Programs the SDRAM Memory Refresh rate.
<> 144:ef7eb2e8f9f7 749 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 750 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 751 * @param RefreshRate: The SDRAM refresh rate value
<> 144:ef7eb2e8f9f7 752 * @retval HAL status
<> 144:ef7eb2e8f9f7 753 */
<> 144:ef7eb2e8f9f7 754 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
<> 144:ef7eb2e8f9f7 755 {
<> 144:ef7eb2e8f9f7 756 /* Check the SDRAM controller state */
<> 144:ef7eb2e8f9f7 757 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
<> 144:ef7eb2e8f9f7 758 {
<> 144:ef7eb2e8f9f7 759 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 760 }
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /* Update the SDRAM state */
<> 144:ef7eb2e8f9f7 763 hsdram->State = HAL_SDRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /* Program the refresh rate */
<> 144:ef7eb2e8f9f7 766 FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 /* Update the SDRAM state */
<> 144:ef7eb2e8f9f7 769 hsdram->State = HAL_SDRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 return HAL_OK;
<> 144:ef7eb2e8f9f7 772 }
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 /**
<> 144:ef7eb2e8f9f7 775 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
<> 144:ef7eb2e8f9f7 776 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 777 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 778 * @param AutoRefreshNumber: The SDRAM auto Refresh number
<> 144:ef7eb2e8f9f7 779 * @retval HAL status
<> 144:ef7eb2e8f9f7 780 */
<> 144:ef7eb2e8f9f7 781 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
<> 144:ef7eb2e8f9f7 782 {
<> 144:ef7eb2e8f9f7 783 /* Check the SDRAM controller state */
<> 144:ef7eb2e8f9f7 784 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
<> 144:ef7eb2e8f9f7 785 {
<> 144:ef7eb2e8f9f7 786 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 787 }
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 /* Update the SDRAM state */
<> 144:ef7eb2e8f9f7 790 hsdram->State = HAL_SDRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 /* Set the Auto-Refresh number */
<> 144:ef7eb2e8f9f7 793 FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 /* Update the SDRAM state */
<> 144:ef7eb2e8f9f7 796 hsdram->State = HAL_SDRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 797
<> 144:ef7eb2e8f9f7 798 return HAL_OK;
<> 144:ef7eb2e8f9f7 799 }
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 /**
<> 144:ef7eb2e8f9f7 802 * @brief Returns the SDRAM memory current mode.
<> 144:ef7eb2e8f9f7 803 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 804 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 805 * @retval The SDRAM memory mode.
<> 144:ef7eb2e8f9f7 806 */
<> 144:ef7eb2e8f9f7 807 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
<> 144:ef7eb2e8f9f7 808 {
<> 144:ef7eb2e8f9f7 809 /* Return the SDRAM memory current mode */
<> 144:ef7eb2e8f9f7 810 return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
<> 144:ef7eb2e8f9f7 811 }
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 /**
<> 144:ef7eb2e8f9f7 814 * @}
<> 144:ef7eb2e8f9f7 815 */
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
<> 144:ef7eb2e8f9f7 818 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 819 *
<> 144:ef7eb2e8f9f7 820 @verbatim
<> 144:ef7eb2e8f9f7 821 ==============================================================================
<> 144:ef7eb2e8f9f7 822 ##### SDRAM State functions #####
<> 144:ef7eb2e8f9f7 823 ==============================================================================
<> 144:ef7eb2e8f9f7 824 [..]
<> 144:ef7eb2e8f9f7 825 This subsection permits to get in run-time the status of the SDRAM controller
<> 144:ef7eb2e8f9f7 826 and the data flow.
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 @endverbatim
<> 144:ef7eb2e8f9f7 829 * @{
<> 144:ef7eb2e8f9f7 830 */
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832 /**
<> 144:ef7eb2e8f9f7 833 * @brief Returns the SDRAM state.
<> 144:ef7eb2e8f9f7 834 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 835 * the configuration information for SDRAM module.
<> 144:ef7eb2e8f9f7 836 * @retval HAL state
<> 144:ef7eb2e8f9f7 837 */
<> 144:ef7eb2e8f9f7 838 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
<> 144:ef7eb2e8f9f7 839 {
<> 144:ef7eb2e8f9f7 840 return hsdram->State;
<> 144:ef7eb2e8f9f7 841 }
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /**
<> 144:ef7eb2e8f9f7 844 * @}
<> 144:ef7eb2e8f9f7 845 */
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /**
<> 144:ef7eb2e8f9f7 848 * @}
<> 144:ef7eb2e8f9f7 849 */
<> 144:ef7eb2e8f9f7 850 #endif /* HAL_SDRAM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 851 /**
<> 144:ef7eb2e8f9f7 852 * @}
<> 144:ef7eb2e8f9f7 853 */
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 /**
<> 144:ef7eb2e8f9f7 856 * @}
<> 144:ef7eb2e8f9f7 857 */
<> 144:ef7eb2e8f9f7 858
<> 144:ef7eb2e8f9f7 859 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/