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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_sdmmc.h@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:39:01 2017 +0100
Revision:
165:e614a9f1c9e2
Parent:
154:37f96f9d4de2 
This updates the lib to the mbed lib v 143

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_ll_sdmmc.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 165:e614a9f1c9e2 5 * @version V1.1.0
AnnaBridge 165:e614a9f1c9e2 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Header file of low layer SDMMC HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 165:e614a9f1c9e2 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __stm32f1xx_LL_SD_H
<> 144:ef7eb2e8f9f7 40 #define __stm32f1xx_LL_SD_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #if defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 45 extern "C" {
<> 144:ef7eb2e8f9f7 46 #endif
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 49 #include "stm32f1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @addtogroup SDMMC_LL
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
<> 144:ef7eb2e8f9f7 61 * @{
<> 144:ef7eb2e8f9f7 62 */
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /**
<> 144:ef7eb2e8f9f7 65 * @brief SDMMC Configuration Structure definition
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67 typedef struct
<> 144:ef7eb2e8f9f7 68 {
<> 144:ef7eb2e8f9f7 69 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
<> 144:ef7eb2e8f9f7 70 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
<> 144:ef7eb2e8f9f7 73 enabled or disabled.
<> 144:ef7eb2e8f9f7 74 This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
<> 144:ef7eb2e8f9f7 77 disabled when the bus is idle.
<> 144:ef7eb2e8f9f7 78 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 uint32_t BusWide; /*!< Specifies the SDIO bus width.
<> 144:ef7eb2e8f9f7 81 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
<> 144:ef7eb2e8f9f7 84 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
<> 144:ef7eb2e8f9f7 87 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 }SDIO_InitTypeDef;
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /**
<> 144:ef7eb2e8f9f7 93 * @brief SDIO Command Control structure
<> 144:ef7eb2e8f9f7 94 */
<> 144:ef7eb2e8f9f7 95 typedef struct
<> 144:ef7eb2e8f9f7 96 {
<> 144:ef7eb2e8f9f7 97 uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
<> 144:ef7eb2e8f9f7 98 to a card as part of a command message. If a command
<> 144:ef7eb2e8f9f7 99 contains an argument, it must be loaded into this register
<> 144:ef7eb2e8f9f7 100 before writing the command to the command register. */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
<> 144:ef7eb2e8f9f7 103 Max_Data = 64 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 uint32_t Response; /*!< Specifies the SDIO response type.
<> 144:ef7eb2e8f9f7 106 This parameter can be a value of @ref SDMMC_LL_Response_Type */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
<> 144:ef7eb2e8f9f7 109 enabled or disabled.
<> 144:ef7eb2e8f9f7 110 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
<> 144:ef7eb2e8f9f7 113 is enabled or disabled.
<> 144:ef7eb2e8f9f7 114 This parameter can be a value of @ref SDMMC_LL_CPSM_State */
<> 144:ef7eb2e8f9f7 115 }SDIO_CmdInitTypeDef;
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /**
<> 144:ef7eb2e8f9f7 119 * @brief SDIO Data Control structure
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121 typedef struct
<> 144:ef7eb2e8f9f7 122 {
<> 144:ef7eb2e8f9f7 123 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
<> 144:ef7eb2e8f9f7 128 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
<> 144:ef7eb2e8f9f7 131 is a read or write.
<> 144:ef7eb2e8f9f7 132 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
<> 144:ef7eb2e8f9f7 135 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
<> 144:ef7eb2e8f9f7 138 is enabled or disabled.
<> 144:ef7eb2e8f9f7 139 This parameter can be a value of @ref SDMMC_LL_DPSM_State */
<> 144:ef7eb2e8f9f7 140 }SDIO_DataInitTypeDef;
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /**
<> 144:ef7eb2e8f9f7 143 * @}
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 147 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
<> 144:ef7eb2e8f9f7 148 * @{
<> 144:ef7eb2e8f9f7 149 */
AnnaBridge 165:e614a9f1c9e2 150 #define SDMMC_ERROR_NONE 0x00000000U /*!< No error */
AnnaBridge 165:e614a9f1c9e2 151 #define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */
AnnaBridge 165:e614a9f1c9e2 152 #define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */
AnnaBridge 165:e614a9f1c9e2 153 #define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */
AnnaBridge 165:e614a9f1c9e2 154 #define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */
AnnaBridge 165:e614a9f1c9e2 155 #define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */
AnnaBridge 165:e614a9f1c9e2 156 #define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */
AnnaBridge 165:e614a9f1c9e2 157 #define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */
AnnaBridge 165:e614a9f1c9e2 158 #define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the
AnnaBridge 165:e614a9f1c9e2 159 number of transferred bytes does not match the block length */
AnnaBridge 165:e614a9f1c9e2 160 #define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */
AnnaBridge 165:e614a9f1c9e2 161 #define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */
AnnaBridge 165:e614a9f1c9e2 162 #define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */
AnnaBridge 165:e614a9f1c9e2 163 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock
AnnaBridge 165:e614a9f1c9e2 164 command or if there was an attempt to access a locked card */
AnnaBridge 165:e614a9f1c9e2 165 #define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */
AnnaBridge 165:e614a9f1c9e2 166 #define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */
AnnaBridge 165:e614a9f1c9e2 167 #define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */
AnnaBridge 165:e614a9f1c9e2 168 #define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */
AnnaBridge 165:e614a9f1c9e2 169 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */
AnnaBridge 165:e614a9f1c9e2 170 #define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */
AnnaBridge 165:e614a9f1c9e2 171 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */
AnnaBridge 165:e614a9f1c9e2 172 #define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */
AnnaBridge 165:e614a9f1c9e2 173 #define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */
AnnaBridge 165:e614a9f1c9e2 174 #define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */
AnnaBridge 165:e614a9f1c9e2 175 #define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out
AnnaBridge 165:e614a9f1c9e2 176 of erase sequence command was received */
AnnaBridge 165:e614a9f1c9e2 177 #define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */
AnnaBridge 165:e614a9f1c9e2 178 #define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */
AnnaBridge 165:e614a9f1c9e2 179 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */
AnnaBridge 165:e614a9f1c9e2 180 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */
AnnaBridge 165:e614a9f1c9e2 181 #define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */
AnnaBridge 165:e614a9f1c9e2 182 #define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */
AnnaBridge 165:e614a9f1c9e2 183 #define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */
AnnaBridge 165:e614a9f1c9e2 184 #define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */
AnnaBridge 165:e614a9f1c9e2 185 #define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */
<> 144:ef7eb2e8f9f7 186
AnnaBridge 165:e614a9f1c9e2 187 /**
AnnaBridge 165:e614a9f1c9e2 188 * @brief SDMMC Commands Index
AnnaBridge 165:e614a9f1c9e2 189 */
AnnaBridge 165:e614a9f1c9e2 190 #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */
AnnaBridge 165:e614a9f1c9e2 191 #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */
AnnaBridge 165:e614a9f1c9e2 192 #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
AnnaBridge 165:e614a9f1c9e2 193 #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */
AnnaBridge 165:e614a9f1c9e2 194 #define SDMMC_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */
AnnaBridge 165:e614a9f1c9e2 195 #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
AnnaBridge 165:e614a9f1c9e2 196 operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge 165:e614a9f1c9e2 197 #define SDMMC_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
AnnaBridge 165:e614a9f1c9e2 198 #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */
AnnaBridge 165:e614a9f1c9e2 199 #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
AnnaBridge 165:e614a9f1c9e2 200 and asks the card whether card supports voltage. */
AnnaBridge 165:e614a9f1c9e2 201 #define SDMMC_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
AnnaBridge 165:e614a9f1c9e2 202 #define SDMMC_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */
AnnaBridge 165:e614a9f1c9e2 203 #define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */
AnnaBridge 165:e614a9f1c9e2 204 #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */
AnnaBridge 165:e614a9f1c9e2 205 #define SDMMC_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */
AnnaBridge 165:e614a9f1c9e2 206 #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14) /*!< Reserved */
AnnaBridge 165:e614a9f1c9e2 207 #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */
AnnaBridge 165:e614a9f1c9e2 208 #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands
AnnaBridge 165:e614a9f1c9e2 209 (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
AnnaBridge 165:e614a9f1c9e2 210 for SDHS and SDXC. */
AnnaBridge 165:e614a9f1c9e2 211 #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge 165:e614a9f1c9e2 212 fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge 165:e614a9f1c9e2 213 #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by
AnnaBridge 165:e614a9f1c9e2 214 STOP_TRANSMISSION command. */
AnnaBridge 165:e614a9f1c9e2 215 #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
AnnaBridge 165:e614a9f1c9e2 216 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */
AnnaBridge 165:e614a9f1c9e2 217 #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */
AnnaBridge 165:e614a9f1c9e2 218 #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge 165:e614a9f1c9e2 219 fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge 165:e614a9f1c9e2 220 #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
AnnaBridge 165:e614a9f1c9e2 221 #define SDMMC_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */
AnnaBridge 165:e614a9f1c9e2 222 #define SDMMC_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */
AnnaBridge 165:e614a9f1c9e2 223 #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */
AnnaBridge 165:e614a9f1c9e2 224 #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */
AnnaBridge 165:e614a9f1c9e2 225 #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */
AnnaBridge 165:e614a9f1c9e2 226 #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */
AnnaBridge 165:e614a9f1c9e2 227 #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */
AnnaBridge 165:e614a9f1c9e2 228 #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command
AnnaBridge 165:e614a9f1c9e2 229 system set by switch function command (CMD6). */
AnnaBridge 165:e614a9f1c9e2 230 #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased.
AnnaBridge 165:e614a9f1c9e2 231 Reserved for each command system set by switch function command (CMD6). */
AnnaBridge 165:e614a9f1c9e2 232 #define SDMMC_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */
AnnaBridge 165:e614a9f1c9e2 233 #define SDMMC_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */
AnnaBridge 165:e614a9f1c9e2 234 #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */
AnnaBridge 165:e614a9f1c9e2 235 #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
AnnaBridge 165:e614a9f1c9e2 236 the SET_BLOCK_LEN command. */
AnnaBridge 165:e614a9f1c9e2 237 #define SDMMC_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather
AnnaBridge 165:e614a9f1c9e2 238 than a standard command. */
AnnaBridge 165:e614a9f1c9e2 239 #define SDMMC_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card
AnnaBridge 165:e614a9f1c9e2 240 for general purpose/application specific commands. */
AnnaBridge 165:e614a9f1c9e2 241 #define SDMMC_CMD_NO_CMD ((uint8_t)64) /*!< No command */
AnnaBridge 165:e614a9f1c9e2 242
AnnaBridge 165:e614a9f1c9e2 243 /**
AnnaBridge 165:e614a9f1c9e2 244 * @brief Following commands are SD Card Specific commands.
AnnaBridge 165:e614a9f1c9e2 245 * SDMMC_APP_CMD should be sent before sending these commands.
AnnaBridge 165:e614a9f1c9e2 246 */
AnnaBridge 165:e614a9f1c9e2 247 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
AnnaBridge 165:e614a9f1c9e2 248 widths are given in SCR register. */
AnnaBridge 165:e614a9f1c9e2 249 #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */
AnnaBridge 165:e614a9f1c9e2 250 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
AnnaBridge 165:e614a9f1c9e2 251 32bit+CRC data block. */
AnnaBridge 165:e614a9f1c9e2 252 #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
AnnaBridge 165:e614a9f1c9e2 253 send its operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge 165:e614a9f1c9e2 254 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
AnnaBridge 165:e614a9f1c9e2 255 #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */
AnnaBridge 165:e614a9f1c9e2 256 #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */
AnnaBridge 165:e614a9f1c9e2 257 #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */
AnnaBridge 165:e614a9f1c9e2 258
AnnaBridge 165:e614a9f1c9e2 259 /**
AnnaBridge 165:e614a9f1c9e2 260 * @brief Following commands are SD Card Specific security commands.
AnnaBridge 165:e614a9f1c9e2 261 * SDMMC_CMD_APP_CMD should be sent before sending these commands.
AnnaBridge 165:e614a9f1c9e2 262 */
AnnaBridge 165:e614a9f1c9e2 263 #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43)
AnnaBridge 165:e614a9f1c9e2 264 #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44)
AnnaBridge 165:e614a9f1c9e2 265 #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45)
AnnaBridge 165:e614a9f1c9e2 266 #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46)
AnnaBridge 165:e614a9f1c9e2 267 #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47)
AnnaBridge 165:e614a9f1c9e2 268 #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48)
AnnaBridge 165:e614a9f1c9e2 269 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18)
AnnaBridge 165:e614a9f1c9e2 270 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25)
AnnaBridge 165:e614a9f1c9e2 271 #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38)
AnnaBridge 165:e614a9f1c9e2 272 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49)
AnnaBridge 165:e614a9f1c9e2 273 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48)
AnnaBridge 165:e614a9f1c9e2 274
AnnaBridge 165:e614a9f1c9e2 275 /**
AnnaBridge 165:e614a9f1c9e2 276 * @brief Masks for errors Card Status R1 (OCR Register)
AnnaBridge 165:e614a9f1c9e2 277 */
AnnaBridge 165:e614a9f1c9e2 278 #define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U
AnnaBridge 165:e614a9f1c9e2 279 #define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U
AnnaBridge 165:e614a9f1c9e2 280 #define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U
AnnaBridge 165:e614a9f1c9e2 281 #define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U
AnnaBridge 165:e614a9f1c9e2 282 #define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U
AnnaBridge 165:e614a9f1c9e2 283 #define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U
AnnaBridge 165:e614a9f1c9e2 284 #define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U
AnnaBridge 165:e614a9f1c9e2 285 #define SDMMC_OCR_COM_CRC_FAILED 0x00800000U
AnnaBridge 165:e614a9f1c9e2 286 #define SDMMC_OCR_ILLEGAL_CMD 0x00400000U
AnnaBridge 165:e614a9f1c9e2 287 #define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U
AnnaBridge 165:e614a9f1c9e2 288 #define SDMMC_OCR_CC_ERROR 0x00100000U
AnnaBridge 165:e614a9f1c9e2 289 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U
AnnaBridge 165:e614a9f1c9e2 290 #define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U
AnnaBridge 165:e614a9f1c9e2 291 #define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U
AnnaBridge 165:e614a9f1c9e2 292 #define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U
AnnaBridge 165:e614a9f1c9e2 293 #define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U
AnnaBridge 165:e614a9f1c9e2 294 #define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U
AnnaBridge 165:e614a9f1c9e2 295 #define SDMMC_OCR_ERASE_RESET 0x00002000U
AnnaBridge 165:e614a9f1c9e2 296 #define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U
AnnaBridge 165:e614a9f1c9e2 297 #define SDMMC_OCR_ERRORBITS 0xFDFFE008U
AnnaBridge 165:e614a9f1c9e2 298
AnnaBridge 165:e614a9f1c9e2 299 /**
AnnaBridge 165:e614a9f1c9e2 300 * @brief Masks for R6 Response
AnnaBridge 165:e614a9f1c9e2 301 */
AnnaBridge 165:e614a9f1c9e2 302 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U
AnnaBridge 165:e614a9f1c9e2 303 #define SDMMC_R6_ILLEGAL_CMD 0x00004000U
AnnaBridge 165:e614a9f1c9e2 304 #define SDMMC_R6_COM_CRC_FAILED 0x00008000U
AnnaBridge 165:e614a9f1c9e2 305
AnnaBridge 165:e614a9f1c9e2 306 #define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
AnnaBridge 165:e614a9f1c9e2 307 #define SDMMC_HIGH_CAPACITY 0x40000000U
AnnaBridge 165:e614a9f1c9e2 308 #define SDMMC_STD_CAPACITY 0x00000000U
AnnaBridge 165:e614a9f1c9e2 309 #define SDMMC_CHECK_PATTERN 0x000001AAU
AnnaBridge 165:e614a9f1c9e2 310
AnnaBridge 165:e614a9f1c9e2 311 #define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU
AnnaBridge 165:e614a9f1c9e2 312
AnnaBridge 165:e614a9f1c9e2 313 #define SDMMC_MAX_TRIAL 0x0000FFFFU
AnnaBridge 165:e614a9f1c9e2 314
AnnaBridge 165:e614a9f1c9e2 315 #define SDMMC_ALLZERO 0x00000000U
AnnaBridge 165:e614a9f1c9e2 316
AnnaBridge 165:e614a9f1c9e2 317 #define SDMMC_WIDE_BUS_SUPPORT 0x00040000U
AnnaBridge 165:e614a9f1c9e2 318 #define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
AnnaBridge 165:e614a9f1c9e2 319 #define SDMMC_CARD_LOCKED 0x02000000U
AnnaBridge 165:e614a9f1c9e2 320
AnnaBridge 165:e614a9f1c9e2 321 #define SDMMC_DATATIMEOUT 0xFFFFFFFFU
AnnaBridge 165:e614a9f1c9e2 322
AnnaBridge 165:e614a9f1c9e2 323 #define SDMMC_0TO7BITS 0x000000FFU
AnnaBridge 165:e614a9f1c9e2 324 #define SDMMC_8TO15BITS 0x0000FF00U
AnnaBridge 165:e614a9f1c9e2 325 #define SDMMC_16TO23BITS 0x00FF0000U
AnnaBridge 165:e614a9f1c9e2 326 #define SDMMC_24TO31BITS 0xFF000000U
AnnaBridge 165:e614a9f1c9e2 327 #define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU
AnnaBridge 165:e614a9f1c9e2 328
AnnaBridge 165:e614a9f1c9e2 329 #define SDMMC_HALFFIFO 0x00000008U
AnnaBridge 165:e614a9f1c9e2 330 #define SDMMC_HALFFIFOBYTES 0x00000020U
AnnaBridge 165:e614a9f1c9e2 331
AnnaBridge 165:e614a9f1c9e2 332 /**
AnnaBridge 165:e614a9f1c9e2 333 * @brief Command Class supported
AnnaBridge 165:e614a9f1c9e2 334 */
AnnaBridge 165:e614a9f1c9e2 335 #define SDIO_CCCC_ERASE 0x00000020U
AnnaBridge 165:e614a9f1c9e2 336
AnnaBridge 165:e614a9f1c9e2 337 #define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */
AnnaBridge 165:e614a9f1c9e2 338 #define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */
AnnaBridge 165:e614a9f1c9e2 339
AnnaBridge 165:e614a9f1c9e2 340
AnnaBridge 165:e614a9f1c9e2 341 /** @defgroup SDIO_LL_Clock_Edge Clock Edge
<> 144:ef7eb2e8f9f7 342 * @{
<> 144:ef7eb2e8f9f7 343 */
AnnaBridge 165:e614a9f1c9e2 344 #define SDIO_CLOCK_EDGE_RISING 0x00000000U
<> 144:ef7eb2e8f9f7 345 #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
<> 144:ef7eb2e8f9f7 348 ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
<> 144:ef7eb2e8f9f7 349 /**
<> 144:ef7eb2e8f9f7 350 * @}
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352
AnnaBridge 165:e614a9f1c9e2 353 /** @defgroup SDIO_LL_Clock_Bypass Clock Bypass
<> 144:ef7eb2e8f9f7 354 * @{
<> 144:ef7eb2e8f9f7 355 */
AnnaBridge 165:e614a9f1c9e2 356 #define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 357 #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
<> 144:ef7eb2e8f9f7 360 ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
<> 144:ef7eb2e8f9f7 361 /**
<> 144:ef7eb2e8f9f7 362 * @}
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364
AnnaBridge 165:e614a9f1c9e2 365 /** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving
<> 144:ef7eb2e8f9f7 366 * @{
<> 144:ef7eb2e8f9f7 367 */
AnnaBridge 165:e614a9f1c9e2 368 #define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 369 #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
<> 144:ef7eb2e8f9f7 372 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
<> 144:ef7eb2e8f9f7 373 /**
<> 144:ef7eb2e8f9f7 374 * @}
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376
AnnaBridge 165:e614a9f1c9e2 377 /** @defgroup SDIO_LL_Bus_Wide Bus Width
<> 144:ef7eb2e8f9f7 378 * @{
<> 144:ef7eb2e8f9f7 379 */
AnnaBridge 165:e614a9f1c9e2 380 #define SDIO_BUS_WIDE_1B 0x00000000U
<> 144:ef7eb2e8f9f7 381 #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
<> 144:ef7eb2e8f9f7 382 #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
<> 144:ef7eb2e8f9f7 385 ((WIDE) == SDIO_BUS_WIDE_4B) || \
<> 144:ef7eb2e8f9f7 386 ((WIDE) == SDIO_BUS_WIDE_8B))
<> 144:ef7eb2e8f9f7 387 /**
<> 144:ef7eb2e8f9f7 388 * @}
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390
AnnaBridge 165:e614a9f1c9e2 391 /** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control
<> 144:ef7eb2e8f9f7 392 * @{
<> 144:ef7eb2e8f9f7 393 */
AnnaBridge 165:e614a9f1c9e2 394 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 395 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
<> 144:ef7eb2e8f9f7 398 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
<> 144:ef7eb2e8f9f7 399 /**
<> 144:ef7eb2e8f9f7 400 * @}
<> 144:ef7eb2e8f9f7 401 */
<> 144:ef7eb2e8f9f7 402
AnnaBridge 165:e614a9f1c9e2 403 /** @defgroup SDIO_LL_Clock_Division Clock Division
<> 144:ef7eb2e8f9f7 404 * @{
<> 144:ef7eb2e8f9f7 405 */
AnnaBridge 165:e614a9f1c9e2 406 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU)
<> 144:ef7eb2e8f9f7 407 /**
<> 144:ef7eb2e8f9f7 408 * @}
<> 144:ef7eb2e8f9f7 409 */
<> 144:ef7eb2e8f9f7 410
AnnaBridge 165:e614a9f1c9e2 411 /** @defgroup SDIO_LL_Command_Index Command Index
<> 144:ef7eb2e8f9f7 412 * @{
<> 144:ef7eb2e8f9f7 413 */
AnnaBridge 165:e614a9f1c9e2 414 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
<> 144:ef7eb2e8f9f7 415 /**
<> 144:ef7eb2e8f9f7 416 * @}
<> 144:ef7eb2e8f9f7 417 */
<> 144:ef7eb2e8f9f7 418
AnnaBridge 165:e614a9f1c9e2 419 /** @defgroup SDIO_LL_Response_Type Response Type
<> 144:ef7eb2e8f9f7 420 * @{
<> 144:ef7eb2e8f9f7 421 */
AnnaBridge 165:e614a9f1c9e2 422 #define SDIO_RESPONSE_NO 0x00000000U
<> 144:ef7eb2e8f9f7 423 #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
<> 144:ef7eb2e8f9f7 424 #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
<> 144:ef7eb2e8f9f7 427 ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
<> 144:ef7eb2e8f9f7 428 ((RESPONSE) == SDIO_RESPONSE_LONG))
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @}
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432
AnnaBridge 165:e614a9f1c9e2 433 /** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt
<> 144:ef7eb2e8f9f7 434 * @{
<> 144:ef7eb2e8f9f7 435 */
AnnaBridge 165:e614a9f1c9e2 436 #define SDIO_WAIT_NO 0x00000000U
<> 144:ef7eb2e8f9f7 437 #define SDIO_WAIT_IT SDIO_CMD_WAITINT
<> 144:ef7eb2e8f9f7 438 #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
<> 144:ef7eb2e8f9f7 441 ((WAIT) == SDIO_WAIT_IT) || \
<> 144:ef7eb2e8f9f7 442 ((WAIT) == SDIO_WAIT_PEND))
<> 144:ef7eb2e8f9f7 443 /**
<> 144:ef7eb2e8f9f7 444 * @}
<> 144:ef7eb2e8f9f7 445 */
<> 144:ef7eb2e8f9f7 446
AnnaBridge 165:e614a9f1c9e2 447 /** @defgroup SDIO_LL_CPSM_State CPSM State
<> 144:ef7eb2e8f9f7 448 * @{
<> 144:ef7eb2e8f9f7 449 */
AnnaBridge 165:e614a9f1c9e2 450 #define SDIO_CPSM_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 451 #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
<> 144:ef7eb2e8f9f7 454 ((CPSM) == SDIO_CPSM_ENABLE))
<> 144:ef7eb2e8f9f7 455 /**
<> 144:ef7eb2e8f9f7 456 * @}
<> 144:ef7eb2e8f9f7 457 */
<> 144:ef7eb2e8f9f7 458
AnnaBridge 165:e614a9f1c9e2 459 /** @defgroup SDIO_LL_Response_Registers Response Register
<> 144:ef7eb2e8f9f7 460 * @{
<> 144:ef7eb2e8f9f7 461 */
AnnaBridge 165:e614a9f1c9e2 462 #define SDIO_RESP1 0x00000000U
AnnaBridge 165:e614a9f1c9e2 463 #define SDIO_RESP2 0x00000004U
AnnaBridge 165:e614a9f1c9e2 464 #define SDIO_RESP3 0x00000008U
AnnaBridge 165:e614a9f1c9e2 465 #define SDIO_RESP4 0x0000000CU
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
<> 144:ef7eb2e8f9f7 468 ((RESP) == SDIO_RESP2) || \
<> 144:ef7eb2e8f9f7 469 ((RESP) == SDIO_RESP3) || \
<> 144:ef7eb2e8f9f7 470 ((RESP) == SDIO_RESP4))
<> 144:ef7eb2e8f9f7 471 /**
<> 144:ef7eb2e8f9f7 472 * @}
<> 144:ef7eb2e8f9f7 473 */
<> 144:ef7eb2e8f9f7 474
AnnaBridge 165:e614a9f1c9e2 475 /** @defgroup SDIO_LL_Data_Length Data Lenght
<> 144:ef7eb2e8f9f7 476 * @{
<> 144:ef7eb2e8f9f7 477 */
AnnaBridge 165:e614a9f1c9e2 478 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
<> 144:ef7eb2e8f9f7 479 /**
<> 144:ef7eb2e8f9f7 480 * @}
<> 144:ef7eb2e8f9f7 481 */
<> 144:ef7eb2e8f9f7 482
AnnaBridge 165:e614a9f1c9e2 483 /** @defgroup SDIO_LL_Data_Block_Size Data Block Size
<> 144:ef7eb2e8f9f7 484 * @{
<> 144:ef7eb2e8f9f7 485 */
AnnaBridge 165:e614a9f1c9e2 486 #define SDIO_DATABLOCK_SIZE_1B 0x00000000U
<> 144:ef7eb2e8f9f7 487 #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
<> 144:ef7eb2e8f9f7 488 #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
<> 144:ef7eb2e8f9f7 489 #define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1)
<> 144:ef7eb2e8f9f7 490 #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
<> 144:ef7eb2e8f9f7 491 #define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2)
<> 144:ef7eb2e8f9f7 492 #define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
<> 144:ef7eb2e8f9f7 493 #define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
<> 144:ef7eb2e8f9f7 494 #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
<> 144:ef7eb2e8f9f7 495 #define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3)
<> 144:ef7eb2e8f9f7 496 #define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
<> 144:ef7eb2e8f9f7 497 #define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
<> 144:ef7eb2e8f9f7 498 #define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
<> 144:ef7eb2e8f9f7 499 #define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
<> 144:ef7eb2e8f9f7 500 #define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
<> 144:ef7eb2e8f9f7 503 ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
<> 144:ef7eb2e8f9f7 504 ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
<> 144:ef7eb2e8f9f7 505 ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
<> 144:ef7eb2e8f9f7 506 ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
<> 144:ef7eb2e8f9f7 507 ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
<> 144:ef7eb2e8f9f7 508 ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
<> 144:ef7eb2e8f9f7 509 ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
<> 144:ef7eb2e8f9f7 510 ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
<> 144:ef7eb2e8f9f7 511 ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
<> 144:ef7eb2e8f9f7 512 ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
<> 144:ef7eb2e8f9f7 513 ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
<> 144:ef7eb2e8f9f7 514 ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
<> 144:ef7eb2e8f9f7 515 ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
<> 144:ef7eb2e8f9f7 516 ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
<> 144:ef7eb2e8f9f7 517 /**
<> 144:ef7eb2e8f9f7 518 * @}
<> 144:ef7eb2e8f9f7 519 */
<> 144:ef7eb2e8f9f7 520
AnnaBridge 165:e614a9f1c9e2 521 /** @defgroup SDIO_LL_Transfer_Direction Transfer Direction
<> 144:ef7eb2e8f9f7 522 * @{
<> 144:ef7eb2e8f9f7 523 */
AnnaBridge 165:e614a9f1c9e2 524 #define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U
<> 144:ef7eb2e8f9f7 525 #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
<> 144:ef7eb2e8f9f7 528 ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
<> 144:ef7eb2e8f9f7 529 /**
<> 144:ef7eb2e8f9f7 530 * @}
<> 144:ef7eb2e8f9f7 531 */
<> 144:ef7eb2e8f9f7 532
AnnaBridge 165:e614a9f1c9e2 533 /** @defgroup SDIO_LL_Transfer_Type Transfer Type
<> 144:ef7eb2e8f9f7 534 * @{
<> 144:ef7eb2e8f9f7 535 */
AnnaBridge 165:e614a9f1c9e2 536 #define SDIO_TRANSFER_MODE_BLOCK 0x00000000U
<> 144:ef7eb2e8f9f7 537 #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
<> 144:ef7eb2e8f9f7 540 ((MODE) == SDIO_TRANSFER_MODE_STREAM))
<> 144:ef7eb2e8f9f7 541 /**
<> 144:ef7eb2e8f9f7 542 * @}
<> 144:ef7eb2e8f9f7 543 */
<> 144:ef7eb2e8f9f7 544
AnnaBridge 165:e614a9f1c9e2 545 /** @defgroup SDIO_LL_DPSM_State DPSM State
<> 144:ef7eb2e8f9f7 546 * @{
<> 144:ef7eb2e8f9f7 547 */
AnnaBridge 165:e614a9f1c9e2 548 #define SDIO_DPSM_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 549 #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
<> 144:ef7eb2e8f9f7 552 ((DPSM) == SDIO_DPSM_ENABLE))
<> 144:ef7eb2e8f9f7 553 /**
<> 144:ef7eb2e8f9f7 554 * @}
<> 144:ef7eb2e8f9f7 555 */
<> 144:ef7eb2e8f9f7 556
AnnaBridge 165:e614a9f1c9e2 557 /** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode
<> 144:ef7eb2e8f9f7 558 * @{
<> 144:ef7eb2e8f9f7 559 */
AnnaBridge 165:e614a9f1c9e2 560 #define SDIO_READ_WAIT_MODE_DATA2 0x00000000U
<> 144:ef7eb2e8f9f7 561 #define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD)
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
<> 144:ef7eb2e8f9f7 564 ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
<> 144:ef7eb2e8f9f7 565 /**
<> 144:ef7eb2e8f9f7 566 * @}
<> 144:ef7eb2e8f9f7 567 */
<> 144:ef7eb2e8f9f7 568
AnnaBridge 165:e614a9f1c9e2 569 /** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
<> 144:ef7eb2e8f9f7 570 * @{
<> 144:ef7eb2e8f9f7 571 */
<> 144:ef7eb2e8f9f7 572 #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
<> 144:ef7eb2e8f9f7 573 #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
<> 144:ef7eb2e8f9f7 574 #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
<> 144:ef7eb2e8f9f7 575 #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
<> 144:ef7eb2e8f9f7 576 #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
<> 144:ef7eb2e8f9f7 577 #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
<> 144:ef7eb2e8f9f7 578 #define SDIO_IT_CMDREND SDIO_STA_CMDREND
<> 144:ef7eb2e8f9f7 579 #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
<> 144:ef7eb2e8f9f7 580 #define SDIO_IT_DATAEND SDIO_STA_DATAEND
<> 144:ef7eb2e8f9f7 581 #define SDIO_IT_STBITERR SDIO_STA_STBITERR
<> 144:ef7eb2e8f9f7 582 #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
<> 144:ef7eb2e8f9f7 583 #define SDIO_IT_CMDACT SDIO_STA_CMDACT
<> 144:ef7eb2e8f9f7 584 #define SDIO_IT_TXACT SDIO_STA_TXACT
<> 144:ef7eb2e8f9f7 585 #define SDIO_IT_RXACT SDIO_STA_RXACT
<> 144:ef7eb2e8f9f7 586 #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
<> 144:ef7eb2e8f9f7 587 #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
<> 144:ef7eb2e8f9f7 588 #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
<> 144:ef7eb2e8f9f7 589 #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
<> 144:ef7eb2e8f9f7 590 #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
<> 144:ef7eb2e8f9f7 591 #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
<> 144:ef7eb2e8f9f7 592 #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
<> 144:ef7eb2e8f9f7 593 #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
<> 144:ef7eb2e8f9f7 594 #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
<> 144:ef7eb2e8f9f7 595 #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
<> 144:ef7eb2e8f9f7 596 /**
<> 144:ef7eb2e8f9f7 597 * @}
<> 144:ef7eb2e8f9f7 598 */
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 /** @defgroup SDMMC_LL_Flags Flags
<> 144:ef7eb2e8f9f7 601 * @{
<> 144:ef7eb2e8f9f7 602 */
<> 144:ef7eb2e8f9f7 603 #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
<> 144:ef7eb2e8f9f7 604 #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
<> 144:ef7eb2e8f9f7 605 #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
<> 144:ef7eb2e8f9f7 606 #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
<> 144:ef7eb2e8f9f7 607 #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
<> 144:ef7eb2e8f9f7 608 #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
<> 144:ef7eb2e8f9f7 609 #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
<> 144:ef7eb2e8f9f7 610 #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
<> 144:ef7eb2e8f9f7 611 #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
<> 144:ef7eb2e8f9f7 612 #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
<> 144:ef7eb2e8f9f7 613 #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
<> 144:ef7eb2e8f9f7 614 #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
<> 144:ef7eb2e8f9f7 615 #define SDIO_FLAG_TXACT SDIO_STA_TXACT
<> 144:ef7eb2e8f9f7 616 #define SDIO_FLAG_RXACT SDIO_STA_RXACT
<> 144:ef7eb2e8f9f7 617 #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
<> 144:ef7eb2e8f9f7 618 #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
<> 144:ef7eb2e8f9f7 619 #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
<> 144:ef7eb2e8f9f7 620 #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
<> 144:ef7eb2e8f9f7 621 #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
<> 144:ef7eb2e8f9f7 622 #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
<> 144:ef7eb2e8f9f7 623 #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
<> 144:ef7eb2e8f9f7 624 #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
<> 144:ef7eb2e8f9f7 625 #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
<> 144:ef7eb2e8f9f7 626 #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
AnnaBridge 165:e614a9f1c9e2 627 #define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
AnnaBridge 165:e614a9f1c9e2 628 SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\
AnnaBridge 165:e614a9f1c9e2 629 SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\
AnnaBridge 165:e614a9f1c9e2 630 SDIO_FLAG_DBCKEND))
<> 144:ef7eb2e8f9f7 631 /**
<> 144:ef7eb2e8f9f7 632 * @}
<> 144:ef7eb2e8f9f7 633 */
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /**
<> 144:ef7eb2e8f9f7 636 * @}
AnnaBridge 165:e614a9f1c9e2 637 */
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 640 /** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros
AnnaBridge 165:e614a9f1c9e2 641 * @{
AnnaBridge 165:e614a9f1c9e2 642 */
AnnaBridge 165:e614a9f1c9e2 643
AnnaBridge 165:e614a9f1c9e2 644 /** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
<> 144:ef7eb2e8f9f7 645 * @{
<> 144:ef7eb2e8f9f7 646 */
AnnaBridge 165:e614a9f1c9e2 647 /* ------------ SDIO registers bit address in the alias region -------------- */
AnnaBridge 165:e614a9f1c9e2 648 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
AnnaBridge 165:e614a9f1c9e2 649
AnnaBridge 165:e614a9f1c9e2 650 /* --- CLKCR Register ---*/
AnnaBridge 165:e614a9f1c9e2 651 /* Alias word address of CLKEN bit */
AnnaBridge 165:e614a9f1c9e2 652 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04U)
AnnaBridge 165:e614a9f1c9e2 653 #define CLKEN_BITNUMBER 0x08U
AnnaBridge 165:e614a9f1c9e2 654 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
AnnaBridge 165:e614a9f1c9e2 655
AnnaBridge 165:e614a9f1c9e2 656 /* --- CMD Register ---*/
AnnaBridge 165:e614a9f1c9e2 657 /* Alias word address of SDIOSUSPEND bit */
AnnaBridge 165:e614a9f1c9e2 658 #define CMD_OFFSET (SDIO_OFFSET + 0x0CU)
AnnaBridge 165:e614a9f1c9e2 659 #define SDIOSUSPEND_BITNUMBER 0x0BU
AnnaBridge 165:e614a9f1c9e2 660 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
AnnaBridge 165:e614a9f1c9e2 661
AnnaBridge 165:e614a9f1c9e2 662 /* Alias word address of ENCMDCOMPL bit */
AnnaBridge 165:e614a9f1c9e2 663 #define ENCMDCOMPL_BITNUMBER 0x0CU
AnnaBridge 165:e614a9f1c9e2 664 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
AnnaBridge 165:e614a9f1c9e2 665
AnnaBridge 165:e614a9f1c9e2 666 /* Alias word address of NIEN bit */
AnnaBridge 165:e614a9f1c9e2 667 #define NIEN_BITNUMBER 0x0DU
AnnaBridge 165:e614a9f1c9e2 668 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
AnnaBridge 165:e614a9f1c9e2 669
AnnaBridge 165:e614a9f1c9e2 670 /* Alias word address of ATACMD bit */
AnnaBridge 165:e614a9f1c9e2 671 #define ATACMD_BITNUMBER 0x0EU
AnnaBridge 165:e614a9f1c9e2 672 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
AnnaBridge 165:e614a9f1c9e2 673
AnnaBridge 165:e614a9f1c9e2 674 /* --- DCTRL Register ---*/
AnnaBridge 165:e614a9f1c9e2 675 /* Alias word address of DMAEN bit */
AnnaBridge 165:e614a9f1c9e2 676 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU)
AnnaBridge 165:e614a9f1c9e2 677 #define DMAEN_BITNUMBER 0x03U
AnnaBridge 165:e614a9f1c9e2 678 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
AnnaBridge 165:e614a9f1c9e2 679
AnnaBridge 165:e614a9f1c9e2 680 /* Alias word address of RWSTART bit */
AnnaBridge 165:e614a9f1c9e2 681 #define RWSTART_BITNUMBER 0x08U
AnnaBridge 165:e614a9f1c9e2 682 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
AnnaBridge 165:e614a9f1c9e2 683
AnnaBridge 165:e614a9f1c9e2 684 /* Alias word address of RWSTOP bit */
AnnaBridge 165:e614a9f1c9e2 685 #define RWSTOP_BITNUMBER 0x09U
AnnaBridge 165:e614a9f1c9e2 686 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
AnnaBridge 165:e614a9f1c9e2 687
AnnaBridge 165:e614a9f1c9e2 688 /* Alias word address of RWMOD bit */
AnnaBridge 165:e614a9f1c9e2 689 #define RWMOD_BITNUMBER 0x0AU
AnnaBridge 165:e614a9f1c9e2 690 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
AnnaBridge 165:e614a9f1c9e2 691
AnnaBridge 165:e614a9f1c9e2 692 /* Alias word address of SDIOEN bit */
AnnaBridge 165:e614a9f1c9e2 693 #define SDIOEN_BITNUMBER 0x0BU
AnnaBridge 165:e614a9f1c9e2 694 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
AnnaBridge 165:e614a9f1c9e2 695 /**
AnnaBridge 165:e614a9f1c9e2 696 * @}
AnnaBridge 165:e614a9f1c9e2 697 */
AnnaBridge 165:e614a9f1c9e2 698
AnnaBridge 165:e614a9f1c9e2 699 /** @defgroup SDIO_LL_Register Bits And Addresses Definitions
AnnaBridge 165:e614a9f1c9e2 700 * @brief SDIO_LL registers bit address in the alias region
<> 144:ef7eb2e8f9f7 701 * @{
<> 144:ef7eb2e8f9f7 702 */
<> 144:ef7eb2e8f9f7 703 /* ---------------------- SDIO registers bit mask --------------------------- */
<> 144:ef7eb2e8f9f7 704 /* --- CLKCR Register ---*/
<> 144:ef7eb2e8f9f7 705 /* CLKCR register clear mask */
<> 144:ef7eb2e8f9f7 706 #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\
<> 144:ef7eb2e8f9f7 707 SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\
<> 144:ef7eb2e8f9f7 708 SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 /* --- DCTRL Register ---*/
<> 144:ef7eb2e8f9f7 711 /* SDIO DCTRL Clear Mask */
<> 144:ef7eb2e8f9f7 712 #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\
<> 144:ef7eb2e8f9f7 713 SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE))
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 /* --- CMD Register ---*/
<> 144:ef7eb2e8f9f7 716 /* CMD Register clear mask */
<> 144:ef7eb2e8f9f7 717 #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
<> 144:ef7eb2e8f9f7 718 SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\
<> 144:ef7eb2e8f9f7 719 SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND))
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /* SDIO RESP Registers Address */
<> 144:ef7eb2e8f9f7 722 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 /* SDIO Intialization Frequency (400KHz max) */
<> 144:ef7eb2e8f9f7 725 #define SDIO_INIT_CLK_DIV ((uint8_t)0xC3)
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 /* SDIO Data Transfer Frequency */
<> 144:ef7eb2e8f9f7 728 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x9)
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 /**
<> 144:ef7eb2e8f9f7 731 * @}
<> 144:ef7eb2e8f9f7 732 */
AnnaBridge 165:e614a9f1c9e2 733
AnnaBridge 165:e614a9f1c9e2 734 /** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration
AnnaBridge 165:e614a9f1c9e2 735 * @brief macros to handle interrupts and specific clock configurations
AnnaBridge 165:e614a9f1c9e2 736 * @{
AnnaBridge 165:e614a9f1c9e2 737 */
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /**
<> 144:ef7eb2e8f9f7 740 * @brief Enable the SDIO device.
<> 144:ef7eb2e8f9f7 741 * @param __INSTANCE__: SDIO Instance
<> 144:ef7eb2e8f9f7 742 * @retval None
<> 144:ef7eb2e8f9f7 743 */
AnnaBridge 165:e614a9f1c9e2 744 #define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 /**
<> 144:ef7eb2e8f9f7 747 * @brief Disable the SDIO device.
<> 144:ef7eb2e8f9f7 748 * @param __INSTANCE__: SDIO Instance
<> 144:ef7eb2e8f9f7 749 * @retval None
<> 144:ef7eb2e8f9f7 750 */
AnnaBridge 165:e614a9f1c9e2 751 #define __SDIO_DISABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /**
<> 144:ef7eb2e8f9f7 754 * @brief Enable the SDIO DMA transfer.
AnnaBridge 165:e614a9f1c9e2 755 * @param __INSTANCE__: SDIO Instance
<> 144:ef7eb2e8f9f7 756 * @retval None
<> 144:ef7eb2e8f9f7 757 */
AnnaBridge 165:e614a9f1c9e2 758 #define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
<> 144:ef7eb2e8f9f7 759 /**
<> 144:ef7eb2e8f9f7 760 * @brief Disable the SDIO DMA transfer.
AnnaBridge 165:e614a9f1c9e2 761 * @param __INSTANCE__: SDIO Instance
<> 144:ef7eb2e8f9f7 762 * @retval None
<> 144:ef7eb2e8f9f7 763 */
AnnaBridge 165:e614a9f1c9e2 764 #define __SDIO_DMA_DISABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 /**
<> 144:ef7eb2e8f9f7 767 * @brief Enable the SDIO device interrupt.
<> 144:ef7eb2e8f9f7 768 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 769 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
<> 144:ef7eb2e8f9f7 770 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 771 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 772 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 773 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 774 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 775 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 776 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 777 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 778 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<> 144:ef7eb2e8f9f7 779 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 780 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 781 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
<> 144:ef7eb2e8f9f7 782 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
<> 144:ef7eb2e8f9f7 783 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
<> 144:ef7eb2e8f9f7 784 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<> 144:ef7eb2e8f9f7 785 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<> 144:ef7eb2e8f9f7 786 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
<> 144:ef7eb2e8f9f7 787 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
<> 144:ef7eb2e8f9f7 788 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
<> 144:ef7eb2e8f9f7 789 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
<> 144:ef7eb2e8f9f7 790 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
<> 144:ef7eb2e8f9f7 791 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge 165:e614a9f1c9e2 792 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 793 * @retval None
<> 144:ef7eb2e8f9f7 794 */
<> 144:ef7eb2e8f9f7 795 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 /**
<> 144:ef7eb2e8f9f7 798 * @brief Disable the SDIO device interrupt.
<> 144:ef7eb2e8f9f7 799 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 800 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
<> 144:ef7eb2e8f9f7 801 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 802 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 803 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 804 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 805 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 806 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 807 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 808 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 809 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<> 144:ef7eb2e8f9f7 810 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 811 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 812 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
<> 144:ef7eb2e8f9f7 813 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
<> 144:ef7eb2e8f9f7 814 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
<> 144:ef7eb2e8f9f7 815 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<> 144:ef7eb2e8f9f7 816 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<> 144:ef7eb2e8f9f7 817 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
<> 144:ef7eb2e8f9f7 818 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
<> 144:ef7eb2e8f9f7 819 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
<> 144:ef7eb2e8f9f7 820 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
<> 144:ef7eb2e8f9f7 821 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
<> 144:ef7eb2e8f9f7 822 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge 165:e614a9f1c9e2 823 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 824 * @retval None
<> 144:ef7eb2e8f9f7 825 */
<> 144:ef7eb2e8f9f7 826 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 /**
<> 144:ef7eb2e8f9f7 829 * @brief Checks whether the specified SDIO flag is set or not.
<> 144:ef7eb2e8f9f7 830 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 831 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 832 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 833 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
<> 144:ef7eb2e8f9f7 834 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
<> 144:ef7eb2e8f9f7 835 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
<> 144:ef7eb2e8f9f7 836 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
<> 144:ef7eb2e8f9f7 837 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
<> 144:ef7eb2e8f9f7 838 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
<> 144:ef7eb2e8f9f7 839 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
<> 144:ef7eb2e8f9f7 840 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
<> 144:ef7eb2e8f9f7 841 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
<> 144:ef7eb2e8f9f7 842 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
<> 144:ef7eb2e8f9f7 843 * @arg SDIO_FLAG_CMDACT: Command transfer in progress
<> 144:ef7eb2e8f9f7 844 * @arg SDIO_FLAG_TXACT: Data transmit in progress
<> 144:ef7eb2e8f9f7 845 * @arg SDIO_FLAG_RXACT: Data receive in progress
<> 144:ef7eb2e8f9f7 846 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
<> 144:ef7eb2e8f9f7 847 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
<> 144:ef7eb2e8f9f7 848 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
<> 144:ef7eb2e8f9f7 849 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
<> 144:ef7eb2e8f9f7 850 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
<> 144:ef7eb2e8f9f7 851 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
<> 144:ef7eb2e8f9f7 852 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
<> 144:ef7eb2e8f9f7 853 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
<> 144:ef7eb2e8f9f7 854 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
<> 144:ef7eb2e8f9f7 855 * @retval The new state of SDIO_FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 856 */
AnnaBridge 165:e614a9f1c9e2 857 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
<> 144:ef7eb2e8f9f7 858
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 /**
<> 144:ef7eb2e8f9f7 861 * @brief Clears the SDIO pending flags.
<> 144:ef7eb2e8f9f7 862 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 863 * @param __FLAG__: specifies the flag to clear.
<> 144:ef7eb2e8f9f7 864 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 865 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
<> 144:ef7eb2e8f9f7 866 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
<> 144:ef7eb2e8f9f7 867 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
<> 144:ef7eb2e8f9f7 868 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
<> 144:ef7eb2e8f9f7 869 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
<> 144:ef7eb2e8f9f7 870 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
<> 144:ef7eb2e8f9f7 871 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
<> 144:ef7eb2e8f9f7 872 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
<> 144:ef7eb2e8f9f7 873 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
<> 144:ef7eb2e8f9f7 874 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
<> 144:ef7eb2e8f9f7 875 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
<> 144:ef7eb2e8f9f7 876 * @retval None
<> 144:ef7eb2e8f9f7 877 */
AnnaBridge 165:e614a9f1c9e2 878 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 /**
<> 144:ef7eb2e8f9f7 881 * @brief Checks whether the specified SDIO interrupt has occurred or not.
<> 144:ef7eb2e8f9f7 882 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 883 * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
<> 144:ef7eb2e8f9f7 884 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 885 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 886 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 887 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 888 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 889 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 890 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 891 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 892 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<> 144:ef7eb2e8f9f7 893 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 894 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 895 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
<> 144:ef7eb2e8f9f7 896 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
<> 144:ef7eb2e8f9f7 897 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
<> 144:ef7eb2e8f9f7 898 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<> 144:ef7eb2e8f9f7 899 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<> 144:ef7eb2e8f9f7 900 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
<> 144:ef7eb2e8f9f7 901 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
<> 144:ef7eb2e8f9f7 902 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
<> 144:ef7eb2e8f9f7 903 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
<> 144:ef7eb2e8f9f7 904 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
<> 144:ef7eb2e8f9f7 905 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
<> 144:ef7eb2e8f9f7 906 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 907 * @retval The new state of SDIO_IT (SET or RESET).
<> 144:ef7eb2e8f9f7 908 */
AnnaBridge 165:e614a9f1c9e2 909 #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 /**
<> 144:ef7eb2e8f9f7 912 * @brief Clears the SDIO's interrupt pending bits.
<> 144:ef7eb2e8f9f7 913 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 914 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
<> 144:ef7eb2e8f9f7 915 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 916 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 917 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 918 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 919 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 920 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 921 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 922 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 923 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<> 144:ef7eb2e8f9f7 924 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 925 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 926 * @retval None
<> 144:ef7eb2e8f9f7 927 */
AnnaBridge 165:e614a9f1c9e2 928 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 /**
<> 144:ef7eb2e8f9f7 931 * @brief Enable Start the SD I/O Read Wait operation.
<> 144:ef7eb2e8f9f7 932 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 933 * @retval None
<> 144:ef7eb2e8f9f7 934 */
AnnaBridge 165:e614a9f1c9e2 935 #define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 /**
<> 144:ef7eb2e8f9f7 938 * @brief Disable Start the SD I/O Read Wait operations.
<> 144:ef7eb2e8f9f7 939 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 940 * @retval None
<> 144:ef7eb2e8f9f7 941 */
AnnaBridge 165:e614a9f1c9e2 942 #define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
<> 144:ef7eb2e8f9f7 943
<> 144:ef7eb2e8f9f7 944 /**
<> 144:ef7eb2e8f9f7 945 * @brief Enable Start the SD I/O Read Wait operation.
<> 144:ef7eb2e8f9f7 946 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 947 * @retval None
<> 144:ef7eb2e8f9f7 948 */
AnnaBridge 165:e614a9f1c9e2 949 #define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 /**
<> 144:ef7eb2e8f9f7 952 * @brief Disable Stop the SD I/O Read Wait operations.
<> 144:ef7eb2e8f9f7 953 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 954 * @retval None
<> 144:ef7eb2e8f9f7 955 */
AnnaBridge 165:e614a9f1c9e2 956 #define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
<> 144:ef7eb2e8f9f7 957
<> 144:ef7eb2e8f9f7 958 /**
<> 144:ef7eb2e8f9f7 959 * @brief Enable the SD I/O Mode Operation.
<> 144:ef7eb2e8f9f7 960 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 961 * @retval None
<> 144:ef7eb2e8f9f7 962 */
AnnaBridge 165:e614a9f1c9e2 963 #define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 /**
<> 144:ef7eb2e8f9f7 966 * @brief Disable the SD I/O Mode Operation.
<> 144:ef7eb2e8f9f7 967 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 968 * @retval None
<> 144:ef7eb2e8f9f7 969 */
AnnaBridge 165:e614a9f1c9e2 970 #define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
<> 144:ef7eb2e8f9f7 971
<> 144:ef7eb2e8f9f7 972 /**
<> 144:ef7eb2e8f9f7 973 * @brief Enable the SD I/O Suspend command sending.
<> 144:ef7eb2e8f9f7 974 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 975 * @retval None
<> 144:ef7eb2e8f9f7 976 */
AnnaBridge 165:e614a9f1c9e2 977 #define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
<> 144:ef7eb2e8f9f7 978
<> 144:ef7eb2e8f9f7 979 /**
<> 144:ef7eb2e8f9f7 980 * @brief Disable the SD I/O Suspend command sending.
<> 144:ef7eb2e8f9f7 981 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 982 * @retval None
<> 144:ef7eb2e8f9f7 983 */
AnnaBridge 165:e614a9f1c9e2 984 #define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
<> 144:ef7eb2e8f9f7 985 /**
<> 144:ef7eb2e8f9f7 986 * @brief Enable the command completion signal.
<> 144:ef7eb2e8f9f7 987 * @retval None
<> 144:ef7eb2e8f9f7 988 */
AnnaBridge 165:e614a9f1c9e2 989 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
<> 144:ef7eb2e8f9f7 990
<> 144:ef7eb2e8f9f7 991 /**
<> 144:ef7eb2e8f9f7 992 * @brief Disable the command completion signal.
<> 144:ef7eb2e8f9f7 993 * @retval None
<> 144:ef7eb2e8f9f7 994 */
AnnaBridge 165:e614a9f1c9e2 995 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
<> 144:ef7eb2e8f9f7 996
<> 144:ef7eb2e8f9f7 997 /**
<> 144:ef7eb2e8f9f7 998 * @brief Enable the CE-ATA interrupt.
<> 144:ef7eb2e8f9f7 999 * @retval None
<> 144:ef7eb2e8f9f7 1000 */
AnnaBridge 165:e614a9f1c9e2 1001 #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U)
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 /**
<> 144:ef7eb2e8f9f7 1004 * @brief Disable the CE-ATA interrupt.
<> 144:ef7eb2e8f9f7 1005 * @retval None
<> 144:ef7eb2e8f9f7 1006 */
AnnaBridge 165:e614a9f1c9e2 1007 #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U)
<> 144:ef7eb2e8f9f7 1008
<> 144:ef7eb2e8f9f7 1009 /**
<> 144:ef7eb2e8f9f7 1010 * @brief Enable send CE-ATA command (CMD61).
<> 144:ef7eb2e8f9f7 1011 * @retval None
<> 144:ef7eb2e8f9f7 1012 */
AnnaBridge 165:e614a9f1c9e2 1013 #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 /**
<> 144:ef7eb2e8f9f7 1016 * @brief Disable send CE-ATA command (CMD61).
<> 144:ef7eb2e8f9f7 1017 * @retval None
<> 144:ef7eb2e8f9f7 1018 */
AnnaBridge 165:e614a9f1c9e2 1019 #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 /**
<> 144:ef7eb2e8f9f7 1022 * @}
<> 144:ef7eb2e8f9f7 1023 */
AnnaBridge 165:e614a9f1c9e2 1024
<> 144:ef7eb2e8f9f7 1025 /**
<> 144:ef7eb2e8f9f7 1026 * @}
<> 144:ef7eb2e8f9f7 1027 */
AnnaBridge 165:e614a9f1c9e2 1028
<> 144:ef7eb2e8f9f7 1029 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1030 /** @addtogroup SDMMC_LL_Exported_Functions
<> 144:ef7eb2e8f9f7 1031 * @{
<> 144:ef7eb2e8f9f7 1032 */
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 /* Initialization/de-initialization functions **********************************/
<> 144:ef7eb2e8f9f7 1035 /** @addtogroup HAL_SDMMC_LL_Group1
<> 144:ef7eb2e8f9f7 1036 * @{
<> 144:ef7eb2e8f9f7 1037 */
<> 144:ef7eb2e8f9f7 1038 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
<> 144:ef7eb2e8f9f7 1039 /**
<> 144:ef7eb2e8f9f7 1040 * @}
<> 144:ef7eb2e8f9f7 1041 */
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 /* I/O operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 1044 /** @addtogroup HAL_SDMMC_LL_Group2
<> 144:ef7eb2e8f9f7 1045 * @{
<> 144:ef7eb2e8f9f7 1046 */
<> 144:ef7eb2e8f9f7 1047 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 1048 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
<> 144:ef7eb2e8f9f7 1049 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
<> 144:ef7eb2e8f9f7 1050 /**
<> 144:ef7eb2e8f9f7 1051 * @}
<> 144:ef7eb2e8f9f7 1052 */
<> 144:ef7eb2e8f9f7 1053
<> 144:ef7eb2e8f9f7 1054 /* Peripheral Control functions ************************************************/
<> 144:ef7eb2e8f9f7 1055 /** @addtogroup HAL_SDMMC_LL_Group3
<> 144:ef7eb2e8f9f7 1056 * @{
<> 144:ef7eb2e8f9f7 1057 */
<> 144:ef7eb2e8f9f7 1058 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
<> 144:ef7eb2e8f9f7 1059 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
<> 144:ef7eb2e8f9f7 1060 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
<> 144:ef7eb2e8f9f7 1061
<> 144:ef7eb2e8f9f7 1062 /* Command path state machine (CPSM) management functions */
<> 144:ef7eb2e8f9f7 1063 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command);
<> 144:ef7eb2e8f9f7 1064 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
<> 144:ef7eb2e8f9f7 1065 uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 /* Data path state machine (DPSM) management functions */
AnnaBridge 165:e614a9f1c9e2 1068 HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data);
<> 144:ef7eb2e8f9f7 1069 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
<> 144:ef7eb2e8f9f7 1070 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
<> 144:ef7eb2e8f9f7 1071
AnnaBridge 165:e614a9f1c9e2 1072 /* SDMMC Cards mode management functions */
AnnaBridge 165:e614a9f1c9e2 1073 HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
AnnaBridge 165:e614a9f1c9e2 1074
AnnaBridge 165:e614a9f1c9e2 1075 /* SDMMC Commands management functions */
AnnaBridge 165:e614a9f1c9e2 1076 uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
AnnaBridge 165:e614a9f1c9e2 1077 uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
AnnaBridge 165:e614a9f1c9e2 1078 uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
AnnaBridge 165:e614a9f1c9e2 1079 uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
AnnaBridge 165:e614a9f1c9e2 1080 uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
AnnaBridge 165:e614a9f1c9e2 1081 uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
AnnaBridge 165:e614a9f1c9e2 1082 uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
AnnaBridge 165:e614a9f1c9e2 1083 uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
AnnaBridge 165:e614a9f1c9e2 1084 uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
AnnaBridge 165:e614a9f1c9e2 1085 uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
AnnaBridge 165:e614a9f1c9e2 1086 uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
AnnaBridge 165:e614a9f1c9e2 1087 uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
AnnaBridge 165:e614a9f1c9e2 1088 uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge 165:e614a9f1c9e2 1089 uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType);
AnnaBridge 165:e614a9f1c9e2 1090 uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
AnnaBridge 165:e614a9f1c9e2 1091 uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
AnnaBridge 165:e614a9f1c9e2 1092 uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
AnnaBridge 165:e614a9f1c9e2 1093 uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge 165:e614a9f1c9e2 1094 uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA);
AnnaBridge 165:e614a9f1c9e2 1095 uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge 165:e614a9f1c9e2 1096 uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
AnnaBridge 165:e614a9f1c9e2 1097
AnnaBridge 165:e614a9f1c9e2 1098 uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge 165:e614a9f1c9e2 1099 uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge 165:e614a9f1c9e2 1100 uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
AnnaBridge 165:e614a9f1c9e2 1101 uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
<> 144:ef7eb2e8f9f7 1102
<> 144:ef7eb2e8f9f7 1103 /**
<> 144:ef7eb2e8f9f7 1104 * @}
<> 144:ef7eb2e8f9f7 1105 */
<> 144:ef7eb2e8f9f7 1106
<> 144:ef7eb2e8f9f7 1107 /**
<> 144:ef7eb2e8f9f7 1108 * @}
<> 144:ef7eb2e8f9f7 1109 */
<> 144:ef7eb2e8f9f7 1110
<> 144:ef7eb2e8f9f7 1111 /**
<> 144:ef7eb2e8f9f7 1112 * @}
<> 144:ef7eb2e8f9f7 1113 */
<> 144:ef7eb2e8f9f7 1114
<> 144:ef7eb2e8f9f7 1115 /**
<> 144:ef7eb2e8f9f7 1116 * @}
<> 144:ef7eb2e8f9f7 1117 */
<> 144:ef7eb2e8f9f7 1118
<> 144:ef7eb2e8f9f7 1119 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1120 }
<> 144:ef7eb2e8f9f7 1121 #endif
<> 144:ef7eb2e8f9f7 1122
<> 144:ef7eb2e8f9f7 1123 #endif /* STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 1124
<> 144:ef7eb2e8f9f7 1125 #endif /* __stm32f1xx_LL_SD_H */
<> 144:ef7eb2e8f9f7 1126
<> 144:ef7eb2e8f9f7 1127 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/