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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/device/MKW41Z4_features.h@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:
<>
Date:
Wed Jan 04 16:58:05 2017 +0000
Revision:
154:37f96f9d4de2
This updates the lib to the mbed lib v133

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 ** ###################################################################
<> 154:37f96f9d4de2 3 ** Version: rev. 1.0, 2015-09-23
<> 154:37f96f9d4de2 4 ** Build: b160720
<> 154:37f96f9d4de2 5 **
<> 154:37f96f9d4de2 6 ** Abstract:
<> 154:37f96f9d4de2 7 ** Chip specific module features.
<> 154:37f96f9d4de2 8 **
<> 154:37f96f9d4de2 9 ** Copyright (c) 2016 Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 10 ** All rights reserved.
<> 154:37f96f9d4de2 11 **
<> 154:37f96f9d4de2 12 ** Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 13 ** are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 14 **
<> 154:37f96f9d4de2 15 ** o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 16 ** of conditions and the following disclaimer.
<> 154:37f96f9d4de2 17 **
<> 154:37f96f9d4de2 18 ** o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 19 ** list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 20 ** other materials provided with the distribution.
<> 154:37f96f9d4de2 21 **
<> 154:37f96f9d4de2 22 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 23 ** contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 24 ** software without specific prior written permission.
<> 154:37f96f9d4de2 25 **
<> 154:37f96f9d4de2 26 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 27 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 28 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 29 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 30 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 31 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 32 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 33 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 34 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 35 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 36 **
<> 154:37f96f9d4de2 37 ** http: www.freescale.com
<> 154:37f96f9d4de2 38 ** mail: support@freescale.com
<> 154:37f96f9d4de2 39 **
<> 154:37f96f9d4de2 40 ** Revisions:
<> 154:37f96f9d4de2 41 ** - rev. 1.0 (2015-09-23)
<> 154:37f96f9d4de2 42 ** Initial version.
<> 154:37f96f9d4de2 43 **
<> 154:37f96f9d4de2 44 ** ###################################################################
<> 154:37f96f9d4de2 45 */
<> 154:37f96f9d4de2 46
<> 154:37f96f9d4de2 47 #ifndef _MKW41Z4_FEATURES_H_
<> 154:37f96f9d4de2 48 #define _MKW41Z4_FEATURES_H_
<> 154:37f96f9d4de2 49
<> 154:37f96f9d4de2 50 /* SOC module features */
<> 154:37f96f9d4de2 51
<> 154:37f96f9d4de2 52 /* @brief ACMP availability on the SoC. */
<> 154:37f96f9d4de2 53 #define FSL_FEATURE_SOC_ACMP_COUNT (0)
<> 154:37f96f9d4de2 54 /* @brief ADC16 availability on the SoC. */
<> 154:37f96f9d4de2 55 #define FSL_FEATURE_SOC_ADC16_COUNT (1)
<> 154:37f96f9d4de2 56 /* @brief ADC12 availability on the SoC. */
<> 154:37f96f9d4de2 57 #define FSL_FEATURE_SOC_ADC12_COUNT (0)
<> 154:37f96f9d4de2 58 /* @brief AFE availability on the SoC. */
<> 154:37f96f9d4de2 59 #define FSL_FEATURE_SOC_AFE_COUNT (0)
<> 154:37f96f9d4de2 60 /* @brief AIPS availability on the SoC. */
<> 154:37f96f9d4de2 61 #define FSL_FEATURE_SOC_AIPS_COUNT (0)
<> 154:37f96f9d4de2 62 /* @brief AOI availability on the SoC. */
<> 154:37f96f9d4de2 63 #define FSL_FEATURE_SOC_AOI_COUNT (0)
<> 154:37f96f9d4de2 64 /* @brief AXBS availability on the SoC. */
<> 154:37f96f9d4de2 65 #define FSL_FEATURE_SOC_AXBS_COUNT (0)
<> 154:37f96f9d4de2 66 /* @brief ASMC availability on the SoC. */
<> 154:37f96f9d4de2 67 #define FSL_FEATURE_SOC_ASMC_COUNT (0)
<> 154:37f96f9d4de2 68 /* @brief CADC availability on the SoC. */
<> 154:37f96f9d4de2 69 #define FSL_FEATURE_SOC_CADC_COUNT (0)
<> 154:37f96f9d4de2 70 /* @brief FLEXCAN availability on the SoC. */
<> 154:37f96f9d4de2 71 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (0)
<> 154:37f96f9d4de2 72 /* @brief MMCAU availability on the SoC. */
<> 154:37f96f9d4de2 73 #define FSL_FEATURE_SOC_MMCAU_COUNT (0)
<> 154:37f96f9d4de2 74 /* @brief CMP availability on the SoC. */
<> 154:37f96f9d4de2 75 #define FSL_FEATURE_SOC_CMP_COUNT (1)
<> 154:37f96f9d4de2 76 /* @brief CMT availability on the SoC. */
<> 154:37f96f9d4de2 77 #define FSL_FEATURE_SOC_CMT_COUNT (1)
<> 154:37f96f9d4de2 78 /* @brief CNC availability on the SoC. */
<> 154:37f96f9d4de2 79 #define FSL_FEATURE_SOC_CNC_COUNT (0)
<> 154:37f96f9d4de2 80 /* @brief CRC availability on the SoC. */
<> 154:37f96f9d4de2 81 #define FSL_FEATURE_SOC_CRC_COUNT (0)
<> 154:37f96f9d4de2 82 /* @brief DAC availability on the SoC. */
<> 154:37f96f9d4de2 83 #define FSL_FEATURE_SOC_DAC_COUNT (1)
<> 154:37f96f9d4de2 84 /* @brief DAC32 availability on the SoC. */
<> 154:37f96f9d4de2 85 #define FSL_FEATURE_SOC_DAC32_COUNT (0)
<> 154:37f96f9d4de2 86 /* @brief DCDC availability on the SoC. */
<> 154:37f96f9d4de2 87 #define FSL_FEATURE_SOC_DCDC_COUNT (1)
<> 154:37f96f9d4de2 88 /* @brief DDR availability on the SoC. */
<> 154:37f96f9d4de2 89 #define FSL_FEATURE_SOC_DDR_COUNT (0)
<> 154:37f96f9d4de2 90 /* @brief DMA availability on the SoC. */
<> 154:37f96f9d4de2 91 #define FSL_FEATURE_SOC_DMA_COUNT (0)
<> 154:37f96f9d4de2 92 /* @brief EDMA availability on the SoC. */
<> 154:37f96f9d4de2 93 #define FSL_FEATURE_SOC_EDMA_COUNT (1)
<> 154:37f96f9d4de2 94 /* @brief DMAMUX availability on the SoC. */
<> 154:37f96f9d4de2 95 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
<> 154:37f96f9d4de2 96 /* @brief DRY availability on the SoC. */
<> 154:37f96f9d4de2 97 #define FSL_FEATURE_SOC_DRY_COUNT (0)
<> 154:37f96f9d4de2 98 /* @brief DSPI availability on the SoC. */
<> 154:37f96f9d4de2 99 #define FSL_FEATURE_SOC_DSPI_COUNT (2)
<> 154:37f96f9d4de2 100 /* @brief EMVSIM availability on the SoC. */
<> 154:37f96f9d4de2 101 #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
<> 154:37f96f9d4de2 102 /* @brief ENC availability on the SoC. */
<> 154:37f96f9d4de2 103 #define FSL_FEATURE_SOC_ENC_COUNT (0)
<> 154:37f96f9d4de2 104 /* @brief ENET availability on the SoC. */
<> 154:37f96f9d4de2 105 #define FSL_FEATURE_SOC_ENET_COUNT (0)
<> 154:37f96f9d4de2 106 /* @brief EWM availability on the SoC. */
<> 154:37f96f9d4de2 107 #define FSL_FEATURE_SOC_EWM_COUNT (0)
<> 154:37f96f9d4de2 108 /* @brief FB availability on the SoC. */
<> 154:37f96f9d4de2 109 #define FSL_FEATURE_SOC_FB_COUNT (0)
<> 154:37f96f9d4de2 110 /* @brief FGPIO availability on the SoC. */
<> 154:37f96f9d4de2 111 #define FSL_FEATURE_SOC_FGPIO_COUNT (3)
<> 154:37f96f9d4de2 112 /* @brief FLEXIO availability on the SoC. */
<> 154:37f96f9d4de2 113 #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
<> 154:37f96f9d4de2 114 /* @brief FMC availability on the SoC. */
<> 154:37f96f9d4de2 115 #define FSL_FEATURE_SOC_FMC_COUNT (0)
<> 154:37f96f9d4de2 116 /* @brief FSKDT availability on the SoC. */
<> 154:37f96f9d4de2 117 #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
<> 154:37f96f9d4de2 118 /* @brief FTFA availability on the SoC. */
<> 154:37f96f9d4de2 119 #define FSL_FEATURE_SOC_FTFA_COUNT (1)
<> 154:37f96f9d4de2 120 /* @brief FTFE availability on the SoC. */
<> 154:37f96f9d4de2 121 #define FSL_FEATURE_SOC_FTFE_COUNT (0)
<> 154:37f96f9d4de2 122 /* @brief FTFL availability on the SoC. */
<> 154:37f96f9d4de2 123 #define FSL_FEATURE_SOC_FTFL_COUNT (0)
<> 154:37f96f9d4de2 124 /* @brief FTM availability on the SoC. */
<> 154:37f96f9d4de2 125 #define FSL_FEATURE_SOC_FTM_COUNT (0)
<> 154:37f96f9d4de2 126 /* @brief FTMRA availability on the SoC. */
<> 154:37f96f9d4de2 127 #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
<> 154:37f96f9d4de2 128 /* @brief FTMRE availability on the SoC. */
<> 154:37f96f9d4de2 129 #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
<> 154:37f96f9d4de2 130 /* @brief FTMRH availability on the SoC. */
<> 154:37f96f9d4de2 131 #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
<> 154:37f96f9d4de2 132 /* @brief GPIO availability on the SoC. */
<> 154:37f96f9d4de2 133 #define FSL_FEATURE_SOC_GPIO_COUNT (3)
<> 154:37f96f9d4de2 134 /* @brief HSADC availability on the SoC. */
<> 154:37f96f9d4de2 135 #define FSL_FEATURE_SOC_HSADC_COUNT (0)
<> 154:37f96f9d4de2 136 /* @brief I2C availability on the SoC. */
<> 154:37f96f9d4de2 137 #define FSL_FEATURE_SOC_I2C_COUNT (2)
<> 154:37f96f9d4de2 138 /* @brief I2S availability on the SoC. */
<> 154:37f96f9d4de2 139 #define FSL_FEATURE_SOC_I2S_COUNT (0)
<> 154:37f96f9d4de2 140 /* @brief ICS availability on the SoC. */
<> 154:37f96f9d4de2 141 #define FSL_FEATURE_SOC_ICS_COUNT (0)
<> 154:37f96f9d4de2 142 /* @brief INTMUX availability on the SoC. */
<> 154:37f96f9d4de2 143 #define FSL_FEATURE_SOC_INTMUX_COUNT (0)
<> 154:37f96f9d4de2 144 /* @brief IRQ availability on the SoC. */
<> 154:37f96f9d4de2 145 #define FSL_FEATURE_SOC_IRQ_COUNT (0)
<> 154:37f96f9d4de2 146 /* @brief KBI availability on the SoC. */
<> 154:37f96f9d4de2 147 #define FSL_FEATURE_SOC_KBI_COUNT (0)
<> 154:37f96f9d4de2 148 /* @brief SLCD availability on the SoC. */
<> 154:37f96f9d4de2 149 #define FSL_FEATURE_SOC_SLCD_COUNT (0)
<> 154:37f96f9d4de2 150 /* @brief LCDC availability on the SoC. */
<> 154:37f96f9d4de2 151 #define FSL_FEATURE_SOC_LCDC_COUNT (0)
<> 154:37f96f9d4de2 152 /* @brief LDO availability on the SoC. */
<> 154:37f96f9d4de2 153 #define FSL_FEATURE_SOC_LDO_COUNT (0)
<> 154:37f96f9d4de2 154 /* @brief LLWU availability on the SoC. */
<> 154:37f96f9d4de2 155 #define FSL_FEATURE_SOC_LLWU_COUNT (1)
<> 154:37f96f9d4de2 156 /* @brief LMEM availability on the SoC. */
<> 154:37f96f9d4de2 157 #define FSL_FEATURE_SOC_LMEM_COUNT (0)
<> 154:37f96f9d4de2 158 /* @brief LPI2C availability on the SoC. */
<> 154:37f96f9d4de2 159 #define FSL_FEATURE_SOC_LPI2C_COUNT (0)
<> 154:37f96f9d4de2 160 /* @brief LPIT availability on the SoC. */
<> 154:37f96f9d4de2 161 #define FSL_FEATURE_SOC_LPIT_COUNT (0)
<> 154:37f96f9d4de2 162 /* @brief LPSCI availability on the SoC. */
<> 154:37f96f9d4de2 163 #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
<> 154:37f96f9d4de2 164 /* @brief LPSPI availability on the SoC. */
<> 154:37f96f9d4de2 165 #define FSL_FEATURE_SOC_LPSPI_COUNT (0)
<> 154:37f96f9d4de2 166 /* @brief LPTMR availability on the SoC. */
<> 154:37f96f9d4de2 167 #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
<> 154:37f96f9d4de2 168 /* @brief LPTPM availability on the SoC. */
<> 154:37f96f9d4de2 169 #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
<> 154:37f96f9d4de2 170 /* @brief LPUART availability on the SoC. */
<> 154:37f96f9d4de2 171 #define FSL_FEATURE_SOC_LPUART_COUNT (1)
<> 154:37f96f9d4de2 172 /* @brief LTC availability on the SoC. */
<> 154:37f96f9d4de2 173 #define FSL_FEATURE_SOC_LTC_COUNT (1)
<> 154:37f96f9d4de2 174 /* @brief MC availability on the SoC. */
<> 154:37f96f9d4de2 175 #define FSL_FEATURE_SOC_MC_COUNT (0)
<> 154:37f96f9d4de2 176 /* @brief MCG availability on the SoC. */
<> 154:37f96f9d4de2 177 #define FSL_FEATURE_SOC_MCG_COUNT (1)
<> 154:37f96f9d4de2 178 /* @brief MCGLITE availability on the SoC. */
<> 154:37f96f9d4de2 179 #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
<> 154:37f96f9d4de2 180 /* @brief MCM availability on the SoC. */
<> 154:37f96f9d4de2 181 #define FSL_FEATURE_SOC_MCM_COUNT (1)
<> 154:37f96f9d4de2 182 /* @brief MMAU availability on the SoC. */
<> 154:37f96f9d4de2 183 #define FSL_FEATURE_SOC_MMAU_COUNT (0)
<> 154:37f96f9d4de2 184 /* @brief MMDVSQ availability on the SoC. */
<> 154:37f96f9d4de2 185 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
<> 154:37f96f9d4de2 186 /* @brief MPU availability on the SoC. */
<> 154:37f96f9d4de2 187 #define FSL_FEATURE_SOC_MPU_COUNT (0)
<> 154:37f96f9d4de2 188 /* @brief MSCAN availability on the SoC. */
<> 154:37f96f9d4de2 189 #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
<> 154:37f96f9d4de2 190 /* @brief MSCM availability on the SoC. */
<> 154:37f96f9d4de2 191 #define FSL_FEATURE_SOC_MSCM_COUNT (0)
<> 154:37f96f9d4de2 192 /* @brief MTB availability on the SoC. */
<> 154:37f96f9d4de2 193 #define FSL_FEATURE_SOC_MTB_COUNT (1)
<> 154:37f96f9d4de2 194 /* @brief MTBDWT availability on the SoC. */
<> 154:37f96f9d4de2 195 #define FSL_FEATURE_SOC_MTBDWT_COUNT (1)
<> 154:37f96f9d4de2 196 /* @brief MU availability on the SoC. */
<> 154:37f96f9d4de2 197 #define FSL_FEATURE_SOC_MU_COUNT (0)
<> 154:37f96f9d4de2 198 /* @brief NFC availability on the SoC. */
<> 154:37f96f9d4de2 199 #define FSL_FEATURE_SOC_NFC_COUNT (0)
<> 154:37f96f9d4de2 200 /* @brief OPAMP availability on the SoC. */
<> 154:37f96f9d4de2 201 #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
<> 154:37f96f9d4de2 202 /* @brief OSC availability on the SoC. */
<> 154:37f96f9d4de2 203 #define FSL_FEATURE_SOC_OSC_COUNT (0)
<> 154:37f96f9d4de2 204 /* @brief OSC32 availability on the SoC. */
<> 154:37f96f9d4de2 205 #define FSL_FEATURE_SOC_OSC32_COUNT (0)
<> 154:37f96f9d4de2 206 /* @brief OTFAD availability on the SoC. */
<> 154:37f96f9d4de2 207 #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
<> 154:37f96f9d4de2 208 /* @brief PDB availability on the SoC. */
<> 154:37f96f9d4de2 209 #define FSL_FEATURE_SOC_PDB_COUNT (0)
<> 154:37f96f9d4de2 210 /* @brief PCC availability on the SoC. */
<> 154:37f96f9d4de2 211 #define FSL_FEATURE_SOC_PCC_COUNT (0)
<> 154:37f96f9d4de2 212 /* @brief PGA availability on the SoC. */
<> 154:37f96f9d4de2 213 #define FSL_FEATURE_SOC_PGA_COUNT (0)
<> 154:37f96f9d4de2 214 /* @brief PIT availability on the SoC. */
<> 154:37f96f9d4de2 215 #define FSL_FEATURE_SOC_PIT_COUNT (1)
<> 154:37f96f9d4de2 216 /* @brief PMC availability on the SoC. */
<> 154:37f96f9d4de2 217 #define FSL_FEATURE_SOC_PMC_COUNT (1)
<> 154:37f96f9d4de2 218 /* @brief PORT availability on the SoC. */
<> 154:37f96f9d4de2 219 #define FSL_FEATURE_SOC_PORT_COUNT (3)
<> 154:37f96f9d4de2 220 /* @brief PWM availability on the SoC. */
<> 154:37f96f9d4de2 221 #define FSL_FEATURE_SOC_PWM_COUNT (0)
<> 154:37f96f9d4de2 222 /* @brief PWT availability on the SoC. */
<> 154:37f96f9d4de2 223 #define FSL_FEATURE_SOC_PWT_COUNT (0)
<> 154:37f96f9d4de2 224 /* @brief QuadSPI availability on the SoC. */
<> 154:37f96f9d4de2 225 #define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
<> 154:37f96f9d4de2 226 /* @brief RCM availability on the SoC. */
<> 154:37f96f9d4de2 227 #define FSL_FEATURE_SOC_RCM_COUNT (1)
<> 154:37f96f9d4de2 228 /* @brief RFSYS availability on the SoC. */
<> 154:37f96f9d4de2 229 #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
<> 154:37f96f9d4de2 230 /* @brief RFVBAT availability on the SoC. */
<> 154:37f96f9d4de2 231 #define FSL_FEATURE_SOC_RFVBAT_COUNT (0)
<> 154:37f96f9d4de2 232 /* @brief RNG availability on the SoC. */
<> 154:37f96f9d4de2 233 #define FSL_FEATURE_SOC_RNG_COUNT (0)
<> 154:37f96f9d4de2 234 /* @brief RNGB availability on the SoC. */
<> 154:37f96f9d4de2 235 #define FSL_FEATURE_SOC_RNGB_COUNT (0)
<> 154:37f96f9d4de2 236 /* @brief ROM availability on the SoC. */
<> 154:37f96f9d4de2 237 #define FSL_FEATURE_SOC_ROM_COUNT (1)
<> 154:37f96f9d4de2 238 /* @brief RSIM availability on the SoC. */
<> 154:37f96f9d4de2 239 #define FSL_FEATURE_SOC_RSIM_COUNT (1)
<> 154:37f96f9d4de2 240 /* @brief RTC availability on the SoC. */
<> 154:37f96f9d4de2 241 #define FSL_FEATURE_SOC_RTC_COUNT (1)
<> 154:37f96f9d4de2 242 /* @brief SCG availability on the SoC. */
<> 154:37f96f9d4de2 243 #define FSL_FEATURE_SOC_SCG_COUNT (0)
<> 154:37f96f9d4de2 244 /* @brief SCI availability on the SoC. */
<> 154:37f96f9d4de2 245 #define FSL_FEATURE_SOC_SCI_COUNT (0)
<> 154:37f96f9d4de2 246 /* @brief SDHC availability on the SoC. */
<> 154:37f96f9d4de2 247 #define FSL_FEATURE_SOC_SDHC_COUNT (0)
<> 154:37f96f9d4de2 248 /* @brief SDRAM availability on the SoC. */
<> 154:37f96f9d4de2 249 #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
<> 154:37f96f9d4de2 250 /* @brief SEMA42 availability on the SoC. */
<> 154:37f96f9d4de2 251 #define FSL_FEATURE_SOC_SEMA42_COUNT (0)
<> 154:37f96f9d4de2 252 /* @brief SIM availability on the SoC. */
<> 154:37f96f9d4de2 253 #define FSL_FEATURE_SOC_SIM_COUNT (1)
<> 154:37f96f9d4de2 254 /* @brief SMC availability on the SoC. */
<> 154:37f96f9d4de2 255 #define FSL_FEATURE_SOC_SMC_COUNT (1)
<> 154:37f96f9d4de2 256 /* @brief SPI availability on the SoC. */
<> 154:37f96f9d4de2 257 #define FSL_FEATURE_SOC_SPI_COUNT (0)
<> 154:37f96f9d4de2 258 /* @brief TMR availability on the SoC. */
<> 154:37f96f9d4de2 259 #define FSL_FEATURE_SOC_TMR_COUNT (0)
<> 154:37f96f9d4de2 260 /* @brief TPM availability on the SoC. */
<> 154:37f96f9d4de2 261 #define FSL_FEATURE_SOC_TPM_COUNT (3)
<> 154:37f96f9d4de2 262 /* @brief TRGMUX availability on the SoC. */
<> 154:37f96f9d4de2 263 #define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
<> 154:37f96f9d4de2 264 /* @brief TRIAMP availability on the SoC. */
<> 154:37f96f9d4de2 265 #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
<> 154:37f96f9d4de2 266 /* @brief TRNG availability on the SoC. */
<> 154:37f96f9d4de2 267 #define FSL_FEATURE_SOC_TRNG_COUNT (1)
<> 154:37f96f9d4de2 268 /* @brief TSI availability on the SoC. */
<> 154:37f96f9d4de2 269 #define FSL_FEATURE_SOC_TSI_COUNT (1)
<> 154:37f96f9d4de2 270 /* @brief TSTMR availability on the SoC. */
<> 154:37f96f9d4de2 271 #define FSL_FEATURE_SOC_TSTMR_COUNT (0)
<> 154:37f96f9d4de2 272 /* @brief UART availability on the SoC. */
<> 154:37f96f9d4de2 273 #define FSL_FEATURE_SOC_UART_COUNT (0)
<> 154:37f96f9d4de2 274 /* @brief USB availability on the SoC. */
<> 154:37f96f9d4de2 275 #define FSL_FEATURE_SOC_USB_COUNT (0)
<> 154:37f96f9d4de2 276 /* @brief USBDCD availability on the SoC. */
<> 154:37f96f9d4de2 277 #define FSL_FEATURE_SOC_USBDCD_COUNT (0)
<> 154:37f96f9d4de2 278 /* @brief USBHSDCD availability on the SoC. */
<> 154:37f96f9d4de2 279 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
<> 154:37f96f9d4de2 280 /* @brief USBPHY availability on the SoC. */
<> 154:37f96f9d4de2 281 #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
<> 154:37f96f9d4de2 282 /* @brief VREF availability on the SoC. */
<> 154:37f96f9d4de2 283 #define FSL_FEATURE_SOC_VREF_COUNT (1)
<> 154:37f96f9d4de2 284 /* @brief WDOG availability on the SoC. */
<> 154:37f96f9d4de2 285 #define FSL_FEATURE_SOC_WDOG_COUNT (0)
<> 154:37f96f9d4de2 286 /* @brief XBAR availability on the SoC. */
<> 154:37f96f9d4de2 287 #define FSL_FEATURE_SOC_XBAR_COUNT (0)
<> 154:37f96f9d4de2 288 /* @brief XBARA availability on the SoC. */
<> 154:37f96f9d4de2 289 #define FSL_FEATURE_SOC_XBARA_COUNT (0)
<> 154:37f96f9d4de2 290 /* @brief XBARB availability on the SoC. */
<> 154:37f96f9d4de2 291 #define FSL_FEATURE_SOC_XBARB_COUNT (0)
<> 154:37f96f9d4de2 292 /* @brief XCVR availability on the SoC. */
<> 154:37f96f9d4de2 293 #define FSL_FEATURE_SOC_XCVR_COUNT (1)
<> 154:37f96f9d4de2 294 /* @brief XRDC availability on the SoC. */
<> 154:37f96f9d4de2 295 #define FSL_FEATURE_SOC_XRDC_COUNT (0)
<> 154:37f96f9d4de2 296 /* @brief ZLL availability on the SoC. */
<> 154:37f96f9d4de2 297 #define FSL_FEATURE_SOC_ZLL_COUNT (1)
<> 154:37f96f9d4de2 298
<> 154:37f96f9d4de2 299 /* ADC16 module features */
<> 154:37f96f9d4de2 300
<> 154:37f96f9d4de2 301 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
<> 154:37f96f9d4de2 302 #define FSL_FEATURE_ADC16_HAS_PGA (0)
<> 154:37f96f9d4de2 303 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
<> 154:37f96f9d4de2 304 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
<> 154:37f96f9d4de2 305 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
<> 154:37f96f9d4de2 306 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
<> 154:37f96f9d4de2 307 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
<> 154:37f96f9d4de2 308 #define FSL_FEATURE_ADC16_HAS_DMA (1)
<> 154:37f96f9d4de2 309 /* @brief Has differential mode (bitfield SC1x[DIFF]). */
<> 154:37f96f9d4de2 310 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
<> 154:37f96f9d4de2 311 /* @brief Has FIFO (bit SC4[AFDEP]). */
<> 154:37f96f9d4de2 312 #define FSL_FEATURE_ADC16_HAS_FIFO (0)
<> 154:37f96f9d4de2 313 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */
<> 154:37f96f9d4de2 314 #define FSL_FEATURE_ADC16_FIFO_SIZE (0)
<> 154:37f96f9d4de2 315 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
<> 154:37f96f9d4de2 316 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
<> 154:37f96f9d4de2 317 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
<> 154:37f96f9d4de2 318 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
<> 154:37f96f9d4de2 319 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
<> 154:37f96f9d4de2 320 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
<> 154:37f96f9d4de2 321 /* @brief Has HW averaging (bit SC3[AVGE]). */
<> 154:37f96f9d4de2 322 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
<> 154:37f96f9d4de2 323 /* @brief Has offset correction (register OFS). */
<> 154:37f96f9d4de2 324 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
<> 154:37f96f9d4de2 325 /* @brief Maximum ADC resolution. */
<> 154:37f96f9d4de2 326 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
<> 154:37f96f9d4de2 327 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
<> 154:37f96f9d4de2 328 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
<> 154:37f96f9d4de2 329
<> 154:37f96f9d4de2 330 /* CMP module features */
<> 154:37f96f9d4de2 331
<> 154:37f96f9d4de2 332 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
<> 154:37f96f9d4de2 333 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1)
<> 154:37f96f9d4de2 334 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */
<> 154:37f96f9d4de2 335 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0)
<> 154:37f96f9d4de2 336 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
<> 154:37f96f9d4de2 337 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0)
<> 154:37f96f9d4de2 338 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
<> 154:37f96f9d4de2 339 #define FSL_FEATURE_CMP_HAS_DMA (1)
<> 154:37f96f9d4de2 340 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
<> 154:37f96f9d4de2 341 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
<> 154:37f96f9d4de2 342 /* @brief Has DAC Test function in CMP (register DACTEST). */
<> 154:37f96f9d4de2 343 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
<> 154:37f96f9d4de2 344
<> 154:37f96f9d4de2 345 /* COP module features */
<> 154:37f96f9d4de2 346
<> 154:37f96f9d4de2 347 /* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */
<> 154:37f96f9d4de2 348 #define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1)
<> 154:37f96f9d4de2 349 /* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */
<> 154:37f96f9d4de2 350 #define FSL_FEATURE_COP_HAS_STOP_ENABLE (1)
<> 154:37f96f9d4de2 351 /* @brief Has more clock sources like MCGIRC */
<> 154:37f96f9d4de2 352 #define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1)
<> 154:37f96f9d4de2 353 /* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */
<> 154:37f96f9d4de2 354 #define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1)
<> 154:37f96f9d4de2 355
<> 154:37f96f9d4de2 356 /* DAC module features */
<> 154:37f96f9d4de2 357
<> 154:37f96f9d4de2 358 /* @brief Define the size of hardware buffer */
<> 154:37f96f9d4de2 359 #define FSL_FEATURE_DAC_BUFFER_SIZE (2)
<> 154:37f96f9d4de2 360 /* @brief Define whether the buffer supports watermark event detection or not. */
<> 154:37f96f9d4de2 361 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
<> 154:37f96f9d4de2 362 /* @brief Define whether the buffer supports watermark selection detection or not. */
<> 154:37f96f9d4de2 363 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
<> 154:37f96f9d4de2 364 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
<> 154:37f96f9d4de2 365 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
<> 154:37f96f9d4de2 366 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
<> 154:37f96f9d4de2 367 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
<> 154:37f96f9d4de2 368 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
<> 154:37f96f9d4de2 369 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
<> 154:37f96f9d4de2 370 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
<> 154:37f96f9d4de2 371 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
<> 154:37f96f9d4de2 372 /* @brief Define whether FIFO buffer mode is available or not. */
<> 154:37f96f9d4de2 373 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
<> 154:37f96f9d4de2 374 /* @brief Define whether swing buffer mode is available or not.. */
<> 154:37f96f9d4de2 375 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0)
<> 154:37f96f9d4de2 376
<> 154:37f96f9d4de2 377 /* DCDC module features */
<> 154:37f96f9d4de2 378
<> 154:37f96f9d4de2 379 /* @brief Has VDD1P5 bits in DCDC REG3. */
<> 154:37f96f9d4de2 380 #define FSL_FEATURE_DCDC_REG3_HAS_VDD1P5_BITS (1)
<> 154:37f96f9d4de2 381 /* @brief Has VDD1P45 bits in DCDC REG3. */
<> 154:37f96f9d4de2 382 #define FSL_FEATURE_DCDC_REG3_HAS_VDD1P45_BITS (0)
<> 154:37f96f9d4de2 383
<> 154:37f96f9d4de2 384 /* EDMA module features */
<> 154:37f96f9d4de2 385
<> 154:37f96f9d4de2 386 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
<> 154:37f96f9d4de2 387 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (4)
<> 154:37f96f9d4de2 388 /* @brief Total number of DMA channels on all modules. */
<> 154:37f96f9d4de2 389 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 4)
<> 154:37f96f9d4de2 390 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
<> 154:37f96f9d4de2 391 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
<> 154:37f96f9d4de2 392 /* @brief Has DMA_Error interrupt vector. */
<> 154:37f96f9d4de2 393 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0)
<> 154:37f96f9d4de2 394 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
<> 154:37f96f9d4de2 395 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4)
<> 154:37f96f9d4de2 396
<> 154:37f96f9d4de2 397 /* DMAMUX module features */
<> 154:37f96f9d4de2 398
<> 154:37f96f9d4de2 399 /* @brief Number of DMA channels (related to number of register CHCFGn). */
<> 154:37f96f9d4de2 400 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4)
<> 154:37f96f9d4de2 401 /* @brief Total number of DMA channels on all modules. */
<> 154:37f96f9d4de2 402 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4)
<> 154:37f96f9d4de2 403 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
<> 154:37f96f9d4de2 404 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
<> 154:37f96f9d4de2 405
<> 154:37f96f9d4de2 406 /* FLASH module features */
<> 154:37f96f9d4de2 407
<> 154:37f96f9d4de2 408 #if defined(CPU_MKW41Z256VHT4)
<> 154:37f96f9d4de2 409 /* @brief Is of type FTFA. */
<> 154:37f96f9d4de2 410 #define FSL_FEATURE_FLASH_IS_FTFA (1)
<> 154:37f96f9d4de2 411 /* @brief Is of type FTFE. */
<> 154:37f96f9d4de2 412 #define FSL_FEATURE_FLASH_IS_FTFE (0)
<> 154:37f96f9d4de2 413 /* @brief Is of type FTFL. */
<> 154:37f96f9d4de2 414 #define FSL_FEATURE_FLASH_IS_FTFL (0)
<> 154:37f96f9d4de2 415 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
<> 154:37f96f9d4de2 416 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
<> 154:37f96f9d4de2 417 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
<> 154:37f96f9d4de2 418 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
<> 154:37f96f9d4de2 419 /* @brief Has EEPROM region protection (register FEPROT). */
<> 154:37f96f9d4de2 420 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
<> 154:37f96f9d4de2 421 /* @brief Has data flash region protection (register FDPROT). */
<> 154:37f96f9d4de2 422 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
<> 154:37f96f9d4de2 423 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
<> 154:37f96f9d4de2 424 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
<> 154:37f96f9d4de2 425 /* @brief Has flash cache control in FMC module. */
<> 154:37f96f9d4de2 426 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
<> 154:37f96f9d4de2 427 /* @brief Has flash cache control in MCM module. */
<> 154:37f96f9d4de2 428 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
<> 154:37f96f9d4de2 429 /* @brief Has flash cache control in MSCM module. */
<> 154:37f96f9d4de2 430 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
<> 154:37f96f9d4de2 431 /* @brief P-Flash start address. */
<> 154:37f96f9d4de2 432 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
<> 154:37f96f9d4de2 433 /* @brief P-Flash block count. */
<> 154:37f96f9d4de2 434 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
<> 154:37f96f9d4de2 435 /* @brief P-Flash block size. */
<> 154:37f96f9d4de2 436 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072)
<> 154:37f96f9d4de2 437 /* @brief P-Flash sector size. */
<> 154:37f96f9d4de2 438 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
<> 154:37f96f9d4de2 439 /* @brief P-Flash write unit size. */
<> 154:37f96f9d4de2 440 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
<> 154:37f96f9d4de2 441 /* @brief P-Flash data path width. */
<> 154:37f96f9d4de2 442 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
<> 154:37f96f9d4de2 443 /* @brief P-Flash block swap feature. */
<> 154:37f96f9d4de2 444 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
<> 154:37f96f9d4de2 445 /* @brief P-Flash protection region count. */
<> 154:37f96f9d4de2 446 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
<> 154:37f96f9d4de2 447 /* @brief Has FlexNVM memory. */
<> 154:37f96f9d4de2 448 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
<> 154:37f96f9d4de2 449 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
<> 154:37f96f9d4de2 450 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
<> 154:37f96f9d4de2 451 /* @brief FlexNVM block count. */
<> 154:37f96f9d4de2 452 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
<> 154:37f96f9d4de2 453 /* @brief FlexNVM block size. */
<> 154:37f96f9d4de2 454 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
<> 154:37f96f9d4de2 455 /* @brief FlexNVM sector size. */
<> 154:37f96f9d4de2 456 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
<> 154:37f96f9d4de2 457 /* @brief FlexNVM write unit size. */
<> 154:37f96f9d4de2 458 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
<> 154:37f96f9d4de2 459 /* @brief FlexNVM data path width. */
<> 154:37f96f9d4de2 460 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
<> 154:37f96f9d4de2 461 /* @brief Has FlexRAM memory. */
<> 154:37f96f9d4de2 462 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
<> 154:37f96f9d4de2 463 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
<> 154:37f96f9d4de2 464 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
<> 154:37f96f9d4de2 465 /* @brief FlexRAM size. */
<> 154:37f96f9d4de2 466 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
<> 154:37f96f9d4de2 467 /* @brief Has 0x00 Read 1s Block command. */
<> 154:37f96f9d4de2 468 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
<> 154:37f96f9d4de2 469 /* @brief Has 0x01 Read 1s Section command. */
<> 154:37f96f9d4de2 470 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
<> 154:37f96f9d4de2 471 /* @brief Has 0x02 Program Check command. */
<> 154:37f96f9d4de2 472 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
<> 154:37f96f9d4de2 473 /* @brief Has 0x03 Read Resource command. */
<> 154:37f96f9d4de2 474 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
<> 154:37f96f9d4de2 475 /* @brief Has 0x06 Program Longword command. */
<> 154:37f96f9d4de2 476 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
<> 154:37f96f9d4de2 477 /* @brief Has 0x07 Program Phrase command. */
<> 154:37f96f9d4de2 478 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
<> 154:37f96f9d4de2 479 /* @brief Has 0x08 Erase Flash Block command. */
<> 154:37f96f9d4de2 480 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
<> 154:37f96f9d4de2 481 /* @brief Has 0x09 Erase Flash Sector command. */
<> 154:37f96f9d4de2 482 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
<> 154:37f96f9d4de2 483 /* @brief Has 0x0B Program Section command. */
<> 154:37f96f9d4de2 484 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
<> 154:37f96f9d4de2 485 /* @brief Has 0x40 Read 1s All Blocks command. */
<> 154:37f96f9d4de2 486 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
<> 154:37f96f9d4de2 487 /* @brief Has 0x41 Read Once command. */
<> 154:37f96f9d4de2 488 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
<> 154:37f96f9d4de2 489 /* @brief Has 0x43 Program Once command. */
<> 154:37f96f9d4de2 490 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
<> 154:37f96f9d4de2 491 /* @brief Has 0x44 Erase All Blocks command. */
<> 154:37f96f9d4de2 492 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
<> 154:37f96f9d4de2 493 /* @brief Has 0x45 Verify Backdoor Access Key command. */
<> 154:37f96f9d4de2 494 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
<> 154:37f96f9d4de2 495 /* @brief Has 0x46 Swap Control command. */
<> 154:37f96f9d4de2 496 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
<> 154:37f96f9d4de2 497 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
<> 154:37f96f9d4de2 498 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
<> 154:37f96f9d4de2 499 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
<> 154:37f96f9d4de2 500 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
<> 154:37f96f9d4de2 501 /* @brief Has 0x4B Erase All Execute-only Segments command. */
<> 154:37f96f9d4de2 502 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
<> 154:37f96f9d4de2 503 /* @brief Has 0x80 Program Partition command. */
<> 154:37f96f9d4de2 504 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
<> 154:37f96f9d4de2 505 /* @brief Has 0x81 Set FlexRAM Function command. */
<> 154:37f96f9d4de2 506 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
<> 154:37f96f9d4de2 507 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
<> 154:37f96f9d4de2 508 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
<> 154:37f96f9d4de2 509 /* @brief P-Flash Erase sector command address alignment. */
<> 154:37f96f9d4de2 510 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
<> 154:37f96f9d4de2 511 /* @brief P-Flash Rrogram/Verify section command address alignment. */
<> 154:37f96f9d4de2 512 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
<> 154:37f96f9d4de2 513 /* @brief P-Flash Read resource command address alignment. */
<> 154:37f96f9d4de2 514 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
<> 154:37f96f9d4de2 515 /* @brief P-Flash Program check command address alignment. */
<> 154:37f96f9d4de2 516 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
<> 154:37f96f9d4de2 517 /* @brief P-Flash Program check command address alignment. */
<> 154:37f96f9d4de2 518 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
<> 154:37f96f9d4de2 519 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
<> 154:37f96f9d4de2 520 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
<> 154:37f96f9d4de2 521 /* @brief FlexNVM Erase sector command address alignment. */
<> 154:37f96f9d4de2 522 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
<> 154:37f96f9d4de2 523 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
<> 154:37f96f9d4de2 524 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
<> 154:37f96f9d4de2 525 /* @brief FlexNVM Read resource command address alignment. */
<> 154:37f96f9d4de2 526 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
<> 154:37f96f9d4de2 527 /* @brief FlexNVM Program check command address alignment. */
<> 154:37f96f9d4de2 528 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
<> 154:37f96f9d4de2 529 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 530 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
<> 154:37f96f9d4de2 531 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 532 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
<> 154:37f96f9d4de2 533 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 534 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
<> 154:37f96f9d4de2 535 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 536 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
<> 154:37f96f9d4de2 537 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 538 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
<> 154:37f96f9d4de2 539 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 540 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
<> 154:37f96f9d4de2 541 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 542 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
<> 154:37f96f9d4de2 543 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 544 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
<> 154:37f96f9d4de2 545 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 546 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
<> 154:37f96f9d4de2 547 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 548 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
<> 154:37f96f9d4de2 549 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 550 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
<> 154:37f96f9d4de2 551 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 552 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
<> 154:37f96f9d4de2 553 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 554 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
<> 154:37f96f9d4de2 555 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 556 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
<> 154:37f96f9d4de2 557 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 558 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
<> 154:37f96f9d4de2 559 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 560 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
<> 154:37f96f9d4de2 561 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 562 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
<> 154:37f96f9d4de2 563 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 564 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
<> 154:37f96f9d4de2 565 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 566 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
<> 154:37f96f9d4de2 567 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 568 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
<> 154:37f96f9d4de2 569 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 570 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
<> 154:37f96f9d4de2 571 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 572 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
<> 154:37f96f9d4de2 573 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 574 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
<> 154:37f96f9d4de2 575 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 576 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
<> 154:37f96f9d4de2 577 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 578 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
<> 154:37f96f9d4de2 579 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 580 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
<> 154:37f96f9d4de2 581 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 582 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
<> 154:37f96f9d4de2 583 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 584 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
<> 154:37f96f9d4de2 585 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 586 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
<> 154:37f96f9d4de2 587 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 588 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
<> 154:37f96f9d4de2 589 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 590 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
<> 154:37f96f9d4de2 591 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 592 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
<> 154:37f96f9d4de2 593 #elif defined(CPU_MKW41Z512VHT4)
<> 154:37f96f9d4de2 594 /* @brief Is of type FTFA. */
<> 154:37f96f9d4de2 595 #define FSL_FEATURE_FLASH_IS_FTFA (1)
<> 154:37f96f9d4de2 596 /* @brief Is of type FTFE. */
<> 154:37f96f9d4de2 597 #define FSL_FEATURE_FLASH_IS_FTFE (0)
<> 154:37f96f9d4de2 598 /* @brief Is of type FTFL. */
<> 154:37f96f9d4de2 599 #define FSL_FEATURE_FLASH_IS_FTFL (0)
<> 154:37f96f9d4de2 600 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
<> 154:37f96f9d4de2 601 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
<> 154:37f96f9d4de2 602 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
<> 154:37f96f9d4de2 603 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
<> 154:37f96f9d4de2 604 /* @brief Has EEPROM region protection (register FEPROT). */
<> 154:37f96f9d4de2 605 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
<> 154:37f96f9d4de2 606 /* @brief Has data flash region protection (register FDPROT). */
<> 154:37f96f9d4de2 607 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
<> 154:37f96f9d4de2 608 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
<> 154:37f96f9d4de2 609 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
<> 154:37f96f9d4de2 610 /* @brief Has flash cache control in FMC module. */
<> 154:37f96f9d4de2 611 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
<> 154:37f96f9d4de2 612 /* @brief Has flash cache control in MCM module. */
<> 154:37f96f9d4de2 613 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
<> 154:37f96f9d4de2 614 /* @brief Has flash cache control in MSCM module. */
<> 154:37f96f9d4de2 615 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
<> 154:37f96f9d4de2 616 /* @brief P-Flash start address. */
<> 154:37f96f9d4de2 617 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
<> 154:37f96f9d4de2 618 /* @brief P-Flash block count. */
<> 154:37f96f9d4de2 619 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
<> 154:37f96f9d4de2 620 /* @brief P-Flash block size. */
<> 154:37f96f9d4de2 621 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144)
<> 154:37f96f9d4de2 622 /* @brief P-Flash sector size. */
<> 154:37f96f9d4de2 623 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
<> 154:37f96f9d4de2 624 /* @brief P-Flash write unit size. */
<> 154:37f96f9d4de2 625 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
<> 154:37f96f9d4de2 626 /* @brief P-Flash data path width. */
<> 154:37f96f9d4de2 627 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
<> 154:37f96f9d4de2 628 /* @brief P-Flash block swap feature. */
<> 154:37f96f9d4de2 629 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
<> 154:37f96f9d4de2 630 /* @brief P-Flash protection region count. */
<> 154:37f96f9d4de2 631 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
<> 154:37f96f9d4de2 632 /* @brief Has FlexNVM memory. */
<> 154:37f96f9d4de2 633 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
<> 154:37f96f9d4de2 634 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
<> 154:37f96f9d4de2 635 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
<> 154:37f96f9d4de2 636 /* @brief FlexNVM block count. */
<> 154:37f96f9d4de2 637 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
<> 154:37f96f9d4de2 638 /* @brief FlexNVM block size. */
<> 154:37f96f9d4de2 639 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
<> 154:37f96f9d4de2 640 /* @brief FlexNVM sector size. */
<> 154:37f96f9d4de2 641 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
<> 154:37f96f9d4de2 642 /* @brief FlexNVM write unit size. */
<> 154:37f96f9d4de2 643 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
<> 154:37f96f9d4de2 644 /* @brief FlexNVM data path width. */
<> 154:37f96f9d4de2 645 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
<> 154:37f96f9d4de2 646 /* @brief Has FlexRAM memory. */
<> 154:37f96f9d4de2 647 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
<> 154:37f96f9d4de2 648 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
<> 154:37f96f9d4de2 649 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
<> 154:37f96f9d4de2 650 /* @brief FlexRAM size. */
<> 154:37f96f9d4de2 651 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
<> 154:37f96f9d4de2 652 /* @brief Has 0x00 Read 1s Block command. */
<> 154:37f96f9d4de2 653 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
<> 154:37f96f9d4de2 654 /* @brief Has 0x01 Read 1s Section command. */
<> 154:37f96f9d4de2 655 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
<> 154:37f96f9d4de2 656 /* @brief Has 0x02 Program Check command. */
<> 154:37f96f9d4de2 657 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
<> 154:37f96f9d4de2 658 /* @brief Has 0x03 Read Resource command. */
<> 154:37f96f9d4de2 659 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
<> 154:37f96f9d4de2 660 /* @brief Has 0x06 Program Longword command. */
<> 154:37f96f9d4de2 661 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
<> 154:37f96f9d4de2 662 /* @brief Has 0x07 Program Phrase command. */
<> 154:37f96f9d4de2 663 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
<> 154:37f96f9d4de2 664 /* @brief Has 0x08 Erase Flash Block command. */
<> 154:37f96f9d4de2 665 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
<> 154:37f96f9d4de2 666 /* @brief Has 0x09 Erase Flash Sector command. */
<> 154:37f96f9d4de2 667 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
<> 154:37f96f9d4de2 668 /* @brief Has 0x0B Program Section command. */
<> 154:37f96f9d4de2 669 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
<> 154:37f96f9d4de2 670 /* @brief Has 0x40 Read 1s All Blocks command. */
<> 154:37f96f9d4de2 671 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
<> 154:37f96f9d4de2 672 /* @brief Has 0x41 Read Once command. */
<> 154:37f96f9d4de2 673 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
<> 154:37f96f9d4de2 674 /* @brief Has 0x43 Program Once command. */
<> 154:37f96f9d4de2 675 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
<> 154:37f96f9d4de2 676 /* @brief Has 0x44 Erase All Blocks command. */
<> 154:37f96f9d4de2 677 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
<> 154:37f96f9d4de2 678 /* @brief Has 0x45 Verify Backdoor Access Key command. */
<> 154:37f96f9d4de2 679 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
<> 154:37f96f9d4de2 680 /* @brief Has 0x46 Swap Control command. */
<> 154:37f96f9d4de2 681 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
<> 154:37f96f9d4de2 682 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
<> 154:37f96f9d4de2 683 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
<> 154:37f96f9d4de2 684 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
<> 154:37f96f9d4de2 685 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
<> 154:37f96f9d4de2 686 /* @brief Has 0x4B Erase All Execute-only Segments command. */
<> 154:37f96f9d4de2 687 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
<> 154:37f96f9d4de2 688 /* @brief Has 0x80 Program Partition command. */
<> 154:37f96f9d4de2 689 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
<> 154:37f96f9d4de2 690 /* @brief Has 0x81 Set FlexRAM Function command. */
<> 154:37f96f9d4de2 691 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
<> 154:37f96f9d4de2 692 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
<> 154:37f96f9d4de2 693 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
<> 154:37f96f9d4de2 694 /* @brief P-Flash Erase sector command address alignment. */
<> 154:37f96f9d4de2 695 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
<> 154:37f96f9d4de2 696 /* @brief P-Flash Rrogram/Verify section command address alignment. */
<> 154:37f96f9d4de2 697 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
<> 154:37f96f9d4de2 698 /* @brief P-Flash Read resource command address alignment. */
<> 154:37f96f9d4de2 699 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
<> 154:37f96f9d4de2 700 /* @brief P-Flash Program check command address alignment. */
<> 154:37f96f9d4de2 701 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
<> 154:37f96f9d4de2 702 /* @brief P-Flash Program check command address alignment. */
<> 154:37f96f9d4de2 703 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
<> 154:37f96f9d4de2 704 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
<> 154:37f96f9d4de2 705 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
<> 154:37f96f9d4de2 706 /* @brief FlexNVM Erase sector command address alignment. */
<> 154:37f96f9d4de2 707 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
<> 154:37f96f9d4de2 708 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
<> 154:37f96f9d4de2 709 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
<> 154:37f96f9d4de2 710 /* @brief FlexNVM Read resource command address alignment. */
<> 154:37f96f9d4de2 711 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
<> 154:37f96f9d4de2 712 /* @brief FlexNVM Program check command address alignment. */
<> 154:37f96f9d4de2 713 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
<> 154:37f96f9d4de2 714 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 715 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
<> 154:37f96f9d4de2 716 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 717 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
<> 154:37f96f9d4de2 718 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 719 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
<> 154:37f96f9d4de2 720 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 721 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
<> 154:37f96f9d4de2 722 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 723 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
<> 154:37f96f9d4de2 724 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 725 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
<> 154:37f96f9d4de2 726 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 727 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
<> 154:37f96f9d4de2 728 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 729 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
<> 154:37f96f9d4de2 730 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 731 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
<> 154:37f96f9d4de2 732 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 733 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
<> 154:37f96f9d4de2 734 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 735 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
<> 154:37f96f9d4de2 736 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 737 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
<> 154:37f96f9d4de2 738 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 739 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
<> 154:37f96f9d4de2 740 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 741 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
<> 154:37f96f9d4de2 742 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 743 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
<> 154:37f96f9d4de2 744 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
<> 154:37f96f9d4de2 745 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
<> 154:37f96f9d4de2 746 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 747 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
<> 154:37f96f9d4de2 748 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 749 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
<> 154:37f96f9d4de2 750 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 751 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
<> 154:37f96f9d4de2 752 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 753 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
<> 154:37f96f9d4de2 754 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 755 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
<> 154:37f96f9d4de2 756 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 757 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
<> 154:37f96f9d4de2 758 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 759 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
<> 154:37f96f9d4de2 760 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 761 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
<> 154:37f96f9d4de2 762 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 763 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
<> 154:37f96f9d4de2 764 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 765 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
<> 154:37f96f9d4de2 766 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 767 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
<> 154:37f96f9d4de2 768 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 769 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
<> 154:37f96f9d4de2 770 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 771 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
<> 154:37f96f9d4de2 772 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 773 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
<> 154:37f96f9d4de2 774 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 775 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
<> 154:37f96f9d4de2 776 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
<> 154:37f96f9d4de2 777 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
<> 154:37f96f9d4de2 778 #endif /* defined(CPU_MKW41Z256VHT4) */
<> 154:37f96f9d4de2 779
<> 154:37f96f9d4de2 780 /* GPIO module features */
<> 154:37f96f9d4de2 781
<> 154:37f96f9d4de2 782 /* @brief Has fast (single cycle) access capability via a dedicated memory region. */
<> 154:37f96f9d4de2 783 #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1)
<> 154:37f96f9d4de2 784 /* @brief Has port input disable register (PIDR). */
<> 154:37f96f9d4de2 785 #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
<> 154:37f96f9d4de2 786 /* @brief Has dedicated interrupt vector. */
<> 154:37f96f9d4de2 787 #define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
<> 154:37f96f9d4de2 788
<> 154:37f96f9d4de2 789 /* I2C module features */
<> 154:37f96f9d4de2 790
<> 154:37f96f9d4de2 791 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
<> 154:37f96f9d4de2 792 #define FSL_FEATURE_I2C_HAS_SMBUS (1)
<> 154:37f96f9d4de2 793 /* @brief Maximum supported baud rate in kilobit per second. */
<> 154:37f96f9d4de2 794 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
<> 154:37f96f9d4de2 795 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
<> 154:37f96f9d4de2 796 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
<> 154:37f96f9d4de2 797 /* @brief Has DMA support (register bit C1[DMAEN]). */
<> 154:37f96f9d4de2 798 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
<> 154:37f96f9d4de2 799 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
<> 154:37f96f9d4de2 800 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
<> 154:37f96f9d4de2 801 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
<> 154:37f96f9d4de2 802 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
<> 154:37f96f9d4de2 803 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
<> 154:37f96f9d4de2 804 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
<> 154:37f96f9d4de2 805 /* @brief Maximum width of the glitch filter in number of bus clocks. */
<> 154:37f96f9d4de2 806 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
<> 154:37f96f9d4de2 807 /* @brief Has control of the drive capability of the I2C pins. */
<> 154:37f96f9d4de2 808 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
<> 154:37f96f9d4de2 809 /* @brief Has double buffering support (register S2). */
<> 154:37f96f9d4de2 810 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1)
<> 154:37f96f9d4de2 811 /* @brief Has double buffer enable. */
<> 154:37f96f9d4de2 812 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (1)
<> 154:37f96f9d4de2 813
<> 154:37f96f9d4de2 814 /* LLWU module features */
<> 154:37f96f9d4de2 815
<> 154:37f96f9d4de2 816 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
<> 154:37f96f9d4de2 817 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
<> 154:37f96f9d4de2 818 /* @brief Has pins 8-15 connected to LLWU device. */
<> 154:37f96f9d4de2 819 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
<> 154:37f96f9d4de2 820 /* @brief Maximum number of internal modules connected to LLWU device. */
<> 154:37f96f9d4de2 821 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
<> 154:37f96f9d4de2 822 /* @brief Number of digital filters. */
<> 154:37f96f9d4de2 823 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
<> 154:37f96f9d4de2 824 /* @brief Has MF register. */
<> 154:37f96f9d4de2 825 #define FSL_FEATURE_LLWU_HAS_MF (0)
<> 154:37f96f9d4de2 826 /* @brief Has PF register. */
<> 154:37f96f9d4de2 827 #define FSL_FEATURE_LLWU_HAS_PF (0)
<> 154:37f96f9d4de2 828 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
<> 154:37f96f9d4de2 829 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
<> 154:37f96f9d4de2 830 /* @brief Has external pin 0 connected to LLWU device. */
<> 154:37f96f9d4de2 831 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
<> 154:37f96f9d4de2 832 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 833 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX)
<> 154:37f96f9d4de2 834 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 835 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16)
<> 154:37f96f9d4de2 836 /* @brief Has external pin 1 connected to LLWU device. */
<> 154:37f96f9d4de2 837 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
<> 154:37f96f9d4de2 838 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 839 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX)
<> 154:37f96f9d4de2 840 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 841 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17)
<> 154:37f96f9d4de2 842 /* @brief Has external pin 2 connected to LLWU device. */
<> 154:37f96f9d4de2 843 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
<> 154:37f96f9d4de2 844 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 845 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX)
<> 154:37f96f9d4de2 846 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 847 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18)
<> 154:37f96f9d4de2 848 /* @brief Has external pin 3 connected to LLWU device. */
<> 154:37f96f9d4de2 849 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
<> 154:37f96f9d4de2 850 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 851 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX)
<> 154:37f96f9d4de2 852 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 853 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19)
<> 154:37f96f9d4de2 854 /* @brief Has external pin 4 connected to LLWU device. */
<> 154:37f96f9d4de2 855 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
<> 154:37f96f9d4de2 856 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 857 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
<> 154:37f96f9d4de2 858 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 859 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16)
<> 154:37f96f9d4de2 860 /* @brief Has external pin 5 connected to LLWU device. */
<> 154:37f96f9d4de2 861 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
<> 154:37f96f9d4de2 862 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 863 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX)
<> 154:37f96f9d4de2 864 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 865 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17)
<> 154:37f96f9d4de2 866 /* @brief Has external pin 6 connected to LLWU device. */
<> 154:37f96f9d4de2 867 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
<> 154:37f96f9d4de2 868 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 869 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX)
<> 154:37f96f9d4de2 870 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 871 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18)
<> 154:37f96f9d4de2 872 /* @brief Has external pin 7 connected to LLWU device. */
<> 154:37f96f9d4de2 873 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
<> 154:37f96f9d4de2 874 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 875 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX)
<> 154:37f96f9d4de2 876 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 877 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19)
<> 154:37f96f9d4de2 878 /* @brief Has external pin 8 connected to LLWU device. */
<> 154:37f96f9d4de2 879 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
<> 154:37f96f9d4de2 880 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 881 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX)
<> 154:37f96f9d4de2 882 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 883 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0)
<> 154:37f96f9d4de2 884 /* @brief Has external pin 9 connected to LLWU device. */
<> 154:37f96f9d4de2 885 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (0)
<> 154:37f96f9d4de2 886 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 887 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (0)
<> 154:37f96f9d4de2 888 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 889 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0)
<> 154:37f96f9d4de2 890 /* @brief Has external pin 10 connected to LLWU device. */
<> 154:37f96f9d4de2 891 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
<> 154:37f96f9d4de2 892 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 893 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
<> 154:37f96f9d4de2 894 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 895 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2)
<> 154:37f96f9d4de2 896 /* @brief Has external pin 11 connected to LLWU device. */
<> 154:37f96f9d4de2 897 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
<> 154:37f96f9d4de2 898 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 899 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
<> 154:37f96f9d4de2 900 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 901 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3)
<> 154:37f96f9d4de2 902 /* @brief Has external pin 12 connected to LLWU device. */
<> 154:37f96f9d4de2 903 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
<> 154:37f96f9d4de2 904 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 905 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX)
<> 154:37f96f9d4de2 906 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 907 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4)
<> 154:37f96f9d4de2 908 /* @brief Has external pin 13 connected to LLWU device. */
<> 154:37f96f9d4de2 909 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
<> 154:37f96f9d4de2 910 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 911 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX)
<> 154:37f96f9d4de2 912 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 913 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5)
<> 154:37f96f9d4de2 914 /* @brief Has external pin 14 connected to LLWU device. */
<> 154:37f96f9d4de2 915 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
<> 154:37f96f9d4de2 916 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 917 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX)
<> 154:37f96f9d4de2 918 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 919 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6)
<> 154:37f96f9d4de2 920 /* @brief Has external pin 15 connected to LLWU device. */
<> 154:37f96f9d4de2 921 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
<> 154:37f96f9d4de2 922 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 923 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX)
<> 154:37f96f9d4de2 924 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 925 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7)
<> 154:37f96f9d4de2 926 /* @brief Has external pin 16 connected to LLWU device. */
<> 154:37f96f9d4de2 927 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
<> 154:37f96f9d4de2 928 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 929 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
<> 154:37f96f9d4de2 930 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 931 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
<> 154:37f96f9d4de2 932 /* @brief Has external pin 17 connected to LLWU device. */
<> 154:37f96f9d4de2 933 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
<> 154:37f96f9d4de2 934 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 935 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
<> 154:37f96f9d4de2 936 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 937 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
<> 154:37f96f9d4de2 938 /* @brief Has external pin 18 connected to LLWU device. */
<> 154:37f96f9d4de2 939 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
<> 154:37f96f9d4de2 940 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 941 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
<> 154:37f96f9d4de2 942 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 943 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
<> 154:37f96f9d4de2 944 /* @brief Has external pin 19 connected to LLWU device. */
<> 154:37f96f9d4de2 945 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
<> 154:37f96f9d4de2 946 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 947 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
<> 154:37f96f9d4de2 948 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 949 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
<> 154:37f96f9d4de2 950 /* @brief Has external pin 20 connected to LLWU device. */
<> 154:37f96f9d4de2 951 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
<> 154:37f96f9d4de2 952 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 953 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
<> 154:37f96f9d4de2 954 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 955 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
<> 154:37f96f9d4de2 956 /* @brief Has external pin 21 connected to LLWU device. */
<> 154:37f96f9d4de2 957 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
<> 154:37f96f9d4de2 958 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 959 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
<> 154:37f96f9d4de2 960 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 961 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
<> 154:37f96f9d4de2 962 /* @brief Has external pin 22 connected to LLWU device. */
<> 154:37f96f9d4de2 963 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
<> 154:37f96f9d4de2 964 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 965 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
<> 154:37f96f9d4de2 966 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 967 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
<> 154:37f96f9d4de2 968 /* @brief Has external pin 23 connected to LLWU device. */
<> 154:37f96f9d4de2 969 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
<> 154:37f96f9d4de2 970 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 971 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
<> 154:37f96f9d4de2 972 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 973 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
<> 154:37f96f9d4de2 974 /* @brief Has external pin 24 connected to LLWU device. */
<> 154:37f96f9d4de2 975 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
<> 154:37f96f9d4de2 976 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 977 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
<> 154:37f96f9d4de2 978 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 979 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
<> 154:37f96f9d4de2 980 /* @brief Has external pin 25 connected to LLWU device. */
<> 154:37f96f9d4de2 981 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
<> 154:37f96f9d4de2 982 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 983 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
<> 154:37f96f9d4de2 984 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 985 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
<> 154:37f96f9d4de2 986 /* @brief Has external pin 26 connected to LLWU device. */
<> 154:37f96f9d4de2 987 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
<> 154:37f96f9d4de2 988 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 989 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
<> 154:37f96f9d4de2 990 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 991 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
<> 154:37f96f9d4de2 992 /* @brief Has external pin 27 connected to LLWU device. */
<> 154:37f96f9d4de2 993 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
<> 154:37f96f9d4de2 994 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 995 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
<> 154:37f96f9d4de2 996 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 997 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
<> 154:37f96f9d4de2 998 /* @brief Has external pin 28 connected to LLWU device. */
<> 154:37f96f9d4de2 999 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
<> 154:37f96f9d4de2 1000 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 1001 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
<> 154:37f96f9d4de2 1002 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 1003 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
<> 154:37f96f9d4de2 1004 /* @brief Has external pin 29 connected to LLWU device. */
<> 154:37f96f9d4de2 1005 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
<> 154:37f96f9d4de2 1006 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 1007 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
<> 154:37f96f9d4de2 1008 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 1009 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
<> 154:37f96f9d4de2 1010 /* @brief Has external pin 30 connected to LLWU device. */
<> 154:37f96f9d4de2 1011 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
<> 154:37f96f9d4de2 1012 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 1013 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
<> 154:37f96f9d4de2 1014 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 1015 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
<> 154:37f96f9d4de2 1016 /* @brief Has external pin 31 connected to LLWU device. */
<> 154:37f96f9d4de2 1017 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
<> 154:37f96f9d4de2 1018 /* @brief Index of port of external pin. */
<> 154:37f96f9d4de2 1019 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
<> 154:37f96f9d4de2 1020 /* @brief Number of external pin port on specified port. */
<> 154:37f96f9d4de2 1021 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
<> 154:37f96f9d4de2 1022 /* @brief Has internal module 0 connected to LLWU device. */
<> 154:37f96f9d4de2 1023 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
<> 154:37f96f9d4de2 1024 /* @brief Has internal module 1 connected to LLWU device. */
<> 154:37f96f9d4de2 1025 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
<> 154:37f96f9d4de2 1026 /* @brief Has internal module 2 connected to LLWU device. */
<> 154:37f96f9d4de2 1027 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
<> 154:37f96f9d4de2 1028 /* @brief Has internal module 3 connected to LLWU device. */
<> 154:37f96f9d4de2 1029 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
<> 154:37f96f9d4de2 1030 /* @brief Has internal module 4 connected to LLWU device. */
<> 154:37f96f9d4de2 1031 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
<> 154:37f96f9d4de2 1032 /* @brief Has internal module 5 connected to LLWU device. */
<> 154:37f96f9d4de2 1033 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
<> 154:37f96f9d4de2 1034 /* @brief Has internal module 6 connected to LLWU device. */
<> 154:37f96f9d4de2 1035 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
<> 154:37f96f9d4de2 1036 /* @brief Has internal module 7 connected to LLWU device. */
<> 154:37f96f9d4de2 1037 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
<> 154:37f96f9d4de2 1038 /* @brief Has Version ID Register (LLWU_VERID). */
<> 154:37f96f9d4de2 1039 #define FSL_FEATURE_LLWU_HAS_VERID (0)
<> 154:37f96f9d4de2 1040 /* @brief Has Parameter Register (LLWU_PARAM). */
<> 154:37f96f9d4de2 1041 #define FSL_FEATURE_LLWU_HAS_PARAM (0)
<> 154:37f96f9d4de2 1042 /* @brief Width of registers of the LLWU. */
<> 154:37f96f9d4de2 1043 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
<> 154:37f96f9d4de2 1044 /* @brief Has DMA Enable register (LLWU_DE). */
<> 154:37f96f9d4de2 1045 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
<> 154:37f96f9d4de2 1046
<> 154:37f96f9d4de2 1047 /* LPTMR module features */
<> 154:37f96f9d4de2 1048
<> 154:37f96f9d4de2 1049 /* @brief Has shared interrupt handler with another LPTMR module. */
<> 154:37f96f9d4de2 1050 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
<> 154:37f96f9d4de2 1051
<> 154:37f96f9d4de2 1052 /* LPUART module features */
<> 154:37f96f9d4de2 1053
<> 154:37f96f9d4de2 1054 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
<> 154:37f96f9d4de2 1055 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
<> 154:37f96f9d4de2 1056 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
<> 154:37f96f9d4de2 1057 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
<> 154:37f96f9d4de2 1058 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
<> 154:37f96f9d4de2 1059 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
<> 154:37f96f9d4de2 1060 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
<> 154:37f96f9d4de2 1061 #define FSL_FEATURE_LPUART_HAS_FIFO (0)
<> 154:37f96f9d4de2 1062 /* @brief Has 32-bit register MODIR */
<> 154:37f96f9d4de2 1063 #define FSL_FEATURE_LPUART_HAS_MODIR (1)
<> 154:37f96f9d4de2 1064 /* @brief Hardware flow control (RTS, CTS) is supported. */
<> 154:37f96f9d4de2 1065 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
<> 154:37f96f9d4de2 1066 /* @brief Infrared (modulation) is supported. */
<> 154:37f96f9d4de2 1067 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
<> 154:37f96f9d4de2 1068 /* @brief 2 bits long stop bit is available. */
<> 154:37f96f9d4de2 1069 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
<> 154:37f96f9d4de2 1070 /* @brief If 10-bit mode is supported. */
<> 154:37f96f9d4de2 1071 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
<> 154:37f96f9d4de2 1072 /* @brief If 7-bit mode is supported. */
<> 154:37f96f9d4de2 1073 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0)
<> 154:37f96f9d4de2 1074 /* @brief Baud rate fine adjustment is available. */
<> 154:37f96f9d4de2 1075 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
<> 154:37f96f9d4de2 1076 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
<> 154:37f96f9d4de2 1077 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
<> 154:37f96f9d4de2 1078 /* @brief Baud rate oversampling is available. */
<> 154:37f96f9d4de2 1079 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
<> 154:37f96f9d4de2 1080 /* @brief Baud rate oversampling is available. */
<> 154:37f96f9d4de2 1081 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
<> 154:37f96f9d4de2 1082 /* @brief Peripheral type. */
<> 154:37f96f9d4de2 1083 #define FSL_FEATURE_LPUART_IS_SCI (1)
<> 154:37f96f9d4de2 1084 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
<> 154:37f96f9d4de2 1085 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0)
<> 154:37f96f9d4de2 1086 /* @brief Maximal data width without parity bit. */
<> 154:37f96f9d4de2 1087 #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
<> 154:37f96f9d4de2 1088 /* @brief Maximal data width with parity bit. */
<> 154:37f96f9d4de2 1089 #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
<> 154:37f96f9d4de2 1090 /* @brief Supports two match addresses to filter incoming frames. */
<> 154:37f96f9d4de2 1091 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
<> 154:37f96f9d4de2 1092 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
<> 154:37f96f9d4de2 1093 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
<> 154:37f96f9d4de2 1094 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
<> 154:37f96f9d4de2 1095 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
<> 154:37f96f9d4de2 1096 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
<> 154:37f96f9d4de2 1097 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
<> 154:37f96f9d4de2 1098 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
<> 154:37f96f9d4de2 1099 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
<> 154:37f96f9d4de2 1100 /* @brief Has improved smart card (ISO7816 protocol) support. */
<> 154:37f96f9d4de2 1101 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
<> 154:37f96f9d4de2 1102 /* @brief Has local operation network (CEA709.1-B protocol) support. */
<> 154:37f96f9d4de2 1103 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
<> 154:37f96f9d4de2 1104 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
<> 154:37f96f9d4de2 1105 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
<> 154:37f96f9d4de2 1106 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
<> 154:37f96f9d4de2 1107 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
<> 154:37f96f9d4de2 1108 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
<> 154:37f96f9d4de2 1109 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
<> 154:37f96f9d4de2 1110 /* @brief Has separate DMA RX and TX requests. */
<> 154:37f96f9d4de2 1111 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
<> 154:37f96f9d4de2 1112 /* @brief Has separate RX and TX interrupts. */
<> 154:37f96f9d4de2 1113 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
<> 154:37f96f9d4de2 1114 /* @brief Has LPAURT_PARAM. */
<> 154:37f96f9d4de2 1115 #define FSL_FEATURE_LPUART_HAS_PARAM (0)
<> 154:37f96f9d4de2 1116 /* @brief Has LPUART_VERID. */
<> 154:37f96f9d4de2 1117 #define FSL_FEATURE_LPUART_HAS_VERID (0)
<> 154:37f96f9d4de2 1118 /* @brief Has LPUART_GLOBAL. */
<> 154:37f96f9d4de2 1119 #define FSL_FEATURE_LPUART_HAS_GLOBAL (0)
<> 154:37f96f9d4de2 1120 /* @brief Has LPUART_PINCFG. */
<> 154:37f96f9d4de2 1121 #define FSL_FEATURE_LPUART_HAS_PINCFG (0)
<> 154:37f96f9d4de2 1122
<> 154:37f96f9d4de2 1123 /* LTC module features */
<> 154:37f96f9d4de2 1124
<> 154:37f96f9d4de2 1125 /* @brief LTC module supports DES algorithm. */
<> 154:37f96f9d4de2 1126 #define FSL_FEATURE_LTC_HAS_DES (0)
<> 154:37f96f9d4de2 1127 /* @brief LTC module supports PKHA algorithm. */
<> 154:37f96f9d4de2 1128 #define FSL_FEATURE_LTC_HAS_PKHA (0)
<> 154:37f96f9d4de2 1129 /* @brief LTC module supports SHA algorithm. */
<> 154:37f96f9d4de2 1130 #define FSL_FEATURE_LTC_HAS_SHA (0)
<> 154:37f96f9d4de2 1131 /* @brief LTC module supports AES GCM mode. */
<> 154:37f96f9d4de2 1132 #define FSL_FEATURE_LTC_HAS_GCM (0)
<> 154:37f96f9d4de2 1133 /* @brief LTC module supports DPAMS registers. */
<> 154:37f96f9d4de2 1134 #define FSL_FEATURE_LTC_HAS_DPAMS (0)
<> 154:37f96f9d4de2 1135 /* @brief LTC module supports AES with 24 bytes key. */
<> 154:37f96f9d4de2 1136 #define FSL_FEATURE_LTC_HAS_AES192 (0)
<> 154:37f96f9d4de2 1137 /* @brief LTC module supports AES with 32 bytes key. */
<> 154:37f96f9d4de2 1138 #define FSL_FEATURE_LTC_HAS_AES256 (0)
<> 154:37f96f9d4de2 1139
<> 154:37f96f9d4de2 1140 /* MCG module features */
<> 154:37f96f9d4de2 1141
<> 154:37f96f9d4de2 1142 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
<> 154:37f96f9d4de2 1143 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0)
<> 154:37f96f9d4de2 1144 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
<> 154:37f96f9d4de2 1145 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0)
<> 154:37f96f9d4de2 1146 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
<> 154:37f96f9d4de2 1147 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0)
<> 154:37f96f9d4de2 1148 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */
<> 154:37f96f9d4de2 1149 #define FSL_FEATURE_MCG_PLL_REF_MIN (0)
<> 154:37f96f9d4de2 1150 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */
<> 154:37f96f9d4de2 1151 #define FSL_FEATURE_MCG_PLL_REF_MAX (0)
<> 154:37f96f9d4de2 1152 /* @brief The PLL clock is divided by 2 before VCO divider. */
<> 154:37f96f9d4de2 1153 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
<> 154:37f96f9d4de2 1154 /* @brief FRDIV supports 1280. */
<> 154:37f96f9d4de2 1155 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
<> 154:37f96f9d4de2 1156 /* @brief FRDIV supports 1536. */
<> 154:37f96f9d4de2 1157 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
<> 154:37f96f9d4de2 1158 /* @brief MCGFFCLK divider. */
<> 154:37f96f9d4de2 1159 #define FSL_FEATURE_MCG_FFCLK_DIV (1)
<> 154:37f96f9d4de2 1160 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
<> 154:37f96f9d4de2 1161 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
<> 154:37f96f9d4de2 1162 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
<> 154:37f96f9d4de2 1163 #define FSL_FEATURE_MCG_HAS_RTC_32K (1)
<> 154:37f96f9d4de2 1164 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
<> 154:37f96f9d4de2 1165 #define FSL_FEATURE_MCG_HAS_PLL1 (0)
<> 154:37f96f9d4de2 1166 /* @brief Has 48MHz internal oscillator. */
<> 154:37f96f9d4de2 1167 #define FSL_FEATURE_MCG_HAS_IRC_48M (0)
<> 154:37f96f9d4de2 1168 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
<> 154:37f96f9d4de2 1169 #define FSL_FEATURE_MCG_HAS_OSC1 (0)
<> 154:37f96f9d4de2 1170 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
<> 154:37f96f9d4de2 1171 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
<> 154:37f96f9d4de2 1172 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
<> 154:37f96f9d4de2 1173 #define FSL_FEATURE_MCG_HAS_LOLRE (0)
<> 154:37f96f9d4de2 1174 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
<> 154:37f96f9d4de2 1175 #define FSL_FEATURE_MCG_USE_OSCSEL (1)
<> 154:37f96f9d4de2 1176 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
<> 154:37f96f9d4de2 1177 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
<> 154:37f96f9d4de2 1178 /* @brief TBD */
<> 154:37f96f9d4de2 1179 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
<> 154:37f96f9d4de2 1180 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
<> 154:37f96f9d4de2 1181 #define FSL_FEATURE_MCG_HAS_PLL (0)
<> 154:37f96f9d4de2 1182 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
<> 154:37f96f9d4de2 1183 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0)
<> 154:37f96f9d4de2 1184 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
<> 154:37f96f9d4de2 1185 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (0)
<> 154:37f96f9d4de2 1186 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
<> 154:37f96f9d4de2 1187 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
<> 154:37f96f9d4de2 1188 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
<> 154:37f96f9d4de2 1189 #define FSL_FEATURE_MCG_HAS_FLL (1)
<> 154:37f96f9d4de2 1190 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
<> 154:37f96f9d4de2 1191 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
<> 154:37f96f9d4de2 1192 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
<> 154:37f96f9d4de2 1193 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
<> 154:37f96f9d4de2 1194 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
<> 154:37f96f9d4de2 1195 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0)
<> 154:37f96f9d4de2 1196 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
<> 154:37f96f9d4de2 1197 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
<> 154:37f96f9d4de2 1198 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
<> 154:37f96f9d4de2 1199 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
<> 154:37f96f9d4de2 1200 /* @brief Has external clock monitor (register bit C6[CME]). */
<> 154:37f96f9d4de2 1201 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
<> 154:37f96f9d4de2 1202 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
<> 154:37f96f9d4de2 1203 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
<> 154:37f96f9d4de2 1204 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
<> 154:37f96f9d4de2 1205 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
<> 154:37f96f9d4de2 1206 /* @brief Has PEI mode or PBI mode. */
<> 154:37f96f9d4de2 1207 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
<> 154:37f96f9d4de2 1208 /* @brief Reset clock mode is BLPI. */
<> 154:37f96f9d4de2 1209 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
<> 154:37f96f9d4de2 1210
<> 154:37f96f9d4de2 1211 /* interrupt module features */
<> 154:37f96f9d4de2 1212
<> 154:37f96f9d4de2 1213 /* @brief Lowest interrupt request number. */
<> 154:37f96f9d4de2 1214 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
<> 154:37f96f9d4de2 1215 /* @brief Highest interrupt request number. */
<> 154:37f96f9d4de2 1216 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
<> 154:37f96f9d4de2 1217
<> 154:37f96f9d4de2 1218 /* PIT module features */
<> 154:37f96f9d4de2 1219
<> 154:37f96f9d4de2 1220 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
<> 154:37f96f9d4de2 1221 #define FSL_FEATURE_PIT_TIMER_COUNT (2)
<> 154:37f96f9d4de2 1222 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
<> 154:37f96f9d4de2 1223 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
<> 154:37f96f9d4de2 1224 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
<> 154:37f96f9d4de2 1225 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
<> 154:37f96f9d4de2 1226 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
<> 154:37f96f9d4de2 1227 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
<> 154:37f96f9d4de2 1228
<> 154:37f96f9d4de2 1229 /* PMC module features */
<> 154:37f96f9d4de2 1230
<> 154:37f96f9d4de2 1231 /* @brief Has Bandgap Enable In VLPx Operation support. */
<> 154:37f96f9d4de2 1232 #define FSL_FEATURE_PMC_HAS_BGEN (0)
<> 154:37f96f9d4de2 1233 /* @brief Has Bandgap Buffer Enable. */
<> 154:37f96f9d4de2 1234 #define FSL_FEATURE_PMC_HAS_BGBE (1)
<> 154:37f96f9d4de2 1235 /* @brief Has Bandgap Buffer Drive Select. */
<> 154:37f96f9d4de2 1236 #define FSL_FEATURE_PMC_HAS_BGBDS (0)
<> 154:37f96f9d4de2 1237 /* @brief Has Low-Voltage Detect Voltage Select support. */
<> 154:37f96f9d4de2 1238 #define FSL_FEATURE_PMC_HAS_LVDV (1)
<> 154:37f96f9d4de2 1239 /* @brief Has Low-Voltage Warning Voltage Select support. */
<> 154:37f96f9d4de2 1240 #define FSL_FEATURE_PMC_HAS_LVWV (1)
<> 154:37f96f9d4de2 1241 /* @brief Has LPO. */
<> 154:37f96f9d4de2 1242 #define FSL_FEATURE_PMC_HAS_LPO (0)
<> 154:37f96f9d4de2 1243 /* @brief Has VLPx option PMC_REGSC[VLPO]. */
<> 154:37f96f9d4de2 1244 #define FSL_FEATURE_PMC_HAS_VLPO (1)
<> 154:37f96f9d4de2 1245 /* @brief Has acknowledge isolation support. */
<> 154:37f96f9d4de2 1246 #define FSL_FEATURE_PMC_HAS_ACKISO (1)
<> 154:37f96f9d4de2 1247 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
<> 154:37f96f9d4de2 1248 #define FSL_FEATURE_PMC_HAS_REGFPM (0)
<> 154:37f96f9d4de2 1249 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
<> 154:37f96f9d4de2 1250 #define FSL_FEATURE_PMC_HAS_REGONS (1)
<> 154:37f96f9d4de2 1251 /* @brief Has PMC_HVDSC1. */
<> 154:37f96f9d4de2 1252 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0)
<> 154:37f96f9d4de2 1253 /* @brief Has PMC_PARAM. */
<> 154:37f96f9d4de2 1254 #define FSL_FEATURE_PMC_HAS_PARAM (0)
<> 154:37f96f9d4de2 1255 /* @brief Has PMC_VERID. */
<> 154:37f96f9d4de2 1256 #define FSL_FEATURE_PMC_HAS_VERID (0)
<> 154:37f96f9d4de2 1257
<> 154:37f96f9d4de2 1258 /* PORT module features */
<> 154:37f96f9d4de2 1259
<> 154:37f96f9d4de2 1260 /* @brief Has control lock (register bit PCR[LK]). */
<> 154:37f96f9d4de2 1261 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
<> 154:37f96f9d4de2 1262 /* @brief Has open drain control (register bit PCR[ODE]). */
<> 154:37f96f9d4de2 1263 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
<> 154:37f96f9d4de2 1264 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
<> 154:37f96f9d4de2 1265 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
<> 154:37f96f9d4de2 1266 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
<> 154:37f96f9d4de2 1267 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
<> 154:37f96f9d4de2 1268 /* @brief Has pull resistor selection available. */
<> 154:37f96f9d4de2 1269 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
<> 154:37f96f9d4de2 1270 /* @brief Has pull resistor enable (register bit PCR[PE]). */
<> 154:37f96f9d4de2 1271 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
<> 154:37f96f9d4de2 1272 /* @brief Has slew rate control (register bit PCR[SRE]). */
<> 154:37f96f9d4de2 1273 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
<> 154:37f96f9d4de2 1274 /* @brief Has passive filter (register bit field PCR[PFE]). */
<> 154:37f96f9d4de2 1275 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
<> 154:37f96f9d4de2 1276 /* @brief Has drive strength control (register bit PCR[DSE]). */
<> 154:37f96f9d4de2 1277 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
<> 154:37f96f9d4de2 1278 /* @brief Has separate drive strength register (HDRVE). */
<> 154:37f96f9d4de2 1279 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
<> 154:37f96f9d4de2 1280 /* @brief Has glitch filter (register IOFLT). */
<> 154:37f96f9d4de2 1281 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
<> 154:37f96f9d4de2 1282 /* @brief Defines width of PCR[MUX] field. */
<> 154:37f96f9d4de2 1283 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
<> 154:37f96f9d4de2 1284 /* @brief Has dedicated interrupt vector. */
<> 154:37f96f9d4de2 1285 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
<> 154:37f96f9d4de2 1286 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */
<> 154:37f96f9d4de2 1287 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
<> 154:37f96f9d4de2 1288 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
<> 154:37f96f9d4de2 1289 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
<> 154:37f96f9d4de2 1290
<> 154:37f96f9d4de2 1291 /* RADIO module features */
<> 154:37f96f9d4de2 1292
<> 154:37f96f9d4de2 1293 /* @brief Zigbee availability. */
<> 154:37f96f9d4de2 1294 #define FSL_FEATURE_RADIO_HAS_ZIGBEE (1)
<> 154:37f96f9d4de2 1295 /* @brief Bluetooth availability. */
<> 154:37f96f9d4de2 1296 #define FSL_FEATURE_RADIO_HAS_BLE (1)
<> 154:37f96f9d4de2 1297 /* @brief ANT availability */
<> 154:37f96f9d4de2 1298 #define FSL_FEATURE_RADIO_HAS_ANT (1)
<> 154:37f96f9d4de2 1299
<> 154:37f96f9d4de2 1300 /* RCM module features */
<> 154:37f96f9d4de2 1301
<> 154:37f96f9d4de2 1302 /* @brief Has Loss-of-Lock Reset support. */
<> 154:37f96f9d4de2 1303 #define FSL_FEATURE_RCM_HAS_LOL (0)
<> 154:37f96f9d4de2 1304 /* @brief Has Loss-of-Clock Reset support. */
<> 154:37f96f9d4de2 1305 #define FSL_FEATURE_RCM_HAS_LOC (1)
<> 154:37f96f9d4de2 1306 /* @brief Has JTAG generated Reset support. */
<> 154:37f96f9d4de2 1307 #define FSL_FEATURE_RCM_HAS_JTAG (0)
<> 154:37f96f9d4de2 1308 /* @brief Has EzPort generated Reset support. */
<> 154:37f96f9d4de2 1309 #define FSL_FEATURE_RCM_HAS_EZPORT (0)
<> 154:37f96f9d4de2 1310 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
<> 154:37f96f9d4de2 1311 #define FSL_FEATURE_RCM_HAS_EZPMS (0)
<> 154:37f96f9d4de2 1312 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
<> 154:37f96f9d4de2 1313 #define FSL_FEATURE_RCM_HAS_BOOTROM (0)
<> 154:37f96f9d4de2 1314 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
<> 154:37f96f9d4de2 1315 #define FSL_FEATURE_RCM_HAS_SSRS (0)
<> 154:37f96f9d4de2 1316 /* @brief Has Version ID Register (RCM_VERID). */
<> 154:37f96f9d4de2 1317 #define FSL_FEATURE_RCM_HAS_VERID (0)
<> 154:37f96f9d4de2 1318 /* @brief Has Parameter Register (RCM_PARAM). */
<> 154:37f96f9d4de2 1319 #define FSL_FEATURE_RCM_HAS_PARAM (0)
<> 154:37f96f9d4de2 1320 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
<> 154:37f96f9d4de2 1321 #define FSL_FEATURE_RCM_HAS_SRIE (0)
<> 154:37f96f9d4de2 1322 /* @brief Width of registers of the RCM. */
<> 154:37f96f9d4de2 1323 #define FSL_FEATURE_RCM_REG_WIDTH (8)
<> 154:37f96f9d4de2 1324 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
<> 154:37f96f9d4de2 1325 #define FSL_FEATURE_RCM_HAS_CORE1 (0)
<> 154:37f96f9d4de2 1326 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
<> 154:37f96f9d4de2 1327 #define FSL_FEATURE_RCM_HAS_MDM_AP (1)
<> 154:37f96f9d4de2 1328 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
<> 154:37f96f9d4de2 1329 #define FSL_FEATURE_RCM_HAS_WAKEUP (1)
<> 154:37f96f9d4de2 1330
<> 154:37f96f9d4de2 1331 /* RTC module features */
<> 154:37f96f9d4de2 1332
<> 154:37f96f9d4de2 1333 /* @brief Has wakeup pin. */
<> 154:37f96f9d4de2 1334 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
<> 154:37f96f9d4de2 1335 /* @brief Has wakeup pin selection (bit field CR[WPS]). */
<> 154:37f96f9d4de2 1336 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
<> 154:37f96f9d4de2 1337 /* @brief Has low power features (registers MER, MCLR and MCHR). */
<> 154:37f96f9d4de2 1338 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
<> 154:37f96f9d4de2 1339 /* @brief Has read/write access control (registers WAR and RAR). */
<> 154:37f96f9d4de2 1340 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0)
<> 154:37f96f9d4de2 1341 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
<> 154:37f96f9d4de2 1342 #define FSL_FEATURE_RTC_HAS_SECURITY (0)
<> 154:37f96f9d4de2 1343 /* @brief Has RTC_CLKIN available. */
<> 154:37f96f9d4de2 1344 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
<> 154:37f96f9d4de2 1345 /* @brief Has prescaler adjust for LPO. */
<> 154:37f96f9d4de2 1346 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
<> 154:37f96f9d4de2 1347 /* @brief Has Clock Pin Enable field. */
<> 154:37f96f9d4de2 1348 #define FSL_FEATURE_RTC_HAS_CPE (0)
<> 154:37f96f9d4de2 1349 /* @brief Has Timer Seconds Interrupt Configuration field. */
<> 154:37f96f9d4de2 1350 #define FSL_FEATURE_RTC_HAS_TSIC (0)
<> 154:37f96f9d4de2 1351 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
<> 154:37f96f9d4de2 1352 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
<> 154:37f96f9d4de2 1353
<> 154:37f96f9d4de2 1354 /* SIM module features */
<> 154:37f96f9d4de2 1355
<> 154:37f96f9d4de2 1356 /* @brief Has USB FS divider. */
<> 154:37f96f9d4de2 1357 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
<> 154:37f96f9d4de2 1358 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
<> 154:37f96f9d4de2 1359 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
<> 154:37f96f9d4de2 1360 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
<> 154:37f96f9d4de2 1361 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
<> 154:37f96f9d4de2 1362 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
<> 154:37f96f9d4de2 1363 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
<> 154:37f96f9d4de2 1364 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
<> 154:37f96f9d4de2 1365 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
<> 154:37f96f9d4de2 1366 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
<> 154:37f96f9d4de2 1367 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
<> 154:37f96f9d4de2 1368 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
<> 154:37f96f9d4de2 1369 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
<> 154:37f96f9d4de2 1370 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
<> 154:37f96f9d4de2 1371 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
<> 154:37f96f9d4de2 1372 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
<> 154:37f96f9d4de2 1373 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
<> 154:37f96f9d4de2 1374 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
<> 154:37f96f9d4de2 1375 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
<> 154:37f96f9d4de2 1376 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
<> 154:37f96f9d4de2 1377 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
<> 154:37f96f9d4de2 1378 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
<> 154:37f96f9d4de2 1379 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
<> 154:37f96f9d4de2 1380 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
<> 154:37f96f9d4de2 1381 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
<> 154:37f96f9d4de2 1382 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
<> 154:37f96f9d4de2 1383 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
<> 154:37f96f9d4de2 1384 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
<> 154:37f96f9d4de2 1385 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1)
<> 154:37f96f9d4de2 1386 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
<> 154:37f96f9d4de2 1387 #define FSL_FEATURE_SIM_OPT_UART_COUNT (0)
<> 154:37f96f9d4de2 1388 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
<> 154:37f96f9d4de2 1389 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
<> 154:37f96f9d4de2 1390 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
<> 154:37f96f9d4de2 1391 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
<> 154:37f96f9d4de2 1392 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
<> 154:37f96f9d4de2 1393 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
<> 154:37f96f9d4de2 1394 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
<> 154:37f96f9d4de2 1395 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1)
<> 154:37f96f9d4de2 1396 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
<> 154:37f96f9d4de2 1397 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
<> 154:37f96f9d4de2 1398 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
<> 154:37f96f9d4de2 1399 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
<> 154:37f96f9d4de2 1400 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
<> 154:37f96f9d4de2 1401 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1)
<> 154:37f96f9d4de2 1402 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
<> 154:37f96f9d4de2 1403 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
<> 154:37f96f9d4de2 1404 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
<> 154:37f96f9d4de2 1405 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
<> 154:37f96f9d4de2 1406 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
<> 154:37f96f9d4de2 1407 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
<> 154:37f96f9d4de2 1408 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
<> 154:37f96f9d4de2 1409 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0)
<> 154:37f96f9d4de2 1410 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
<> 154:37f96f9d4de2 1411 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0)
<> 154:37f96f9d4de2 1412 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
<> 154:37f96f9d4de2 1413 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0)
<> 154:37f96f9d4de2 1414 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
<> 154:37f96f9d4de2 1415 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0)
<> 154:37f96f9d4de2 1416 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
<> 154:37f96f9d4de2 1417 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
<> 154:37f96f9d4de2 1418 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
<> 154:37f96f9d4de2 1419 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
<> 154:37f96f9d4de2 1420 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
<> 154:37f96f9d4de2 1421 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
<> 154:37f96f9d4de2 1422 /* @brief Has FTM module(s) configuration. */
<> 154:37f96f9d4de2 1423 #define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
<> 154:37f96f9d4de2 1424 /* @brief Number of FTM modules. */
<> 154:37f96f9d4de2 1425 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
<> 154:37f96f9d4de2 1426 /* @brief Number of FTM triggers with selectable source. */
<> 154:37f96f9d4de2 1427 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
<> 154:37f96f9d4de2 1428 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
<> 154:37f96f9d4de2 1429 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
<> 154:37f96f9d4de2 1430 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
<> 154:37f96f9d4de2 1431 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
<> 154:37f96f9d4de2 1432 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
<> 154:37f96f9d4de2 1433 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
<> 154:37f96f9d4de2 1434 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
<> 154:37f96f9d4de2 1435 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
<> 154:37f96f9d4de2 1436 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
<> 154:37f96f9d4de2 1437 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
<> 154:37f96f9d4de2 1438 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
<> 154:37f96f9d4de2 1439 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
<> 154:37f96f9d4de2 1440 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
<> 154:37f96f9d4de2 1441 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
<> 154:37f96f9d4de2 1442 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
<> 154:37f96f9d4de2 1443 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
<> 154:37f96f9d4de2 1444 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
<> 154:37f96f9d4de2 1445 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
<> 154:37f96f9d4de2 1446 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
<> 154:37f96f9d4de2 1447 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
<> 154:37f96f9d4de2 1448 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
<> 154:37f96f9d4de2 1449 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
<> 154:37f96f9d4de2 1450 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
<> 154:37f96f9d4de2 1451 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
<> 154:37f96f9d4de2 1452 /* @brief Has TPM module(s) configuration. */
<> 154:37f96f9d4de2 1453 #define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
<> 154:37f96f9d4de2 1454 /* @brief The highest TPM module index. */
<> 154:37f96f9d4de2 1455 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
<> 154:37f96f9d4de2 1456 /* @brief Has TPM module with index 0. */
<> 154:37f96f9d4de2 1457 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1)
<> 154:37f96f9d4de2 1458 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
<> 154:37f96f9d4de2 1459 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1)
<> 154:37f96f9d4de2 1460 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
<> 154:37f96f9d4de2 1461 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1)
<> 154:37f96f9d4de2 1462 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
<> 154:37f96f9d4de2 1463 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
<> 154:37f96f9d4de2 1464 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
<> 154:37f96f9d4de2 1465 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1)
<> 154:37f96f9d4de2 1466 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
<> 154:37f96f9d4de2 1467 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1)
<> 154:37f96f9d4de2 1468 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
<> 154:37f96f9d4de2 1469 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1)
<> 154:37f96f9d4de2 1470 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
<> 154:37f96f9d4de2 1471 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1)
<> 154:37f96f9d4de2 1472 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
<> 154:37f96f9d4de2 1473 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
<> 154:37f96f9d4de2 1474 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
<> 154:37f96f9d4de2 1475 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
<> 154:37f96f9d4de2 1476 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
<> 154:37f96f9d4de2 1477 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
<> 154:37f96f9d4de2 1478 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
<> 154:37f96f9d4de2 1479 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
<> 154:37f96f9d4de2 1480 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
<> 154:37f96f9d4de2 1481 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
<> 154:37f96f9d4de2 1482 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
<> 154:37f96f9d4de2 1483 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
<> 154:37f96f9d4de2 1484 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
<> 154:37f96f9d4de2 1485 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
<> 154:37f96f9d4de2 1486 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
<> 154:37f96f9d4de2 1487 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
<> 154:37f96f9d4de2 1488 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
<> 154:37f96f9d4de2 1489 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
<> 154:37f96f9d4de2 1490 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
<> 154:37f96f9d4de2 1491 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
<> 154:37f96f9d4de2 1492 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
<> 154:37f96f9d4de2 1493 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
<> 154:37f96f9d4de2 1494 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
<> 154:37f96f9d4de2 1495 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
<> 154:37f96f9d4de2 1496 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
<> 154:37f96f9d4de2 1497 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1)
<> 154:37f96f9d4de2 1498 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
<> 154:37f96f9d4de2 1499 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
<> 154:37f96f9d4de2 1500 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
<> 154:37f96f9d4de2 1501 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
<> 154:37f96f9d4de2 1502 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
<> 154:37f96f9d4de2 1503 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
<> 154:37f96f9d4de2 1504 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
<> 154:37f96f9d4de2 1505 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
<> 154:37f96f9d4de2 1506 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
<> 154:37f96f9d4de2 1507 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
<> 154:37f96f9d4de2 1508 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
<> 154:37f96f9d4de2 1509 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
<> 154:37f96f9d4de2 1510 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
<> 154:37f96f9d4de2 1511 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1)
<> 154:37f96f9d4de2 1512 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
<> 154:37f96f9d4de2 1513 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0)
<> 154:37f96f9d4de2 1514 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
<> 154:37f96f9d4de2 1515 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
<> 154:37f96f9d4de2 1516 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
<> 154:37f96f9d4de2 1517 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
<> 154:37f96f9d4de2 1518 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
<> 154:37f96f9d4de2 1519 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
<> 154:37f96f9d4de2 1520 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
<> 154:37f96f9d4de2 1521 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
<> 154:37f96f9d4de2 1522 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
<> 154:37f96f9d4de2 1523 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
<> 154:37f96f9d4de2 1524 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
<> 154:37f96f9d4de2 1525 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
<> 154:37f96f9d4de2 1526 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
<> 154:37f96f9d4de2 1527 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
<> 154:37f96f9d4de2 1528 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
<> 154:37f96f9d4de2 1529 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
<> 154:37f96f9d4de2 1530 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
<> 154:37f96f9d4de2 1531 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
<> 154:37f96f9d4de2 1532 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
<> 154:37f96f9d4de2 1533 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
<> 154:37f96f9d4de2 1534 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
<> 154:37f96f9d4de2 1535 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
<> 154:37f96f9d4de2 1536 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
<> 154:37f96f9d4de2 1537 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3)
<> 154:37f96f9d4de2 1538 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
<> 154:37f96f9d4de2 1539 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
<> 154:37f96f9d4de2 1540 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
<> 154:37f96f9d4de2 1541 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
<> 154:37f96f9d4de2 1542 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
<> 154:37f96f9d4de2 1543 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
<> 154:37f96f9d4de2 1544 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
<> 154:37f96f9d4de2 1545 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
<> 154:37f96f9d4de2 1546 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
<> 154:37f96f9d4de2 1547 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
<> 154:37f96f9d4de2 1548 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
<> 154:37f96f9d4de2 1549 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
<> 154:37f96f9d4de2 1550 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
<> 154:37f96f9d4de2 1551 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
<> 154:37f96f9d4de2 1552 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
<> 154:37f96f9d4de2 1553 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
<> 154:37f96f9d4de2 1554 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
<> 154:37f96f9d4de2 1555 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
<> 154:37f96f9d4de2 1556 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
<> 154:37f96f9d4de2 1557 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
<> 154:37f96f9d4de2 1558 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
<> 154:37f96f9d4de2 1559 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
<> 154:37f96f9d4de2 1560 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
<> 154:37f96f9d4de2 1561 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
<> 154:37f96f9d4de2 1562 /* @brief Has device die ID (register bit field SDID[DIEID]). */
<> 154:37f96f9d4de2 1563 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
<> 154:37f96f9d4de2 1564 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
<> 154:37f96f9d4de2 1565 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1)
<> 154:37f96f9d4de2 1566 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
<> 154:37f96f9d4de2 1567 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
<> 154:37f96f9d4de2 1568 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
<> 154:37f96f9d4de2 1569 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
<> 154:37f96f9d4de2 1570 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
<> 154:37f96f9d4de2 1571 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
<> 154:37f96f9d4de2 1572 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
<> 154:37f96f9d4de2 1573 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
<> 154:37f96f9d4de2 1574 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
<> 154:37f96f9d4de2 1575 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
<> 154:37f96f9d4de2 1576 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
<> 154:37f96f9d4de2 1577 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
<> 154:37f96f9d4de2 1578 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
<> 154:37f96f9d4de2 1579 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
<> 154:37f96f9d4de2 1580 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
<> 154:37f96f9d4de2 1581 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
<> 154:37f96f9d4de2 1582 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
<> 154:37f96f9d4de2 1583 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
<> 154:37f96f9d4de2 1584 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
<> 154:37f96f9d4de2 1585 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
<> 154:37f96f9d4de2 1586 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
<> 154:37f96f9d4de2 1587 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
<> 154:37f96f9d4de2 1588 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
<> 154:37f96f9d4de2 1589 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
<> 154:37f96f9d4de2 1590 /* @brief Has miscellanious control register (register MCR). */
<> 154:37f96f9d4de2 1591 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
<> 154:37f96f9d4de2 1592 /* @brief Has COP watchdog (registers COPC and SRVCOP). */
<> 154:37f96f9d4de2 1593 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1)
<> 154:37f96f9d4de2 1594 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
<> 154:37f96f9d4de2 1595 #define FSL_FEATURE_SIM_HAS_COP_STOP (1)
<> 154:37f96f9d4de2 1596 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
<> 154:37f96f9d4de2 1597 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
<> 154:37f96f9d4de2 1598
<> 154:37f96f9d4de2 1599 /* SMC module features */
<> 154:37f96f9d4de2 1600
<> 154:37f96f9d4de2 1601 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
<> 154:37f96f9d4de2 1602 #define FSL_FEATURE_SMC_HAS_PSTOPO (1)
<> 154:37f96f9d4de2 1603 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
<> 154:37f96f9d4de2 1604 #define FSL_FEATURE_SMC_HAS_LPOPO (0)
<> 154:37f96f9d4de2 1605 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
<> 154:37f96f9d4de2 1606 #define FSL_FEATURE_SMC_HAS_PORPO (1)
<> 154:37f96f9d4de2 1607 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
<> 154:37f96f9d4de2 1608 #define FSL_FEATURE_SMC_HAS_LPWUI (0)
<> 154:37f96f9d4de2 1609 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
<> 154:37f96f9d4de2 1610 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1)
<> 154:37f96f9d4de2 1611 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
<> 154:37f96f9d4de2 1612 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
<> 154:37f96f9d4de2 1613 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
<> 154:37f96f9d4de2 1614 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
<> 154:37f96f9d4de2 1615 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
<> 154:37f96f9d4de2 1616 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1)
<> 154:37f96f9d4de2 1617 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
<> 154:37f96f9d4de2 1618 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
<> 154:37f96f9d4de2 1619 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
<> 154:37f96f9d4de2 1620 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
<> 154:37f96f9d4de2 1621 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
<> 154:37f96f9d4de2 1622 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
<> 154:37f96f9d4de2 1623 /* @brief Has stop submode. */
<> 154:37f96f9d4de2 1624 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
<> 154:37f96f9d4de2 1625 /* @brief Has stop submode 0(VLLS0). */
<> 154:37f96f9d4de2 1626 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
<> 154:37f96f9d4de2 1627 /* @brief Has stop submode 2(VLLS2). */
<> 154:37f96f9d4de2 1628 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
<> 154:37f96f9d4de2 1629 /* @brief Has SMC_PARAM. */
<> 154:37f96f9d4de2 1630 #define FSL_FEATURE_SMC_HAS_PARAM (0)
<> 154:37f96f9d4de2 1631 /* @brief Has SMC_VERID. */
<> 154:37f96f9d4de2 1632 #define FSL_FEATURE_SMC_HAS_VERID (0)
<> 154:37f96f9d4de2 1633
<> 154:37f96f9d4de2 1634 /* DSPI module features */
<> 154:37f96f9d4de2 1635
<> 154:37f96f9d4de2 1636 /* @brief Receive/transmit FIFO size in number of items. */
<> 154:37f96f9d4de2 1637 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4)
<> 154:37f96f9d4de2 1638 /* @brief Maximum transfer data width in bits. */
<> 154:37f96f9d4de2 1639 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
<> 154:37f96f9d4de2 1640 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
<> 154:37f96f9d4de2 1641 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (4)
<> 154:37f96f9d4de2 1642 /* @brief Number of chip select pins. */
<> 154:37f96f9d4de2 1643 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (3)
<> 154:37f96f9d4de2 1644 /* @brief Has chip select strobe capability on the PCS5 pin. */
<> 154:37f96f9d4de2 1645 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0)
<> 154:37f96f9d4de2 1646 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
<> 154:37f96f9d4de2 1647 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
<> 154:37f96f9d4de2 1648 /* @brief Has 16-bit data transfer support. */
<> 154:37f96f9d4de2 1649 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
<> 154:37f96f9d4de2 1650 /* @brief Has separate DMA RX and TX requests. */
<> 154:37f96f9d4de2 1651 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
<> 154:37f96f9d4de2 1652
<> 154:37f96f9d4de2 1653 /* SysTick module features */
<> 154:37f96f9d4de2 1654
<> 154:37f96f9d4de2 1655 /* @brief Systick has external reference clock. */
<> 154:37f96f9d4de2 1656 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1)
<> 154:37f96f9d4de2 1657 /* @brief Systick external reference clock is core clock divided by this value. */
<> 154:37f96f9d4de2 1658 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16)
<> 154:37f96f9d4de2 1659
<> 154:37f96f9d4de2 1660 /* TPM module features */
<> 154:37f96f9d4de2 1661
<> 154:37f96f9d4de2 1662 /* @brief Bus clock is the source clock for the module. */
<> 154:37f96f9d4de2 1663 #define FSL_FEATURE_TPM_BUS_CLOCK (0)
<> 154:37f96f9d4de2 1664 /* @brief Number of channels. */
<> 154:37f96f9d4de2 1665 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \
<> 154:37f96f9d4de2 1666 ((x) == TPM0 ? (4) : \
<> 154:37f96f9d4de2 1667 ((x) == TPM1 ? (2) : \
<> 154:37f96f9d4de2 1668 ((x) == TPM2 ? (2) : (-1))))
<> 154:37f96f9d4de2 1669 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
<> 154:37f96f9d4de2 1670 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
<> 154:37f96f9d4de2 1671 /* @brief Has TPM_PARAM. */
<> 154:37f96f9d4de2 1672 #define FSL_FEATURE_TPM_HAS_PARAM (0)
<> 154:37f96f9d4de2 1673 /* @brief Has TPM_VERID. */
<> 154:37f96f9d4de2 1674 #define FSL_FEATURE_TPM_HAS_VERID (0)
<> 154:37f96f9d4de2 1675 /* @brief Has TPM_GLOBAL. */
<> 154:37f96f9d4de2 1676 #define FSL_FEATURE_TPM_HAS_GLOBAL (0)
<> 154:37f96f9d4de2 1677 /* @brief Has TPM_TRIG. */
<> 154:37f96f9d4de2 1678 #define FSL_FEATURE_TPM_HAS_TRIG (0)
<> 154:37f96f9d4de2 1679 /* @brief Has counter pause on trigger. */
<> 154:37f96f9d4de2 1680 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
<> 154:37f96f9d4de2 1681 /* @brief Has external trigger selection. */
<> 154:37f96f9d4de2 1682 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
<> 154:37f96f9d4de2 1683 /* @brief Has TPM_COMBINE. */
<> 154:37f96f9d4de2 1684 #define FSL_FEATURE_TPM_HAS_COMBINE (1)
<> 154:37f96f9d4de2 1685 /* @brief Has TPM_POL. */
<> 154:37f96f9d4de2 1686 #define FSL_FEATURE_TPM_HAS_POL (1)
<> 154:37f96f9d4de2 1687 /* @brief Has TPM_FILTER. */
<> 154:37f96f9d4de2 1688 #define FSL_FEATURE_TPM_HAS_FILTER (1)
<> 154:37f96f9d4de2 1689 /* @brief Has TPM_QDCTRL. */
<> 154:37f96f9d4de2 1690 #define FSL_FEATURE_TPM_HAS_QDCTRL (1)
<> 154:37f96f9d4de2 1691
<> 154:37f96f9d4de2 1692 /* TRNG0 module features */
<> 154:37f96f9d4de2 1693
<> 154:37f96f9d4de2 1694 /* No feature definitions */
<> 154:37f96f9d4de2 1695
<> 154:37f96f9d4de2 1696 /* TSI module features */
<> 154:37f96f9d4de2 1697
<> 154:37f96f9d4de2 1698 /* @brief TSI module version. */
<> 154:37f96f9d4de2 1699 #define FSL_FEATURE_TSI_VERSION (4)
<> 154:37f96f9d4de2 1700 /* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */
<> 154:37f96f9d4de2 1701 #define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0)
<> 154:37f96f9d4de2 1702 /* @brief Number of TSI channels. */
<> 154:37f96f9d4de2 1703 #define FSL_FEATURE_TSI_CHANNEL_COUNT (16)
<> 154:37f96f9d4de2 1704
<> 154:37f96f9d4de2 1705 /* VREF module features */
<> 154:37f96f9d4de2 1706
<> 154:37f96f9d4de2 1707 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */
<> 154:37f96f9d4de2 1708 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
<> 154:37f96f9d4de2 1709 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
<> 154:37f96f9d4de2 1710 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
<> 154:37f96f9d4de2 1711 /* @brief If high/low buffer mode supported */
<> 154:37f96f9d4de2 1712 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
<> 154:37f96f9d4de2 1713 /* @brief Module has also low reference (registers VREFL/VREFH) */
<> 154:37f96f9d4de2 1714 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
<> 154:37f96f9d4de2 1715 /* @brief Has VREF_TRM4. */
<> 154:37f96f9d4de2 1716 #define FSL_FEATURE_VREF_HAS_TRM4 (0)
<> 154:37f96f9d4de2 1717
<> 154:37f96f9d4de2 1718 #endif /* _MKW41Z4_FEATURES_H_ */
<> 154:37f96f9d4de2 1719