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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_iwdg.h@167:356ef919c855, 2017-06-20 (annotated)

Committer:
kkado
Date:
Tue Jun 20 11:06:37 2017 +0000
Revision:
167:356ef919c855
Parent:
151:5eaa88a5bcc7 
Build 137 with reduced HSE timeout

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_iwdg.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 151:5eaa88a5bcc7 5 * @version V1.7.0
<> 151:5eaa88a5bcc7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of IWDG HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32L0xx_HAL_IWDG_H
<> 144:ef7eb2e8f9f7 40 #define __STM32L0xx_HAL_IWDG_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32l0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @defgroup IWDG IWDG
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @defgroup IWDG_Exported_Types IWDG Exported Types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /** @defgroup IWDG_State IWDG state definition
<> 144:ef7eb2e8f9f7 64 * @{
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 /**
<> 144:ef7eb2e8f9f7 67 * @brief IWDG HAL State Structure definition
<> 144:ef7eb2e8f9f7 68 */
<> 144:ef7eb2e8f9f7 69 typedef enum
<> 144:ef7eb2e8f9f7 70 {
<> 151:5eaa88a5bcc7 71 HAL_IWDG_STATE_RESET = 0x00U, /*!< IWDG not yet initialized or disabled */
<> 151:5eaa88a5bcc7 72 HAL_IWDG_STATE_READY = 0x01U, /*!< IWDG initialized and ready for use */
<> 151:5eaa88a5bcc7 73 HAL_IWDG_STATE_BUSY = 0x02U, /*!< IWDG internal process is ongoing */
<> 151:5eaa88a5bcc7 74 HAL_IWDG_STATE_TIMEOUT = 0x03U, /*!< IWDG timeout state */
<> 151:5eaa88a5bcc7 75 HAL_IWDG_STATE_ERROR = 0x04U /*!< IWDG error state */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 }HAL_IWDG_StateTypeDef;
<> 144:ef7eb2e8f9f7 78 /**
<> 144:ef7eb2e8f9f7 79 * @}
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81 /** @defgroup IWDG_Init IWDG init configuration structure
<> 144:ef7eb2e8f9f7 82 * @{
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84 /**
<> 144:ef7eb2e8f9f7 85 * @brief IWDG Init structure definition
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87 typedef struct
<> 144:ef7eb2e8f9f7 88 {
<> 144:ef7eb2e8f9f7 89 uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
<> 144:ef7eb2e8f9f7 90 This parameter can be a value of @ref IWDG_Prescaler */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
<> 144:ef7eb2e8f9f7 93 This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
<> 144:ef7eb2e8f9f7 96 This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 } IWDG_InitTypeDef;
<> 144:ef7eb2e8f9f7 99 /**
<> 144:ef7eb2e8f9f7 100 * @}
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /** @defgroup IWDG_handle IWDG handler
<> 144:ef7eb2e8f9f7 104 * @{
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106 /**
<> 144:ef7eb2e8f9f7 107 * @brief IWDG Handle Structure definition
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109 typedef struct
<> 144:ef7eb2e8f9f7 110 {
<> 144:ef7eb2e8f9f7 111 IWDG_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 IWDG_InitTypeDef Init; /*!< IWDG required parameters */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 HAL_LockTypeDef Lock; /*!< IWDG Locking object */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 }IWDG_HandleTypeDef;
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /**
<> 144:ef7eb2e8f9f7 122 * @}
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /**
<> 144:ef7eb2e8f9f7 126 * @}
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /** @defgroup IWDG_Exported_Constants IWDG Exported Constants
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /** @defgroup IWDG_Registers_Key IWDG key
<> 144:ef7eb2e8f9f7 136 * @brief IWDG registers bit mask
<> 144:ef7eb2e8f9f7 137 * @{
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139 /* --- KR Register ---*/
<> 144:ef7eb2e8f9f7 140 /* KR register bit mask */
<> 151:5eaa88a5bcc7 141 #define IWDG_KEY_RELOAD ((uint32_t)0xAAAAU) /*!< IWDG Reload Counter Enable */
<> 151:5eaa88a5bcc7 142 #define IWDG_KEY_ENABLE ((uint32_t)0xCCCCU) /*!< IWDG Peripheral Enable */
<> 151:5eaa88a5bcc7 143 #define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x5555U) /*!< IWDG KR Write Access Enable */
<> 151:5eaa88a5bcc7 144 #define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x0000U) /*!< IWDG KR Write Access Disable */
<> 144:ef7eb2e8f9f7 145 /**
<> 144:ef7eb2e8f9f7 146 * @}
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 #define IS_IWDG_KR(__KR__) (((__KR__) == IWDG_KEY_RELOAD) || \
<> 144:ef7eb2e8f9f7 150 ((__KR__) == IWDG_KEY_ENABLE))|| \
<> 144:ef7eb2e8f9f7 151 ((__KR__) == IWDG_KEY_WRITE_ACCESS_ENABLE)) || \
<> 144:ef7eb2e8f9f7 152 ((__KR__) == IWDG_KEY_WRITE_ACCESS_DISABLE))
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /** @defgroup IWDG_Flag_definition IWDG Flag definition
<> 144:ef7eb2e8f9f7 156 * @{
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158 #define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update flag */
<> 144:ef7eb2e8f9f7 159 #define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update flag */
<> 144:ef7eb2e8f9f7 160 #define IWDG_FLAG_WVU ((uint32_t)IWDG_SR_WVU) /*!< Watchdog counter window value update Flag */
<> 144:ef7eb2e8f9f7 161 /**
<> 144:ef7eb2e8f9f7 162 * @}
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /** @defgroup IWDG_Prescaler IWDG Prescaler
<> 144:ef7eb2e8f9f7 166 * @{
<> 144:ef7eb2e8f9f7 167 */
<> 151:5eaa88a5bcc7 168 #define IWDG_PRESCALER_4 ((uint8_t)0x00U) /*!< IWDG prescaler set to 4 */
<> 144:ef7eb2e8f9f7 169 #define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */
<> 144:ef7eb2e8f9f7 170 #define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */
<> 144:ef7eb2e8f9f7 171 #define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */
<> 144:ef7eb2e8f9f7 172 #define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */
<> 144:ef7eb2e8f9f7 173 #define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */
<> 144:ef7eb2e8f9f7 174 #define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */
<> 144:ef7eb2e8f9f7 175 /**
<> 144:ef7eb2e8f9f7 176 * @}
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178 #define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
<> 144:ef7eb2e8f9f7 179 ((__PRESCALER__) == IWDG_PRESCALER_8) || \
<> 144:ef7eb2e8f9f7 180 ((__PRESCALER__) == IWDG_PRESCALER_16) || \
<> 144:ef7eb2e8f9f7 181 ((__PRESCALER__) == IWDG_PRESCALER_32) || \
<> 144:ef7eb2e8f9f7 182 ((__PRESCALER__) == IWDG_PRESCALER_64) || \
<> 144:ef7eb2e8f9f7 183 ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
<> 144:ef7eb2e8f9f7 184 ((__PRESCALER__) == IWDG_PRESCALER_256))
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Check for reload value */
<> 151:5eaa88a5bcc7 187 #define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFFU)
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /* Check for window value */
<> 151:5eaa88a5bcc7 190 #define IS_IWDG_WINDOW(__VALUE__) ((__VALUE__) <= 0xFFFU)
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /** @defgroup IWDG_Disable IWDG Disable
<> 144:ef7eb2e8f9f7 194 * @{
<> 144:ef7eb2e8f9f7 195 */
<> 151:5eaa88a5bcc7 196 #define IWDG_WINDOW_DISABLE 0xFFFU
<> 144:ef7eb2e8f9f7 197 /**
<> 144:ef7eb2e8f9f7 198 * @}
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /**
<> 144:ef7eb2e8f9f7 202 * @}
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 205 /** @defgroup IWDG_Exported_Macro IWDG Exported Macros
<> 144:ef7eb2e8f9f7 206 * @{
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /** @brief Reset IWDG handle state
<> 144:ef7eb2e8f9f7 210 * @param __HANDLE__ : IWDG handle
<> 144:ef7eb2e8f9f7 211 * @retval None
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213 #define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /**
<> 144:ef7eb2e8f9f7 216 * @brief Enables the IWDG peripheral.
<> 144:ef7eb2e8f9f7 217 * @param __HANDLE__ : IWDG handle
<> 144:ef7eb2e8f9f7 218 * @retval None
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220 #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /**
<> 144:ef7eb2e8f9f7 223 * @brief Reloads IWDG counter with value defined in the reload register
<> 144:ef7eb2e8f9f7 224 * (write access to IWDG_PR and IWDG_RLR registers disabled).
<> 144:ef7eb2e8f9f7 225 * @param __HANDLE__ : IWDG handle
<> 144:ef7eb2e8f9f7 226 * @retval None
<> 144:ef7eb2e8f9f7 227 */
<> 144:ef7eb2e8f9f7 228 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /**
<> 144:ef7eb2e8f9f7 231 * @brief Enables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
<> 144:ef7eb2e8f9f7 232 * @param __HANDLE__ : IWDG handle
<> 144:ef7eb2e8f9f7 233 * @retval None
<> 144:ef7eb2e8f9f7 234 */
<> 144:ef7eb2e8f9f7 235 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /**
<> 144:ef7eb2e8f9f7 238 * @brief Disables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
<> 144:ef7eb2e8f9f7 239 * @param __HANDLE__ : IWDG handle
<> 144:ef7eb2e8f9f7 240 * @retval None
<> 144:ef7eb2e8f9f7 241 */
<> 144:ef7eb2e8f9f7 242 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /**
<> 144:ef7eb2e8f9f7 245 * @brief Gets the selected IWDG's flag status.
<> 144:ef7eb2e8f9f7 246 * @param __HANDLE__ : IWDG handle
<> 144:ef7eb2e8f9f7 247 * @param __FLAG__ : specifies the flag to check.
<> 144:ef7eb2e8f9f7 248 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 249 * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
<> 144:ef7eb2e8f9f7 250 * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
<> 144:ef7eb2e8f9f7 251 * @arg IWDG_FLAG_WVU: Watchdog counter window value flag
<> 144:ef7eb2e8f9f7 252 * @retval The new state of __FLAG__ (TRUE or FALSE) .
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254 #define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /**
<> 144:ef7eb2e8f9f7 257 * @}
<> 144:ef7eb2e8f9f7 258 */
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 261 /** @defgroup IWDG_Exported_Functions IWDG Exported Functions
<> 144:ef7eb2e8f9f7 262 * @{
<> 144:ef7eb2e8f9f7 263 */
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /** @defgroup IWDG_Exported_Functions_Group1 Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 266 * @{
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
<> 144:ef7eb2e8f9f7 269 void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
<> 144:ef7eb2e8f9f7 270 /**
<> 144:ef7eb2e8f9f7 271 * @}
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /** @defgroup IWDG_Exported_Functions_Group2 I/O operation functions
<> 144:ef7eb2e8f9f7 275 * @{
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277 HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
<> 144:ef7eb2e8f9f7 278 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
<> 144:ef7eb2e8f9f7 279 /**
<> 144:ef7eb2e8f9f7 280 * @}
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions
<> 144:ef7eb2e8f9f7 284 * @{
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
<> 144:ef7eb2e8f9f7 287 /**
<> 144:ef7eb2e8f9f7 288 * @}
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /**
<> 144:ef7eb2e8f9f7 292 * @}
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /* Define the private group ***********************************/
<> 144:ef7eb2e8f9f7 296 /**************************************************************/
<> 144:ef7eb2e8f9f7 297 /** @defgroup IWDG_Private IWDG Private
<> 144:ef7eb2e8f9f7 298 * @{
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300 /**
<> 144:ef7eb2e8f9f7 301 * @}
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303 /**************************************************************/
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /**
<> 144:ef7eb2e8f9f7 306 * @}
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /**
<> 144:ef7eb2e8f9f7 310 * @}
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315 #endif
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 #endif /* __STM32L0xx_HAL_IWDG_H */
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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