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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dma_ex.h@167:356ef919c855, 2017-06-20 (annotated)

Committer:
kkado
Date:
Tue Jun 20 11:06:37 2017 +0000
Revision:
167:356ef919c855
Parent:
157:ff67d9f36b67 
Build 137 with reduced HSE timeout

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f3xx_hal_dma_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 157:ff67d9f36b67 5 * @version V1.4.0
<> 157:ff67d9f36b67 6 * @date 16-December-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of DMA HAL extension module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F3xx_HAL_DMA_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F3xx_HAL_DMA_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f3xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F3xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup DMAEx
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
<> 144:ef7eb2e8f9f7 61 * @{
<> 144:ef7eb2e8f9f7 62 */
<> 144:ef7eb2e8f9f7 63 /* Interrupt & Flag management */
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 66 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 67 defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 68 /**
<> 144:ef7eb2e8f9f7 69 * @brief Returns the current DMA Channel transfer complete flag.
<> 144:ef7eb2e8f9f7 70 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 71 * @retval The specified transfer complete flag index.
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
<> 144:ef7eb2e8f9f7 74 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
<> 144:ef7eb2e8f9f7 75 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
<> 144:ef7eb2e8f9f7 76 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
<> 144:ef7eb2e8f9f7 77 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
<> 144:ef7eb2e8f9f7 78 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
<> 144:ef7eb2e8f9f7 79 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
<> 144:ef7eb2e8f9f7 80 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
<> 144:ef7eb2e8f9f7 81 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
<> 144:ef7eb2e8f9f7 82 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
<> 144:ef7eb2e8f9f7 83 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
<> 144:ef7eb2e8f9f7 84 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
<> 144:ef7eb2e8f9f7 85 DMA_FLAG_TC5)
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /**
<> 144:ef7eb2e8f9f7 88 * @brief Returns the current DMA Channel half transfer complete flag.
<> 144:ef7eb2e8f9f7 89 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 90 * @retval The specified half transfer complete flag index.
<> 144:ef7eb2e8f9f7 91 */
<> 144:ef7eb2e8f9f7 92 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 93 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
<> 144:ef7eb2e8f9f7 94 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
<> 144:ef7eb2e8f9f7 95 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
<> 144:ef7eb2e8f9f7 96 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
<> 144:ef7eb2e8f9f7 97 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
<> 144:ef7eb2e8f9f7 98 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
<> 144:ef7eb2e8f9f7 99 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
<> 144:ef7eb2e8f9f7 100 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
<> 144:ef7eb2e8f9f7 101 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
<> 144:ef7eb2e8f9f7 102 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
<> 144:ef7eb2e8f9f7 103 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
<> 144:ef7eb2e8f9f7 104 DMA_FLAG_HT5)
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /**
<> 144:ef7eb2e8f9f7 107 * @brief Returns the current DMA Channel transfer error flag.
<> 144:ef7eb2e8f9f7 108 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 109 * @retval The specified transfer error flag index.
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 112 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
<> 144:ef7eb2e8f9f7 113 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
<> 144:ef7eb2e8f9f7 114 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
<> 144:ef7eb2e8f9f7 115 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
<> 144:ef7eb2e8f9f7 116 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
<> 144:ef7eb2e8f9f7 117 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
<> 144:ef7eb2e8f9f7 118 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
<> 144:ef7eb2e8f9f7 119 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
<> 144:ef7eb2e8f9f7 120 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
<> 144:ef7eb2e8f9f7 121 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
<> 144:ef7eb2e8f9f7 122 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
<> 144:ef7eb2e8f9f7 123 DMA_FLAG_TE5)
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /**
<> 144:ef7eb2e8f9f7 126 * @brief Return the current DMA Channel Global interrupt flag.
<> 144:ef7eb2e8f9f7 127 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 128 * @retval The specified transfer error flag index.
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 131 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
<> 144:ef7eb2e8f9f7 132 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
<> 144:ef7eb2e8f9f7 133 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
<> 144:ef7eb2e8f9f7 134 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
<> 144:ef7eb2e8f9f7 135 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
<> 144:ef7eb2e8f9f7 136 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
<> 144:ef7eb2e8f9f7 137 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
<> 144:ef7eb2e8f9f7 138 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
<> 144:ef7eb2e8f9f7 139 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
<> 144:ef7eb2e8f9f7 140 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
<> 144:ef7eb2e8f9f7 141 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
<> 144:ef7eb2e8f9f7 142 DMA_FLAG_GL5)
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /**
<> 144:ef7eb2e8f9f7 145 * @brief Get the DMA Channel pending flags.
<> 144:ef7eb2e8f9f7 146 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 147 * @param __FLAG__: Get the specified flag.
<> 144:ef7eb2e8f9f7 148 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 149 * @arg DMA_FLAG_TCx: Transfer complete flag
<> 144:ef7eb2e8f9f7 150 * @arg DMA_FLAG_HTx: Half transfer complete flag
<> 144:ef7eb2e8f9f7 151 * @arg DMA_FLAG_TEx: Transfer error flag
<> 144:ef7eb2e8f9f7 152 * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
<> 144:ef7eb2e8f9f7 153 * @retval The state of FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
<> 144:ef7eb2e8f9f7 156 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
<> 144:ef7eb2e8f9f7 157 (DMA1->ISR & (__FLAG__)))
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /**
<> 144:ef7eb2e8f9f7 160 * @brief Clears the DMA Channel pending flags.
<> 144:ef7eb2e8f9f7 161 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 162 * @param __FLAG__: specifies the flag to clear.
<> 144:ef7eb2e8f9f7 163 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 164 * @arg DMA_FLAG_TCx: Transfer complete flag
<> 144:ef7eb2e8f9f7 165 * @arg DMA_FLAG_HTx: Half transfer complete flag
<> 144:ef7eb2e8f9f7 166 * @arg DMA_FLAG_TEx: Transfer error flag
<> 144:ef7eb2e8f9f7 167 * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
<> 144:ef7eb2e8f9f7 168 * @retval None
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
<> 144:ef7eb2e8f9f7 171 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
<> 144:ef7eb2e8f9f7 172 (DMA1->IFCR = (__FLAG__)))
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /**
<> 144:ef7eb2e8f9f7 175 * @}
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 #else /* STM32F301x8_STM32F302x8_STM32F318xx_STM32F303x8_STM32F334x8_STM32F328xx Product devices */
<> 144:ef7eb2e8f9f7 179 /** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
<> 144:ef7eb2e8f9f7 180 * @{
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /**
<> 144:ef7eb2e8f9f7 184 * @brief Returns the current DMA Channel transfer complete flag.
<> 144:ef7eb2e8f9f7 185 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 186 * @retval The specified transfer complete flag index.
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
<> 144:ef7eb2e8f9f7 189 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
<> 144:ef7eb2e8f9f7 190 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
<> 144:ef7eb2e8f9f7 191 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
<> 144:ef7eb2e8f9f7 192 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
<> 144:ef7eb2e8f9f7 193 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
<> 144:ef7eb2e8f9f7 194 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
<> 144:ef7eb2e8f9f7 195 DMA_FLAG_TC7)
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /**
<> 144:ef7eb2e8f9f7 198 * @brief Returns the current DMA Channel half transfer complete flag.
<> 144:ef7eb2e8f9f7 199 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 200 * @retval The specified half transfer complete flag index.
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 203 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
<> 144:ef7eb2e8f9f7 204 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
<> 144:ef7eb2e8f9f7 205 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
<> 144:ef7eb2e8f9f7 206 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
<> 144:ef7eb2e8f9f7 207 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
<> 144:ef7eb2e8f9f7 208 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
<> 144:ef7eb2e8f9f7 209 DMA_FLAG_HT7)
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /**
<> 144:ef7eb2e8f9f7 212 * @brief Returns the current DMA Channel transfer error flag.
<> 144:ef7eb2e8f9f7 213 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 214 * @retval The specified transfer error flag index.
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 217 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
<> 144:ef7eb2e8f9f7 218 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
<> 144:ef7eb2e8f9f7 219 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
<> 144:ef7eb2e8f9f7 220 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
<> 144:ef7eb2e8f9f7 221 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
<> 144:ef7eb2e8f9f7 222 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
<> 144:ef7eb2e8f9f7 223 DMA_FLAG_TE7)
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /**
<> 144:ef7eb2e8f9f7 226 * @brief Return the current DMA Channel Global interrupt flag.
<> 144:ef7eb2e8f9f7 227 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 228 * @retval The specified transfer error flag index.
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 231 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
<> 144:ef7eb2e8f9f7 232 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
<> 144:ef7eb2e8f9f7 233 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
<> 144:ef7eb2e8f9f7 234 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
<> 144:ef7eb2e8f9f7 235 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
<> 144:ef7eb2e8f9f7 236 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
<> 144:ef7eb2e8f9f7 237 DMA_FLAG_GL7)
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /**
<> 144:ef7eb2e8f9f7 240 * @brief Get the DMA Channel pending flags.
<> 144:ef7eb2e8f9f7 241 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 242 * @param __FLAG__: Get the specified flag.
<> 144:ef7eb2e8f9f7 243 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 244 * @arg DMA_FLAG_TCx: Transfer complete flag
<> 144:ef7eb2e8f9f7 245 * @arg DMA_FLAG_HTx: Half transfer complete flag
<> 144:ef7eb2e8f9f7 246 * @arg DMA_FLAG_TEx: Transfer error flag
<> 144:ef7eb2e8f9f7 247 * Where x can be 1_7 to select the DMA Channel flag.
<> 144:ef7eb2e8f9f7 248 * @retval The state of FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /**
<> 144:ef7eb2e8f9f7 254 * @brief Clears the DMA Channel pending flags.
<> 144:ef7eb2e8f9f7 255 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 256 * @param __FLAG__: specifies the flag to clear.
<> 144:ef7eb2e8f9f7 257 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 258 * @arg DMA_FLAG_TCx: Transfer complete flag
<> 144:ef7eb2e8f9f7 259 * @arg DMA_FLAG_HTx: Half transfer complete flag
<> 144:ef7eb2e8f9f7 260 * @arg DMA_FLAG_TEx: Transfer error flag
<> 144:ef7eb2e8f9f7 261 * Where x can be 1_7 to select the DMA Channel flag.
<> 144:ef7eb2e8f9f7 262 * @retval None
<> 144:ef7eb2e8f9f7 263 */
<> 144:ef7eb2e8f9f7 264 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /**
<> 144:ef7eb2e8f9f7 267 * @}
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 #endif
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /**
<> 144:ef7eb2e8f9f7 273 * @}
<> 144:ef7eb2e8f9f7 274 */
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /**
<> 144:ef7eb2e8f9f7 277 * @}
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /**
<> 144:ef7eb2e8f9f7 281 * @}
<> 144:ef7eb2e8f9f7 282 */
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 285 }
<> 144:ef7eb2e8f9f7 286 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 287 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 288 /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 #endif /* __STM32F3xx_HAL_DMA_H */
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/