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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_tpm.h@167:356ef919c855, 2017-06-20 (annotated)

Committer:
kkado
Date:
Tue Jun 20 11:06:37 2017 +0000
Revision:
167:356ef919c855
Parent:
154:37f96f9d4de2 
Build 137 with reduced HSE timeout

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30 #ifndef _FSL_TPM_H_
<> 154:37f96f9d4de2 31 #define _FSL_TPM_H_
<> 154:37f96f9d4de2 32
<> 154:37f96f9d4de2 33 #include "fsl_common.h"
<> 154:37f96f9d4de2 34
<> 154:37f96f9d4de2 35 /*!
<> 154:37f96f9d4de2 36 * @addtogroup tpm
<> 154:37f96f9d4de2 37 * @{
<> 154:37f96f9d4de2 38 */
<> 154:37f96f9d4de2 39
<> 154:37f96f9d4de2 40
<> 154:37f96f9d4de2 41 /*******************************************************************************
<> 154:37f96f9d4de2 42 * Definitions
<> 154:37f96f9d4de2 43 ******************************************************************************/
<> 154:37f96f9d4de2 44
<> 154:37f96f9d4de2 45 /*! @name Driver version */
<> 154:37f96f9d4de2 46 /*@{*/
<> 154:37f96f9d4de2 47 #define FSL_TPM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */
<> 154:37f96f9d4de2 48 /*@}*/
<> 154:37f96f9d4de2 49
<> 154:37f96f9d4de2 50 /*!
<> 154:37f96f9d4de2 51 * @brief List of TPM channels.
<> 154:37f96f9d4de2 52 * @note Actual number of available channels is SoC dependent
<> 154:37f96f9d4de2 53 */
<> 154:37f96f9d4de2 54 typedef enum _tpm_chnl
<> 154:37f96f9d4de2 55 {
<> 154:37f96f9d4de2 56 kTPM_Chnl_0 = 0U, /*!< TPM channel number 0*/
<> 154:37f96f9d4de2 57 kTPM_Chnl_1, /*!< TPM channel number 1 */
<> 154:37f96f9d4de2 58 kTPM_Chnl_2, /*!< TPM channel number 2 */
<> 154:37f96f9d4de2 59 kTPM_Chnl_3, /*!< TPM channel number 3 */
<> 154:37f96f9d4de2 60 kTPM_Chnl_4, /*!< TPM channel number 4 */
<> 154:37f96f9d4de2 61 kTPM_Chnl_5, /*!< TPM channel number 5 */
<> 154:37f96f9d4de2 62 kTPM_Chnl_6, /*!< TPM channel number 6 */
<> 154:37f96f9d4de2 63 kTPM_Chnl_7 /*!< TPM channel number 7 */
<> 154:37f96f9d4de2 64 } tpm_chnl_t;
<> 154:37f96f9d4de2 65
<> 154:37f96f9d4de2 66 /*! @brief TPM PWM operation modes */
<> 154:37f96f9d4de2 67 typedef enum _tpm_pwm_mode
<> 154:37f96f9d4de2 68 {
<> 154:37f96f9d4de2 69 kTPM_EdgeAlignedPwm = 0U, /*!< Edge aligned PWM */
<> 154:37f96f9d4de2 70 kTPM_CenterAlignedPwm, /*!< Center aligned PWM */
<> 154:37f96f9d4de2 71 #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
<> 154:37f96f9d4de2 72 kTPM_CombinedPwm /*!< Combined PWM */
<> 154:37f96f9d4de2 73 #endif
<> 154:37f96f9d4de2 74 } tpm_pwm_mode_t;
<> 154:37f96f9d4de2 75
<> 154:37f96f9d4de2 76 /*! @brief TPM PWM output pulse mode: high-true, low-true or no output */
<> 154:37f96f9d4de2 77 typedef enum _tpm_pwm_level_select
<> 154:37f96f9d4de2 78 {
<> 154:37f96f9d4de2 79 kTPM_NoPwmSignal = 0U, /*!< No PWM output on pin */
<> 154:37f96f9d4de2 80 kTPM_LowTrue, /*!< Low true pulses */
<> 154:37f96f9d4de2 81 kTPM_HighTrue /*!< High true pulses */
<> 154:37f96f9d4de2 82 } tpm_pwm_level_select_t;
<> 154:37f96f9d4de2 83
<> 154:37f96f9d4de2 84 /*! @brief Options to configure a TPM channel's PWM signal */
<> 154:37f96f9d4de2 85 typedef struct _tpm_chnl_pwm_signal_param
<> 154:37f96f9d4de2 86 {
<> 154:37f96f9d4de2 87 tpm_chnl_t chnlNumber; /*!< TPM channel to configure.
<> 154:37f96f9d4de2 88 In combined mode (available in some SoC's, this represents the
<> 154:37f96f9d4de2 89 channel pair number */
<> 154:37f96f9d4de2 90 tpm_pwm_level_select_t level; /*!< PWM output active level select */
<> 154:37f96f9d4de2 91 uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100
<> 154:37f96f9d4de2 92 0=inactive signal(0% duty cycle)...
<> 154:37f96f9d4de2 93 100=always active signal (100% duty cycle)*/
<> 154:37f96f9d4de2 94 #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
<> 154:37f96f9d4de2 95 uint8_t firstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate asymmetrical PWM.
<> 154:37f96f9d4de2 96 Specifies the delay to the first edge in a PWM period.
<> 154:37f96f9d4de2 97 If unsure, leave as 0; Should be specified as
<> 154:37f96f9d4de2 98 percentage of the PWM period */
<> 154:37f96f9d4de2 99 #endif
<> 154:37f96f9d4de2 100 } tpm_chnl_pwm_signal_param_t;
<> 154:37f96f9d4de2 101
<> 154:37f96f9d4de2 102 /*!
<> 154:37f96f9d4de2 103 * @brief Trigger options available.
<> 154:37f96f9d4de2 104 *
<> 154:37f96f9d4de2 105 * This is used for both internal & external trigger sources (external option available in certain SoC's)
<> 154:37f96f9d4de2 106 *
<> 154:37f96f9d4de2 107 * @note The actual trigger options available is SoC-specific.
<> 154:37f96f9d4de2 108 */
<> 154:37f96f9d4de2 109 typedef enum _tpm_trigger_select
<> 154:37f96f9d4de2 110 {
<> 154:37f96f9d4de2 111 kTPM_Trigger_Select_0 = 0U,
<> 154:37f96f9d4de2 112 kTPM_Trigger_Select_1,
<> 154:37f96f9d4de2 113 kTPM_Trigger_Select_2,
<> 154:37f96f9d4de2 114 kTPM_Trigger_Select_3,
<> 154:37f96f9d4de2 115 kTPM_Trigger_Select_4,
<> 154:37f96f9d4de2 116 kTPM_Trigger_Select_5,
<> 154:37f96f9d4de2 117 kTPM_Trigger_Select_6,
<> 154:37f96f9d4de2 118 kTPM_Trigger_Select_7,
<> 154:37f96f9d4de2 119 kTPM_Trigger_Select_8,
<> 154:37f96f9d4de2 120 kTPM_Trigger_Select_9,
<> 154:37f96f9d4de2 121 kTPM_Trigger_Select_10,
<> 154:37f96f9d4de2 122 kTPM_Trigger_Select_11,
<> 154:37f96f9d4de2 123 kTPM_Trigger_Select_12,
<> 154:37f96f9d4de2 124 kTPM_Trigger_Select_13,
<> 154:37f96f9d4de2 125 kTPM_Trigger_Select_14,
<> 154:37f96f9d4de2 126 kTPM_Trigger_Select_15
<> 154:37f96f9d4de2 127 } tpm_trigger_select_t;
<> 154:37f96f9d4de2 128
<> 154:37f96f9d4de2 129 #if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
<> 154:37f96f9d4de2 130 /*!
<> 154:37f96f9d4de2 131 * @brief Trigger source options available
<> 154:37f96f9d4de2 132 *
<> 154:37f96f9d4de2 133 * @note This selection is available only on some SoC's. For SoC's without this selection, the only
<> 154:37f96f9d4de2 134 * trigger source available is internal triger.
<> 154:37f96f9d4de2 135 */
<> 154:37f96f9d4de2 136 typedef enum _tpm_trigger_source
<> 154:37f96f9d4de2 137 {
<> 154:37f96f9d4de2 138 kTPM_TriggerSource_External = 0U, /*!< Use external trigger input */
<> 154:37f96f9d4de2 139 kTPM_TriggerSource_Internal /*!< Use internal trigger */
<> 154:37f96f9d4de2 140 } tpm_trigger_source_t;
<> 154:37f96f9d4de2 141 #endif
<> 154:37f96f9d4de2 142
<> 154:37f96f9d4de2 143 /*! @brief TPM output compare modes */
<> 154:37f96f9d4de2 144 typedef enum _tpm_output_compare_mode
<> 154:37f96f9d4de2 145 {
<> 154:37f96f9d4de2 146 kTPM_NoOutputSignal = (1U << TPM_CnSC_MSA_SHIFT), /*!< No channel output when counter reaches CnV */
<> 154:37f96f9d4de2 147 kTPM_ToggleOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)), /*!< Toggle output */
<> 154:37f96f9d4de2 148 kTPM_ClearOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT)), /*!< Clear output */
<> 154:37f96f9d4de2 149 kTPM_SetOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (3U << TPM_CnSC_ELSA_SHIFT)), /*!< Set output */
<> 154:37f96f9d4de2 150 kTPM_HighPulseOutput = ((3U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)), /*!< Pulse output high */
<> 154:37f96f9d4de2 151 kTPM_LowPulseOutput = ((3U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT)) /*!< Pulse output low */
<> 154:37f96f9d4de2 152 } tpm_output_compare_mode_t;
<> 154:37f96f9d4de2 153
<> 154:37f96f9d4de2 154 /*! @brief TPM input capture edge */
<> 154:37f96f9d4de2 155 typedef enum _tpm_input_capture_edge
<> 154:37f96f9d4de2 156 {
<> 154:37f96f9d4de2 157 kTPM_RisingEdge = (1U << TPM_CnSC_ELSA_SHIFT), /*!< Capture on rising edge only */
<> 154:37f96f9d4de2 158 kTPM_FallingEdge = (2U << TPM_CnSC_ELSA_SHIFT), /*!< Capture on falling edge only */
<> 154:37f96f9d4de2 159 kTPM_RiseAndFallEdge = (3U << TPM_CnSC_ELSA_SHIFT) /*!< Capture on rising or falling edge */
<> 154:37f96f9d4de2 160 } tpm_input_capture_edge_t;
<> 154:37f96f9d4de2 161
<> 154:37f96f9d4de2 162 #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
<> 154:37f96f9d4de2 163 /*!
<> 154:37f96f9d4de2 164 * @brief TPM dual edge capture parameters
<> 154:37f96f9d4de2 165 *
<> 154:37f96f9d4de2 166 * @note This mode is available only on some SoC's.
<> 154:37f96f9d4de2 167 */
<> 154:37f96f9d4de2 168 typedef struct _tpm_dual_edge_capture_param
<> 154:37f96f9d4de2 169 {
<> 154:37f96f9d4de2 170 bool enableSwap; /*!< true: Use channel n+1 input, channel n input is ignored;
<> 154:37f96f9d4de2 171 false: Use channel n input, channel n+1 input is ignored */
<> 154:37f96f9d4de2 172 tpm_input_capture_edge_t currChanEdgeMode; /*!< Input capture edge select for channel n */
<> 154:37f96f9d4de2 173 tpm_input_capture_edge_t nextChanEdgeMode; /*!< Input capture edge select for channel n+1 */
<> 154:37f96f9d4de2 174 } tpm_dual_edge_capture_param_t;
<> 154:37f96f9d4de2 175 #endif
<> 154:37f96f9d4de2 176
<> 154:37f96f9d4de2 177 #if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
<> 154:37f96f9d4de2 178 /*!
<> 154:37f96f9d4de2 179 * @brief TPM quadrature decode modes
<> 154:37f96f9d4de2 180 *
<> 154:37f96f9d4de2 181 * @note This mode is available only on some SoC's.
<> 154:37f96f9d4de2 182 */
<> 154:37f96f9d4de2 183 typedef enum _tpm_quad_decode_mode
<> 154:37f96f9d4de2 184 {
<> 154:37f96f9d4de2 185 kTPM_QuadPhaseEncode = 0U, /*!< Phase A and Phase B encoding mode */
<> 154:37f96f9d4de2 186 kTPM_QuadCountAndDir /*!< Count and direction encoding mode */
<> 154:37f96f9d4de2 187 } tpm_quad_decode_mode_t;
<> 154:37f96f9d4de2 188
<> 154:37f96f9d4de2 189 /*! @brief TPM quadrature phase polarities */
<> 154:37f96f9d4de2 190 typedef enum _tpm_phase_polarity
<> 154:37f96f9d4de2 191 {
<> 154:37f96f9d4de2 192 kTPM_QuadPhaseNormal = 0U, /*!< Phase input signal is not inverted */
<> 154:37f96f9d4de2 193 kTPM_QuadPhaseInvert /*!< Phase input signal is inverted */
<> 154:37f96f9d4de2 194 } tpm_phase_polarity_t;
<> 154:37f96f9d4de2 195
<> 154:37f96f9d4de2 196 /*! @brief TPM quadrature decode phase parameters */
<> 154:37f96f9d4de2 197 typedef struct _tpm_phase_param
<> 154:37f96f9d4de2 198 {
<> 154:37f96f9d4de2 199 uint32_t phaseFilterVal; /*!< Filter value, filter is disabled when the value is zero */
<> 154:37f96f9d4de2 200 tpm_phase_polarity_t phasePolarity; /*!< Phase polarity */
<> 154:37f96f9d4de2 201 } tpm_phase_params_t;
<> 154:37f96f9d4de2 202 #endif
<> 154:37f96f9d4de2 203
<> 154:37f96f9d4de2 204 /*! @brief TPM clock source selection*/
<> 154:37f96f9d4de2 205 typedef enum _tpm_clock_source
<> 154:37f96f9d4de2 206 {
<> 154:37f96f9d4de2 207 kTPM_SystemClock = 1U, /*!< System clock */
<> 154:37f96f9d4de2 208 kTPM_ExternalClock /*!< External clock */
<> 154:37f96f9d4de2 209 } tpm_clock_source_t;
<> 154:37f96f9d4de2 210
<> 154:37f96f9d4de2 211 /*! @brief TPM prescale value selection for the clock source*/
<> 154:37f96f9d4de2 212 typedef enum _tpm_clock_prescale
<> 154:37f96f9d4de2 213 {
<> 154:37f96f9d4de2 214 kTPM_Prescale_Divide_1 = 0U, /*!< Divide by 1 */
<> 154:37f96f9d4de2 215 kTPM_Prescale_Divide_2, /*!< Divide by 2 */
<> 154:37f96f9d4de2 216 kTPM_Prescale_Divide_4, /*!< Divide by 4 */
<> 154:37f96f9d4de2 217 kTPM_Prescale_Divide_8, /*!< Divide by 8 */
<> 154:37f96f9d4de2 218 kTPM_Prescale_Divide_16, /*!< Divide by 16 */
<> 154:37f96f9d4de2 219 kTPM_Prescale_Divide_32, /*!< Divide by 32 */
<> 154:37f96f9d4de2 220 kTPM_Prescale_Divide_64, /*!< Divide by 64 */
<> 154:37f96f9d4de2 221 kTPM_Prescale_Divide_128 /*!< Divide by 128 */
<> 154:37f96f9d4de2 222 } tpm_clock_prescale_t;
<> 154:37f96f9d4de2 223
<> 154:37f96f9d4de2 224 /*!
<> 154:37f96f9d4de2 225 * @brief TPM config structure
<> 154:37f96f9d4de2 226 *
<> 154:37f96f9d4de2 227 * This structure holds the configuration settings for the TPM peripheral. To initialize this
<> 154:37f96f9d4de2 228 * structure to reasonable defaults, call the TPM_GetDefaultConfig() function and pass a
<> 154:37f96f9d4de2 229 * pointer to your config structure instance.
<> 154:37f96f9d4de2 230 *
<> 154:37f96f9d4de2 231 * The config struct can be made const so it resides in flash
<> 154:37f96f9d4de2 232 */
<> 154:37f96f9d4de2 233 typedef struct _tpm_config
<> 154:37f96f9d4de2 234 {
<> 154:37f96f9d4de2 235 tpm_clock_prescale_t prescale; /*!< Select TPM clock prescale value */
<> 154:37f96f9d4de2 236 bool useGlobalTimeBase; /*!< true: Use of an external global time base is enabled;
<> 154:37f96f9d4de2 237 false: disabled */
<> 154:37f96f9d4de2 238 tpm_trigger_select_t triggerSelect; /*!< Input trigger to use for controlling the counter operation */
<> 154:37f96f9d4de2 239 #if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
<> 154:37f96f9d4de2 240 tpm_trigger_source_t triggerSource; /*!< Decides if we use external or internal trigger. */
<> 154:37f96f9d4de2 241 #endif
<> 154:37f96f9d4de2 242 bool enableDoze; /*!< true: TPM counter is paused in doze mode;
<> 154:37f96f9d4de2 243 false: TPM counter continues in doze mode */
<> 154:37f96f9d4de2 244 bool enableDebugMode; /*!< true: TPM counter continues in debug mode;
<> 154:37f96f9d4de2 245 false: TPM counter is paused in debug mode */
<> 154:37f96f9d4de2 246 bool enableReloadOnTrigger; /*!< true: TPM counter is reloaded on trigger;
<> 154:37f96f9d4de2 247 false: TPM counter not reloaded */
<> 154:37f96f9d4de2 248 bool enableStopOnOverflow; /*!< true: TPM counter stops after overflow;
<> 154:37f96f9d4de2 249 false: TPM counter continues running after overflow */
<> 154:37f96f9d4de2 250 bool enableStartOnTrigger; /*!< true: TPM counter only starts when a trigger is detected;
<> 154:37f96f9d4de2 251 false: TPM counter starts immediately */
<> 154:37f96f9d4de2 252 #if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER
<> 154:37f96f9d4de2 253 bool enablePauseOnTrigger; /*!< true: TPM counter will pause while trigger remains asserted;
<> 154:37f96f9d4de2 254 false: TPM counter continues running */
<> 154:37f96f9d4de2 255 #endif
<> 154:37f96f9d4de2 256 } tpm_config_t;
<> 154:37f96f9d4de2 257
<> 154:37f96f9d4de2 258 /*! @brief List of TPM interrupts */
<> 154:37f96f9d4de2 259 typedef enum _tpm_interrupt_enable
<> 154:37f96f9d4de2 260 {
<> 154:37f96f9d4de2 261 kTPM_Chnl0InterruptEnable = (1U << 0), /*!< Channel 0 interrupt.*/
<> 154:37f96f9d4de2 262 kTPM_Chnl1InterruptEnable = (1U << 1), /*!< Channel 1 interrupt.*/
<> 154:37f96f9d4de2 263 kTPM_Chnl2InterruptEnable = (1U << 2), /*!< Channel 2 interrupt.*/
<> 154:37f96f9d4de2 264 kTPM_Chnl3InterruptEnable = (1U << 3), /*!< Channel 3 interrupt.*/
<> 154:37f96f9d4de2 265 kTPM_Chnl4InterruptEnable = (1U << 4), /*!< Channel 4 interrupt.*/
<> 154:37f96f9d4de2 266 kTPM_Chnl5InterruptEnable = (1U << 5), /*!< Channel 5 interrupt.*/
<> 154:37f96f9d4de2 267 kTPM_Chnl6InterruptEnable = (1U << 6), /*!< Channel 6 interrupt.*/
<> 154:37f96f9d4de2 268 kTPM_Chnl7InterruptEnable = (1U << 7), /*!< Channel 7 interrupt.*/
<> 154:37f96f9d4de2 269 kTPM_TimeOverflowInterruptEnable = (1U << 8) /*!< Time overflow interrupt.*/
<> 154:37f96f9d4de2 270 } tpm_interrupt_enable_t;
<> 154:37f96f9d4de2 271
<> 154:37f96f9d4de2 272 /*! @brief List of TPM flags */
<> 154:37f96f9d4de2 273 typedef enum _tpm_status_flags
<> 154:37f96f9d4de2 274 {
<> 154:37f96f9d4de2 275 kTPM_Chnl0Flag = (1U << 0), /*!< Channel 0 flag */
<> 154:37f96f9d4de2 276 kTPM_Chnl1Flag = (1U << 1), /*!< Channel 1 flag */
<> 154:37f96f9d4de2 277 kTPM_Chnl2Flag = (1U << 2), /*!< Channel 2 flag */
<> 154:37f96f9d4de2 278 kTPM_Chnl3Flag = (1U << 3), /*!< Channel 3 flag */
<> 154:37f96f9d4de2 279 kTPM_Chnl4Flag = (1U << 4), /*!< Channel 4 flag */
<> 154:37f96f9d4de2 280 kTPM_Chnl5Flag = (1U << 5), /*!< Channel 5 flag */
<> 154:37f96f9d4de2 281 kTPM_Chnl6Flag = (1U << 6), /*!< Channel 6 flag */
<> 154:37f96f9d4de2 282 kTPM_Chnl7Flag = (1U << 7), /*!< Channel 7 flag */
<> 154:37f96f9d4de2 283 kTPM_TimeOverflowFlag = (1U << 8) /*!< Time overflow flag */
<> 154:37f96f9d4de2 284 } tpm_status_flags_t;
<> 154:37f96f9d4de2 285
<> 154:37f96f9d4de2 286 /*******************************************************************************
<> 154:37f96f9d4de2 287 * API
<> 154:37f96f9d4de2 288 ******************************************************************************/
<> 154:37f96f9d4de2 289
<> 154:37f96f9d4de2 290 #if defined(__cplusplus)
<> 154:37f96f9d4de2 291 extern "C" {
<> 154:37f96f9d4de2 292 #endif
<> 154:37f96f9d4de2 293
<> 154:37f96f9d4de2 294 /*!
<> 154:37f96f9d4de2 295 * @name Initialization and deinitialization
<> 154:37f96f9d4de2 296 * @{
<> 154:37f96f9d4de2 297 */
<> 154:37f96f9d4de2 298
<> 154:37f96f9d4de2 299 /*!
<> 154:37f96f9d4de2 300 * @brief Ungates the TPM clock and configures the peripheral for basic operation.
<> 154:37f96f9d4de2 301 *
<> 154:37f96f9d4de2 302 * @note This API should be called at the beginning of the application using the TPM driver.
<> 154:37f96f9d4de2 303 *
<> 154:37f96f9d4de2 304 * @param base TPM peripheral base address
<> 154:37f96f9d4de2 305 * @param config Pointer to user's TPM config structure.
<> 154:37f96f9d4de2 306 */
<> 154:37f96f9d4de2 307 void TPM_Init(TPM_Type *base, const tpm_config_t *config);
<> 154:37f96f9d4de2 308
<> 154:37f96f9d4de2 309 /*!
<> 154:37f96f9d4de2 310 * @brief Stops the counter and gates the TPM clock
<> 154:37f96f9d4de2 311 *
<> 154:37f96f9d4de2 312 * @param base TPM peripheral base address
<> 154:37f96f9d4de2 313 */
<> 154:37f96f9d4de2 314 void TPM_Deinit(TPM_Type *base);
<> 154:37f96f9d4de2 315
<> 154:37f96f9d4de2 316 /*!
<> 154:37f96f9d4de2 317 * @brief Fill in the TPM config struct with the default settings
<> 154:37f96f9d4de2 318 *
<> 154:37f96f9d4de2 319 * The default values are:
<> 154:37f96f9d4de2 320 * @code
<> 154:37f96f9d4de2 321 * config->prescale = kTPM_Prescale_Divide_1;
<> 154:37f96f9d4de2 322 * config->useGlobalTimeBase = false;
<> 154:37f96f9d4de2 323 * config->dozeEnable = false;
<> 154:37f96f9d4de2 324 * config->dbgMode = false;
<> 154:37f96f9d4de2 325 * config->enableReloadOnTrigger = false;
<> 154:37f96f9d4de2 326 * config->enableStopOnOverflow = false;
<> 154:37f96f9d4de2 327 * config->enableStartOnTrigger = false;
<> 154:37f96f9d4de2 328 *#if FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER
<> 154:37f96f9d4de2 329 * config->enablePauseOnTrigger = false;
<> 154:37f96f9d4de2 330 *#endif
<> 154:37f96f9d4de2 331 * config->triggerSelect = kTPM_Trigger_Select_0;
<> 154:37f96f9d4de2 332 *#if FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
<> 154:37f96f9d4de2 333 * config->triggerSource = kTPM_TriggerSource_External;
<> 154:37f96f9d4de2 334 *#endif
<> 154:37f96f9d4de2 335 * @endcode
<> 154:37f96f9d4de2 336 * @param config Pointer to user's TPM config structure.
<> 154:37f96f9d4de2 337 */
<> 154:37f96f9d4de2 338 void TPM_GetDefaultConfig(tpm_config_t *config);
<> 154:37f96f9d4de2 339
<> 154:37f96f9d4de2 340 /*! @}*/
<> 154:37f96f9d4de2 341
<> 154:37f96f9d4de2 342 /*!
<> 154:37f96f9d4de2 343 * @name Channel mode operations
<> 154:37f96f9d4de2 344 * @{
<> 154:37f96f9d4de2 345 */
<> 154:37f96f9d4de2 346
<> 154:37f96f9d4de2 347 /*!
<> 154:37f96f9d4de2 348 * @brief Configures the PWM signal parameters
<> 154:37f96f9d4de2 349 *
<> 154:37f96f9d4de2 350 * User calls this function to configure the PWM signals period, mode, dutycycle and edge. Use this
<> 154:37f96f9d4de2 351 * function to configure all the TPM channels that will be used to output a PWM signal
<> 154:37f96f9d4de2 352 *
<> 154:37f96f9d4de2 353 * @param base TPM peripheral base address
<> 154:37f96f9d4de2 354 * @param chnlParams Array of PWM channel parameters to configure the channel(s)
<> 154:37f96f9d4de2 355 * @param numOfChnls Number of channels to configure, this should be the size of the array passed in
<> 154:37f96f9d4de2 356 * @param mode PWM operation mode, options available in enumeration ::tpm_pwm_mode_t
<> 154:37f96f9d4de2 357 * @param pwmFreq_Hz PWM signal frequency in Hz
<> 154:37f96f9d4de2 358 * @param srcClock_Hz TPM counter clock in Hz
<> 154:37f96f9d4de2 359 *
<> 154:37f96f9d4de2 360 * @return kStatus_Success if the PWM setup was successful,
<> 154:37f96f9d4de2 361 * kStatus_Error on failure
<> 154:37f96f9d4de2 362 */
<> 154:37f96f9d4de2 363 status_t TPM_SetupPwm(TPM_Type *base,
<> 154:37f96f9d4de2 364 const tpm_chnl_pwm_signal_param_t *chnlParams,
<> 154:37f96f9d4de2 365 uint8_t numOfChnls,
<> 154:37f96f9d4de2 366 tpm_pwm_mode_t mode,
<> 154:37f96f9d4de2 367 uint32_t pwmFreq_Hz,
<> 154:37f96f9d4de2 368 uint32_t srcClock_Hz);
<> 154:37f96f9d4de2 369
<> 154:37f96f9d4de2 370 /*!
<> 154:37f96f9d4de2 371 * @brief Update the duty cycle of an active PWM signal
<> 154:37f96f9d4de2 372 *
<> 154:37f96f9d4de2 373 * @param base TPM peripheral base address
<> 154:37f96f9d4de2 374 * @param chnlNumber The channel number. In combined mode, this represents
<> 154:37f96f9d4de2 375 * the channel pair number
<> 154:37f96f9d4de2 376 * @param currentPwmMode The current PWM mode set during PWM setup
<> 154:37f96f9d4de2 377 * @param dutyCyclePercent New PWM pulse width, value should be between 0 to 100
<> 154:37f96f9d4de2 378 * 0=inactive signal(0% duty cycle)...
<> 154:37f96f9d4de2 379 * 100=active signal (100% duty cycle)
<> 154:37f96f9d4de2 380 */
<> 154:37f96f9d4de2 381 void TPM_UpdatePwmDutycycle(TPM_Type *base,
<> 154:37f96f9d4de2 382 tpm_chnl_t chnlNumber,
<> 154:37f96f9d4de2 383 tpm_pwm_mode_t currentPwmMode,
<> 154:37f96f9d4de2 384 uint8_t dutyCyclePercent);
<> 154:37f96f9d4de2 385
<> 154:37f96f9d4de2 386 /*!
<> 154:37f96f9d4de2 387 * @brief Update the edge level selection for a channel
<> 154:37f96f9d4de2 388 *
<> 154:37f96f9d4de2 389 * @param base TPM peripheral base address
<> 154:37f96f9d4de2 390 * @param chnlNumber The channel number
<> 154:37f96f9d4de2 391 * @param level The level to be set to the ELSnB:ELSnA field; valid values are 00, 01, 10, 11.
<> 154:37f96f9d4de2 392 * See the appropriate SoC reference manual for details about this field.
<> 154:37f96f9d4de2 393 */
<> 154:37f96f9d4de2 394 void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t level);
<> 154:37f96f9d4de2 395
<> 154:37f96f9d4de2 396 /*!
<> 154:37f96f9d4de2 397 * @brief Enables capturing an input signal on the channel using the function parameters.
<> 154:37f96f9d4de2 398 *
<> 154:37f96f9d4de2 399 * When the edge specified in the captureMode argument occurs on the channel, the TPM counter is captured into
<> 154:37f96f9d4de2 400 * the CnV register. The user has to read the CnV register separately to get this value.
<> 154:37f96f9d4de2 401 *
<> 154:37f96f9d4de2 402 * @param base TPM peripheral base address
<> 154:37f96f9d4de2 403 * @param chnlNumber The channel number
<> 154:37f96f9d4de2 404 * @param captureMode Specifies which edge to capture
<> 154:37f96f9d4de2 405 */
<> 154:37f96f9d4de2 406 void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capture_edge_t captureMode);
<> 154:37f96f9d4de2 407
<> 154:37f96f9d4de2 408 /*!
<> 154:37f96f9d4de2 409 * @brief Configures the TPM to generate timed pulses.
<> 154:37f96f9d4de2 410 *
<> 154:37f96f9d4de2 411 * When the TPM counter matches the value of compareVal argument (this is written into CnV reg), the channel
<> 154:37f96f9d4de2 412 * output is changed based on what is specified in the compareMode argument.
<> 154:37f96f9d4de2 413 *
<> 154:37f96f9d4de2 414 * @param base TPM peripheral base address
<> 154:37f96f9d4de2 415 * @param chnlNumber The channel number
<> 154:37f96f9d4de2 416 * @param compareMode Action to take on the channel output when the compare condition is met
<> 154:37f96f9d4de2 417 * @param compareValue Value to be programmed in the CnV register.
<> 154:37f96f9d4de2 418 */
<> 154:37f96f9d4de2 419 void TPM_SetupOutputCompare(TPM_Type *base,
<> 154:37f96f9d4de2 420 tpm_chnl_t chnlNumber,
<> 154:37f96f9d4de2 421 tpm_output_compare_mode_t compareMode,
<> 154:37f96f9d4de2 422 uint32_t compareValue);
<> 154:37f96f9d4de2 423
<> 154:37f96f9d4de2 424 #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
<> 154:37f96f9d4de2 425 /*!
<> 154:37f96f9d4de2 426 * @brief Configures the dual edge capture mode of the TPM.
<> 154:37f96f9d4de2 427 *
<> 154:37f96f9d4de2 428 * This function allows to measure a pulse width of the signal on the input of channel of a
<> 154:37f96f9d4de2 429 * channel pair. The filter function is disabled if the filterVal argument passed is zero.
<> 154:37f96f9d4de2 430 *
<> 154:37f96f9d4de2 431 * @param base TPM peripheral base address
<> 154:37f96f9d4de2 432 * @param chnlPairNumber The TPM channel pair number; options are 0, 1, 2, 3
<> 154:37f96f9d4de2 433 * @param edgeParam Sets up the dual edge capture function
<> 154:37f96f9d4de2 434 * @param filterValue Filter value, specify 0 to disable filter.
<> 154:37f96f9d4de2 435 */
<> 154:37f96f9d4de2 436 void TPM_SetupDualEdgeCapture(TPM_Type *base,
<> 154:37f96f9d4de2 437 tpm_chnl_t chnlPairNumber,
<> 154:37f96f9d4de2 438 const tpm_dual_edge_capture_param_t *edgeParam,
<> 154:37f96f9d4de2 439 uint32_t filterValue);
<> 154:37f96f9d4de2 440 #endif
<> 154:37f96f9d4de2 441
<> 154:37f96f9d4de2 442 #if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
<> 154:37f96f9d4de2 443 /*!
<> 154:37f96f9d4de2 444 * @brief Configures the parameters and activates the quadrature decode mode.
<> 154:37f96f9d4de2 445 *
<> 154:37f96f9d4de2 446 * @param base TPM peripheral base address
<> 154:37f96f9d4de2 447 * @param phaseAParams Phase A configuration parameters
<> 154:37f96f9d4de2 448 * @param phaseBParams Phase B configuration parameters
<> 154:37f96f9d4de2 449 * @param quadMode Selects encoding mode used in quadrature decoder mode
<> 154:37f96f9d4de2 450 */
<> 154:37f96f9d4de2 451 void TPM_SetupQuadDecode(TPM_Type *base,
<> 154:37f96f9d4de2 452 const tpm_phase_params_t *phaseAParams,
<> 154:37f96f9d4de2 453 const tpm_phase_params_t *phaseBParams,
<> 154:37f96f9d4de2 454 tpm_quad_decode_mode_t quadMode);
<> 154:37f96f9d4de2 455 #endif
<> 154:37f96f9d4de2 456
<> 154:37f96f9d4de2 457 /*! @}*/
<> 154:37f96f9d4de2 458
<> 154:37f96f9d4de2 459 /*!
<> 154:37f96f9d4de2 460 * @name Interrupt Interface
<> 154:37f96f9d4de2 461 * @{
<> 154:37f96f9d4de2 462 */
<> 154:37f96f9d4de2 463
<> 154:37f96f9d4de2 464 /*!
<> 154:37f96f9d4de2 465 * @brief Enables the selected TPM interrupts.
<> 154:37f96f9d4de2 466 *
<> 154:37f96f9d4de2 467 * @param base TPM peripheral base address
<> 154:37f96f9d4de2 468 * @param mask The interrupts to enable. This is a logical OR of members of the
<> 154:37f96f9d4de2 469 * enumeration ::tpm_interrupt_enable_t
<> 154:37f96f9d4de2 470 */
<> 154:37f96f9d4de2 471 void TPM_EnableInterrupts(TPM_Type *base, uint32_t mask);
<> 154:37f96f9d4de2 472
<> 154:37f96f9d4de2 473 /*!
<> 154:37f96f9d4de2 474 * @brief Disables the selected TPM interrupts.
<> 154:37f96f9d4de2 475 *
<> 154:37f96f9d4de2 476 * @param base TPM peripheral base address
<> 154:37f96f9d4de2 477 * @param mask The interrupts to disable. This is a logical OR of members of the
<> 154:37f96f9d4de2 478 * enumeration ::tpm_interrupt_enable_t
<> 154:37f96f9d4de2 479 */
<> 154:37f96f9d4de2 480 void TPM_DisableInterrupts(TPM_Type *base, uint32_t mask);
<> 154:37f96f9d4de2 481
<> 154:37f96f9d4de2 482 /*!
<> 154:37f96f9d4de2 483 * @brief Gets the enabled TPM interrupts.
<> 154:37f96f9d4de2 484 *
<> 154:37f96f9d4de2 485 * @param base TPM peripheral base address
<> 154:37f96f9d4de2 486 *
<> 154:37f96f9d4de2 487 * @return The enabled interrupts. This is the logical OR of members of the
<> 154:37f96f9d4de2 488 * enumeration ::tpm_interrupt_enable_t
<> 154:37f96f9d4de2 489 */
<> 154:37f96f9d4de2 490 uint32_t TPM_GetEnabledInterrupts(TPM_Type *base);
<> 154:37f96f9d4de2 491
<> 154:37f96f9d4de2 492 /*! @}*/
<> 154:37f96f9d4de2 493
<> 154:37f96f9d4de2 494 /*!
<> 154:37f96f9d4de2 495 * @name Status Interface
<> 154:37f96f9d4de2 496 * @{
<> 154:37f96f9d4de2 497 */
<> 154:37f96f9d4de2 498
<> 154:37f96f9d4de2 499 /*!
<> 154:37f96f9d4de2 500 * @brief Gets the TPM status flags
<> 154:37f96f9d4de2 501 *
<> 154:37f96f9d4de2 502 * @param base TPM peripheral base address
<> 154:37f96f9d4de2 503 *
<> 154:37f96f9d4de2 504 * @return The status flags. This is the logical OR of members of the
<> 154:37f96f9d4de2 505 * enumeration ::tpm_status_flags_t
<> 154:37f96f9d4de2 506 */
<> 154:37f96f9d4de2 507 static inline uint32_t TPM_GetStatusFlags(TPM_Type *base)
<> 154:37f96f9d4de2 508 {
<> 154:37f96f9d4de2 509 return base->STATUS;
<> 154:37f96f9d4de2 510 }
<> 154:37f96f9d4de2 511
<> 154:37f96f9d4de2 512 /*!
<> 154:37f96f9d4de2 513 * @brief Clears the TPM status flags
<> 154:37f96f9d4de2 514 *
<> 154:37f96f9d4de2 515 * @param base TPM peripheral base address
<> 154:37f96f9d4de2 516 * @param mask The status flags to clear. This is a logical OR of members of the
<> 154:37f96f9d4de2 517 * enumeration ::tpm_status_flags_t
<> 154:37f96f9d4de2 518 */
<> 154:37f96f9d4de2 519 static inline void TPM_ClearStatusFlags(TPM_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 520 {
<> 154:37f96f9d4de2 521 /* Clear the status flags */
<> 154:37f96f9d4de2 522 base->STATUS = mask;
<> 154:37f96f9d4de2 523 }
<> 154:37f96f9d4de2 524
<> 154:37f96f9d4de2 525 /*! @}*/
<> 154:37f96f9d4de2 526
<> 154:37f96f9d4de2 527 /*!
<> 154:37f96f9d4de2 528 * @name Timer Start and Stop
<> 154:37f96f9d4de2 529 * @{
<> 154:37f96f9d4de2 530 */
<> 154:37f96f9d4de2 531
<> 154:37f96f9d4de2 532 /*!
<> 154:37f96f9d4de2 533 * @brief Starts the TPM counter.
<> 154:37f96f9d4de2 534 *
<> 154:37f96f9d4de2 535 *
<> 154:37f96f9d4de2 536 * @param base TPM peripheral base address
<> 154:37f96f9d4de2 537 * @param clockSource TPM clock source; once clock source is set the counter will start running
<> 154:37f96f9d4de2 538 */
<> 154:37f96f9d4de2 539 static inline void TPM_StartTimer(TPM_Type *base, tpm_clock_source_t clockSource)
<> 154:37f96f9d4de2 540 {
<> 154:37f96f9d4de2 541 uint32_t reg = base->SC;
<> 154:37f96f9d4de2 542
<> 154:37f96f9d4de2 543 reg &= ~(TPM_SC_CMOD_MASK);
<> 154:37f96f9d4de2 544 reg |= TPM_SC_CMOD(clockSource);
<> 154:37f96f9d4de2 545 base->SC = reg;
<> 154:37f96f9d4de2 546 }
<> 154:37f96f9d4de2 547
<> 154:37f96f9d4de2 548 /*!
<> 154:37f96f9d4de2 549 * @brief Stops the TPM counter.
<> 154:37f96f9d4de2 550 *
<> 154:37f96f9d4de2 551 * @param base TPM peripheral base address
<> 154:37f96f9d4de2 552 */
<> 154:37f96f9d4de2 553 static inline void TPM_StopTimer(TPM_Type *base)
<> 154:37f96f9d4de2 554 {
<> 154:37f96f9d4de2 555 /* Set clock source to none to disable counter */
<> 154:37f96f9d4de2 556 base->SC &= ~(TPM_SC_CMOD_MASK);
<> 154:37f96f9d4de2 557
<> 154:37f96f9d4de2 558 /* Wait till this reads as zero acknowledging the counter is disabled */
<> 154:37f96f9d4de2 559 while (base->SC & TPM_SC_CMOD_MASK)
<> 154:37f96f9d4de2 560 {
<> 154:37f96f9d4de2 561 }
<> 154:37f96f9d4de2 562 }
<> 154:37f96f9d4de2 563
<> 154:37f96f9d4de2 564 /*! @}*/
<> 154:37f96f9d4de2 565
<> 154:37f96f9d4de2 566 #if defined(FSL_FEATURE_TPM_HAS_GLOBAL) && FSL_FEATURE_TPM_HAS_GLOBAL
<> 154:37f96f9d4de2 567 /*!
<> 154:37f96f9d4de2 568 * @brief Performs a software reset on the TPM module.
<> 154:37f96f9d4de2 569 *
<> 154:37f96f9d4de2 570 * Reset all internal logic and registers, except the Global Register. Remains set until cleared by software..
<> 154:37f96f9d4de2 571 *
<> 154:37f96f9d4de2 572 * @note TPM software reset is available on certain SoC's only
<> 154:37f96f9d4de2 573 *
<> 154:37f96f9d4de2 574 * @param base TPM peripheral base address
<> 154:37f96f9d4de2 575 */
<> 154:37f96f9d4de2 576 static inline void TPM_Reset(TPM_Type *base)
<> 154:37f96f9d4de2 577 {
<> 154:37f96f9d4de2 578 base->GLOBAL |= TPM_GLOBAL_RST_MASK;
<> 154:37f96f9d4de2 579 base->GLOBAL &= ~TPM_GLOBAL_RST_MASK;
<> 154:37f96f9d4de2 580 }
<> 154:37f96f9d4de2 581 #endif
<> 154:37f96f9d4de2 582
<> 154:37f96f9d4de2 583 #if defined(__cplusplus)
<> 154:37f96f9d4de2 584 }
<> 154:37f96f9d4de2 585 #endif
<> 154:37f96f9d4de2 586
<> 154:37f96f9d4de2 587 /*! @}*/
<> 154:37f96f9d4de2 588
<> 154:37f96f9d4de2 589 #endif /* _FSL_TPM_H_ */