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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_lpuart.c@167:356ef919c855, 2017-06-20 (annotated)

Committer:
kkado
Date:
Tue Jun 20 11:06:37 2017 +0000
Revision:
167:356ef919c855
Parent:
154:37f96f9d4de2 
Build 137 with reduced HSE timeout

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30
<> 154:37f96f9d4de2 31 #include "fsl_lpuart.h"
<> 154:37f96f9d4de2 32
<> 154:37f96f9d4de2 33 /*******************************************************************************
<> 154:37f96f9d4de2 34 * Definitions
<> 154:37f96f9d4de2 35 ******************************************************************************/
<> 154:37f96f9d4de2 36 /* LPUART transfer state. */
<> 154:37f96f9d4de2 37 enum _lpuart_transfer_states
<> 154:37f96f9d4de2 38 {
<> 154:37f96f9d4de2 39 kLPUART_TxIdle, /*!< TX idle. */
<> 154:37f96f9d4de2 40 kLPUART_TxBusy, /*!< TX busy. */
<> 154:37f96f9d4de2 41 kLPUART_RxIdle, /*!< RX idle. */
<> 154:37f96f9d4de2 42 kLPUART_RxBusy /*!< RX busy. */
<> 154:37f96f9d4de2 43 };
<> 154:37f96f9d4de2 44
<> 154:37f96f9d4de2 45 /* Typedef for interrupt handler. */
<> 154:37f96f9d4de2 46 typedef void (*lpuart_isr_t)(LPUART_Type *base, lpuart_handle_t *handle);
<> 154:37f96f9d4de2 47
<> 154:37f96f9d4de2 48 /*******************************************************************************
<> 154:37f96f9d4de2 49 * Prototypes
<> 154:37f96f9d4de2 50 ******************************************************************************/
<> 154:37f96f9d4de2 51 /*!
<> 154:37f96f9d4de2 52 * @brief Get the LPUART instance from peripheral base address.
<> 154:37f96f9d4de2 53 *
<> 154:37f96f9d4de2 54 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 55 * @return LPUART instance.
<> 154:37f96f9d4de2 56 */
<> 154:37f96f9d4de2 57 uint32_t LPUART_GetInstance(LPUART_Type *base);
<> 154:37f96f9d4de2 58
<> 154:37f96f9d4de2 59 /*!
<> 154:37f96f9d4de2 60 * @brief Get the length of received data in RX ring buffer.
<> 154:37f96f9d4de2 61 *
<> 154:37f96f9d4de2 62 * @userData handle LPUART handle pointer.
<> 154:37f96f9d4de2 63 * @return Length of received data in RX ring buffer.
<> 154:37f96f9d4de2 64 */
<> 154:37f96f9d4de2 65 static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle);
<> 154:37f96f9d4de2 66
<> 154:37f96f9d4de2 67 /*!
<> 154:37f96f9d4de2 68 * @brief Check whether the RX ring buffer is full.
<> 154:37f96f9d4de2 69 *
<> 154:37f96f9d4de2 70 * @userData handle LPUART handle pointer.
<> 154:37f96f9d4de2 71 * @retval true RX ring buffer is full.
<> 154:37f96f9d4de2 72 * @retval false RX ring buffer is not full.
<> 154:37f96f9d4de2 73 */
<> 154:37f96f9d4de2 74 static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle);
<> 154:37f96f9d4de2 75
<> 154:37f96f9d4de2 76 /*!
<> 154:37f96f9d4de2 77 * @brief Write to TX register using non-blocking method.
<> 154:37f96f9d4de2 78 *
<> 154:37f96f9d4de2 79 * This function writes data to the TX register directly, upper layer must make
<> 154:37f96f9d4de2 80 * sure the TX register is empty or TX FIFO has empty room before calling this function.
<> 154:37f96f9d4de2 81 *
<> 154:37f96f9d4de2 82 * @note This function does not check whether all the data has been sent out to bus,
<> 154:37f96f9d4de2 83 * so before disable TX, check kLPUART_TransmissionCompleteFlag to ensure the TX is
<> 154:37f96f9d4de2 84 * finished.
<> 154:37f96f9d4de2 85 *
<> 154:37f96f9d4de2 86 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 87 * @param data Start addresss of the data to write.
<> 154:37f96f9d4de2 88 * @param length Size of the buffer to be sent.
<> 154:37f96f9d4de2 89 */
<> 154:37f96f9d4de2 90 static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
<> 154:37f96f9d4de2 91
<> 154:37f96f9d4de2 92 /*!
<> 154:37f96f9d4de2 93 * @brief Read RX register using non-blocking method.
<> 154:37f96f9d4de2 94 *
<> 154:37f96f9d4de2 95 * This function reads data from the TX register directly, upper layer must make
<> 154:37f96f9d4de2 96 * sure the RX register is full or TX FIFO has data before calling this function.
<> 154:37f96f9d4de2 97 *
<> 154:37f96f9d4de2 98 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 99 * @param data Start addresss of the buffer to store the received data.
<> 154:37f96f9d4de2 100 * @param length Size of the buffer.
<> 154:37f96f9d4de2 101 */
<> 154:37f96f9d4de2 102 static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length);
<> 154:37f96f9d4de2 103
<> 154:37f96f9d4de2 104 /*******************************************************************************
<> 154:37f96f9d4de2 105 * Variables
<> 154:37f96f9d4de2 106 ******************************************************************************/
<> 154:37f96f9d4de2 107 /* Array of LPUART handle. */
<> 154:37f96f9d4de2 108 static lpuart_handle_t *s_lpuartHandle[FSL_FEATURE_SOC_LPUART_COUNT];
<> 154:37f96f9d4de2 109 /* Array of LPUART peripheral base address. */
<> 154:37f96f9d4de2 110 static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS;
<> 154:37f96f9d4de2 111 /* Array of LPUART IRQ number. */
<> 154:37f96f9d4de2 112 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
<> 154:37f96f9d4de2 113 static const IRQn_Type s_lpuartRxIRQ[] = LPUART_RX_IRQS;
<> 154:37f96f9d4de2 114 static const IRQn_Type s_lpuartTxIRQ[] = LPUART_TX_IRQS;
<> 154:37f96f9d4de2 115 #else
<> 154:37f96f9d4de2 116 static const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS;
<> 154:37f96f9d4de2 117 #endif
<> 154:37f96f9d4de2 118 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
<> 154:37f96f9d4de2 119 /* Array of LPUART clock name. */
<> 154:37f96f9d4de2 120 static const clock_ip_name_t s_lpuartClock[] = LPUART_CLOCKS;
<> 154:37f96f9d4de2 121 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
<> 154:37f96f9d4de2 122 /* LPUART ISR for transactional APIs. */
<> 154:37f96f9d4de2 123 static lpuart_isr_t s_lpuartIsr;
<> 154:37f96f9d4de2 124
<> 154:37f96f9d4de2 125 /*******************************************************************************
<> 154:37f96f9d4de2 126 * Code
<> 154:37f96f9d4de2 127 ******************************************************************************/
<> 154:37f96f9d4de2 128 uint32_t LPUART_GetInstance(LPUART_Type *base)
<> 154:37f96f9d4de2 129 {
<> 154:37f96f9d4de2 130 uint32_t instance;
<> 154:37f96f9d4de2 131
<> 154:37f96f9d4de2 132 /* Find the instance index from base address mappings. */
<> 154:37f96f9d4de2 133 for (instance = 0; instance < FSL_FEATURE_SOC_LPUART_COUNT; instance++)
<> 154:37f96f9d4de2 134 {
<> 154:37f96f9d4de2 135 if (s_lpuartBases[instance] == base)
<> 154:37f96f9d4de2 136 {
<> 154:37f96f9d4de2 137 break;
<> 154:37f96f9d4de2 138 }
<> 154:37f96f9d4de2 139 }
<> 154:37f96f9d4de2 140
<> 154:37f96f9d4de2 141 assert(instance < FSL_FEATURE_SOC_LPUART_COUNT);
<> 154:37f96f9d4de2 142
<> 154:37f96f9d4de2 143 return instance;
<> 154:37f96f9d4de2 144 }
<> 154:37f96f9d4de2 145
<> 154:37f96f9d4de2 146 static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)
<> 154:37f96f9d4de2 147 {
<> 154:37f96f9d4de2 148 assert(handle);
<> 154:37f96f9d4de2 149
<> 154:37f96f9d4de2 150 size_t size;
<> 154:37f96f9d4de2 151
<> 154:37f96f9d4de2 152 if (handle->rxRingBufferTail > handle->rxRingBufferHead)
<> 154:37f96f9d4de2 153 {
<> 154:37f96f9d4de2 154 size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);
<> 154:37f96f9d4de2 155 }
<> 154:37f96f9d4de2 156 else
<> 154:37f96f9d4de2 157 {
<> 154:37f96f9d4de2 158 size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);
<> 154:37f96f9d4de2 159 }
<> 154:37f96f9d4de2 160
<> 154:37f96f9d4de2 161 return size;
<> 154:37f96f9d4de2 162 }
<> 154:37f96f9d4de2 163
<> 154:37f96f9d4de2 164 static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle)
<> 154:37f96f9d4de2 165 {
<> 154:37f96f9d4de2 166 assert(handle);
<> 154:37f96f9d4de2 167
<> 154:37f96f9d4de2 168 bool full;
<> 154:37f96f9d4de2 169
<> 154:37f96f9d4de2 170 if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U))
<> 154:37f96f9d4de2 171 {
<> 154:37f96f9d4de2 172 full = true;
<> 154:37f96f9d4de2 173 }
<> 154:37f96f9d4de2 174 else
<> 154:37f96f9d4de2 175 {
<> 154:37f96f9d4de2 176 full = false;
<> 154:37f96f9d4de2 177 }
<> 154:37f96f9d4de2 178 return full;
<> 154:37f96f9d4de2 179 }
<> 154:37f96f9d4de2 180
<> 154:37f96f9d4de2 181 static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
<> 154:37f96f9d4de2 182 {
<> 154:37f96f9d4de2 183 assert(data);
<> 154:37f96f9d4de2 184
<> 154:37f96f9d4de2 185 size_t i;
<> 154:37f96f9d4de2 186
<> 154:37f96f9d4de2 187 /* The Non Blocking write data API assume user have ensured there is enough space in
<> 154:37f96f9d4de2 188 peripheral to write. */
<> 154:37f96f9d4de2 189 for (i = 0; i < length; i++)
<> 154:37f96f9d4de2 190 {
<> 154:37f96f9d4de2 191 base->DATA = data[i];
<> 154:37f96f9d4de2 192 }
<> 154:37f96f9d4de2 193 }
<> 154:37f96f9d4de2 194
<> 154:37f96f9d4de2 195 static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length)
<> 154:37f96f9d4de2 196 {
<> 154:37f96f9d4de2 197 assert(data);
<> 154:37f96f9d4de2 198
<> 154:37f96f9d4de2 199 size_t i;
<> 154:37f96f9d4de2 200 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
<> 154:37f96f9d4de2 201 uint32_t ctrl = base->CTRL;
<> 154:37f96f9d4de2 202 bool isSevenDataBits =
<> 154:37f96f9d4de2 203 ((ctrl & LPUART_CTRL_M7_MASK) ||
<> 154:37f96f9d4de2 204 ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
<> 154:37f96f9d4de2 205 #endif
<> 154:37f96f9d4de2 206
<> 154:37f96f9d4de2 207 /* The Non Blocking read data API assume user have ensured there is enough space in
<> 154:37f96f9d4de2 208 peripheral to write. */
<> 154:37f96f9d4de2 209 for (i = 0; i < length; i++)
<> 154:37f96f9d4de2 210 {
<> 154:37f96f9d4de2 211 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
<> 154:37f96f9d4de2 212 if (isSevenDataBits)
<> 154:37f96f9d4de2 213 {
<> 154:37f96f9d4de2 214 data[i] = (base->DATA & 0x7F);
<> 154:37f96f9d4de2 215 }
<> 154:37f96f9d4de2 216 else
<> 154:37f96f9d4de2 217 {
<> 154:37f96f9d4de2 218 data[i] = base->DATA;
<> 154:37f96f9d4de2 219 }
<> 154:37f96f9d4de2 220 #else
<> 154:37f96f9d4de2 221 data[i] = base->DATA;
<> 154:37f96f9d4de2 222 #endif
<> 154:37f96f9d4de2 223 }
<> 154:37f96f9d4de2 224 }
<> 154:37f96f9d4de2 225
<> 154:37f96f9d4de2 226 status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)
<> 154:37f96f9d4de2 227 {
<> 154:37f96f9d4de2 228 assert(config);
<> 154:37f96f9d4de2 229 assert(config->baudRate_Bps);
<> 154:37f96f9d4de2 230 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 231 assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark);
<> 154:37f96f9d4de2 232 assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark);
<> 154:37f96f9d4de2 233 #endif
<> 154:37f96f9d4de2 234
<> 154:37f96f9d4de2 235 uint32_t temp;
<> 154:37f96f9d4de2 236 uint16_t sbr, sbrTemp;
<> 154:37f96f9d4de2 237 uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff;
<> 154:37f96f9d4de2 238
<> 154:37f96f9d4de2 239 /* This LPUART instantiation uses a slightly different baud rate calculation
<> 154:37f96f9d4de2 240 * The idea is to use the best OSR (over-sampling rate) possible
<> 154:37f96f9d4de2 241 * Note, OSR is typically hard-set to 16 in other LPUART instantiations
<> 154:37f96f9d4de2 242 * loop to find the best OSR value possible, one that generates minimum baudDiff
<> 154:37f96f9d4de2 243 * iterate through the rest of the supported values of OSR */
<> 154:37f96f9d4de2 244
<> 154:37f96f9d4de2 245 baudDiff = config->baudRate_Bps;
<> 154:37f96f9d4de2 246 osr = 0;
<> 154:37f96f9d4de2 247 sbr = 0;
<> 154:37f96f9d4de2 248 for (osrTemp = 4; osrTemp <= 32; osrTemp++)
<> 154:37f96f9d4de2 249 {
<> 154:37f96f9d4de2 250 /* calculate the temporary sbr value */
<> 154:37f96f9d4de2 251 sbrTemp = (srcClock_Hz / (config->baudRate_Bps * osrTemp));
<> 154:37f96f9d4de2 252 /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
<> 154:37f96f9d4de2 253 if (sbrTemp == 0)
<> 154:37f96f9d4de2 254 {
<> 154:37f96f9d4de2 255 sbrTemp = 1;
<> 154:37f96f9d4de2 256 }
<> 154:37f96f9d4de2 257 /* Calculate the baud rate based on the temporary OSR and SBR values */
<> 154:37f96f9d4de2 258 calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp));
<> 154:37f96f9d4de2 259
<> 154:37f96f9d4de2 260 tempDiff = calculatedBaud - config->baudRate_Bps;
<> 154:37f96f9d4de2 261
<> 154:37f96f9d4de2 262 /* Select the better value between srb and (sbr + 1) */
<> 154:37f96f9d4de2 263 if (tempDiff > (config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)))))
<> 154:37f96f9d4de2 264 {
<> 154:37f96f9d4de2 265 tempDiff = config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)));
<> 154:37f96f9d4de2 266 sbrTemp++;
<> 154:37f96f9d4de2 267 }
<> 154:37f96f9d4de2 268
<> 154:37f96f9d4de2 269 if (tempDiff <= baudDiff)
<> 154:37f96f9d4de2 270 {
<> 154:37f96f9d4de2 271 baudDiff = tempDiff;
<> 154:37f96f9d4de2 272 osr = osrTemp; /* update and store the best OSR value calculated */
<> 154:37f96f9d4de2 273 sbr = sbrTemp; /* update store the best SBR value calculated */
<> 154:37f96f9d4de2 274 }
<> 154:37f96f9d4de2 275 }
<> 154:37f96f9d4de2 276
<> 154:37f96f9d4de2 277 /* Check to see if actual baud rate is within 3% of desired baud rate
<> 154:37f96f9d4de2 278 * based on the best calculate OSR value */
<> 154:37f96f9d4de2 279 if (baudDiff > ((config->baudRate_Bps / 100) * 3))
<> 154:37f96f9d4de2 280 {
<> 154:37f96f9d4de2 281 /* Unacceptable baud rate difference of more than 3%*/
<> 154:37f96f9d4de2 282 return kStatus_LPUART_BaudrateNotSupport;
<> 154:37f96f9d4de2 283 }
<> 154:37f96f9d4de2 284
<> 154:37f96f9d4de2 285 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
<> 154:37f96f9d4de2 286 /* Enable lpuart clock */
<> 154:37f96f9d4de2 287 CLOCK_EnableClock(s_lpuartClock[LPUART_GetInstance(base)]);
<> 154:37f96f9d4de2 288 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
<> 154:37f96f9d4de2 289
<> 154:37f96f9d4de2 290 #if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL
<> 154:37f96f9d4de2 291 /*Reset all internal logic and registers, except the Global Register */
<> 154:37f96f9d4de2 292 LPUART_SoftwareReset(base);
<> 154:37f96f9d4de2 293 #else
<> 154:37f96f9d4de2 294 /* Disable LPUART TX RX before setting. */
<> 154:37f96f9d4de2 295 base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
<> 154:37f96f9d4de2 296 #endif
<> 154:37f96f9d4de2 297
<> 154:37f96f9d4de2 298 temp = base->BAUD;
<> 154:37f96f9d4de2 299
<> 154:37f96f9d4de2 300 /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
<> 154:37f96f9d4de2 301 * If so, then "BOTHEDGE" sampling must be turned on */
<> 154:37f96f9d4de2 302 if ((osr > 3) && (osr < 8))
<> 154:37f96f9d4de2 303 {
<> 154:37f96f9d4de2 304 temp |= LPUART_BAUD_BOTHEDGE_MASK;
<> 154:37f96f9d4de2 305 }
<> 154:37f96f9d4de2 306
<> 154:37f96f9d4de2 307 /* program the osr value (bit value is one less than actual value) */
<> 154:37f96f9d4de2 308 temp &= ~LPUART_BAUD_OSR_MASK;
<> 154:37f96f9d4de2 309 temp |= LPUART_BAUD_OSR(osr - 1);
<> 154:37f96f9d4de2 310
<> 154:37f96f9d4de2 311 /* write the sbr value to the BAUD registers */
<> 154:37f96f9d4de2 312 temp &= ~LPUART_BAUD_SBR_MASK;
<> 154:37f96f9d4de2 313 base->BAUD = temp | LPUART_BAUD_SBR(sbr);
<> 154:37f96f9d4de2 314
<> 154:37f96f9d4de2 315 /* Set bit count and parity mode. */
<> 154:37f96f9d4de2 316 base->BAUD &= ~LPUART_BAUD_M10_MASK;
<> 154:37f96f9d4de2 317
<> 154:37f96f9d4de2 318 temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK);
<> 154:37f96f9d4de2 319
<> 154:37f96f9d4de2 320 temp |= (uint8_t)config->parityMode;
<> 154:37f96f9d4de2 321
<> 154:37f96f9d4de2 322 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
<> 154:37f96f9d4de2 323 if (kLPUART_SevenDataBits == config->dataBitsCount)
<> 154:37f96f9d4de2 324 {
<> 154:37f96f9d4de2 325 if (kLPUART_ParityDisabled != config->parityMode)
<> 154:37f96f9d4de2 326 {
<> 154:37f96f9d4de2 327 temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */
<> 154:37f96f9d4de2 328 }
<> 154:37f96f9d4de2 329 else
<> 154:37f96f9d4de2 330 {
<> 154:37f96f9d4de2 331 temp |= LPUART_CTRL_M7_MASK;
<> 154:37f96f9d4de2 332 }
<> 154:37f96f9d4de2 333 }
<> 154:37f96f9d4de2 334 else
<> 154:37f96f9d4de2 335 #endif
<> 154:37f96f9d4de2 336 {
<> 154:37f96f9d4de2 337 if (kLPUART_ParityDisabled != config->parityMode)
<> 154:37f96f9d4de2 338 {
<> 154:37f96f9d4de2 339 temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */
<> 154:37f96f9d4de2 340 }
<> 154:37f96f9d4de2 341 }
<> 154:37f96f9d4de2 342
<> 154:37f96f9d4de2 343 base->CTRL = temp;
<> 154:37f96f9d4de2 344
<> 154:37f96f9d4de2 345 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
<> 154:37f96f9d4de2 346 /* set stop bit per char */
<> 154:37f96f9d4de2 347 temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK;
<> 154:37f96f9d4de2 348 base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount);
<> 154:37f96f9d4de2 349 #endif
<> 154:37f96f9d4de2 350
<> 154:37f96f9d4de2 351 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 352 /* Set tx/rx WATER watermark */
<> 154:37f96f9d4de2 353 base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16) | config->txFifoWatermark);
<> 154:37f96f9d4de2 354
<> 154:37f96f9d4de2 355 /* Enable tx/rx FIFO */
<> 154:37f96f9d4de2 356 base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK);
<> 154:37f96f9d4de2 357
<> 154:37f96f9d4de2 358 /* Flush FIFO */
<> 154:37f96f9d4de2 359 base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK);
<> 154:37f96f9d4de2 360 #endif
<> 154:37f96f9d4de2 361
<> 154:37f96f9d4de2 362 /* Clear all status flags */
<> 154:37f96f9d4de2 363 temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
<> 154:37f96f9d4de2 364 LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
<> 154:37f96f9d4de2 365
<> 154:37f96f9d4de2 366 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
<> 154:37f96f9d4de2 367 temp |= LPUART_STAT_LBKDIF_MASK;
<> 154:37f96f9d4de2 368 #endif
<> 154:37f96f9d4de2 369
<> 154:37f96f9d4de2 370 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
<> 154:37f96f9d4de2 371 temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
<> 154:37f96f9d4de2 372 #endif
<> 154:37f96f9d4de2 373
<> 154:37f96f9d4de2 374 /* Set data bits order. */
<> 154:37f96f9d4de2 375 if (config->isMsb)
<> 154:37f96f9d4de2 376 {
<> 154:37f96f9d4de2 377 temp |= LPUART_STAT_MSBF_MASK;
<> 154:37f96f9d4de2 378 }
<> 154:37f96f9d4de2 379 else
<> 154:37f96f9d4de2 380 {
<> 154:37f96f9d4de2 381 temp &= ~LPUART_STAT_MSBF_MASK;
<> 154:37f96f9d4de2 382 }
<> 154:37f96f9d4de2 383
<> 154:37f96f9d4de2 384 base->STAT |= temp;
<> 154:37f96f9d4de2 385
<> 154:37f96f9d4de2 386 /* Enable TX/RX base on configure structure. */
<> 154:37f96f9d4de2 387 temp = base->CTRL;
<> 154:37f96f9d4de2 388 if (config->enableTx)
<> 154:37f96f9d4de2 389 {
<> 154:37f96f9d4de2 390 temp |= LPUART_CTRL_TE_MASK;
<> 154:37f96f9d4de2 391 }
<> 154:37f96f9d4de2 392
<> 154:37f96f9d4de2 393 if (config->enableRx)
<> 154:37f96f9d4de2 394 {
<> 154:37f96f9d4de2 395 temp |= LPUART_CTRL_RE_MASK;
<> 154:37f96f9d4de2 396 }
<> 154:37f96f9d4de2 397
<> 154:37f96f9d4de2 398 base->CTRL = temp;
<> 154:37f96f9d4de2 399
<> 154:37f96f9d4de2 400 return kStatus_Success;
<> 154:37f96f9d4de2 401 }
<> 154:37f96f9d4de2 402 void LPUART_Deinit(LPUART_Type *base)
<> 154:37f96f9d4de2 403 {
<> 154:37f96f9d4de2 404 uint32_t temp;
<> 154:37f96f9d4de2 405
<> 154:37f96f9d4de2 406 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 407 /* Wait tx FIFO send out*/
<> 154:37f96f9d4de2 408 while (0 != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT))
<> 154:37f96f9d4de2 409 {
<> 154:37f96f9d4de2 410 }
<> 154:37f96f9d4de2 411 #endif
<> 154:37f96f9d4de2 412 /* Wait last char shoft out */
<> 154:37f96f9d4de2 413 while (0 == (base->STAT & LPUART_STAT_TC_MASK))
<> 154:37f96f9d4de2 414 {
<> 154:37f96f9d4de2 415 }
<> 154:37f96f9d4de2 416
<> 154:37f96f9d4de2 417 /* Clear all status flags */
<> 154:37f96f9d4de2 418 temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
<> 154:37f96f9d4de2 419 LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
<> 154:37f96f9d4de2 420
<> 154:37f96f9d4de2 421 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
<> 154:37f96f9d4de2 422 temp |= LPUART_STAT_LBKDIF_MASK;
<> 154:37f96f9d4de2 423 #endif
<> 154:37f96f9d4de2 424
<> 154:37f96f9d4de2 425 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
<> 154:37f96f9d4de2 426 temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
<> 154:37f96f9d4de2 427 #endif
<> 154:37f96f9d4de2 428
<> 154:37f96f9d4de2 429 base->STAT |= temp;
<> 154:37f96f9d4de2 430
<> 154:37f96f9d4de2 431 /* Disable the module. */
<> 154:37f96f9d4de2 432 base->CTRL = 0;
<> 154:37f96f9d4de2 433
<> 154:37f96f9d4de2 434 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
<> 154:37f96f9d4de2 435 /* Disable lpuart clock */
<> 154:37f96f9d4de2 436 CLOCK_DisableClock(s_lpuartClock[LPUART_GetInstance(base)]);
<> 154:37f96f9d4de2 437 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
<> 154:37f96f9d4de2 438 }
<> 154:37f96f9d4de2 439
<> 154:37f96f9d4de2 440 void LPUART_GetDefaultConfig(lpuart_config_t *config)
<> 154:37f96f9d4de2 441 {
<> 154:37f96f9d4de2 442 assert(config);
<> 154:37f96f9d4de2 443
<> 154:37f96f9d4de2 444 config->baudRate_Bps = 115200U;
<> 154:37f96f9d4de2 445 config->parityMode = kLPUART_ParityDisabled;
<> 154:37f96f9d4de2 446 config->dataBitsCount = kLPUART_EightDataBits;
<> 154:37f96f9d4de2 447 config->isMsb = false;
<> 154:37f96f9d4de2 448 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
<> 154:37f96f9d4de2 449 config->stopBitCount = kLPUART_OneStopBit;
<> 154:37f96f9d4de2 450 #endif
<> 154:37f96f9d4de2 451 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 452 config->txFifoWatermark = 0;
<> 154:37f96f9d4de2 453 config->rxFifoWatermark = 0;
<> 154:37f96f9d4de2 454 #endif
<> 154:37f96f9d4de2 455 config->enableTx = false;
<> 154:37f96f9d4de2 456 config->enableRx = false;
<> 154:37f96f9d4de2 457 }
<> 154:37f96f9d4de2 458
<> 154:37f96f9d4de2 459 status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
<> 154:37f96f9d4de2 460 {
<> 154:37f96f9d4de2 461 assert(baudRate_Bps);
<> 154:37f96f9d4de2 462
<> 154:37f96f9d4de2 463 uint32_t temp, oldCtrl;
<> 154:37f96f9d4de2 464 uint16_t sbr, sbrTemp;
<> 154:37f96f9d4de2 465 uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff;
<> 154:37f96f9d4de2 466
<> 154:37f96f9d4de2 467 /* This LPUART instantiation uses a slightly different baud rate calculation
<> 154:37f96f9d4de2 468 * The idea is to use the best OSR (over-sampling rate) possible
<> 154:37f96f9d4de2 469 * Note, OSR is typically hard-set to 16 in other LPUART instantiations
<> 154:37f96f9d4de2 470 * loop to find the best OSR value possible, one that generates minimum baudDiff
<> 154:37f96f9d4de2 471 * iterate through the rest of the supported values of OSR */
<> 154:37f96f9d4de2 472
<> 154:37f96f9d4de2 473 baudDiff = baudRate_Bps;
<> 154:37f96f9d4de2 474 osr = 0;
<> 154:37f96f9d4de2 475 sbr = 0;
<> 154:37f96f9d4de2 476 for (osrTemp = 4; osrTemp <= 32; osrTemp++)
<> 154:37f96f9d4de2 477 {
<> 154:37f96f9d4de2 478 /* calculate the temporary sbr value */
<> 154:37f96f9d4de2 479 sbrTemp = (srcClock_Hz / (baudRate_Bps * osrTemp));
<> 154:37f96f9d4de2 480 /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
<> 154:37f96f9d4de2 481 if (sbrTemp == 0)
<> 154:37f96f9d4de2 482 {
<> 154:37f96f9d4de2 483 sbrTemp = 1;
<> 154:37f96f9d4de2 484 }
<> 154:37f96f9d4de2 485 /* Calculate the baud rate based on the temporary OSR and SBR values */
<> 154:37f96f9d4de2 486 calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp));
<> 154:37f96f9d4de2 487
<> 154:37f96f9d4de2 488 tempDiff = calculatedBaud - baudRate_Bps;
<> 154:37f96f9d4de2 489
<> 154:37f96f9d4de2 490 /* Select the better value between srb and (sbr + 1) */
<> 154:37f96f9d4de2 491 if (tempDiff > (baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)))))
<> 154:37f96f9d4de2 492 {
<> 154:37f96f9d4de2 493 tempDiff = baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)));
<> 154:37f96f9d4de2 494 sbrTemp++;
<> 154:37f96f9d4de2 495 }
<> 154:37f96f9d4de2 496
<> 154:37f96f9d4de2 497 if (tempDiff <= baudDiff)
<> 154:37f96f9d4de2 498 {
<> 154:37f96f9d4de2 499 baudDiff = tempDiff;
<> 154:37f96f9d4de2 500 osr = osrTemp; /* update and store the best OSR value calculated */
<> 154:37f96f9d4de2 501 sbr = sbrTemp; /* update store the best SBR value calculated */
<> 154:37f96f9d4de2 502 }
<> 154:37f96f9d4de2 503 }
<> 154:37f96f9d4de2 504
<> 154:37f96f9d4de2 505 /* Check to see if actual baud rate is within 3% of desired baud rate
<> 154:37f96f9d4de2 506 * based on the best calculate OSR value */
<> 154:37f96f9d4de2 507 if (baudDiff < ((baudRate_Bps / 100) * 3))
<> 154:37f96f9d4de2 508 {
<> 154:37f96f9d4de2 509 /* Store CTRL before disable Tx and Rx */
<> 154:37f96f9d4de2 510 oldCtrl = base->CTRL;
<> 154:37f96f9d4de2 511
<> 154:37f96f9d4de2 512 /* Disable LPUART TX RX before setting. */
<> 154:37f96f9d4de2 513 base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
<> 154:37f96f9d4de2 514
<> 154:37f96f9d4de2 515 temp = base->BAUD;
<> 154:37f96f9d4de2 516
<> 154:37f96f9d4de2 517 /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
<> 154:37f96f9d4de2 518 * If so, then "BOTHEDGE" sampling must be turned on */
<> 154:37f96f9d4de2 519 if ((osr > 3) && (osr < 8))
<> 154:37f96f9d4de2 520 {
<> 154:37f96f9d4de2 521 temp |= LPUART_BAUD_BOTHEDGE_MASK;
<> 154:37f96f9d4de2 522 }
<> 154:37f96f9d4de2 523
<> 154:37f96f9d4de2 524 /* program the osr value (bit value is one less than actual value) */
<> 154:37f96f9d4de2 525 temp &= ~LPUART_BAUD_OSR_MASK;
<> 154:37f96f9d4de2 526 temp |= LPUART_BAUD_OSR(osr - 1);
<> 154:37f96f9d4de2 527
<> 154:37f96f9d4de2 528 /* write the sbr value to the BAUD registers */
<> 154:37f96f9d4de2 529 temp &= ~LPUART_BAUD_SBR_MASK;
<> 154:37f96f9d4de2 530 base->BAUD = temp | LPUART_BAUD_SBR(sbr);
<> 154:37f96f9d4de2 531
<> 154:37f96f9d4de2 532 /* Restore CTRL. */
<> 154:37f96f9d4de2 533 base->CTRL = oldCtrl;
<> 154:37f96f9d4de2 534
<> 154:37f96f9d4de2 535 return kStatus_Success;
<> 154:37f96f9d4de2 536 }
<> 154:37f96f9d4de2 537 else
<> 154:37f96f9d4de2 538 {
<> 154:37f96f9d4de2 539 /* Unacceptable baud rate difference of more than 3%*/
<> 154:37f96f9d4de2 540 return kStatus_LPUART_BaudrateNotSupport;
<> 154:37f96f9d4de2 541 }
<> 154:37f96f9d4de2 542 }
<> 154:37f96f9d4de2 543
<> 154:37f96f9d4de2 544 void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 545 {
<> 154:37f96f9d4de2 546 base->BAUD |= ((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
<> 154:37f96f9d4de2 547 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 548 base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) |
<> 154:37f96f9d4de2 549 ((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
<> 154:37f96f9d4de2 550 #endif
<> 154:37f96f9d4de2 551 mask &= 0xFFFFFF00U;
<> 154:37f96f9d4de2 552 base->CTRL |= mask;
<> 154:37f96f9d4de2 553 }
<> 154:37f96f9d4de2 554
<> 154:37f96f9d4de2 555 void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 556 {
<> 154:37f96f9d4de2 557 base->BAUD &= ~((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
<> 154:37f96f9d4de2 558 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 559 base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) &
<> 154:37f96f9d4de2 560 ~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
<> 154:37f96f9d4de2 561 #endif
<> 154:37f96f9d4de2 562 mask &= 0xFFFFFF00U;
<> 154:37f96f9d4de2 563 base->CTRL &= ~mask;
<> 154:37f96f9d4de2 564 }
<> 154:37f96f9d4de2 565
<> 154:37f96f9d4de2 566 uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base)
<> 154:37f96f9d4de2 567 {
<> 154:37f96f9d4de2 568 uint32_t temp;
<> 154:37f96f9d4de2 569 temp = (base->BAUD & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)) >> 8;
<> 154:37f96f9d4de2 570 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 571 temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8;
<> 154:37f96f9d4de2 572 #endif
<> 154:37f96f9d4de2 573 temp |= (base->CTRL & 0xFF0C000);
<> 154:37f96f9d4de2 574
<> 154:37f96f9d4de2 575 return temp;
<> 154:37f96f9d4de2 576 }
<> 154:37f96f9d4de2 577
<> 154:37f96f9d4de2 578 uint32_t LPUART_GetStatusFlags(LPUART_Type *base)
<> 154:37f96f9d4de2 579 {
<> 154:37f96f9d4de2 580 uint32_t temp;
<> 154:37f96f9d4de2 581 temp = base->STAT;
<> 154:37f96f9d4de2 582 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 583 temp |= (base->FIFO &
<> 154:37f96f9d4de2 584 (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >>
<> 154:37f96f9d4de2 585 16;
<> 154:37f96f9d4de2 586 #endif
<> 154:37f96f9d4de2 587 return temp;
<> 154:37f96f9d4de2 588 }
<> 154:37f96f9d4de2 589
<> 154:37f96f9d4de2 590 status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 591 {
<> 154:37f96f9d4de2 592 uint32_t temp;
<> 154:37f96f9d4de2 593 status_t status;
<> 154:37f96f9d4de2 594 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 595 temp = (uint32_t)base->FIFO;
<> 154:37f96f9d4de2 596 temp &= (uint32_t)(~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK));
<> 154:37f96f9d4de2 597 temp |= (mask << 16) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK);
<> 154:37f96f9d4de2 598 base->FIFO = temp;
<> 154:37f96f9d4de2 599 #endif
<> 154:37f96f9d4de2 600 temp = (uint32_t)base->STAT;
<> 154:37f96f9d4de2 601 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
<> 154:37f96f9d4de2 602 temp &= (uint32_t)(~(LPUART_STAT_LBKDIF_MASK));
<> 154:37f96f9d4de2 603 temp |= mask & LPUART_STAT_LBKDIF_MASK;
<> 154:37f96f9d4de2 604 #endif
<> 154:37f96f9d4de2 605 temp &= (uint32_t)(~(LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
<> 154:37f96f9d4de2 606 LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK));
<> 154:37f96f9d4de2 607 temp |= mask & (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
<> 154:37f96f9d4de2 608 LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
<> 154:37f96f9d4de2 609 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
<> 154:37f96f9d4de2 610 temp &= (uint32_t)(~(LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK));
<> 154:37f96f9d4de2 611 temp |= mask & (LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK);
<> 154:37f96f9d4de2 612 #endif
<> 154:37f96f9d4de2 613 base->STAT = temp;
<> 154:37f96f9d4de2 614 /* If some flags still pending. */
<> 154:37f96f9d4de2 615 if (mask & LPUART_GetStatusFlags(base))
<> 154:37f96f9d4de2 616 {
<> 154:37f96f9d4de2 617 /* Some flags can only clear or set by the hardware itself, these flags are: kLPUART_TxDataRegEmptyFlag,
<> 154:37f96f9d4de2 618 kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag,
<> 154:37f96f9d4de2 619 kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
<> 154:37f96f9d4de2 620 kLPUART_TxFifoEmptyFlag, kLPUART_RxFifoEmptyFlag. */
<> 154:37f96f9d4de2 621 status = kStatus_LPUART_FlagCannotClearManually; /* flags can not clear manually */
<> 154:37f96f9d4de2 622 }
<> 154:37f96f9d4de2 623 else
<> 154:37f96f9d4de2 624 {
<> 154:37f96f9d4de2 625 status = kStatus_Success;
<> 154:37f96f9d4de2 626 }
<> 154:37f96f9d4de2 627
<> 154:37f96f9d4de2 628 return status;
<> 154:37f96f9d4de2 629 }
<> 154:37f96f9d4de2 630
<> 154:37f96f9d4de2 631 void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
<> 154:37f96f9d4de2 632 {
<> 154:37f96f9d4de2 633 assert(data);
<> 154:37f96f9d4de2 634
<> 154:37f96f9d4de2 635 /* This API can only ensure that the data is written into the data buffer but can't
<> 154:37f96f9d4de2 636 ensure all data in the data buffer are sent into the transmit shift buffer. */
<> 154:37f96f9d4de2 637 while (length--)
<> 154:37f96f9d4de2 638 {
<> 154:37f96f9d4de2 639 while (!(base->STAT & LPUART_STAT_TDRE_MASK))
<> 154:37f96f9d4de2 640 {
<> 154:37f96f9d4de2 641 }
<> 154:37f96f9d4de2 642 base->DATA = *(data++);
<> 154:37f96f9d4de2 643 }
<> 154:37f96f9d4de2 644 }
<> 154:37f96f9d4de2 645
<> 154:37f96f9d4de2 646 status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)
<> 154:37f96f9d4de2 647 {
<> 154:37f96f9d4de2 648 assert(data);
<> 154:37f96f9d4de2 649
<> 154:37f96f9d4de2 650 uint32_t statusFlag;
<> 154:37f96f9d4de2 651 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
<> 154:37f96f9d4de2 652 uint32_t ctrl = base->CTRL;
<> 154:37f96f9d4de2 653 bool isSevenDataBits =
<> 154:37f96f9d4de2 654 ((ctrl & LPUART_CTRL_M7_MASK) ||
<> 154:37f96f9d4de2 655 ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
<> 154:37f96f9d4de2 656 #endif
<> 154:37f96f9d4de2 657
<> 154:37f96f9d4de2 658 while (length--)
<> 154:37f96f9d4de2 659 {
<> 154:37f96f9d4de2 660 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 661 while (0 == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT))
<> 154:37f96f9d4de2 662 #else
<> 154:37f96f9d4de2 663 while (!(base->STAT & LPUART_STAT_RDRF_MASK))
<> 154:37f96f9d4de2 664 #endif
<> 154:37f96f9d4de2 665 {
<> 154:37f96f9d4de2 666 statusFlag = LPUART_GetStatusFlags(base);
<> 154:37f96f9d4de2 667
<> 154:37f96f9d4de2 668 if (statusFlag & kLPUART_RxOverrunFlag)
<> 154:37f96f9d4de2 669 {
<> 154:37f96f9d4de2 670 LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag);
<> 154:37f96f9d4de2 671 return kStatus_LPUART_RxHardwareOverrun;
<> 154:37f96f9d4de2 672 }
<> 154:37f96f9d4de2 673
<> 154:37f96f9d4de2 674 if (statusFlag & kLPUART_NoiseErrorFlag)
<> 154:37f96f9d4de2 675 {
<> 154:37f96f9d4de2 676 LPUART_ClearStatusFlags(base, kLPUART_NoiseErrorFlag);
<> 154:37f96f9d4de2 677 return kStatus_LPUART_NoiseError;
<> 154:37f96f9d4de2 678 }
<> 154:37f96f9d4de2 679
<> 154:37f96f9d4de2 680 if (statusFlag & kLPUART_FramingErrorFlag)
<> 154:37f96f9d4de2 681 {
<> 154:37f96f9d4de2 682 LPUART_ClearStatusFlags(base, kLPUART_FramingErrorFlag);
<> 154:37f96f9d4de2 683 return kStatus_LPUART_FramingError;
<> 154:37f96f9d4de2 684 }
<> 154:37f96f9d4de2 685
<> 154:37f96f9d4de2 686 if (statusFlag & kLPUART_ParityErrorFlag)
<> 154:37f96f9d4de2 687 {
<> 154:37f96f9d4de2 688 LPUART_ClearStatusFlags(base, kLPUART_ParityErrorFlag);
<> 154:37f96f9d4de2 689 return kStatus_LPUART_ParityError;
<> 154:37f96f9d4de2 690 }
<> 154:37f96f9d4de2 691 }
<> 154:37f96f9d4de2 692 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
<> 154:37f96f9d4de2 693 if (isSevenDataBits)
<> 154:37f96f9d4de2 694 {
<> 154:37f96f9d4de2 695 *(data++) = (base->DATA & 0x7F);
<> 154:37f96f9d4de2 696 }
<> 154:37f96f9d4de2 697 else
<> 154:37f96f9d4de2 698 {
<> 154:37f96f9d4de2 699 *(data++) = base->DATA;
<> 154:37f96f9d4de2 700 }
<> 154:37f96f9d4de2 701 #else
<> 154:37f96f9d4de2 702 *(data++) = base->DATA;
<> 154:37f96f9d4de2 703 #endif
<> 154:37f96f9d4de2 704 }
<> 154:37f96f9d4de2 705
<> 154:37f96f9d4de2 706 return kStatus_Success;
<> 154:37f96f9d4de2 707 }
<> 154:37f96f9d4de2 708
<> 154:37f96f9d4de2 709 void LPUART_TransferCreateHandle(LPUART_Type *base,
<> 154:37f96f9d4de2 710 lpuart_handle_t *handle,
<> 154:37f96f9d4de2 711 lpuart_transfer_callback_t callback,
<> 154:37f96f9d4de2 712 void *userData)
<> 154:37f96f9d4de2 713 {
<> 154:37f96f9d4de2 714 assert(handle);
<> 154:37f96f9d4de2 715
<> 154:37f96f9d4de2 716 uint32_t instance;
<> 154:37f96f9d4de2 717 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
<> 154:37f96f9d4de2 718 uint32_t ctrl = base->CTRL;
<> 154:37f96f9d4de2 719 bool isSevenDataBits =
<> 154:37f96f9d4de2 720 ((ctrl & LPUART_CTRL_M7_MASK) ||
<> 154:37f96f9d4de2 721 ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
<> 154:37f96f9d4de2 722 #endif
<> 154:37f96f9d4de2 723
<> 154:37f96f9d4de2 724 /* Zero the handle. */
<> 154:37f96f9d4de2 725 memset(handle, 0, sizeof(lpuart_handle_t));
<> 154:37f96f9d4de2 726
<> 154:37f96f9d4de2 727 /* Set the TX/RX state. */
<> 154:37f96f9d4de2 728 handle->rxState = kLPUART_RxIdle;
<> 154:37f96f9d4de2 729 handle->txState = kLPUART_TxIdle;
<> 154:37f96f9d4de2 730
<> 154:37f96f9d4de2 731 /* Set the callback and user data. */
<> 154:37f96f9d4de2 732 handle->callback = callback;
<> 154:37f96f9d4de2 733 handle->userData = userData;
<> 154:37f96f9d4de2 734
<> 154:37f96f9d4de2 735 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
<> 154:37f96f9d4de2 736 /* Initial seven data bits flag */
<> 154:37f96f9d4de2 737 handle->isSevenDataBits = isSevenDataBits;
<> 154:37f96f9d4de2 738 #endif
<> 154:37f96f9d4de2 739
<> 154:37f96f9d4de2 740 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 741 /* Note:
<> 154:37f96f9d4de2 742 Take care of the RX FIFO, RX interrupt request only assert when received bytes
<> 154:37f96f9d4de2 743 equal or more than RX water mark, there is potential issue if RX water
<> 154:37f96f9d4de2 744 mark larger than 1.
<> 154:37f96f9d4de2 745 For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
<> 154:37f96f9d4de2 746 5 bytes are received. the last byte will be saved in FIFO but not trigger
<> 154:37f96f9d4de2 747 RX interrupt because the water mark is 2.
<> 154:37f96f9d4de2 748 */
<> 154:37f96f9d4de2 749 base->WATER &= (~LPUART_WATER_RXWATER_MASK);
<> 154:37f96f9d4de2 750 #endif
<> 154:37f96f9d4de2 751
<> 154:37f96f9d4de2 752 /* Get instance from peripheral base address. */
<> 154:37f96f9d4de2 753 instance = LPUART_GetInstance(base);
<> 154:37f96f9d4de2 754
<> 154:37f96f9d4de2 755 /* Save the handle in global variables to support the double weak mechanism. */
<> 154:37f96f9d4de2 756 s_lpuartHandle[instance] = handle;
<> 154:37f96f9d4de2 757
<> 154:37f96f9d4de2 758 s_lpuartIsr = LPUART_TransferHandleIRQ;
<> 154:37f96f9d4de2 759
<> 154:37f96f9d4de2 760 /* Enable interrupt in NVIC. */
<> 154:37f96f9d4de2 761 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
<> 154:37f96f9d4de2 762 EnableIRQ(s_lpuartRxIRQ[instance]);
<> 154:37f96f9d4de2 763 EnableIRQ(s_lpuartTxIRQ[instance]);
<> 154:37f96f9d4de2 764 #else
<> 154:37f96f9d4de2 765 EnableIRQ(s_lpuartIRQ[instance]);
<> 154:37f96f9d4de2 766 #endif
<> 154:37f96f9d4de2 767 }
<> 154:37f96f9d4de2 768
<> 154:37f96f9d4de2 769 void LPUART_TransferStartRingBuffer(LPUART_Type *base,
<> 154:37f96f9d4de2 770 lpuart_handle_t *handle,
<> 154:37f96f9d4de2 771 uint8_t *ringBuffer,
<> 154:37f96f9d4de2 772 size_t ringBufferSize)
<> 154:37f96f9d4de2 773 {
<> 154:37f96f9d4de2 774 assert(handle);
<> 154:37f96f9d4de2 775 assert(ringBuffer);
<> 154:37f96f9d4de2 776
<> 154:37f96f9d4de2 777 /* Setup the ring buffer address */
<> 154:37f96f9d4de2 778 handle->rxRingBuffer = ringBuffer;
<> 154:37f96f9d4de2 779 handle->rxRingBufferSize = ringBufferSize;
<> 154:37f96f9d4de2 780 handle->rxRingBufferHead = 0U;
<> 154:37f96f9d4de2 781 handle->rxRingBufferTail = 0U;
<> 154:37f96f9d4de2 782
<> 154:37f96f9d4de2 783 /* Enable the interrupt to accept the data when user need the ring buffer. */
<> 154:37f96f9d4de2 784 LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
<> 154:37f96f9d4de2 785 }
<> 154:37f96f9d4de2 786
<> 154:37f96f9d4de2 787 void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)
<> 154:37f96f9d4de2 788 {
<> 154:37f96f9d4de2 789 assert(handle);
<> 154:37f96f9d4de2 790
<> 154:37f96f9d4de2 791 if (handle->rxState == kLPUART_RxIdle)
<> 154:37f96f9d4de2 792 {
<> 154:37f96f9d4de2 793 LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
<> 154:37f96f9d4de2 794 }
<> 154:37f96f9d4de2 795
<> 154:37f96f9d4de2 796 handle->rxRingBuffer = NULL;
<> 154:37f96f9d4de2 797 handle->rxRingBufferSize = 0U;
<> 154:37f96f9d4de2 798 handle->rxRingBufferHead = 0U;
<> 154:37f96f9d4de2 799 handle->rxRingBufferTail = 0U;
<> 154:37f96f9d4de2 800 }
<> 154:37f96f9d4de2 801
<> 154:37f96f9d4de2 802 status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer)
<> 154:37f96f9d4de2 803 {
<> 154:37f96f9d4de2 804 assert(handle);
<> 154:37f96f9d4de2 805 assert(xfer);
<> 154:37f96f9d4de2 806 assert(xfer->data);
<> 154:37f96f9d4de2 807 assert(xfer->dataSize);
<> 154:37f96f9d4de2 808
<> 154:37f96f9d4de2 809 status_t status;
<> 154:37f96f9d4de2 810
<> 154:37f96f9d4de2 811 /* Return error if current TX busy. */
<> 154:37f96f9d4de2 812 if (kLPUART_TxBusy == handle->txState)
<> 154:37f96f9d4de2 813 {
<> 154:37f96f9d4de2 814 status = kStatus_LPUART_TxBusy;
<> 154:37f96f9d4de2 815 }
<> 154:37f96f9d4de2 816 else
<> 154:37f96f9d4de2 817 {
<> 154:37f96f9d4de2 818 handle->txData = xfer->data;
<> 154:37f96f9d4de2 819 handle->txDataSize = xfer->dataSize;
<> 154:37f96f9d4de2 820 handle->txDataSizeAll = xfer->dataSize;
<> 154:37f96f9d4de2 821 handle->txState = kLPUART_TxBusy;
<> 154:37f96f9d4de2 822
<> 154:37f96f9d4de2 823 /* Enable transmiter interrupt. */
<> 154:37f96f9d4de2 824 LPUART_EnableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable);
<> 154:37f96f9d4de2 825
<> 154:37f96f9d4de2 826 status = kStatus_Success;
<> 154:37f96f9d4de2 827 }
<> 154:37f96f9d4de2 828
<> 154:37f96f9d4de2 829 return status;
<> 154:37f96f9d4de2 830 }
<> 154:37f96f9d4de2 831
<> 154:37f96f9d4de2 832 void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)
<> 154:37f96f9d4de2 833 {
<> 154:37f96f9d4de2 834 assert(handle);
<> 154:37f96f9d4de2 835
<> 154:37f96f9d4de2 836 LPUART_DisableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_TransmissionCompleteInterruptEnable);
<> 154:37f96f9d4de2 837
<> 154:37f96f9d4de2 838 handle->txDataSize = 0;
<> 154:37f96f9d4de2 839 handle->txState = kLPUART_TxIdle;
<> 154:37f96f9d4de2 840 }
<> 154:37f96f9d4de2 841
<> 154:37f96f9d4de2 842 status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
<> 154:37f96f9d4de2 843 {
<> 154:37f96f9d4de2 844 assert(handle);
<> 154:37f96f9d4de2 845 assert(count);
<> 154:37f96f9d4de2 846
<> 154:37f96f9d4de2 847 if (kLPUART_TxIdle == handle->txState)
<> 154:37f96f9d4de2 848 {
<> 154:37f96f9d4de2 849 return kStatus_NoTransferInProgress;
<> 154:37f96f9d4de2 850 }
<> 154:37f96f9d4de2 851
<> 154:37f96f9d4de2 852 *count = handle->txDataSizeAll - handle->txDataSize;
<> 154:37f96f9d4de2 853
<> 154:37f96f9d4de2 854 return kStatus_Success;
<> 154:37f96f9d4de2 855 }
<> 154:37f96f9d4de2 856
<> 154:37f96f9d4de2 857 status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
<> 154:37f96f9d4de2 858 lpuart_handle_t *handle,
<> 154:37f96f9d4de2 859 lpuart_transfer_t *xfer,
<> 154:37f96f9d4de2 860 size_t *receivedBytes)
<> 154:37f96f9d4de2 861 {
<> 154:37f96f9d4de2 862 assert(handle);
<> 154:37f96f9d4de2 863 assert(xfer);
<> 154:37f96f9d4de2 864 assert(xfer->data);
<> 154:37f96f9d4de2 865 assert(xfer->dataSize);
<> 154:37f96f9d4de2 866
<> 154:37f96f9d4de2 867 uint32_t i;
<> 154:37f96f9d4de2 868 status_t status;
<> 154:37f96f9d4de2 869 /* How many bytes to copy from ring buffer to user memory. */
<> 154:37f96f9d4de2 870 size_t bytesToCopy = 0U;
<> 154:37f96f9d4de2 871 /* How many bytes to receive. */
<> 154:37f96f9d4de2 872 size_t bytesToReceive;
<> 154:37f96f9d4de2 873 /* How many bytes currently have received. */
<> 154:37f96f9d4de2 874 size_t bytesCurrentReceived;
<> 154:37f96f9d4de2 875
<> 154:37f96f9d4de2 876 /* How to get data:
<> 154:37f96f9d4de2 877 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
<> 154:37f96f9d4de2 878 to lpuart handle, enable interrupt to store received data to xfer->data. When
<> 154:37f96f9d4de2 879 all data received, trigger callback.
<> 154:37f96f9d4de2 880 2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
<> 154:37f96f9d4de2 881 If there are enough data in ring buffer, copy them to xfer->data and return.
<> 154:37f96f9d4de2 882 If there are not enough data in ring buffer, copy all of them to xfer->data,
<> 154:37f96f9d4de2 883 save the xfer->data remained empty space to lpuart handle, receive data
<> 154:37f96f9d4de2 884 to this empty space and trigger callback when finished. */
<> 154:37f96f9d4de2 885
<> 154:37f96f9d4de2 886 if (kLPUART_RxBusy == handle->rxState)
<> 154:37f96f9d4de2 887 {
<> 154:37f96f9d4de2 888 status = kStatus_LPUART_RxBusy;
<> 154:37f96f9d4de2 889 }
<> 154:37f96f9d4de2 890 else
<> 154:37f96f9d4de2 891 {
<> 154:37f96f9d4de2 892 bytesToReceive = xfer->dataSize;
<> 154:37f96f9d4de2 893 bytesCurrentReceived = 0;
<> 154:37f96f9d4de2 894
<> 154:37f96f9d4de2 895 /* If RX ring buffer is used. */
<> 154:37f96f9d4de2 896 if (handle->rxRingBuffer)
<> 154:37f96f9d4de2 897 {
<> 154:37f96f9d4de2 898 /* Disable LPUART RX IRQ, protect ring buffer. */
<> 154:37f96f9d4de2 899 LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable);
<> 154:37f96f9d4de2 900
<> 154:37f96f9d4de2 901 /* How many bytes in RX ring buffer currently. */
<> 154:37f96f9d4de2 902 bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle);
<> 154:37f96f9d4de2 903
<> 154:37f96f9d4de2 904 if (bytesToCopy)
<> 154:37f96f9d4de2 905 {
<> 154:37f96f9d4de2 906 bytesToCopy = MIN(bytesToReceive, bytesToCopy);
<> 154:37f96f9d4de2 907
<> 154:37f96f9d4de2 908 bytesToReceive -= bytesToCopy;
<> 154:37f96f9d4de2 909
<> 154:37f96f9d4de2 910 /* Copy data from ring buffer to user memory. */
<> 154:37f96f9d4de2 911 for (i = 0U; i < bytesToCopy; i++)
<> 154:37f96f9d4de2 912 {
<> 154:37f96f9d4de2 913 xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
<> 154:37f96f9d4de2 914
<> 154:37f96f9d4de2 915 /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
<> 154:37f96f9d4de2 916 if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
<> 154:37f96f9d4de2 917 {
<> 154:37f96f9d4de2 918 handle->rxRingBufferTail = 0U;
<> 154:37f96f9d4de2 919 }
<> 154:37f96f9d4de2 920 else
<> 154:37f96f9d4de2 921 {
<> 154:37f96f9d4de2 922 handle->rxRingBufferTail++;
<> 154:37f96f9d4de2 923 }
<> 154:37f96f9d4de2 924 }
<> 154:37f96f9d4de2 925 }
<> 154:37f96f9d4de2 926
<> 154:37f96f9d4de2 927 /* If ring buffer does not have enough data, still need to read more data. */
<> 154:37f96f9d4de2 928 if (bytesToReceive)
<> 154:37f96f9d4de2 929 {
<> 154:37f96f9d4de2 930 /* No data in ring buffer, save the request to LPUART handle. */
<> 154:37f96f9d4de2 931 handle->rxData = xfer->data + bytesCurrentReceived;
<> 154:37f96f9d4de2 932 handle->rxDataSize = bytesToReceive;
<> 154:37f96f9d4de2 933 handle->rxDataSizeAll = bytesToReceive;
<> 154:37f96f9d4de2 934 handle->rxState = kLPUART_RxBusy;
<> 154:37f96f9d4de2 935 }
<> 154:37f96f9d4de2 936 /* Enable LPUART RX IRQ if previously enabled. */
<> 154:37f96f9d4de2 937 LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable);
<> 154:37f96f9d4de2 938
<> 154:37f96f9d4de2 939 /* Call user callback since all data are received. */
<> 154:37f96f9d4de2 940 if (0 == bytesToReceive)
<> 154:37f96f9d4de2 941 {
<> 154:37f96f9d4de2 942 if (handle->callback)
<> 154:37f96f9d4de2 943 {
<> 154:37f96f9d4de2 944 handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
<> 154:37f96f9d4de2 945 }
<> 154:37f96f9d4de2 946 }
<> 154:37f96f9d4de2 947 }
<> 154:37f96f9d4de2 948 /* Ring buffer not used. */
<> 154:37f96f9d4de2 949 else
<> 154:37f96f9d4de2 950 {
<> 154:37f96f9d4de2 951 handle->rxData = xfer->data + bytesCurrentReceived;
<> 154:37f96f9d4de2 952 handle->rxDataSize = bytesToReceive;
<> 154:37f96f9d4de2 953 handle->rxDataSizeAll = bytesToReceive;
<> 154:37f96f9d4de2 954 handle->rxState = kLPUART_RxBusy;
<> 154:37f96f9d4de2 955
<> 154:37f96f9d4de2 956 /* Enable RX interrupt. */
<> 154:37f96f9d4de2 957 LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
<> 154:37f96f9d4de2 958 }
<> 154:37f96f9d4de2 959
<> 154:37f96f9d4de2 960 /* Return the how many bytes have read. */
<> 154:37f96f9d4de2 961 if (receivedBytes)
<> 154:37f96f9d4de2 962 {
<> 154:37f96f9d4de2 963 *receivedBytes = bytesCurrentReceived;
<> 154:37f96f9d4de2 964 }
<> 154:37f96f9d4de2 965
<> 154:37f96f9d4de2 966 status = kStatus_Success;
<> 154:37f96f9d4de2 967 }
<> 154:37f96f9d4de2 968
<> 154:37f96f9d4de2 969 return status;
<> 154:37f96f9d4de2 970 }
<> 154:37f96f9d4de2 971
<> 154:37f96f9d4de2 972 void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)
<> 154:37f96f9d4de2 973 {
<> 154:37f96f9d4de2 974 assert(handle);
<> 154:37f96f9d4de2 975
<> 154:37f96f9d4de2 976 /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
<> 154:37f96f9d4de2 977 if (!handle->rxRingBuffer)
<> 154:37f96f9d4de2 978 {
<> 154:37f96f9d4de2 979 /* Disable RX interrupt. */
<> 154:37f96f9d4de2 980 LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
<> 154:37f96f9d4de2 981 }
<> 154:37f96f9d4de2 982
<> 154:37f96f9d4de2 983 handle->rxDataSize = 0U;
<> 154:37f96f9d4de2 984 handle->rxState = kLPUART_RxIdle;
<> 154:37f96f9d4de2 985 }
<> 154:37f96f9d4de2 986
<> 154:37f96f9d4de2 987 status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
<> 154:37f96f9d4de2 988 {
<> 154:37f96f9d4de2 989 assert(handle);
<> 154:37f96f9d4de2 990 assert(count);
<> 154:37f96f9d4de2 991
<> 154:37f96f9d4de2 992 if (kLPUART_RxIdle == handle->rxState)
<> 154:37f96f9d4de2 993 {
<> 154:37f96f9d4de2 994 return kStatus_NoTransferInProgress;
<> 154:37f96f9d4de2 995 }
<> 154:37f96f9d4de2 996
<> 154:37f96f9d4de2 997 *count = handle->rxDataSizeAll - handle->rxDataSize;
<> 154:37f96f9d4de2 998
<> 154:37f96f9d4de2 999 return kStatus_Success;
<> 154:37f96f9d4de2 1000 }
<> 154:37f96f9d4de2 1001
<> 154:37f96f9d4de2 1002 void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
<> 154:37f96f9d4de2 1003 {
<> 154:37f96f9d4de2 1004 assert(handle);
<> 154:37f96f9d4de2 1005
<> 154:37f96f9d4de2 1006 uint8_t count;
<> 154:37f96f9d4de2 1007 uint8_t tempCount;
<> 154:37f96f9d4de2 1008
<> 154:37f96f9d4de2 1009 /* If RX overrun. */
<> 154:37f96f9d4de2 1010 if (LPUART_STAT_OR_MASK & base->STAT)
<> 154:37f96f9d4de2 1011 {
<> 154:37f96f9d4de2 1012 /* Clear overrun flag, otherwise the RX does not work. */
<> 154:37f96f9d4de2 1013 base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK);
<> 154:37f96f9d4de2 1014
<> 154:37f96f9d4de2 1015 /* Trigger callback. */
<> 154:37f96f9d4de2 1016 if (handle->callback)
<> 154:37f96f9d4de2 1017 {
<> 154:37f96f9d4de2 1018 handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData);
<> 154:37f96f9d4de2 1019 }
<> 154:37f96f9d4de2 1020 }
<> 154:37f96f9d4de2 1021
<> 154:37f96f9d4de2 1022 /* Receive data register full */
<> 154:37f96f9d4de2 1023 if ((LPUART_STAT_RDRF_MASK & base->STAT) && (LPUART_CTRL_RIE_MASK & base->CTRL))
<> 154:37f96f9d4de2 1024 {
<> 154:37f96f9d4de2 1025 /* Get the size that can be stored into buffer for this interrupt. */
<> 154:37f96f9d4de2 1026 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 1027 count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT));
<> 154:37f96f9d4de2 1028 #else
<> 154:37f96f9d4de2 1029 count = 1;
<> 154:37f96f9d4de2 1030 #endif
<> 154:37f96f9d4de2 1031
<> 154:37f96f9d4de2 1032 /* If handle->rxDataSize is not 0, first save data to handle->rxData. */
<> 154:37f96f9d4de2 1033 while ((count) && (handle->rxDataSize))
<> 154:37f96f9d4de2 1034 {
<> 154:37f96f9d4de2 1035 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 1036 tempCount = MIN(handle->rxDataSize, count);
<> 154:37f96f9d4de2 1037 #else
<> 154:37f96f9d4de2 1038 tempCount = 1;
<> 154:37f96f9d4de2 1039 #endif
<> 154:37f96f9d4de2 1040
<> 154:37f96f9d4de2 1041 /* Using non block API to read the data from the registers. */
<> 154:37f96f9d4de2 1042 LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
<> 154:37f96f9d4de2 1043 handle->rxData += tempCount;
<> 154:37f96f9d4de2 1044 handle->rxDataSize -= tempCount;
<> 154:37f96f9d4de2 1045 count -= tempCount;
<> 154:37f96f9d4de2 1046
<> 154:37f96f9d4de2 1047 /* If all the data required for upper layer is ready, trigger callback. */
<> 154:37f96f9d4de2 1048 if (!handle->rxDataSize)
<> 154:37f96f9d4de2 1049 {
<> 154:37f96f9d4de2 1050 handle->rxState = kLPUART_RxIdle;
<> 154:37f96f9d4de2 1051
<> 154:37f96f9d4de2 1052 if (handle->callback)
<> 154:37f96f9d4de2 1053 {
<> 154:37f96f9d4de2 1054 handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
<> 154:37f96f9d4de2 1055 }
<> 154:37f96f9d4de2 1056 }
<> 154:37f96f9d4de2 1057 }
<> 154:37f96f9d4de2 1058
<> 154:37f96f9d4de2 1059 /* If use RX ring buffer, receive data to ring buffer. */
<> 154:37f96f9d4de2 1060 if (handle->rxRingBuffer)
<> 154:37f96f9d4de2 1061 {
<> 154:37f96f9d4de2 1062 while (count--)
<> 154:37f96f9d4de2 1063 {
<> 154:37f96f9d4de2 1064 /* If RX ring buffer is full, trigger callback to notify over run. */
<> 154:37f96f9d4de2 1065 if (LPUART_TransferIsRxRingBufferFull(base, handle))
<> 154:37f96f9d4de2 1066 {
<> 154:37f96f9d4de2 1067 if (handle->callback)
<> 154:37f96f9d4de2 1068 {
<> 154:37f96f9d4de2 1069 handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData);
<> 154:37f96f9d4de2 1070 }
<> 154:37f96f9d4de2 1071 }
<> 154:37f96f9d4de2 1072
<> 154:37f96f9d4de2 1073 /* If ring buffer is still full after callback function, the oldest data is overrided. */
<> 154:37f96f9d4de2 1074 if (LPUART_TransferIsRxRingBufferFull(base, handle))
<> 154:37f96f9d4de2 1075 {
<> 154:37f96f9d4de2 1076 /* Increase handle->rxRingBufferTail to make room for new data. */
<> 154:37f96f9d4de2 1077 if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
<> 154:37f96f9d4de2 1078 {
<> 154:37f96f9d4de2 1079 handle->rxRingBufferTail = 0U;
<> 154:37f96f9d4de2 1080 }
<> 154:37f96f9d4de2 1081 else
<> 154:37f96f9d4de2 1082 {
<> 154:37f96f9d4de2 1083 handle->rxRingBufferTail++;
<> 154:37f96f9d4de2 1084 }
<> 154:37f96f9d4de2 1085 }
<> 154:37f96f9d4de2 1086
<> 154:37f96f9d4de2 1087 /* Read data. */
<> 154:37f96f9d4de2 1088 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
<> 154:37f96f9d4de2 1089 if (handle->isSevenDataBits)
<> 154:37f96f9d4de2 1090 {
<> 154:37f96f9d4de2 1091 handle->rxRingBuffer[handle->rxRingBufferHead] = (base->DATA & 0x7F);
<> 154:37f96f9d4de2 1092 }
<> 154:37f96f9d4de2 1093 else
<> 154:37f96f9d4de2 1094 {
<> 154:37f96f9d4de2 1095 handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA;
<> 154:37f96f9d4de2 1096 }
<> 154:37f96f9d4de2 1097 #else
<> 154:37f96f9d4de2 1098 handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA;
<> 154:37f96f9d4de2 1099 #endif
<> 154:37f96f9d4de2 1100
<> 154:37f96f9d4de2 1101 /* Increase handle->rxRingBufferHead. */
<> 154:37f96f9d4de2 1102 if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
<> 154:37f96f9d4de2 1103 {
<> 154:37f96f9d4de2 1104 handle->rxRingBufferHead = 0U;
<> 154:37f96f9d4de2 1105 }
<> 154:37f96f9d4de2 1106 else
<> 154:37f96f9d4de2 1107 {
<> 154:37f96f9d4de2 1108 handle->rxRingBufferHead++;
<> 154:37f96f9d4de2 1109 }
<> 154:37f96f9d4de2 1110 }
<> 154:37f96f9d4de2 1111 }
<> 154:37f96f9d4de2 1112 /* If no receive requst pending, stop RX interrupt. */
<> 154:37f96f9d4de2 1113 else if (!handle->rxDataSize)
<> 154:37f96f9d4de2 1114 {
<> 154:37f96f9d4de2 1115 LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
<> 154:37f96f9d4de2 1116 }
<> 154:37f96f9d4de2 1117 else
<> 154:37f96f9d4de2 1118 {
<> 154:37f96f9d4de2 1119 }
<> 154:37f96f9d4de2 1120 }
<> 154:37f96f9d4de2 1121
<> 154:37f96f9d4de2 1122 /* Send data register empty and the interrupt is enabled. */
<> 154:37f96f9d4de2 1123 if ((base->STAT & LPUART_STAT_TDRE_MASK) && (base->CTRL & LPUART_CTRL_TIE_MASK))
<> 154:37f96f9d4de2 1124 {
<> 154:37f96f9d4de2 1125 /* Get the bytes that available at this moment. */
<> 154:37f96f9d4de2 1126 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 1127 count = FSL_FEATURE_LPUART_FIFO_SIZEn(base) -
<> 154:37f96f9d4de2 1128 ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT);
<> 154:37f96f9d4de2 1129 #else
<> 154:37f96f9d4de2 1130 count = 1;
<> 154:37f96f9d4de2 1131 #endif
<> 154:37f96f9d4de2 1132
<> 154:37f96f9d4de2 1133 while ((count) && (handle->txDataSize))
<> 154:37f96f9d4de2 1134 {
<> 154:37f96f9d4de2 1135 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 1136 tempCount = MIN(handle->txDataSize, count);
<> 154:37f96f9d4de2 1137 #else
<> 154:37f96f9d4de2 1138 tempCount = 1;
<> 154:37f96f9d4de2 1139 #endif
<> 154:37f96f9d4de2 1140
<> 154:37f96f9d4de2 1141 /* Using non block API to write the data to the registers. */
<> 154:37f96f9d4de2 1142 LPUART_WriteNonBlocking(base, handle->txData, tempCount);
<> 154:37f96f9d4de2 1143 handle->txData += tempCount;
<> 154:37f96f9d4de2 1144 handle->txDataSize -= tempCount;
<> 154:37f96f9d4de2 1145 count -= tempCount;
<> 154:37f96f9d4de2 1146
<> 154:37f96f9d4de2 1147 /* If all the data are written to data register, notify user with the callback, then TX finished. */
<> 154:37f96f9d4de2 1148 if (!handle->txDataSize)
<> 154:37f96f9d4de2 1149 {
<> 154:37f96f9d4de2 1150 handle->txState = kLPUART_TxIdle;
<> 154:37f96f9d4de2 1151
<> 154:37f96f9d4de2 1152 /* Disable TX register empty interrupt. */
<> 154:37f96f9d4de2 1153 base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK);
<> 154:37f96f9d4de2 1154
<> 154:37f96f9d4de2 1155 /* Trigger callback. */
<> 154:37f96f9d4de2 1156 if (handle->callback)
<> 154:37f96f9d4de2 1157 {
<> 154:37f96f9d4de2 1158 handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData);
<> 154:37f96f9d4de2 1159 }
<> 154:37f96f9d4de2 1160 }
<> 154:37f96f9d4de2 1161 }
<> 154:37f96f9d4de2 1162 }
<> 154:37f96f9d4de2 1163 }
<> 154:37f96f9d4de2 1164
<> 154:37f96f9d4de2 1165 void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle)
<> 154:37f96f9d4de2 1166 {
<> 154:37f96f9d4de2 1167 /* To be implemented by User. */
<> 154:37f96f9d4de2 1168 }
<> 154:37f96f9d4de2 1169
<> 154:37f96f9d4de2 1170 #if defined(LPUART0)
<> 154:37f96f9d4de2 1171 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
<> 154:37f96f9d4de2 1172 void LPUART0_TX_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1173 {
<> 154:37f96f9d4de2 1174 s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
<> 154:37f96f9d4de2 1175 }
<> 154:37f96f9d4de2 1176 void LPUART0_RX_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1177 {
<> 154:37f96f9d4de2 1178 s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
<> 154:37f96f9d4de2 1179 }
<> 154:37f96f9d4de2 1180 #else
<> 154:37f96f9d4de2 1181 void LPUART0_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1182 {
<> 154:37f96f9d4de2 1183 s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
<> 154:37f96f9d4de2 1184 }
<> 154:37f96f9d4de2 1185 #endif
<> 154:37f96f9d4de2 1186 #endif
<> 154:37f96f9d4de2 1187
<> 154:37f96f9d4de2 1188 #if defined(LPUART1)
<> 154:37f96f9d4de2 1189 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
<> 154:37f96f9d4de2 1190 void LPUART1_TX_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1191 {
<> 154:37f96f9d4de2 1192 s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
<> 154:37f96f9d4de2 1193 }
<> 154:37f96f9d4de2 1194 void LPUART1_RX_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1195 {
<> 154:37f96f9d4de2 1196 s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
<> 154:37f96f9d4de2 1197 }
<> 154:37f96f9d4de2 1198 #else
<> 154:37f96f9d4de2 1199 void LPUART1_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1200 {
<> 154:37f96f9d4de2 1201 s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
<> 154:37f96f9d4de2 1202 }
<> 154:37f96f9d4de2 1203 #endif
<> 154:37f96f9d4de2 1204 #endif
<> 154:37f96f9d4de2 1205
<> 154:37f96f9d4de2 1206 #if defined(LPUART2)
<> 154:37f96f9d4de2 1207 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
<> 154:37f96f9d4de2 1208 void LPUART2_TX_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1209 {
<> 154:37f96f9d4de2 1210 s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
<> 154:37f96f9d4de2 1211 }
<> 154:37f96f9d4de2 1212 void LPUART2_RX_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1213 {
<> 154:37f96f9d4de2 1214 s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
<> 154:37f96f9d4de2 1215 }
<> 154:37f96f9d4de2 1216 #else
<> 154:37f96f9d4de2 1217 void LPUART2_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1218 {
<> 154:37f96f9d4de2 1219 s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
<> 154:37f96f9d4de2 1220 }
<> 154:37f96f9d4de2 1221 #endif
<> 154:37f96f9d4de2 1222 #endif
<> 154:37f96f9d4de2 1223
<> 154:37f96f9d4de2 1224 #if defined(LPUART3)
<> 154:37f96f9d4de2 1225 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
<> 154:37f96f9d4de2 1226 void LPUART3_TX_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1227 {
<> 154:37f96f9d4de2 1228 s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
<> 154:37f96f9d4de2 1229 }
<> 154:37f96f9d4de2 1230 void LPUART3_RX_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1231 {
<> 154:37f96f9d4de2 1232 s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
<> 154:37f96f9d4de2 1233 }
<> 154:37f96f9d4de2 1234 #else
<> 154:37f96f9d4de2 1235 void LPUART3_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1236 {
<> 154:37f96f9d4de2 1237 s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
<> 154:37f96f9d4de2 1238 }
<> 154:37f96f9d4de2 1239 #endif
<> 154:37f96f9d4de2 1240 #endif
<> 154:37f96f9d4de2 1241
<> 154:37f96f9d4de2 1242 #if defined(LPUART4)
<> 154:37f96f9d4de2 1243 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
<> 154:37f96f9d4de2 1244 void LPUART4_TX_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1245 {
<> 154:37f96f9d4de2 1246 s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
<> 154:37f96f9d4de2 1247 }
<> 154:37f96f9d4de2 1248 void LPUART4_RX_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1249 {
<> 154:37f96f9d4de2 1250 s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
<> 154:37f96f9d4de2 1251 }
<> 154:37f96f9d4de2 1252 #else
<> 154:37f96f9d4de2 1253 void LPUART4_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1254 {
<> 154:37f96f9d4de2 1255 s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
<> 154:37f96f9d4de2 1256 }
<> 154:37f96f9d4de2 1257 #endif
<> 154:37f96f9d4de2 1258 #endif
<> 154:37f96f9d4de2 1259
<> 154:37f96f9d4de2 1260 #if defined(LPUART5)
<> 154:37f96f9d4de2 1261 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
<> 154:37f96f9d4de2 1262 void LPUART5_TX_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1263 {
<> 154:37f96f9d4de2 1264 s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
<> 154:37f96f9d4de2 1265 }
<> 154:37f96f9d4de2 1266 void LPUART5_RX_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1267 {
<> 154:37f96f9d4de2 1268 s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
<> 154:37f96f9d4de2 1269 }
<> 154:37f96f9d4de2 1270 #else
<> 154:37f96f9d4de2 1271 void LPUART5_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1272 {
<> 154:37f96f9d4de2 1273 s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
<> 154:37f96f9d4de2 1274 }
<> 154:37f96f9d4de2 1275 #endif
<> 154:37f96f9d4de2 1276 #endif