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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.c@144:ef7eb2e8f9f7
Child:
151:5eaa88a5bcc7
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_adc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.0
<> 144:ef7eb2e8f9f7 6 * @date 8-January-2016
<> 144:ef7eb2e8f9f7 7 * @brief This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 8 * functionalities of the Analog to Digital Convertor (ADC)
<> 144:ef7eb2e8f9f7 9 * peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * ++ Initialization and Configuration of ADC
<> 144:ef7eb2e8f9f7 12 * + Operation functions
<> 144:ef7eb2e8f9f7 13 * ++ Start, stop, get result of conversions of regular
<> 144:ef7eb2e8f9f7 14 * group, using 3 possible modes : polling, interruption or DMA.
<> 144:ef7eb2e8f9f7 15 * + Control functions
<> 144:ef7eb2e8f9f7 16 * ++ Channels configuration on regular group
<> 144:ef7eb2e8f9f7 17 * ++ Analog Watchdog configuration
<> 144:ef7eb2e8f9f7 18 * + State functions
<> 144:ef7eb2e8f9f7 19 * ++ ADC state machine management
<> 144:ef7eb2e8f9f7 20 * ++ Interrupts and flags management
<> 144:ef7eb2e8f9f7 21 * Other functions (extended functions) are available in file
<> 144:ef7eb2e8f9f7 22 * "stm32l0xx_hal_adc_ex.c".
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 @verbatim
<> 144:ef7eb2e8f9f7 25 ==============================================================================
<> 144:ef7eb2e8f9f7 26 ##### ADC peripheral features #####
<> 144:ef7eb2e8f9f7 27 ==============================================================================
<> 144:ef7eb2e8f9f7 28 [..]
<> 144:ef7eb2e8f9f7 29 (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 (+) A built-in hardware oversampler can handle multiple conversions and average
<> 144:ef7eb2e8f9f7 32 them into a single data with increased data width, up to 16-bit.
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 (+) Interrupt generation at the end of regular conversion and in case of
<> 144:ef7eb2e8f9f7 35 analog watchdog or overrun events.
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 (+) Single and continuous conversion modes.
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 (+) Scan mode for conversion of several channels sequentially.
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 (+) Data alignment with in-built data coherency.
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 (+) Programmable sampling time (common for all channels)
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 (+) ADC conversion of regular group.
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 (+) External trigger (timer or EXTI) with configurable polarity
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 (+) DMA request generation for transfer of conversions data of regular group.
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 (+) ADC calibration
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
<> 144:ef7eb2e8f9f7 54 slower speed.
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
<> 144:ef7eb2e8f9f7 57 Vdda or to an external voltage reference).
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 61 ==============================================================================
<> 144:ef7eb2e8f9f7 62 [..]
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 *** Configuration of top level parameters related to ADC ***
<> 144:ef7eb2e8f9f7 65 ============================================================
<> 144:ef7eb2e8f9f7 66 [..]
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 (#) Enable the ADC interface
<> 144:ef7eb2e8f9f7 69 (++) As prerequisite, ADC clock must be configured at RCC top level.
<> 144:ef7eb2e8f9f7 70 Caution: On STM32L0, ADC clock frequency max is 16MHz (refer
<> 144:ef7eb2e8f9f7 71 to device datasheet).
<> 144:ef7eb2e8f9f7 72 Therefore, ADC clock prescaler must be configured in
<> 144:ef7eb2e8f9f7 73 function of ADC clock source frequency to remain below
<> 144:ef7eb2e8f9f7 74 this maximum frequency.
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 (++) Two clock settings are mandatory:
<> 144:ef7eb2e8f9f7 77 (+++) ADC clock (core clock, also possibly conversion clock).
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 (+++) ADC clock (conversions clock).
<> 144:ef7eb2e8f9f7 80 Two possible clock sources: synchronous clock derived from APB clock
<> 144:ef7eb2e8f9f7 81 or asynchronous clock derived from ADC dedicated HSI RC oscillator
<> 144:ef7eb2e8f9f7 82 16MHz.
<> 144:ef7eb2e8f9f7 83 If asynchronous clock is selected, parameter "HSIState" must be set either:
<> 144:ef7eb2e8f9f7 84 - to "...HSIState = RCC_HSI_ON" to maintain the HSI16 oscillator
<> 144:ef7eb2e8f9f7 85 always enabled: can be used to supply the main system clock.
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 (+++) Example:
<> 144:ef7eb2e8f9f7 88 Into HAL_ADC_MspInit() (recommended code location) or with
<> 144:ef7eb2e8f9f7 89 other device clock parameters configuration:
<> 144:ef7eb2e8f9f7 90 (+++) __HAL_RCC_ADC1_CLK_ENABLE(); (mandatory)
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 HSI16 enable : (optional: if asynchronous clock selected)
<> 144:ef7eb2e8f9f7 93 (+++) RCC_OscInitTypeDef RCC_OscInitStructure;
<> 144:ef7eb2e8f9f7 94 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
<> 144:ef7eb2e8f9f7 95 (+++) RCC_OscInitStructure.HSI16CalibrationValue = RCC_HSICALIBRATION_DEFAULT;
<> 144:ef7eb2e8f9f7 96 (+++) RCC_OscInitStructure.HSIState = RCC_HSI_ON;
<> 144:ef7eb2e8f9f7 97 (+++) RCC_OscInitStructure.PLL... (optional if used for system clock)
<> 144:ef7eb2e8f9f7 98 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 (++) ADC clock source and clock prescaler are configured at ADC level with
<> 144:ef7eb2e8f9f7 101 parameter "ClockPrescaler" using function HAL_ADC_Init().
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 (#) ADC pins configuration
<> 144:ef7eb2e8f9f7 104 (++) Enable the clock for the ADC GPIOs
<> 144:ef7eb2e8f9f7 105 using macro __HAL_RCC_GPIOx_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 106 (++) Configure these ADC pins in analog mode
<> 144:ef7eb2e8f9f7 107 using function HAL_GPIO_Init()
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 (#) Optionally, in case of usage of ADC with interruptions:
<> 144:ef7eb2e8f9f7 110 (++) Configure the NVIC for ADC
<> 144:ef7eb2e8f9f7 111 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
<> 144:ef7eb2e8f9f7 112 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
<> 144:ef7eb2e8f9f7 113 into the function of corresponding ADC interruption vector
<> 144:ef7eb2e8f9f7 114 ADCx_IRQHandler().
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 (#) Optionally, in case of usage of DMA:
<> 144:ef7eb2e8f9f7 117 (++) Configure the DMA (DMA channel, mode normal or circular, ...)
<> 144:ef7eb2e8f9f7 118 using function HAL_DMA_Init().
<> 144:ef7eb2e8f9f7 119 (++) Configure the NVIC for DMA
<> 144:ef7eb2e8f9f7 120 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
<> 144:ef7eb2e8f9f7 121 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
<> 144:ef7eb2e8f9f7 122 into the function of corresponding DMA interruption vector
<> 144:ef7eb2e8f9f7 123 DMAx_Channelx_IRQHandler().
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 *** Configuration of ADC, group regular, channels parameters ***
<> 144:ef7eb2e8f9f7 126 ================================================================
<> 144:ef7eb2e8f9f7 127 [..]
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 (#) Configure the ADC parameters (resolution, data alignment, oversampler, continuous mode, ...)
<> 144:ef7eb2e8f9f7 130 and regular group parameters (conversion trigger, sequencer, ...)
<> 144:ef7eb2e8f9f7 131 using function HAL_ADC_Init().
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 (#) Configure the channels for regular group parameters (channel number,
<> 144:ef7eb2e8f9f7 134 channel rank into sequencer, ..., into regular group)
<> 144:ef7eb2e8f9f7 135 using function HAL_ADC_ConfigChannel().
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 (#) Optionally, configure the analog watchdog parameters (channels
<> 144:ef7eb2e8f9f7 138 monitored, thresholds, ...)
<> 144:ef7eb2e8f9f7 139 using function HAL_ADC_AnalogWDGConfig().
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 (#) When device is in mode low-power (low-power run, low-power sleep or stop mode),
<> 144:ef7eb2e8f9f7 143 function "HAL_ADCEx_EnableVREFINT()" must be called before function HAL_ADC_Init().
<> 144:ef7eb2e8f9f7 144 In case of internal temperature sensor to be measured:
<> 144:ef7eb2e8f9f7 145 function "HAL_ADCEx_EnableVREFINTTempSensor()" must be called similarilly
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 *** Execution of ADC conversions ***
<> 144:ef7eb2e8f9f7 148 ====================================
<> 144:ef7eb2e8f9f7 149 [..]
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 (#) Optionally, perform an automatic ADC calibration to improve the
<> 144:ef7eb2e8f9f7 152 conversion accuracy
<> 144:ef7eb2e8f9f7 153 using function HAL_ADCEx_Calibration_Start().
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 (#) ADC driver can be used among three modes: polling, interruption,
<> 144:ef7eb2e8f9f7 156 transfer by DMA.
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 (++) ADC conversion by polling:
<> 144:ef7eb2e8f9f7 159 (+++) Activate the ADC peripheral and start conversions
<> 144:ef7eb2e8f9f7 160 using function HAL_ADC_Start()
<> 144:ef7eb2e8f9f7 161 (+++) Wait for ADC conversion completion
<> 144:ef7eb2e8f9f7 162 using function HAL_ADC_PollForConversion()
<> 144:ef7eb2e8f9f7 163 (+++) Retrieve conversion results
<> 144:ef7eb2e8f9f7 164 using function HAL_ADC_GetValue()
<> 144:ef7eb2e8f9f7 165 (+++) Stop conversion and disable the ADC peripheral
<> 144:ef7eb2e8f9f7 166 using function HAL_ADC_Stop()
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 (++) ADC conversion by interruption:
<> 144:ef7eb2e8f9f7 169 (+++) Activate the ADC peripheral and start conversions
<> 144:ef7eb2e8f9f7 170 using function HAL_ADC_Start_IT()
<> 144:ef7eb2e8f9f7 171 (+++) Wait for ADC conversion completion by call of function
<> 144:ef7eb2e8f9f7 172 HAL_ADC_ConvCpltCallback()
<> 144:ef7eb2e8f9f7 173 (this function must be implemented in user program)
<> 144:ef7eb2e8f9f7 174 (+++) Retrieve conversion results
<> 144:ef7eb2e8f9f7 175 using function HAL_ADC_GetValue()
<> 144:ef7eb2e8f9f7 176 (+++) Stop conversion and disable the ADC peripheral
<> 144:ef7eb2e8f9f7 177 using function HAL_ADC_Stop_IT()
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 (++) ADC conversion with transfer by DMA:
<> 144:ef7eb2e8f9f7 180 (+++) Activate the ADC peripheral and start conversions
<> 144:ef7eb2e8f9f7 181 using function HAL_ADC_Start_DMA()
<> 144:ef7eb2e8f9f7 182 (+++) Wait for ADC conversion completion by call of function
<> 144:ef7eb2e8f9f7 183 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
<> 144:ef7eb2e8f9f7 184 (these functions must be implemented in user program)
<> 144:ef7eb2e8f9f7 185 (+++) Conversion results are automatically transferred by DMA into
<> 144:ef7eb2e8f9f7 186 destination variable address.
<> 144:ef7eb2e8f9f7 187 (+++) Stop conversion and disable the ADC peripheral
<> 144:ef7eb2e8f9f7 188 using function HAL_ADC_Stop_DMA()
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 [..]
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 (@) Callback functions must be implemented in user program:
<> 144:ef7eb2e8f9f7 193 (+@) HAL_ADC_ErrorCallback()
<> 144:ef7eb2e8f9f7 194 (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
<> 144:ef7eb2e8f9f7 195 (+@) HAL_ADC_ConvCpltCallback()
<> 144:ef7eb2e8f9f7 196 (+@) HAL_ADC_ConvHalfCpltCallback
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 *** Deinitialization of ADC ***
<> 144:ef7eb2e8f9f7 199 ============================================================
<> 144:ef7eb2e8f9f7 200 [..]
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 (#) Disable the ADC interface
<> 144:ef7eb2e8f9f7 203 (++) ADC clock can be hard reset and disabled at RCC top level.
<> 144:ef7eb2e8f9f7 204 (++) Hard reset of ADC peripherals
<> 144:ef7eb2e8f9f7 205 using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
<> 144:ef7eb2e8f9f7 206 (++) ADC clock disable
<> 144:ef7eb2e8f9f7 207 using the equivalent macro/functions as configuration step.
<> 144:ef7eb2e8f9f7 208 (+++) Example:
<> 144:ef7eb2e8f9f7 209 Into HAL_ADC_MspDeInit() (recommended code location) or with
<> 144:ef7eb2e8f9f7 210 other device clock parameters configuration:
<> 144:ef7eb2e8f9f7 211 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
<> 144:ef7eb2e8f9f7 212 (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
<> 144:ef7eb2e8f9f7 213 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 (#) ADC pins configuration
<> 144:ef7eb2e8f9f7 216 (++) Disable the clock for the ADC GPIOs
<> 144:ef7eb2e8f9f7 217 using macro __HAL_RCC_GPIOx_CLK_DISABLE()
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 (#) Optionally, in case of usage of ADC with interruptions:
<> 144:ef7eb2e8f9f7 220 (++) Disable the NVIC for ADC
<> 144:ef7eb2e8f9f7 221 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 (#) Optionally, in case of usage of DMA:
<> 144:ef7eb2e8f9f7 224 (++) Deinitialize the DMA
<> 144:ef7eb2e8f9f7 225 using function HAL_DMA_Init().
<> 144:ef7eb2e8f9f7 226 (++) Disable the NVIC for DMA
<> 144:ef7eb2e8f9f7 227 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 [..]
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 @endverbatim
<> 144:ef7eb2e8f9f7 232 ******************************************************************************
<> 144:ef7eb2e8f9f7 233 * @attention
<> 144:ef7eb2e8f9f7 234 *
<> 144:ef7eb2e8f9f7 235 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 236 *
<> 144:ef7eb2e8f9f7 237 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 238 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 239 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 240 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 241 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 242 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 243 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 244 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 245 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 246 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 247 *
<> 144:ef7eb2e8f9f7 248 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 249 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 250 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 251 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 252 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 253 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 254 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 255 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 256 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 257 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 258 *
<> 144:ef7eb2e8f9f7 259 ******************************************************************************
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 263 #include "stm32l0xx_hal.h"
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 266 * @{
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 #ifdef HAL_ADC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /** @addtogroup ADC
<> 144:ef7eb2e8f9f7 272 * @brief ADC driver modules
<> 144:ef7eb2e8f9f7 273 * @{
<> 144:ef7eb2e8f9f7 274 */
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /** @addtogroup ADC_Private
<> 144:ef7eb2e8f9f7 277 * @{
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 281 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /* Delay for ADC stabilization time. */
<> 144:ef7eb2e8f9f7 284 /* Maximum delay is 1us (refer to device datasheet, parameter tSTART). */
<> 144:ef7eb2e8f9f7 285 /* Unit: us */
<> 144:ef7eb2e8f9f7 286 #define ADC_STAB_DELAY_US ((uint32_t) 1)
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /* Delay for temperature sensor stabilization time. */
<> 144:ef7eb2e8f9f7 289 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
<> 144:ef7eb2e8f9f7 290 /* Unit: us */
<> 144:ef7eb2e8f9f7 291 #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
<> 144:ef7eb2e8f9f7 292 /**
<> 144:ef7eb2e8f9f7 293 * @}
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 297 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 298 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 299 /** @addtogroup ADC_Private
<> 144:ef7eb2e8f9f7 300 * @{
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 303 static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 304 static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 305 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 306 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 307 static void ADC_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 308 static void ADC_DelayMicroSecond(uint32_t microSecond);
<> 144:ef7eb2e8f9f7 309 /**
<> 144:ef7eb2e8f9f7 310 * @}
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /** @addtogroup ADC_Exported_Functions
<> 144:ef7eb2e8f9f7 314 * @{
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /** @addtogroup ADC_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 318 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 319 *
<> 144:ef7eb2e8f9f7 320 @verbatim
<> 144:ef7eb2e8f9f7 321 ===============================================================================
<> 144:ef7eb2e8f9f7 322 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 323 ===============================================================================
<> 144:ef7eb2e8f9f7 324 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 325 (+) Initialize and configure the ADC.
<> 144:ef7eb2e8f9f7 326 (+) De-initialize the ADC.
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 @endverbatim
<> 144:ef7eb2e8f9f7 329 * @{
<> 144:ef7eb2e8f9f7 330 */
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /**
<> 144:ef7eb2e8f9f7 334 * @brief Initializes the ADC peripheral and regular group according to
<> 144:ef7eb2e8f9f7 335 * parameters specified in structure "ADC_InitTypeDef".
<> 144:ef7eb2e8f9f7 336 * @note As prerequisite, ADC clock must be configured at RCC top level
<> 144:ef7eb2e8f9f7 337 * depending on both possible clock sources: APB clock of HSI clock.
<> 144:ef7eb2e8f9f7 338 * See commented example code below that can be copied and uncommented
<> 144:ef7eb2e8f9f7 339 * into HAL_ADC_MspInit().
<> 144:ef7eb2e8f9f7 340 * @note Possibility to update parameters on the fly:
<> 144:ef7eb2e8f9f7 341 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
<> 144:ef7eb2e8f9f7 342 * coming from ADC state reset. Following calls to this function can
<> 144:ef7eb2e8f9f7 343 * be used to reconfigure some parameters of ADC_InitTypeDef
<> 144:ef7eb2e8f9f7 344 * structure on the fly, without modifying MSP configuration. If ADC
<> 144:ef7eb2e8f9f7 345 * MSP has to be modified again, HAL_ADC_DeInit() must be called
<> 144:ef7eb2e8f9f7 346 * before HAL_ADC_Init().
<> 144:ef7eb2e8f9f7 347 * The setting of these parameters is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 348 * For parameters constraints, see comments of structure
<> 144:ef7eb2e8f9f7 349 * "ADC_InitTypeDef".
<> 144:ef7eb2e8f9f7 350 * @note This function configures the ADC within 2 scopes: scope of entire
<> 144:ef7eb2e8f9f7 351 * ADC and scope of regular group. For parameters details, see comments
<> 144:ef7eb2e8f9f7 352 * of structure "ADC_InitTypeDef".
<> 144:ef7eb2e8f9f7 353 * @note When device is in mode low-power (low-power run, low-power sleep or stop mode),
<> 144:ef7eb2e8f9f7 354 * function "HAL_ADCEx_EnableVREFINT()" must be called before function HAL_ADC_Init()
<> 144:ef7eb2e8f9f7 355 * (in case of previous ADC operations: function HAL_ADC_DeInit() must be called first).
<> 144:ef7eb2e8f9f7 356 * In case of internal temperature sensor to be measured:
<> 144:ef7eb2e8f9f7 357 * function "HAL_ADCEx_EnableVREFINTTempSensor()" must be called similarilly.
<> 144:ef7eb2e8f9f7 358 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 359 * @retval HAL status
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 362 {
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /* Check ADC handle */
<> 144:ef7eb2e8f9f7 365 if(hadc == NULL)
<> 144:ef7eb2e8f9f7 366 {
<> 144:ef7eb2e8f9f7 367 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 368 }
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /* Check the parameters */
<> 144:ef7eb2e8f9f7 371 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 372 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
<> 144:ef7eb2e8f9f7 373 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
<> 144:ef7eb2e8f9f7 374 assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTime));
<> 144:ef7eb2e8f9f7 375 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
<> 144:ef7eb2e8f9f7 376 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
<> 144:ef7eb2e8f9f7 377 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
<> 144:ef7eb2e8f9f7 378 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
<> 144:ef7eb2e8f9f7 379 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
<> 144:ef7eb2e8f9f7 380 assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
<> 144:ef7eb2e8f9f7 381 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
<> 144:ef7eb2e8f9f7 382 assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
<> 144:ef7eb2e8f9f7 383 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
<> 144:ef7eb2e8f9f7 384 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerFrequencyMode));
<> 144:ef7eb2e8f9f7 385 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff));
<> 144:ef7eb2e8f9f7 386 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
<> 144:ef7eb2e8f9f7 389 /* at RCC top level depending on both possible clock sources: */
<> 144:ef7eb2e8f9f7 390 /* APB clock or HSI clock. */
<> 144:ef7eb2e8f9f7 391 /* Refer to header of this file for more details on clock enabling procedure*/
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /* Actions performed only if ADC is coming from state reset: */
<> 144:ef7eb2e8f9f7 394 /* - Initialization of ADC MSP */
<> 144:ef7eb2e8f9f7 395 /* - ADC voltage regulator enable */
<> 144:ef7eb2e8f9f7 396 if(hadc->State == HAL_ADC_STATE_RESET)
<> 144:ef7eb2e8f9f7 397 {
<> 144:ef7eb2e8f9f7 398 /* Initialize ADC error code */
<> 144:ef7eb2e8f9f7 399 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 402 hadc->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 405 HAL_ADC_MspInit(hadc);
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /* Configuration of ADC parameters if previous preliminary actions are */
<> 144:ef7eb2e8f9f7 409 /* correctly completed. */
<> 144:ef7eb2e8f9f7 410 /* and if there is no conversion on going on regular group (ADC can be */
<> 144:ef7eb2e8f9f7 411 /* enabled anyway, in case of call of this function to update a parameter */
<> 144:ef7eb2e8f9f7 412 /* on the fly). */
<> 144:ef7eb2e8f9f7 413 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) ||
<> 144:ef7eb2e8f9f7 414 (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET) )
<> 144:ef7eb2e8f9f7 415 {
<> 144:ef7eb2e8f9f7 416 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 417 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Process unlocked */
<> 144:ef7eb2e8f9f7 420 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 421 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 422 }
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Set ADC state */
<> 144:ef7eb2e8f9f7 425 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 426 HAL_ADC_STATE_REG_BUSY,
<> 144:ef7eb2e8f9f7 427 HAL_ADC_STATE_BUSY_INTERNAL);
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 430 /* Parameters that can be updated only when ADC is disabled: */
<> 144:ef7eb2e8f9f7 431 /* - ADC clock mode */
<> 144:ef7eb2e8f9f7 432 /* - ADC clock prescaler */
<> 144:ef7eb2e8f9f7 433 /* - ADC Resolution */
<> 144:ef7eb2e8f9f7 434 if (ADC_IS_ENABLE(hadc) == RESET)
<> 144:ef7eb2e8f9f7 435 {
<> 144:ef7eb2e8f9f7 436 /* Some parameters of this register are not reset, since they are set */
<> 144:ef7eb2e8f9f7 437 /* by other functions and must be kept in case of usage of this */
<> 144:ef7eb2e8f9f7 438 /* function on the fly (update of a parameter of ADC_InitTypeDef */
<> 144:ef7eb2e8f9f7 439 /* without needing to reconfigure all other ADC groups/channels */
<> 144:ef7eb2e8f9f7 440 /* parameters): */
<> 144:ef7eb2e8f9f7 441 /* - internal measurement paths: Vbat, temperature sensor, Vref */
<> 144:ef7eb2e8f9f7 442 /* (set into HAL_ADC_ConfigChannel() ) */
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /* Configuration of ADC clock: clock source PCLK or asynchronous with
<> 144:ef7eb2e8f9f7 445 selectable prescaler */
<> 144:ef7eb2e8f9f7 446 __HAL_ADC_CLOCK_PRESCALER(hadc);
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /* Configuration of ADC: */
<> 144:ef7eb2e8f9f7 449 /* - Resolution */
<> 144:ef7eb2e8f9f7 450 hadc->Instance->CFGR1 &= ~( ADC_CFGR1_RES);
<> 144:ef7eb2e8f9f7 451 hadc->Instance->CFGR1 |= hadc->Init.Resolution;
<> 144:ef7eb2e8f9f7 452 }
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /* Set the Low Frequency mode */
<> 144:ef7eb2e8f9f7 455 ADC->CCR &= (uint32_t)~ADC_CCR_LFMEN;
<> 144:ef7eb2e8f9f7 456 ADC->CCR |=__HAL_ADC_CCR_LOWFREQUENCY(hadc->Init.LowPowerFrequencyMode);
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /* Enable voltage regulator (if disabled at this step) */
<> 144:ef7eb2e8f9f7 459 if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
<> 144:ef7eb2e8f9f7 460 {
<> 144:ef7eb2e8f9f7 461 /* Set ADVREGEN bit */
<> 144:ef7eb2e8f9f7 462 hadc->Instance->CR |= ADC_CR_ADVREGEN;
<> 144:ef7eb2e8f9f7 463 }
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /* Configuration of ADC: */
<> 144:ef7eb2e8f9f7 466 /* - Resolution */
<> 144:ef7eb2e8f9f7 467 /* - Data alignment */
<> 144:ef7eb2e8f9f7 468 /* - Scan direction */
<> 144:ef7eb2e8f9f7 469 /* - External trigger to start conversion */
<> 144:ef7eb2e8f9f7 470 /* - External trigger polarity */
<> 144:ef7eb2e8f9f7 471 /* - Continuous conversion mode */
<> 144:ef7eb2e8f9f7 472 /* - DMA continuous request */
<> 144:ef7eb2e8f9f7 473 /* - Overrun */
<> 144:ef7eb2e8f9f7 474 /* - AutoDelay feature */
<> 144:ef7eb2e8f9f7 475 /* - Discontinuous mode */
<> 144:ef7eb2e8f9f7 476 hadc->Instance->CFGR1 &= ~(ADC_CFGR1_ALIGN |
<> 144:ef7eb2e8f9f7 477 ADC_CFGR1_SCANDIR |
<> 144:ef7eb2e8f9f7 478 ADC_CFGR1_EXTSEL |
<> 144:ef7eb2e8f9f7 479 ADC_CFGR1_EXTEN |
<> 144:ef7eb2e8f9f7 480 ADC_CFGR1_CONT |
<> 144:ef7eb2e8f9f7 481 ADC_CFGR1_DMACFG |
<> 144:ef7eb2e8f9f7 482 ADC_CFGR1_OVRMOD |
<> 144:ef7eb2e8f9f7 483 ADC_CFGR1_AUTDLY |
<> 144:ef7eb2e8f9f7 484 ADC_CFGR1_AUTOFF |
<> 144:ef7eb2e8f9f7 485 ADC_CFGR1_DISCEN);
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 hadc->Instance->CFGR1 |= (hadc->Init.DataAlign |
<> 144:ef7eb2e8f9f7 488 ADC_SCANDIR(hadc->Init.ScanConvMode) |
<> 144:ef7eb2e8f9f7 489 ADC_CONTINUOUS(hadc->Init.ContinuousConvMode) |
<> 144:ef7eb2e8f9f7 490 ADC_DMACONTREQ(hadc->Init.DMAContinuousRequests) |
<> 144:ef7eb2e8f9f7 491 hadc->Init.Overrun |
<> 144:ef7eb2e8f9f7 492 __HAL_ADC_CFGR1_AutoDelay(hadc->Init.LowPowerAutoWait) |
<> 144:ef7eb2e8f9f7 493 __HAL_ADC_CFGR1_AUTOFF(hadc->Init.LowPowerAutoPowerOff));
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /* Enable external trigger if trigger selection is different of software */
<> 144:ef7eb2e8f9f7 496 /* start. */
<> 144:ef7eb2e8f9f7 497 /* Note: This configuration keeps the hardware feature of parameter */
<> 144:ef7eb2e8f9f7 498 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
<> 144:ef7eb2e8f9f7 499 /* software start. */
<> 144:ef7eb2e8f9f7 500 if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 501 {
<> 144:ef7eb2e8f9f7 502 hadc->Instance->CFGR1 |= hadc->Init.ExternalTrigConv |
<> 144:ef7eb2e8f9f7 503 hadc->Init.ExternalTrigConvEdge;
<> 144:ef7eb2e8f9f7 504 }
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 /* Enable discontinuous mode only if continuous mode is disabled */
<> 144:ef7eb2e8f9f7 507 if (hadc->Init.DiscontinuousConvMode == ENABLE)
<> 144:ef7eb2e8f9f7 508 {
<> 144:ef7eb2e8f9f7 509 if (hadc->Init.ContinuousConvMode == DISABLE)
<> 144:ef7eb2e8f9f7 510 {
<> 144:ef7eb2e8f9f7 511 /* Enable the selected ADC group regular discontinuous mode */
<> 144:ef7eb2e8f9f7 512 hadc->Instance->CFGR1 |= (ADC_CFGR1_DISCEN);
<> 144:ef7eb2e8f9f7 513 }
<> 144:ef7eb2e8f9f7 514 else
<> 144:ef7eb2e8f9f7 515 {
<> 144:ef7eb2e8f9f7 516 /* ADC regular group discontinuous was intended to be enabled, */
<> 144:ef7eb2e8f9f7 517 /* but ADC regular group modes continuous and sequencer discontinuous */
<> 144:ef7eb2e8f9f7 518 /* cannot be enabled simultaneously. */
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 521 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 524 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 525 }
<> 144:ef7eb2e8f9f7 526 }
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 if (hadc->Init.OversamplingMode == ENABLE)
<> 144:ef7eb2e8f9f7 529 {
<> 144:ef7eb2e8f9f7 530 assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversample.Ratio));
<> 144:ef7eb2e8f9f7 531 assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversample.RightBitShift));
<> 144:ef7eb2e8f9f7 532 assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversample.TriggeredMode));
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /* Configuration of Oversampler: */
<> 144:ef7eb2e8f9f7 535 /* - Oversampling Ratio */
<> 144:ef7eb2e8f9f7 536 /* - Right bit shift */
<> 144:ef7eb2e8f9f7 537 /* - Triggered mode */
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 hadc->Instance->CFGR2 &= ~( ADC_CFGR2_OVSR |
<> 144:ef7eb2e8f9f7 540 ADC_CFGR2_OVSS |
<> 144:ef7eb2e8f9f7 541 ADC_CFGR2_TOVS );
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 hadc->Instance->CFGR2 |= ( hadc->Init.Oversample.Ratio |
<> 144:ef7eb2e8f9f7 544 hadc->Init.Oversample.RightBitShift |
<> 144:ef7eb2e8f9f7 545 hadc->Init.Oversample.TriggeredMode );
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /* Enable OverSampling mode */
<> 144:ef7eb2e8f9f7 548 hadc->Instance->CFGR2 |= ADC_CFGR2_OVSE;
<> 144:ef7eb2e8f9f7 549 }
<> 144:ef7eb2e8f9f7 550 else
<> 144:ef7eb2e8f9f7 551 {
<> 144:ef7eb2e8f9f7 552 if(HAL_IS_BIT_SET(hadc->Instance->CFGR2, ADC_CFGR2_OVSE))
<> 144:ef7eb2e8f9f7 553 {
<> 144:ef7eb2e8f9f7 554 /* Disable OverSampling mode if needed */
<> 144:ef7eb2e8f9f7 555 hadc->Instance->CFGR2 &= ~ADC_CFGR2_OVSE;
<> 144:ef7eb2e8f9f7 556 }
<> 144:ef7eb2e8f9f7 557 }
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /* Clear the old sampling time */
<> 144:ef7eb2e8f9f7 560 hadc->Instance->SMPR &= (uint32_t)(~ADC_SMPR_SMPR);
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /* Set the new sample time */
<> 144:ef7eb2e8f9f7 563 hadc->Instance->SMPR |= hadc->Init.SamplingTime;
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /* Clear ADC error code */
<> 144:ef7eb2e8f9f7 566 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /* Set the ADC state */
<> 144:ef7eb2e8f9f7 569 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 570 HAL_ADC_STATE_BUSY_INTERNAL,
<> 144:ef7eb2e8f9f7 571 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /* Return function status */
<> 144:ef7eb2e8f9f7 575 return HAL_OK;
<> 144:ef7eb2e8f9f7 576 }
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /**
<> 144:ef7eb2e8f9f7 579 * @brief Deinitialize the ADC peripheral registers to their default reset
<> 144:ef7eb2e8f9f7 580 * values, with deinitialization of the ADC MSP.
<> 144:ef7eb2e8f9f7 581 * @note For devices with several ADCs: reset of ADC common registers is done
<> 144:ef7eb2e8f9f7 582 * only if all ADCs sharing the same common group are disabled.
<> 144:ef7eb2e8f9f7 583 * If this is not the case, reset of these common parameters reset is
<> 144:ef7eb2e8f9f7 584 * bypassed without error reporting: it can be the intended behaviour in
<> 144:ef7eb2e8f9f7 585 * case of reset of a single ADC while the other ADCs sharing the same
<> 144:ef7eb2e8f9f7 586 * common group is still running.
<> 144:ef7eb2e8f9f7 587 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 588 * @retval HAL status
<> 144:ef7eb2e8f9f7 589 */
<> 144:ef7eb2e8f9f7 590 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 591 {
<> 144:ef7eb2e8f9f7 592 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /* Check ADC handle */
<> 144:ef7eb2e8f9f7 595 if(hadc == NULL)
<> 144:ef7eb2e8f9f7 596 {
<> 144:ef7eb2e8f9f7 597 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 598 }
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 /* Check the parameters */
<> 144:ef7eb2e8f9f7 601 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /* Set ADC state */
<> 144:ef7eb2e8f9f7 604 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 /* Stop potential conversion on going, on regular group */
<> 144:ef7eb2e8f9f7 607 tmp_hal_status = ADC_ConversionStop(hadc);
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /* Disable ADC peripheral if conversions are effectively stopped */
<> 144:ef7eb2e8f9f7 610 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 611 {
<> 144:ef7eb2e8f9f7 612 /* Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 613 tmp_hal_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 616 if (tmp_hal_status != HAL_ERROR)
<> 144:ef7eb2e8f9f7 617 {
<> 144:ef7eb2e8f9f7 618 /* Change ADC state */
<> 144:ef7eb2e8f9f7 619 hadc->State = HAL_ADC_STATE_READY;
<> 144:ef7eb2e8f9f7 620 }
<> 144:ef7eb2e8f9f7 621 }
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* Configuration of ADC parameters if previous preliminary actions are */
<> 144:ef7eb2e8f9f7 625 /* correctly completed. */
<> 144:ef7eb2e8f9f7 626 if (tmp_hal_status != HAL_ERROR)
<> 144:ef7eb2e8f9f7 627 {
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /* ========== Reset ADC registers ========== */
<> 144:ef7eb2e8f9f7 630 /* Reset register IER */
<> 144:ef7eb2e8f9f7 631 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD | ADC_IT_OVR | ADC_IT_EOCAL | ADC_IT_EOS | \
<> 144:ef7eb2e8f9f7 632 ADC_IT_EOC | ADC_IT_RDY | ADC_IT_EOSMP ));
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /* Reset register ISR */
<> 144:ef7eb2e8f9f7 636 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_EOCAL | ADC_FLAG_OVR | ADC_FLAG_EOS | \
<> 144:ef7eb2e8f9f7 637 ADC_FLAG_EOC | ADC_FLAG_EOSMP | ADC_FLAG_RDY));
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /* Reset register CR */
<> 144:ef7eb2e8f9f7 641 /* Disable voltage regulator */
<> 144:ef7eb2e8f9f7 642 /* Note: Regulator disable useful for power saving */
<> 144:ef7eb2e8f9f7 643 /* Reset ADVREGEN bit */
<> 144:ef7eb2e8f9f7 644 hadc->Instance->CR &= ~ADC_CR_ADVREGEN;
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 /* Bits ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode "read-set": no direct reset applicable */
<> 144:ef7eb2e8f9f7 647 /* No action */
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 /* Reset register CFGR1 */
<> 144:ef7eb2e8f9f7 650 hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | \
<> 144:ef7eb2e8f9f7 651 ADC_CFGR1_DISCEN | ADC_CFGR1_AUTOFF | ADC_CFGR1_AUTDLY | \
<> 144:ef7eb2e8f9f7 652 ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | ADC_CFGR1_EXTEN | \
<> 144:ef7eb2e8f9f7 653 ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES | \
<> 144:ef7eb2e8f9f7 654 ADC_CFGR1_SCANDIR| ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN);
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /* Reset register CFGR2 */
<> 144:ef7eb2e8f9f7 657 hadc->Instance->CFGR2 &= ~(ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR | \
<> 144:ef7eb2e8f9f7 658 ADC_CFGR2_OVSE | ADC_CFGR2_CKMODE );
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /* Reset register SMPR */
<> 144:ef7eb2e8f9f7 662 hadc->Instance->SMPR &= ~(ADC_SMPR_SMPR);
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /* Reset register TR */
<> 144:ef7eb2e8f9f7 665 hadc->Instance->TR &= ~(ADC_TR_LT | ADC_TR_HT);
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /* Reset register CALFACT */
<> 144:ef7eb2e8f9f7 668 hadc->Instance->CALFACT &= ~(ADC_CALFACT_CALFACT);
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /* Reset register DR */
<> 144:ef7eb2e8f9f7 675 /* bits in access mode read only, no direct reset applicable*/
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /* Reset register CALFACT */
<> 144:ef7eb2e8f9f7 678 hadc->Instance->CALFACT &= ~(ADC_CALFACT_CALFACT);
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 /* ========== Hard reset ADC peripheral ========== */
<> 144:ef7eb2e8f9f7 681 /* Performs a global reset of the entire ADC peripheral: ADC state is */
<> 144:ef7eb2e8f9f7 682 /* forced to a similar state after device power-on. */
<> 144:ef7eb2e8f9f7 683 /* If needed, copy-paste and uncomment the following reset code into */
<> 144:ef7eb2e8f9f7 684 /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
<> 144:ef7eb2e8f9f7 685 /* */
<> 144:ef7eb2e8f9f7 686 /* __HAL_RCC_ADC1_FORCE_RESET() */
<> 144:ef7eb2e8f9f7 687 /* __HAL_RCC_ADC1_RELEASE_RESET() */
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 690 HAL_ADC_MspDeInit(hadc);
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 /* Set ADC error code to none */
<> 144:ef7eb2e8f9f7 693 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /* Set ADC state */
<> 144:ef7eb2e8f9f7 696 hadc->State = HAL_ADC_STATE_RESET;
<> 144:ef7eb2e8f9f7 697 }
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /* Process unlocked */
<> 144:ef7eb2e8f9f7 700 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /* Return function status */
<> 144:ef7eb2e8f9f7 703 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 704 }
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 /**
<> 144:ef7eb2e8f9f7 708 * @brief Initializes the ADC MSP.
<> 144:ef7eb2e8f9f7 709 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 710 * @retval None
<> 144:ef7eb2e8f9f7 711 */
<> 144:ef7eb2e8f9f7 712 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 713 {
<> 144:ef7eb2e8f9f7 714 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 715 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 718 the HAL_ADC_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 719 */
<> 144:ef7eb2e8f9f7 720 }
<> 144:ef7eb2e8f9f7 721
<> 144:ef7eb2e8f9f7 722 /**
<> 144:ef7eb2e8f9f7 723 * @brief DeInitializes the ADC MSP.
<> 144:ef7eb2e8f9f7 724 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 725 * @retval None
<> 144:ef7eb2e8f9f7 726 */
<> 144:ef7eb2e8f9f7 727 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 728 {
<> 144:ef7eb2e8f9f7 729 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 730 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 733 function HAL_ADC_MspDeInit must be implemented in the user file.
<> 144:ef7eb2e8f9f7 734 */
<> 144:ef7eb2e8f9f7 735 }
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /**
<> 144:ef7eb2e8f9f7 738 * @}
<> 144:ef7eb2e8f9f7 739 */
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 /** @addtogroup ADC_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 742 * @brief I/O operation functions
<> 144:ef7eb2e8f9f7 743 *
<> 144:ef7eb2e8f9f7 744 @verbatim
<> 144:ef7eb2e8f9f7 745 ===============================================================================
<> 144:ef7eb2e8f9f7 746 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 747 ===============================================================================
<> 144:ef7eb2e8f9f7 748 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 749 (+) Start conversion of regular group.
<> 144:ef7eb2e8f9f7 750 (+) Stop conversion of regular group.
<> 144:ef7eb2e8f9f7 751 (+) Poll for conversion complete on regular group.
<> 144:ef7eb2e8f9f7 752 (+) poll for conversion event.
<> 144:ef7eb2e8f9f7 753 (+) Get result of regular channel conversion.
<> 144:ef7eb2e8f9f7 754 (+) Start conversion of regular group and enable interruptions.
<> 144:ef7eb2e8f9f7 755 (+) Stop conversion of regular group and disable interruptions.
<> 144:ef7eb2e8f9f7 756 (+) Handle ADC interrupt request
<> 144:ef7eb2e8f9f7 757 (+) Start conversion of regular group and enable DMA transfer.
<> 144:ef7eb2e8f9f7 758 (+) Stop conversion of regular group and disable ADC DMA transfer.
<> 144:ef7eb2e8f9f7 759 @endverbatim
<> 144:ef7eb2e8f9f7 760 * @{
<> 144:ef7eb2e8f9f7 761 */
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /**
<> 144:ef7eb2e8f9f7 765 * @brief Enables ADC, starts conversion of regular group.
<> 144:ef7eb2e8f9f7 766 * Interruptions enabled in this function: None.
<> 144:ef7eb2e8f9f7 767 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 768 * @retval HAL status
<> 144:ef7eb2e8f9f7 769 */
<> 144:ef7eb2e8f9f7 770 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 771 {
<> 144:ef7eb2e8f9f7 772 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 /* Check the parameters */
<> 144:ef7eb2e8f9f7 775 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 776
<> 144:ef7eb2e8f9f7 777 /* Perform ADC enable and conversion start if no conversion is on going */
<> 144:ef7eb2e8f9f7 778 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 779 {
<> 144:ef7eb2e8f9f7 780 /* Process locked */
<> 144:ef7eb2e8f9f7 781 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 784 /* If low power mode AutoPowerOff is enabled, power-on/off phases are */
<> 144:ef7eb2e8f9f7 785 /* performed automatically by hardware. */
<> 144:ef7eb2e8f9f7 786 if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
<> 144:ef7eb2e8f9f7 787 {
<> 144:ef7eb2e8f9f7 788 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 789 }
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 792 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 793 {
<> 144:ef7eb2e8f9f7 794 /* Set ADC state */
<> 144:ef7eb2e8f9f7 795 /* - Clear state bitfield related to regular group conversion results */
<> 144:ef7eb2e8f9f7 796 /* - Set state bitfield related to regular operation */
<> 144:ef7eb2e8f9f7 797 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 798 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
<> 144:ef7eb2e8f9f7 799 HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 802 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /* Process unlocked */
<> 144:ef7eb2e8f9f7 805 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 806 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 807 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /* Clear regular group conversion flag and overrun flag */
<> 144:ef7eb2e8f9f7 810 /* (To ensure of no unknown state from potential previous ADC */
<> 144:ef7eb2e8f9f7 811 /* operations) */
<> 144:ef7eb2e8f9f7 812 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /* Enable conversion of regular group. */
<> 144:ef7eb2e8f9f7 815 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 816 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 817 /* trigger event. */
<> 144:ef7eb2e8f9f7 818 hadc->Instance->CR |= ADC_CR_ADSTART;
<> 144:ef7eb2e8f9f7 819 }
<> 144:ef7eb2e8f9f7 820 }
<> 144:ef7eb2e8f9f7 821 else
<> 144:ef7eb2e8f9f7 822 {
<> 144:ef7eb2e8f9f7 823 tmp_hal_status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 824 }
<> 144:ef7eb2e8f9f7 825
<> 144:ef7eb2e8f9f7 826 /* Return function status */
<> 144:ef7eb2e8f9f7 827 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 828 }
<> 144:ef7eb2e8f9f7 829
<> 144:ef7eb2e8f9f7 830 /**
<> 144:ef7eb2e8f9f7 831 * @brief Stop ADC conversion of regular group, disable ADC peripheral.
<> 144:ef7eb2e8f9f7 832 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 833 * @retval HAL status.
<> 144:ef7eb2e8f9f7 834 */
<> 144:ef7eb2e8f9f7 835 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 836 {
<> 144:ef7eb2e8f9f7 837 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /* Check the parameters */
<> 144:ef7eb2e8f9f7 840 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 /* Process locked */
<> 144:ef7eb2e8f9f7 843 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /* 1. Stop potential conversion on going, on regular group */
<> 144:ef7eb2e8f9f7 846 tmp_hal_status = ADC_ConversionStop(hadc);
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 /* Disable ADC peripheral if conversions are effectively stopped */
<> 144:ef7eb2e8f9f7 849 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 850 {
<> 144:ef7eb2e8f9f7 851 /* 2. Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 852 tmp_hal_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 855 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 856 {
<> 144:ef7eb2e8f9f7 857 /* Set ADC state */
<> 144:ef7eb2e8f9f7 858 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 859 HAL_ADC_STATE_REG_BUSY,
<> 144:ef7eb2e8f9f7 860 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 861 }
<> 144:ef7eb2e8f9f7 862 }
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 /* Process unlocked */
<> 144:ef7eb2e8f9f7 865 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 /* Return function status */
<> 144:ef7eb2e8f9f7 868 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 869 }
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 /**
<> 144:ef7eb2e8f9f7 872 * @brief Wait for regular group conversion to be completed.
<> 144:ef7eb2e8f9f7 873 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
<> 144:ef7eb2e8f9f7 874 * conversion) are cleared by this function, with an exception:
<> 144:ef7eb2e8f9f7 875 * if low power feature "LowPowerAutoWait" is enabled, flags are
<> 144:ef7eb2e8f9f7 876 * not cleared to not interfere with this feature until data register
<> 144:ef7eb2e8f9f7 877 * is read using function HAL_ADC_GetValue().
<> 144:ef7eb2e8f9f7 878 * @note This function cannot be used in a particular setup: ADC configured
<> 144:ef7eb2e8f9f7 879 * in DMA mode and polling for end of each conversion (ADC init
<> 144:ef7eb2e8f9f7 880 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
<> 144:ef7eb2e8f9f7 881 * In this case, DMA resets the flag EOC and polling cannot be
<> 144:ef7eb2e8f9f7 882 * performed on each conversion. Nevertheless, polling can still
<> 144:ef7eb2e8f9f7 883 * be performed on the complete sequence (ADC init
<> 144:ef7eb2e8f9f7 884 * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
<> 144:ef7eb2e8f9f7 885 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 886 * @param Timeout: Timeout value in millisecond.
<> 144:ef7eb2e8f9f7 887 * @retval HAL status
<> 144:ef7eb2e8f9f7 888 */
<> 144:ef7eb2e8f9f7 889 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 890 {
<> 144:ef7eb2e8f9f7 891 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 892 uint32_t tmp_Flag_EOC;
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 /* Check the parameters */
<> 144:ef7eb2e8f9f7 895 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 896 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 /* If end of conversion selected to end of sequence */
<> 144:ef7eb2e8f9f7 899 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
<> 144:ef7eb2e8f9f7 900 {
<> 144:ef7eb2e8f9f7 901 tmp_Flag_EOC = ADC_FLAG_EOS;
<> 144:ef7eb2e8f9f7 902 }
<> 144:ef7eb2e8f9f7 903 /* If end of conversion selected to end of each conversion */
<> 144:ef7eb2e8f9f7 904 else /* ADC_EOC_SINGLE_CONV */
<> 144:ef7eb2e8f9f7 905 {
<> 144:ef7eb2e8f9f7 906 /* Verification that ADC configuration is compliant with polling for */
<> 144:ef7eb2e8f9f7 907 /* each conversion: */
<> 144:ef7eb2e8f9f7 908 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
<> 144:ef7eb2e8f9f7 909 /* several ranks and polling for end of each conversion. */
<> 144:ef7eb2e8f9f7 910 /* For code simplicity sake, this particular case is generalized to */
<> 144:ef7eb2e8f9f7 911 /* ADC configured in DMA mode and and polling for end of each conversion. */
<> 144:ef7eb2e8f9f7 912 if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN))
<> 144:ef7eb2e8f9f7 913 {
<> 144:ef7eb2e8f9f7 914 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 915 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 /* Process unlocked */
<> 144:ef7eb2e8f9f7 918 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 921 }
<> 144:ef7eb2e8f9f7 922 else
<> 144:ef7eb2e8f9f7 923 {
<> 144:ef7eb2e8f9f7 924 tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS);
<> 144:ef7eb2e8f9f7 925 }
<> 144:ef7eb2e8f9f7 926 }
<> 144:ef7eb2e8f9f7 927
<> 144:ef7eb2e8f9f7 928 /* Get tick count */
<> 144:ef7eb2e8f9f7 929 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 930
<> 144:ef7eb2e8f9f7 931 /* Wait until End of Conversion flag is raised */
<> 144:ef7eb2e8f9f7 932 while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
<> 144:ef7eb2e8f9f7 933 {
<> 144:ef7eb2e8f9f7 934 /* Check if timeout is disabled (set to infinite wait) */
<> 144:ef7eb2e8f9f7 935 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 936 {
<> 144:ef7eb2e8f9f7 937 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 938 {
<> 144:ef7eb2e8f9f7 939 /* Update ADC state machine to timeout */
<> 144:ef7eb2e8f9f7 940 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 /* Process unlocked */
<> 144:ef7eb2e8f9f7 943 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 944
<> 144:ef7eb2e8f9f7 945 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 946 }
<> 144:ef7eb2e8f9f7 947 }
<> 144:ef7eb2e8f9f7 948 }
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 /* Update ADC state machine */
<> 144:ef7eb2e8f9f7 951 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 /* Determine whether any further conversion upcoming on group regular */
<> 144:ef7eb2e8f9f7 954 /* by external trigger, continuous mode or scan sequence on going. */
<> 144:ef7eb2e8f9f7 955 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 956 (hadc->Init.ContinuousConvMode == DISABLE) )
<> 144:ef7eb2e8f9f7 957 {
<> 144:ef7eb2e8f9f7 958 /* If End of Sequence is reached, disable interrupts */
<> 144:ef7eb2e8f9f7 959 if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
<> 144:ef7eb2e8f9f7 960 {
<> 144:ef7eb2e8f9f7 961 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
<> 144:ef7eb2e8f9f7 962 /* ADSTART==0 (no conversion on going) */
<> 144:ef7eb2e8f9f7 963 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 964 {
<> 144:ef7eb2e8f9f7 965 /* Disable ADC end of single conversion interrupt on group regular */
<> 144:ef7eb2e8f9f7 966 /* Note: Overrun interrupt was enabled with EOC interrupt in */
<> 144:ef7eb2e8f9f7 967 /* HAL_Start_IT(), but is not disabled here because can be used */
<> 144:ef7eb2e8f9f7 968 /* by overrun IRQ process below. */
<> 144:ef7eb2e8f9f7 969 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 /* Set ADC state */
<> 144:ef7eb2e8f9f7 972 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 973 HAL_ADC_STATE_REG_BUSY,
<> 144:ef7eb2e8f9f7 974 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 975 }
<> 144:ef7eb2e8f9f7 976 else
<> 144:ef7eb2e8f9f7 977 {
<> 144:ef7eb2e8f9f7 978 /* Change ADC state to error state */
<> 144:ef7eb2e8f9f7 979 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 982 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 983 }
<> 144:ef7eb2e8f9f7 984 }
<> 144:ef7eb2e8f9f7 985 }
<> 144:ef7eb2e8f9f7 986
<> 144:ef7eb2e8f9f7 987 /* Clear end of conversion flag of regular group if low power feature */
<> 144:ef7eb2e8f9f7 988 /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
<> 144:ef7eb2e8f9f7 989 /* until data register is read using function HAL_ADC_GetValue(). */
<> 144:ef7eb2e8f9f7 990 if (hadc->Init.LowPowerAutoWait == DISABLE)
<> 144:ef7eb2e8f9f7 991 {
<> 144:ef7eb2e8f9f7 992 /* Clear regular group conversion flag */
<> 144:ef7eb2e8f9f7 993 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
<> 144:ef7eb2e8f9f7 994 }
<> 144:ef7eb2e8f9f7 995
<> 144:ef7eb2e8f9f7 996 /* Return ADC state */
<> 144:ef7eb2e8f9f7 997 return HAL_OK;
<> 144:ef7eb2e8f9f7 998 }
<> 144:ef7eb2e8f9f7 999
<> 144:ef7eb2e8f9f7 1000 /**
<> 144:ef7eb2e8f9f7 1001 * @brief Poll for conversion event.
<> 144:ef7eb2e8f9f7 1002 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1003 * @param EventType: the ADC event type.
<> 144:ef7eb2e8f9f7 1004 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1005 * @arg ADC_AWD_EVENT: ADC Analog watchdog event
<> 144:ef7eb2e8f9f7 1006 * @arg ADC_OVR_EVENT: ADC Overrun event
<> 144:ef7eb2e8f9f7 1007 * @param Timeout: Timeout value in millisecond.
<> 144:ef7eb2e8f9f7 1008 * @retval HAL status
<> 144:ef7eb2e8f9f7 1009 */
<> 144:ef7eb2e8f9f7 1010 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1011 {
<> 144:ef7eb2e8f9f7 1012 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1013
<> 144:ef7eb2e8f9f7 1014 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1015 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1016 assert_param(IS_ADC_EVENT_TYPE(EventType));
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 /* Get tick count */
<> 144:ef7eb2e8f9f7 1019 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 /* Check selected event flag */
<> 144:ef7eb2e8f9f7 1022 while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
<> 144:ef7eb2e8f9f7 1023 {
<> 144:ef7eb2e8f9f7 1024 /* Check if timeout is disabled (set to infinite wait) */
<> 144:ef7eb2e8f9f7 1025 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1026 {
<> 144:ef7eb2e8f9f7 1027 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1028 {
<> 144:ef7eb2e8f9f7 1029 /* Update ADC state machine to timeout */
<> 144:ef7eb2e8f9f7 1030 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 144:ef7eb2e8f9f7 1031
<> 144:ef7eb2e8f9f7 1032 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1033 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1036 }
<> 144:ef7eb2e8f9f7 1037 }
<> 144:ef7eb2e8f9f7 1038 }
<> 144:ef7eb2e8f9f7 1039
<> 144:ef7eb2e8f9f7 1040 switch(EventType)
<> 144:ef7eb2e8f9f7 1041 {
<> 144:ef7eb2e8f9f7 1042 /* Analog watchdog (level out of window) event */
<> 144:ef7eb2e8f9f7 1043 case ADC_AWD_EVENT:
<> 144:ef7eb2e8f9f7 1044 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1045 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 /* Clear ADC analog watchdog flag */
<> 144:ef7eb2e8f9f7 1048 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
<> 144:ef7eb2e8f9f7 1049 break;
<> 144:ef7eb2e8f9f7 1050
<> 144:ef7eb2e8f9f7 1051 /* Overrun event */
<> 144:ef7eb2e8f9f7 1052 default: /* Case ADC_OVR_EVENT */
<> 144:ef7eb2e8f9f7 1053 /* If overrun is set to overwrite previous data, overrun event is not */
<> 144:ef7eb2e8f9f7 1054 /* considered as an error. */
<> 144:ef7eb2e8f9f7 1055 /* (cf ref manual "Managing conversions without using the DMA and without */
<> 144:ef7eb2e8f9f7 1056 /* overrun ") */
<> 144:ef7eb2e8f9f7 1057 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
<> 144:ef7eb2e8f9f7 1058 {
<> 144:ef7eb2e8f9f7 1059 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1060 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
<> 144:ef7eb2e8f9f7 1061
<> 144:ef7eb2e8f9f7 1062 /* Set ADC error code to overrun */
<> 144:ef7eb2e8f9f7 1063 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
<> 144:ef7eb2e8f9f7 1064 }
<> 144:ef7eb2e8f9f7 1065
<> 144:ef7eb2e8f9f7 1066 /* Clear ADC Overrun flag */
<> 144:ef7eb2e8f9f7 1067 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<> 144:ef7eb2e8f9f7 1068 break;
<> 144:ef7eb2e8f9f7 1069 }
<> 144:ef7eb2e8f9f7 1070
<> 144:ef7eb2e8f9f7 1071 /* Return ADC state */
<> 144:ef7eb2e8f9f7 1072 return HAL_OK;
<> 144:ef7eb2e8f9f7 1073 }
<> 144:ef7eb2e8f9f7 1074
<> 144:ef7eb2e8f9f7 1075 /**
<> 144:ef7eb2e8f9f7 1076 * @brief Enables ADC, starts conversion of regular group with interruption.
<> 144:ef7eb2e8f9f7 1077 * Interruptions enabled in this function:
<> 144:ef7eb2e8f9f7 1078 * - EOC (end of conversion of regular group) or EOS (end of
<> 144:ef7eb2e8f9f7 1079 * sequence of regular group) depending on ADC initialization
<> 144:ef7eb2e8f9f7 1080 * parameter "EOCSelection"
<> 144:ef7eb2e8f9f7 1081 * - overrun (if available)
<> 144:ef7eb2e8f9f7 1082 * Each of these interruptions has its dedicated callback function.
<> 144:ef7eb2e8f9f7 1083 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1084 * @retval HAL status
<> 144:ef7eb2e8f9f7 1085 */
<> 144:ef7eb2e8f9f7 1086 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1087 {
<> 144:ef7eb2e8f9f7 1088 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1091 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 /* Perform ADC enable and conversion start if no conversion is on going */
<> 144:ef7eb2e8f9f7 1094 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1095 {
<> 144:ef7eb2e8f9f7 1096 /* Process locked */
<> 144:ef7eb2e8f9f7 1097 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1098
<> 144:ef7eb2e8f9f7 1099 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 1100 /* If low power mode AutoPowerOff is enabled, power-on/off phases are */
<> 144:ef7eb2e8f9f7 1101 /* performed automatically by hardware. */
<> 144:ef7eb2e8f9f7 1102 if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
<> 144:ef7eb2e8f9f7 1103 {
<> 144:ef7eb2e8f9f7 1104 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 1105 }
<> 144:ef7eb2e8f9f7 1106
<> 144:ef7eb2e8f9f7 1107 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 1108 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1109 {
<> 144:ef7eb2e8f9f7 1110 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1111 /* - Clear state bitfield related to regular group conversion results */
<> 144:ef7eb2e8f9f7 1112 /* - Set state bitfield related to regular operation */
<> 144:ef7eb2e8f9f7 1113 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 1114 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
<> 144:ef7eb2e8f9f7 1115 HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 1116
<> 144:ef7eb2e8f9f7 1117 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 1118 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 1119
<> 144:ef7eb2e8f9f7 1120 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1121 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 1122 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 1123 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1124
<> 144:ef7eb2e8f9f7 1125 /* Clear regular group conversion flag and overrun flag */
<> 144:ef7eb2e8f9f7 1126 /* (To ensure of no unknown state from potential previous ADC */
<> 144:ef7eb2e8f9f7 1127 /* operations) */
<> 144:ef7eb2e8f9f7 1128 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
<> 144:ef7eb2e8f9f7 1129
<> 144:ef7eb2e8f9f7 1130 /* Enable ADC end of conversion interrupt */
<> 144:ef7eb2e8f9f7 1131 /* Enable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 1132 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
<> 144:ef7eb2e8f9f7 1133 switch(hadc->Init.EOCSelection)
<> 144:ef7eb2e8f9f7 1134 {
<> 144:ef7eb2e8f9f7 1135 case ADC_EOC_SEQ_CONV:
<> 144:ef7eb2e8f9f7 1136 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
<> 144:ef7eb2e8f9f7 1137 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR));
<> 144:ef7eb2e8f9f7 1138 break;
<> 144:ef7eb2e8f9f7 1139 /* case ADC_EOC_SINGLE_CONV */
<> 144:ef7eb2e8f9f7 1140 default:
<> 144:ef7eb2e8f9f7 1141 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
<> 144:ef7eb2e8f9f7 1142 break;
<> 144:ef7eb2e8f9f7 1143 }
<> 144:ef7eb2e8f9f7 1144
<> 144:ef7eb2e8f9f7 1145 /* Enable conversion of regular group. */
<> 144:ef7eb2e8f9f7 1146 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 1147 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 1148 /* trigger event. */
<> 144:ef7eb2e8f9f7 1149 hadc->Instance->CR |= ADC_CR_ADSTART;
<> 144:ef7eb2e8f9f7 1150 }
<> 144:ef7eb2e8f9f7 1151 }
<> 144:ef7eb2e8f9f7 1152 else
<> 144:ef7eb2e8f9f7 1153 {
<> 144:ef7eb2e8f9f7 1154 tmp_hal_status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1155 }
<> 144:ef7eb2e8f9f7 1156
<> 144:ef7eb2e8f9f7 1157 /* Return function status */
<> 144:ef7eb2e8f9f7 1158 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1159 }
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 /**
<> 144:ef7eb2e8f9f7 1162 * @brief Stop ADC conversion of regular group, disable interruption of
<> 144:ef7eb2e8f9f7 1163 * end-of-conversion, disable ADC peripheral.
<> 144:ef7eb2e8f9f7 1164 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1165 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1166 */
<> 144:ef7eb2e8f9f7 1167 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1168 {
<> 144:ef7eb2e8f9f7 1169 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1172 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174 /* Process locked */
<> 144:ef7eb2e8f9f7 1175 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177 /* 1. Stop potential conversion on going, on regular group */
<> 144:ef7eb2e8f9f7 1178 tmp_hal_status = ADC_ConversionStop(hadc);
<> 144:ef7eb2e8f9f7 1179
<> 144:ef7eb2e8f9f7 1180 /* Disable ADC peripheral if conversions are effectively stopped */
<> 144:ef7eb2e8f9f7 1181 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1182 {
<> 144:ef7eb2e8f9f7 1183 /* Disable ADC end of conversion interrupt for regular group */
<> 144:ef7eb2e8f9f7 1184 /* Disable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 1185 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 /* 2. Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 1188 tmp_hal_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 1189
<> 144:ef7eb2e8f9f7 1190 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 1191 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1192 {
<> 144:ef7eb2e8f9f7 1193 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1194 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 1195 HAL_ADC_STATE_REG_BUSY,
<> 144:ef7eb2e8f9f7 1196 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1197 }
<> 144:ef7eb2e8f9f7 1198 }
<> 144:ef7eb2e8f9f7 1199
<> 144:ef7eb2e8f9f7 1200 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1201 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1202
<> 144:ef7eb2e8f9f7 1203 /* Return function status */
<> 144:ef7eb2e8f9f7 1204 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1205 }
<> 144:ef7eb2e8f9f7 1206
<> 144:ef7eb2e8f9f7 1207 /**
<> 144:ef7eb2e8f9f7 1208 * @brief Enables ADC, starts conversion of regular group and transfers result
<> 144:ef7eb2e8f9f7 1209 * through DMA.
<> 144:ef7eb2e8f9f7 1210 * Interruptions enabled in this function:
<> 144:ef7eb2e8f9f7 1211 * - DMA transfer complete
<> 144:ef7eb2e8f9f7 1212 * - DMA half transfer
<> 144:ef7eb2e8f9f7 1213 * - overrun
<> 144:ef7eb2e8f9f7 1214 * Each of these interruptions has its dedicated callback function.
<> 144:ef7eb2e8f9f7 1215 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1216 * @param pData: The destination Buffer address.
<> 144:ef7eb2e8f9f7 1217 * @param Length: The length of data to be transferred from ADC peripheral to memory.
<> 144:ef7eb2e8f9f7 1218 * @retval None
<> 144:ef7eb2e8f9f7 1219 */
<> 144:ef7eb2e8f9f7 1220 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
<> 144:ef7eb2e8f9f7 1221 {
<> 144:ef7eb2e8f9f7 1222 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1223
<> 144:ef7eb2e8f9f7 1224 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1225 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1226
<> 144:ef7eb2e8f9f7 1227 /* Perform ADC enable and conversion start if no conversion is on going */
<> 144:ef7eb2e8f9f7 1228 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1229 {
<> 144:ef7eb2e8f9f7 1230 /* Process locked */
<> 144:ef7eb2e8f9f7 1231 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1232
<> 144:ef7eb2e8f9f7 1233 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 1234 /* If low power mode AutoPowerOff is enabled, power-on/off phases are */
<> 144:ef7eb2e8f9f7 1235 /* performed automatically by hardware. */
<> 144:ef7eb2e8f9f7 1236 if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
<> 144:ef7eb2e8f9f7 1237 {
<> 144:ef7eb2e8f9f7 1238 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 1239 }
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 1242 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1243 {
<> 144:ef7eb2e8f9f7 1244 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1245 /* - Clear state bitfield related to regular group conversion results */
<> 144:ef7eb2e8f9f7 1246 /* - Set state bitfield related to regular operation */
<> 144:ef7eb2e8f9f7 1247 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 1248 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
<> 144:ef7eb2e8f9f7 1249 HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 1250
<> 144:ef7eb2e8f9f7 1251 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 1252 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 1253
<> 144:ef7eb2e8f9f7 1254 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1255 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 1256 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 1257 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1258
<> 144:ef7eb2e8f9f7 1259 /* Set the DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1260 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
<> 144:ef7eb2e8f9f7 1261
<> 144:ef7eb2e8f9f7 1262 /* Set the DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 1263 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
<> 144:ef7eb2e8f9f7 1264
<> 144:ef7eb2e8f9f7 1265 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1266 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
<> 144:ef7eb2e8f9f7 1267
<> 144:ef7eb2e8f9f7 1268
<> 144:ef7eb2e8f9f7 1269 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
<> 144:ef7eb2e8f9f7 1270 /* start (in case of SW start): */
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 /* Clear regular group conversion flag and overrun flag */
<> 144:ef7eb2e8f9f7 1273 /* (To ensure of no unknown state from potential previous ADC */
<> 144:ef7eb2e8f9f7 1274 /* operations) */
<> 144:ef7eb2e8f9f7 1275 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
<> 144:ef7eb2e8f9f7 1276
<> 144:ef7eb2e8f9f7 1277 /* Enable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 1278 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 /* Enable ADC DMA mode */
<> 144:ef7eb2e8f9f7 1281 hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN;
<> 144:ef7eb2e8f9f7 1282
<> 144:ef7eb2e8f9f7 1283 /* Start the DMA channel */
<> 144:ef7eb2e8f9f7 1284 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1285
<> 144:ef7eb2e8f9f7 1286 /* Enable conversion of regular group. */
<> 144:ef7eb2e8f9f7 1287 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 1288 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 1289 /* trigger event. */
<> 144:ef7eb2e8f9f7 1290 hadc->Instance->CR |= ADC_CR_ADSTART;
<> 144:ef7eb2e8f9f7 1291 }
<> 144:ef7eb2e8f9f7 1292 }
<> 144:ef7eb2e8f9f7 1293 else
<> 144:ef7eb2e8f9f7 1294 {
<> 144:ef7eb2e8f9f7 1295 tmp_hal_status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1296 }
<> 144:ef7eb2e8f9f7 1297
<> 144:ef7eb2e8f9f7 1298 /* Return function status */
<> 144:ef7eb2e8f9f7 1299 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1300 }
<> 144:ef7eb2e8f9f7 1301
<> 144:ef7eb2e8f9f7 1302 /**
<> 144:ef7eb2e8f9f7 1303 * @brief Stop ADC conversion of regular group, disable ADC DMA transfer, disable
<> 144:ef7eb2e8f9f7 1304 * ADC peripheral.
<> 144:ef7eb2e8f9f7 1305 * Each of these interruptions has its dedicated callback function.
<> 144:ef7eb2e8f9f7 1306 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1307 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1308 */
<> 144:ef7eb2e8f9f7 1309 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1310 {
<> 144:ef7eb2e8f9f7 1311 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1312
<> 144:ef7eb2e8f9f7 1313 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1314 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1315
<> 144:ef7eb2e8f9f7 1316 /* Process locked */
<> 144:ef7eb2e8f9f7 1317 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1318
<> 144:ef7eb2e8f9f7 1319 /* 1. Stop potential conversion on going, on regular group */
<> 144:ef7eb2e8f9f7 1320 tmp_hal_status = ADC_ConversionStop(hadc);
<> 144:ef7eb2e8f9f7 1321
<> 144:ef7eb2e8f9f7 1322 /* Disable ADC peripheral if conversions are effectively stopped */
<> 144:ef7eb2e8f9f7 1323 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1324 {
<> 144:ef7eb2e8f9f7 1325 /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
<> 144:ef7eb2e8f9f7 1326 hadc->Instance->CFGR1 &= ~ADC_CFGR1_DMAEN;
<> 144:ef7eb2e8f9f7 1327
<> 144:ef7eb2e8f9f7 1328 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
<> 144:ef7eb2e8f9f7 1329 /* while DMA transfer is on going) */
<> 144:ef7eb2e8f9f7 1330 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
<> 144:ef7eb2e8f9f7 1331
<> 144:ef7eb2e8f9f7 1332 /* Check if DMA channel effectively disabled */
<> 144:ef7eb2e8f9f7 1333 if (tmp_hal_status != HAL_OK)
<> 144:ef7eb2e8f9f7 1334 {
<> 144:ef7eb2e8f9f7 1335 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1336 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<> 144:ef7eb2e8f9f7 1337 }
<> 144:ef7eb2e8f9f7 1338
<> 144:ef7eb2e8f9f7 1339 /* Disable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 1340 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
<> 144:ef7eb2e8f9f7 1341
<> 144:ef7eb2e8f9f7 1342 /* 2. Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 1343 /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */
<> 144:ef7eb2e8f9f7 1344 /* in memory a potential failing status. */
<> 144:ef7eb2e8f9f7 1345 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1346 {
<> 144:ef7eb2e8f9f7 1347 tmp_hal_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 1348 }
<> 144:ef7eb2e8f9f7 1349 else
<> 144:ef7eb2e8f9f7 1350 {
<> 144:ef7eb2e8f9f7 1351 ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 1352 }
<> 144:ef7eb2e8f9f7 1353
<> 144:ef7eb2e8f9f7 1354 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 1355 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1356 {
<> 144:ef7eb2e8f9f7 1357 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1358 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 1359 HAL_ADC_STATE_REG_BUSY,
<> 144:ef7eb2e8f9f7 1360 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1361 }
<> 144:ef7eb2e8f9f7 1362 }
<> 144:ef7eb2e8f9f7 1363
<> 144:ef7eb2e8f9f7 1364 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1365 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1366
<> 144:ef7eb2e8f9f7 1367 /* Return function status */
<> 144:ef7eb2e8f9f7 1368 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1369 }
<> 144:ef7eb2e8f9f7 1370
<> 144:ef7eb2e8f9f7 1371 /**
<> 144:ef7eb2e8f9f7 1372 * @brief Get ADC regular group conversion result.
<> 144:ef7eb2e8f9f7 1373 * @note Reading DR register automatically clears EOC (end of conversion of
<> 144:ef7eb2e8f9f7 1374 * regular group) flag.
<> 144:ef7eb2e8f9f7 1375 * @note This function does not clear ADC flag EOS
<> 144:ef7eb2e8f9f7 1376 * (ADC group regular end of sequence conversion).
<> 144:ef7eb2e8f9f7 1377 * Occurrence of flag EOS rising:
<> 144:ef7eb2e8f9f7 1378 * - If sequencer is composed of 1 rank, flag EOS is equivalent
<> 144:ef7eb2e8f9f7 1379 * to flag EOC.
<> 144:ef7eb2e8f9f7 1380 * - If sequencer is composed of several ranks, during the scan
<> 144:ef7eb2e8f9f7 1381 * sequence flag EOC only is raised, at the end of the scan sequence
<> 144:ef7eb2e8f9f7 1382 * both flags EOC and EOS are raised.
<> 144:ef7eb2e8f9f7 1383 * To clear this flag, either use function:
<> 144:ef7eb2e8f9f7 1384 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
<> 144:ef7eb2e8f9f7 1385 * model polling: @ref HAL_ADC_PollForConversion()
<> 144:ef7eb2e8f9f7 1386 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
<> 144:ef7eb2e8f9f7 1387 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1388 * @retval Converted value
<> 144:ef7eb2e8f9f7 1389 */
<> 144:ef7eb2e8f9f7 1390 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1391 {
<> 144:ef7eb2e8f9f7 1392 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1393 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1394
<> 144:ef7eb2e8f9f7 1395 /* Note: EOC flag is not cleared here by software because automatically */
<> 144:ef7eb2e8f9f7 1396 /* cleared by hardware when reading register DR. */
<> 144:ef7eb2e8f9f7 1397
<> 144:ef7eb2e8f9f7 1398 /* Return ADC converted value */
<> 144:ef7eb2e8f9f7 1399 return hadc->Instance->DR;
<> 144:ef7eb2e8f9f7 1400 }
<> 144:ef7eb2e8f9f7 1401
<> 144:ef7eb2e8f9f7 1402 /**
<> 144:ef7eb2e8f9f7 1403 * @brief Handles ADC interrupt request.
<> 144:ef7eb2e8f9f7 1404 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1405 * @retval None
<> 144:ef7eb2e8f9f7 1406 */
<> 144:ef7eb2e8f9f7 1407 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1408 {
<> 144:ef7eb2e8f9f7 1409 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1410 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1411 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
<> 144:ef7eb2e8f9f7 1412
<> 144:ef7eb2e8f9f7 1413 /* ========== Check End of Conversion flag for regular group ========== */
<> 144:ef7eb2e8f9f7 1414 if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) ||
<> 144:ef7eb2e8f9f7 1415 (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) )
<> 144:ef7eb2e8f9f7 1416 {
<> 144:ef7eb2e8f9f7 1417 /* Update state machine on conversion status if not in error state */
<> 144:ef7eb2e8f9f7 1418 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<> 144:ef7eb2e8f9f7 1419 {
<> 144:ef7eb2e8f9f7 1420 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1421 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<> 144:ef7eb2e8f9f7 1422 }
<> 144:ef7eb2e8f9f7 1423
<> 144:ef7eb2e8f9f7 1424 /* Determine whether any further conversion upcoming on group regular */
<> 144:ef7eb2e8f9f7 1425 /* by external trigger, continuous mode or scan sequence on going. */
<> 144:ef7eb2e8f9f7 1426 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 1427 (hadc->Init.ContinuousConvMode == DISABLE) )
<> 144:ef7eb2e8f9f7 1428 {
<> 144:ef7eb2e8f9f7 1429 /* If End of Sequence is reached, disable interrupts */
<> 144:ef7eb2e8f9f7 1430 if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
<> 144:ef7eb2e8f9f7 1431 {
<> 144:ef7eb2e8f9f7 1432 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
<> 144:ef7eb2e8f9f7 1433 /* ADSTART==0 (no conversion on going) */
<> 144:ef7eb2e8f9f7 1434 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1435 {
<> 144:ef7eb2e8f9f7 1436 /* Disable ADC end of single conversion interrupt on group regular */
<> 144:ef7eb2e8f9f7 1437 /* Note: Overrun interrupt was enabled with EOC interrupt in */
<> 144:ef7eb2e8f9f7 1438 /* HAL_Start_IT(), but is not disabled here because can be used */
<> 144:ef7eb2e8f9f7 1439 /* by overrun IRQ process below. */
<> 144:ef7eb2e8f9f7 1440 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
<> 144:ef7eb2e8f9f7 1441
<> 144:ef7eb2e8f9f7 1442 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1443 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 1444 HAL_ADC_STATE_REG_BUSY,
<> 144:ef7eb2e8f9f7 1445 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1446 }
<> 144:ef7eb2e8f9f7 1447 else
<> 144:ef7eb2e8f9f7 1448 {
<> 144:ef7eb2e8f9f7 1449 /* Change ADC state to error state */
<> 144:ef7eb2e8f9f7 1450 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 1451
<> 144:ef7eb2e8f9f7 1452 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 1453 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 1454 }
<> 144:ef7eb2e8f9f7 1455 }
<> 144:ef7eb2e8f9f7 1456 }
<> 144:ef7eb2e8f9f7 1457
<> 144:ef7eb2e8f9f7 1458 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 1459 /* Note: into callback, to determine if conversion has been triggered */
<> 144:ef7eb2e8f9f7 1460 /* from EOC or EOS, possibility to use: */
<> 144:ef7eb2e8f9f7 1461 /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
<> 144:ef7eb2e8f9f7 1462 HAL_ADC_ConvCpltCallback(hadc);
<> 144:ef7eb2e8f9f7 1463
<> 144:ef7eb2e8f9f7 1464
<> 144:ef7eb2e8f9f7 1465 /* Clear regular group conversion flag */
<> 144:ef7eb2e8f9f7 1466 /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
<> 144:ef7eb2e8f9f7 1467 /* conversion flags clear induces the release of the preserved data.*/
<> 144:ef7eb2e8f9f7 1468 /* Therefore, if the preserved data value is needed, it must be */
<> 144:ef7eb2e8f9f7 1469 /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
<> 144:ef7eb2e8f9f7 1470 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
<> 144:ef7eb2e8f9f7 1471 }
<> 144:ef7eb2e8f9f7 1472
<> 144:ef7eb2e8f9f7 1473 /* ========== Check Analog watchdog flags ========== */
<> 144:ef7eb2e8f9f7 1474 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
<> 144:ef7eb2e8f9f7 1475 {
<> 144:ef7eb2e8f9f7 1476 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1477 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
<> 144:ef7eb2e8f9f7 1478
<> 144:ef7eb2e8f9f7 1479 /* Level out of window callback */
<> 144:ef7eb2e8f9f7 1480 HAL_ADC_LevelOutOfWindowCallback(hadc);
<> 144:ef7eb2e8f9f7 1481
<> 144:ef7eb2e8f9f7 1482 /* Clear ADC Analog watchdog flag */
<> 144:ef7eb2e8f9f7 1483 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
<> 144:ef7eb2e8f9f7 1484
<> 144:ef7eb2e8f9f7 1485 }
<> 144:ef7eb2e8f9f7 1486
<> 144:ef7eb2e8f9f7 1487
<> 144:ef7eb2e8f9f7 1488 /* ========== Check Overrun flag ========== */
<> 144:ef7eb2e8f9f7 1489 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
<> 144:ef7eb2e8f9f7 1490 {
<> 144:ef7eb2e8f9f7 1491 /* If overrun is set to overwrite previous data (default setting), */
<> 144:ef7eb2e8f9f7 1492 /* overrun event is not considered as an error. */
<> 144:ef7eb2e8f9f7 1493 /* (cf ref manual "Managing conversions without using the DMA and without */
<> 144:ef7eb2e8f9f7 1494 /* overrun ") */
<> 144:ef7eb2e8f9f7 1495 /* Exception for usage with DMA overrun event always considered as an */
<> 144:ef7eb2e8f9f7 1496 /* error. */
<> 144:ef7eb2e8f9f7 1497 if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) ||
<> 144:ef7eb2e8f9f7 1498 HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) )
<> 144:ef7eb2e8f9f7 1499 {
<> 144:ef7eb2e8f9f7 1500 /* Set ADC error code to overrun */
<> 144:ef7eb2e8f9f7 1501 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
<> 144:ef7eb2e8f9f7 1502
<> 144:ef7eb2e8f9f7 1503 /* Clear ADC overrun flag */
<> 144:ef7eb2e8f9f7 1504 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<> 144:ef7eb2e8f9f7 1505
<> 144:ef7eb2e8f9f7 1506 /* Error callback */
<> 144:ef7eb2e8f9f7 1507 HAL_ADC_ErrorCallback(hadc);
<> 144:ef7eb2e8f9f7 1508 }
<> 144:ef7eb2e8f9f7 1509
<> 144:ef7eb2e8f9f7 1510 /* Clear the Overrun flag */
<> 144:ef7eb2e8f9f7 1511 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<> 144:ef7eb2e8f9f7 1512 }
<> 144:ef7eb2e8f9f7 1513 }
<> 144:ef7eb2e8f9f7 1514
<> 144:ef7eb2e8f9f7 1515 /**
<> 144:ef7eb2e8f9f7 1516 * @brief Conversion complete callback in non blocking mode
<> 144:ef7eb2e8f9f7 1517 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1518 * @retval None
<> 144:ef7eb2e8f9f7 1519 */
<> 144:ef7eb2e8f9f7 1520 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1521 {
<> 144:ef7eb2e8f9f7 1522 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1523 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 1524
<> 144:ef7eb2e8f9f7 1525 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 1526 function HAL_ADC_ConvCpltCallback must be implemented in the user file.
<> 144:ef7eb2e8f9f7 1527 */
<> 144:ef7eb2e8f9f7 1528 }
<> 144:ef7eb2e8f9f7 1529
<> 144:ef7eb2e8f9f7 1530 /**
<> 144:ef7eb2e8f9f7 1531 * @brief Conversion DMA half-transfer callback in non blocking mode
<> 144:ef7eb2e8f9f7 1532 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1533 * @retval None
<> 144:ef7eb2e8f9f7 1534 */
<> 144:ef7eb2e8f9f7 1535 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1536 {
<> 144:ef7eb2e8f9f7 1537 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1538 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 1539
<> 144:ef7eb2e8f9f7 1540 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 1541 function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
<> 144:ef7eb2e8f9f7 1542 */
<> 144:ef7eb2e8f9f7 1543 }
<> 144:ef7eb2e8f9f7 1544
<> 144:ef7eb2e8f9f7 1545 /**
<> 144:ef7eb2e8f9f7 1546 * @brief Analog watchdog callback in non blocking mode.
<> 144:ef7eb2e8f9f7 1547 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1548 * @retval None
<> 144:ef7eb2e8f9f7 1549 */
<> 144:ef7eb2e8f9f7 1550 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1551 {
<> 144:ef7eb2e8f9f7 1552 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1553 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 1554
<> 144:ef7eb2e8f9f7 1555 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 1556 function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file.
<> 144:ef7eb2e8f9f7 1557 */
<> 144:ef7eb2e8f9f7 1558 }
<> 144:ef7eb2e8f9f7 1559
<> 144:ef7eb2e8f9f7 1560 /**
<> 144:ef7eb2e8f9f7 1561 * @brief ADC error callback in non blocking mode
<> 144:ef7eb2e8f9f7 1562 * (ADC conversion with interruption or transfer by DMA)
<> 144:ef7eb2e8f9f7 1563 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1564 * @retval None
<> 144:ef7eb2e8f9f7 1565 */
<> 144:ef7eb2e8f9f7 1566 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
<> 144:ef7eb2e8f9f7 1567 {
<> 144:ef7eb2e8f9f7 1568 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1569 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 1570
<> 144:ef7eb2e8f9f7 1571 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 1572 function HAL_ADC_ErrorCallback must be implemented in the user file.
<> 144:ef7eb2e8f9f7 1573 */
<> 144:ef7eb2e8f9f7 1574 }
<> 144:ef7eb2e8f9f7 1575
<> 144:ef7eb2e8f9f7 1576 /**
<> 144:ef7eb2e8f9f7 1577 * @}
<> 144:ef7eb2e8f9f7 1578 */
<> 144:ef7eb2e8f9f7 1579
<> 144:ef7eb2e8f9f7 1580 /** @addtogroup ADC_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 1581 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 1582 *
<> 144:ef7eb2e8f9f7 1583 @verbatim
<> 144:ef7eb2e8f9f7 1584 ===============================================================================
<> 144:ef7eb2e8f9f7 1585 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1586 ===============================================================================
<> 144:ef7eb2e8f9f7 1587 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1588 (+) Configure channels on regular group
<> 144:ef7eb2e8f9f7 1589 (+) Configure the analog watchdog
<> 144:ef7eb2e8f9f7 1590
<> 144:ef7eb2e8f9f7 1591 @endverbatim
<> 144:ef7eb2e8f9f7 1592 * @{
<> 144:ef7eb2e8f9f7 1593 */
<> 144:ef7eb2e8f9f7 1594
<> 144:ef7eb2e8f9f7 1595
<> 144:ef7eb2e8f9f7 1596 /**
<> 144:ef7eb2e8f9f7 1597 * @brief Configures the the selected channel to be linked to the regular
<> 144:ef7eb2e8f9f7 1598 * group.
<> 144:ef7eb2e8f9f7 1599 * @note In case of usage of internal measurement channels:
<> 144:ef7eb2e8f9f7 1600 * VrefInt/Vlcd(STM32L0x3xx only)/TempSensor.
<> 144:ef7eb2e8f9f7 1601 * Sampling time constraints must be respected (sampling time can be
<> 144:ef7eb2e8f9f7 1602 * adjusted in function of ADC clock frequency and sampling time
<> 144:ef7eb2e8f9f7 1603 * setting).
<> 144:ef7eb2e8f9f7 1604 * Refer to device datasheet for timings values, parameters TS_vrefint,
<> 144:ef7eb2e8f9f7 1605 * TS_vlcd (STM32L0x3xx only), TS_temp (values rough order: 5us to 17us).
<> 144:ef7eb2e8f9f7 1606 * These internal paths can be be disabled using function
<> 144:ef7eb2e8f9f7 1607 * HAL_ADC_DeInit().
<> 144:ef7eb2e8f9f7 1608 * @note Possibility to update parameters on the fly:
<> 144:ef7eb2e8f9f7 1609 * This function initializes channel into regular group, following
<> 144:ef7eb2e8f9f7 1610 * calls to this function can be used to reconfigure some parameters
<> 144:ef7eb2e8f9f7 1611 * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
<> 144:ef7eb2e8f9f7 1612 * the ADC.
<> 144:ef7eb2e8f9f7 1613 * The setting of these parameters is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 1614 * For parameters constraints, see comments of structure
<> 144:ef7eb2e8f9f7 1615 * "ADC_ChannelConfTypeDef".
<> 144:ef7eb2e8f9f7 1616 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1617 * @param sConfig: Structure of ADC channel for regular group.
<> 144:ef7eb2e8f9f7 1618 * @retval HAL status
<> 144:ef7eb2e8f9f7 1619 */
<> 144:ef7eb2e8f9f7 1620 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 1621 {
<> 144:ef7eb2e8f9f7 1622 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1623 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1624 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
<> 144:ef7eb2e8f9f7 1625 assert_param(IS_ADC_RANK(sConfig->Rank));
<> 144:ef7eb2e8f9f7 1626
<> 144:ef7eb2e8f9f7 1627 /* Process locked */
<> 144:ef7eb2e8f9f7 1628 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1629
<> 144:ef7eb2e8f9f7 1630 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 1631 /* Parameters that can be updated when ADC is disabled or enabled without */
<> 144:ef7eb2e8f9f7 1632 /* conversion on going on regular group: */
<> 144:ef7eb2e8f9f7 1633 /* - Channel number */
<> 144:ef7eb2e8f9f7 1634 /* - Management of internal measurement channels: Vbat/VrefInt/TempSensor */
<> 144:ef7eb2e8f9f7 1635 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET)
<> 144:ef7eb2e8f9f7 1636 {
<> 144:ef7eb2e8f9f7 1637 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1638 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 1639 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1640 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1641 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1642 }
<> 144:ef7eb2e8f9f7 1643
<> 144:ef7eb2e8f9f7 1644 if (sConfig->Rank != ADC_RANK_NONE)
<> 144:ef7eb2e8f9f7 1645 {
<> 144:ef7eb2e8f9f7 1646 /* Enable selected channels */
<> 144:ef7eb2e8f9f7 1647 hadc->Instance->CHSELR |= (uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK);
<> 144:ef7eb2e8f9f7 1648
<> 144:ef7eb2e8f9f7 1649 /* Management of internal measurement channels: Vlcd (STM32L0x3xx only)/VrefInt/TempSensor */
<> 144:ef7eb2e8f9f7 1650 /* internal measurement paths enable: If internal channel selected, enable */
<> 144:ef7eb2e8f9f7 1651 /* dedicated internal buffers and path. */
<> 144:ef7eb2e8f9f7 1652
<> 144:ef7eb2e8f9f7 1653 /* If Temperature sensor channel is selected, then enable the internal */
<> 144:ef7eb2e8f9f7 1654 /* buffers and path */
<> 144:ef7eb2e8f9f7 1655 if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_TEMPSENSOR ) == (ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_MASK))
<> 144:ef7eb2e8f9f7 1656 {
<> 144:ef7eb2e8f9f7 1657 ADC->CCR |= ADC_CCR_TSEN;
<> 144:ef7eb2e8f9f7 1658
<> 144:ef7eb2e8f9f7 1659 /* Delay for temperature sensor stabilization time */
<> 144:ef7eb2e8f9f7 1660 ADC_DelayMicroSecond(ADC_TEMPSENSOR_DELAY_US);
<> 144:ef7eb2e8f9f7 1661 }
<> 144:ef7eb2e8f9f7 1662
<> 144:ef7eb2e8f9f7 1663 /* If VRefInt channel is selected, then enable the internal buffers and path */
<> 144:ef7eb2e8f9f7 1664 if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VREFINT) == (ADC_CHANNEL_VREFINT & ADC_CHANNEL_MASK))
<> 144:ef7eb2e8f9f7 1665 {
<> 144:ef7eb2e8f9f7 1666 ADC->CCR |= ADC_CCR_VREFEN;
<> 144:ef7eb2e8f9f7 1667 }
<> 144:ef7eb2e8f9f7 1668
<> 144:ef7eb2e8f9f7 1669 #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 1670 /* If Vlcd channel is selected, then enable the internal buffers and path */
<> 144:ef7eb2e8f9f7 1671 if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VLCD) == (ADC_CHANNEL_VLCD & ADC_CHANNEL_MASK))
<> 144:ef7eb2e8f9f7 1672 {
<> 144:ef7eb2e8f9f7 1673 ADC->CCR |= ADC_CCR_VLCDEN;
<> 144:ef7eb2e8f9f7 1674 }
<> 144:ef7eb2e8f9f7 1675 #endif
<> 144:ef7eb2e8f9f7 1676 }
<> 144:ef7eb2e8f9f7 1677 else
<> 144:ef7eb2e8f9f7 1678 {
<> 144:ef7eb2e8f9f7 1679 /* Regular sequence configuration */
<> 144:ef7eb2e8f9f7 1680 /* Reset the channel selection register from the selected channel */
<> 144:ef7eb2e8f9f7 1681 hadc->Instance->CHSELR &= ~((uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK));
<> 144:ef7eb2e8f9f7 1682
<> 144:ef7eb2e8f9f7 1683 /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
<> 144:ef7eb2e8f9f7 1684 /* internal measurement paths disable: If internal channel selected, */
<> 144:ef7eb2e8f9f7 1685 /* disable dedicated internal buffers and path. */
<> 144:ef7eb2e8f9f7 1686 if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_TEMPSENSOR ) == (ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_MASK))
<> 144:ef7eb2e8f9f7 1687 {
<> 144:ef7eb2e8f9f7 1688 ADC->CCR &= ~ADC_CCR_TSEN;
<> 144:ef7eb2e8f9f7 1689 }
<> 144:ef7eb2e8f9f7 1690
<> 144:ef7eb2e8f9f7 1691 /* If VRefInt channel is selected, then enable the internal buffers and path */
<> 144:ef7eb2e8f9f7 1692 if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VREFINT) == (ADC_CHANNEL_VREFINT & ADC_CHANNEL_MASK))
<> 144:ef7eb2e8f9f7 1693 {
<> 144:ef7eb2e8f9f7 1694 ADC->CCR &= ~ADC_CCR_VREFEN;
<> 144:ef7eb2e8f9f7 1695 }
<> 144:ef7eb2e8f9f7 1696
<> 144:ef7eb2e8f9f7 1697 #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 1698 /* If Vlcd channel is selected, then enable the internal buffers and path */
<> 144:ef7eb2e8f9f7 1699 if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VLCD) == (ADC_CHANNEL_VLCD & ADC_CHANNEL_MASK))
<> 144:ef7eb2e8f9f7 1700 {
<> 144:ef7eb2e8f9f7 1701 ADC->CCR &= ~ADC_CCR_VLCDEN;
<> 144:ef7eb2e8f9f7 1702 }
<> 144:ef7eb2e8f9f7 1703 #endif
<> 144:ef7eb2e8f9f7 1704 }
<> 144:ef7eb2e8f9f7 1705
<> 144:ef7eb2e8f9f7 1706 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1707 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1708
<> 144:ef7eb2e8f9f7 1709 /* Return function status */
<> 144:ef7eb2e8f9f7 1710 return HAL_OK;
<> 144:ef7eb2e8f9f7 1711 }
<> 144:ef7eb2e8f9f7 1712
<> 144:ef7eb2e8f9f7 1713 /**
<> 144:ef7eb2e8f9f7 1714 * @brief Configures the analog watchdog.
<> 144:ef7eb2e8f9f7 1715 * @note Possibility to update parameters on the fly:
<> 144:ef7eb2e8f9f7 1716 * This function initializes the selected analog watchdog, following
<> 144:ef7eb2e8f9f7 1717 * calls to this function can be used to reconfigure some parameters
<> 144:ef7eb2e8f9f7 1718 * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
<> 144:ef7eb2e8f9f7 1719 * the ADC.
<> 144:ef7eb2e8f9f7 1720 * The setting of these parameters is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 1721 * For parameters constraints, see comments of structure
<> 144:ef7eb2e8f9f7 1722 * "ADC_AnalogWDGConfTypeDef".
<> 144:ef7eb2e8f9f7 1723 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1724 * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
<> 144:ef7eb2e8f9f7 1725 * @retval HAL status
<> 144:ef7eb2e8f9f7 1726 */
<> 144:ef7eb2e8f9f7 1727 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
<> 144:ef7eb2e8f9f7 1728 {
<> 144:ef7eb2e8f9f7 1729 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1730
<> 144:ef7eb2e8f9f7 1731 uint32_t tmpAWDHighThresholdShifted;
<> 144:ef7eb2e8f9f7 1732 uint32_t tmpAWDLowThresholdShifted;
<> 144:ef7eb2e8f9f7 1733
<> 144:ef7eb2e8f9f7 1734 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1735 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1736 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
<> 144:ef7eb2e8f9f7 1737 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
<> 144:ef7eb2e8f9f7 1738 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
<> 144:ef7eb2e8f9f7 1739
<> 144:ef7eb2e8f9f7 1740 /* Verify if threshold is within the selected ADC resolution */
<> 144:ef7eb2e8f9f7 1741 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
<> 144:ef7eb2e8f9f7 1742 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
<> 144:ef7eb2e8f9f7 1743
<> 144:ef7eb2e8f9f7 1744 if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
<> 144:ef7eb2e8f9f7 1745 {
<> 144:ef7eb2e8f9f7 1746 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
<> 144:ef7eb2e8f9f7 1747 }
<> 144:ef7eb2e8f9f7 1748
<> 144:ef7eb2e8f9f7 1749 /* Process locked */
<> 144:ef7eb2e8f9f7 1750 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1751
<> 144:ef7eb2e8f9f7 1752 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 1753 /* Parameters that can be updated when ADC is disabled or enabled without */
<> 144:ef7eb2e8f9f7 1754 /* conversion on going on regular group: */
<> 144:ef7eb2e8f9f7 1755 /* - Analog watchdog channels */
<> 144:ef7eb2e8f9f7 1756 /* - Analog watchdog thresholds */
<> 144:ef7eb2e8f9f7 1757 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1758 {
<> 144:ef7eb2e8f9f7 1759 /* Configure ADC Analog watchdog interrupt */
<> 144:ef7eb2e8f9f7 1760 if(AnalogWDGConfig->ITMode == ENABLE)
<> 144:ef7eb2e8f9f7 1761 {
<> 144:ef7eb2e8f9f7 1762 /* Enable the ADC Analog watchdog interrupt */
<> 144:ef7eb2e8f9f7 1763 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
<> 144:ef7eb2e8f9f7 1764 }
<> 144:ef7eb2e8f9f7 1765 else
<> 144:ef7eb2e8f9f7 1766 {
<> 144:ef7eb2e8f9f7 1767 /* Disable the ADC Analog watchdog interrupt */
<> 144:ef7eb2e8f9f7 1768 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
<> 144:ef7eb2e8f9f7 1769 }
<> 144:ef7eb2e8f9f7 1770
<> 144:ef7eb2e8f9f7 1771 /* Configuration of analog watchdog: */
<> 144:ef7eb2e8f9f7 1772 /* - Set the analog watchdog mode */
<> 144:ef7eb2e8f9f7 1773 /* - Set the Analog watchdog channel (is not used if watchdog */
<> 144:ef7eb2e8f9f7 1774 /* mode "all channels": ADC_CFGR1_AWD1SGL=0) */
<> 144:ef7eb2e8f9f7 1775 hadc->Instance->CFGR1 &= ~( ADC_CFGR1_AWDSGL |
<> 144:ef7eb2e8f9f7 1776 ADC_CFGR1_AWDEN |
<> 144:ef7eb2e8f9f7 1777 ADC_CFGR1_AWDCH);
<> 144:ef7eb2e8f9f7 1778
<> 144:ef7eb2e8f9f7 1779 hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode |
<> 144:ef7eb2e8f9f7 1780 (AnalogWDGConfig->Channel & ADC_CHANNEL_AWD_MASK));
<> 144:ef7eb2e8f9f7 1781
<> 144:ef7eb2e8f9f7 1782
<> 144:ef7eb2e8f9f7 1783 /* Shift the offset in function of the selected ADC resolution: Thresholds */
<> 144:ef7eb2e8f9f7 1784 /* have to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
<> 144:ef7eb2e8f9f7 1785 tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
<> 144:ef7eb2e8f9f7 1786 tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
<> 144:ef7eb2e8f9f7 1787
<> 144:ef7eb2e8f9f7 1788 /* Clear High & Low high thresholds */
<> 144:ef7eb2e8f9f7 1789 hadc->Instance->TR &= (uint32_t) ~ (ADC_TR_HT | ADC_TR_LT);
<> 144:ef7eb2e8f9f7 1790
<> 144:ef7eb2e8f9f7 1791 /* Set the high threshold */
<> 144:ef7eb2e8f9f7 1792 hadc->Instance->TR = ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted);
<> 144:ef7eb2e8f9f7 1793 /* Set the low threshold */
<> 144:ef7eb2e8f9f7 1794 hadc->Instance->TR |= tmpAWDLowThresholdShifted;
<> 144:ef7eb2e8f9f7 1795 }
<> 144:ef7eb2e8f9f7 1796 else
<> 144:ef7eb2e8f9f7 1797 {
<> 144:ef7eb2e8f9f7 1798 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1799 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 1800
<> 144:ef7eb2e8f9f7 1801 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1802 }
<> 144:ef7eb2e8f9f7 1803
<> 144:ef7eb2e8f9f7 1804
<> 144:ef7eb2e8f9f7 1805 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1806 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1807
<> 144:ef7eb2e8f9f7 1808 /* Return function status */
<> 144:ef7eb2e8f9f7 1809 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1810 }
<> 144:ef7eb2e8f9f7 1811
<> 144:ef7eb2e8f9f7 1812 /**
<> 144:ef7eb2e8f9f7 1813 * @}
<> 144:ef7eb2e8f9f7 1814 */
<> 144:ef7eb2e8f9f7 1815
<> 144:ef7eb2e8f9f7 1816 /** @addtogroup ADC_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 1817 * @brief ADC Peripheral State functions
<> 144:ef7eb2e8f9f7 1818 *
<> 144:ef7eb2e8f9f7 1819 @verbatim
<> 144:ef7eb2e8f9f7 1820 ===============================================================================
<> 144:ef7eb2e8f9f7 1821 ##### ADC Peripheral State functions #####
<> 144:ef7eb2e8f9f7 1822 ===============================================================================
<> 144:ef7eb2e8f9f7 1823 [..]
<> 144:ef7eb2e8f9f7 1824 This subsection provides functions allowing to
<> 144:ef7eb2e8f9f7 1825 (+) Check the ADC state.
<> 144:ef7eb2e8f9f7 1826 (+) handle ADC interrupt request.
<> 144:ef7eb2e8f9f7 1827
<> 144:ef7eb2e8f9f7 1828 @endverbatim
<> 144:ef7eb2e8f9f7 1829 * @{
<> 144:ef7eb2e8f9f7 1830 */
<> 144:ef7eb2e8f9f7 1831
<> 144:ef7eb2e8f9f7 1832 /**
<> 144:ef7eb2e8f9f7 1833 * @brief return the ADC state
<> 144:ef7eb2e8f9f7 1834 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1835 * @retval HAL state
<> 144:ef7eb2e8f9f7 1836 */
<> 144:ef7eb2e8f9f7 1837 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1838 {
<> 144:ef7eb2e8f9f7 1839 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1840 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1841
<> 144:ef7eb2e8f9f7 1842 /* Return ADC state */
<> 144:ef7eb2e8f9f7 1843 return hadc->State;
<> 144:ef7eb2e8f9f7 1844 }
<> 144:ef7eb2e8f9f7 1845
<> 144:ef7eb2e8f9f7 1846 /**
<> 144:ef7eb2e8f9f7 1847 * @brief Return the ADC error code
<> 144:ef7eb2e8f9f7 1848 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1849 * @retval ADC Error Code
<> 144:ef7eb2e8f9f7 1850 */
<> 144:ef7eb2e8f9f7 1851 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
<> 144:ef7eb2e8f9f7 1852 {
<> 144:ef7eb2e8f9f7 1853 return hadc->ErrorCode;
<> 144:ef7eb2e8f9f7 1854 }
<> 144:ef7eb2e8f9f7 1855
<> 144:ef7eb2e8f9f7 1856
<> 144:ef7eb2e8f9f7 1857 /**
<> 144:ef7eb2e8f9f7 1858 * @}
<> 144:ef7eb2e8f9f7 1859 */
<> 144:ef7eb2e8f9f7 1860
<> 144:ef7eb2e8f9f7 1861 /**
<> 144:ef7eb2e8f9f7 1862 * @}
<> 144:ef7eb2e8f9f7 1863 */
<> 144:ef7eb2e8f9f7 1864
<> 144:ef7eb2e8f9f7 1865
<> 144:ef7eb2e8f9f7 1866 /** @addtogroup ADC_Private
<> 144:ef7eb2e8f9f7 1867 * @{
<> 144:ef7eb2e8f9f7 1868 */
<> 144:ef7eb2e8f9f7 1869
<> 144:ef7eb2e8f9f7 1870 /**
<> 144:ef7eb2e8f9f7 1871 * @brief Enable the selected ADC.
<> 144:ef7eb2e8f9f7 1872 * @note Prerequisite condition to use this function: ADC must be disabled
<> 144:ef7eb2e8f9f7 1873 * and voltage regulator must be enabled (done into HAL_ADC_Init()).
<> 144:ef7eb2e8f9f7 1874 * @note If low power mode AutoPowerOff is enabled, power-on/off phases are
<> 144:ef7eb2e8f9f7 1875 * performed automatically by hardware.
<> 144:ef7eb2e8f9f7 1876 * In this mode, this function is useless and must not be called because
<> 144:ef7eb2e8f9f7 1877 * flag ADC_FLAG_RDY is not usable.
<> 144:ef7eb2e8f9f7 1878 * Therefore, this function must be called under condition of
<> 144:ef7eb2e8f9f7 1879 * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)".
<> 144:ef7eb2e8f9f7 1880 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1881 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1882 */
<> 144:ef7eb2e8f9f7 1883 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1884 {
<> 144:ef7eb2e8f9f7 1885 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1886
<> 144:ef7eb2e8f9f7 1887 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
<> 144:ef7eb2e8f9f7 1888 /* enabling phase not yet completed: flag ADC ready not yet set). */
<> 144:ef7eb2e8f9f7 1889 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
<> 144:ef7eb2e8f9f7 1890 /* causes: ADC clock not running, ...). */
<> 144:ef7eb2e8f9f7 1891 if (ADC_IS_ENABLE(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1892 {
<> 144:ef7eb2e8f9f7 1893 /* Check if conditions to enable the ADC are fulfilled */
<> 144:ef7eb2e8f9f7 1894 if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1895 {
<> 144:ef7eb2e8f9f7 1896 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1897 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 1898
<> 144:ef7eb2e8f9f7 1899 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 1900 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 1901
<> 144:ef7eb2e8f9f7 1902 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1903 }
<> 144:ef7eb2e8f9f7 1904
<> 144:ef7eb2e8f9f7 1905 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 1906 __HAL_ADC_ENABLE(hadc);
<> 144:ef7eb2e8f9f7 1907
<> 144:ef7eb2e8f9f7 1908 /* Delay for ADC stabilization time. */
<> 144:ef7eb2e8f9f7 1909 ADC_DelayMicroSecond(ADC_STAB_DELAY_US);
<> 144:ef7eb2e8f9f7 1910
<> 144:ef7eb2e8f9f7 1911 /* Get tick count */
<> 144:ef7eb2e8f9f7 1912 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1913
<> 144:ef7eb2e8f9f7 1914 /* Wait for ADC effectively enabled */
<> 144:ef7eb2e8f9f7 1915 while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
<> 144:ef7eb2e8f9f7 1916 {
<> 144:ef7eb2e8f9f7 1917 if((HAL_GetTick() - tickstart ) > ADC_ENABLE_TIMEOUT)
<> 144:ef7eb2e8f9f7 1918 {
<> 144:ef7eb2e8f9f7 1919 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1920 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 1921
<> 144:ef7eb2e8f9f7 1922 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 1923 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 1924
<> 144:ef7eb2e8f9f7 1925 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1926 }
<> 144:ef7eb2e8f9f7 1927 }
<> 144:ef7eb2e8f9f7 1928
<> 144:ef7eb2e8f9f7 1929 }
<> 144:ef7eb2e8f9f7 1930
<> 144:ef7eb2e8f9f7 1931 /* Return HAL status */
<> 144:ef7eb2e8f9f7 1932 return HAL_OK;
<> 144:ef7eb2e8f9f7 1933 }
<> 144:ef7eb2e8f9f7 1934
<> 144:ef7eb2e8f9f7 1935 /**
<> 144:ef7eb2e8f9f7 1936 * @brief Disable the selected ADC.
<> 144:ef7eb2e8f9f7 1937 * @note Prerequisite condition to use this function: ADC conversions must be
<> 144:ef7eb2e8f9f7 1938 * stopped.
<> 144:ef7eb2e8f9f7 1939 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1940 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1941 */
<> 144:ef7eb2e8f9f7 1942 static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1943 {
<> 144:ef7eb2e8f9f7 1944 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1945
<> 144:ef7eb2e8f9f7 1946 /* Verification if ADC is not already disabled: */
<> 144:ef7eb2e8f9f7 1947 /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
<> 144:ef7eb2e8f9f7 1948 /* disabled. */
<> 144:ef7eb2e8f9f7 1949 if (ADC_IS_ENABLE(hadc) != RESET )
<> 144:ef7eb2e8f9f7 1950 {
<> 144:ef7eb2e8f9f7 1951 /* Check if conditions to disable the ADC are fulfilled */
<> 144:ef7eb2e8f9f7 1952 if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
<> 144:ef7eb2e8f9f7 1953 {
<> 144:ef7eb2e8f9f7 1954 /* Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 1955 __HAL_ADC_DISABLE(hadc);
<> 144:ef7eb2e8f9f7 1956 }
<> 144:ef7eb2e8f9f7 1957 else
<> 144:ef7eb2e8f9f7 1958 {
<> 144:ef7eb2e8f9f7 1959 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1960 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 1961
<> 144:ef7eb2e8f9f7 1962 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 1963 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 1964
<> 144:ef7eb2e8f9f7 1965 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1966 }
<> 144:ef7eb2e8f9f7 1967
<> 144:ef7eb2e8f9f7 1968 /* Wait for ADC effectively disabled */
<> 144:ef7eb2e8f9f7 1969 /* Get tick count */
<> 144:ef7eb2e8f9f7 1970 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1971
<> 144:ef7eb2e8f9f7 1972 while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
<> 144:ef7eb2e8f9f7 1973 {
<> 144:ef7eb2e8f9f7 1974 if((HAL_GetTick() - tickstart ) > ADC_DISABLE_TIMEOUT)
<> 144:ef7eb2e8f9f7 1975 {
<> 144:ef7eb2e8f9f7 1976 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1977 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 1978
<> 144:ef7eb2e8f9f7 1979 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 1980 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 1981
<> 144:ef7eb2e8f9f7 1982 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1983 }
<> 144:ef7eb2e8f9f7 1984 }
<> 144:ef7eb2e8f9f7 1985 }
<> 144:ef7eb2e8f9f7 1986
<> 144:ef7eb2e8f9f7 1987 /* Return HAL status */
<> 144:ef7eb2e8f9f7 1988 return HAL_OK;
<> 144:ef7eb2e8f9f7 1989 }
<> 144:ef7eb2e8f9f7 1990
<> 144:ef7eb2e8f9f7 1991 /**
<> 144:ef7eb2e8f9f7 1992 * @brief Stop ADC conversion.
<> 144:ef7eb2e8f9f7 1993 * @note Prerequisite condition to use this function: ADC conversions must be
<> 144:ef7eb2e8f9f7 1994 * stopped to disable the ADC.
<> 144:ef7eb2e8f9f7 1995 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1996 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1997 */
<> 144:ef7eb2e8f9f7 1998 static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1999 {
<> 144:ef7eb2e8f9f7 2000 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 2001
<> 144:ef7eb2e8f9f7 2002 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2003 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 2004
<> 144:ef7eb2e8f9f7 2005 /* Verification if ADC is not already stopped on regular group to bypass */
<> 144:ef7eb2e8f9f7 2006 /* this function if not needed. */
<> 144:ef7eb2e8f9f7 2007 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
<> 144:ef7eb2e8f9f7 2008 {
<> 144:ef7eb2e8f9f7 2009
<> 144:ef7eb2e8f9f7 2010 /* Stop potential conversion on going on regular group */
<> 144:ef7eb2e8f9f7 2011 /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
<> 144:ef7eb2e8f9f7 2012 if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
<> 144:ef7eb2e8f9f7 2013 HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
<> 144:ef7eb2e8f9f7 2014 {
<> 144:ef7eb2e8f9f7 2015 /* Stop conversions on regular group */
<> 144:ef7eb2e8f9f7 2016 hadc->Instance->CR |= ADC_CR_ADSTP;
<> 144:ef7eb2e8f9f7 2017 }
<> 144:ef7eb2e8f9f7 2018
<> 144:ef7eb2e8f9f7 2019 /* Wait for conversion effectively stopped */
<> 144:ef7eb2e8f9f7 2020 /* Get tick count */
<> 144:ef7eb2e8f9f7 2021 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 2022
<> 144:ef7eb2e8f9f7 2023 while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET)
<> 144:ef7eb2e8f9f7 2024 {
<> 144:ef7eb2e8f9f7 2025 if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
<> 144:ef7eb2e8f9f7 2026 {
<> 144:ef7eb2e8f9f7 2027 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 2028 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 2029
<> 144:ef7eb2e8f9f7 2030 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 2031 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 2032
<> 144:ef7eb2e8f9f7 2033 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2034 }
<> 144:ef7eb2e8f9f7 2035 }
<> 144:ef7eb2e8f9f7 2036
<> 144:ef7eb2e8f9f7 2037 }
<> 144:ef7eb2e8f9f7 2038
<> 144:ef7eb2e8f9f7 2039 /* Return HAL status */
<> 144:ef7eb2e8f9f7 2040 return HAL_OK;
<> 144:ef7eb2e8f9f7 2041 }
<> 144:ef7eb2e8f9f7 2042
<> 144:ef7eb2e8f9f7 2043 /**
<> 144:ef7eb2e8f9f7 2044 * @brief DMA transfer complete callback.
<> 144:ef7eb2e8f9f7 2045 * @param hdma: pointer to DMA handle.
<> 144:ef7eb2e8f9f7 2046 * @retval None
<> 144:ef7eb2e8f9f7 2047 */
<> 144:ef7eb2e8f9f7 2048 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2049 {
<> 144:ef7eb2e8f9f7 2050 /* Retrieve ADC handle corresponding to current DMA handle */
<> 144:ef7eb2e8f9f7 2051 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2052
<> 144:ef7eb2e8f9f7 2053 /* Update state machine on conversion status if not in error state */
<> 144:ef7eb2e8f9f7 2054 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
<> 144:ef7eb2e8f9f7 2055 {
<> 144:ef7eb2e8f9f7 2056 /* Set ADC state */
<> 144:ef7eb2e8f9f7 2057 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<> 144:ef7eb2e8f9f7 2058
<> 144:ef7eb2e8f9f7 2059 /* Determine whether any further conversion upcoming on group regular */
<> 144:ef7eb2e8f9f7 2060 /* by external trigger, continuous mode or scan sequence on going. */
<> 144:ef7eb2e8f9f7 2061 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 2062 (hadc->Init.ContinuousConvMode == DISABLE) )
<> 144:ef7eb2e8f9f7 2063 {
<> 144:ef7eb2e8f9f7 2064 /* If End of Sequence is reached, disable interrupts */
<> 144:ef7eb2e8f9f7 2065 if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
<> 144:ef7eb2e8f9f7 2066 {
<> 144:ef7eb2e8f9f7 2067 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
<> 144:ef7eb2e8f9f7 2068 /* ADSTART==0 (no conversion on going) */
<> 144:ef7eb2e8f9f7 2069 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 2070 {
<> 144:ef7eb2e8f9f7 2071 /* Disable ADC end of single conversion interrupt on group regular */
<> 144:ef7eb2e8f9f7 2072 /* Note: Overrun interrupt was enabled with EOC interrupt in */
<> 144:ef7eb2e8f9f7 2073 /* HAL_Start_IT(), but is not disabled here because can be used */
<> 144:ef7eb2e8f9f7 2074 /* by overrun IRQ process below. */
<> 144:ef7eb2e8f9f7 2075 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
<> 144:ef7eb2e8f9f7 2076
<> 144:ef7eb2e8f9f7 2077 /* Set ADC state */
<> 144:ef7eb2e8f9f7 2078 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 2079 HAL_ADC_STATE_REG_BUSY,
<> 144:ef7eb2e8f9f7 2080 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 2081 }
<> 144:ef7eb2e8f9f7 2082 else
<> 144:ef7eb2e8f9f7 2083 {
<> 144:ef7eb2e8f9f7 2084 /* Change ADC state to error state */
<> 144:ef7eb2e8f9f7 2085 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 2086
<> 144:ef7eb2e8f9f7 2087 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 2088 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 2089 }
<> 144:ef7eb2e8f9f7 2090 }
<> 144:ef7eb2e8f9f7 2091 }
<> 144:ef7eb2e8f9f7 2092
<> 144:ef7eb2e8f9f7 2093 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 2094 HAL_ADC_ConvCpltCallback(hadc);
<> 144:ef7eb2e8f9f7 2095 }
<> 144:ef7eb2e8f9f7 2096 else
<> 144:ef7eb2e8f9f7 2097 {
<> 144:ef7eb2e8f9f7 2098 /* Call DMA error callback */
<> 144:ef7eb2e8f9f7 2099 hadc->DMA_Handle->XferErrorCallback(hdma);
<> 144:ef7eb2e8f9f7 2100 }
<> 144:ef7eb2e8f9f7 2101
<> 144:ef7eb2e8f9f7 2102 }
<> 144:ef7eb2e8f9f7 2103
<> 144:ef7eb2e8f9f7 2104 /**
<> 144:ef7eb2e8f9f7 2105 * @brief DMA half transfer complete callback.
<> 144:ef7eb2e8f9f7 2106 * @param hdma: pointer to DMA handle.
<> 144:ef7eb2e8f9f7 2107 * @retval None
<> 144:ef7eb2e8f9f7 2108 */
<> 144:ef7eb2e8f9f7 2109 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2110 {
<> 144:ef7eb2e8f9f7 2111 /* Retrieve ADC handle corresponding to current DMA handle */
<> 144:ef7eb2e8f9f7 2112 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2113
<> 144:ef7eb2e8f9f7 2114 /* Half conversion callback */
<> 144:ef7eb2e8f9f7 2115 HAL_ADC_ConvHalfCpltCallback(hadc);
<> 144:ef7eb2e8f9f7 2116 }
<> 144:ef7eb2e8f9f7 2117
<> 144:ef7eb2e8f9f7 2118 /**
<> 144:ef7eb2e8f9f7 2119 * @brief DMA error callback
<> 144:ef7eb2e8f9f7 2120 * @param hdma: pointer to DMA handle.
<> 144:ef7eb2e8f9f7 2121 * @retval None
<> 144:ef7eb2e8f9f7 2122 */
<> 144:ef7eb2e8f9f7 2123 static void ADC_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2124 {
<> 144:ef7eb2e8f9f7 2125 /* Retrieve ADC handle corresponding to current DMA handle */
<> 144:ef7eb2e8f9f7 2126 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2127
<> 144:ef7eb2e8f9f7 2128 /* Set ADC state */
<> 144:ef7eb2e8f9f7 2129 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<> 144:ef7eb2e8f9f7 2130
<> 144:ef7eb2e8f9f7 2131 /* Set ADC error code to DMA error */
<> 144:ef7eb2e8f9f7 2132 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
<> 144:ef7eb2e8f9f7 2133
<> 144:ef7eb2e8f9f7 2134 /* Error callback */
<> 144:ef7eb2e8f9f7 2135 HAL_ADC_ErrorCallback(hadc);
<> 144:ef7eb2e8f9f7 2136 }
<> 144:ef7eb2e8f9f7 2137
<> 144:ef7eb2e8f9f7 2138 /**
<> 144:ef7eb2e8f9f7 2139 * @brief Delay micro seconds
<> 144:ef7eb2e8f9f7 2140 * @param microSecond : delay
<> 144:ef7eb2e8f9f7 2141 * @retval None
<> 144:ef7eb2e8f9f7 2142 */
<> 144:ef7eb2e8f9f7 2143 static void ADC_DelayMicroSecond(uint32_t microSecond)
<> 144:ef7eb2e8f9f7 2144 {
<> 144:ef7eb2e8f9f7 2145 /* Compute number of CPU cycles to wait for */
<> 144:ef7eb2e8f9f7 2146 __IO uint32_t waitLoopIndex = (microSecond * (SystemCoreClock / 1000000));
<> 144:ef7eb2e8f9f7 2147
<> 144:ef7eb2e8f9f7 2148 while(waitLoopIndex != 0)
<> 144:ef7eb2e8f9f7 2149 {
<> 144:ef7eb2e8f9f7 2150 waitLoopIndex--;
<> 144:ef7eb2e8f9f7 2151 }
<> 144:ef7eb2e8f9f7 2152 }
<> 144:ef7eb2e8f9f7 2153
<> 144:ef7eb2e8f9f7 2154 /**
<> 144:ef7eb2e8f9f7 2155 * @}
<> 144:ef7eb2e8f9f7 2156 */
<> 144:ef7eb2e8f9f7 2157
<> 144:ef7eb2e8f9f7 2158 /**
<> 144:ef7eb2e8f9f7 2159 * @}
<> 144:ef7eb2e8f9f7 2160 */
<> 144:ef7eb2e8f9f7 2161
<> 144:ef7eb2e8f9f7 2162 #endif /* HAL_ADC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2163 /**
<> 144:ef7eb2e8f9f7 2164 * @}
<> 144:ef7eb2e8f9f7 2165 */
<> 144:ef7eb2e8f9f7 2166
<> 144:ef7eb2e8f9f7 2167 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/