Revision 147:30b64687e01f, committed 2016-09-16

Comitter:

<>

Date:

Fri Sep 16 16:24:25 2016 +0100

Parent:

146:11f9a9a04805

Child:

148:21d94c44109e

Commit message:

This updates the lib to the mbed lib v126

Changed in this revision

--- a/api/CAN.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/api/CAN.h	Fri Sep 16 16:24:25 2016 +0100
@@ -203,7 +203,9 @@
         EpIrq,
         AlIrq,
         BeIrq,
-        IdIrq
+        IdIrq,
+
+        IrqCnt
     };
 
     /** Attach a function to call whenever a CAN frame received interrupt is
@@ -246,7 +248,7 @@
     virtual void lock();
     virtual void unlock();
     can_t               _can;
-    Callback<void()>    _irq[9];
+    Callback<void()>    _irq[IrqCnt];
     PlatformMutex       _mutex;
 };
 

--- a/api/SerialBase.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/api/SerialBase.h	Fri Sep 16 16:24:25 2016 +0100
@@ -55,7 +55,9 @@
 
     enum IrqType {
         RxIrq = 0,
-        TxIrq
+        TxIrq,
+
+        IrqCnt
     };
 
     enum Flow {
@@ -231,7 +233,7 @@
 #endif
 
     serial_t         _serial;
-    Callback<void()> _irq[2];
+    Callback<void()> _irq[IrqCnt];
     int              _baud;
 
 };

--- a/api/mbed.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/api/mbed.h	Fri Sep 16 16:24:25 2016 +0100
@@ -16,7 +16,7 @@
 #ifndef MBED_H
 #define MBED_H
 
-#define MBED_LIBRARY_VERSION 125
+#define MBED_LIBRARY_VERSION 126
 
 #if MBED_CONF_RTOS_PRESENT
 #include "rtos/rtos.h"

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api/mbed_mem_trace.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,138 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MBED_MEM_TRACE_H__
+#define __MBED_MEM_TRACE_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+/* Operation types for tracer */
+enum {
+    MBED_MEM_TRACE_MALLOC,
+    MBED_MEM_TRACE_REALLOC,
+    MBED_MEM_TRACE_CALLOC,
+    MBED_MEM_TRACE_FREE
+};
+
+/* Prefix for the output of the default tracer */
+#define MBED_MEM_DEFAULT_TRACER_PREFIX  "#"
+
+/**
+ * Type of the callback used by the memory tracer. This callback is called when a memory
+ * allocation operation (malloc, realloc, calloc, free) is called and tracing is enabled
+ * for that memory allocation function.
+ *
+ * @param op the ID of the operation (MBED_MEM_TRACE_MALLOC, MBED_MEM_TRACE_REALLOC,
+ *           MBED_MEM_TRACE_CALLOC or MBED_MEM_TRACE_FREE).
+ * @param res the result that the memory operation returned (NULL for 'free').
+ * @param caller the caller of the memory operation. Note that the value of 'caller' might be
+ *               unreliable.
+ *
+ * The rest of the parameters passed 'mbed_mem_trace_cb_t' are the same as the memory operations
+ * that triggered its call (see 'man malloc' for details):
+ *
+ * - for malloc: cb(MBED_MEM_TRACE_MALLOC, res, caller, size).
+ * - for realloc: cb(MBED_MEM_TRACE_REALLOC, res, caller, ptr, size).
+ * - for calloc: cb(MBED_MEM_TRACE_CALLOC, res, caller, nmemb, size).
+ * - for free: cb(MBED_MEM_TRACE_FREE, NULL, caller, ptr).
+ */
+typedef void (*mbed_mem_trace_cb_t)(uint8_t op, void *res, void* caller, ...);
+
+/**
+ * Set the callback used by the memory tracer (use NULL for disable tracing).
+ *
+ * @param cb the callback to call on each memory operation.
+ */
+void mbed_mem_trace_set_callback(mbed_mem_trace_cb_t cb);
+
+/**
+ * Trace a call to 'malloc'.
+ * @param res the result of running 'malloc'.
+ * @param size the 'size' argument given to 'malloc'.
+ * @param caller the caller of the memory operation.
+ * @return 'res' (the first argument).
+ */
+void *mbed_mem_trace_malloc(void *res, size_t size, void *caller);
+
+/**
+ * Trace a call to 'realloc'.
+ * @param res the result of running 'realloc'.
+ * @param ptr the 'ptr' argument given to 'realloc'.
+ * @param size the 'size' argument given to 'realloc'.
+ *
+ * @return 'res' (the first argument).
+ */
+void *mbed_mem_trace_realloc(void *res, void *ptr, size_t size, void *caller);
+
+/**
+ * Trace a call to 'calloc'.
+ * @param res the result of running 'calloc'.
+ * @param nmemb the 'nmemb' argument given to 'calloc'.
+ * @param size the 'size' argument given to 'calloc'.
+ * @param caller the caller of the memory operation.
+ * @Return 'res' (the first argument).
+ */
+void *mbed_mem_trace_calloc(void *res, size_t num, size_t size, void *caller);
+
+/**
+ * Trace a call to 'free'.
+ * @param ptr the 'ptr' argument given to 'free'.
+ * @param caller the caller of the memory operation.
+ */
+void mbed_mem_trace_free(void *ptr, void *caller);
+
+/**
+ * Default memory trace callback. DO NOT CALL DIRECTLY. It is meant to be used
+ * as the second argument of 'mbed_mem_trace_setup'.
+ *
+ * The default callback outputs trace data using 'printf', in a format that's
+ * easily parsable by an external tool. For each memory operation, the callback
+ * outputs a line that begins with '#<op>:<0xresult>;<0xcaller>-':
+ *
+ * - 'op' identifies the memory operation ('m' for 'malloc', 'r' for 'realloc',
+ *   'c' for 'calloc' and 'f' for 'free').
+ * - 'result' (base 16) is the result of the memor operation. This is always NULL
+ *   for 'free', since 'free' doesn't return anything.
+ * -'caller' (base 16) is the caller of the memory operation. Note that the value
+ *   of 'caller' might be unreliable.
+ *
+ * The rest of the output depends on the operation being traced:
+ *
+ * - for 'malloc': 'size', where 'size' is the original argument to 'malloc'.
+ * - for 'realloc': '0xptr;size', where 'ptr' (base 16) and 'size' are the original arguments to 'realloc'.
+ * - for 'calloc': 'nmemb;size', where 'nmemb' and 'size' are the original arguments to 'calloc'.
+ * - for 'free': '0xptr', where 'ptr' (base 16) is the original argument to 'free'.
+ *
+ * Examples:
+ *
+ * - '#m:0x20003240;0x600d-50' encodes a 'malloc' that returned 0x20003240, was called
+ *   by the instruction at 0x600D with a the 'size' argument equal to 50.
+ * - '#f:0x0;0x602f-0x20003240' encodes a 'free' that was called by the instruction at
+ *   0x602f with the 'ptr' argument equal to 0x20003240.
+ */
+void mbed_mem_trace_default_callback(uint8_t op, void *res, void *caller, ...);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif// #ifndef __MBED_MEM_TRACE_H__
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api/mbed_stats.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_STATS_H
+#define MBED_STATS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    uint32_t current_size;      /**< Bytes allocated currently. */
+    uint32_t max_size;          /**< Max bytes allocated at a given time. */
+    uint32_t total_size;        /**< Cumulative sum of bytes ever allocated. */
+    uint32_t alloc_cnt;         /**< Current number of allocations. */
+    uint32_t alloc_fail_cnt;    /**< Number of failed allocations. */
+} mbed_stats_heap_t;
+
+/**
+ * Fill the passed in structure with heap stats.
+ */
+void mbed_stats_heap_get(mbed_stats_heap_t *stats);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- a/api/toolchain.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/api/toolchain.h	Fri Sep 16 16:24:25 2016 +0100
@@ -240,6 +240,29 @@
  */
 #define MBED_DEPRECATED_SINCE(D, M) MBED_DEPRECATED(M " [since " D "]")
 
+/** MBED_CALLER_ADDR()
+ * Returns the caller of the current function.
+ *
+ * @note
+ * This macro is only implemented for GCC and ARMCC.
+ *
+ * @code
+ * #include "toolchain.h"
+ *
+ * printf("This function was called from %p", MBED_CALLER_ADDR());
+ * @endcode
+ *
+ * @return Address of the calling function
+ */
+#ifndef MBED_CALLER_ADDR
+#if (defined(__GNUC__) || defined(__clang__)) && !defined(__CC_ARM)
+#define MBED_CALLER_ADDR() __builtin_extract_return_addr(__builtin_return_address(0))
+#elif defined(__CC_ARM)
+#define MBED_CALLER_ADDR() __builtin_return_address(0)
+#else
+#define MBED_CALLER_ADDR() (NULL)
+#endif
+#endif
 
 // FILEHANDLE declaration
 #if defined(TOOLCHAIN_ARM)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/common/mbed_alloc_wrappers.cpp	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,338 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed_mem_trace.h"
+#include "mbed_stats.h"
+#include "toolchain.h"
+#include "SingletonPtr.h"
+#include "PlatformMutex.h"
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+
+/* There are two memory tracers in mbed OS:
+
+- the first can be used to detect the maximum heap usage at runtime. It is
+  activated by defining the MBED_HEAP_STATS_ENABLED macro.
+- the second can be used to trace each memory call by automatically invoking
+  a callback on each memory operation (see hal/api/mbed_mem_trace.h). It is
+  activated by defining the MBED_MEM_TRACING_ENABLED macro.
+
+Both tracers can be activated and deactivated in any combination. If both tracers
+are active, the second one (MBED_MEM_TRACING_ENABLED) will trace the first one's
+(MBED_HEAP_STATS_ENABLED) memory calls.*/
+
+/******************************************************************************/
+/* Implementation of the runtime max heap usage checker                       */
+/******************************************************************************/
+
+/* Size must be a multiple of 8 to keep alignment */
+typedef struct {
+    uint32_t size;
+    uint32_t pad;
+} alloc_info_t;
+
+#ifdef MBED_MEM_TRACING_ENABLED
+static SingletonPtr<PlatformMutex> mem_trace_mutex;
+#endif
+#ifdef MBED_HEAP_STATS_ENABLED
+static SingletonPtr<PlatformMutex> malloc_stats_mutex;
+static mbed_stats_heap_t heap_stats = {0, 0, 0, 0, 0};
+#endif
+
+void mbed_stats_heap_get(mbed_stats_heap_t *stats)
+{
+#ifdef MBED_HEAP_STATS_ENABLED
+    malloc_stats_mutex->lock();
+    memcpy(stats, &heap_stats, sizeof(mbed_stats_heap_t));
+    malloc_stats_mutex->unlock();
+#else
+    memset(stats, 0, sizeof(mbed_stats_heap_t));
+#endif
+}
+
+/******************************************************************************/
+/* GCC memory allocation wrappers                                             */
+/******************************************************************************/
+
+#if defined(TOOLCHAIN_GCC)
+
+#ifdef   FEATURE_UVISOR
+#include "uvisor-lib/uvisor-lib.h"
+#endif/* FEATURE_UVISOR */
+
+extern "C" {
+    void * __real__malloc_r(struct _reent * r, size_t size);
+    void * __real__realloc_r(struct _reent * r, void * ptr, size_t size);
+    void __real__free_r(struct _reent * r, void * ptr);
+    void* __real__calloc_r(struct _reent * r, size_t nmemb, size_t size);
+}
+
+// TODO: memory tracing doesn't work with uVisor enabled.
+#if !defined(FEATURE_UVISOR)
+
+extern "C" void * __wrap__malloc_r(struct _reent * r, size_t size) {
+    void *ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+    malloc_stats_mutex->lock();
+    alloc_info_t *alloc_info = (alloc_info_t*)__real__malloc_r(r, size + sizeof(alloc_info_t));
+    if (alloc_info != NULL) {
+        alloc_info->size = size;
+        ptr = (void*)(alloc_info + 1);
+        heap_stats.current_size += size;
+        heap_stats.total_size += size;
+        heap_stats.alloc_cnt += 1;
+        if (heap_stats.current_size > heap_stats.max_size) {
+            heap_stats.max_size = heap_stats.current_size;
+        }
+    } else {
+        heap_stats.alloc_fail_cnt += 1;
+    }
+    malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    ptr = __real__malloc_r(r, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_malloc(ptr, size, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+    return ptr;
+}
+
+extern "C" void * __wrap__realloc_r(struct _reent * r, void * ptr, size_t size) {
+    void *new_ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+    // Implement realloc_r with malloc and free.
+    // The function realloc_r can't be used here directly since
+    // it can call into __wrap__malloc_r (returns ptr + 4) or
+    // resize memory directly (returns ptr + 0).
+
+    // Note - no lock needed since malloc and free are thread safe
+
+    // Get old size
+    uint32_t old_size = 0;
+    if (ptr != NULL) {
+        alloc_info_t *alloc_info = ((alloc_info_t*)ptr) - 1;
+        old_size = alloc_info->size;
+    }
+
+    // Allocate space
+    if (size != 0) {
+        new_ptr = malloc(size);
+    }
+
+    // If the new buffer has been allocated copy the data to it
+    // and free the old buffer
+    if (new_ptr != NULL) {
+        uint32_t copy_size = (old_size < size) ? old_size : size;
+        memcpy(new_ptr, (void*)ptr, copy_size);
+        free(ptr);
+    }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    new_ptr = __real__realloc_r(r, ptr, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_realloc(new_ptr, ptr, size, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+    return new_ptr;
+}
+
+extern "C" void __wrap__free_r(struct _reent * r, void * ptr) {
+#ifdef MBED_HEAP_STATS_ENABLED
+    malloc_stats_mutex->lock();
+    alloc_info_t *alloc_info = NULL;
+    if (ptr != NULL) {
+        alloc_info = ((alloc_info_t*)ptr) - 1;
+        heap_stats.current_size -= alloc_info->size;
+        heap_stats.alloc_cnt -= 1;
+    }
+    __real__free_r(r, (void*)alloc_info);
+    malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    __real__free_r(r, ptr);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_free(ptr, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+}
+
+#endif // if !defined(FEATURE_UVISOR)
+
+extern "C" void * __wrap__calloc_r(struct _reent * r, size_t nmemb, size_t size) {
+    void *ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+    // Note - no lock needed since malloc is thread safe
+
+    ptr = malloc(nmemb * size);
+    if (ptr != NULL) {
+        memset(ptr, 0, nmemb * size);
+    }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    ptr = __real__calloc_r(r, nmemb, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_calloc(ptr, nmemb, size, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+    return ptr;
+}
+
+
+/******************************************************************************/
+/* ARMCC memory allocation wrappers                                           */
+/******************************************************************************/
+
+#elif defined(TOOLCHAIN_ARM) // #if defined(TOOLCHAIN_GCC)
+
+/* Enable hooking of memory function only if tracing is also enabled */
+#if defined(MBED_MEM_TRACING_ENABLED) || defined(MBED_HEAP_STATS_ENABLED)
+
+extern "C" {
+    void *$Super$$malloc(size_t size);
+    void *$Super$$realloc(void *ptr, size_t size);
+    void *$Super$$calloc(size_t nmemb, size_t size);
+    void $Super$$free(void *ptr);
+}
+
+extern "C" void* $Sub$$malloc(size_t size) {
+    void *ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+    malloc_stats_mutex->lock();
+    alloc_info_t *alloc_info = (alloc_info_t*)$Super$$malloc(size + sizeof(alloc_info_t));
+    if (alloc_info != NULL) {
+        alloc_info->size = size;
+        ptr = (void*)(alloc_info + 1);
+        heap_stats.current_size += size;
+        heap_stats.total_size += size;
+        heap_stats.alloc_cnt += 1;
+        if (heap_stats.current_size > heap_stats.max_size) {
+            heap_stats.max_size = heap_stats.current_size;
+        }
+    } else {
+        heap_stats.alloc_fail_cnt += 1;
+    }
+    malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    ptr = $Super$$malloc(size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_malloc(ptr, size, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+    return ptr;
+}
+
+extern "C" void* $Sub$$realloc(void *ptr, size_t size) {
+    void *new_ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+    // Note - no lock needed since malloc and free are thread safe
+
+    // Get old size
+    uint32_t old_size = 0;
+    if (ptr != NULL) {
+        alloc_info_t *alloc_info = ((alloc_info_t*)ptr) - 1;
+        old_size = alloc_info->size;
+    }
+
+    // Allocate space
+    if (size != 0) {
+        new_ptr = malloc(size);
+    }
+
+    // If the new buffer has been allocated copy the data to it
+    // and free the old buffer
+    if (new_ptr != NULL) {
+        uint32_t copy_size = (old_size < size) ? old_size : size;
+        memcpy(new_ptr, (void*)ptr, copy_size);
+        free(ptr);
+    }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    new_ptr = $Super$$realloc(ptr, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_realloc(new_ptr, ptr, size, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+    return new_ptr;
+}
+
+extern "C" void *$Sub$$calloc(size_t nmemb, size_t size) {
+    void *ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+    // Note - no lock needed since malloc is thread safe
+    ptr = malloc(nmemb * size);
+    if (ptr != NULL) {
+        memset(ptr, 0, nmemb * size);
+    }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    ptr = $Super$$calloc(nmemb, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_calloc(ptr, nmemb, size, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+    return ptr;
+}
+
+extern "C" void $Sub$$free(void *ptr) {
+#ifdef MBED_HEAP_STATS_ENABLED
+    malloc_stats_mutex->lock();
+    alloc_info_t *alloc_info = NULL;
+    if (ptr != NULL) {
+        alloc_info = ((alloc_info_t*)ptr) - 1;
+        heap_stats.current_size -= alloc_info->size;
+        heap_stats.alloc_cnt -= 1;
+    }
+    $Super$$free((void*)alloc_info);
+    malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    $Super$$free(ptr);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_free(ptr, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+}
+
+#endif // #if defined(MBED_MEM_TRACING_ENABLED) || defined(MBED_HEAP_STATS_ENABLED)
+
+/******************************************************************************/
+/* Allocation wrappers for other toolchains are not supported yet             */
+/******************************************************************************/
+
+#else // #if defined(TOOLCHAIN_GCC)
+
+#ifdef MBED_MEM_TRACING_ENABLED
+#warning Memory tracing is not supported with the current toolchain.
+#endif
+
+#ifdef MBED_HEAP_STATS_ENABLED
+#warning Heap statistics are not supported with the current toolchain.
+#endif
+
+#endif // #if defined(TOOLCHAIN_GCC)
+

--- a/common/mbed_critical.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/common/mbed_critical.c	Fri Sep 16 16:24:25 2016 +0100
@@ -86,6 +86,11 @@
 
 #if EXCLUSIVE_ACCESS
 
+/* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */
+#if defined (__CC_ARM) 
+#pragma diag_suppress 3731
+#endif
+
 bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
 {
     uint8_t currentValue = __LDREXB((volatile uint8_t*)ptr);

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/common/mbed_mem_trace.c	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,115 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdlib.h>
+#include <stdarg.h>
+#include <stdio.h>
+#include "mbed_mem_trace.h"
+#include "critical.h"
+
+/******************************************************************************
+ * Internal variables, functions and helpers
+ *****************************************************************************/
+
+/* The callback function that will be called after a traced memory operations finishes. */
+static mbed_mem_trace_cb_t mem_trace_cb;
+/* 'trave_level' guards "trace inside trace" situations (for example, the implementation
+ * of realloc() might call malloc() internally, and since malloc() is also traced, this could
+ * result in two calls to the callback function instead of one. */
+static uint8_t trace_level;
+
+/******************************************************************************
+ * Public interface
+ *****************************************************************************/
+
+void mbed_mem_trace_set_callback(mbed_mem_trace_cb_t cb) {
+    mem_trace_cb = cb;
+}
+
+void *mbed_mem_trace_malloc(void *res, size_t size, void *caller) {
+    if (mem_trace_cb) {
+        if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
+            mem_trace_cb(MBED_MEM_TRACE_MALLOC, res, caller, size);
+        }
+        core_util_atomic_decr_u8(&trace_level, 1);
+    }
+    return res;
+}
+
+void *mbed_mem_trace_realloc(void *res, void *ptr, size_t size, void *caller) {
+    if (mem_trace_cb) {
+        if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
+            mem_trace_cb(MBED_MEM_TRACE_REALLOC, res, caller, ptr, size);
+        }
+        core_util_atomic_decr_u8(&trace_level, 1);
+    }
+    return res;
+}
+
+void *mbed_mem_trace_calloc(void *res, size_t num, size_t size, void *caller) {
+    if (mem_trace_cb) {
+        if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
+            mem_trace_cb(MBED_MEM_TRACE_CALLOC, res, caller, num, size);
+        }
+        core_util_atomic_decr_u8(&trace_level, 1);
+    }
+    return res;
+}
+
+void mbed_mem_trace_free(void *ptr, void *caller) {
+    if (mem_trace_cb) {
+        if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
+            mem_trace_cb(MBED_MEM_TRACE_FREE, NULL, caller, ptr);
+        }
+        core_util_atomic_decr_u8(&trace_level, 1);
+    }
+}
+
+void mbed_mem_trace_default_callback(uint8_t op, void *res, void *caller, ...) {
+    va_list va;
+    size_t temp_s1, temp_s2;
+    void *temp_ptr;
+
+    va_start(va, caller);
+    switch(op) {
+        case MBED_MEM_TRACE_MALLOC:
+            temp_s1 = va_arg(va, size_t);
+            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "m:%p;%p-%u\n", res, caller, temp_s1);
+            break;
+
+        case MBED_MEM_TRACE_REALLOC:
+            temp_ptr = va_arg(va, void*);
+            temp_s1 = va_arg(va, size_t);
+            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "r:%p;%p-%p;%u\n", res, caller, temp_ptr, temp_s1);
+            break;
+
+        case MBED_MEM_TRACE_CALLOC:
+            temp_s1 = va_arg(va, size_t);
+            temp_s2 = va_arg(va, size_t);
+            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "c:%p;%p-%u;%u\n", res, caller, temp_s1, temp_s2);
+            break;
+
+        case MBED_MEM_TRACE_FREE:
+            temp_ptr = va_arg(va, void*);
+            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "f:%p;%p-%p\n", res, caller, temp_ptr);
+            break;
+
+        default:
+            printf("?\n");
+    }
+    va_end(va);
+}
+

--- a/common/retarget.cpp	Thu Sep 08 15:05:30 2016 +0100
+++ b/common/retarget.cpp	Fri Sep 16 16:24:25 2016 +0100
@@ -24,7 +24,9 @@
 #include "SingletonPtr.h"
 #include "PlatformMutex.h"
 #include "mbed_error.h"
+#include "mbed_stats.h"
 #include <stdlib.h>
+#include <string.h>
 #if DEVICE_STDIO_MESSAGES
 #include <stdio.h>
 #endif
@@ -478,26 +480,11 @@
 #endif
 
 #if defined(TOOLCHAIN_GCC)
-#ifdef   FEATURE_UVISOR
+
+#ifdef  FEATURE_UVISOR
 #include "uvisor-lib/uvisor-lib.h"
 #endif/* FEATURE_UVISOR */
 
-#ifndef  FEATURE_UVISOR
-extern "C" {
-void * __wrap__malloc_r(struct _reent * r, size_t size) {
-    extern void * __real__malloc_r(struct _reent * r, size_t size);
-    return __real__malloc_r(r, size);
-}
-void * __wrap__realloc_r(struct _reent * r, void * ptr, size_t size) {
-    extern void * __real__realloc_r(struct _reent * r, void * ptr, size_t size);
-    return __real__realloc_r(r, ptr, size);
-}
-void __wrap__free_r(struct _reent * r, void * ptr) {
-    extern void __real__free_r(struct _reent * r, void * ptr);
-    __real__free_r(r, ptr);
-}
-}
-#endif/* FEATURE_UVISOR */
 
 extern "C" WEAK void software_init_hook_rtos(void)
 {
@@ -684,6 +671,8 @@
 #endif
 }
 
+} // namespace mbed
+
 #if defined (__ICCARM__)
 // Stub out locks when an rtos is not present
 extern "C" WEAK void __iar_system_Mtxinit(__iar_Rmtx *mutex) {}
@@ -723,9 +712,44 @@
 {
     __rtos_env_unlock(_r);
 }
-#endif
+
+#define CXA_GUARD_INIT_DONE             (1 << 0)
+#define CXA_GUARD_INIT_IN_PROGRESS      (1 << 1)
+#define CXA_GUARD_MASK                  (CXA_GUARD_INIT_DONE | CXA_GUARD_INIT_IN_PROGRESS)
 
-} // namespace mbed
+extern "C" int __cxa_guard_acquire(int *guard_object_p)
+{
+    uint8_t *guard_object = (uint8_t *)guard_object_p;
+    if (CXA_GUARD_INIT_DONE == (*guard_object & CXA_GUARD_MASK)) {
+        return 0;
+    }
+    singleton_lock();
+    if (CXA_GUARD_INIT_DONE == (*guard_object & CXA_GUARD_MASK)) {
+        singleton_unlock();
+        return 0;
+    }
+    MBED_ASSERT(0 == (*guard_object & CXA_GUARD_MASK));
+    *guard_object = *guard_object | CXA_GUARD_INIT_IN_PROGRESS;
+    return 1;
+}
+
+extern "C" void __cxa_guard_release(int *guard_object_p)
+{
+    uint8_t *guard_object = (uint8_t *)guard_object_p;
+    MBED_ASSERT(CXA_GUARD_INIT_IN_PROGRESS == (*guard_object & CXA_GUARD_MASK));
+    *guard_object = (*guard_object & ~CXA_GUARD_MASK) | CXA_GUARD_INIT_DONE;
+    singleton_unlock();
+}
+
+extern "C" void __cxa_guard_abort(int *guard_object_p)
+{
+    uint8_t *guard_object = (uint8_t *)guard_object_p;
+    MBED_ASSERT(CXA_GUARD_INIT_IN_PROGRESS == (*guard_object & CXA_GUARD_MASK));
+    *guard_object = *guard_object & ~CXA_GUARD_INIT_IN_PROGRESS;
+    singleton_unlock();
+}
+
+#endif
 
 void *operator new(std::size_t count)
 {

--- a/targets.json	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets.json	Fri Sep 16 16:24:25 2016 +0100
@@ -624,11 +624,12 @@
         "core": "Cortex-M0",
         "default_toolchain": "uARM",
         "extra_labels": ["STM", "STM32F0", "STM32F031K6"],
+        "macros": ["DEVICE_RTC_LSI=1"],
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "progen": {"target": "nucleo-f031k6"},
         "detect_code": ["0791"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "RTC_LSI", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "default_build": "small",
         "release_versions": ["2"]
     },
@@ -637,11 +638,12 @@
         "core": "Cortex-M0",
         "default_toolchain": "uARM",
         "extra_labels": ["STM", "STM32F0", "STM32F042K6"],
+        "macros": ["DEVICE_RTC_LSI=1"],
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "progen": {"target": "nucleo-f042k6"},
         "detect_code": ["0785"],
-        "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "RTC_LSI", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "default_build": "small",
         "release_versions": ["2"]
     },
@@ -690,7 +692,7 @@
         "inherits": ["Target"],
         "progen": {"target": "nucleo-f103rb"},
         "detect_code": ["0700"],
-        "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"]
     },
     "NUCLEO_F207ZG": {
@@ -702,9 +704,9 @@
         "inherits": ["Target"],
         "progen": {"target": "nucleo-f207zg"},
         "detect_code": ["0835"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "features": ["IPV4"],
-        "release_versions": ["2"]
+        "release_versions": ["2", "5"]
     },
     "NUCLEO_F302R8": {
         "supported_form_factors": ["ARDUINO", "MORPHO"],
@@ -724,6 +726,7 @@
         "core": "Cortex-M4F",
         "default_toolchain": "ARM",
         "extra_labels": ["STM", "STM32F3", "STM32F303K8"],
+        "macros": ["DEVICE_RTC_LSI=1"],
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "progen": {"target": "nucleo-f303k8"},
@@ -744,6 +747,19 @@
         "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"]
     },
+    "NUCLEO_F303ZE": {
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M4F",
+        "fpu": "single",
+        "default_toolchain": "uARM",
+        "extra_labels": ["STM", "STM32F3", "STM32F303ZE"],
+        "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
+        "inherits": ["Target"],
+        "progen": {"target": "nucleo-f303ze"},
+        "detect_code": ["0745"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "release_versions": ["2"]
+    },
     "NUCLEO_F334R8": {
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M4F",
@@ -814,8 +830,8 @@
         "extra_labels": ["STM", "STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xx"],
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "progen": {"target": "nucleo-f429zi"},
-        "macros": ["MBEDTLS_ENTROPY_HARDWARE_ALT"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "RTC_LSI", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "macros": ["MBEDTLS_ENTROPY_HARDWARE_ALT", "DEVICE_RTC_LSI=1"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "detect_code": ["0796"],
         "features": ["IPV4"],
         "release_versions": ["2", "5"]
@@ -842,7 +858,7 @@
         "progen": {"target": "nucleo-f446ze"},
         "detect_code": ["0778"],
         "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
-        "release_versions": ["2"]
+        "release_versions": ["2", "5"]
     },
 
     "B96B_F446VE": {
@@ -1022,18 +1038,20 @@
         "core": "Cortex-M4F",
         "default_toolchain": "ARM",
         "extra_labels": ["STM", "STM32F3", "STM32F303", "STM32F303VC"],
+        "macros": ["DEVICE_RTC_LSI=1"],
         "supported_toolchains": ["GCC_ARM"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "RTC_LSI", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"]
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"]
     },
     "DISCO_F334C8": {
         "inherits": ["Target"],
         "core": "Cortex-M4F",
         "default_toolchain": "ARM",
         "extra_labels": ["STM", "STM32F3", "STM32F334C8"],
+        "macros": ["DEVICE_RTC_LSI=1"],
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "progen": {"target": "disco-f334c8"},
         "detect_code": ["0810"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "RTC_LSI", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "default_lib": "small",
 	"release_versions": ["2"]
     },
@@ -1050,10 +1068,10 @@
         "core": "Cortex-M4F",
         "default_toolchain": "ARM",
         "extra_labels": ["STM", "STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xx"],
-        "macros": ["MBEDTLS_ENTROPY_HARDWARE_ALT"],
+        "macros": ["MBEDTLS_ENTROPY_HARDWARE_ALT", "DEVICE_RTC_LSI=1"],
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "progen": {"target": "disco-f429zi"},
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "RTC_LSI", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"]
     },
     "DISCO_F469NI": {
@@ -1093,6 +1111,18 @@
         "features": ["IPV4"],
         "release_versions": ["2", "5"]
     },
+    "DISCO_F769NI": {
+        "inherits": ["Target"],
+        "core": "Cortex-M7FD",
+        "extra_labels": ["STM", "STM32F7", "STM32F769", "STM32F769NI"],
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "default_toolchain": "ARM",
+        "progen": {"target": "disco-f769ni"},
+        "detect_code": ["0817"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "features": ["IPV4"],
+        "release_versions": ["2"]
+    },
     "DISCO_L476VG": {
         "inherits": ["Target"],
         "core": "Cortex-M4F",
@@ -1101,7 +1131,7 @@
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "progen": {"target": "disco-l476vg"},
         "detect_code": ["0820"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"]
     },
     "MTS_MDOT_F405RG": {
@@ -1148,10 +1178,11 @@
         "core": "Cortex-M3",
         "default_toolchain": "uARM",
         "extra_labels": ["STM", "STM32L1", "STM32L152RC"],
+        "macros": ["DEVICE_RTC_LSI=1"],
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "progen": {"target": "stm32l151rc"},
         "detect_code": ["4100"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "RTC_LSI", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "default_build": "small",
         "release_versions": ["2"]
     },
@@ -1180,9 +1211,10 @@
         "default_toolchain": "uARM",
         "program_cycle_s": 1.5,
         "extra_labels": ["STM", "STM32L1", "STM32L151RC"],
+        "macros": ["DEVICE_RTC_LSI=1"],
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
         "progen": {"target": "stm32l151rc"},
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "RTC_LSI", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "default_build": "small"
     },
     "MCU_NRF51": {
@@ -1550,6 +1582,22 @@
         "extra_labels_add": ["NRF51_MICROBIT"],
         "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
     },
+    "MTM_MTCONNECT04S": {
+        "inherits": ["MCU_NRF51_32K"],
+        "progen": {"target": "mtm-mtconnect04s"},
+        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+        "release_versions": ["2"]
+    },
+    "MTM_MTCONNECT04S_BOOT": {
+        "inherits": ["MCU_NRF51_32K_BOOT"],
+        "extra_labels_add": ["MTM_CONNECT04S"],
+        "macros_add": ["TARGET_MTM_CONNECT04S"]
+    },
+    "MTM_MTCONNECT04S_OTA": {
+        "inherits": ["MCU_NRF51_32K_OTA"],
+        "extra_labels_add": ["MTM_CONNECT04S"],
+        "macros_add": ["TARGET_MTM_CONNECT04S"]
+    },
 
     "TY51822R3": {
         "inherits": ["MCU_NRF51_32K_UNIFIED"],
@@ -2001,6 +2049,34 @@
         "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
         "release_versions": ["2", "5"]
     },
+    "DELTA_DFBM_NQ620": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF52"],
+        "progen": {"target": "dfbm-nq620"},
+        "macros_add": [
+            "BOARD_PCA10040",
+            "NRF52_PAN_12",
+            "NRF52_PAN_15",
+            "NRF52_PAN_58",
+            "NRF52_PAN_55",
+            "NRF52_PAN_54",
+            "NRF52_PAN_31",
+            "NRF52_PAN_30",
+            "NRF52_PAN_51",
+            "NRF52_PAN_36",
+            "NRF52_PAN_53",
+            "S132",
+            "CONFIG_GPIO_AS_PINRESET",
+            "BLE_STACK_SUPPORT_REQD",
+            "SWI_DISABLE0",
+            "NRF52_PAN_20",
+            "NRF52_PAN_64",
+            "NRF52_PAN_62",
+            "NRF52_PAN_63"
+        ],
+        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "release_versions": ["2", "5"]
+    },
     "BLUEPILL_F103C8": {
         "core": "Cortex-M3",
         "default_toolchain": "GCC_ARM",

--- a/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/startup_LPC11U68.cpp	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/startup_LPC11U68.cpp	Fri Sep 16 16:24:25 2016 +0100
@@ -137,7 +137,8 @@
 
 
 /* Reset entry point*/
-extern "C" void software_init_hook(void) __attribute__((weak));
+extern "C" void software_init_hook(void);
+extern "C" void pre_main(void) __attribute__((weak));
 
 AFTER_VECTORS void ResetISR(void) {
     unsigned int LoadAddr, ExeAddr, SectionLen;
@@ -169,9 +170,10 @@
 
     
     SystemInit();
-    if (software_init_hook) 
-        software_init_hook(); 
-    else {
+    if (pre_main)  { // give control to the RTOS
+        software_init_hook();  // this will also call __libc_init_array
+    }
+    else {           // for BareMetal (non-RTOS) build
         __libc_init_array();
         main();
     }

--- a/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp	Fri Sep 16 16:24:25 2016 +0100
@@ -113,7 +113,8 @@
 extern unsigned int __data_section_table_end;
 extern unsigned int __bss_section_table_end;
 
-extern "C" void software_init_hook(void) __attribute__((weak));
+extern "C" void software_init_hook(void);
+extern "C" void pre_main(void) __attribute__((weak));
 
 AFTER_VECTORS void ResetISR(void) {
     unsigned int LoadAddr, ExeAddr, SectionLen;
@@ -136,9 +137,10 @@
     }
     
     SystemInit();
-    if (software_init_hook) // give control to the RTOS
+    if (pre_main) { // give control to the RTOS
         software_init_hook(); // this will also call __libc_init_array
-    else {
+    }
+    else {          // for BareMetal (non-RTOS) build
         __libc_init_array();
         main();
     }

--- a/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CR/TARGET_LPC11XX/startup_LPC11xx.cpp	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CR/TARGET_LPC11XX/startup_LPC11xx.cpp	Fri Sep 16 16:24:25 2016 +0100
@@ -113,7 +113,8 @@
 extern unsigned int __data_section_table_end;
 extern unsigned int __bss_section_table_end;
 
-extern "C" void software_init_hook(void) __attribute__((weak));
+extern "C" void software_init_hook(void);
+extern "C" void pre_main(void) __attribute__((weak));
 
 AFTER_VECTORS void ResetISR(void) {
     unsigned int LoadAddr, ExeAddr, SectionLen;
@@ -136,9 +137,10 @@
     }
     
     SystemInit();
-    if (software_init_hook) // give control to the RTOS
+    if (pre_main) { // give control to the RTOS
         software_init_hook(); // this will also call __libc_init_array
-    else {
+    }
+    else {          // for BareMetal (non-RTOS) build
         __libc_init_array();
         main();
     }
@@ -147,7 +149,7 @@
 
 AFTER_VECTORS void NMI_Handler      (void) {while(1){}}
 AFTER_VECTORS void HardFault_Handler(void) {while(1){}}
-AFTER_VECTORS void SVC_Handler   (void) {while(1){}}
+AFTER_VECTORS void SVC_Handler      (void) {while(1){}}
 AFTER_VECTORS void PendSV_Handler   (void) {while(1){}}
 AFTER_VECTORS void SysTick_Handler  (void) {while(1){}}
 AFTER_VECTORS void IntDefaultHandler(void) {while(1){}}

--- a/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_CR/startup_LPC15xx.cpp	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_CR/startup_LPC15xx.cpp	Fri Sep 16 16:24:25 2016 +0100
@@ -166,7 +166,8 @@
 
 
 /* Reset entry point*/
-extern "C" void software_init_hook(void) __attribute__((weak));
+extern "C" void software_init_hook(void);
+extern "C" void pre_main(void) __attribute__((weak));
 
 AFTER_VECTORS void ResetISR(void) {
     unsigned int LoadAddr, ExeAddr, SectionLen;
@@ -187,9 +188,10 @@
     }
     
     SystemInit();
-    if (software_init_hook) 
-        software_init_hook(); 
-    else {
+    if (pre_main) { // give control to the RTOS
+        software_init_hook();  // this will also call __libc_init_array
+    }
+    else {          // for BareMetal (non-RTOS) build
         __libc_init_array();
         main();
     }

--- a/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CR/startup_LPC17xx.cpp	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CR/startup_LPC17xx.cpp	Fri Sep 16 16:24:25 2016 +0100
@@ -130,7 +130,8 @@
     for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
 }
 
-extern "C" void software_init_hook(void) __attribute__((weak));
+extern "C" void software_init_hook(void);
+extern "C" void pre_main(void) __attribute__((weak));
 
 AFTER_VECTORS void ResetISR(void) {
     unsigned int LoadAddr, ExeAddr, SectionLen;
@@ -151,9 +152,10 @@
     }
     
     SystemInit();
-    if (software_init_hook) // give control to the RTOS
+    if (pre_main) { // give control to the RTOS
         software_init_hook(); // this will also call __libc_init_array
-    else {
+    }
+    else {          // for BareMetal (non-RTOS) build
         __libc_init_array();
         main();
     }

--- a/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_CR/startup_lpc407x_8x.cpp	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_CR/startup_lpc407x_8x.cpp	Fri Sep 16 16:24:25 2016 +0100
@@ -260,7 +260,8 @@
 // library.
 //*****************************************************************************
 
-extern "C" void software_init_hook(void) __attribute__((weak));
+extern "C" void software_init_hook(void);
+extern "C" void pre_main(void) __attribute__((weak));
 
 __attribute__ ((section(".after_vectors")))
 void
@@ -319,26 +320,15 @@
 		*pSCB_VTOR = (unsigned int)g_pfnVectors;
 	}
 
-//#ifdef __USE_CMSIS
-	SystemInit();
-//#endif
-  if (software_init_hook) // give control to the RTOS
-    software_init_hook(); // this will also call __libc_init_array
-  else {
-#if defined (__cplusplus)
-    //
-    // Call C++ library initialisation
-    //
-    __libc_init_array();
+    SystemInit();
+    if (pre_main) { // give control to the RTOS
+        software_init_hook(); // this will also call __libc_init_array
+    }
+    else {          // for BareMetal (non-RTOS) build
+        __libc_init_array();
+        main();
 #endif
-
-#if defined (__REDLIB__)
-    // Call the Redlib library, which in turn calls main()
-    __main() ;
-#else
-    main();
-#endif
-  }
+    }
 	//
 	// main() shouldn't return, but if it does, we'll just enter an infinite loop 
 	//

--- a/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/NCS36510.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/NCS36510.h	Fri Sep 16 16:24:25 2016 +0100
@@ -1,6 +1,6 @@
 /**************************************************************************/
 /**
- * @file     ARMCM3.h
+ * @file     NCS36510.h
  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
  *           for CM3 Device Series
  * @version  V1.05

--- a/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/cmsis_nvic.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/cmsis_nvic.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 0.1 $
 * $Date: 2015-11-06 $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+* Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+* All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+* under limited terms and conditions.  The terms and conditions pertaining to the software
+* and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+* (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+* if applicable the software license agreement.  Do not use this software and/or
+* documentation unless you have carefully read and you agree to the limited terms and
+* conditions.  By using this software and/or documentation, you agree to the limited
+* terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
@@ -18,10 +24,11 @@
 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 * @endinternal
 *
-* @ingroup app
+* @ingroup 
 *
 * @details
 */
+
 #include <cmsis_nvic.h>
 
 #define NVIC_RAM_VECTOR_ADDRESS   (0x20000000)  // Vectors positioned at start of RAM

--- a/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/cmsis_nvic.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/cmsis_nvic.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 0.1 $
 * $Date: 2015-11-06 $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+* Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+* All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+* under limited terms and conditions.  The terms and conditions pertaining to the software
+* and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+* (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+* if applicable the software license agreement.  Do not use this software and/or
+* documentation unless you have carefully read and you agree to the limited terms and
+* conditions.  By using this software and/or documentation, you agree to the limited
+* terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
@@ -18,7 +24,7 @@
 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 * @endinternal
 *
-* @ingroup app
+* @ingroup 
 *
 * @details
 */

--- a/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/system_NCS36510.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/system_NCS36510.c	Fri Sep 16 16:24:25 2016 +0100
@@ -1,5 +1,5 @@
 /**************************************************************************//**
- * @file     system_ARMCM3.c
+ * @file     system_NCS36510.c
  * @brief    CMSIS Cortex-M3 Device System Source File
  *           for CM3 Device Series
  * @version  V1.05

--- a/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/system_NCS36510.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/system_NCS36510.h	Fri Sep 16 16:24:25 2016 +0100
@@ -1,5 +1,5 @@
 /**************************************************************************//**
- * @file     system_ARMCM3.h
+ * @file     system_NCS36510.h
  * @brief    CMSIS Cortex-M3 Device System Header File
  *           for CM3 Device Series
  * @version  V1.05

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_MICRO/startup_stm32f303xe.S	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,407 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name          : startup_stm32f303xe.s
+;* Author             : MCD Application Team
+;* Version            : V2.1.0
+;* Date               : 12-Sept-2014
+;* Description        : STM32F303xE devices vector table for MDK-ARM_MICRO toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+                
+Stack_Mem       SPACE   Stack_Size
+__initial_sp    EQU     0x20004000 ; Top of RAM
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000400
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit    EQU (__initial_sp - Stack_Size)
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_TSC_IRQHandler              ; EXTI Line2 and Touch Sense controller
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler                 ; ADC1 and ADC2
+                DCD     USB_HP_CAN_TX_IRQHandler          ; USB Device High Priority or CAN TX
+                DCD     USB_LP_CAN_RX0_IRQHandler         ; USB Device Low Priority or CAN RX0
+                DCD     CAN_RX1_IRQHandler                ; CAN RX1
+                DCD     CAN_SCE_IRQHandler                ; CAN SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     USBWakeUp_IRQHandler              ; USB Wakeup through EXTI line
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare
+                DCD     ADC3_IRQHandler                   ; ADC3
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     ADC4_IRQHandler                   ; ADC4
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     COMP1_2_3_IRQHandler              ; COMP1, COMP2 and COMP3
+                DCD     COMP4_5_6_IRQHandler              ; COMP4, COMP5 and COMP6
+                DCD     COMP7_IRQHandler                  ; COMP7
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     I2C3_EV_IRQHandler                ; I2C3 Event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 Error
+                DCD     USB_HP_IRQHandler                 ; USB High Priority remap
+                DCD     USB_LP_IRQHandler                 ; USB Low Priority remap
+                DCD     USBWakeUp_RMP_IRQHandler          ; USB Wakeup remap through EXTI
+                DCD     TIM20_BRK_IRQHandler              ; TIM20 Break
+                DCD     TIM20_UP_IRQHandler               ; TIM20 Update
+                DCD     TIM20_TRG_COM_IRQHandler          ; TIM20 Trigger and Commutation
+                DCD     TIM20_CC_IRQHandler               ; TIM20 Capture Compare
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SPI4_IRQHandler                   ; SPI4
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_IRQHandler                    [WEAK]
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_TSC_IRQHandler              [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_2_IRQHandler                 [WEAK]
+                EXPORT  USB_HP_CAN_TX_IRQHandler          [WEAK]
+                EXPORT  USB_LP_CAN_RX0_IRQHandler         [WEAK]
+                EXPORT  CAN_RX1_IRQHandler                [WEAK]
+                EXPORT  CAN_SCE_IRQHandler                [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_TIM15_IRQHandler         [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  TIM3_IRQHandler                   [WEAK]
+                EXPORT  TIM4_IRQHandler                   [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  USART2_IRQHandler                 [WEAK]
+                EXPORT  USART3_IRQHandler                 [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  USBWakeUp_IRQHandler              [WEAK]
+                EXPORT  TIM8_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM8_UP_IRQHandler                [WEAK]
+                EXPORT  TIM8_TRG_COM_IRQHandler           [WEAK]
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]
+                EXPORT  ADC3_IRQHandler                   [WEAK]
+                EXPORT  FMC_IRQHandler                    [WEAK]
+                EXPORT  SPI3_IRQHandler                   [WEAK]
+                EXPORT  UART4_IRQHandler                  [WEAK]
+                EXPORT  UART5_IRQHandler                  [WEAK]
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]
+                EXPORT  TIM7_IRQHandler                   [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  ADC4_IRQHandler                   [WEAK]
+                EXPORT  COMP1_2_3_IRQHandler              [WEAK]
+                EXPORT  COMP4_5_6_IRQHandler              [WEAK]
+                EXPORT  COMP7_IRQHandler                  [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  USBWakeUp_RMP_IRQHandler          [WEAK]
+                EXPORT  TIM20_BRK_IRQHandler              [WEAK]
+                EXPORT  TIM20_UP_IRQHandler               [WEAK]
+                EXPORT  TIM20_TRG_COM_IRQHandler          [WEAK]
+                EXPORT  TIM20_CC_IRQHandler               [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  SPI4_IRQHandler                   [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_TSC_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN_TX_IRQHandler
+USB_LP_CAN_RX0_IRQHandler
+CAN_RX1_IRQHandler
+CAN_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+USBWakeUp_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+FMC_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+ADC4_IRQHandler
+COMP1_2_3_IRQHandler
+COMP4_5_6_IRQHandler
+COMP7_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+USBWakeUp_RMP_IRQHandler
+TIM20_BRK_IRQHandler
+TIM20_UP_IRQHandler
+TIM20_TRG_COM_IRQHandler
+TIM20_CC_IRQHandler
+FPU_IRQHandler
+SPI4_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_MICRO/stm32f303xe.sct	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F303RE: 512KB FLASH (0x80000) + 64KB SRAM (0x10000)
+LR_IROM1 0x08000000 0x80000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x80000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; 101 vectors = 404 bytes (0x194) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x194) (0x10000-0x194)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_STD/startup_stm32f303xe.S	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,380 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name          : startup_stm32f303xe.s
+;* Author             : MCD Application Team
+;* Version            : V2.1.0
+;* Date               : 12-Sept-2014
+;* Description        : STM32F303xE devices vector table for MDK-ARM_STD toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+__initial_sp    EQU     0x20004000 ; Top of RAM
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_TSC_IRQHandler              ; EXTI Line2 and Touch Sense controller
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler                 ; ADC1 and ADC2
+                DCD     USB_HP_CAN_TX_IRQHandler          ; USB Device High Priority or CAN TX
+                DCD     USB_LP_CAN_RX0_IRQHandler         ; USB Device Low Priority or CAN RX0
+                DCD     CAN_RX1_IRQHandler                ; CAN RX1
+                DCD     CAN_SCE_IRQHandler                ; CAN SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     USBWakeUp_IRQHandler              ; USB Wakeup through EXTI line
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare
+                DCD     ADC3_IRQHandler                   ; ADC3
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     ADC4_IRQHandler                   ; ADC4
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     COMP1_2_3_IRQHandler              ; COMP1, COMP2 and COMP3
+                DCD     COMP4_5_6_IRQHandler              ; COMP4, COMP5 and COMP6
+                DCD     COMP7_IRQHandler                  ; COMP7
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     I2C3_EV_IRQHandler                ; I2C3 Event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 Error
+                DCD     USB_HP_IRQHandler                 ; USB High Priority remap
+                DCD     USB_LP_IRQHandler                 ; USB Low Priority remap
+                DCD     USBWakeUp_RMP_IRQHandler          ; USB Wakeup remap through EXTI
+                DCD     TIM20_BRK_IRQHandler              ; TIM20 Break
+                DCD     TIM20_UP_IRQHandler               ; TIM20 Update
+                DCD     TIM20_TRG_COM_IRQHandler          ; TIM20 Trigger and Commutation
+                DCD     TIM20_CC_IRQHandler               ; TIM20 Capture Compare
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SPI4_IRQHandler                   ; SPI4
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_IRQHandler                    [WEAK]
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_TSC_IRQHandler              [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC1_2_IRQHandler                 [WEAK]
+                EXPORT  USB_HP_CAN_TX_IRQHandler          [WEAK]
+                EXPORT  USB_LP_CAN_RX0_IRQHandler         [WEAK]
+                EXPORT  CAN_RX1_IRQHandler                [WEAK]
+                EXPORT  CAN_SCE_IRQHandler                [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_TIM15_IRQHandler         [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  TIM3_IRQHandler                   [WEAK]
+                EXPORT  TIM4_IRQHandler                   [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  USART2_IRQHandler                 [WEAK]
+                EXPORT  USART3_IRQHandler                 [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  USBWakeUp_IRQHandler              [WEAK]
+                EXPORT  TIM8_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM8_UP_IRQHandler                [WEAK]
+                EXPORT  TIM8_TRG_COM_IRQHandler           [WEAK]
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]
+                EXPORT  ADC3_IRQHandler                   [WEAK]
+                EXPORT  FMC_IRQHandler                    [WEAK]
+                EXPORT  SPI3_IRQHandler                   [WEAK]
+                EXPORT  UART4_IRQHandler                  [WEAK]
+                EXPORT  UART5_IRQHandler                  [WEAK]
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]
+                EXPORT  TIM7_IRQHandler                   [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  ADC4_IRQHandler                   [WEAK]
+                EXPORT  COMP1_2_3_IRQHandler              [WEAK]
+                EXPORT  COMP4_5_6_IRQHandler              [WEAK]
+                EXPORT  COMP7_IRQHandler                  [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  USB_HP_IRQHandler                 [WEAK]
+                EXPORT  USB_LP_IRQHandler                 [WEAK]
+                EXPORT  USBWakeUp_RMP_IRQHandler          [WEAK]
+                EXPORT  TIM20_BRK_IRQHandler              [WEAK]
+                EXPORT  TIM20_UP_IRQHandler               [WEAK]
+                EXPORT  TIM20_TRG_COM_IRQHandler          [WEAK]
+                EXPORT  TIM20_CC_IRQHandler               [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  SPI4_IRQHandler                   [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_TSC_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN_TX_IRQHandler
+USB_LP_CAN_RX0_IRQHandler
+CAN_RX1_IRQHandler
+CAN_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+USBWakeUp_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+FMC_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+ADC4_IRQHandler
+COMP1_2_3_IRQHandler
+COMP4_5_6_IRQHandler
+COMP7_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+USBWakeUp_RMP_IRQHandler
+TIM20_BRK_IRQHandler
+TIM20_UP_IRQHandler
+TIM20_TRG_COM_IRQHandler
+TIM20_CC_IRQHandler
+FPU_IRQHandler
+SPI4_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_STD/stm32f303xe.sct	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F303RE: 512KB FLASH (0x80000) + 64KB SRAM (0x10000)
+LR_IROM1 0x08000000 0x80000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x80000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; 101 vectors = 404 bytes (0x194) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x194) (0x10000-0x194)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_STD/sys.cpp	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model, 
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_GCC_ARM/STM32F303XE.ld	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,155 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{ 
+  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
+  CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 16K
+  RAM (rwx) : ORIGIN = 0x20000194, LENGTH = 64K - 0x194
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+    _sidata = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        _sdata = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+        _edata = .;
+
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        _sbss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+        _ebss = .;
+    } > RAM
+    
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+    
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.S	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,505 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f303xe.s
+  * @author    MCD Application Team
+  * @version   
+  * @date      12-Sept-2014
+  * @brief     STM32F303xE devices vector table for Atollic 
+  *            TrueSTUDIO toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system  
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
+
+/* Call the clock system intitialization function.*/
+    bl  SystemInit
+/* Call static constructors */
+    //bl __libc_init_array
+/* Call the application's entry point.*/
+    //bl  main
+/**
+ * Calling the crt0 'cold-start' entry point. There __libc_init_array is called
+ * and when existing hardware_init_hook() and software_init_hook() before 
+ * starting main(). software_init_hook() is available and has to be called due 
+ * to initializsation when using rtos.
+*/
+    bl _start
+
+LoopForever:
+    b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_IRQHandler
+	.word	TAMP_STAMP_IRQHandler
+	.word	RTC_WKUP_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	RCC_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_TSC_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	ADC1_2_IRQHandler
+	.word	USB_HP_CAN_TX_IRQHandler
+	.word	USB_LP_CAN_RX0_IRQHandler
+	.word	CAN_RX1_IRQHandler
+	.word	CAN_SCE_IRQHandler
+	.word	EXTI9_5_IRQHandler
+	.word	TIM1_BRK_TIM15_IRQHandler
+	.word	TIM1_UP_TIM16_IRQHandler
+	.word	TIM1_TRG_COM_TIM17_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	EXTI15_10_IRQHandler
+	.word	RTC_Alarm_IRQHandler
+	.word	USBWakeUp_IRQHandler
+	.word	TIM8_BRK_IRQHandler
+	.word	TIM8_UP_IRQHandler
+	.word	TIM8_TRG_COM_IRQHandler
+	.word	TIM8_CC_IRQHandler
+	.word	ADC3_IRQHandler
+	.word	FMC_IRQHandler
+	.word	0
+	.word	0
+	.word	SPI3_IRQHandler
+	.word	UART4_IRQHandler
+	.word	UART5_IRQHandler
+	.word	TIM6_DAC_IRQHandler
+	.word	TIM7_IRQHandler
+	.word	DMA2_Channel1_IRQHandler
+	.word	DMA2_Channel2_IRQHandler
+	.word	DMA2_Channel3_IRQHandler
+	.word	DMA2_Channel4_IRQHandler
+	.word	DMA2_Channel5_IRQHandler
+	.word	ADC4_IRQHandler
+	.word	0
+	.word	0
+	.word	COMP1_2_3_IRQHandler
+	.word	COMP4_5_6_IRQHandler
+	.word	COMP7_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	I2C3_EV_IRQHandler
+	.word	I2C3_ER_IRQHandler
+	.word	USB_HP_IRQHandler
+	.word	USB_LP_IRQHandler
+	.word	USBWakeUp_RMP_IRQHandler
+	.word	TIM20_BRK_IRQHandler
+	.word	TIM20_UP_IRQHandler
+	.word	TIM20_TRG_COM_IRQHandler
+	.word	TIM20_CC_IRQHandler
+	.word	FPU_IRQHandler
+	.word	0
+	.word	0
+	.word	SPI4_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+  .weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+  .weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+  .weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_IRQHandler
+	.thumb_set PVD_IRQHandler,Default_Handler
+
+	.weak	TAMP_STAMP_IRQHandler
+	.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+	.weak	RTC_WKUP_IRQHandler
+	.thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_TSC_IRQHandler
+	.thumb_set EXTI2_TSC_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel7_IRQHandler
+	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	ADC1_2_IRQHandler
+	.thumb_set ADC1_2_IRQHandler,Default_Handler
+
+	.weak	USB_HP_CAN_TX_IRQHandler
+	.thumb_set USB_HP_CAN_TX_IRQHandler,Default_Handler
+
+	.weak	USB_LP_CAN_RX0_IRQHandler
+	.thumb_set USB_LP_CAN_RX0_IRQHandler,Default_Handler
+
+	.weak	CAN_RX1_IRQHandler
+	.thumb_set CAN_RX1_IRQHandler,Default_Handler
+
+	.weak	CAN_SCE_IRQHandler
+	.thumb_set CAN_SCE_IRQHandler,Default_Handler
+
+	.weak	EXTI9_5_IRQHandler
+	.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_TIM15_IRQHandler
+	.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_TIM16_IRQHandler
+	.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_TIM17_IRQHandler
+	.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	TIM4_IRQHandler
+	.thumb_set TIM4_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	EXTI15_10_IRQHandler
+	.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+	.weak	RTC_Alarm_IRQHandler
+	.thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+	.weak	USBWakeUp_IRQHandler
+	.thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+	.weak	TIM8_BRK_IRQHandler
+	.thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM8_UP_IRQHandler
+	.thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+	.weak	TIM8_TRG_COM_IRQHandler
+	.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM8_CC_IRQHandler
+	.thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+	.weak	ADC3_IRQHandler
+	.thumb_set ADC3_IRQHandler,Default_Handler
+
+	.weak	FMC_IRQHandler
+	.thumb_set FMC_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	UART4_IRQHandler
+	.thumb_set UART4_IRQHandler,Default_Handler
+
+	.weak	UART5_IRQHandler
+	.thumb_set UART5_IRQHandler,Default_Handler
+
+	.weak	TIM6_DAC_IRQHandler
+	.thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel1_IRQHandler
+	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel2_IRQHandler
+	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel3_IRQHandler
+	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel4_IRQHandler
+	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel5_IRQHandler
+	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	ADC4_IRQHandler
+	.thumb_set ADC4_IRQHandler,Default_Handler	
+	
+	.weak	COMP1_2_3_IRQHandler
+	.thumb_set COMP1_2_3_IRQHandler,Default_Handler
+	
+	.weak	COMP4_5_6_IRQHandler
+	.thumb_set COMP4_5_6_IRQHandler,Default_Handler
+	
+	.weak	COMP7_IRQHandler
+	.thumb_set COMP7_IRQHandler,Default_Handler	
+	
+	.weak	I2C3_EV_IRQHandler
+	.thumb_set I2C3_EV_IRQHandler,Default_Handler	
+	
+	.weak	I2C3_ER_IRQHandler
+	.thumb_set I2C3_ER_IRQHandler,Default_Handler	
+	
+	.weak	USB_HP_IRQHandler
+	.thumb_set USB_HP_IRQHandler,Default_Handler
+	
+	.weak	USB_LP_IRQHandler
+	.thumb_set USB_LP_IRQHandler,Default_Handler
+	
+	.weak	USBWakeUp_RMP_IRQHandler
+	.thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
+	
+	.weak	TIM20_BRK_IRQHandler
+	.thumb_set TIM20_BRK_IRQHandler,Default_Handler
+	
+	.weak	TIM20_UP_IRQHandler
+	.thumb_set TIM20_UP_IRQHandler,Default_Handler
+	
+	.weak	TIM20_TRG_COM_IRQHandler
+	.thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler
+	
+	.weak	TIM20_CC_IRQHandler
+	.thumb_set TIM20_CC_IRQHandler,Default_Handler
+	
+	.weak	FPU_IRQHandler
+	.thumb_set FPU_IRQHandler,Default_Handler
+	
+	.weak	SPI4_IRQHandler
+	.thumb_set SPI4_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_IAR/startup_stm32f303xe.S	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,610 @@
+;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name          : startup_stm32f303xe.s
+;* Author             : MCD Application Team
+;* Version            : V2.1.0
+;* Date               : 12-Sept-2014
+;* Description        : STM32F303RE/STM32F303VE/STM32F303ZE devices vector table 
+;*                      for EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; 0: Window WatchDog
+        DCD     PVD_IRQHandler                    ; 1: PVD through EXTI Line detection
+        DCD     TAMP_STAMP_IRQHandler             ; 2: Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; 3: RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; 4: FLASH
+        DCD     RCC_IRQHandler                    ; 5: RCC
+        DCD     EXTI0_IRQHandler                  ; 6: EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; 7: EXTI Line1
+        DCD     EXTI2_TSC_IRQHandler              ; 8: EXTI Line2 and Touch Sense controller
+        DCD     EXTI3_IRQHandler                  ; 9: EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; 10: EXTI Line4
+        DCD     DMA1_Channel1_IRQHandler          ; 11: DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler          ; 12: DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler          ; 13: DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler          ; 14: DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler          ; 15: DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler          ; 16: DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler          ; 17: DMA1 Channel 7
+        DCD     ADC1_2_IRQHandler                 ; 18: ADC1 and ADC2
+        DCD     USB_HP_CAN_TX_IRQHandler          ; 19: USB Device High Priority or CAN TX
+        DCD     USB_LP_CAN_RX0_IRQHandler         ; 20: USB Device Low Priority or CAN RX0
+        DCD     CAN_RX1_IRQHandler                ; 21: CAN RX1
+        DCD     CAN_SCE_IRQHandler                ; 22: CAN SCE
+        DCD     EXTI9_5_IRQHandler                ; 23: External Line[9:5]s
+        DCD     TIM1_BRK_TIM15_IRQHandler         ; 24: TIM1 Break and TIM15
+        DCD     TIM1_UP_TIM16_IRQHandler          ; 25: TIM1 Update and TIM16
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; 26: TIM1 Trigger and Commutation and TIM17
+        DCD     TIM1_CC_IRQHandler                ; 27: TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; 28: TIM2
+        DCD     TIM3_IRQHandler                   ; 29: TIM3
+        DCD     TIM4_IRQHandler                   ; 30: TIM4
+        DCD     I2C1_EV_IRQHandler                ; 31: I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; 32: I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; 33: I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; 34: I2C2 Error
+        DCD     SPI1_IRQHandler                   ; 35: SPI1
+        DCD     SPI2_IRQHandler                   ; 36: SPI2
+        DCD     USART1_IRQHandler                 ; 37: USART1
+        DCD     USART2_IRQHandler                 ; 38: USART2
+        DCD     USART3_IRQHandler                 ; 39: USART3
+        DCD     EXTI15_10_IRQHandler              ; 40: External Line[15:10]s
+        DCD     RTC_Alarm_IRQHandler              ; 41: RTC Alarm (A and B) through EXTI Line
+        DCD     USBWakeUp_IRQHandler              ; 42: USB Wakeup through EXTI line
+        DCD     TIM8_BRK_IRQHandler               ; 43: TIM8 Break
+        DCD     TIM8_UP_IRQHandler                ; 44: TIM8 Update
+        DCD     TIM8_TRG_COM_IRQHandler           ; 45: TIM8 Trigger and Commutation
+        DCD     TIM8_CC_IRQHandler                ; 46: TIM8 Capture Compare
+        DCD     ADC3_IRQHandler                   ; 47: ADC3
+        DCD     FMC_IRQHandler                    ; 48: FMC
+        DCD     0                                 ; 49: Reserved
+        DCD     0                                 ; 50: Reserved
+        DCD     SPI3_IRQHandler                   ; 51: SPI3
+        DCD     UART4_IRQHandler                  ; 52: UART4
+        DCD     UART5_IRQHandler                  ; 53: UART5
+        DCD     TIM6_DAC_IRQHandler               ; 54: TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; 55: TIM7
+        DCD     DMA2_Channel1_IRQHandler          ; 56: DMA2 Channel 1
+        DCD     DMA2_Channel2_IRQHandler          ; 57: DMA2 Channel 2
+        DCD     DMA2_Channel3_IRQHandler          ; 58: DMA2 Channel 3
+        DCD     DMA2_Channel4_IRQHandler          ; 59: DMA2 Channel 4
+        DCD     DMA2_Channel5_IRQHandler          ; 60: DMA2 Channel 5
+        DCD     ADC4_IRQHandler                   ; 61: ADC4
+        DCD     0                                 ; 62: Reserved
+        DCD     0                                 ; 63: Reserved
+        DCD     COMP1_2_3_IRQHandler              ; 64: COMP1, COMP2 and COMP3
+        DCD     COMP4_5_6_IRQHandler              ; 65: COMP4, COMP5 and COMP6
+        DCD     COMP7_IRQHandler                  ; 66: COMP7
+        DCD     0                                 ; 67: Reserved
+        DCD     0                                 ; 68: Reserved
+        DCD     0                                 ; 69: Reserved
+        DCD     0                                 ; 70: Reserved
+        DCD     0                                 ; 71: Reserved
+        DCD     I2C3_EV_IRQHandler                ; 72: I2C3 Event
+        DCD     I2C3_ER_IRQHandler                ; 73: I2C3 Error
+        DCD     USB_HP_IRQHandler                 ; 74: USB High Priority remap
+        DCD     USB_LP_IRQHandler                 ; 75: USB Low Priority remap
+        DCD     USBWakeUp_RMP_IRQHandler          ; 76: USB Wakeup remap through EXTI
+        DCD     TIM20_BRK_IRQHandler              ; 77: TIM20 Break
+        DCD     TIM20_UP_IRQHandler               ; 78: TIM20 Update
+        DCD     TIM20_TRG_COM_IRQHandler          ; 79: TIM20 Trigger and Commutation
+        DCD     TIM20_CC_IRQHandler               ; 80: TIM20 Capture Compare
+        DCD     FPU_IRQHandler                    ; 81: FPU
+        DCD     0                                 ; 82: Reserved
+        DCD     0                                 ; 83: Reserved
+        DCD     SPI4_IRQHandler                   ; 84: SPI4
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_IRQHandler
+        B PVD_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_TSC_IRQHandler
+        B EXTI2_TSC_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+        B ADC1_2_IRQHandler
+
+        PUBWEAK USB_HP_CAN_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_CAN_TX_IRQHandler
+        B USB_HP_CAN_TX_IRQHandler
+
+        PUBWEAK USB_LP_CAN_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_CAN_RX0_IRQHandler
+        B USB_LP_CAN_RX0_IRQHandler
+
+        PUBWEAK CAN_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX1_IRQHandler
+        B CAN_RX1_IRQHandler
+
+        PUBWEAK CAN_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_SCE_IRQHandler
+        B CAN_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+        B TIM1_BRK_TIM15_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK USBWakeUp_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USBWakeUp_IRQHandler
+        B USBWakeUp_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK ADC3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+        B ADC3_IRQHandler
+        
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler        
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+
+        PUBWEAK ADC4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC4_IRQHandler
+        B ADC4_IRQHandler
+
+        PUBWEAK COMP1_2_3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_2_3_IRQHandler
+        B COMP1_2_3_IRQHandler
+
+        PUBWEAK COMP4_5_6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP4_5_6_IRQHandler
+        B COMP4_5_6_IRQHandler
+
+        PUBWEAK COMP7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP7_IRQHandler
+        B COMP7_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK USBWakeUp_RMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USBWakeUp_RMP_IRQHandler
+        B USBWakeUp_RMP_IRQHandler
+
+        PUBWEAK TIM20_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM20_BRK_IRQHandler
+        B TIM20_BRK_IRQHandler
+
+        PUBWEAK TIM20_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM20_UP_IRQHandler
+        B TIM20_UP_IRQHandler
+
+        PUBWEAK TIM20_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM20_TRG_COM_IRQHandler
+        B TIM20_TRG_COM_IRQHandler
+
+        PUBWEAK TIM20_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM20_CC_IRQHandler
+        B TIM20_CC_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+        B SPI4_IRQHandler
+        
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_IAR/stm32f303xe.icf	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,35 @@
+/* [ROM = 512kb = 0x80000] */
+define symbol __intvec_start__     = 0x08000000;
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__   = 0x0807FFFF;
+
+define symbol __region_CCMRAM_start__ = 0x10000000;
+define symbol __region_CCMRAM_end__   = 0x10003FFF;
+
+/* [RAM = 64kb = 0x10000] Vector table dynamic copy: 101 vectors = 404 bytes (0x194) to be reserved in RAM */
+define symbol __NVIC_start__          = 0x20000000;
+define symbol __NVIC_end__            = 0x20000197; /* Add 4 more bytes to be aligned on 8 bytes */
+define symbol __region_RAM_start__    = 0x20000198;
+define symbol __region_RAM_end__      = 0x2000FFFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region    = mem:[from __region_ROM_start__    to __region_ROM_end__];
+define region RAM_region    = mem:[from __region_RAM_start__    to __region_RAM_end__];
+define region CCMRAM_region = mem:[from __region_CCMRAM_start__ to __region_CCMRAM_end__];
+
+/* Stack and Heap */
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __size_cstack__ = 0x2000;
+define symbol __size_heap__   = 0x4000;
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, block STACKHEAP };

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/cmsis.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32f3xx.h"
+#include "cmsis_nvic.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/cmsis_nvic.c	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */ 
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS   (0x20000000)  // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000)  // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    uint32_t *vectors = (uint32_t *)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = vectors;
+        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+        for (i=0; i<NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+    }
+    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/cmsis_nvic.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */ 
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// STM32F303RE
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 85 vectors = 340 bytes from 0x40 to 0x193
+// Total: 101 vectors = 404 bytes (0x194) to be reserved in RAM
+#define NVIC_NUM_VECTORS      101
+#define NVIC_USER_IRQ_OFFSET  16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/hal_tick.c	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,120 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.c
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#include "hal_tick.h"
+
+TIM_HandleTypeDef TimMasterHandle;
+uint32_t PreviousVal = 0;
+
+void us_ticker_irq_handler(void);
+
+void timer_irq_handler(void) {
+    // Channel 1 for mbed timeout
+    if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
+        __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
+        us_ticker_irq_handler();
+    }
+
+    // Channel 2 for HAL tick
+    if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
+        __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
+        uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
+        if ((val - PreviousVal) >= HAL_TICK_DELAY) {
+            // Increment HAL variable
+            HAL_IncTick();
+            // Prepare next interrupt
+            __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
+            PreviousVal = val;
+#if 0 // For DEBUG only
+            HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
+#endif
+        }
+    }
+}
+
+// Reconfigure the HAL tick using a standard timer instead of systick.
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
+    // Enable timer clock
+    TIM_MST_RCC;
+
+    // Reset timer
+    TIM_MST_RESET_ON;
+    TIM_MST_RESET_OFF;
+
+    // Configure time base
+    TimMasterHandle.Instance = TIM_MST;
+    TimMasterHandle.Init.Period            = 0xFFFFFFFF;
+    TimMasterHandle.Init.Prescaler         = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick
+    TimMasterHandle.Init.ClockDivision     = 0;
+    TimMasterHandle.Init.CounterMode       = TIM_COUNTERMODE_UP;
+    TimMasterHandle.Init.RepetitionCounter = 0;
+    HAL_TIM_OC_Init(&TimMasterHandle);
+
+    NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
+    NVIC_EnableIRQ(TIM_MST_IRQ);
+
+    // Channel 1 for mbed timeout
+    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+    // Channel 2 for HAL tick
+    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
+    PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
+    __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
+    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+
+#if 0 // For DEBUG only
+    __GPIOB_CLK_ENABLE();
+    GPIO_InitTypeDef GPIO_InitStruct;
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#endif
+
+    return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/hal_tick.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,60 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.h
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f3xx.h"
+#include "cmsis_nvic.h"
+   
+#define TIM_MST      TIM2
+#define TIM_MST_IRQ  TIM2_IRQn
+#define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/stm32f303xe.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,15169 @@
+/**
+  ******************************************************************************
+  * @file    stm32f303xe.h
+  * @author  MCD Application Team
+  * @version V2.3.0
+  * @date    29-April-2015
+  * @brief   CMSIS STM32F303xE Devices Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32f303xe
+  * @{
+  */
+
+#ifndef __STM32F303xE_H
+#define __STM32F303xE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
+#define __MPU_PRESENT             1U       /*!< STM32F303xE devices provide an MPU */
+#define __NVIC_PRIO_BITS          4U       /*!< STM32F303xE devices use 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT             1U       /*!< STM32F303xE devices provide an FPU */
+#endif
+/**
+  * @}
+  */
+   
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32F303xE devices Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum
+{
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line 19          */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line 20                     */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_TSC_IRQn              = 8,      /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt         */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 Interrupt                                          */
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 Interrupt                                          */
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 Interrupt                                          */
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 Interrupt                                          */
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 Interrupt                                          */
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 Interrupt                                          */
+  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 Interrupt                                          */
+  ADC1_2_IRQn                 = 18,     /*!< ADC1 & ADC2 Interrupts                                            */
+  USB_HP_CAN_TX_IRQn          = 19,     /*!< USB Device High Priority or CAN TX Interrupts                     */
+  USB_LP_CAN_RX0_IRQn         = 20,     /*!< USB Device Low Priority or CAN RX0 Interrupts                     */
+  CAN_RX1_IRQn                = 21,     /*!< CAN RX1 Interrupt                                                 */
+  CAN_SCE_IRQn                = 22,     /*!< CAN SCE Interrupt                                                 */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                                   */
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                                  */
+  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt                  */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup)        */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup)        */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup)   */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup)   */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup)   */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt                 */
+  USBWakeUp_IRQn              = 42,     /*!< USB Wakeup Interrupt                                              */
+  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                              */
+  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                             */
+  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt                            */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                             */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup)     */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup)     */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC underrun error Interrupt             */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                             */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */
+  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */
+  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */
+  ADC4_IRQn                   = 61,     /*!< ADC4  global Interrupt                                            */
+  COMP1_2_3_IRQn              = 64,     /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
+  COMP4_5_6_IRQn              = 65,     /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
+  COMP7_IRQn                  = 66,     /*!< COMP7 global Interrupt via EXTI Line33                            */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 Error Interrupt                                              */
+  USB_HP_IRQn                 = 74,     /*!< USB High Priority global Interrupt                                */
+  USB_LP_IRQn                 = 75,     /*!< USB Low Priority global Interrupt                                 */
+  USBWakeUp_RMP_IRQn          = 76,     /*!< USB Wakeup Interrupt remap                                        */
+  TIM20_BRK_IRQn              = 77,     /*!< TIM20 Break Interrupt                                              */
+  TIM20_UP_IRQn               = 78,     /*!< TIM20 Update Interrupt                                             */
+  TIM20_TRG_COM_IRQn          = 79,     /*!< TIM20 Trigger and Commutation Interrupt                            */
+  TIM20_CC_IRQn               = 80,     /*!< TIM20 Capture Compare Interrupt                                    */
+  FPU_IRQn                    = 81,      /*!< Floating point Interrupt                                          */
+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */   
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"            /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f3xx.h"    /* STM32F3xx System Header */
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                 Address offset: 0x00 */
+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                     Address offset: 0x04 */
+  __IO uint32_t CR;               /*!< ADC control register,                              Address offset: 0x08 */
+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                        Address offset: 0x0C */
+  uint32_t      RESERVED0;        /*!< Reserved, 0x010                                                         */
+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                        Address offset: 0x14 */
+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                        Address offset: 0x18 */
+  uint32_t      RESERVED1;        /*!< Reserved, 0x01C                                                         */
+  __IO uint32_t TR1;              /*!< ADC watchdog threshold register 1,                 Address offset: 0x20 */
+  __IO uint32_t TR2;              /*!< ADC watchdog threshold register 2,                 Address offset: 0x24 */
+  __IO uint32_t TR3;              /*!< ADC watchdog threshold register 3,                 Address offset: 0x28 */
+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                         */
+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                   Address offset: 0x30 */
+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                   Address offset: 0x34 */
+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                   Address offset: 0x38 */
+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                   Address offset: 0x3C */
+  __IO uint32_t DR;               /*!< ADC regular data register,                         Address offset: 0x40 */
+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                         */
+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                         */
+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                    Address offset: 0x4C */
+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                 */
+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                             Address offset: 0x60 */
+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                             Address offset: 0x64 */
+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                             Address offset: 0x68 */
+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                             Address offset: 0x6C */
+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                 */
+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                      Address offset: 0x80 */
+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                      Address offset: 0x84 */
+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                      Address offset: 0x88 */
+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                      Address offset: 0x8C */
+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                 */
+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,     Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,     Address offset: 0xA4 */
+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                         */
+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                         */
+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,         Address offset: 0xB0 */
+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                          Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;            /*!< ADC Common status register,                  Address offset: ADC1/3 base address + 0x300 */
+  uint32_t      RESERVED;       /*!< Reserved, ADC1/3 base address + 0x304                                                    */
+  __IO uint32_t CCR;            /*!< ADC common control register,                 Address offset: ADC1/3 base address + 0x308 */
+  __IO uint32_t CDR;            /*!< ADC common regular data register for dual
+                                     AND triple modes,                            Address offset: ADC1/3 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+/**
+  * @brief Controller Area Network TxMailBox
+  */
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+  * @brief Controller Area Network FIFOMailBox
+  */
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+  * @brief Controller Area Network FilterRegister
+  */
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+  * @brief Controller Area Network
+  */
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+/**
+  * @brief Analog Comparators
+  */
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
+  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
+  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
+  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
+  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
+  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */
+  __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */
+  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */
+  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */
+  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */
+  __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */
+  uint32_t      RESERVED1;    /*!< Reserved, 0x18                                                                */
+  uint32_t      RESERVED2;    /*!< Reserved, 0x1C                                                                */
+  __IO uint32_t IMR2;         /*!< EXTI Interrupt mask register,                            Address offset: 0x20 */
+  __IO uint32_t EMR2;         /*!< EXTI Event mask register,                                Address offset: 0x24 */
+  __IO uint32_t RTSR2;        /*!< EXTI Rising trigger selection register,                  Address offset: 0x28 */
+  __IO uint32_t FTSR2;        /*!< EXTI Falling trigger selection register,                 Address offset: 0x2C */
+  __IO uint32_t SWIER2;       /*!< EXTI Software interrupt event register,                  Address offset: 0x30 */
+  __IO uint32_t PR2;          /*!< EXTI Pending register,                                   Address offset: 0x34 */
+}EXTI_TypeDef;
+
+/**
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;          /*!< FLASH access control register,              Address offset: 0x00 */
+  __IO uint32_t KEYR;         /*!< FLASH key register,                         Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;      /*!< FLASH option key register,                  Address offset: 0x08 */
+  __IO uint32_t SR;           /*!< FLASH status register,                      Address offset: 0x0C */
+  __IO uint32_t CR;           /*!< FLASH control register,                     Address offset: 0x10 */
+  __IO uint32_t AR;           /*!< FLASH address register,                     Address offset: 0x14 */
+  uint32_t      RESERVED;     /*!< Reserved, 0x18                                                   */
+  __IO uint32_t OBR;          /*!< FLASH Option byte register,                 Address offset: 0x1C */
+  __IO uint32_t WRPR;         /*!< FLASH Write register,                       Address offset: 0x20 */
+
+} FLASH_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
+} FMC_Bank1_TypeDef; 
+
+/** 
+  * @brief Flexible Memory Controller Bank1E
+  */
+  
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/** 
+  * @brief Flexible Memory Controller Bank2
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
+  uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */
+  uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */
+  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
+  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
+  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
+  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+  uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */
+  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
+} FMC_Bank2_3_TypeDef;
+
+/** 
+  * @brief Flexible Memory Controller Bank4
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
+  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
+  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
+  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
+  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
+} FMC_Bank4_TypeDef; 
+
+/**
+  * @brief Option Bytes Registers
+  */
+typedef struct
+{
+  __IO uint16_t RDP;          /*!<FLASH option byte Read protection,             Address offset: 0x00 */
+  __IO uint16_t USER;         /*!<FLASH option byte user options,                Address offset: 0x02 */
+  uint16_t RESERVED0;         /*!< Reserved,                                                     0x04 */
+  uint16_t RESERVED1;         /*!< Reserved,                                                     0x06 */
+  __IO uint16_t WRP0;         /*!<FLASH option byte write protection 0,          Address offset: 0x08 */
+  __IO uint16_t WRP1;         /*!<FLASH option byte write protection 1,          Address offset: 0x0C */
+  __IO uint16_t WRP2;         /*!<FLASH option byte write protection 2,          Address offset: 0x10 */
+  __IO uint16_t WRP3;         /*!<FLASH option byte write protection 3,          Address offset: 0x12 */
+} OB_TypeDef;
+
+/**
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;        /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;       /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;          /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;          /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset register,      Address offset: 0x1A */
+  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];       /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+  __IO uint32_t BRR;          /*!< GPIO bit reset register,               Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+  * @brief Operational Amplifier (OPAMP)
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;        /*!< OPAMP control and status register,            Address offset: 0x00 */
+} OPAMP_TypeDef;
+
+/**
+  * @brief System configuration controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                      Address offset: 0x00 */
+  __IO uint32_t RCR;        /*!< SYSCFG CCM SRAM protection register,               Address offset: 0x04 */
+  __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
+  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                      Address offset: 0x18 */
+  __IO uint32_t RESERVED0;  /*!< Reserved,                                                          0x1C */
+  __IO uint32_t RESERVED1;  /*!< Reserved,                                                          0x20 */
+  __IO uint32_t RESERVED2;  /*!< Reserved,                                                          0x24 */
+  __IO uint32_t RESERVED4;  /*!< Reserved,                                                          0x28 */
+  __IO uint32_t RESERVED5;  /*!< Reserved,                                                          0x2C */
+  __IO uint32_t RESERVED6;  /*!< Reserved,                                                          0x30 */
+  __IO uint32_t RESERVED7;  /*!< Reserved,                                                          0x34 */
+  __IO uint32_t RESERVED8;  /*!< Reserved,                                                          0x38 */
+  __IO uint32_t RESERVED9;  /*!< Reserved,                                                          0x3C */
+  __IO uint32_t RESERVED10; /*!< Reserved,                                                          0x40 */
+  __IO uint32_t RESERVED11; /*!< Reserved,                                                          0x44 */
+  __IO uint32_t CFGR4;      /*!< SYSCFG configuration register 4,                   Address offset: 0x48 */
+  __IO uint32_t RESERVED12; /*!< Reserved,                                                          0x4C */
+  __IO uint32_t RESERVED13; /*!< Reserved,                                                          0x50 */
+} SYSCFG_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
+}I2C_TypeDef;
+
+/**
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+  * @brief Reset and Clock Control
+  */
+typedef struct
+{
+  __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
+  __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
+  __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
+  __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
+  __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
+  __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
+  __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */
+  __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
+  __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
+  __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
+  __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */
+} RCC_TypeDef;
+
+/**
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                        Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                        Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                     Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                   Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                   Address offset: 0x10 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                Address offset: 0x14 */
+  uint32_t RESERVED0;       /*!< Reserved, 0x18                                                                 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                     Address offset: 0x1C */
+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                     Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                            Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                  Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                               Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                             Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                             Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                 Address offset: 0x3C */
+  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                          Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                          Address offset: 0x48 */
+  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                 */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                    Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                    Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                    Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                    Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                    Address offset: 0x60 */
+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                    Address offset: 0x64 */
+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                    Address offset: 0x68 */
+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                    Address offset: 0x6C */
+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                    Address offset: 0x70 */
+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                    Address offset: 0x74 */
+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                   Address offset: 0x78 */
+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                   Address offset: 0x7C */
+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                   Address offset: 0x80 */
+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                   Address offset: 0x84 */
+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                   Address offset: 0x88 */
+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                   Address offset: 0x8C */
+} RTC_TypeDef;
+
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< SPI Control register 1,                              Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
+  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
+  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
+  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
+  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
+  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
+  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
+  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+  * @brief TIM
+  */
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
+  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,       Address offset: 0x58 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare register 4,      Address offset: 0x5C */
+} TIM_TypeDef;
+
+/**
+  * @brief Touch Sensing Controller (TSC)
+  */
+typedef struct
+{
+  __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
+  __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
+  __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
+  __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
+  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
+  uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
+  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
+  uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
+  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
+  uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
+  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
+  uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
+  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
+  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED1;  /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED2;  /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef;
+
+/** 
+  * @brief Universal Serial Bus Full Speed Device
+  */
+  
+typedef struct
+{
+  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
+  __IO uint16_t RESERVED0;       /*!< Reserved */     
+  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
+  __IO uint16_t RESERVED1;       /*!< Reserved */       
+  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
+  __IO uint16_t RESERVED2;       /*!< Reserved */       
+  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
+  __IO uint16_t RESERVED3;       /*!< Reserved */       
+  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
+  __IO uint16_t RESERVED4;       /*!< Reserved */       
+  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
+  __IO uint16_t RESERVED5;       /*!< Reserved */       
+  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
+  __IO uint16_t RESERVED6;       /*!< Reserved */       
+  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
+  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
+  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
+  __IO uint16_t RESERVED8;       /*!< Reserved */       
+  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
+  __IO uint16_t RESERVED9;       /*!< Reserved */       
+  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
+  __IO uint16_t RESERVEDA;       /*!< Reserved */       
+  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
+  __IO uint16_t RESERVEDB;       /*!< Reserved */       
+  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
+  __IO uint16_t RESERVEDC;       /*!< Reserved */
+  __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
+  __IO uint16_t RESERVEDD;       /*!< Reserved */
+} USB_TypeDef;
+
+/**
+  * @brief Window WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
+#define CCMDATARAM_BASE       ((uint32_t)0x10000000U) /*!< CCM(core coupled memory) data RAM base address in the alias region     */
+#define SRAM_BASE             ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
+#define FMC_BASE              ((uint32_t)0x60000000U) /*!< FMC base address                                                             */
+#define FMC_R_BASE            ((uint32_t)0xA0000000U) /*!< FMC registers base address                                                   */
+
+#define SRAM_BB_BASE          ((uint32_t)0x22000000U) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000U)
+#define AHB3PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000U)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400U)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800U)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000U)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400U)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800U)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00U)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000U)
+#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x00003400U)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800U)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00U)
+#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x00004000U)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400U)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800U)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00U)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000U)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400U)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800U)
+#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
+#define CAN_BASE              (APB1PERIPH_BASE + 0x00006400U)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000U)
+#define DAC1_BASE             (APB1PERIPH_BASE + 0x00007400U)
+#define DAC_BASE               DAC1_BASE
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x00007800U)
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000U)
+#define COMP1_BASE            (APB2PERIPH_BASE + 0x0000001CU)
+#define COMP2_BASE            (APB2PERIPH_BASE + 0x00000020U)
+#define COMP3_BASE            (APB2PERIPH_BASE + 0x00000024U)
+#define COMP4_BASE            (APB2PERIPH_BASE + 0x00000028U)
+#define COMP5_BASE            (APB2PERIPH_BASE + 0x0000002CU)
+#define COMP6_BASE            (APB2PERIPH_BASE + 0x00000030U)
+#define COMP7_BASE            (APB2PERIPH_BASE + 0x00000034U)
+#define COMP_BASE             COMP1_BASE
+#define OPAMP1_BASE           (APB2PERIPH_BASE + 0x00000038U)
+#define OPAMP2_BASE           (APB2PERIPH_BASE + 0x0000003CU)
+#define OPAMP3_BASE           (APB2PERIPH_BASE + 0x00000040U)
+#define OPAMP4_BASE           (APB2PERIPH_BASE + 0x00000044U)
+#define OPAMP_BASE            OPAMP1_BASE
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400U)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x00002C00U)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000U)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x00003400U)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800U)
+#define SPI4_BASE             (APB2PERIPH_BASE + 0x00003C00U)
+#define TIM15_BASE            (APB2PERIPH_BASE + 0x00004000U)
+#define TIM16_BASE            (APB2PERIPH_BASE + 0x00004400U)
+#define TIM17_BASE            (APB2PERIPH_BASE + 0x00004800U)
+#define TIM20_BASE            (APB2PERIPH_BASE + 0x00005000U)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x00000000U)
+#define DMA1_Channel1_BASE    (AHB1PERIPH_BASE + 0x00000008U)
+#define DMA1_Channel2_BASE    (AHB1PERIPH_BASE + 0x0000001CU)
+#define DMA1_Channel3_BASE    (AHB1PERIPH_BASE + 0x00000030U)
+#define DMA1_Channel4_BASE    (AHB1PERIPH_BASE + 0x00000044U)
+#define DMA1_Channel5_BASE    (AHB1PERIPH_BASE + 0x00000058U)
+#define DMA1_Channel6_BASE    (AHB1PERIPH_BASE + 0x0000006CU)
+#define DMA1_Channel7_BASE    (AHB1PERIPH_BASE + 0x00000080U)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x00000400U)
+#define DMA2_Channel1_BASE    (AHB1PERIPH_BASE + 0x00000408U)
+#define DMA2_Channel2_BASE    (AHB1PERIPH_BASE + 0x0000041CU)
+#define DMA2_Channel3_BASE    (AHB1PERIPH_BASE + 0x00000430U)
+#define DMA2_Channel4_BASE    (AHB1PERIPH_BASE + 0x00000444U)
+#define DMA2_Channel5_BASE    (AHB1PERIPH_BASE + 0x00000458U)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x00001000U)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
+#define OB_BASE               ((uint32_t)0x1FFFF800U)         /*!< Flash Option Bytes base address */
+#define FLASHSIZE_BASE        ((uint32_t)0x1FFFF7CCU)         /*!< FLASH Size register base address */
+#define UID_BASE              ((uint32_t)0x1FFFF7ACU)         /*!< Unique device ID register base address */
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x00003000U)
+#define TSC_BASE              (AHB1PERIPH_BASE + 0x00004000U)
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000U)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400U)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800U)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x00000C00U)
+#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x00001000U)
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400U)
+#define GPIOG_BASE            (AHB2PERIPH_BASE + 0x00001800U)
+#define GPIOH_BASE            (AHB2PERIPH_BASE + 0x00001C00U)
+
+/*!< AHB3 peripherals */
+#define ADC1_BASE             (AHB3PERIPH_BASE + 0x00000000U)
+#define ADC2_BASE             (AHB3PERIPH_BASE + 0x00000100U)
+#define ADC1_2_COMMON_BASE    (AHB3PERIPH_BASE + 0x00000300U)
+#define ADC3_BASE             (AHB3PERIPH_BASE + 0x00000400U)
+#define ADC4_BASE             (AHB3PERIPH_BASE + 0x00000500U)
+#define ADC3_4_COMMON_BASE    (AHB3PERIPH_BASE + 0x00000700U)
+
+/*!< FMC Bankx base address */
+#define FMC_BANK1             (FMC_BASE)               /*!< FMC Bank1 base address   */
+#define FMC_BANK1_1           (FMC_BANK1)              /*!< FMC Bank1_1 base address */
+#define FMC_BANK1_2           (FMC_BANK1 + 0x04000000U) /*!< FMC Bank1_2 base address */
+#define FMC_BANK1_3           (FMC_BANK1 + 0x08000000U) /*!< FMC Bank1_3 base address */
+#define FMC_BANK1_4           (FMC_BANK1 + 0x0C000000U) /*!< FMC Bank1_4 base address */
+
+#define FMC_BANK2             (FMC_BASE + 0x10000000U)  /*!< FMC Bank2 base address   */
+#define FMC_BANK3             (FMC_BASE + 0x20000000U)  /*!< FMC Bank3 base address   */
+#define FMC_BANK4             (FMC_BASE + 0x30000000U)  /*!< FMC Bank4 base address   */
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
+#define FMC_Bank2_3_R_BASE    (FMC_R_BASE + 0x0060U)
+#define FMC_Bank4_R_BASE      (FMC_R_BASE + 0x00A0U)
+
+#define DBGMCU_BASE          ((uint32_t)0xE0042000U) /*!< Debug MCU registers base address */
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1               ((CAN_TypeDef *) CAN_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)
+#define COMP3               ((COMP_TypeDef *) COMP3_BASE)
+#define COMP4               ((COMP_TypeDef *) COMP4_BASE)
+#define COMP34_COMMON       ((COMP_Common_TypeDef *) COMP4_BASE)
+#define COMP5               ((COMP_TypeDef *) COMP5_BASE)
+#define COMP6               ((COMP_TypeDef *) COMP6_BASE)
+#define COMP56_COMMON       ((COMP_Common_TypeDef *) COMP6_BASE)
+#define COMP7               ((COMP_TypeDef *) COMP7_BASE)
+/* Legacy define */
+#define COMP                ((COMP_TypeDef *) COMP_BASE)
+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define OPAMP3              ((OPAMP_TypeDef *) OPAMP3_BASE)
+#define OPAMP4              ((OPAMP_TypeDef *) OPAMP4_BASE)
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define TIM20               ((TIM_TypeDef *) TIM20_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC4                ((ADC_TypeDef *) ADC4_BASE)
+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
+#define ADC34_COMMON        ((ADC_Common_TypeDef *) ADC3_4_COMMON_BASE)
+/* Legacy defines */
+#define ADC1_2_COMMON       ADC12_COMMON
+#define ADC3_4_COMMON       ADC34_COMMON
+#define USB                 ((USB_TypeDef *) USB_BASE)
+#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_3         ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
+#define FMC_Bank4           ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter SAR (ADC)               */
+/*                                                                            */
+/******************************************************************************/
+
+#define ADC5_V1_1                                      /*!< ADC IP version */
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ */
+#define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/********************  Bit definition for ADC_ISR register  ********************/
+#define ADC_ISR_ADRDY_Pos              (0U)                                    
+#define ADC_ISR_ADRDY_Msk              (0x1U << ADC_ISR_ADRDY_Pos)             /*!< 0x00000001 */
+#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
+#define ADC_ISR_EOSMP_Pos              (1U)                                    
+#define ADC_ISR_EOSMP_Msk              (0x1U << ADC_ISR_EOSMP_Pos)             /*!< 0x00000002 */
+#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
+#define ADC_ISR_EOC_Pos                (2U)                                    
+#define ADC_ISR_EOC_Msk                (0x1U << ADC_ISR_EOC_Pos)               /*!< 0x00000004 */
+#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
+#define ADC_ISR_EOS_Pos                (3U)                                    
+#define ADC_ISR_EOS_Msk                (0x1U << ADC_ISR_EOS_Pos)               /*!< 0x00000008 */
+#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
+#define ADC_ISR_OVR_Pos                (4U)                                    
+#define ADC_ISR_OVR_Msk                (0x1U << ADC_ISR_OVR_Pos)               /*!< 0x00000010 */
+#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
+#define ADC_ISR_JEOC_Pos               (5U)                                    
+#define ADC_ISR_JEOC_Msk               (0x1U << ADC_ISR_JEOC_Pos)              /*!< 0x00000020 */
+#define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
+#define ADC_ISR_JEOS_Pos               (6U)                                    
+#define ADC_ISR_JEOS_Msk               (0x1U << ADC_ISR_JEOS_Pos)              /*!< 0x00000040 */
+#define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
+#define ADC_ISR_AWD1_Pos               (7U)                                    
+#define ADC_ISR_AWD1_Msk               (0x1U << ADC_ISR_AWD1_Pos)              /*!< 0x00000080 */
+#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos               (8U)                                    
+#define ADC_ISR_AWD2_Msk               (0x1U << ADC_ISR_AWD2_Pos)              /*!< 0x00000100 */
+#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos               (9U)                                    
+#define ADC_ISR_AWD3_Msk               (0x1U << ADC_ISR_AWD3_Pos)              /*!< 0x00000200 */
+#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos              (10U)                                   
+#define ADC_ISR_JQOVF_Msk              (0x1U << ADC_ISR_JQOVF_Pos)             /*!< 0x00000400 */
+#define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
+
+/* Legacy defines */
+#define ADC_ISR_ADRD            (ADC_ISR_ADRDY)
+
+/********************  Bit definition for ADC_IER register  ********************/
+#define ADC_IER_ADRDYIE_Pos            (0U)                                    
+#define ADC_IER_ADRDYIE_Msk            (0x1U << ADC_IER_ADRDYIE_Pos)           /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
+#define ADC_IER_EOSMPIE_Pos            (1U)                                    
+#define ADC_IER_EOSMPIE_Msk            (0x1U << ADC_IER_EOSMPIE_Pos)           /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
+#define ADC_IER_EOCIE_Pos              (2U)                                    
+#define ADC_IER_EOCIE_Msk              (0x1U << ADC_IER_EOCIE_Pos)             /*!< 0x00000004 */
+#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
+#define ADC_IER_EOSIE_Pos              (3U)                                    
+#define ADC_IER_EOSIE_Msk              (0x1U << ADC_IER_EOSIE_Pos)             /*!< 0x00000008 */
+#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_IER_OVRIE_Pos              (4U)                                    
+#define ADC_IER_OVRIE_Msk              (0x1U << ADC_IER_OVRIE_Pos)             /*!< 0x00000010 */
+#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
+#define ADC_IER_JEOCIE_Pos             (5U)                                    
+#define ADC_IER_JEOCIE_Msk             (0x1U << ADC_IER_JEOCIE_Pos)            /*!< 0x00000020 */
+#define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
+#define ADC_IER_JEOSIE_Pos             (6U)                                    
+#define ADC_IER_JEOSIE_Msk             (0x1U << ADC_IER_JEOSIE_Pos)            /*!< 0x00000040 */
+#define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_IER_AWD1IE_Pos             (7U)                                    
+#define ADC_IER_AWD1IE_Msk             (0x1U << ADC_IER_AWD1IE_Pos)            /*!< 0x00000080 */
+#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
+#define ADC_IER_AWD2IE_Pos             (8U)                                    
+#define ADC_IER_AWD2IE_Msk             (0x1U << ADC_IER_AWD2IE_Pos)            /*!< 0x00000100 */
+#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
+#define ADC_IER_AWD3IE_Pos             (9U)                                    
+#define ADC_IER_AWD3IE_Msk             (0x1U << ADC_IER_AWD3IE_Pos)            /*!< 0x00000200 */
+#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
+#define ADC_IER_JQOVFIE_Pos            (10U)                                   
+#define ADC_IER_JQOVFIE_Msk            (0x1U << ADC_IER_JQOVFIE_Pos)           /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
+
+/* Legacy defines */
+#define ADC_IER_RDY             (ADC_IER_ADRDYIE)
+#define ADC_IER_EOSMP           (ADC_IER_EOSMPIE)
+#define ADC_IER_EOC             (ADC_IER_EOCIE)
+#define ADC_IER_EOS             (ADC_IER_EOSIE)
+#define ADC_IER_OVR             (ADC_IER_OVRIE)
+#define ADC_IER_JEOC            (ADC_IER_JEOCIE)
+#define ADC_IER_JEOS            (ADC_IER_JEOSIE)
+#define ADC_IER_AWD1            (ADC_IER_AWD1IE)
+#define ADC_IER_AWD2            (ADC_IER_AWD2IE)
+#define ADC_IER_AWD3            (ADC_IER_AWD3IE)
+#define ADC_IER_JQOVF           (ADC_IER_JQOVFIE)
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN_Pos                (0U)                                    
+#define ADC_CR_ADEN_Msk                (0x1U << ADC_CR_ADEN_Pos)               /*!< 0x00000001 */
+#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
+#define ADC_CR_ADDIS_Pos               (1U)                                    
+#define ADC_CR_ADDIS_Msk               (0x1U << ADC_CR_ADDIS_Pos)              /*!< 0x00000002 */
+#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
+#define ADC_CR_ADSTART_Pos             (2U)                                    
+#define ADC_CR_ADSTART_Msk             (0x1U << ADC_CR_ADSTART_Pos)            /*!< 0x00000004 */
+#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
+#define ADC_CR_JADSTART_Pos            (3U)                                    
+#define ADC_CR_JADSTART_Msk            (0x1U << ADC_CR_JADSTART_Pos)           /*!< 0x00000008 */
+#define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
+#define ADC_CR_ADSTP_Pos               (4U)                                    
+#define ADC_CR_ADSTP_Msk               (0x1U << ADC_CR_ADSTP_Pos)              /*!< 0x00000010 */
+#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
+#define ADC_CR_JADSTP_Pos              (5U)                                    
+#define ADC_CR_JADSTP_Msk              (0x1U << ADC_CR_JADSTP_Pos)             /*!< 0x00000020 */
+#define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
+#define ADC_CR_ADVREGEN_Pos            (28U)                                   
+#define ADC_CR_ADVREGEN_Msk            (0x3U << ADC_CR_ADVREGEN_Pos)           /*!< 0x30000000 */
+#define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
+#define ADC_CR_ADVREGEN_0              (0x1U << ADC_CR_ADVREGEN_Pos)           /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN_1              (0x2U << ADC_CR_ADVREGEN_Pos)           /*!< 0x20000000 */
+#define ADC_CR_ADCALDIF_Pos            (30U)                                   
+#define ADC_CR_ADCALDIF_Msk            (0x1U << ADC_CR_ADCALDIF_Pos)           /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
+#define ADC_CR_ADCAL_Pos               (31U)                                   
+#define ADC_CR_ADCAL_Msk               (0x1U << ADC_CR_ADCAL_Pos)              /*!< 0x80000000 */
+#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
+
+/********************  Bit definition for ADC_CFGR register  ******************/
+#define ADC_CFGR_DMAEN_Pos             (0U)                                    
+#define ADC_CFGR_DMAEN_Msk             (0x1U << ADC_CFGR_DMAEN_Pos)            /*!< 0x00000001 */
+#define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA enable */
+#define ADC_CFGR_DMACFG_Pos            (1U)                                    
+#define ADC_CFGR_DMACFG_Msk            (0x1U << ADC_CFGR_DMACFG_Pos)           /*!< 0x00000002 */
+#define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA configuration */
+
+#define ADC_CFGR_RES_Pos               (3U)                                    
+#define ADC_CFGR_RES_Msk               (0x3U << ADC_CFGR_RES_Pos)              /*!< 0x00000018 */
+#define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
+#define ADC_CFGR_RES_0                 (0x1U << ADC_CFGR_RES_Pos)              /*!< 0x00000008 */
+#define ADC_CFGR_RES_1                 (0x2U << ADC_CFGR_RES_Pos)              /*!< 0x00000010 */
+
+#define ADC_CFGR_ALIGN_Pos             (5U)                                    
+#define ADC_CFGR_ALIGN_Msk             (0x1U << ADC_CFGR_ALIGN_Pos)            /*!< 0x00000020 */
+#define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignement */
+
+#define ADC_CFGR_EXTSEL_Pos            (6U)                                    
+#define ADC_CFGR_EXTSEL_Msk            (0xFU << ADC_CFGR_EXTSEL_Pos)           /*!< 0x000003C0 */
+#define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
+#define ADC_CFGR_EXTSEL_0              (0x1U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000040 */
+#define ADC_CFGR_EXTSEL_1              (0x2U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000080 */
+#define ADC_CFGR_EXTSEL_2              (0x4U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000100 */
+#define ADC_CFGR_EXTSEL_3              (0x8U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000200 */
+
+#define ADC_CFGR_EXTEN_Pos             (10U)                                   
+#define ADC_CFGR_EXTEN_Msk             (0x3U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000C00 */
+#define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
+#define ADC_CFGR_EXTEN_0               (0x1U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000400 */
+#define ADC_CFGR_EXTEN_1               (0x2U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000800 */
+
+#define ADC_CFGR_OVRMOD_Pos            (12U)                                   
+#define ADC_CFGR_OVRMOD_Msk            (0x1U << ADC_CFGR_OVRMOD_Pos)           /*!< 0x00001000 */
+#define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
+#define ADC_CFGR_CONT_Pos              (13U)                                   
+#define ADC_CFGR_CONT_Msk              (0x1U << ADC_CFGR_CONT_Pos)             /*!< 0x00002000 */
+#define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
+#define ADC_CFGR_AUTDLY_Pos            (14U)                                   
+#define ADC_CFGR_AUTDLY_Msk            (0x1U << ADC_CFGR_AUTDLY_Pos)           /*!< 0x00004000 */
+#define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
+
+#define ADC_CFGR_DISCEN_Pos            (16U)                                   
+#define ADC_CFGR_DISCEN_Msk            (0x1U << ADC_CFGR_DISCEN_Pos)           /*!< 0x00010000 */
+#define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
+
+#define ADC_CFGR_DISCNUM_Pos           (17U)                                   
+#define ADC_CFGR_DISCNUM_Msk           (0x7U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x000E0000 */
+#define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC Discontinuous mode channel count */
+#define ADC_CFGR_DISCNUM_0             (0x1U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00020000 */
+#define ADC_CFGR_DISCNUM_1             (0x2U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00040000 */
+#define ADC_CFGR_DISCNUM_2             (0x4U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00080000 */
+
+#define ADC_CFGR_JDISCEN_Pos           (20U)                                   
+#define ADC_CFGR_JDISCEN_Msk           (0x1U << ADC_CFGR_JDISCEN_Pos)          /*!< 0x00100000 */
+#define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC Discontinuous mode on injected channels */
+#define ADC_CFGR_JQM_Pos               (21U)                                   
+#define ADC_CFGR_JQM_Msk               (0x1U << ADC_CFGR_JQM_Pos)              /*!< 0x00200000 */
+#define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
+#define ADC_CFGR_AWD1SGL_Pos           (22U)                                   
+#define ADC_CFGR_AWD1SGL_Msk           (0x1U << ADC_CFGR_AWD1SGL_Pos)          /*!< 0x00400000 */
+#define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CFGR_AWD1EN_Pos            (23U)                                   
+#define ADC_CFGR_AWD1EN_Msk            (0x1U << ADC_CFGR_AWD1EN_Pos)           /*!< 0x00800000 */
+#define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+#define ADC_CFGR_JAWD1EN_Pos           (24U)                                   
+#define ADC_CFGR_JAWD1EN_Msk           (0x1U << ADC_CFGR_JAWD1EN_Pos)          /*!< 0x01000000 */
+#define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CFGR_JAUTO_Pos             (25U)                                   
+#define ADC_CFGR_JAUTO_Msk             (0x1U << ADC_CFGR_JAUTO_Pos)            /*!< 0x02000000 */
+#define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
+
+#define ADC_CFGR_AWD1CH_Pos            (26U)                                   
+#define ADC_CFGR_AWD1CH_Msk            (0x1FU << ADC_CFGR_AWD1CH_Pos)          /*!< 0x7C000000 */
+#define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CFGR_AWD1CH_0              (0x01U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x04000000 */
+#define ADC_CFGR_AWD1CH_1              (0x02U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x08000000 */
+#define ADC_CFGR_AWD1CH_2              (0x04U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x10000000 */
+#define ADC_CFGR_AWD1CH_3              (0x08U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x20000000 */
+#define ADC_CFGR_AWD1CH_4              (0x10U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x40000000 */
+
+/* Legacy defines */
+#define ADC_CFGR_AUTOFF_Pos            (15U)                                   
+#define ADC_CFGR_AUTOFF_Msk            (0x1U << ADC_CFGR_AUTOFF_Pos)           /*!< 0x00008000 */
+#define ADC_CFGR_AUTOFF                ADC_CFGR_AUTOFF_Msk                     /*!< ADC low power auto power off */
+
+/********************  Bit definition for ADC_SMPR1 register  *****************/
+#define ADC_SMPR1_SMP0_Pos             (0U)                                    
+#define ADC_SMPR1_SMP0_Msk             (0x7U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
+#define ADC_SMPR1_SMP0_0               (0x1U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1               (0x2U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2               (0x4U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos             (3U)                                    
+#define ADC_SMPR1_SMP1_Msk             (0x7U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
+#define ADC_SMPR1_SMP1_0               (0x1U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1               (0x2U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2               (0x4U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos             (6U)                                    
+#define ADC_SMPR1_SMP2_Msk             (0x7U << ADC_SMPR1_SMP2_Pos)            /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
+#define ADC_SMPR1_SMP2_0               (0x1U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1               (0x2U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2               (0x4U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos             (9U)                                    
+#define ADC_SMPR1_SMP3_Msk             (0x7U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
+#define ADC_SMPR1_SMP3_0               (0x1U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1               (0x2U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2               (0x4U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos             (12U)                                   
+#define ADC_SMPR1_SMP4_Msk             (0x7U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
+#define ADC_SMPR1_SMP4_0               (0x1U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1               (0x2U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2               (0x4U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos             (15U)                                   
+#define ADC_SMPR1_SMP5_Msk             (0x7U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
+#define ADC_SMPR1_SMP5_0               (0x1U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1               (0x2U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2               (0x4U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos             (18U)                                   
+#define ADC_SMPR1_SMP6_Msk             (0x7U << ADC_SMPR1_SMP6_Pos)            /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
+#define ADC_SMPR1_SMP6_0               (0x1U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1               (0x2U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2               (0x4U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos             (21U)                                   
+#define ADC_SMPR1_SMP7_Msk             (0x7U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
+#define ADC_SMPR1_SMP7_0               (0x1U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1               (0x2U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2               (0x4U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos             (24U)                                   
+#define ADC_SMPR1_SMP8_Msk             (0x7U << ADC_SMPR1_SMP8_Pos)            /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
+#define ADC_SMPR1_SMP8_0               (0x1U << ADC_SMPR1_SMP8_Pos)            /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1               (0x2U << ADC_SMPR1_SMP8_Pos)            /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2               (0x4U << ADC_SMPR1_SMP8_Pos)            /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos             (27U)                                   
+#define ADC_SMPR1_SMP9_Msk             (0x7U << ADC_SMPR1_SMP9_Pos)            /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
+#define ADC_SMPR1_SMP9_0               (0x1U << ADC_SMPR1_SMP9_Pos)            /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1               (0x2U << ADC_SMPR1_SMP9_Pos)            /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2               (0x4U << ADC_SMPR1_SMP9_Pos)            /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_SMPR2 register  *****************/
+#define ADC_SMPR2_SMP10_Pos            (0U)                                    
+#define ADC_SMPR2_SMP10_Msk            (0x7U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
+#define ADC_SMPR2_SMP10_0              (0x1U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1              (0x2U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2              (0x4U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos            (3U)                                    
+#define ADC_SMPR2_SMP11_Msk            (0x7U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
+#define ADC_SMPR2_SMP11_0              (0x1U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1              (0x2U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2              (0x4U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos            (6U)                                    
+#define ADC_SMPR2_SMP12_Msk            (0x7U << ADC_SMPR2_SMP12_Pos)           /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
+#define ADC_SMPR2_SMP12_0              (0x1U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1              (0x2U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2              (0x4U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos            (9U)                                    
+#define ADC_SMPR2_SMP13_Msk            (0x7U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
+#define ADC_SMPR2_SMP13_0              (0x1U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1              (0x2U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2              (0x4U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos            (12U)                                   
+#define ADC_SMPR2_SMP14_Msk            (0x7U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
+#define ADC_SMPR2_SMP14_0              (0x1U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1              (0x2U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2              (0x4U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos            (15U)                                   
+#define ADC_SMPR2_SMP15_Msk            (0x7U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
+#define ADC_SMPR2_SMP15_0              (0x1U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1              (0x2U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2              (0x4U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos            (18U)                                   
+#define ADC_SMPR2_SMP16_Msk            (0x7U << ADC_SMPR2_SMP16_Pos)           /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
+#define ADC_SMPR2_SMP16_0              (0x1U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1              (0x2U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2              (0x4U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos            (21U)                                   
+#define ADC_SMPR2_SMP17_Msk            (0x7U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
+#define ADC_SMPR2_SMP17_0              (0x1U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1              (0x2U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2              (0x4U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos            (24U)                                   
+#define ADC_SMPR2_SMP18_Msk            (0x7U << ADC_SMPR2_SMP18_Pos)           /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
+#define ADC_SMPR2_SMP18_0              (0x1U << ADC_SMPR2_SMP18_Pos)           /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1              (0x2U << ADC_SMPR2_SMP18_Pos)           /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2              (0x4U << ADC_SMPR2_SMP18_Pos)           /*!< 0x04000000 */
+
+/********************  Bit definition for ADC_TR1 register  *******************/
+#define ADC_TR1_LT1_Pos                (0U)                                    
+#define ADC_TR1_LT1_Msk                (0xFFFU << ADC_TR1_LT1_Pos)             /*!< 0x00000FFF */
+#define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
+#define ADC_TR1_LT1_0                  (0x001U << ADC_TR1_LT1_Pos)             /*!< 0x00000001 */
+#define ADC_TR1_LT1_1                  (0x002U << ADC_TR1_LT1_Pos)             /*!< 0x00000002 */
+#define ADC_TR1_LT1_2                  (0x004U << ADC_TR1_LT1_Pos)             /*!< 0x00000004 */
+#define ADC_TR1_LT1_3                  (0x008U << ADC_TR1_LT1_Pos)             /*!< 0x00000008 */
+#define ADC_TR1_LT1_4                  (0x010U << ADC_TR1_LT1_Pos)             /*!< 0x00000010 */
+#define ADC_TR1_LT1_5                  (0x020U << ADC_TR1_LT1_Pos)             /*!< 0x00000020 */
+#define ADC_TR1_LT1_6                  (0x040U << ADC_TR1_LT1_Pos)             /*!< 0x00000040 */
+#define ADC_TR1_LT1_7                  (0x080U << ADC_TR1_LT1_Pos)             /*!< 0x00000080 */
+#define ADC_TR1_LT1_8                  (0x100U << ADC_TR1_LT1_Pos)             /*!< 0x00000100 */
+#define ADC_TR1_LT1_9                  (0x200U << ADC_TR1_LT1_Pos)             /*!< 0x00000200 */
+#define ADC_TR1_LT1_10                 (0x400U << ADC_TR1_LT1_Pos)             /*!< 0x00000400 */
+#define ADC_TR1_LT1_11                 (0x800U << ADC_TR1_LT1_Pos)             /*!< 0x00000800 */
+
+#define ADC_TR1_HT1_Pos                (16U)                                   
+#define ADC_TR1_HT1_Msk                (0xFFFU << ADC_TR1_HT1_Pos)             /*!< 0x0FFF0000 */
+#define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */
+#define ADC_TR1_HT1_0                  (0x001U << ADC_TR1_HT1_Pos)             /*!< 0x00010000 */
+#define ADC_TR1_HT1_1                  (0x002U << ADC_TR1_HT1_Pos)             /*!< 0x00020000 */
+#define ADC_TR1_HT1_2                  (0x004U << ADC_TR1_HT1_Pos)             /*!< 0x00040000 */
+#define ADC_TR1_HT1_3                  (0x008U << ADC_TR1_HT1_Pos)             /*!< 0x00080000 */
+#define ADC_TR1_HT1_4                  (0x010U << ADC_TR1_HT1_Pos)             /*!< 0x00100000 */
+#define ADC_TR1_HT1_5                  (0x020U << ADC_TR1_HT1_Pos)             /*!< 0x00200000 */
+#define ADC_TR1_HT1_6                  (0x040U << ADC_TR1_HT1_Pos)             /*!< 0x00400000 */
+#define ADC_TR1_HT1_7                  (0x080U << ADC_TR1_HT1_Pos)             /*!< 0x00800000 */
+#define ADC_TR1_HT1_8                  (0x100U << ADC_TR1_HT1_Pos)             /*!< 0x01000000 */
+#define ADC_TR1_HT1_9                  (0x200U << ADC_TR1_HT1_Pos)             /*!< 0x02000000 */
+#define ADC_TR1_HT1_10                 (0x400U << ADC_TR1_HT1_Pos)             /*!< 0x04000000 */
+#define ADC_TR1_HT1_11                 (0x800U << ADC_TR1_HT1_Pos)             /*!< 0x08000000 */
+
+/********************  Bit definition for ADC_TR2 register  *******************/
+#define ADC_TR2_LT2_Pos                (0U)                                    
+#define ADC_TR2_LT2_Msk                (0xFFU << ADC_TR2_LT2_Pos)              /*!< 0x000000FF */
+#define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
+#define ADC_TR2_LT2_0                  (0x01U << ADC_TR2_LT2_Pos)              /*!< 0x00000001 */
+#define ADC_TR2_LT2_1                  (0x02U << ADC_TR2_LT2_Pos)              /*!< 0x00000002 */
+#define ADC_TR2_LT2_2                  (0x04U << ADC_TR2_LT2_Pos)              /*!< 0x00000004 */
+#define ADC_TR2_LT2_3                  (0x08U << ADC_TR2_LT2_Pos)              /*!< 0x00000008 */
+#define ADC_TR2_LT2_4                  (0x10U << ADC_TR2_LT2_Pos)              /*!< 0x00000010 */
+#define ADC_TR2_LT2_5                  (0x20U << ADC_TR2_LT2_Pos)              /*!< 0x00000020 */
+#define ADC_TR2_LT2_6                  (0x40U << ADC_TR2_LT2_Pos)              /*!< 0x00000040 */
+#define ADC_TR2_LT2_7                  (0x80U << ADC_TR2_LT2_Pos)              /*!< 0x00000080 */
+
+#define ADC_TR2_HT2_Pos                (16U)                                   
+#define ADC_TR2_HT2_Msk                (0xFFU << ADC_TR2_HT2_Pos)              /*!< 0x00FF0000 */
+#define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
+#define ADC_TR2_HT2_0                  (0x01U << ADC_TR2_HT2_Pos)              /*!< 0x00010000 */
+#define ADC_TR2_HT2_1                  (0x02U << ADC_TR2_HT2_Pos)              /*!< 0x00020000 */
+#define ADC_TR2_HT2_2                  (0x04U << ADC_TR2_HT2_Pos)              /*!< 0x00040000 */
+#define ADC_TR2_HT2_3                  (0x08U << ADC_TR2_HT2_Pos)              /*!< 0x00080000 */
+#define ADC_TR2_HT2_4                  (0x10U << ADC_TR2_HT2_Pos)              /*!< 0x00100000 */
+#define ADC_TR2_HT2_5                  (0x20U << ADC_TR2_HT2_Pos)              /*!< 0x00200000 */
+#define ADC_TR2_HT2_6                  (0x40U << ADC_TR2_HT2_Pos)              /*!< 0x00400000 */
+#define ADC_TR2_HT2_7                  (0x80U << ADC_TR2_HT2_Pos)              /*!< 0x00800000 */
+
+/********************  Bit definition for ADC_TR3 register  *******************/
+#define ADC_TR3_LT3_Pos                (0U)                                    
+#define ADC_TR3_LT3_Msk                (0xFFU << ADC_TR3_LT3_Pos)              /*!< 0x000000FF */
+#define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
+#define ADC_TR3_LT3_0                  (0x01U << ADC_TR3_LT3_Pos)              /*!< 0x00000001 */
+#define ADC_TR3_LT3_1                  (0x02U << ADC_TR3_LT3_Pos)              /*!< 0x00000002 */
+#define ADC_TR3_LT3_2                  (0x04U << ADC_TR3_LT3_Pos)              /*!< 0x00000004 */
+#define ADC_TR3_LT3_3                  (0x08U << ADC_TR3_LT3_Pos)              /*!< 0x00000008 */
+#define ADC_TR3_LT3_4                  (0x10U << ADC_TR3_LT3_Pos)              /*!< 0x00000010 */
+#define ADC_TR3_LT3_5                  (0x20U << ADC_TR3_LT3_Pos)              /*!< 0x00000020 */
+#define ADC_TR3_LT3_6                  (0x40U << ADC_TR3_LT3_Pos)              /*!< 0x00000040 */
+#define ADC_TR3_LT3_7                  (0x80U << ADC_TR3_LT3_Pos)              /*!< 0x00000080 */
+
+#define ADC_TR3_HT3_Pos                (16U)                                   
+#define ADC_TR3_HT3_Msk                (0xFFU << ADC_TR3_HT3_Pos)              /*!< 0x00FF0000 */
+#define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
+#define ADC_TR3_HT3_0                  (0x01U << ADC_TR3_HT3_Pos)              /*!< 0x00010000 */
+#define ADC_TR3_HT3_1                  (0x02U << ADC_TR3_HT3_Pos)              /*!< 0x00020000 */
+#define ADC_TR3_HT3_2                  (0x04U << ADC_TR3_HT3_Pos)              /*!< 0x00040000 */
+#define ADC_TR3_HT3_3                  (0x08U << ADC_TR3_HT3_Pos)              /*!< 0x00080000 */
+#define ADC_TR3_HT3_4                  (0x10U << ADC_TR3_HT3_Pos)              /*!< 0x00100000 */
+#define ADC_TR3_HT3_5                  (0x20U << ADC_TR3_HT3_Pos)              /*!< 0x00200000 */
+#define ADC_TR3_HT3_6                  (0x40U << ADC_TR3_HT3_Pos)              /*!< 0x00400000 */
+#define ADC_TR3_HT3_7                  (0x80U << ADC_TR3_HT3_Pos)              /*!< 0x00800000 */
+
+/********************  Bit definition for ADC_SQR1 register  ******************/
+#define ADC_SQR1_L_Pos                 (0U)                                    
+#define ADC_SQR1_L_Msk                 (0xFU << ADC_SQR1_L_Pos)                /*!< 0x0000000F */
+#define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0                   (0x1U << ADC_SQR1_L_Pos)                /*!< 0x00000001 */
+#define ADC_SQR1_L_1                   (0x2U << ADC_SQR1_L_Pos)                /*!< 0x00000002 */
+#define ADC_SQR1_L_2                   (0x4U << ADC_SQR1_L_Pos)                /*!< 0x00000004 */
+#define ADC_SQR1_L_3                   (0x8U << ADC_SQR1_L_Pos)                /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos               (6U)                                    
+#define ADC_SQR1_SQ1_Msk               (0x1FU << ADC_SQR1_SQ1_Pos)             /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR1_SQ1_0                 (0x01U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1                 (0x02U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2                 (0x04U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3                 (0x08U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4                 (0x10U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos               (12U)                                   
+#define ADC_SQR1_SQ2_Msk               (0x1FU << ADC_SQR1_SQ2_Pos)             /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR1_SQ2_0                 (0x01U << ADC_SQR1_SQ2_Pos)             /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1                 (0x02U << ADC_SQR1_SQ2_Pos)             /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2                 (0x04U << ADC_SQR1_SQ2_Pos)             /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3                 (0x08U << ADC_SQR1_SQ2_Pos)             /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4                 (0x10U << ADC_SQR1_SQ2_Pos)             /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos               (18U)                                   
+#define ADC_SQR1_SQ3_Msk               (0x1FU << ADC_SQR1_SQ3_Pos)             /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR1_SQ3_0                 (0x01U << ADC_SQR1_SQ3_Pos)             /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1                 (0x02U << ADC_SQR1_SQ3_Pos)             /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2                 (0x04U << ADC_SQR1_SQ3_Pos)             /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3                 (0x08U << ADC_SQR1_SQ3_Pos)             /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4                 (0x10U << ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos               (24U)                                   
+#define ADC_SQR1_SQ4_Msk               (0x1FU << ADC_SQR1_SQ4_Pos)             /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR1_SQ4_0                 (0x01U << ADC_SQR1_SQ4_Pos)             /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1                 (0x02U << ADC_SQR1_SQ4_Pos)             /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2                 (0x04U << ADC_SQR1_SQ4_Pos)             /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3                 (0x08U << ADC_SQR1_SQ4_Pos)             /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4                 (0x10U << ADC_SQR1_SQ4_Pos)             /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR2 register  ******************/
+#define ADC_SQR2_SQ5_Pos               (0U)                                    
+#define ADC_SQR2_SQ5_Msk               (0x1FU << ADC_SQR2_SQ5_Pos)             /*!< 0x0000001F */
+#define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR2_SQ5_0                 (0x01U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1                 (0x02U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2                 (0x04U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3                 (0x08U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4                 (0x10U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos               (6U)                                    
+#define ADC_SQR2_SQ6_Msk               (0x1FU << ADC_SQR2_SQ6_Pos)             /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR2_SQ6_0                 (0x01U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1                 (0x02U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2                 (0x04U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3                 (0x08U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4                 (0x10U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos               (12U)                                   
+#define ADC_SQR2_SQ7_Msk               (0x1FU << ADC_SQR2_SQ7_Pos)             /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0                 (0x01U << ADC_SQR2_SQ7_Pos)             /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1                 (0x02U << ADC_SQR2_SQ7_Pos)             /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2                 (0x04U << ADC_SQR2_SQ7_Pos)             /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3                 (0x08U << ADC_SQR2_SQ7_Pos)             /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4                 (0x10U << ADC_SQR2_SQ7_Pos)             /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos               (18U)                                   
+#define ADC_SQR2_SQ8_Msk               (0x1FU << ADC_SQR2_SQ8_Pos)             /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0                 (0x01U << ADC_SQR2_SQ8_Pos)             /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1                 (0x02U << ADC_SQR2_SQ8_Pos)             /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2                 (0x04U << ADC_SQR2_SQ8_Pos)             /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3                 (0x08U << ADC_SQR2_SQ8_Pos)             /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4                 (0x10U << ADC_SQR2_SQ8_Pos)             /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos               (24U)                                   
+#define ADC_SQR2_SQ9_Msk               (0x1FU << ADC_SQR2_SQ9_Pos)             /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0                 (0x01U << ADC_SQR2_SQ9_Pos)             /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1                 (0x02U << ADC_SQR2_SQ9_Pos)             /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2                 (0x04U << ADC_SQR2_SQ9_Pos)             /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3                 (0x08U << ADC_SQR2_SQ9_Pos)             /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4                 (0x10U << ADC_SQR2_SQ9_Pos)             /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR3 register  ******************/
+#define ADC_SQR3_SQ10_Pos              (0U)                                    
+#define ADC_SQR3_SQ10_Msk              (0x1FU << ADC_SQR3_SQ10_Pos)            /*!< 0x0000001F */
+#define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR3_SQ10_0                (0x01U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1                (0x02U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2                (0x04U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3                (0x08U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4                (0x10U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos              (6U)                                    
+#define ADC_SQR3_SQ11_Msk              (0x1FU << ADC_SQR3_SQ11_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
+#define ADC_SQR3_SQ11_0                (0x01U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1                (0x02U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2                (0x04U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3                (0x08U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4                (0x10U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos              (12U)                                   
+#define ADC_SQR3_SQ12_Msk              (0x1FU << ADC_SQR3_SQ12_Pos)            /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR3_SQ12_0                (0x01U << ADC_SQR3_SQ12_Pos)            /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1                (0x02U << ADC_SQR3_SQ12_Pos)            /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2                (0x04U << ADC_SQR3_SQ12_Pos)            /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3                (0x08U << ADC_SQR3_SQ12_Pos)            /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4                (0x10U << ADC_SQR3_SQ12_Pos)            /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos              (18U)                                   
+#define ADC_SQR3_SQ13_Msk              (0x1FU << ADC_SQR3_SQ13_Pos)            /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR3_SQ13_0                (0x01U << ADC_SQR3_SQ13_Pos)            /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1                (0x02U << ADC_SQR3_SQ13_Pos)            /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2                (0x04U << ADC_SQR3_SQ13_Pos)            /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3                (0x08U << ADC_SQR3_SQ13_Pos)            /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4                (0x10U << ADC_SQR3_SQ13_Pos)            /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos              (24U)                                   
+#define ADC_SQR3_SQ14_Msk              (0x1FU << ADC_SQR3_SQ14_Pos)            /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR3_SQ14_0                (0x01U << ADC_SQR3_SQ14_Pos)            /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1                (0x02U << ADC_SQR3_SQ14_Pos)            /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2                (0x04U << ADC_SQR3_SQ14_Pos)            /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3                (0x08U << ADC_SQR3_SQ14_Pos)            /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4                (0x10U << ADC_SQR3_SQ14_Pos)            /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR4 register  ******************/
+#define ADC_SQR4_SQ15_Pos              (0U)                                    
+#define ADC_SQR4_SQ15_Msk              (0x1FU << ADC_SQR4_SQ15_Pos)            /*!< 0x0000001F */
+#define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR4_SQ15_0                (0x01U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1                (0x02U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2                (0x04U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3                (0x08U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4                (0x10U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos              (6U)                                    
+#define ADC_SQR4_SQ16_Msk              (0x1FU << ADC_SQR4_SQ16_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR4_SQ16_0                (0x01U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1                (0x02U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2                (0x04U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3                (0x08U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4                (0x10U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000400 */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA_Pos               (0U)                                    
+#define ADC_DR_RDATA_Msk               (0xFFFFU << ADC_DR_RDATA_Pos)           /*!< 0x0000FFFF */
+#define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
+#define ADC_DR_RDATA_0                 (0x0001U << ADC_DR_RDATA_Pos)           /*!< 0x00000001 */
+#define ADC_DR_RDATA_1                 (0x0002U << ADC_DR_RDATA_Pos)           /*!< 0x00000002 */
+#define ADC_DR_RDATA_2                 (0x0004U << ADC_DR_RDATA_Pos)           /*!< 0x00000004 */
+#define ADC_DR_RDATA_3                 (0x0008U << ADC_DR_RDATA_Pos)           /*!< 0x00000008 */
+#define ADC_DR_RDATA_4                 (0x0010U << ADC_DR_RDATA_Pos)           /*!< 0x00000010 */
+#define ADC_DR_RDATA_5                 (0x0020U << ADC_DR_RDATA_Pos)           /*!< 0x00000020 */
+#define ADC_DR_RDATA_6                 (0x0040U << ADC_DR_RDATA_Pos)           /*!< 0x00000040 */
+#define ADC_DR_RDATA_7                 (0x0080U << ADC_DR_RDATA_Pos)           /*!< 0x00000080 */
+#define ADC_DR_RDATA_8                 (0x0100U << ADC_DR_RDATA_Pos)           /*!< 0x00000100 */
+#define ADC_DR_RDATA_9                 (0x0200U << ADC_DR_RDATA_Pos)           /*!< 0x00000200 */
+#define ADC_DR_RDATA_10                (0x0400U << ADC_DR_RDATA_Pos)           /*!< 0x00000400 */
+#define ADC_DR_RDATA_11                (0x0800U << ADC_DR_RDATA_Pos)           /*!< 0x00000800 */
+#define ADC_DR_RDATA_12                (0x1000U << ADC_DR_RDATA_Pos)           /*!< 0x00001000 */
+#define ADC_DR_RDATA_13                (0x2000U << ADC_DR_RDATA_Pos)           /*!< 0x00002000 */
+#define ADC_DR_RDATA_14                (0x4000U << ADC_DR_RDATA_Pos)           /*!< 0x00004000 */
+#define ADC_DR_RDATA_15                (0x8000U << ADC_DR_RDATA_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JSQR register  ******************/
+#define ADC_JSQR_JL_Pos                (0U)                                    
+#define ADC_JSQR_JL_Msk                (0x3U << ADC_JSQR_JL_Pos)               /*!< 0x00000003 */
+#define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0                  (0x1U << ADC_JSQR_JL_Pos)               /*!< 0x00000001 */
+#define ADC_JSQR_JL_1                  (0x2U << ADC_JSQR_JL_Pos)               /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos           (2U)                                    
+#define ADC_JSQR_JEXTSEL_Msk           (0xFU << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x0000003C */
+#define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
+#define ADC_JSQR_JEXTSEL_0             (0x1U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1             (0x2U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2             (0x4U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3             (0x8U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000020 */
+
+#define ADC_JSQR_JEXTEN_Pos            (6U)                                    
+#define ADC_JSQR_JEXTEN_Msk            (0x3U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x000000C0 */
+#define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
+#define ADC_JSQR_JEXTEN_0              (0x1U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000040 */
+#define ADC_JSQR_JEXTEN_1              (0x2U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000080 */
+
+#define ADC_JSQR_JSQ1_Pos              (8U)                                    
+#define ADC_JSQR_JSQ1_Msk              (0x1FU << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001F00 */
+#define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0                (0x01U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000100 */
+#define ADC_JSQR_JSQ1_1                (0x02U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_2                (0x04U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_3                (0x08U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_4                (0x10U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001000 */
+
+#define ADC_JSQR_JSQ2_Pos              (14U)                                   
+#define ADC_JSQR_JSQ2_Msk              (0x1FU << ADC_JSQR_JSQ2_Pos)            /*!< 0x0007C000 */
+#define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0                (0x01U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00004000 */
+#define ADC_JSQR_JSQ2_1                (0x02U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_2                (0x04U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_3                (0x08U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_4                (0x10U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00040000 */
+
+#define ADC_JSQR_JSQ3_Pos              (20U)                                   
+#define ADC_JSQR_JSQ3_Msk              (0x1FU << ADC_JSQR_JSQ3_Pos)            /*!< 0x01F00000 */
+#define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0                (0x01U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00100000 */
+#define ADC_JSQR_JSQ3_1                (0x02U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_2                (0x04U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_3                (0x08U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_4                (0x10U << ADC_JSQR_JSQ3_Pos)            /*!< 0x01000000 */
+
+#define ADC_JSQR_JSQ4_Pos              (26U)                                   
+#define ADC_JSQR_JSQ4_Msk              (0x1FU << ADC_JSQR_JSQ4_Pos)            /*!< 0x7C000000 */
+#define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0                (0x01U << ADC_JSQR_JSQ4_Pos)            /*!< 0x04000000 */
+#define ADC_JSQR_JSQ4_1                (0x02U << ADC_JSQR_JSQ4_Pos)            /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_2                (0x04U << ADC_JSQR_JSQ4_Pos)            /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_3                (0x08U << ADC_JSQR_JSQ4_Pos)            /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_4                (0x10U << ADC_JSQR_JSQ4_Pos)            /*!< 0x40000000 */
+
+
+/********************  Bit definition for ADC_OFR1 register  ******************/
+#define ADC_OFR1_OFFSET1_Pos           (0U)                                    
+#define ADC_OFR1_OFFSET1_Msk           (0xFFFU << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
+#define ADC_OFR1_OFFSET1_0             (0x001U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1             (0x002U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2             (0x004U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3             (0x008U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4             (0x010U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5             (0x020U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6             (0x040U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7             (0x080U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8             (0x100U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9             (0x200U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10            (0x400U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11            (0x800U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR1_OFFSET1_CH_Pos        (26U)                                   
+#define ADC_OFR1_OFFSET1_CH_Msk        (0x1FU << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
+#define ADC_OFR1_OFFSET1_CH_0          (0x01U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1          (0x02U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2          (0x04U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3          (0x08U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4          (0x10U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR1_OFFSET1_EN_Pos        (31U)                                   
+#define ADC_OFR1_OFFSET1_EN_Msk        (0x1U << ADC_OFR1_OFFSET1_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
+
+/********************  Bit definition for ADC_OFR2 register  ******************/
+#define ADC_OFR2_OFFSET2_Pos           (0U)                                    
+#define ADC_OFR2_OFFSET2_Msk           (0xFFFU << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
+#define ADC_OFR2_OFFSET2_0             (0x001U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1             (0x002U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2             (0x004U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3             (0x008U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4             (0x010U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5             (0x020U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6             (0x040U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7             (0x080U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8             (0x100U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9             (0x200U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10            (0x400U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11            (0x800U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR2_OFFSET2_CH_Pos        (26U)                                   
+#define ADC_OFR2_OFFSET2_CH_Msk        (0x1FU << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
+#define ADC_OFR2_OFFSET2_CH_0          (0x01U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1          (0x02U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2          (0x04U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3          (0x08U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4          (0x10U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR2_OFFSET2_EN_Pos        (31U)                                   
+#define ADC_OFR2_OFFSET2_EN_Msk        (0x1U << ADC_OFR2_OFFSET2_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
+
+/********************  Bit definition for ADC_OFR3 register  ******************/
+#define ADC_OFR3_OFFSET3_Pos           (0U)                                    
+#define ADC_OFR3_OFFSET3_Msk           (0xFFFU << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
+#define ADC_OFR3_OFFSET3_0             (0x001U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1             (0x002U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2             (0x004U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3             (0x008U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4             (0x010U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5             (0x020U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6             (0x040U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7             (0x080U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8             (0x100U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9             (0x200U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10            (0x400U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11            (0x800U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR3_OFFSET3_CH_Pos        (26U)                                   
+#define ADC_OFR3_OFFSET3_CH_Msk        (0x1FU << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
+#define ADC_OFR3_OFFSET3_CH_0          (0x01U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1          (0x02U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2          (0x04U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3          (0x08U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4          (0x10U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR3_OFFSET3_EN_Pos        (31U)                                   
+#define ADC_OFR3_OFFSET3_EN_Msk        (0x1U << ADC_OFR3_OFFSET3_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
+
+/********************  Bit definition for ADC_OFR4 register  ******************/
+#define ADC_OFR4_OFFSET4_Pos           (0U)                                    
+#define ADC_OFR4_OFFSET4_Msk           (0xFFFU << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
+#define ADC_OFR4_OFFSET4_0             (0x001U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1             (0x002U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2             (0x004U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3             (0x008U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4             (0x010U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5             (0x020U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6             (0x040U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7             (0x080U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8             (0x100U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9             (0x200U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10            (0x400U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11            (0x800U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR4_OFFSET4_CH_Pos        (26U)                                   
+#define ADC_OFR4_OFFSET4_CH_Msk        (0x1FU << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
+#define ADC_OFR4_OFFSET4_CH_0          (0x01U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1          (0x02U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2          (0x04U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3          (0x08U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4          (0x10U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR4_OFFSET4_EN_Pos        (31U)                                   
+#define ADC_OFR4_OFFSET4_EN_Msk        (0x1U << ADC_OFR4_OFFSET4_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
+
+/********************  Bit definition for ADC_JDR1 register  ******************/
+#define ADC_JDR1_JDATA_Pos             (0U)                                    
+#define ADC_JDR1_JDATA_Msk             (0xFFFFU << ADC_JDR1_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
+#define ADC_JDR1_JDATA_0               (0x0001U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1               (0x0002U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2               (0x0004U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3               (0x0008U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4               (0x0010U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5               (0x0020U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6               (0x0040U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7               (0x0080U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8               (0x0100U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9               (0x0200U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10              (0x0400U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11              (0x0800U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12              (0x1000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13              (0x2000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14              (0x4000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15              (0x8000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR2 register  ******************/
+#define ADC_JDR2_JDATA_Pos             (0U)                                    
+#define ADC_JDR2_JDATA_Msk             (0xFFFFU << ADC_JDR2_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
+#define ADC_JDR2_JDATA_0               (0x0001U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1               (0x0002U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2               (0x0004U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3               (0x0008U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4               (0x0010U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5               (0x0020U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6               (0x0040U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7               (0x0080U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8               (0x0100U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9               (0x0200U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10              (0x0400U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11              (0x0800U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12              (0x1000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13              (0x2000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14              (0x4000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15              (0x8000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR3 register  ******************/
+#define ADC_JDR3_JDATA_Pos             (0U)                                    
+#define ADC_JDR3_JDATA_Msk             (0xFFFFU << ADC_JDR3_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
+#define ADC_JDR3_JDATA_0               (0x0001U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1               (0x0002U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2               (0x0004U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3               (0x0008U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4               (0x0010U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5               (0x0020U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6               (0x0040U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7               (0x0080U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8               (0x0100U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9               (0x0200U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10              (0x0400U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11              (0x0800U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12              (0x1000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13              (0x2000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14              (0x4000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15              (0x8000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR4 register  ******************/
+#define ADC_JDR4_JDATA_Pos             (0U)                                    
+#define ADC_JDR4_JDATA_Msk             (0xFFFFU << ADC_JDR4_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
+#define ADC_JDR4_JDATA_0               (0x0001U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1               (0x0002U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2               (0x0004U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3               (0x0008U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4               (0x0010U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5               (0x0020U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6               (0x0040U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7               (0x0080U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8               (0x0100U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9               (0x0200U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10              (0x0400U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11              (0x0800U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12              (0x1000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13              (0x2000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14              (0x4000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15              (0x8000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_AWD2CR register  ****************/
+#define ADC_AWD2CR_AWD2CH_Pos          (0U)                                    
+#define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x0007FFFF */
+#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
+#define ADC_AWD2CR_AWD2CH_0            (0x00001U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1            (0x00002U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2            (0x00004U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3            (0x00008U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4            (0x00010U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5            (0x00020U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6            (0x00040U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7            (0x00080U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8            (0x00100U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9            (0x00200U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10           (0x00400U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11           (0x00800U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12           (0x01000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13           (0x02000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14           (0x04000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15           (0x08000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16           (0x10000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17           (0x20000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18           (0x40000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_AWD3CR register  ****************/
+#define ADC_AWD3CR_AWD3CH_Pos          (0U)                                    
+#define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x0007FFFF */
+#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
+#define ADC_AWD3CR_AWD3CH_0            (0x00001U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1            (0x00002U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2            (0x00004U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3            (0x00008U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4            (0x00010U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5            (0x00020U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6            (0x00040U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7            (0x00080U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8            (0x00100U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9            (0x00200U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10           (0x00400U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11           (0x00800U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12           (0x01000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13           (0x02000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14           (0x04000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15           (0x08000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16           (0x10000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17           (0x20000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18           (0x40000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_DIFSEL register  ****************/
+#define ADC_DIFSEL_DIFSEL_Pos          (0U)                                    
+#define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x0007FFFF */
+#define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
+#define ADC_DIFSEL_DIFSEL_0            (0x00001U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1            (0x00002U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2            (0x00004U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3            (0x00008U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4            (0x00010U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5            (0x00020U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6            (0x00040U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7            (0x00080U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8            (0x00100U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9            (0x00200U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10           (0x00400U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11           (0x00800U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12           (0x01000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13           (0x02000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14           (0x04000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15           (0x08000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16           (0x10000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17           (0x20000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18           (0x40000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_CALFACT register  ***************/
+#define ADC_CALFACT_CALFACT_S_Pos      (0U)                                    
+#define ADC_CALFACT_CALFACT_S_Msk      (0x7FU << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0        (0x01U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1        (0x02U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2        (0x04U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3        (0x08U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4        (0x10U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5        (0x20U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6        (0x40U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000040 */
+
+#define ADC_CALFACT_CALFACT_D_Pos      (16U)                                   
+#define ADC_CALFACT_CALFACT_D_Msk      (0x7FU << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x007F0000 */
+#define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
+#define ADC_CALFACT_CALFACT_D_0        (0x01U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1        (0x02U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2        (0x04U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3        (0x08U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4        (0x10U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5        (0x20U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6        (0x40U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00400000 */
+
+/*************************  ADC Common registers  *****************************/
+/***************  Bit definition for ADC12_COMMON_CSR register  ***************/
+#define ADC12_CSR_ADRDY_MST_Pos          (0U)                                  
+#define ADC12_CSR_ADRDY_MST_Msk          (0x1U << ADC12_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */
+#define ADC12_CSR_ADRDY_MST              ADC12_CSR_ADRDY_MST_Msk               /*!< Master ADC ready */
+#define ADC12_CSR_ADRDY_EOSMP_MST_Pos    (1U)                                  
+#define ADC12_CSR_ADRDY_EOSMP_MST_Msk    (0x1U << ADC12_CSR_ADRDY_EOSMP_MST_Pos) /*!< 0x00000002 */
+#define ADC12_CSR_ADRDY_EOSMP_MST        ADC12_CSR_ADRDY_EOSMP_MST_Msk         /*!< End of sampling phase flag of the master ADC */
+#define ADC12_CSR_ADRDY_EOC_MST_Pos      (2U)                                  
+#define ADC12_CSR_ADRDY_EOC_MST_Msk      (0x1U << ADC12_CSR_ADRDY_EOC_MST_Pos) /*!< 0x00000004 */
+#define ADC12_CSR_ADRDY_EOC_MST          ADC12_CSR_ADRDY_EOC_MST_Msk           /*!< End of regular conversion of the master ADC */
+#define ADC12_CSR_ADRDY_EOS_MST_Pos      (3U)                                  
+#define ADC12_CSR_ADRDY_EOS_MST_Msk      (0x1U << ADC12_CSR_ADRDY_EOS_MST_Pos) /*!< 0x00000008 */
+#define ADC12_CSR_ADRDY_EOS_MST          ADC12_CSR_ADRDY_EOS_MST_Msk           /*!< End of regular sequence flag of the master ADC */
+#define ADC12_CSR_ADRDY_OVR_MST_Pos      (4U)                                  
+#define ADC12_CSR_ADRDY_OVR_MST_Msk      (0x1U << ADC12_CSR_ADRDY_OVR_MST_Pos) /*!< 0x00000010 */
+#define ADC12_CSR_ADRDY_OVR_MST          ADC12_CSR_ADRDY_OVR_MST_Msk           /*!< Overrun flag of the master ADC */
+#define ADC12_CSR_ADRDY_JEOC_MST_Pos     (5U)                                  
+#define ADC12_CSR_ADRDY_JEOC_MST_Msk     (0x1U << ADC12_CSR_ADRDY_JEOC_MST_Pos) /*!< 0x00000020 */
+#define ADC12_CSR_ADRDY_JEOC_MST         ADC12_CSR_ADRDY_JEOC_MST_Msk          /*!< End of injected conversion of the master ADC */
+#define ADC12_CSR_ADRDY_JEOS_MST_Pos     (6U)                                  
+#define ADC12_CSR_ADRDY_JEOS_MST_Msk     (0x1U << ADC12_CSR_ADRDY_JEOS_MST_Pos) /*!< 0x00000040 */
+#define ADC12_CSR_ADRDY_JEOS_MST         ADC12_CSR_ADRDY_JEOS_MST_Msk          /*!< End of injected sequence flag of the master ADC */
+#define ADC12_CSR_AWD1_MST_Pos           (7U)                                  
+#define ADC12_CSR_AWD1_MST_Msk           (0x1U << ADC12_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */
+#define ADC12_CSR_AWD1_MST               ADC12_CSR_AWD1_MST_Msk                /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC12_CSR_AWD2_MST_Pos           (8U)                                  
+#define ADC12_CSR_AWD2_MST_Msk           (0x1U << ADC12_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */
+#define ADC12_CSR_AWD2_MST               ADC12_CSR_AWD2_MST_Msk                /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC12_CSR_AWD3_MST_Pos           (9U)                                  
+#define ADC12_CSR_AWD3_MST_Msk           (0x1U << ADC12_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */
+#define ADC12_CSR_AWD3_MST               ADC12_CSR_AWD3_MST_Msk                /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC12_CSR_JQOVF_MST_Pos          (10U)                                 
+#define ADC12_CSR_JQOVF_MST_Msk          (0x1U << ADC12_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */
+#define ADC12_CSR_JQOVF_MST              ADC12_CSR_JQOVF_MST_Msk               /*!< Injected context queue overflow flag of the master ADC */
+#define ADC12_CSR_ADRDY_SLV_Pos          (16U)                                 
+#define ADC12_CSR_ADRDY_SLV_Msk          (0x1U << ADC12_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */
+#define ADC12_CSR_ADRDY_SLV              ADC12_CSR_ADRDY_SLV_Msk               /*!< Slave ADC ready */
+#define ADC12_CSR_ADRDY_EOSMP_SLV_Pos    (17U)                                 
+#define ADC12_CSR_ADRDY_EOSMP_SLV_Msk    (0x1U << ADC12_CSR_ADRDY_EOSMP_SLV_Pos) /*!< 0x00020000 */
+#define ADC12_CSR_ADRDY_EOSMP_SLV        ADC12_CSR_ADRDY_EOSMP_SLV_Msk         /*!< End of sampling phase flag of the slave ADC */
+#define ADC12_CSR_ADRDY_EOC_SLV_Pos      (18U)                                 
+#define ADC12_CSR_ADRDY_EOC_SLV_Msk      (0x1U << ADC12_CSR_ADRDY_EOC_SLV_Pos) /*!< 0x00040000 */
+#define ADC12_CSR_ADRDY_EOC_SLV          ADC12_CSR_ADRDY_EOC_SLV_Msk           /*!< End of regular conversion of the slave ADC */
+#define ADC12_CSR_ADRDY_EOS_SLV_Pos      (19U)                                 
+#define ADC12_CSR_ADRDY_EOS_SLV_Msk      (0x1U << ADC12_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */
+#define ADC12_CSR_ADRDY_EOS_SLV          ADC12_CSR_ADRDY_EOS_SLV_Msk           /*!< End of regular sequence flag of the slave ADC */
+#define ADC12_CSR_ADRDY_OVR_SLV_Pos      (20U)                                 
+#define ADC12_CSR_ADRDY_OVR_SLV_Msk      (0x1U << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
+#define ADC12_CSR_ADRDY_OVR_SLV          ADC12_CSR_ADRDY_OVR_SLV_Msk           /*!< Overrun flag of the slave ADC */
+#define ADC12_CSR_ADRDY_JEOC_SLV_Pos     (21U)                                 
+#define ADC12_CSR_ADRDY_JEOC_SLV_Msk     (0x1U << ADC12_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */
+#define ADC12_CSR_ADRDY_JEOC_SLV         ADC12_CSR_ADRDY_JEOC_SLV_Msk          /*!< End of injected conversion of the slave ADC */
+#define ADC12_CSR_ADRDY_JEOS_SLV_Pos     (22U)                                 
+#define ADC12_CSR_ADRDY_JEOS_SLV_Msk     (0x1U << ADC12_CSR_ADRDY_JEOS_SLV_Pos) /*!< 0x00400000 */
+#define ADC12_CSR_ADRDY_JEOS_SLV         ADC12_CSR_ADRDY_JEOS_SLV_Msk          /*!< End of injected sequence flag of the slave ADC */
+#define ADC12_CSR_AWD1_SLV_Pos           (23U)                                 
+#define ADC12_CSR_AWD1_SLV_Msk           (0x1U << ADC12_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */
+#define ADC12_CSR_AWD1_SLV               ADC12_CSR_AWD1_SLV_Msk                /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC12_CSR_AWD2_SLV_Pos           (24U)                                 
+#define ADC12_CSR_AWD2_SLV_Msk           (0x1U << ADC12_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */
+#define ADC12_CSR_AWD2_SLV               ADC12_CSR_AWD2_SLV_Msk                /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC12_CSR_AWD3_SLV_Pos           (25U)                                 
+#define ADC12_CSR_AWD3_SLV_Msk           (0x1U << ADC12_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */
+#define ADC12_CSR_AWD3_SLV               ADC12_CSR_AWD3_SLV_Msk                /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC12_CSR_JQOVF_SLV_Pos          (26U)                                 
+#define ADC12_CSR_JQOVF_SLV_Msk          (0x1U << ADC12_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */
+#define ADC12_CSR_JQOVF_SLV              ADC12_CSR_JQOVF_SLV_Msk               /*!< Injected context queue overflow flag of the slave ADC */
+
+/***************  Bit definition for ADC34_COMMON_CSR register  ***************/
+#define ADC34_CSR_ADRDY_MST_Pos          (0U)                                  
+#define ADC34_CSR_ADRDY_MST_Msk          (0x1U << ADC34_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */
+#define ADC34_CSR_ADRDY_MST              ADC34_CSR_ADRDY_MST_Msk               /*!< Master ADC ready */
+#define ADC34_CSR_ADRDY_EOSMP_MST_Pos    (1U)                                  
+#define ADC34_CSR_ADRDY_EOSMP_MST_Msk    (0x1U << ADC34_CSR_ADRDY_EOSMP_MST_Pos) /*!< 0x00000002 */
+#define ADC34_CSR_ADRDY_EOSMP_MST        ADC34_CSR_ADRDY_EOSMP_MST_Msk         /*!< End of sampling phase flag of the master ADC */
+#define ADC34_CSR_ADRDY_EOC_MST_Pos      (2U)                                  
+#define ADC34_CSR_ADRDY_EOC_MST_Msk      (0x1U << ADC34_CSR_ADRDY_EOC_MST_Pos) /*!< 0x00000004 */
+#define ADC34_CSR_ADRDY_EOC_MST          ADC34_CSR_ADRDY_EOC_MST_Msk           /*!< End of regular conversion of the master ADC */
+#define ADC34_CSR_ADRDY_EOS_MST_Pos      (3U)                                  
+#define ADC34_CSR_ADRDY_EOS_MST_Msk      (0x1U << ADC34_CSR_ADRDY_EOS_MST_Pos) /*!< 0x00000008 */
+#define ADC34_CSR_ADRDY_EOS_MST          ADC34_CSR_ADRDY_EOS_MST_Msk           /*!< End of regular sequence flag of the master ADC */
+#define ADC34_CSR_ADRDY_OVR_MST_Pos      (4U)                                  
+#define ADC34_CSR_ADRDY_OVR_MST_Msk      (0x1U << ADC34_CSR_ADRDY_OVR_MST_Pos) /*!< 0x00000010 */
+#define ADC34_CSR_ADRDY_OVR_MST          ADC34_CSR_ADRDY_OVR_MST_Msk           /*!< Overrun flag of the master ADC */
+#define ADC34_CSR_ADRDY_JEOC_MST_Pos     (5U)                                  
+#define ADC34_CSR_ADRDY_JEOC_MST_Msk     (0x1U << ADC34_CSR_ADRDY_JEOC_MST_Pos) /*!< 0x00000020 */
+#define ADC34_CSR_ADRDY_JEOC_MST         ADC34_CSR_ADRDY_JEOC_MST_Msk          /*!< End of injected conversion of the master ADC */
+#define ADC34_CSR_ADRDY_JEOS_MST_Pos     (6U)                                  
+#define ADC34_CSR_ADRDY_JEOS_MST_Msk     (0x1U << ADC34_CSR_ADRDY_JEOS_MST_Pos) /*!< 0x00000040 */
+#define ADC34_CSR_ADRDY_JEOS_MST         ADC34_CSR_ADRDY_JEOS_MST_Msk          /*!< End of injected sequence flag of the master ADC */
+#define ADC34_CSR_AWD1_MST_Pos           (7U)                                  
+#define ADC34_CSR_AWD1_MST_Msk           (0x1U << ADC34_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */
+#define ADC34_CSR_AWD1_MST               ADC34_CSR_AWD1_MST_Msk                /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC34_CSR_AWD2_MST_Pos           (8U)                                  
+#define ADC34_CSR_AWD2_MST_Msk           (0x1U << ADC34_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */
+#define ADC34_CSR_AWD2_MST               ADC34_CSR_AWD2_MST_Msk                /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC34_CSR_AWD3_MST_Pos           (9U)                                  
+#define ADC34_CSR_AWD3_MST_Msk           (0x1U << ADC34_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */
+#define ADC34_CSR_AWD3_MST               ADC34_CSR_AWD3_MST_Msk                /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC34_CSR_JQOVF_MST_Pos          (10U)                                 
+#define ADC34_CSR_JQOVF_MST_Msk          (0x1U << ADC34_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */
+#define ADC34_CSR_JQOVF_MST              ADC34_CSR_JQOVF_MST_Msk               /*!< Injected context queue overflow flag of the master ADC */
+#define ADC34_CSR_ADRDY_SLV_Pos          (16U)                                 
+#define ADC34_CSR_ADRDY_SLV_Msk          (0x1U << ADC34_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */
+#define ADC34_CSR_ADRDY_SLV              ADC34_CSR_ADRDY_SLV_Msk               /*!< Slave ADC ready */
+#define ADC34_CSR_ADRDY_EOSMP_SLV_Pos    (17U)                                 
+#define ADC34_CSR_ADRDY_EOSMP_SLV_Msk    (0x1U << ADC34_CSR_ADRDY_EOSMP_SLV_Pos) /*!< 0x00020000 */
+#define ADC34_CSR_ADRDY_EOSMP_SLV        ADC34_CSR_ADRDY_EOSMP_SLV_Msk         /*!< End of sampling phase flag of the slave ADC */
+#define ADC34_CSR_ADRDY_EOC_SLV_Pos      (18U)                                 
+#define ADC34_CSR_ADRDY_EOC_SLV_Msk      (0x1U << ADC34_CSR_ADRDY_EOC_SLV_Pos) /*!< 0x00040000 */
+#define ADC34_CSR_ADRDY_EOC_SLV          ADC34_CSR_ADRDY_EOC_SLV_Msk           /*!< End of regular conversion of the slave ADC */
+#define ADC34_CSR_ADRDY_EOS_SLV_Pos      (19U)                                 
+#define ADC34_CSR_ADRDY_EOS_SLV_Msk      (0x1U << ADC34_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */
+#define ADC34_CSR_ADRDY_EOS_SLV          ADC34_CSR_ADRDY_EOS_SLV_Msk           /*!< End of regular sequence flag of the slave ADC */
+#define ADC12_CSR_ADRDY_OVR_SLV_Pos      (20U)                                 
+#define ADC12_CSR_ADRDY_OVR_SLV_Msk      (0x1U << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
+#define ADC12_CSR_ADRDY_OVR_SLV          ADC12_CSR_ADRDY_OVR_SLV_Msk           /*!< Overrun flag of the slave ADC */
+#define ADC34_CSR_ADRDY_JEOC_SLV_Pos     (21U)                                 
+#define ADC34_CSR_ADRDY_JEOC_SLV_Msk     (0x1U << ADC34_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */
+#define ADC34_CSR_ADRDY_JEOC_SLV         ADC34_CSR_ADRDY_JEOC_SLV_Msk          /*!< End of injected conversion of the slave ADC */
+#define ADC34_CSR_ADRDY_JEOS_SLV_Pos     (22U)                                 
+#define ADC34_CSR_ADRDY_JEOS_SLV_Msk     (0x1U << ADC34_CSR_ADRDY_JEOS_SLV_Pos) /*!< 0x00400000 */
+#define ADC34_CSR_ADRDY_JEOS_SLV         ADC34_CSR_ADRDY_JEOS_SLV_Msk          /*!< End of injected sequence flag of the slave ADC */
+#define ADC34_CSR_AWD1_SLV_Pos           (23U)                                 
+#define ADC34_CSR_AWD1_SLV_Msk           (0x1U << ADC34_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */
+#define ADC34_CSR_AWD1_SLV               ADC34_CSR_AWD1_SLV_Msk                /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC34_CSR_AWD2_SLV_Pos           (24U)                                 
+#define ADC34_CSR_AWD2_SLV_Msk           (0x1U << ADC34_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */
+#define ADC34_CSR_AWD2_SLV               ADC34_CSR_AWD2_SLV_Msk                /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC34_CSR_AWD3_SLV_Pos           (25U)                                 
+#define ADC34_CSR_AWD3_SLV_Msk           (0x1U << ADC34_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */
+#define ADC34_CSR_AWD3_SLV               ADC34_CSR_AWD3_SLV_Msk                /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC34_CSR_JQOVF_SLV_Pos          (26U)                                 
+#define ADC34_CSR_JQOVF_SLV_Msk          (0x1U << ADC34_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */
+#define ADC34_CSR_JQOVF_SLV              ADC34_CSR_JQOVF_SLV_Msk               /*!< Injected context queue overflow flag of the slave ADC */
+
+/***************  Bit definition for ADC12_COMMON_CCR register  ***************/
+#define ADC12_CCR_MULTI_Pos              (0U)                                  
+#define ADC12_CCR_MULTI_Msk              (0x1FU << ADC12_CCR_MULTI_Pos)        /*!< 0x0000001F */
+#define ADC12_CCR_MULTI                  ADC12_CCR_MULTI_Msk                   /*!< Multi ADC mode selection */
+#define ADC12_CCR_MULTI_0                (0x01U << ADC12_CCR_MULTI_Pos)        /*!< 0x00000001 */
+#define ADC12_CCR_MULTI_1                (0x02U << ADC12_CCR_MULTI_Pos)        /*!< 0x00000002 */
+#define ADC12_CCR_MULTI_2                (0x04U << ADC12_CCR_MULTI_Pos)        /*!< 0x00000004 */
+#define ADC12_CCR_MULTI_3                (0x08U << ADC12_CCR_MULTI_Pos)        /*!< 0x00000008 */
+#define ADC12_CCR_MULTI_4                (0x10U << ADC12_CCR_MULTI_Pos)        /*!< 0x00000010 */
+#define ADC12_CCR_DELAY_Pos              (8U)                                  
+#define ADC12_CCR_DELAY_Msk              (0xFU << ADC12_CCR_DELAY_Pos)         /*!< 0x00000F00 */
+#define ADC12_CCR_DELAY                  ADC12_CCR_DELAY_Msk                   /*!< Delay between 2 sampling phases */
+#define ADC12_CCR_DELAY_0                (0x1U << ADC12_CCR_DELAY_Pos)         /*!< 0x00000100 */
+#define ADC12_CCR_DELAY_1                (0x2U << ADC12_CCR_DELAY_Pos)         /*!< 0x00000200 */
+#define ADC12_CCR_DELAY_2                (0x4U << ADC12_CCR_DELAY_Pos)         /*!< 0x00000400 */
+#define ADC12_CCR_DELAY_3                (0x8U << ADC12_CCR_DELAY_Pos)         /*!< 0x00000800 */
+#define ADC12_CCR_DMACFG_Pos             (13U)                                 
+#define ADC12_CCR_DMACFG_Msk             (0x1U << ADC12_CCR_DMACFG_Pos)        /*!< 0x00002000 */
+#define ADC12_CCR_DMACFG                 ADC12_CCR_DMACFG_Msk                  /*!< DMA configuration for multi-ADC mode */
+#define ADC12_CCR_MDMA_Pos               (14U)                                 
+#define ADC12_CCR_MDMA_Msk               (0x3U << ADC12_CCR_MDMA_Pos)          /*!< 0x0000C000 */
+#define ADC12_CCR_MDMA                   ADC12_CCR_MDMA_Msk                    /*!< DMA mode for multi-ADC mode */
+#define ADC12_CCR_MDMA_0                 (0x1U << ADC12_CCR_MDMA_Pos)          /*!< 0x00004000 */
+#define ADC12_CCR_MDMA_1                 (0x2U << ADC12_CCR_MDMA_Pos)          /*!< 0x00008000 */
+#define ADC12_CCR_CKMODE_Pos             (16U)                                 
+#define ADC12_CCR_CKMODE_Msk             (0x3U << ADC12_CCR_CKMODE_Pos)        /*!< 0x00030000 */
+#define ADC12_CCR_CKMODE                 ADC12_CCR_CKMODE_Msk                  /*!< ADC clock mode */
+#define ADC12_CCR_CKMODE_0               (0x1U << ADC12_CCR_CKMODE_Pos)        /*!< 0x00010000 */
+#define ADC12_CCR_CKMODE_1               (0x2U << ADC12_CCR_CKMODE_Pos)        /*!< 0x00020000 */
+#define ADC12_CCR_VREFEN_Pos             (22U)                                 
+#define ADC12_CCR_VREFEN_Msk             (0x1U << ADC12_CCR_VREFEN_Pos)        /*!< 0x00400000 */
+#define ADC12_CCR_VREFEN                 ADC12_CCR_VREFEN_Msk                  /*!< VREFINT enable */
+#define ADC12_CCR_TSEN_Pos               (23U)                                 
+#define ADC12_CCR_TSEN_Msk               (0x1U << ADC12_CCR_TSEN_Pos)          /*!< 0x00800000 */
+#define ADC12_CCR_TSEN                   ADC12_CCR_TSEN_Msk                    /*!< Temperature sensor enable */
+#define ADC12_CCR_VBATEN_Pos             (24U)                                 
+#define ADC12_CCR_VBATEN_Msk             (0x1U << ADC12_CCR_VBATEN_Pos)        /*!< 0x01000000 */
+#define ADC12_CCR_VBATEN                 ADC12_CCR_VBATEN_Msk                  /*!< VBAT enable */
+
+/***************  Bit definition for ADC34_COMMON_CCR register  ***************/
+#define ADC34_CCR_MULTI_Pos              (0U)                                  
+#define ADC34_CCR_MULTI_Msk              (0x1FU << ADC34_CCR_MULTI_Pos)        /*!< 0x0000001F */
+#define ADC34_CCR_MULTI                  ADC34_CCR_MULTI_Msk                   /*!< Multi ADC mode selection */
+#define ADC34_CCR_MULTI_0                (0x01U << ADC34_CCR_MULTI_Pos)        /*!< 0x00000001 */
+#define ADC34_CCR_MULTI_1                (0x02U << ADC34_CCR_MULTI_Pos)        /*!< 0x00000002 */
+#define ADC34_CCR_MULTI_2                (0x04U << ADC34_CCR_MULTI_Pos)        /*!< 0x00000004 */
+#define ADC34_CCR_MULTI_3                (0x08U << ADC34_CCR_MULTI_Pos)        /*!< 0x00000008 */
+#define ADC34_CCR_MULTI_4                (0x10U << ADC34_CCR_MULTI_Pos)        /*!< 0x00000010 */
+
+#define ADC34_CCR_DELAY_Pos              (8U)                                  
+#define ADC34_CCR_DELAY_Msk              (0xFU << ADC34_CCR_DELAY_Pos)         /*!< 0x00000F00 */
+#define ADC34_CCR_DELAY                  ADC34_CCR_DELAY_Msk                   /*!< Delay between 2 sampling phases */
+#define ADC34_CCR_DELAY_0                (0x1U << ADC34_CCR_DELAY_Pos)         /*!< 0x00000100 */
+#define ADC34_CCR_DELAY_1                (0x2U << ADC34_CCR_DELAY_Pos)         /*!< 0x00000200 */
+#define ADC34_CCR_DELAY_2                (0x4U << ADC34_CCR_DELAY_Pos)         /*!< 0x00000400 */
+#define ADC34_CCR_DELAY_3                (0x8U << ADC34_CCR_DELAY_Pos)         /*!< 0x00000800 */
+
+#define ADC34_CCR_DMACFG_Pos             (13U)                                 
+#define ADC34_CCR_DMACFG_Msk             (0x1U << ADC34_CCR_DMACFG_Pos)        /*!< 0x00002000 */
+#define ADC34_CCR_DMACFG                 ADC34_CCR_DMACFG_Msk                  /*!< DMA configuration for multi-ADC mode */
+#define ADC34_CCR_MDMA_Pos               (14U)                                 
+#define ADC34_CCR_MDMA_Msk               (0x3U << ADC34_CCR_MDMA_Pos)          /*!< 0x0000C000 */
+#define ADC34_CCR_MDMA                   ADC34_CCR_MDMA_Msk                    /*!< DMA mode for multi-ADC mode */
+#define ADC34_CCR_MDMA_0                 (0x1U << ADC34_CCR_MDMA_Pos)          /*!< 0x00004000 */
+#define ADC34_CCR_MDMA_1                 (0x2U << ADC34_CCR_MDMA_Pos)          /*!< 0x00008000 */
+
+#define ADC34_CCR_CKMODE_Pos             (16U)                                 
+#define ADC34_CCR_CKMODE_Msk             (0x3U << ADC34_CCR_CKMODE_Pos)        /*!< 0x00030000 */
+#define ADC34_CCR_CKMODE                 ADC34_CCR_CKMODE_Msk                  /*!< ADC clock mode */
+#define ADC34_CCR_CKMODE_0               (0x1U << ADC34_CCR_CKMODE_Pos)        /*!< 0x00010000 */
+#define ADC34_CCR_CKMODE_1               (0x2U << ADC34_CCR_CKMODE_Pos)        /*!< 0x00020000 */
+
+#define ADC34_CCR_VREFEN_Pos             (22U)                                 
+#define ADC34_CCR_VREFEN_Msk             (0x1U << ADC34_CCR_VREFEN_Pos)        /*!< 0x00400000 */
+#define ADC34_CCR_VREFEN                 ADC34_CCR_VREFEN_Msk                  /*!< VREFINT enable */
+#define ADC34_CCR_TSEN_Pos               (23U)                                 
+#define ADC34_CCR_TSEN_Msk               (0x1U << ADC34_CCR_TSEN_Pos)          /*!< 0x00800000 */
+#define ADC34_CCR_TSEN                   ADC34_CCR_TSEN_Msk                    /*!< Temperature sensor enable */
+#define ADC34_CCR_VBATEN_Pos             (24U)                                 
+#define ADC34_CCR_VBATEN_Msk             (0x1U << ADC34_CCR_VBATEN_Pos)        /*!< 0x01000000 */
+#define ADC34_CCR_VBATEN                 ADC34_CCR_VBATEN_Msk                  /*!< VBAT enable */
+
+/***************  Bit definition for ADC12_COMMON_CDR register  ***************/
+#define ADC12_CDR_RDATA_MST_Pos          (0U)                                  
+#define ADC12_CDR_RDATA_MST_Msk          (0xFFFFU << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x0000FFFF */
+#define ADC12_CDR_RDATA_MST              ADC12_CDR_RDATA_MST_Msk               /*!< Regular Data of the master ADC */
+#define ADC12_CDR_RDATA_MST_0            (0x0001U << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000001 */
+#define ADC12_CDR_RDATA_MST_1            (0x0002U << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000002 */
+#define ADC12_CDR_RDATA_MST_2            (0x0004U << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000004 */
+#define ADC12_CDR_RDATA_MST_3            (0x0008U << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000008 */
+#define ADC12_CDR_RDATA_MST_4            (0x0010U << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000010 */
+#define ADC12_CDR_RDATA_MST_5            (0x0020U << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000020 */
+#define ADC12_CDR_RDATA_MST_6            (0x0040U << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000040 */
+#define ADC12_CDR_RDATA_MST_7            (0x0080U << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000080 */
+#define ADC12_CDR_RDATA_MST_8            (0x0100U << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000100 */
+#define ADC12_CDR_RDATA_MST_9            (0x0200U << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000200 */
+#define ADC12_CDR_RDATA_MST_10           (0x0400U << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000400 */
+#define ADC12_CDR_RDATA_MST_11           (0x0800U << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000800 */
+#define ADC12_CDR_RDATA_MST_12           (0x1000U << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00001000 */
+#define ADC12_CDR_RDATA_MST_13           (0x2000U << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00002000 */
+#define ADC12_CDR_RDATA_MST_14           (0x4000U << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00004000 */
+#define ADC12_CDR_RDATA_MST_15           (0x8000U << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00008000 */
+
+#define ADC12_CDR_RDATA_SLV_Pos          (16U)                                 
+#define ADC12_CDR_RDATA_SLV_Msk          (0xFFFFU << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0xFFFF0000 */
+#define ADC12_CDR_RDATA_SLV              ADC12_CDR_RDATA_SLV_Msk               /*!< Regular Data of the master ADC */
+#define ADC12_CDR_RDATA_SLV_0            (0x0001U << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00010000 */
+#define ADC12_CDR_RDATA_SLV_1            (0x0002U << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00020000 */
+#define ADC12_CDR_RDATA_SLV_2            (0x0004U << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00040000 */
+#define ADC12_CDR_RDATA_SLV_3            (0x0008U << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00080000 */
+#define ADC12_CDR_RDATA_SLV_4            (0x0010U << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00100000 */
+#define ADC12_CDR_RDATA_SLV_5            (0x0020U << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00200000 */
+#define ADC12_CDR_RDATA_SLV_6            (0x0040U << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00400000 */
+#define ADC12_CDR_RDATA_SLV_7            (0x0080U << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00800000 */
+#define ADC12_CDR_RDATA_SLV_8            (0x0100U << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x01000000 */
+#define ADC12_CDR_RDATA_SLV_9            (0x0200U << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x02000000 */
+#define ADC12_CDR_RDATA_SLV_10           (0x0400U << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x04000000 */
+#define ADC12_CDR_RDATA_SLV_11           (0x0800U << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x08000000 */
+#define ADC12_CDR_RDATA_SLV_12           (0x1000U << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x10000000 */
+#define ADC12_CDR_RDATA_SLV_13           (0x2000U << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x20000000 */
+#define ADC12_CDR_RDATA_SLV_14           (0x4000U << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x40000000 */
+#define ADC12_CDR_RDATA_SLV_15           (0x8000U << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x80000000 */
+
+/***************  Bit definition for ADC34_COMMON_CDR register  ***************/
+#define ADC34_CDR_RDATA_MST_Pos          (0U)                                  
+#define ADC34_CDR_RDATA_MST_Msk          (0xFFFFU << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x0000FFFF */
+#define ADC34_CDR_RDATA_MST              ADC34_CDR_RDATA_MST_Msk               /*!< Regular Data of the master ADC */
+#define ADC34_CDR_RDATA_MST_0            (0x0001U << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000001 */
+#define ADC34_CDR_RDATA_MST_1            (0x0002U << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000002 */
+#define ADC34_CDR_RDATA_MST_2            (0x0004U << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000004 */
+#define ADC34_CDR_RDATA_MST_3            (0x0008U << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000008 */
+#define ADC34_CDR_RDATA_MST_4            (0x0010U << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000010 */
+#define ADC34_CDR_RDATA_MST_5            (0x0020U << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000020 */
+#define ADC34_CDR_RDATA_MST_6            (0x0040U << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000040 */
+#define ADC34_CDR_RDATA_MST_7            (0x0080U << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000080 */
+#define ADC34_CDR_RDATA_MST_8            (0x0100U << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000100 */
+#define ADC34_CDR_RDATA_MST_9            (0x0200U << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000200 */
+#define ADC34_CDR_RDATA_MST_10           (0x0400U << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000400 */
+#define ADC34_CDR_RDATA_MST_11           (0x0800U << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000800 */
+#define ADC34_CDR_RDATA_MST_12           (0x1000U << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00001000 */
+#define ADC34_CDR_RDATA_MST_13           (0x2000U << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00002000 */
+#define ADC34_CDR_RDATA_MST_14           (0x4000U << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00004000 */
+#define ADC34_CDR_RDATA_MST_15           (0x8000U << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00008000 */
+
+#define ADC34_CDR_RDATA_SLV_Pos          (16U)                                 
+#define ADC34_CDR_RDATA_SLV_Msk          (0xFFFFU << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0xFFFF0000 */
+#define ADC34_CDR_RDATA_SLV              ADC34_CDR_RDATA_SLV_Msk               /*!< Regular Data of the master ADC */
+#define ADC34_CDR_RDATA_SLV_0            (0x0001U << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x00010000 */
+#define ADC34_CDR_RDATA_SLV_1            (0x0002U << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x00020000 */
+#define ADC34_CDR_RDATA_SLV_2            (0x0004U << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x00040000 */
+#define ADC34_CDR_RDATA_SLV_3            (0x0008U << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x00080000 */
+#define ADC34_CDR_RDATA_SLV_4            (0x0010U << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x00100000 */
+#define ADC34_CDR_RDATA_SLV_5            (0x0020U << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x00200000 */
+#define ADC34_CDR_RDATA_SLV_6            (0x0040U << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x00400000 */
+#define ADC34_CDR_RDATA_SLV_7            (0x0080U << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x00800000 */
+#define ADC34_CDR_RDATA_SLV_8            (0x0100U << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x01000000 */
+#define ADC34_CDR_RDATA_SLV_9            (0x0200U << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x02000000 */
+#define ADC34_CDR_RDATA_SLV_10           (0x0400U << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x04000000 */
+#define ADC34_CDR_RDATA_SLV_11           (0x0800U << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x08000000 */
+#define ADC34_CDR_RDATA_SLV_12           (0x1000U << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x10000000 */
+#define ADC34_CDR_RDATA_SLV_13           (0x2000U << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x20000000 */
+#define ADC34_CDR_RDATA_SLV_14           (0x4000U << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x40000000 */
+#define ADC34_CDR_RDATA_SLV_15           (0x8000U << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_CSR register  *******************/
+#define ADC_CSR_ADRDY_MST_Pos          (0U)                                    
+#define ADC_CSR_ADRDY_MST_Msk          (0x1U << ADC_CSR_ADRDY_MST_Pos)         /*!< 0x00000001 */
+#define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
+#define ADC_CSR_EOSMP_MST_Pos          (1U)                                    
+#define ADC_CSR_EOSMP_MST_Msk          (0x1U << ADC_CSR_EOSMP_MST_Pos)         /*!< 0x00000002 */
+#define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
+#define ADC_CSR_EOC_MST_Pos            (2U)                                    
+#define ADC_CSR_EOC_MST_Msk            (0x1U << ADC_CSR_EOC_MST_Pos)           /*!< 0x00000004 */
+#define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_MST_Pos            (3U)                                    
+#define ADC_CSR_EOS_MST_Msk            (0x1U << ADC_CSR_EOS_MST_Pos)           /*!< 0x00000008 */
+#define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_MST_Pos            (4U)                                    
+#define ADC_CSR_OVR_MST_Msk            (0x1U << ADC_CSR_OVR_MST_Pos)           /*!< 0x00000010 */
+#define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
+#define ADC_CSR_JEOC_MST_Pos           (5U)                                    
+#define ADC_CSR_JEOC_MST_Msk           (0x1U << ADC_CSR_JEOC_MST_Pos)          /*!< 0x00000020 */
+#define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_MST_Pos           (6U)                                    
+#define ADC_CSR_JEOS_MST_Msk           (0x1U << ADC_CSR_JEOS_MST_Pos)          /*!< 0x00000040 */
+#define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_MST_Pos           (7U)                                    
+#define ADC_CSR_AWD1_MST_Msk           (0x1U << ADC_CSR_AWD1_MST_Pos)          /*!< 0x00000080 */
+#define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
+#define ADC_CSR_AWD2_MST_Pos           (8U)                                    
+#define ADC_CSR_AWD2_MST_Msk           (0x1U << ADC_CSR_AWD2_MST_Pos)          /*!< 0x00000100 */
+#define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
+#define ADC_CSR_AWD3_MST_Pos           (9U)                                    
+#define ADC_CSR_AWD3_MST_Msk           (0x1U << ADC_CSR_AWD3_MST_Pos)          /*!< 0x00000200 */
+#define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
+#define ADC_CSR_JQOVF_MST_Pos          (10U)                                   
+#define ADC_CSR_JQOVF_MST_Msk          (0x1U << ADC_CSR_JQOVF_MST_Pos)         /*!< 0x00000400 */
+#define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
+
+#define ADC_CSR_ADRDY_SLV_Pos          (16U)                                   
+#define ADC_CSR_ADRDY_SLV_Msk          (0x1U << ADC_CSR_ADRDY_SLV_Pos)         /*!< 0x00010000 */
+#define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
+#define ADC_CSR_EOSMP_SLV_Pos          (17U)                                   
+#define ADC_CSR_EOSMP_SLV_Msk          (0x1U << ADC_CSR_EOSMP_SLV_Pos)         /*!< 0x00020000 */
+#define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
+#define ADC_CSR_EOC_SLV_Pos            (18U)                                   
+#define ADC_CSR_EOC_SLV_Msk            (0x1U << ADC_CSR_EOC_SLV_Pos)           /*!< 0x00040000 */
+#define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_SLV_Pos            (19U)                                   
+#define ADC_CSR_EOS_SLV_Msk            (0x1U << ADC_CSR_EOS_SLV_Pos)           /*!< 0x00080000 */
+#define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_SLV_Pos            (20U)                                   
+#define ADC_CSR_OVR_SLV_Msk            (0x1U << ADC_CSR_OVR_SLV_Pos)           /*!< 0x00100000 */
+#define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
+#define ADC_CSR_JEOC_SLV_Pos           (21U)                                   
+#define ADC_CSR_JEOC_SLV_Msk           (0x1U << ADC_CSR_JEOC_SLV_Pos)          /*!< 0x00200000 */
+#define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_SLV_Pos           (22U)                                   
+#define ADC_CSR_JEOS_SLV_Msk           (0x1U << ADC_CSR_JEOS_SLV_Pos)          /*!< 0x00400000 */
+#define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_SLV_Pos           (23U)                                   
+#define ADC_CSR_AWD1_SLV_Msk           (0x1U << ADC_CSR_AWD1_SLV_Pos)          /*!< 0x00800000 */
+#define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
+#define ADC_CSR_AWD2_SLV_Pos           (24U)                                   
+#define ADC_CSR_AWD2_SLV_Msk           (0x1U << ADC_CSR_AWD2_SLV_Pos)          /*!< 0x01000000 */
+#define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
+#define ADC_CSR_AWD3_SLV_Pos           (25U)                                   
+#define ADC_CSR_AWD3_SLV_Msk           (0x1U << ADC_CSR_AWD3_SLV_Pos)          /*!< 0x02000000 */
+#define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
+#define ADC_CSR_JQOVF_SLV_Pos          (26U)                                   
+#define ADC_CSR_JQOVF_SLV_Msk          (0x1U << ADC_CSR_JQOVF_SLV_Pos)         /*!< 0x04000000 */
+#define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
+
+/* Legacy defines */
+#define ADC_CSR_ADRDY_EOSMP_MST   ADC_CSR_EOSMP_MST
+#define ADC_CSR_ADRDY_EOC_MST     ADC_CSR_EOC_MST
+#define ADC_CSR_ADRDY_EOS_MST     ADC_CSR_EOS_MST
+#define ADC_CSR_ADRDY_OVR_MST     ADC_CSR_OVR_MST
+#define ADC_CSR_ADRDY_JEOC_MST    ADC_CSR_JEOC_MST
+#define ADC_CSR_ADRDY_JEOS_MST    ADC_CSR_JEOS_MST
+
+#define ADC_CSR_ADRDY_EOSMP_SLV   ADC_CSR_EOSMP_SLV
+#define ADC_CSR_ADRDY_EOC_SLV     ADC_CSR_EOC_SLV
+#define ADC_CSR_ADRDY_EOS_SLV     ADC_CSR_EOS_SLV
+#define ADC_CSR_ADRDY_OVR_SLV     ADC_CSR_OVR_SLV
+#define ADC_CSR_ADRDY_JEOC_SLV    ADC_CSR_JEOC_SLV
+#define ADC_CSR_ADRDY_JEOS_SLV    ADC_CSR_JEOS_SLV
+
+/********************  Bit definition for ADC_CCR register  *******************/
+#define ADC_CCR_DUAL_Pos               (0U)                                    
+#define ADC_CCR_DUAL_Msk               (0x1FU << ADC_CCR_DUAL_Pos)             /*!< 0x0000001F */
+#define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
+#define ADC_CCR_DUAL_0                 (0x01U << ADC_CCR_DUAL_Pos)             /*!< 0x00000001 */
+#define ADC_CCR_DUAL_1                 (0x02U << ADC_CCR_DUAL_Pos)             /*!< 0x00000002 */
+#define ADC_CCR_DUAL_2                 (0x04U << ADC_CCR_DUAL_Pos)             /*!< 0x00000004 */
+#define ADC_CCR_DUAL_3                 (0x08U << ADC_CCR_DUAL_Pos)             /*!< 0x00000008 */
+#define ADC_CCR_DUAL_4                 (0x10U << ADC_CCR_DUAL_Pos)             /*!< 0x00000010 */
+
+#define ADC_CCR_DELAY_Pos              (8U)                                    
+#define ADC_CCR_DELAY_Msk              (0xFU << ADC_CCR_DELAY_Pos)             /*!< 0x00000F00 */
+#define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0                (0x1U << ADC_CCR_DELAY_Pos)             /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1                (0x2U << ADC_CCR_DELAY_Pos)             /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2                (0x4U << ADC_CCR_DELAY_Pos)             /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3                (0x8U << ADC_CCR_DELAY_Pos)             /*!< 0x00000800 */
+
+#define ADC_CCR_DMACFG_Pos             (13U)                                   
+#define ADC_CCR_DMACFG_Msk             (0x1U << ADC_CCR_DMACFG_Pos)            /*!< 0x00002000 */
+#define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */
+
+#define ADC_CCR_MDMA_Pos               (14U)                                   
+#define ADC_CCR_MDMA_Msk               (0x3U << ADC_CCR_MDMA_Pos)              /*!< 0x0000C000 */
+#define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
+#define ADC_CCR_MDMA_0                 (0x1U << ADC_CCR_MDMA_Pos)              /*!< 0x00004000 */
+#define ADC_CCR_MDMA_1                 (0x2U << ADC_CCR_MDMA_Pos)              /*!< 0x00008000 */
+
+#define ADC_CCR_CKMODE_Pos             (16U)                                   
+#define ADC_CCR_CKMODE_Msk             (0x3U << ADC_CCR_CKMODE_Pos)            /*!< 0x00030000 */
+#define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
+#define ADC_CCR_CKMODE_0               (0x1U << ADC_CCR_CKMODE_Pos)            /*!< 0x00010000 */
+#define ADC_CCR_CKMODE_1               (0x2U << ADC_CCR_CKMODE_Pos)            /*!< 0x00020000 */
+
+#define ADC_CCR_VREFEN_Pos             (22U)                                   
+#define ADC_CCR_VREFEN_Msk             (0x1U << ADC_CCR_VREFEN_Pos)            /*!< 0x00400000 */
+#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
+#define ADC_CCR_TSEN_Pos               (23U)                                   
+#define ADC_CCR_TSEN_Msk               (0x1U << ADC_CCR_TSEN_Pos)              /*!< 0x00800000 */
+#define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos             (24U)                                   
+#define ADC_CCR_VBATEN_Msk             (0x1U << ADC_CCR_VBATEN_Pos)            /*!< 0x01000000 */
+#define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
+
+/* Legacy defines */
+#define ADC_CCR_MULTI           (ADC_CCR_DUAL)
+#define ADC_CCR_MULTI_0         (ADC_CCR_DUAL_0)
+#define ADC_CCR_MULTI_1         (ADC_CCR_DUAL_1)
+#define ADC_CCR_MULTI_2         (ADC_CCR_DUAL_2)
+#define ADC_CCR_MULTI_3         (ADC_CCR_DUAL_3)
+#define ADC_CCR_MULTI_4         (ADC_CCR_DUAL_4)
+
+/********************  Bit definition for ADC_CDR register  *******************/
+#define ADC_CDR_RDATA_MST_Pos          (0U)                                    
+#define ADC_CDR_RDATA_MST_Msk          (0xFFFFU << ADC_CDR_RDATA_MST_Pos)      /*!< 0x0000FFFF */
+#define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
+#define ADC_CDR_RDATA_MST_0            (0x0001U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000001 */
+#define ADC_CDR_RDATA_MST_1            (0x0002U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000002 */
+#define ADC_CDR_RDATA_MST_2            (0x0004U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000004 */
+#define ADC_CDR_RDATA_MST_3            (0x0008U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000008 */
+#define ADC_CDR_RDATA_MST_4            (0x0010U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000010 */
+#define ADC_CDR_RDATA_MST_5            (0x0020U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000020 */
+#define ADC_CDR_RDATA_MST_6            (0x0040U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000040 */
+#define ADC_CDR_RDATA_MST_7            (0x0080U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000080 */
+#define ADC_CDR_RDATA_MST_8            (0x0100U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000100 */
+#define ADC_CDR_RDATA_MST_9            (0x0200U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000200 */
+#define ADC_CDR_RDATA_MST_10           (0x0400U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000400 */
+#define ADC_CDR_RDATA_MST_11           (0x0800U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000800 */
+#define ADC_CDR_RDATA_MST_12           (0x1000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00001000 */
+#define ADC_CDR_RDATA_MST_13           (0x2000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00002000 */
+#define ADC_CDR_RDATA_MST_14           (0x4000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00004000 */
+#define ADC_CDR_RDATA_MST_15           (0x8000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00008000 */
+
+#define ADC_CDR_RDATA_SLV_Pos          (16U)                                   
+#define ADC_CDR_RDATA_SLV_Msk          (0xFFFFU << ADC_CDR_RDATA_SLV_Pos)      /*!< 0xFFFF0000 */
+#define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
+#define ADC_CDR_RDATA_SLV_0            (0x0001U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00010000 */
+#define ADC_CDR_RDATA_SLV_1            (0x0002U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00020000 */
+#define ADC_CDR_RDATA_SLV_2            (0x0004U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00040000 */
+#define ADC_CDR_RDATA_SLV_3            (0x0008U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00080000 */
+#define ADC_CDR_RDATA_SLV_4            (0x0010U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00100000 */
+#define ADC_CDR_RDATA_SLV_5            (0x0020U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00200000 */
+#define ADC_CDR_RDATA_SLV_6            (0x0040U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00400000 */
+#define ADC_CDR_RDATA_SLV_7            (0x0080U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00800000 */
+#define ADC_CDR_RDATA_SLV_8            (0x0100U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x01000000 */
+#define ADC_CDR_RDATA_SLV_9            (0x0200U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x02000000 */
+#define ADC_CDR_RDATA_SLV_10           (0x0400U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x04000000 */
+#define ADC_CDR_RDATA_SLV_11           (0x0800U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x08000000 */
+#define ADC_CDR_RDATA_SLV_12           (0x1000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x10000000 */
+#define ADC_CDR_RDATA_SLV_13           (0x2000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x20000000 */
+#define ADC_CDR_RDATA_SLV_14           (0x4000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x40000000 */
+#define ADC_CDR_RDATA_SLV_15           (0x8000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x80000000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+
+#define COMP_V1_3_0_0                                  /*!< Comparator IP version */
+
+/**********************  Bit definition for COMP1_CSR register  ***************/
+#define COMP1_CSR_COMP1EN_Pos            (0U)                                  
+#define COMP1_CSR_COMP1EN_Msk            (0x1U << COMP1_CSR_COMP1EN_Pos)       /*!< 0x00000001 */
+#define COMP1_CSR_COMP1EN                COMP1_CSR_COMP1EN_Msk                 /*!< COMP1 enable */
+#define COMP1_CSR_COMP1SW1_Pos           (1U)                                  
+#define COMP1_CSR_COMP1SW1_Msk           (0x1U << COMP1_CSR_COMP1SW1_Pos)      /*!< 0x00000002 */
+#define COMP1_CSR_COMP1SW1               COMP1_CSR_COMP1SW1_Msk                /*!< COMP1 SW1 switch control */
+/* Legacy defines */
+#define COMP_CSR_COMP1SW1                COMP1_CSR_COMP1SW1
+#define COMP1_CSR_COMP1INSEL_Pos         (4U)                                  
+#define COMP1_CSR_COMP1INSEL_Msk         (0x7U << COMP1_CSR_COMP1INSEL_Pos)    /*!< 0x00000070 */
+#define COMP1_CSR_COMP1INSEL             COMP1_CSR_COMP1INSEL_Msk              /*!< COMP1 inverting input select */
+#define COMP1_CSR_COMP1INSEL_0           (0x1U << COMP1_CSR_COMP1INSEL_Pos)    /*!< 0x00000010 */
+#define COMP1_CSR_COMP1INSEL_1           (0x2U << COMP1_CSR_COMP1INSEL_Pos)    /*!< 0x00000020 */
+#define COMP1_CSR_COMP1INSEL_2           (0x4U << COMP1_CSR_COMP1INSEL_Pos)    /*!< 0x00000040 */
+#define COMP1_CSR_COMP1OUTSEL_Pos        (10U)                                 
+#define COMP1_CSR_COMP1OUTSEL_Msk        (0xFU << COMP1_CSR_COMP1OUTSEL_Pos)   /*!< 0x00003C00 */
+#define COMP1_CSR_COMP1OUTSEL            COMP1_CSR_COMP1OUTSEL_Msk             /*!< COMP1 output select */
+#define COMP1_CSR_COMP1OUTSEL_0          (0x1U << COMP1_CSR_COMP1OUTSEL_Pos)   /*!< 0x00000400 */
+#define COMP1_CSR_COMP1OUTSEL_1          (0x2U << COMP1_CSR_COMP1OUTSEL_Pos)   /*!< 0x00000800 */
+#define COMP1_CSR_COMP1OUTSEL_2          (0x4U << COMP1_CSR_COMP1OUTSEL_Pos)   /*!< 0x00001000 */
+#define COMP1_CSR_COMP1OUTSEL_3          (0x8U << COMP1_CSR_COMP1OUTSEL_Pos)   /*!< 0x00002000 */
+#define COMP1_CSR_COMP1POL_Pos           (15U)                                 
+#define COMP1_CSR_COMP1POL_Msk           (0x1U << COMP1_CSR_COMP1POL_Pos)      /*!< 0x00008000 */
+#define COMP1_CSR_COMP1POL               COMP1_CSR_COMP1POL_Msk                /*!< COMP1 output polarity */
+#define COMP1_CSR_COMP1BLANKING_Pos      (18U)                                 
+#define COMP1_CSR_COMP1BLANKING_Msk      (0x3U << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x000C0000 */
+#define COMP1_CSR_COMP1BLANKING          COMP1_CSR_COMP1BLANKING_Msk           /*!< COMP1 blanking */
+#define COMP1_CSR_COMP1BLANKING_0        (0x1U << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x00040000 */
+#define COMP1_CSR_COMP1BLANKING_1        (0x2U << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x00080000 */
+#define COMP1_CSR_COMP1BLANKING_2        (0x4U << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x00100000 */
+#define COMP1_CSR_COMP1OUT_Pos           (30U)                                 
+#define COMP1_CSR_COMP1OUT_Msk           (0x1U << COMP1_CSR_COMP1OUT_Pos)      /*!< 0x40000000 */
+#define COMP1_CSR_COMP1OUT               COMP1_CSR_COMP1OUT_Msk                /*!< COMP1 output level */
+#define COMP1_CSR_COMP1LOCK_Pos          (31U)                                 
+#define COMP1_CSR_COMP1LOCK_Msk          (0x1U << COMP1_CSR_COMP1LOCK_Pos)     /*!< 0x80000000 */
+#define COMP1_CSR_COMP1LOCK              COMP1_CSR_COMP1LOCK_Msk               /*!< COMP1 lock */
+
+/**********************  Bit definition for COMP2_CSR register  ***************/
+#define COMP2_CSR_COMP2EN_Pos            (0U)                                  
+#define COMP2_CSR_COMP2EN_Msk            (0x1U << COMP2_CSR_COMP2EN_Pos)       /*!< 0x00000001 */
+#define COMP2_CSR_COMP2EN                COMP2_CSR_COMP2EN_Msk                 /*!< COMP2 enable */
+#define COMP2_CSR_COMP2INSEL_Pos         (4U)                                  
+#define COMP2_CSR_COMP2INSEL_Msk         (0x40007U << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00400070 */
+#define COMP2_CSR_COMP2INSEL             COMP2_CSR_COMP2INSEL_Msk              /*!< COMP2 inverting input select */
+#define COMP2_CSR_COMP2INSEL_0           (0x00000010U)                         /*!< COMP2 inverting input select bit 0 */
+#define COMP2_CSR_COMP2INSEL_1           (0x00000020U)                         /*!< COMP2 inverting input select bit 1 */
+#define COMP2_CSR_COMP2INSEL_2           (0x00000040U)                         /*!< COMP2 inverting input select bit 2 */
+#define COMP2_CSR_COMP2INSEL_3           (0x00400000U)                         /*!< COMP2 inverting input select bit 3 */
+#define COMP2_CSR_COMP2NONINSEL_Pos      (7U)                                  
+#define COMP2_CSR_COMP2NONINSEL_Msk      (0x1U << COMP2_CSR_COMP2NONINSEL_Pos) /*!< 0x00000080 */
+#define COMP2_CSR_COMP2NONINSEL          COMP2_CSR_COMP2NONINSEL_Msk           /*!< COMP2 non inverting input select */
+#define COMP2_CSR_COMP2WNDWEN_Pos        (9U)                                  
+#define COMP2_CSR_COMP2WNDWEN_Msk        (0x1U << COMP2_CSR_COMP2WNDWEN_Pos)   /*!< 0x00000200 */
+#define COMP2_CSR_COMP2WNDWEN            COMP2_CSR_COMP2WNDWEN_Msk             /*!< COMP2 window mode enable */
+#define COMP2_CSR_COMP2OUTSEL_Pos        (10U)                                 
+#define COMP2_CSR_COMP2OUTSEL_Msk        (0xFU << COMP2_CSR_COMP2OUTSEL_Pos)   /*!< 0x00003C00 */
+#define COMP2_CSR_COMP2OUTSEL            COMP2_CSR_COMP2OUTSEL_Msk             /*!< COMP2 output select */
+#define COMP2_CSR_COMP2OUTSEL_0          (0x1U << COMP2_CSR_COMP2OUTSEL_Pos)   /*!< 0x00000400 */
+#define COMP2_CSR_COMP2OUTSEL_1          (0x2U << COMP2_CSR_COMP2OUTSEL_Pos)   /*!< 0x00000800 */
+#define COMP2_CSR_COMP2OUTSEL_2          (0x4U << COMP2_CSR_COMP2OUTSEL_Pos)   /*!< 0x00001000 */
+#define COMP2_CSR_COMP2OUTSEL_3          (0x8U << COMP2_CSR_COMP2OUTSEL_Pos)   /*!< 0x00002000 */
+#define COMP2_CSR_COMP2POL_Pos           (15U)                                 
+#define COMP2_CSR_COMP2POL_Msk           (0x1U << COMP2_CSR_COMP2POL_Pos)      /*!< 0x00008000 */
+#define COMP2_CSR_COMP2POL               COMP2_CSR_COMP2POL_Msk                /*!< COMP2 output polarity */
+#define COMP2_CSR_COMP2BLANKING_Pos      (18U)                                 
+#define COMP2_CSR_COMP2BLANKING_Msk      (0x3U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x000C0000 */
+#define COMP2_CSR_COMP2BLANKING          COMP2_CSR_COMP2BLANKING_Msk           /*!< COMP2 blanking */
+#define COMP2_CSR_COMP2BLANKING_0        (0x1U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00040000 */
+#define COMP2_CSR_COMP2BLANKING_1        (0x2U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00080000 */
+#define COMP2_CSR_COMP2BLANKING_2        (0x4U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00100000 */
+#define COMP2_CSR_COMP2OUT_Pos           (30U)                                 
+#define COMP2_CSR_COMP2OUT_Msk           (0x1U << COMP2_CSR_COMP2OUT_Pos)      /*!< 0x40000000 */
+#define COMP2_CSR_COMP2OUT               COMP2_CSR_COMP2OUT_Msk                /*!< COMP2 output level */
+#define COMP2_CSR_COMP2LOCK_Pos          (31U)                                 
+#define COMP2_CSR_COMP2LOCK_Msk          (0x1U << COMP2_CSR_COMP2LOCK_Pos)     /*!< 0x80000000 */
+#define COMP2_CSR_COMP2LOCK              COMP2_CSR_COMP2LOCK_Msk               /*!< COMP2 lock */
+
+/**********************  Bit definition for COMP3_CSR register  ***************/
+#define COMP3_CSR_COMP3EN_Pos            (0U)                                  
+#define COMP3_CSR_COMP3EN_Msk            (0x1U << COMP3_CSR_COMP3EN_Pos)       /*!< 0x00000001 */
+#define COMP3_CSR_COMP3EN                COMP3_CSR_COMP3EN_Msk                 /*!< COMP3 enable */
+#define COMP3_CSR_COMP3INSEL_Pos         (4U)                                  
+#define COMP3_CSR_COMP3INSEL_Msk         (0x7U << COMP3_CSR_COMP3INSEL_Pos)    /*!< 0x00000070 */
+#define COMP3_CSR_COMP3INSEL             COMP3_CSR_COMP3INSEL_Msk              /*!< COMP3 inverting input select */
+#define COMP3_CSR_COMP3INSEL_0           (0x1U << COMP3_CSR_COMP3INSEL_Pos)    /*!< 0x00000010 */
+#define COMP3_CSR_COMP3INSEL_1           (0x2U << COMP3_CSR_COMP3INSEL_Pos)    /*!< 0x00000020 */
+#define COMP3_CSR_COMP3INSEL_2           (0x4U << COMP3_CSR_COMP3INSEL_Pos)    /*!< 0x00000040 */
+#define COMP3_CSR_COMP3OUTSEL_Pos        (10U)                                 
+#define COMP3_CSR_COMP3OUTSEL_Msk        (0xFU << COMP3_CSR_COMP3OUTSEL_Pos)   /*!< 0x00003C00 */
+#define COMP3_CSR_COMP3OUTSEL            COMP3_CSR_COMP3OUTSEL_Msk             /*!< COMP3 output select */
+#define COMP3_CSR_COMP3OUTSEL_0          (0x1U << COMP3_CSR_COMP3OUTSEL_Pos)   /*!< 0x00000400 */
+#define COMP3_CSR_COMP3OUTSEL_1          (0x2U << COMP3_CSR_COMP3OUTSEL_Pos)   /*!< 0x00000800 */
+#define COMP3_CSR_COMP3OUTSEL_2          (0x4U << COMP3_CSR_COMP3OUTSEL_Pos)   /*!< 0x00001000 */
+#define COMP3_CSR_COMP3OUTSEL_3          (0x8U << COMP3_CSR_COMP3OUTSEL_Pos)   /*!< 0x00002000 */
+#define COMP3_CSR_COMP3POL_Pos           (15U)                                 
+#define COMP3_CSR_COMP3POL_Msk           (0x1U << COMP3_CSR_COMP3POL_Pos)      /*!< 0x00008000 */
+#define COMP3_CSR_COMP3POL               COMP3_CSR_COMP3POL_Msk                /*!< COMP3 output polarity */
+#define COMP3_CSR_COMP3BLANKING_Pos      (18U)                                 
+#define COMP3_CSR_COMP3BLANKING_Msk      (0x3U << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x000C0000 */
+#define COMP3_CSR_COMP3BLANKING          COMP3_CSR_COMP3BLANKING_Msk           /*!< COMP3 blanking */
+#define COMP3_CSR_COMP3BLANKING_0        (0x1U << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x00040000 */
+#define COMP3_CSR_COMP3BLANKING_1        (0x2U << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x00080000 */
+#define COMP3_CSR_COMP3BLANKING_2        (0x4U << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x00100000 */
+#define COMP3_CSR_COMP3OUT_Pos           (30U)                                 
+#define COMP3_CSR_COMP3OUT_Msk           (0x1U << COMP3_CSR_COMP3OUT_Pos)      /*!< 0x40000000 */
+#define COMP3_CSR_COMP3OUT               COMP3_CSR_COMP3OUT_Msk                /*!< COMP3 output level */
+#define COMP3_CSR_COMP3LOCK_Pos          (31U)                                 
+#define COMP3_CSR_COMP3LOCK_Msk          (0x1U << COMP3_CSR_COMP3LOCK_Pos)     /*!< 0x80000000 */
+#define COMP3_CSR_COMP3LOCK              COMP3_CSR_COMP3LOCK_Msk               /*!< COMP3 lock */
+
+/**********************  Bit definition for COMP4_CSR register  ***************/
+#define COMP4_CSR_COMP4EN_Pos            (0U)                                  
+#define COMP4_CSR_COMP4EN_Msk            (0x1U << COMP4_CSR_COMP4EN_Pos)       /*!< 0x00000001 */
+#define COMP4_CSR_COMP4EN                COMP4_CSR_COMP4EN_Msk                 /*!< COMP4 enable */
+#define COMP4_CSR_COMP4INSEL_Pos         (4U)                                  
+#define COMP4_CSR_COMP4INSEL_Msk         (0x40007U << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00400070 */
+#define COMP4_CSR_COMP4INSEL             COMP4_CSR_COMP4INSEL_Msk              /*!< COMP4 inverting input select */
+#define COMP4_CSR_COMP4INSEL_0           (0x00000010U)                         /*!< COMP4 inverting input select bit 0 */
+#define COMP4_CSR_COMP4INSEL_1           (0x00000020U)                         /*!< COMP4 inverting input select bit 1 */
+#define COMP4_CSR_COMP4INSEL_2           (0x00000040U)                         /*!< COMP4 inverting input select bit 2 */
+#define COMP4_CSR_COMP4INSEL_3           (0x00400000U)                         /*!< COMP4 inverting input select bit 3 */
+#define COMP4_CSR_COMP4NONINSEL_Pos      (7U)                                  
+#define COMP4_CSR_COMP4NONINSEL_Msk      (0x1U << COMP4_CSR_COMP4NONINSEL_Pos) /*!< 0x00000080 */
+#define COMP4_CSR_COMP4NONINSEL          COMP4_CSR_COMP4NONINSEL_Msk           /*!< COMP4 non inverting input select */
+#define COMP4_CSR_COMP4WNDWEN_Pos        (9U)                                  
+#define COMP4_CSR_COMP4WNDWEN_Msk        (0x1U << COMP4_CSR_COMP4WNDWEN_Pos)   /*!< 0x00000200 */
+#define COMP4_CSR_COMP4WNDWEN            COMP4_CSR_COMP4WNDWEN_Msk             /*!< COMP4 window mode enable */
+#define COMP4_CSR_COMP4OUTSEL_Pos        (10U)                                 
+#define COMP4_CSR_COMP4OUTSEL_Msk        (0xFU << COMP4_CSR_COMP4OUTSEL_Pos)   /*!< 0x00003C00 */
+#define COMP4_CSR_COMP4OUTSEL            COMP4_CSR_COMP4OUTSEL_Msk             /*!< COMP4 output select */
+#define COMP4_CSR_COMP4OUTSEL_0          (0x1U << COMP4_CSR_COMP4OUTSEL_Pos)   /*!< 0x00000400 */
+#define COMP4_CSR_COMP4OUTSEL_1          (0x2U << COMP4_CSR_COMP4OUTSEL_Pos)   /*!< 0x00000800 */
+#define COMP4_CSR_COMP4OUTSEL_2          (0x4U << COMP4_CSR_COMP4OUTSEL_Pos)   /*!< 0x00001000 */
+#define COMP4_CSR_COMP4OUTSEL_3          (0x8U << COMP4_CSR_COMP4OUTSEL_Pos)   /*!< 0x00002000 */
+#define COMP4_CSR_COMP4POL_Pos           (15U)                                 
+#define COMP4_CSR_COMP4POL_Msk           (0x1U << COMP4_CSR_COMP4POL_Pos)      /*!< 0x00008000 */
+#define COMP4_CSR_COMP4POL               COMP4_CSR_COMP4POL_Msk                /*!< COMP4 output polarity */
+#define COMP4_CSR_COMP4BLANKING_Pos      (18U)                                 
+#define COMP4_CSR_COMP4BLANKING_Msk      (0x3U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x000C0000 */
+#define COMP4_CSR_COMP4BLANKING          COMP4_CSR_COMP4BLANKING_Msk           /*!< COMP4 blanking */
+#define COMP4_CSR_COMP4BLANKING_0        (0x1U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00040000 */
+#define COMP4_CSR_COMP4BLANKING_1        (0x2U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00080000 */
+#define COMP4_CSR_COMP4BLANKING_2        (0x4U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00100000 */
+#define COMP4_CSR_COMP4OUT_Pos           (30U)                                 
+#define COMP4_CSR_COMP4OUT_Msk           (0x1U << COMP4_CSR_COMP4OUT_Pos)      /*!< 0x40000000 */
+#define COMP4_CSR_COMP4OUT               COMP4_CSR_COMP4OUT_Msk                /*!< COMP4 output level */
+#define COMP4_CSR_COMP4LOCK_Pos          (31U)                                 
+#define COMP4_CSR_COMP4LOCK_Msk          (0x1U << COMP4_CSR_COMP4LOCK_Pos)     /*!< 0x80000000 */
+#define COMP4_CSR_COMP4LOCK              COMP4_CSR_COMP4LOCK_Msk               /*!< COMP4 lock */
+
+/**********************  Bit definition for COMP5_CSR register  ***************/
+#define COMP5_CSR_COMP5EN_Pos            (0U)                                  
+#define COMP5_CSR_COMP5EN_Msk            (0x1U << COMP5_CSR_COMP5EN_Pos)       /*!< 0x00000001 */
+#define COMP5_CSR_COMP5EN                COMP5_CSR_COMP5EN_Msk                 /*!< COMP5 enable */
+#define COMP5_CSR_COMP5INSEL_Pos         (4U)                                  
+#define COMP5_CSR_COMP5INSEL_Msk         (0x7U << COMP5_CSR_COMP5INSEL_Pos)    /*!< 0x00000070 */
+#define COMP5_CSR_COMP5INSEL             COMP5_CSR_COMP5INSEL_Msk              /*!< COMP5 inverting input select */
+#define COMP5_CSR_COMP5INSEL_0           (0x1U << COMP5_CSR_COMP5INSEL_Pos)    /*!< 0x00000010 */
+#define COMP5_CSR_COMP5INSEL_1           (0x2U << COMP5_CSR_COMP5INSEL_Pos)    /*!< 0x00000020 */
+#define COMP5_CSR_COMP5INSEL_2           (0x4U << COMP5_CSR_COMP5INSEL_Pos)    /*!< 0x00000040 */
+#define COMP5_CSR_COMP5OUTSEL_Pos        (10U)                                 
+#define COMP5_CSR_COMP5OUTSEL_Msk        (0xFU << COMP5_CSR_COMP5OUTSEL_Pos)   /*!< 0x00003C00 */
+#define COMP5_CSR_COMP5OUTSEL            COMP5_CSR_COMP5OUTSEL_Msk             /*!< COMP5 output select */
+#define COMP5_CSR_COMP5OUTSEL_0          (0x1U << COMP5_CSR_COMP5OUTSEL_Pos)   /*!< 0x00000400 */
+#define COMP5_CSR_COMP5OUTSEL_1          (0x2U << COMP5_CSR_COMP5OUTSEL_Pos)   /*!< 0x00000800 */
+#define COMP5_CSR_COMP5OUTSEL_2          (0x4U << COMP5_CSR_COMP5OUTSEL_Pos)   /*!< 0x00001000 */
+#define COMP5_CSR_COMP5OUTSEL_3          (0x8U << COMP5_CSR_COMP5OUTSEL_Pos)   /*!< 0x00002000 */
+#define COMP5_CSR_COMP5POL_Pos           (15U)                                 
+#define COMP5_CSR_COMP5POL_Msk           (0x1U << COMP5_CSR_COMP5POL_Pos)      /*!< 0x00008000 */
+#define COMP5_CSR_COMP5POL               COMP5_CSR_COMP5POL_Msk                /*!< COMP5 output polarity */
+#define COMP5_CSR_COMP5BLANKING_Pos      (18U)                                 
+#define COMP5_CSR_COMP5BLANKING_Msk      (0x3U << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x000C0000 */
+#define COMP5_CSR_COMP5BLANKING          COMP5_CSR_COMP5BLANKING_Msk           /*!< COMP5 blanking */
+#define COMP5_CSR_COMP5BLANKING_0        (0x1U << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x00040000 */
+#define COMP5_CSR_COMP5BLANKING_1        (0x2U << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x00080000 */
+#define COMP5_CSR_COMP5BLANKING_2        (0x4U << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x00100000 */
+#define COMP5_CSR_COMP5OUT_Pos           (30U)                                 
+#define COMP5_CSR_COMP5OUT_Msk           (0x1U << COMP5_CSR_COMP5OUT_Pos)      /*!< 0x40000000 */
+#define COMP5_CSR_COMP5OUT               COMP5_CSR_COMP5OUT_Msk                /*!< COMP5 output level */
+#define COMP5_CSR_COMP5LOCK_Pos          (31U)                                 
+#define COMP5_CSR_COMP5LOCK_Msk          (0x1U << COMP5_CSR_COMP5LOCK_Pos)     /*!< 0x80000000 */
+#define COMP5_CSR_COMP5LOCK              COMP5_CSR_COMP5LOCK_Msk               /*!< COMP5 lock */
+
+/**********************  Bit definition for COMP6_CSR register  ***************/
+#define COMP6_CSR_COMP6EN_Pos            (0U)                                  
+#define COMP6_CSR_COMP6EN_Msk            (0x1U << COMP6_CSR_COMP6EN_Pos)       /*!< 0x00000001 */
+#define COMP6_CSR_COMP6EN                COMP6_CSR_COMP6EN_Msk                 /*!< COMP6 enable */
+#define COMP6_CSR_COMP6INSEL_Pos         (4U)                                  
+#define COMP6_CSR_COMP6INSEL_Msk         (0x40007U << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00400070 */
+#define COMP6_CSR_COMP6INSEL             COMP6_CSR_COMP6INSEL_Msk              /*!< COMP6 inverting input select */
+#define COMP6_CSR_COMP6INSEL_0           (0x00000010U)                         /*!< COMP6 inverting input select bit 0 */
+#define COMP6_CSR_COMP6INSEL_1           (0x00000020U)                         /*!< COMP6 inverting input select bit 1 */
+#define COMP6_CSR_COMP6INSEL_2           (0x00000040U)                         /*!< COMP6 inverting input select bit 2 */
+#define COMP6_CSR_COMP6INSEL_3           (0x00400000U)                         /*!< COMP6 inverting input select bit 3 */
+#if defined(STM32F303xE)
+#define COMP6_CSR_COMP6NONINSEL_Pos      (7U)                                  
+#define COMP6_CSR_COMP6NONINSEL_Msk      (0x1U << COMP6_CSR_COMP6NONINSEL_Pos) /*!< 0x00000080 */
+#define COMP6_CSR_COMP6NONINSEL          COMP6_CSR_COMP6NONINSEL_Msk           /*!< COMP6 non inverting input select */
+#endif
+#define COMP6_CSR_COMP6WNDWEN_Pos        (9U)                                  
+#define COMP6_CSR_COMP6WNDWEN_Msk        (0x1U << COMP6_CSR_COMP6WNDWEN_Pos)   /*!< 0x00000200 */
+#define COMP6_CSR_COMP6WNDWEN            COMP6_CSR_COMP6WNDWEN_Msk             /*!< COMP6 window mode enable */
+#define COMP6_CSR_COMP6OUTSEL_Pos        (10U)                                 
+#define COMP6_CSR_COMP6OUTSEL_Msk        (0xFU << COMP6_CSR_COMP6OUTSEL_Pos)   /*!< 0x00003C00 */
+#define COMP6_CSR_COMP6OUTSEL            COMP6_CSR_COMP6OUTSEL_Msk             /*!< COMP6 output select */
+#define COMP6_CSR_COMP6OUTSEL_0          (0x1U << COMP6_CSR_COMP6OUTSEL_Pos)   /*!< 0x00000400 */
+#define COMP6_CSR_COMP6OUTSEL_1          (0x2U << COMP6_CSR_COMP6OUTSEL_Pos)   /*!< 0x00000800 */
+#define COMP6_CSR_COMP6OUTSEL_2          (0x4U << COMP6_CSR_COMP6OUTSEL_Pos)   /*!< 0x00001000 */
+#define COMP6_CSR_COMP6OUTSEL_3          (0x8U << COMP6_CSR_COMP6OUTSEL_Pos)   /*!< 0x00002000 */
+#define COMP6_CSR_COMP6POL_Pos           (15U)                                 
+#define COMP6_CSR_COMP6POL_Msk           (0x1U << COMP6_CSR_COMP6POL_Pos)      /*!< 0x00008000 */
+#define COMP6_CSR_COMP6POL               COMP6_CSR_COMP6POL_Msk                /*!< COMP6 output polarity */
+#define COMP6_CSR_COMP6BLANKING_Pos      (18U)                                 
+#define COMP6_CSR_COMP6BLANKING_Msk      (0x3U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x000C0000 */
+#define COMP6_CSR_COMP6BLANKING          COMP6_CSR_COMP6BLANKING_Msk           /*!< COMP6 blanking */
+#define COMP6_CSR_COMP6BLANKING_0        (0x1U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00040000 */
+#define COMP6_CSR_COMP6BLANKING_1        (0x2U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00080000 */
+#define COMP6_CSR_COMP6BLANKING_2        (0x4U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00100000 */
+#define COMP6_CSR_COMP6OUT_Pos           (30U)                                 
+#define COMP6_CSR_COMP6OUT_Msk           (0x1U << COMP6_CSR_COMP6OUT_Pos)      /*!< 0x40000000 */
+#define COMP6_CSR_COMP6OUT               COMP6_CSR_COMP6OUT_Msk                /*!< COMP6 output level */
+#define COMP6_CSR_COMP6LOCK_Pos          (31U)                                 
+#define COMP6_CSR_COMP6LOCK_Msk          (0x1U << COMP6_CSR_COMP6LOCK_Pos)     /*!< 0x80000000 */
+#define COMP6_CSR_COMP6LOCK              COMP6_CSR_COMP6LOCK_Msk               /*!< COMP6 lock */
+
+/**********************  Bit definition for COMP7_CSR register  ***************/
+#define COMP7_CSR_COMP7EN_Pos            (0U)                                  
+#define COMP7_CSR_COMP7EN_Msk            (0x1U << COMP7_CSR_COMP7EN_Pos)       /*!< 0x00000001 */
+#define COMP7_CSR_COMP7EN                COMP7_CSR_COMP7EN_Msk                 /*!< COMP7 enable */
+#define COMP7_CSR_COMP7INSEL_Pos         (4U)                                  
+#define COMP7_CSR_COMP7INSEL_Msk         (0x7U << COMP7_CSR_COMP7INSEL_Pos)    /*!< 0x00000070 */
+#define COMP7_CSR_COMP7INSEL             COMP7_CSR_COMP7INSEL_Msk              /*!< COMP7 inverting input select */
+#define COMP7_CSR_COMP7INSEL_0           (0x1U << COMP7_CSR_COMP7INSEL_Pos)    /*!< 0x00000010 */
+#define COMP7_CSR_COMP7INSEL_1           (0x2U << COMP7_CSR_COMP7INSEL_Pos)    /*!< 0x00000020 */
+#define COMP7_CSR_COMP7INSEL_2           (0x4U << COMP7_CSR_COMP7INSEL_Pos)    /*!< 0x00000040 */
+#define COMP7_CSR_COMP7OUTSEL_Pos        (10U)                                 
+#define COMP7_CSR_COMP7OUTSEL_Msk        (0xFU << COMP7_CSR_COMP7OUTSEL_Pos)   /*!< 0x00003C00 */
+#define COMP7_CSR_COMP7OUTSEL            COMP7_CSR_COMP7OUTSEL_Msk             /*!< COMP7 output select */
+#define COMP7_CSR_COMP7OUTSEL_0          (0x1U << COMP7_CSR_COMP7OUTSEL_Pos)   /*!< 0x00000400 */
+#define COMP7_CSR_COMP7OUTSEL_1          (0x2U << COMP7_CSR_COMP7OUTSEL_Pos)   /*!< 0x00000800 */
+#define COMP7_CSR_COMP7OUTSEL_2          (0x4U << COMP7_CSR_COMP7OUTSEL_Pos)   /*!< 0x00001000 */
+#define COMP7_CSR_COMP7OUTSEL_3          (0x8U << COMP7_CSR_COMP7OUTSEL_Pos)   /*!< 0x00002000 */
+#define COMP7_CSR_COMP7POL_Pos           (15U)                                 
+#define COMP7_CSR_COMP7POL_Msk           (0x1U << COMP7_CSR_COMP7POL_Pos)      /*!< 0x00008000 */
+#define COMP7_CSR_COMP7POL               COMP7_CSR_COMP7POL_Msk                /*!< COMP7 output polarity */
+#define COMP7_CSR_COMP7BLANKING_Pos      (18U)                                 
+#define COMP7_CSR_COMP7BLANKING_Msk      (0x3U << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x000C0000 */
+#define COMP7_CSR_COMP7BLANKING          COMP7_CSR_COMP7BLANKING_Msk           /*!< COMP7 blanking */
+#define COMP7_CSR_COMP7BLANKING_0        (0x1U << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x00040000 */
+#define COMP7_CSR_COMP7BLANKING_1        (0x2U << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x00080000 */
+#define COMP7_CSR_COMP7BLANKING_2        (0x4U << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x00100000 */
+#define COMP7_CSR_COMP7OUT_Pos           (30U)                                 
+#define COMP7_CSR_COMP7OUT_Msk           (0x1U << COMP7_CSR_COMP7OUT_Pos)      /*!< 0x40000000 */
+#define COMP7_CSR_COMP7OUT               COMP7_CSR_COMP7OUT_Msk                /*!< COMP7 output level */
+#define COMP7_CSR_COMP7LOCK_Pos          (31U)                                 
+#define COMP7_CSR_COMP7LOCK_Msk          (0x1U << COMP7_CSR_COMP7LOCK_Pos)     /*!< 0x80000000 */
+#define COMP7_CSR_COMP7LOCK              COMP7_CSR_COMP7LOCK_Msk               /*!< COMP7 lock */
+
+/**********************  Bit definition for COMP_CSR register  ****************/
+#define COMP_CSR_COMPxEN_Pos            (0U)                                   
+#define COMP_CSR_COMPxEN_Msk            (0x1U << COMP_CSR_COMPxEN_Pos)         /*!< 0x00000001 */
+#define COMP_CSR_COMPxEN                COMP_CSR_COMPxEN_Msk                   /*!< COMPx enable */
+#define COMP_CSR_COMPxSW1_Pos           (1U)                                   
+#define COMP_CSR_COMPxSW1_Msk           (0x1U << COMP_CSR_COMPxSW1_Pos)        /*!< 0x00000002 */
+#define COMP_CSR_COMPxSW1               COMP_CSR_COMPxSW1_Msk                  /*!< COMPx SW1 switch control */
+#define COMP_CSR_COMPxINSEL_Pos         (4U)                                   
+#define COMP_CSR_COMPxINSEL_Msk         (0x40007U << COMP_CSR_COMPxINSEL_Pos)  /*!< 0x00400070 */
+#define COMP_CSR_COMPxINSEL             COMP_CSR_COMPxINSEL_Msk                /*!< COMPx inverting input select */
+#define COMP_CSR_COMPxINSEL_0           (0x00000010U)                          /*!< COMPx inverting input select bit 0 */
+#define COMP_CSR_COMPxINSEL_1           (0x00000020U)                          /*!< COMPx inverting input select bit 1 */
+#define COMP_CSR_COMPxINSEL_2           (0x00000040U)                          /*!< COMPx inverting input select bit 2 */
+#define COMP_CSR_COMPxINSEL_3           (0x00400000U)                          /*!< COMPx inverting input select bit 3 */
+#define COMP_CSR_COMPxNONINSEL_Pos      (7U)                                   
+#define COMP_CSR_COMPxNONINSEL_Msk      (0x1U << COMP_CSR_COMPxNONINSEL_Pos)   /*!< 0x00000080 */
+#define COMP_CSR_COMPxNONINSEL          COMP_CSR_COMPxNONINSEL_Msk             /*!< COMPx non inverting input select */
+#define COMP_CSR_COMPxWNDWEN_Pos        (9U)                                   
+#define COMP_CSR_COMPxWNDWEN_Msk        (0x1U << COMP_CSR_COMPxWNDWEN_Pos)     /*!< 0x00000200 */
+#define COMP_CSR_COMPxWNDWEN            COMP_CSR_COMPxWNDWEN_Msk               /*!< COMPx window mode enable */
+#define COMP_CSR_COMPxOUTSEL_Pos        (10U)                                  
+#define COMP_CSR_COMPxOUTSEL_Msk        (0xFU << COMP_CSR_COMPxOUTSEL_Pos)     /*!< 0x00003C00 */
+#define COMP_CSR_COMPxOUTSEL            COMP_CSR_COMPxOUTSEL_Msk               /*!< COMPx output select */
+#define COMP_CSR_COMPxOUTSEL_0          (0x1U << COMP_CSR_COMPxOUTSEL_Pos)     /*!< 0x00000400 */
+#define COMP_CSR_COMPxOUTSEL_1          (0x2U << COMP_CSR_COMPxOUTSEL_Pos)     /*!< 0x00000800 */
+#define COMP_CSR_COMPxOUTSEL_2          (0x4U << COMP_CSR_COMPxOUTSEL_Pos)     /*!< 0x00001000 */
+#define COMP_CSR_COMPxOUTSEL_3          (0x8U << COMP_CSR_COMPxOUTSEL_Pos)     /*!< 0x00002000 */
+#define COMP_CSR_COMPxPOL_Pos           (15U)                                  
+#define COMP_CSR_COMPxPOL_Msk           (0x1U << COMP_CSR_COMPxPOL_Pos)        /*!< 0x00008000 */
+#define COMP_CSR_COMPxPOL               COMP_CSR_COMPxPOL_Msk                  /*!< COMPx output polarity */
+#define COMP_CSR_COMPxBLANKING_Pos      (18U)                                  
+#define COMP_CSR_COMPxBLANKING_Msk      (0x3U << COMP_CSR_COMPxBLANKING_Pos)   /*!< 0x000C0000 */
+#define COMP_CSR_COMPxBLANKING          COMP_CSR_COMPxBLANKING_Msk             /*!< COMPx blanking */
+#define COMP_CSR_COMPxBLANKING_0        (0x1U << COMP_CSR_COMPxBLANKING_Pos)   /*!< 0x00040000 */
+#define COMP_CSR_COMPxBLANKING_1        (0x2U << COMP_CSR_COMPxBLANKING_Pos)   /*!< 0x00080000 */
+#define COMP_CSR_COMPxBLANKING_2        (0x4U << COMP_CSR_COMPxBLANKING_Pos)   /*!< 0x00100000 */
+#define COMP_CSR_COMPxOUT_Pos           (30U)                                  
+#define COMP_CSR_COMPxOUT_Msk           (0x1U << COMP_CSR_COMPxOUT_Pos)        /*!< 0x40000000 */
+#define COMP_CSR_COMPxOUT               COMP_CSR_COMPxOUT_Msk                  /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK_Pos          (31U)                                  
+#define COMP_CSR_COMPxLOCK_Msk          (0x1U << COMP_CSR_COMPxLOCK_Pos)       /*!< 0x80000000 */
+#define COMP_CSR_COMPxLOCK              COMP_CSR_COMPxLOCK_Msk                 /*!< COMPx lock */
+
+/******************************************************************************/
+/*                                                                            */
+/*                     Operational Amplifier (OPAMP)                          */
+/*                                                                            */
+/******************************************************************************/
+/*********************  Bit definition for OPAMP1_CSR register  ***************/
+#define OPAMP1_CSR_OPAMP1EN_Pos       (0U)                                     
+#define OPAMP1_CSR_OPAMP1EN_Msk       (0x1U << OPAMP1_CSR_OPAMP1EN_Pos)        /*!< 0x00000001 */
+#define OPAMP1_CSR_OPAMP1EN           OPAMP1_CSR_OPAMP1EN_Msk                  /*!< OPAMP1 enable */
+#define OPAMP1_CSR_FORCEVP_Pos        (1U)                                     
+#define OPAMP1_CSR_FORCEVP_Msk        (0x1U << OPAMP1_CSR_FORCEVP_Pos)         /*!< 0x00000002 */
+#define OPAMP1_CSR_FORCEVP            OPAMP1_CSR_FORCEVP_Msk                   /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP1_CSR_VPSEL_Pos          (2U)                                     
+#define OPAMP1_CSR_VPSEL_Msk          (0x3U << OPAMP1_CSR_VPSEL_Pos)           /*!< 0x0000000C */
+#define OPAMP1_CSR_VPSEL              OPAMP1_CSR_VPSEL_Msk                     /*!< Non inverting input selection */
+#define OPAMP1_CSR_VPSEL_0            (0x1U << OPAMP1_CSR_VPSEL_Pos)           /*!< 0x00000004 */
+#define OPAMP1_CSR_VPSEL_1            (0x2U << OPAMP1_CSR_VPSEL_Pos)           /*!< 0x00000008 */
+#define OPAMP1_CSR_VMSEL_Pos          (5U)                                     
+#define OPAMP1_CSR_VMSEL_Msk          (0x3U << OPAMP1_CSR_VMSEL_Pos)           /*!< 0x00000060 */
+#define OPAMP1_CSR_VMSEL              OPAMP1_CSR_VMSEL_Msk                     /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0            (0x1U << OPAMP1_CSR_VMSEL_Pos)           /*!< 0x00000020 */
+#define OPAMP1_CSR_VMSEL_1            (0x2U << OPAMP1_CSR_VMSEL_Pos)           /*!< 0x00000040 */
+#define OPAMP1_CSR_TCMEN_Pos          (7U)                                     
+#define OPAMP1_CSR_TCMEN_Msk          (0x1U << OPAMP1_CSR_TCMEN_Pos)           /*!< 0x00000080 */
+#define OPAMP1_CSR_TCMEN              OPAMP1_CSR_TCMEN_Msk                     /*!< Timer-Controlled Mux mode enable */
+#define OPAMP1_CSR_VMSSEL_Pos         (8U)                                     
+#define OPAMP1_CSR_VMSSEL_Msk         (0x1U << OPAMP1_CSR_VMSSEL_Pos)          /*!< 0x00000100 */
+#define OPAMP1_CSR_VMSSEL             OPAMP1_CSR_VMSSEL_Msk                    /*!< Inverting input secondary selection */
+#define OPAMP1_CSR_VPSSEL_Pos         (9U)                                     
+#define OPAMP1_CSR_VPSSEL_Msk         (0x3U << OPAMP1_CSR_VPSSEL_Pos)          /*!< 0x00000600 */
+#define OPAMP1_CSR_VPSSEL             OPAMP1_CSR_VPSSEL_Msk                    /*!< Non inverting input secondary selection */
+#define OPAMP1_CSR_VPSSEL_0           (0x1U << OPAMP1_CSR_VPSSEL_Pos)          /*!< 0x00000200 */
+#define OPAMP1_CSR_VPSSEL_1           (0x2U << OPAMP1_CSR_VPSSEL_Pos)          /*!< 0x00000400 */
+#define OPAMP1_CSR_CALON_Pos          (11U)                                    
+#define OPAMP1_CSR_CALON_Msk          (0x1U << OPAMP1_CSR_CALON_Pos)           /*!< 0x00000800 */
+#define OPAMP1_CSR_CALON              OPAMP1_CSR_CALON_Msk                     /*!< Calibration mode enable */
+#define OPAMP1_CSR_CALSEL_Pos         (12U)                                    
+#define OPAMP1_CSR_CALSEL_Msk         (0x3U << OPAMP1_CSR_CALSEL_Pos)          /*!< 0x00003000 */
+#define OPAMP1_CSR_CALSEL             OPAMP1_CSR_CALSEL_Msk                    /*!< Calibration selection */
+#define OPAMP1_CSR_CALSEL_0           (0x1U << OPAMP1_CSR_CALSEL_Pos)          /*!< 0x00001000 */
+#define OPAMP1_CSR_CALSEL_1           (0x2U << OPAMP1_CSR_CALSEL_Pos)          /*!< 0x00002000 */
+#define OPAMP1_CSR_PGGAIN_Pos         (14U)                                    
+#define OPAMP1_CSR_PGGAIN_Msk         (0xFU << OPAMP1_CSR_PGGAIN_Pos)          /*!< 0x0003C000 */
+#define OPAMP1_CSR_PGGAIN             OPAMP1_CSR_PGGAIN_Msk                    /*!< Gain in PGA mode */
+#define OPAMP1_CSR_PGGAIN_0           (0x1U << OPAMP1_CSR_PGGAIN_Pos)          /*!< 0x00004000 */
+#define OPAMP1_CSR_PGGAIN_1           (0x2U << OPAMP1_CSR_PGGAIN_Pos)          /*!< 0x00008000 */
+#define OPAMP1_CSR_PGGAIN_2           (0x4U << OPAMP1_CSR_PGGAIN_Pos)          /*!< 0x00010000 */
+#define OPAMP1_CSR_PGGAIN_3           (0x8U << OPAMP1_CSR_PGGAIN_Pos)          /*!< 0x00020000 */
+#define OPAMP1_CSR_USERTRIM_Pos       (18U)                                    
+#define OPAMP1_CSR_USERTRIM_Msk       (0x1U << OPAMP1_CSR_USERTRIM_Pos)        /*!< 0x00040000 */
+#define OPAMP1_CSR_USERTRIM           OPAMP1_CSR_USERTRIM_Msk                  /*!< User trimming enable */
+#define OPAMP1_CSR_TRIMOFFSETP_Pos    (19U)                                    
+#define OPAMP1_CSR_TRIMOFFSETP_Msk    (0x1FU << OPAMP1_CSR_TRIMOFFSETP_Pos)    /*!< 0x00F80000 */
+#define OPAMP1_CSR_TRIMOFFSETP        OPAMP1_CSR_TRIMOFFSETP_Msk               /*!< Offset trimming value (PMOS) */
+#define OPAMP1_CSR_TRIMOFFSETN_Pos    (24U)                                    
+#define OPAMP1_CSR_TRIMOFFSETN_Msk    (0x1FU << OPAMP1_CSR_TRIMOFFSETN_Pos)    /*!< 0x1F000000 */
+#define OPAMP1_CSR_TRIMOFFSETN        OPAMP1_CSR_TRIMOFFSETN_Msk               /*!< Offset trimming value (NMOS) */
+#define OPAMP1_CSR_TSTREF_Pos         (29U)                                    
+#define OPAMP1_CSR_TSTREF_Msk         (0x1U << OPAMP1_CSR_TSTREF_Pos)          /*!< 0x20000000 */
+#define OPAMP1_CSR_TSTREF             OPAMP1_CSR_TSTREF_Msk                    /*!< It enables the switch to put out the internal reference */
+#define OPAMP1_CSR_OUTCAL_Pos         (30U)                                    
+#define OPAMP1_CSR_OUTCAL_Msk         (0x1U << OPAMP1_CSR_OUTCAL_Pos)          /*!< 0x40000000 */
+#define OPAMP1_CSR_OUTCAL             OPAMP1_CSR_OUTCAL_Msk                    /*!< OPAMP ouput status flag */
+#define OPAMP1_CSR_LOCK_Pos           (31U)                                    
+#define OPAMP1_CSR_LOCK_Msk           (0x1U << OPAMP1_CSR_LOCK_Pos)            /*!< 0x80000000 */
+#define OPAMP1_CSR_LOCK               OPAMP1_CSR_LOCK_Msk                      /*!< OPAMP lock */
+
+/*********************  Bit definition for OPAMP2_CSR register  ***************/
+#define OPAMP2_CSR_OPAMP2EN_Pos       (0U)                                     
+#define OPAMP2_CSR_OPAMP2EN_Msk       (0x1U << OPAMP2_CSR_OPAMP2EN_Pos)        /*!< 0x00000001 */
+#define OPAMP2_CSR_OPAMP2EN           OPAMP2_CSR_OPAMP2EN_Msk                  /*!< OPAMP2 enable */
+#define OPAMP2_CSR_FORCEVP_Pos        (1U)                                     
+#define OPAMP2_CSR_FORCEVP_Msk        (0x1U << OPAMP2_CSR_FORCEVP_Pos)         /*!< 0x00000002 */
+#define OPAMP2_CSR_FORCEVP            OPAMP2_CSR_FORCEVP_Msk                   /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP2_CSR_VPSEL_Pos          (2U)                                     
+#define OPAMP2_CSR_VPSEL_Msk          (0x3U << OPAMP2_CSR_VPSEL_Pos)           /*!< 0x0000000C */
+#define OPAMP2_CSR_VPSEL              OPAMP2_CSR_VPSEL_Msk                     /*!< Non inverting input selection */
+#define OPAMP2_CSR_VPSEL_0            (0x1U << OPAMP2_CSR_VPSEL_Pos)           /*!< 0x00000004 */
+#define OPAMP2_CSR_VPSEL_1            (0x2U << OPAMP2_CSR_VPSEL_Pos)           /*!< 0x00000008 */
+#define OPAMP2_CSR_VMSEL_Pos          (5U)                                     
+#define OPAMP2_CSR_VMSEL_Msk          (0x3U << OPAMP2_CSR_VMSEL_Pos)           /*!< 0x00000060 */
+#define OPAMP2_CSR_VMSEL              OPAMP2_CSR_VMSEL_Msk                     /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0            (0x1U << OPAMP2_CSR_VMSEL_Pos)           /*!< 0x00000020 */
+#define OPAMP2_CSR_VMSEL_1            (0x2U << OPAMP2_CSR_VMSEL_Pos)           /*!< 0x00000040 */
+#define OPAMP2_CSR_TCMEN_Pos          (7U)                                     
+#define OPAMP2_CSR_TCMEN_Msk          (0x1U << OPAMP2_CSR_TCMEN_Pos)           /*!< 0x00000080 */
+#define OPAMP2_CSR_TCMEN              OPAMP2_CSR_TCMEN_Msk                     /*!< Timer-Controlled Mux mode enable */
+#define OPAMP2_CSR_VMSSEL_Pos         (8U)                                     
+#define OPAMP2_CSR_VMSSEL_Msk         (0x1U << OPAMP2_CSR_VMSSEL_Pos)          /*!< 0x00000100 */
+#define OPAMP2_CSR_VMSSEL             OPAMP2_CSR_VMSSEL_Msk                    /*!< Inverting input secondary selection */
+#define OPAMP2_CSR_VPSSEL_Pos         (9U)                                     
+#define OPAMP2_CSR_VPSSEL_Msk         (0x3U << OPAMP2_CSR_VPSSEL_Pos)          /*!< 0x00000600 */
+#define OPAMP2_CSR_VPSSEL             OPAMP2_CSR_VPSSEL_Msk                    /*!< Non inverting input secondary selection */
+#define OPAMP2_CSR_VPSSEL_0           (0x1U << OPAMP2_CSR_VPSSEL_Pos)          /*!< 0x00000200 */
+#define OPAMP2_CSR_VPSSEL_1           (0x2U << OPAMP2_CSR_VPSSEL_Pos)          /*!< 0x00000400 */
+#define OPAMP2_CSR_CALON_Pos          (11U)                                    
+#define OPAMP2_CSR_CALON_Msk          (0x1U << OPAMP2_CSR_CALON_Pos)           /*!< 0x00000800 */
+#define OPAMP2_CSR_CALON              OPAMP2_CSR_CALON_Msk                     /*!< Calibration mode enable */
+#define OPAMP2_CSR_CALSEL_Pos         (12U)                                    
+#define OPAMP2_CSR_CALSEL_Msk         (0x3U << OPAMP2_CSR_CALSEL_Pos)          /*!< 0x00003000 */
+#define OPAMP2_CSR_CALSEL             OPAMP2_CSR_CALSEL_Msk                    /*!< Calibration selection */
+#define OPAMP2_CSR_CALSEL_0           (0x1U << OPAMP2_CSR_CALSEL_Pos)          /*!< 0x00001000 */
+#define OPAMP2_CSR_CALSEL_1           (0x2U << OPAMP2_CSR_CALSEL_Pos)          /*!< 0x00002000 */
+#define OPAMP2_CSR_PGGAIN_Pos         (14U)                                    
+#define OPAMP2_CSR_PGGAIN_Msk         (0xFU << OPAMP2_CSR_PGGAIN_Pos)          /*!< 0x0003C000 */
+#define OPAMP2_CSR_PGGAIN             OPAMP2_CSR_PGGAIN_Msk                    /*!< Gain in PGA mode */
+#define OPAMP2_CSR_PGGAIN_0           (0x1U << OPAMP2_CSR_PGGAIN_Pos)          /*!< 0x00004000 */
+#define OPAMP2_CSR_PGGAIN_1           (0x2U << OPAMP2_CSR_PGGAIN_Pos)          /*!< 0x00008000 */
+#define OPAMP2_CSR_PGGAIN_2           (0x4U << OPAMP2_CSR_PGGAIN_Pos)          /*!< 0x00010000 */
+#define OPAMP2_CSR_PGGAIN_3           (0x8U << OPAMP2_CSR_PGGAIN_Pos)          /*!< 0x00020000 */
+#define OPAMP2_CSR_USERTRIM_Pos       (18U)                                    
+#define OPAMP2_CSR_USERTRIM_Msk       (0x1U << OPAMP2_CSR_USERTRIM_Pos)        /*!< 0x00040000 */
+#define OPAMP2_CSR_USERTRIM           OPAMP2_CSR_USERTRIM_Msk                  /*!< User trimming enable */
+#define OPAMP2_CSR_TRIMOFFSETP_Pos    (19U)                                    
+#define OPAMP2_CSR_TRIMOFFSETP_Msk    (0x1FU << OPAMP2_CSR_TRIMOFFSETP_Pos)    /*!< 0x00F80000 */
+#define OPAMP2_CSR_TRIMOFFSETP        OPAMP2_CSR_TRIMOFFSETP_Msk               /*!< Offset trimming value (PMOS) */
+#define OPAMP2_CSR_TRIMOFFSETN_Pos    (24U)                                    
+#define OPAMP2_CSR_TRIMOFFSETN_Msk    (0x1FU << OPAMP2_CSR_TRIMOFFSETN_Pos)    /*!< 0x1F000000 */
+#define OPAMP2_CSR_TRIMOFFSETN        OPAMP2_CSR_TRIMOFFSETN_Msk               /*!< Offset trimming value (NMOS) */
+#define OPAMP2_CSR_TSTREF_Pos         (29U)                                    
+#define OPAMP2_CSR_TSTREF_Msk         (0x1U << OPAMP2_CSR_TSTREF_Pos)          /*!< 0x20000000 */
+#define OPAMP2_CSR_TSTREF             OPAMP2_CSR_TSTREF_Msk                    /*!< It enables the switch to put out the internal reference */
+#define OPAMP2_CSR_OUTCAL_Pos         (30U)                                    
+#define OPAMP2_CSR_OUTCAL_Msk         (0x1U << OPAMP2_CSR_OUTCAL_Pos)          /*!< 0x40000000 */
+#define OPAMP2_CSR_OUTCAL             OPAMP2_CSR_OUTCAL_Msk                    /*!< OPAMP ouput status flag */
+#define OPAMP2_CSR_LOCK_Pos           (31U)                                    
+#define OPAMP2_CSR_LOCK_Msk           (0x1U << OPAMP2_CSR_LOCK_Pos)            /*!< 0x80000000 */
+#define OPAMP2_CSR_LOCK               OPAMP2_CSR_LOCK_Msk                      /*!< OPAMP lock */
+
+/*********************  Bit definition for OPAMP3_CSR register  ***************/
+#define OPAMP3_CSR_OPAMP3EN_Pos       (0U)                                     
+#define OPAMP3_CSR_OPAMP3EN_Msk       (0x1U << OPAMP3_CSR_OPAMP3EN_Pos)        /*!< 0x00000001 */
+#define OPAMP3_CSR_OPAMP3EN           OPAMP3_CSR_OPAMP3EN_Msk                  /*!< OPAMP3 enable */
+#define OPAMP3_CSR_FORCEVP_Pos        (1U)                                     
+#define OPAMP3_CSR_FORCEVP_Msk        (0x1U << OPAMP3_CSR_FORCEVP_Pos)         /*!< 0x00000002 */
+#define OPAMP3_CSR_FORCEVP            OPAMP3_CSR_FORCEVP_Msk                   /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP3_CSR_VPSEL_Pos          (2U)                                     
+#define OPAMP3_CSR_VPSEL_Msk          (0x3U << OPAMP3_CSR_VPSEL_Pos)           /*!< 0x0000000C */
+#define OPAMP3_CSR_VPSEL              OPAMP3_CSR_VPSEL_Msk                     /*!< Non inverting input selection */
+#define OPAMP3_CSR_VPSEL_0            (0x1U << OPAMP3_CSR_VPSEL_Pos)           /*!< 0x00000004 */
+#define OPAMP3_CSR_VPSEL_1            (0x2U << OPAMP3_CSR_VPSEL_Pos)           /*!< 0x00000008 */
+#define OPAMP3_CSR_VMSEL_Pos          (5U)                                     
+#define OPAMP3_CSR_VMSEL_Msk          (0x3U << OPAMP3_CSR_VMSEL_Pos)           /*!< 0x00000060 */
+#define OPAMP3_CSR_VMSEL              OPAMP3_CSR_VMSEL_Msk                     /*!< Inverting input selection */
+#define OPAMP3_CSR_VMSEL_0            (0x1U << OPAMP3_CSR_VMSEL_Pos)           /*!< 0x00000020 */
+#define OPAMP3_CSR_VMSEL_1            (0x2U << OPAMP3_CSR_VMSEL_Pos)           /*!< 0x00000040 */
+#define OPAMP3_CSR_TCMEN_Pos          (7U)                                     
+#define OPAMP3_CSR_TCMEN_Msk          (0x1U << OPAMP3_CSR_TCMEN_Pos)           /*!< 0x00000080 */
+#define OPAMP3_CSR_TCMEN              OPAMP3_CSR_TCMEN_Msk                     /*!< Timer-Controlled Mux mode enable */
+#define OPAMP3_CSR_VMSSEL_Pos         (8U)                                     
+#define OPAMP3_CSR_VMSSEL_Msk         (0x1U << OPAMP3_CSR_VMSSEL_Pos)          /*!< 0x00000100 */
+#define OPAMP3_CSR_VMSSEL             OPAMP3_CSR_VMSSEL_Msk                    /*!< Inverting input secondary selection */
+#define OPAMP3_CSR_VPSSEL_Pos         (9U)                                     
+#define OPAMP3_CSR_VPSSEL_Msk         (0x3U << OPAMP3_CSR_VPSSEL_Pos)          /*!< 0x00000600 */
+#define OPAMP3_CSR_VPSSEL             OPAMP3_CSR_VPSSEL_Msk                    /*!< Non inverting input secondary selection */
+#define OPAMP3_CSR_VPSSEL_0           (0x1U << OPAMP3_CSR_VPSSEL_Pos)          /*!< 0x00000200 */
+#define OPAMP3_CSR_VPSSEL_1           (0x2U << OPAMP3_CSR_VPSSEL_Pos)          /*!< 0x00000400 */
+#define OPAMP3_CSR_CALON_Pos          (11U)                                    
+#define OPAMP3_CSR_CALON_Msk          (0x1U << OPAMP3_CSR_CALON_Pos)           /*!< 0x00000800 */
+#define OPAMP3_CSR_CALON              OPAMP3_CSR_CALON_Msk                     /*!< Calibration mode enable */
+#define OPAMP3_CSR_CALSEL_Pos         (12U)                                    
+#define OPAMP3_CSR_CALSEL_Msk         (0x3U << OPAMP3_CSR_CALSEL_Pos)          /*!< 0x00003000 */
+#define OPAMP3_CSR_CALSEL             OPAMP3_CSR_CALSEL_Msk                    /*!< Calibration selection */
+#define OPAMP3_CSR_CALSEL_0           (0x1U << OPAMP3_CSR_CALSEL_Pos)          /*!< 0x00001000 */
+#define OPAMP3_CSR_CALSEL_1           (0x2U << OPAMP3_CSR_CALSEL_Pos)          /*!< 0x00002000 */
+#define OPAMP3_CSR_PGGAIN_Pos         (14U)                                    
+#define OPAMP3_CSR_PGGAIN_Msk         (0xFU << OPAMP3_CSR_PGGAIN_Pos)          /*!< 0x0003C000 */
+#define OPAMP3_CSR_PGGAIN             OPAMP3_CSR_PGGAIN_Msk                    /*!< Gain in PGA mode */
+#define OPAMP3_CSR_PGGAIN_0           (0x1U << OPAMP3_CSR_PGGAIN_Pos)          /*!< 0x00004000 */
+#define OPAMP3_CSR_PGGAIN_1           (0x2U << OPAMP3_CSR_PGGAIN_Pos)          /*!< 0x00008000 */
+#define OPAMP3_CSR_PGGAIN_2           (0x4U << OPAMP3_CSR_PGGAIN_Pos)          /*!< 0x00010000 */
+#define OPAMP3_CSR_PGGAIN_3           (0x8U << OPAMP3_CSR_PGGAIN_Pos)          /*!< 0x00020000 */
+#define OPAMP3_CSR_USERTRIM_Pos       (18U)                                    
+#define OPAMP3_CSR_USERTRIM_Msk       (0x1U << OPAMP3_CSR_USERTRIM_Pos)        /*!< 0x00040000 */
+#define OPAMP3_CSR_USERTRIM           OPAMP3_CSR_USERTRIM_Msk                  /*!< User trimming enable */
+#define OPAMP3_CSR_TRIMOFFSETP_Pos    (19U)                                    
+#define OPAMP3_CSR_TRIMOFFSETP_Msk    (0x1FU << OPAMP3_CSR_TRIMOFFSETP_Pos)    /*!< 0x00F80000 */
+#define OPAMP3_CSR_TRIMOFFSETP        OPAMP3_CSR_TRIMOFFSETP_Msk               /*!< Offset trimming value (PMOS) */
+#define OPAMP3_CSR_TRIMOFFSETN_Pos    (24U)                                    
+#define OPAMP3_CSR_TRIMOFFSETN_Msk    (0x1FU << OPAMP3_CSR_TRIMOFFSETN_Pos)    /*!< 0x1F000000 */
+#define OPAMP3_CSR_TRIMOFFSETN        OPAMP3_CSR_TRIMOFFSETN_Msk               /*!< Offset trimming value (NMOS) */
+#define OPAMP3_CSR_TSTREF_Pos         (29U)                                    
+#define OPAMP3_CSR_TSTREF_Msk         (0x1U << OPAMP3_CSR_TSTREF_Pos)          /*!< 0x20000000 */
+#define OPAMP3_CSR_TSTREF             OPAMP3_CSR_TSTREF_Msk                    /*!< It enables the switch to put out the internal reference */
+#define OPAMP3_CSR_OUTCAL_Pos         (30U)                                    
+#define OPAMP3_CSR_OUTCAL_Msk         (0x1U << OPAMP3_CSR_OUTCAL_Pos)          /*!< 0x40000000 */
+#define OPAMP3_CSR_OUTCAL             OPAMP3_CSR_OUTCAL_Msk                    /*!< OPAMP ouput status flag */
+#define OPAMP3_CSR_LOCK_Pos           (31U)                                    
+#define OPAMP3_CSR_LOCK_Msk           (0x1U << OPAMP3_CSR_LOCK_Pos)            /*!< 0x80000000 */
+#define OPAMP3_CSR_LOCK               OPAMP3_CSR_LOCK_Msk                      /*!< OPAMP lock */
+
+/*********************  Bit definition for OPAMP4_CSR register  ***************/
+#define OPAMP4_CSR_OPAMP4EN_Pos       (0U)                                     
+#define OPAMP4_CSR_OPAMP4EN_Msk       (0x1U << OPAMP4_CSR_OPAMP4EN_Pos)        /*!< 0x00000001 */
+#define OPAMP4_CSR_OPAMP4EN           OPAMP4_CSR_OPAMP4EN_Msk                  /*!< OPAMP4 enable */
+#define OPAMP4_CSR_FORCEVP_Pos        (1U)                                     
+#define OPAMP4_CSR_FORCEVP_Msk        (0x1U << OPAMP4_CSR_FORCEVP_Pos)         /*!< 0x00000002 */
+#define OPAMP4_CSR_FORCEVP            OPAMP4_CSR_FORCEVP_Msk                   /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP4_CSR_VPSEL_Pos          (2U)                                     
+#define OPAMP4_CSR_VPSEL_Msk          (0x3U << OPAMP4_CSR_VPSEL_Pos)           /*!< 0x0000000C */
+#define OPAMP4_CSR_VPSEL              OPAMP4_CSR_VPSEL_Msk                     /*!< Non inverting input selection */
+#define OPAMP4_CSR_VPSEL_0            (0x1U << OPAMP4_CSR_VPSEL_Pos)           /*!< 0x00000004 */
+#define OPAMP4_CSR_VPSEL_1            (0x2U << OPAMP4_CSR_VPSEL_Pos)           /*!< 0x00000008 */
+#define OPAMP4_CSR_VMSEL_Pos          (5U)                                     
+#define OPAMP4_CSR_VMSEL_Msk          (0x3U << OPAMP4_CSR_VMSEL_Pos)           /*!< 0x00000060 */
+#define OPAMP4_CSR_VMSEL              OPAMP4_CSR_VMSEL_Msk                     /*!< Inverting input selection */
+#define OPAMP4_CSR_VMSEL_0            (0x1U << OPAMP4_CSR_VMSEL_Pos)           /*!< 0x00000020 */
+#define OPAMP4_CSR_VMSEL_1            (0x2U << OPAMP4_CSR_VMSEL_Pos)           /*!< 0x00000040 */
+#define OPAMP4_CSR_TCMEN_Pos          (7U)                                     
+#define OPAMP4_CSR_TCMEN_Msk          (0x1U << OPAMP4_CSR_TCMEN_Pos)           /*!< 0x00000080 */
+#define OPAMP4_CSR_TCMEN              OPAMP4_CSR_TCMEN_Msk                     /*!< Timer-Controlled Mux mode enable */
+#define OPAMP4_CSR_VMSSEL_Pos         (8U)                                     
+#define OPAMP4_CSR_VMSSEL_Msk         (0x1U << OPAMP4_CSR_VMSSEL_Pos)          /*!< 0x00000100 */
+#define OPAMP4_CSR_VMSSEL             OPAMP4_CSR_VMSSEL_Msk                    /*!< Inverting input secondary selection */
+#define OPAMP4_CSR_VPSSEL_Pos         (9U)                                     
+#define OPAMP4_CSR_VPSSEL_Msk         (0x3U << OPAMP4_CSR_VPSSEL_Pos)          /*!< 0x00000600 */
+#define OPAMP4_CSR_VPSSEL             OPAMP4_CSR_VPSSEL_Msk                    /*!< Non inverting input secondary selection */
+#define OPAMP4_CSR_VPSSEL_0           (0x1U << OPAMP4_CSR_VPSSEL_Pos)          /*!< 0x00000200 */
+#define OPAMP4_CSR_VPSSEL_1           (0x2U << OPAMP4_CSR_VPSSEL_Pos)          /*!< 0x00000400 */
+#define OPAMP4_CSR_CALON_Pos          (11U)                                    
+#define OPAMP4_CSR_CALON_Msk          (0x1U << OPAMP4_CSR_CALON_Pos)           /*!< 0x00000800 */
+#define OPAMP4_CSR_CALON              OPAMP4_CSR_CALON_Msk                     /*!< Calibration mode enable */
+#define OPAMP4_CSR_CALSEL_Pos         (12U)                                    
+#define OPAMP4_CSR_CALSEL_Msk         (0x3U << OPAMP4_CSR_CALSEL_Pos)          /*!< 0x00003000 */
+#define OPAMP4_CSR_CALSEL             OPAMP4_CSR_CALSEL_Msk                    /*!< Calibration selection */
+#define OPAMP4_CSR_CALSEL_0           (0x1U << OPAMP4_CSR_CALSEL_Pos)          /*!< 0x00001000 */
+#define OPAMP4_CSR_CALSEL_1           (0x2U << OPAMP4_CSR_CALSEL_Pos)          /*!< 0x00002000 */
+#define OPAMP4_CSR_PGGAIN_Pos         (14U)                                    
+#define OPAMP4_CSR_PGGAIN_Msk         (0xFU << OPAMP4_CSR_PGGAIN_Pos)          /*!< 0x0003C000 */
+#define OPAMP4_CSR_PGGAIN             OPAMP4_CSR_PGGAIN_Msk                    /*!< Gain in PGA mode */
+#define OPAMP4_CSR_PGGAIN_0           (0x1U << OPAMP4_CSR_PGGAIN_Pos)          /*!< 0x00004000 */
+#define OPAMP4_CSR_PGGAIN_1           (0x2U << OPAMP4_CSR_PGGAIN_Pos)          /*!< 0x00008000 */
+#define OPAMP4_CSR_PGGAIN_2           (0x4U << OPAMP4_CSR_PGGAIN_Pos)          /*!< 0x00010000 */
+#define OPAMP4_CSR_PGGAIN_3           (0x8U << OPAMP4_CSR_PGGAIN_Pos)          /*!< 0x00020000 */
+#define OPAMP4_CSR_USERTRIM_Pos       (18U)                                    
+#define OPAMP4_CSR_USERTRIM_Msk       (0x1U << OPAMP4_CSR_USERTRIM_Pos)        /*!< 0x00040000 */
+#define OPAMP4_CSR_USERTRIM           OPAMP4_CSR_USERTRIM_Msk                  /*!< User trimming enable */
+#define OPAMP4_CSR_TRIMOFFSETP_Pos    (19U)                                    
+#define OPAMP4_CSR_TRIMOFFSETP_Msk    (0x1FU << OPAMP4_CSR_TRIMOFFSETP_Pos)    /*!< 0x00F80000 */
+#define OPAMP4_CSR_TRIMOFFSETP        OPAMP4_CSR_TRIMOFFSETP_Msk               /*!< Offset trimming value (PMOS) */
+#define OPAMP4_CSR_TRIMOFFSETN_Pos    (24U)                                    
+#define OPAMP4_CSR_TRIMOFFSETN_Msk    (0x1FU << OPAMP4_CSR_TRIMOFFSETN_Pos)    /*!< 0x1F000000 */
+#define OPAMP4_CSR_TRIMOFFSETN        OPAMP4_CSR_TRIMOFFSETN_Msk               /*!< Offset trimming value (NMOS) */
+#define OPAMP4_CSR_TSTREF_Pos         (29U)                                    
+#define OPAMP4_CSR_TSTREF_Msk         (0x1U << OPAMP4_CSR_TSTREF_Pos)          /*!< 0x20000000 */
+#define OPAMP4_CSR_TSTREF             OPAMP4_CSR_TSTREF_Msk                    /*!< It enables the switch to put out the internal reference */
+#define OPAMP4_CSR_OUTCAL_Pos         (30U)                                    
+#define OPAMP4_CSR_OUTCAL_Msk         (0x1U << OPAMP4_CSR_OUTCAL_Pos)          /*!< 0x40000000 */
+#define OPAMP4_CSR_OUTCAL             OPAMP4_CSR_OUTCAL_Msk                    /*!< OPAMP ouput status flag */
+#define OPAMP4_CSR_LOCK_Pos           (31U)                                    
+#define OPAMP4_CSR_LOCK_Msk           (0x1U << OPAMP4_CSR_LOCK_Pos)            /*!< 0x80000000 */
+#define OPAMP4_CSR_LOCK               OPAMP4_CSR_LOCK_Msk                      /*!< OPAMP lock */
+
+/*********************  Bit definition for OPAMPx_CSR register  ***************/
+#define OPAMP_CSR_OPAMPxEN_Pos       (0U)                                      
+#define OPAMP_CSR_OPAMPxEN_Msk       (0x1U << OPAMP_CSR_OPAMPxEN_Pos)          /*!< 0x00000001 */
+#define OPAMP_CSR_OPAMPxEN           OPAMP_CSR_OPAMPxEN_Msk                    /*!< OPAMP enable */
+#define OPAMP_CSR_FORCEVP_Pos        (1U)                                      
+#define OPAMP_CSR_FORCEVP_Msk        (0x1U << OPAMP_CSR_FORCEVP_Pos)           /*!< 0x00000002 */
+#define OPAMP_CSR_FORCEVP            OPAMP_CSR_FORCEVP_Msk                     /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP_CSR_VPSEL_Pos          (2U)                                      
+#define OPAMP_CSR_VPSEL_Msk          (0x3U << OPAMP_CSR_VPSEL_Pos)             /*!< 0x0000000C */
+#define OPAMP_CSR_VPSEL              OPAMP_CSR_VPSEL_Msk                       /*!< Non inverting input selection */
+#define OPAMP_CSR_VPSEL_0            (0x1U << OPAMP_CSR_VPSEL_Pos)             /*!< 0x00000004 */
+#define OPAMP_CSR_VPSEL_1            (0x2U << OPAMP_CSR_VPSEL_Pos)             /*!< 0x00000008 */
+#define OPAMP_CSR_VMSEL_Pos          (5U)                                      
+#define OPAMP_CSR_VMSEL_Msk          (0x3U << OPAMP_CSR_VMSEL_Pos)             /*!< 0x00000060 */
+#define OPAMP_CSR_VMSEL              OPAMP_CSR_VMSEL_Msk                       /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0            (0x1U << OPAMP_CSR_VMSEL_Pos)             /*!< 0x00000020 */
+#define OPAMP_CSR_VMSEL_1            (0x2U << OPAMP_CSR_VMSEL_Pos)             /*!< 0x00000040 */
+#define OPAMP_CSR_TCMEN_Pos          (7U)                                      
+#define OPAMP_CSR_TCMEN_Msk          (0x1U << OPAMP_CSR_TCMEN_Pos)             /*!< 0x00000080 */
+#define OPAMP_CSR_TCMEN              OPAMP_CSR_TCMEN_Msk                       /*!< Timer-Controlled Mux mode enable */
+#define OPAMP_CSR_VMSSEL_Pos         (8U)                                      
+#define OPAMP_CSR_VMSSEL_Msk         (0x1U << OPAMP_CSR_VMSSEL_Pos)            /*!< 0x00000100 */
+#define OPAMP_CSR_VMSSEL             OPAMP_CSR_VMSSEL_Msk                      /*!< Inverting input secondary selection */
+#define OPAMP_CSR_VPSSEL_Pos         (9U)                                      
+#define OPAMP_CSR_VPSSEL_Msk         (0x3U << OPAMP_CSR_VPSSEL_Pos)            /*!< 0x00000600 */
+#define OPAMP_CSR_VPSSEL             OPAMP_CSR_VPSSEL_Msk                      /*!< Non inverting input secondary selection */
+#define OPAMP_CSR_VPSSEL_0           (0x1U << OPAMP_CSR_VPSSEL_Pos)            /*!< 0x00000200 */
+#define OPAMP_CSR_VPSSEL_1           (0x2U << OPAMP_CSR_VPSSEL_Pos)            /*!< 0x00000400 */
+#define OPAMP_CSR_CALON_Pos          (11U)                                     
+#define OPAMP_CSR_CALON_Msk          (0x1U << OPAMP_CSR_CALON_Pos)             /*!< 0x00000800 */
+#define OPAMP_CSR_CALON              OPAMP_CSR_CALON_Msk                       /*!< Calibration mode enable */
+#define OPAMP_CSR_CALSEL_Pos         (12U)                                     
+#define OPAMP_CSR_CALSEL_Msk         (0x3U << OPAMP_CSR_CALSEL_Pos)            /*!< 0x00003000 */
+#define OPAMP_CSR_CALSEL             OPAMP_CSR_CALSEL_Msk                      /*!< Calibration selection */
+#define OPAMP_CSR_CALSEL_0           (0x1U << OPAMP_CSR_CALSEL_Pos)            /*!< 0x00001000 */
+#define OPAMP_CSR_CALSEL_1           (0x2U << OPAMP_CSR_CALSEL_Pos)            /*!< 0x00002000 */
+#define OPAMP_CSR_PGGAIN_Pos         (14U)                                     
+#define OPAMP_CSR_PGGAIN_Msk         (0xFU << OPAMP_CSR_PGGAIN_Pos)            /*!< 0x0003C000 */
+#define OPAMP_CSR_PGGAIN             OPAMP_CSR_PGGAIN_Msk                      /*!< Gain in PGA mode */
+#define OPAMP_CSR_PGGAIN_0           (0x1U << OPAMP_CSR_PGGAIN_Pos)            /*!< 0x00004000 */
+#define OPAMP_CSR_PGGAIN_1           (0x2U << OPAMP_CSR_PGGAIN_Pos)            /*!< 0x00008000 */
+#define OPAMP_CSR_PGGAIN_2           (0x4U << OPAMP_CSR_PGGAIN_Pos)            /*!< 0x00010000 */
+#define OPAMP_CSR_PGGAIN_3           (0x8U << OPAMP_CSR_PGGAIN_Pos)            /*!< 0x00020000 */
+#define OPAMP_CSR_USERTRIM_Pos       (18U)                                     
+#define OPAMP_CSR_USERTRIM_Msk       (0x1U << OPAMP_CSR_USERTRIM_Pos)          /*!< 0x00040000 */
+#define OPAMP_CSR_USERTRIM           OPAMP_CSR_USERTRIM_Msk                    /*!< User trimming enable */
+#define OPAMP_CSR_TRIMOFFSETP_Pos    (19U)                                     
+#define OPAMP_CSR_TRIMOFFSETP_Msk    (0x1FU << OPAMP_CSR_TRIMOFFSETP_Pos)      /*!< 0x00F80000 */
+#define OPAMP_CSR_TRIMOFFSETP        OPAMP_CSR_TRIMOFFSETP_Msk                 /*!< Offset trimming value (PMOS) */
+#define OPAMP_CSR_TRIMOFFSETN_Pos    (24U)                                     
+#define OPAMP_CSR_TRIMOFFSETN_Msk    (0x1FU << OPAMP_CSR_TRIMOFFSETN_Pos)      /*!< 0x1F000000 */
+#define OPAMP_CSR_TRIMOFFSETN        OPAMP_CSR_TRIMOFFSETN_Msk                 /*!< Offset trimming value (NMOS) */
+#define OPAMP_CSR_TSTREF_Pos         (29U)                                     
+#define OPAMP_CSR_TSTREF_Msk         (0x1U << OPAMP_CSR_TSTREF_Pos)            /*!< 0x20000000 */
+#define OPAMP_CSR_TSTREF             OPAMP_CSR_TSTREF_Msk                      /*!< It enables the switch to put out the internal reference */
+#define OPAMP_CSR_OUTCAL_Pos         (30U)                                     
+#define OPAMP_CSR_OUTCAL_Msk         (0x1U << OPAMP_CSR_OUTCAL_Pos)            /*!< 0x40000000 */
+#define OPAMP_CSR_OUTCAL             OPAMP_CSR_OUTCAL_Msk                      /*!< OPAMP ouput status flag */
+#define OPAMP_CSR_LOCK_Pos           (31U)                                     
+#define OPAMP_CSR_LOCK_Msk           (0x1U << OPAMP_CSR_LOCK_Pos)              /*!< 0x80000000 */
+#define OPAMP_CSR_LOCK               OPAMP_CSR_LOCK_Msk                        /*!< OPAMP lock */
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Controller Area Network (CAN )                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define CAN_MCR_INRQ_Pos       (0U)                                            
+#define CAN_MCR_INRQ_Msk       (0x1U << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
+#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos      (1U)                                            
+#define CAN_MCR_SLEEP_Msk      (0x1U << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
+#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos       (2U)                                            
+#define CAN_MCR_TXFP_Msk       (0x1U << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
+#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos       (3U)                                            
+#define CAN_MCR_RFLM_Msk       (0x1U << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
+#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos       (4U)                                            
+#define CAN_MCR_NART_Msk       (0x1U << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
+#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos       (5U)                                            
+#define CAN_MCR_AWUM_Msk       (0x1U << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
+#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos       (6U)                                            
+#define CAN_MCR_ABOM_Msk       (0x1U << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
+#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos       (7U)                                            
+#define CAN_MCR_TTCM_Msk       (0x1U << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
+#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos      (15U)                                           
+#define CAN_MCR_RESET_Msk      (0x1U << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
+#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
+
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define CAN_MSR_INAK_Pos       (0U)                                            
+#define CAN_MSR_INAK_Msk       (0x1U << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
+#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos       (1U)                                            
+#define CAN_MSR_SLAK_Msk       (0x1U << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
+#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos       (2U)                                            
+#define CAN_MSR_ERRI_Msk       (0x1U << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
+#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos       (3U)                                            
+#define CAN_MSR_WKUI_Msk       (0x1U << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
+#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos      (4U)                                            
+#define CAN_MSR_SLAKI_Msk      (0x1U << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
+#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos        (8U)                                            
+#define CAN_MSR_TXM_Msk        (0x1U << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
+#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos        (9U)                                            
+#define CAN_MSR_RXM_Msk        (0x1U << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
+#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos       (10U)                                           
+#define CAN_MSR_SAMP_Msk       (0x1U << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
+#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos         (11U)                                           
+#define CAN_MSR_RX_Msk         (0x1U << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
+#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define CAN_TSR_RQCP0_Pos      (0U)                                            
+#define CAN_TSR_RQCP0_Msk      (0x1U << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
+#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos      (1U)                                            
+#define CAN_TSR_TXOK0_Msk      (0x1U << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
+#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos      (2U)                                            
+#define CAN_TSR_ALST0_Msk      (0x1U << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
+#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos      (3U)                                            
+#define CAN_TSR_TERR0_Msk      (0x1U << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
+#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos      (7U)                                            
+#define CAN_TSR_ABRQ0_Msk      (0x1U << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos      (8U)                                            
+#define CAN_TSR_RQCP1_Msk      (0x1U << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
+#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos      (9U)                                            
+#define CAN_TSR_TXOK1_Msk      (0x1U << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
+#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos      (10U)                                           
+#define CAN_TSR_ALST1_Msk      (0x1U << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
+#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos      (11U)                                           
+#define CAN_TSR_TERR1_Msk      (0x1U << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
+#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos      (15U)                                           
+#define CAN_TSR_ABRQ1_Msk      (0x1U << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos      (16U)                                           
+#define CAN_TSR_RQCP2_Msk      (0x1U << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
+#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos      (17U)                                           
+#define CAN_TSR_TXOK2_Msk      (0x1U << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
+#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos      (18U)                                           
+#define CAN_TSR_ALST2_Msk      (0x1U << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
+#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos      (19U)                                           
+#define CAN_TSR_TERR2_Msk      (0x1U << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
+#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos      (23U)                                           
+#define CAN_TSR_ABRQ2_Msk      (0x1U << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos       (24U)                                           
+#define CAN_TSR_CODE_Msk       (0x3U << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
+#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos        (26U)                                           
+#define CAN_TSR_TME_Msk        (0x7U << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
+#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos       (26U)                                           
+#define CAN_TSR_TME0_Msk       (0x1U << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
+#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos       (27U)                                           
+#define CAN_TSR_TME1_Msk       (0x1U << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
+#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos       (28U)                                           
+#define CAN_TSR_TME2_Msk       (0x1U << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
+#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos        (29U)                                           
+#define CAN_TSR_LOW_Msk        (0x7U << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
+#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos       (29U)                                           
+#define CAN_TSR_LOW0_Msk       (0x1U << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
+#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos       (30U)                                           
+#define CAN_TSR_LOW1_Msk       (0x1U << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
+#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos       (31U)                                           
+#define CAN_TSR_LOW2_Msk       (0x1U << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
+#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define CAN_RF0R_FMP0_Pos      (0U)                                            
+#define CAN_RF0R_FMP0_Msk      (0x3U << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
+#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos     (3U)                                            
+#define CAN_RF0R_FULL0_Msk     (0x1U << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
+#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos     (4U)                                            
+#define CAN_RF0R_FOVR0_Msk     (0x1U << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos     (5U)                                            
+#define CAN_RF0R_RFOM0_Msk     (0x1U << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define CAN_RF1R_FMP1_Pos      (0U)                                            
+#define CAN_RF1R_FMP1_Msk      (0x3U << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
+#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos     (3U)                                            
+#define CAN_RF1R_FULL1_Msk     (0x1U << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
+#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos     (4U)                                            
+#define CAN_RF1R_FOVR1_Msk     (0x1U << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos     (5U)                                            
+#define CAN_RF1R_RFOM1_Msk     (0x1U << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define CAN_IER_TMEIE_Pos      (0U)                                            
+#define CAN_IER_TMEIE_Msk      (0x1U << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
+#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos     (1U)                                            
+#define CAN_IER_FMPIE0_Msk     (0x1U << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
+#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos      (2U)                                            
+#define CAN_IER_FFIE0_Msk      (0x1U << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
+#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos     (3U)                                            
+#define CAN_IER_FOVIE0_Msk     (0x1U << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
+#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos     (4U)                                            
+#define CAN_IER_FMPIE1_Msk     (0x1U << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
+#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos      (5U)                                            
+#define CAN_IER_FFIE1_Msk      (0x1U << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
+#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos     (6U)                                            
+#define CAN_IER_FOVIE1_Msk     (0x1U << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
+#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos      (8U)                                            
+#define CAN_IER_EWGIE_Msk      (0x1U << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
+#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos      (9U)                                            
+#define CAN_IER_EPVIE_Msk      (0x1U << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
+#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos      (10U)                                           
+#define CAN_IER_BOFIE_Msk      (0x1U << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
+#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos      (11U)                                           
+#define CAN_IER_LECIE_Msk      (0x1U << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
+#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos      (15U)                                           
+#define CAN_IER_ERRIE_Msk      (0x1U << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
+#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos      (16U)                                           
+#define CAN_IER_WKUIE_Msk      (0x1U << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
+#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos      (17U)                                           
+#define CAN_IER_SLKIE_Msk      (0x1U << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
+#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define CAN_ESR_EWGF_Pos       (0U)                                            
+#define CAN_ESR_EWGF_Msk       (0x1U << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
+#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos       (1U)                                            
+#define CAN_ESR_EPVF_Msk       (0x1U << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
+#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos       (2U)                                            
+#define CAN_ESR_BOFF_Msk       (0x1U << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
+#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos        (4U)                                            
+#define CAN_ESR_LEC_Msk        (0x7U << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
+#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0          (0x1U << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
+#define CAN_ESR_LEC_1          (0x2U << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
+#define CAN_ESR_LEC_2          (0x4U << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos        (16U)                                           
+#define CAN_ESR_TEC_Msk        (0xFFU << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
+#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos        (24U)                                           
+#define CAN_ESR_REC_Msk        (0xFFU << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
+#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define CAN_BTR_BRP_Pos        (0U)                                            
+#define CAN_BTR_BRP_Msk        (0x3FFU << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
+#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos        (16U)                                           
+#define CAN_BTR_TS1_Msk        (0xFU << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
+#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0          (0x1U << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
+#define CAN_BTR_TS1_1          (0x2U << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
+#define CAN_BTR_TS1_2          (0x4U << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
+#define CAN_BTR_TS1_3          (0x8U << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos        (20U)                                           
+#define CAN_BTR_TS2_Msk        (0x7U << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
+#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0          (0x1U << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
+#define CAN_BTR_TS2_1          (0x2U << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
+#define CAN_BTR_TS2_2          (0x4U << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos        (24U)                                           
+#define CAN_BTR_SJW_Msk        (0x3U << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
+#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0          (0x1U << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
+#define CAN_BTR_SJW_1          (0x2U << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos       (30U)                                           
+#define CAN_BTR_LBKM_Msk       (0x1U << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
+#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos       (31U)                                           
+#define CAN_BTR_SILM_Msk       (0x1U << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
+#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define CAN_TI0R_TXRQ_Pos      (0U)                                            
+#define CAN_TI0R_TXRQ_Msk      (0x1U << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos       (1U)                                            
+#define CAN_TI0R_RTR_Msk       (0x1U << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos       (2U)                                            
+#define CAN_TI0R_IDE_Msk       (0x1U << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos      (3U)                                            
+#define CAN_TI0R_EXID_Msk      (0x3FFFFU << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos      (21U)                                           
+#define CAN_TI0R_STID_Msk      (0x7FFU << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define CAN_TDT0R_DLC_Pos      (0U)                                            
+#define CAN_TDT0R_DLC_Msk      (0xFU << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos      (8U)                                            
+#define CAN_TDT0R_TGT_Msk      (0x1U << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos     (16U)                                           
+#define CAN_TDT0R_TIME_Msk     (0xFFFFU << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define CAN_TDL0R_DATA0_Pos    (0U)                                            
+#define CAN_TDL0R_DATA0_Msk    (0xFFU << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos    (8U)                                            
+#define CAN_TDL0R_DATA1_Msk    (0xFFU << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos    (16U)                                           
+#define CAN_TDL0R_DATA2_Msk    (0xFFU << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos    (24U)                                           
+#define CAN_TDL0R_DATA3_Msk    (0xFFU << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define CAN_TDH0R_DATA4_Pos    (0U)                                            
+#define CAN_TDH0R_DATA4_Msk    (0xFFU << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos    (8U)                                            
+#define CAN_TDH0R_DATA5_Msk    (0xFFU << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos    (16U)                                           
+#define CAN_TDH0R_DATA6_Msk    (0xFFU << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos    (24U)                                           
+#define CAN_TDH0R_DATA7_Msk    (0xFFU << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define CAN_TI1R_TXRQ_Pos      (0U)                                            
+#define CAN_TI1R_TXRQ_Msk      (0x1U << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos       (1U)                                            
+#define CAN_TI1R_RTR_Msk       (0x1U << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos       (2U)                                            
+#define CAN_TI1R_IDE_Msk       (0x1U << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos      (3U)                                            
+#define CAN_TI1R_EXID_Msk      (0x3FFFFU << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos      (21U)                                           
+#define CAN_TI1R_STID_Msk      (0x7FFU << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define CAN_TDT1R_DLC_Pos      (0U)                                            
+#define CAN_TDT1R_DLC_Msk      (0xFU << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos      (8U)                                            
+#define CAN_TDT1R_TGT_Msk      (0x1U << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos     (16U)                                           
+#define CAN_TDT1R_TIME_Msk     (0xFFFFU << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define CAN_TDL1R_DATA0_Pos    (0U)                                            
+#define CAN_TDL1R_DATA0_Msk    (0xFFU << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos    (8U)                                            
+#define CAN_TDL1R_DATA1_Msk    (0xFFU << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos    (16U)                                           
+#define CAN_TDL1R_DATA2_Msk    (0xFFU << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos    (24U)                                           
+#define CAN_TDL1R_DATA3_Msk    (0xFFU << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define CAN_TDH1R_DATA4_Pos    (0U)                                            
+#define CAN_TDH1R_DATA4_Msk    (0xFFU << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos    (8U)                                            
+#define CAN_TDH1R_DATA5_Msk    (0xFFU << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos    (16U)                                           
+#define CAN_TDH1R_DATA6_Msk    (0xFFU << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos    (24U)                                           
+#define CAN_TDH1R_DATA7_Msk    (0xFFU << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define CAN_TI2R_TXRQ_Pos      (0U)                                            
+#define CAN_TI2R_TXRQ_Msk      (0x1U << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos       (1U)                                            
+#define CAN_TI2R_RTR_Msk       (0x1U << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos       (2U)                                            
+#define CAN_TI2R_IDE_Msk       (0x1U << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos      (3U)                                            
+#define CAN_TI2R_EXID_Msk      (0x3FFFFU << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos      (21U)                                           
+#define CAN_TI2R_STID_Msk      (0x7FFU << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/
+#define CAN_TDT2R_DLC_Pos      (0U)                                            
+#define CAN_TDT2R_DLC_Msk      (0xFU << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos      (8U)                                            
+#define CAN_TDT2R_TGT_Msk      (0x1U << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos     (16U)                                           
+#define CAN_TDT2R_TIME_Msk     (0xFFFFU << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define CAN_TDL2R_DATA0_Pos    (0U)                                            
+#define CAN_TDL2R_DATA0_Msk    (0xFFU << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos    (8U)                                            
+#define CAN_TDL2R_DATA1_Msk    (0xFFU << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos    (16U)                                           
+#define CAN_TDL2R_DATA2_Msk    (0xFFU << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos    (24U)                                           
+#define CAN_TDL2R_DATA3_Msk    (0xFFU << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define CAN_TDH2R_DATA4_Pos    (0U)                                            
+#define CAN_TDH2R_DATA4_Msk    (0xFFU << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos    (8U)                                            
+#define CAN_TDH2R_DATA5_Msk    (0xFFU << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos    (16U)                                           
+#define CAN_TDH2R_DATA6_Msk    (0xFFU << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos    (24U)                                           
+#define CAN_TDH2R_DATA7_Msk    (0xFFU << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define CAN_RI0R_RTR_Pos       (1U)                                            
+#define CAN_RI0R_RTR_Msk       (0x1U << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos       (2U)                                            
+#define CAN_RI0R_IDE_Msk       (0x1U << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos      (3U)                                            
+#define CAN_RI0R_EXID_Msk      (0x3FFFFU << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos      (21U)                                           
+#define CAN_RI0R_STID_Msk      (0x7FFU << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define CAN_RDT0R_DLC_Pos      (0U)                                            
+#define CAN_RDT0R_DLC_Msk      (0xFU << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos      (8U)                                            
+#define CAN_RDT0R_FMI_Msk      (0xFFU << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos     (16U)                                           
+#define CAN_RDT0R_TIME_Msk     (0xFFFFU << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define CAN_RDL0R_DATA0_Pos    (0U)                                            
+#define CAN_RDL0R_DATA0_Msk    (0xFFU << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos    (8U)                                            
+#define CAN_RDL0R_DATA1_Msk    (0xFFU << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos    (16U)                                           
+#define CAN_RDL0R_DATA2_Msk    (0xFFU << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos    (24U)                                           
+#define CAN_RDL0R_DATA3_Msk    (0xFFU << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define CAN_RDH0R_DATA4_Pos    (0U)                                            
+#define CAN_RDH0R_DATA4_Msk    (0xFFU << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos    (8U)                                            
+#define CAN_RDH0R_DATA5_Msk    (0xFFU << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos    (16U)                                           
+#define CAN_RDH0R_DATA6_Msk    (0xFFU << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos    (24U)                                           
+#define CAN_RDH0R_DATA7_Msk    (0xFFU << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define CAN_RI1R_RTR_Pos       (1U)                                            
+#define CAN_RI1R_RTR_Msk       (0x1U << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos       (2U)                                            
+#define CAN_RI1R_IDE_Msk       (0x1U << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos      (3U)                                            
+#define CAN_RI1R_EXID_Msk      (0x3FFFFU << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos      (21U)                                           
+#define CAN_RI1R_STID_Msk      (0x7FFU << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define CAN_RDT1R_DLC_Pos      (0U)                                            
+#define CAN_RDT1R_DLC_Msk      (0xFU << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos      (8U)                                            
+#define CAN_RDT1R_FMI_Msk      (0xFFU << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos     (16U)                                           
+#define CAN_RDT1R_TIME_Msk     (0xFFFFU << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define CAN_RDL1R_DATA0_Pos    (0U)                                            
+#define CAN_RDL1R_DATA0_Msk    (0xFFU << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos    (8U)                                            
+#define CAN_RDL1R_DATA1_Msk    (0xFFU << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos    (16U)                                           
+#define CAN_RDL1R_DATA2_Msk    (0xFFU << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos    (24U)                                           
+#define CAN_RDL1R_DATA3_Msk    (0xFFU << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define CAN_RDH1R_DATA4_Pos    (0U)                                            
+#define CAN_RDH1R_DATA4_Msk    (0xFFU << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos    (8U)                                            
+#define CAN_RDH1R_DATA5_Msk    (0xFFU << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos    (16U)                                           
+#define CAN_RDH1R_DATA6_Msk    (0xFFU << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos    (24U)                                           
+#define CAN_RDH1R_DATA7_Msk    (0xFFU << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define CAN_FMR_FINIT_Pos      (0U)                                            
+#define CAN_FMR_FINIT_Msk      (0x1U << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
+#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define CAN_FM1R_FBM_Pos       (0U)                                            
+#define CAN_FM1R_FBM_Msk       (0x3FFFU << CAN_FM1R_FBM_Pos)                   /*!< 0x00003FFF */
+#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos      (0U)                                            
+#define CAN_FM1R_FBM0_Msk      (0x1U << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
+#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos      (1U)                                            
+#define CAN_FM1R_FBM1_Msk      (0x1U << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
+#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos      (2U)                                            
+#define CAN_FM1R_FBM2_Msk      (0x1U << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
+#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos      (3U)                                            
+#define CAN_FM1R_FBM3_Msk      (0x1U << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
+#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos      (4U)                                            
+#define CAN_FM1R_FBM4_Msk      (0x1U << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
+#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos      (5U)                                            
+#define CAN_FM1R_FBM5_Msk      (0x1U << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
+#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos      (6U)                                            
+#define CAN_FM1R_FBM6_Msk      (0x1U << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
+#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos      (7U)                                            
+#define CAN_FM1R_FBM7_Msk      (0x1U << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
+#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos      (8U)                                            
+#define CAN_FM1R_FBM8_Msk      (0x1U << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
+#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos      (9U)                                            
+#define CAN_FM1R_FBM9_Msk      (0x1U << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
+#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos     (10U)                                           
+#define CAN_FM1R_FBM10_Msk     (0x1U << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
+#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos     (11U)                                           
+#define CAN_FM1R_FBM11_Msk     (0x1U << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
+#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos     (12U)                                           
+#define CAN_FM1R_FBM12_Msk     (0x1U << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
+#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos     (13U)                                           
+#define CAN_FM1R_FBM13_Msk     (0x1U << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
+#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define CAN_FS1R_FSC_Pos       (0U)                                            
+#define CAN_FS1R_FSC_Msk       (0x3FFFU << CAN_FS1R_FSC_Pos)                   /*!< 0x00003FFF */
+#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos      (0U)                                            
+#define CAN_FS1R_FSC0_Msk      (0x1U << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
+#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos      (1U)                                            
+#define CAN_FS1R_FSC1_Msk      (0x1U << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
+#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos      (2U)                                            
+#define CAN_FS1R_FSC2_Msk      (0x1U << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
+#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos      (3U)                                            
+#define CAN_FS1R_FSC3_Msk      (0x1U << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
+#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos      (4U)                                            
+#define CAN_FS1R_FSC4_Msk      (0x1U << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
+#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos      (5U)                                            
+#define CAN_FS1R_FSC5_Msk      (0x1U << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
+#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos      (6U)                                            
+#define CAN_FS1R_FSC6_Msk      (0x1U << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
+#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos      (7U)                                            
+#define CAN_FS1R_FSC7_Msk      (0x1U << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
+#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos      (8U)                                            
+#define CAN_FS1R_FSC8_Msk      (0x1U << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
+#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos      (9U)                                            
+#define CAN_FS1R_FSC9_Msk      (0x1U << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
+#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos     (10U)                                           
+#define CAN_FS1R_FSC10_Msk     (0x1U << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
+#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos     (11U)                                           
+#define CAN_FS1R_FSC11_Msk     (0x1U << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
+#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos     (12U)                                           
+#define CAN_FS1R_FSC12_Msk     (0x1U << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
+#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos     (13U)                                           
+#define CAN_FS1R_FSC13_Msk     (0x1U << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
+#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define CAN_FFA1R_FFA_Pos      (0U)                                            
+#define CAN_FFA1R_FFA_Msk      (0x3FFFU << CAN_FFA1R_FFA_Pos)                  /*!< 0x00003FFF */
+#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos     (0U)                                            
+#define CAN_FFA1R_FFA0_Msk     (0x1U << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1_Pos     (1U)                                            
+#define CAN_FFA1R_FFA1_Msk     (0x1U << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2_Pos     (2U)                                            
+#define CAN_FFA1R_FFA2_Msk     (0x1U << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3_Pos     (3U)                                            
+#define CAN_FFA1R_FFA3_Msk     (0x1U << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4_Pos     (4U)                                            
+#define CAN_FFA1R_FFA4_Msk     (0x1U << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5_Pos     (5U)                                            
+#define CAN_FFA1R_FFA5_Msk     (0x1U << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6_Pos     (6U)                                            
+#define CAN_FFA1R_FFA6_Msk     (0x1U << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7_Pos     (7U)                                            
+#define CAN_FFA1R_FFA7_Msk     (0x1U << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8_Pos     (8U)                                            
+#define CAN_FFA1R_FFA8_Msk     (0x1U << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9_Pos     (9U)                                            
+#define CAN_FFA1R_FFA9_Msk     (0x1U << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10_Pos    (10U)                                           
+#define CAN_FFA1R_FFA10_Msk    (0x1U << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11_Pos    (11U)                                           
+#define CAN_FFA1R_FFA11_Msk    (0x1U << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12_Pos    (12U)                                           
+#define CAN_FFA1R_FFA12_Msk    (0x1U << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13_Pos    (13U)                                           
+#define CAN_FFA1R_FFA13_Msk    (0x1U << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define CAN_FA1R_FACT_Pos      (0U)                                            
+#define CAN_FA1R_FACT_Msk      (0x3FFFU << CAN_FA1R_FACT_Pos)                  /*!< 0x00003FFF */
+#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos     (0U)                                            
+#define CAN_FA1R_FACT0_Msk     (0x1U << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
+#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1_Pos     (1U)                                            
+#define CAN_FA1R_FACT1_Msk     (0x1U << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
+#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2_Pos     (2U)                                            
+#define CAN_FA1R_FACT2_Msk     (0x1U << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
+#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3_Pos     (3U)                                            
+#define CAN_FA1R_FACT3_Msk     (0x1U << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
+#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4_Pos     (4U)                                            
+#define CAN_FA1R_FACT4_Msk     (0x1U << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
+#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5_Pos     (5U)                                            
+#define CAN_FA1R_FACT5_Msk     (0x1U << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
+#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6_Pos     (6U)                                            
+#define CAN_FA1R_FACT6_Msk     (0x1U << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
+#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7_Pos     (7U)                                            
+#define CAN_FA1R_FACT7_Msk     (0x1U << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
+#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8_Pos     (8U)                                            
+#define CAN_FA1R_FACT8_Msk     (0x1U << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
+#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9_Pos     (9U)                                            
+#define CAN_FA1R_FACT9_Msk     (0x1U << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
+#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10_Pos    (10U)                                           
+#define CAN_FA1R_FACT10_Msk    (0x1U << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
+#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11_Pos    (11U)                                           
+#define CAN_FA1R_FACT11_Msk    (0x1U << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
+#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12_Pos    (12U)                                           
+#define CAN_FA1R_FACT12_Msk    (0x1U << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
+#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13_Pos    (13U)                                           
+#define CAN_FA1R_FACT13_Msk    (0x1U << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
+#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define CAN_F0R1_FB0_Pos       (0U)                                            
+#define CAN_F0R1_FB0_Msk       (0x1U << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos       (1U)                                            
+#define CAN_F0R1_FB1_Msk       (0x1U << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos       (2U)                                            
+#define CAN_F0R1_FB2_Msk       (0x1U << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos       (3U)                                            
+#define CAN_F0R1_FB3_Msk       (0x1U << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos       (4U)                                            
+#define CAN_F0R1_FB4_Msk       (0x1U << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos       (5U)                                            
+#define CAN_F0R1_FB5_Msk       (0x1U << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos       (6U)                                            
+#define CAN_F0R1_FB6_Msk       (0x1U << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos       (7U)                                            
+#define CAN_F0R1_FB7_Msk       (0x1U << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos       (8U)                                            
+#define CAN_F0R1_FB8_Msk       (0x1U << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos       (9U)                                            
+#define CAN_F0R1_FB9_Msk       (0x1U << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos      (10U)                                           
+#define CAN_F0R1_FB10_Msk      (0x1U << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos      (11U)                                           
+#define CAN_F0R1_FB11_Msk      (0x1U << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos      (12U)                                           
+#define CAN_F0R1_FB12_Msk      (0x1U << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos      (13U)                                           
+#define CAN_F0R1_FB13_Msk      (0x1U << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos      (14U)                                           
+#define CAN_F0R1_FB14_Msk      (0x1U << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos      (15U)                                           
+#define CAN_F0R1_FB15_Msk      (0x1U << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos      (16U)                                           
+#define CAN_F0R1_FB16_Msk      (0x1U << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos      (17U)                                           
+#define CAN_F0R1_FB17_Msk      (0x1U << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos      (18U)                                           
+#define CAN_F0R1_FB18_Msk      (0x1U << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos      (19U)                                           
+#define CAN_F0R1_FB19_Msk      (0x1U << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos      (20U)                                           
+#define CAN_F0R1_FB20_Msk      (0x1U << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos      (21U)                                           
+#define CAN_F0R1_FB21_Msk      (0x1U << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos      (22U)                                           
+#define CAN_F0R1_FB22_Msk      (0x1U << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos      (23U)                                           
+#define CAN_F0R1_FB23_Msk      (0x1U << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos      (24U)                                           
+#define CAN_F0R1_FB24_Msk      (0x1U << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos      (25U)                                           
+#define CAN_F0R1_FB25_Msk      (0x1U << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos      (26U)                                           
+#define CAN_F0R1_FB26_Msk      (0x1U << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos      (27U)                                           
+#define CAN_F0R1_FB27_Msk      (0x1U << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos      (28U)                                           
+#define CAN_F0R1_FB28_Msk      (0x1U << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos      (29U)                                           
+#define CAN_F0R1_FB29_Msk      (0x1U << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos      (30U)                                           
+#define CAN_F0R1_FB30_Msk      (0x1U << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos      (31U)                                           
+#define CAN_F0R1_FB31_Msk      (0x1U << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define CAN_F1R1_FB0_Pos       (0U)                                            
+#define CAN_F1R1_FB0_Msk       (0x1U << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos       (1U)                                            
+#define CAN_F1R1_FB1_Msk       (0x1U << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos       (2U)                                            
+#define CAN_F1R1_FB2_Msk       (0x1U << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos       (3U)                                            
+#define CAN_F1R1_FB3_Msk       (0x1U << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos       (4U)                                            
+#define CAN_F1R1_FB4_Msk       (0x1U << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos       (5U)                                            
+#define CAN_F1R1_FB5_Msk       (0x1U << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos       (6U)                                            
+#define CAN_F1R1_FB6_Msk       (0x1U << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos       (7U)                                            
+#define CAN_F1R1_FB7_Msk       (0x1U << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos       (8U)                                            
+#define CAN_F1R1_FB8_Msk       (0x1U << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos       (9U)                                            
+#define CAN_F1R1_FB9_Msk       (0x1U << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos      (10U)                                           
+#define CAN_F1R1_FB10_Msk      (0x1U << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos      (11U)                                           
+#define CAN_F1R1_FB11_Msk      (0x1U << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos      (12U)                                           
+#define CAN_F1R1_FB12_Msk      (0x1U << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos      (13U)                                           
+#define CAN_F1R1_FB13_Msk      (0x1U << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos      (14U)                                           
+#define CAN_F1R1_FB14_Msk      (0x1U << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos      (15U)                                           
+#define CAN_F1R1_FB15_Msk      (0x1U << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos      (16U)                                           
+#define CAN_F1R1_FB16_Msk      (0x1U << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos      (17U)                                           
+#define CAN_F1R1_FB17_Msk      (0x1U << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos      (18U)                                           
+#define CAN_F1R1_FB18_Msk      (0x1U << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos      (19U)                                           
+#define CAN_F1R1_FB19_Msk      (0x1U << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos      (20U)                                           
+#define CAN_F1R1_FB20_Msk      (0x1U << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos      (21U)                                           
+#define CAN_F1R1_FB21_Msk      (0x1U << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos      (22U)                                           
+#define CAN_F1R1_FB22_Msk      (0x1U << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos      (23U)                                           
+#define CAN_F1R1_FB23_Msk      (0x1U << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos      (24U)                                           
+#define CAN_F1R1_FB24_Msk      (0x1U << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos      (25U)                                           
+#define CAN_F1R1_FB25_Msk      (0x1U << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos      (26U)                                           
+#define CAN_F1R1_FB26_Msk      (0x1U << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos      (27U)                                           
+#define CAN_F1R1_FB27_Msk      (0x1U << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos      (28U)                                           
+#define CAN_F1R1_FB28_Msk      (0x1U << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos      (29U)                                           
+#define CAN_F1R1_FB29_Msk      (0x1U << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos      (30U)                                           
+#define CAN_F1R1_FB30_Msk      (0x1U << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos      (31U)                                           
+#define CAN_F1R1_FB31_Msk      (0x1U << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define CAN_F2R1_FB0_Pos       (0U)                                            
+#define CAN_F2R1_FB0_Msk       (0x1U << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos       (1U)                                            
+#define CAN_F2R1_FB1_Msk       (0x1U << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos       (2U)                                            
+#define CAN_F2R1_FB2_Msk       (0x1U << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos       (3U)                                            
+#define CAN_F2R1_FB3_Msk       (0x1U << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos       (4U)                                            
+#define CAN_F2R1_FB4_Msk       (0x1U << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos       (5U)                                            
+#define CAN_F2R1_FB5_Msk       (0x1U << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos       (6U)                                            
+#define CAN_F2R1_FB6_Msk       (0x1U << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos       (7U)                                            
+#define CAN_F2R1_FB7_Msk       (0x1U << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos       (8U)                                            
+#define CAN_F2R1_FB8_Msk       (0x1U << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos       (9U)                                            
+#define CAN_F2R1_FB9_Msk       (0x1U << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos      (10U)                                           
+#define CAN_F2R1_FB10_Msk      (0x1U << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos      (11U)                                           
+#define CAN_F2R1_FB11_Msk      (0x1U << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos      (12U)                                           
+#define CAN_F2R1_FB12_Msk      (0x1U << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos      (13U)                                           
+#define CAN_F2R1_FB13_Msk      (0x1U << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos      (14U)                                           
+#define CAN_F2R1_FB14_Msk      (0x1U << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos      (15U)                                           
+#define CAN_F2R1_FB15_Msk      (0x1U << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos      (16U)                                           
+#define CAN_F2R1_FB16_Msk      (0x1U << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos      (17U)                                           
+#define CAN_F2R1_FB17_Msk      (0x1U << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos      (18U)                                           
+#define CAN_F2R1_FB18_Msk      (0x1U << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos      (19U)                                           
+#define CAN_F2R1_FB19_Msk      (0x1U << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos      (20U)                                           
+#define CAN_F2R1_FB20_Msk      (0x1U << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos      (21U)                                           
+#define CAN_F2R1_FB21_Msk      (0x1U << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos      (22U)                                           
+#define CAN_F2R1_FB22_Msk      (0x1U << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos      (23U)                                           
+#define CAN_F2R1_FB23_Msk      (0x1U << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos      (24U)                                           
+#define CAN_F2R1_FB24_Msk      (0x1U << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos      (25U)                                           
+#define CAN_F2R1_FB25_Msk      (0x1U << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos      (26U)                                           
+#define CAN_F2R1_FB26_Msk      (0x1U << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos      (27U)                                           
+#define CAN_F2R1_FB27_Msk      (0x1U << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos      (28U)                                           
+#define CAN_F2R1_FB28_Msk      (0x1U << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos      (29U)                                           
+#define CAN_F2R1_FB29_Msk      (0x1U << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos      (30U)                                           
+#define CAN_F2R1_FB30_Msk      (0x1U << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos      (31U)                                           
+#define CAN_F2R1_FB31_Msk      (0x1U << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define CAN_F3R1_FB0_Pos       (0U)                                            
+#define CAN_F3R1_FB0_Msk       (0x1U << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos       (1U)                                            
+#define CAN_F3R1_FB1_Msk       (0x1U << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos       (2U)                                            
+#define CAN_F3R1_FB2_Msk       (0x1U << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos       (3U)                                            
+#define CAN_F3R1_FB3_Msk       (0x1U << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos       (4U)                                            
+#define CAN_F3R1_FB4_Msk       (0x1U << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos       (5U)                                            
+#define CAN_F3R1_FB5_Msk       (0x1U << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos       (6U)                                            
+#define CAN_F3R1_FB6_Msk       (0x1U << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos       (7U)                                            
+#define CAN_F3R1_FB7_Msk       (0x1U << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos       (8U)                                            
+#define CAN_F3R1_FB8_Msk       (0x1U << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos       (9U)                                            
+#define CAN_F3R1_FB9_Msk       (0x1U << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos      (10U)                                           
+#define CAN_F3R1_FB10_Msk      (0x1U << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos      (11U)                                           
+#define CAN_F3R1_FB11_Msk      (0x1U << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos      (12U)                                           
+#define CAN_F3R1_FB12_Msk      (0x1U << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos      (13U)                                           
+#define CAN_F3R1_FB13_Msk      (0x1U << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos      (14U)                                           
+#define CAN_F3R1_FB14_Msk      (0x1U << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos      (15U)                                           
+#define CAN_F3R1_FB15_Msk      (0x1U << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos      (16U)                                           
+#define CAN_F3R1_FB16_Msk      (0x1U << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos      (17U)                                           
+#define CAN_F3R1_FB17_Msk      (0x1U << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos      (18U)                                           
+#define CAN_F3R1_FB18_Msk      (0x1U << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos      (19U)                                           
+#define CAN_F3R1_FB19_Msk      (0x1U << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos      (20U)                                           
+#define CAN_F3R1_FB20_Msk      (0x1U << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos      (21U)                                           
+#define CAN_F3R1_FB21_Msk      (0x1U << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos      (22U)                                           
+#define CAN_F3R1_FB22_Msk      (0x1U << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos      (23U)                                           
+#define CAN_F3R1_FB23_Msk      (0x1U << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos      (24U)                                           
+#define CAN_F3R1_FB24_Msk      (0x1U << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos      (25U)                                           
+#define CAN_F3R1_FB25_Msk      (0x1U << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos      (26U)                                           
+#define CAN_F3R1_FB26_Msk      (0x1U << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos      (27U)                                           
+#define CAN_F3R1_FB27_Msk      (0x1U << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos      (28U)                                           
+#define CAN_F3R1_FB28_Msk      (0x1U << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos      (29U)                                           
+#define CAN_F3R1_FB29_Msk      (0x1U << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos      (30U)                                           
+#define CAN_F3R1_FB30_Msk      (0x1U << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos      (31U)                                           
+#define CAN_F3R1_FB31_Msk      (0x1U << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define CAN_F4R1_FB0_Pos       (0U)                                            
+#define CAN_F4R1_FB0_Msk       (0x1U << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos       (1U)                                            
+#define CAN_F4R1_FB1_Msk       (0x1U << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos       (2U)                                            
+#define CAN_F4R1_FB2_Msk       (0x1U << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos       (3U)                                            
+#define CAN_F4R1_FB3_Msk       (0x1U << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos       (4U)                                            
+#define CAN_F4R1_FB4_Msk       (0x1U << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos       (5U)                                            
+#define CAN_F4R1_FB5_Msk       (0x1U << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos       (6U)                                            
+#define CAN_F4R1_FB6_Msk       (0x1U << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos       (7U)                                            
+#define CAN_F4R1_FB7_Msk       (0x1U << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos       (8U)                                            
+#define CAN_F4R1_FB8_Msk       (0x1U << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos       (9U)                                            
+#define CAN_F4R1_FB9_Msk       (0x1U << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos      (10U)                                           
+#define CAN_F4R1_FB10_Msk      (0x1U << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos      (11U)                                           
+#define CAN_F4R1_FB11_Msk      (0x1U << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos      (12U)                                           
+#define CAN_F4R1_FB12_Msk      (0x1U << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos      (13U)                                           
+#define CAN_F4R1_FB13_Msk      (0x1U << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos      (14U)                                           
+#define CAN_F4R1_FB14_Msk      (0x1U << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos      (15U)                                           
+#define CAN_F4R1_FB15_Msk      (0x1U << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos      (16U)                                           
+#define CAN_F4R1_FB16_Msk      (0x1U << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos      (17U)                                           
+#define CAN_F4R1_FB17_Msk      (0x1U << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos      (18U)                                           
+#define CAN_F4R1_FB18_Msk      (0x1U << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos      (19U)                                           
+#define CAN_F4R1_FB19_Msk      (0x1U << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos      (20U)                                           
+#define CAN_F4R1_FB20_Msk      (0x1U << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos      (21U)                                           
+#define CAN_F4R1_FB21_Msk      (0x1U << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos      (22U)                                           
+#define CAN_F4R1_FB22_Msk      (0x1U << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos      (23U)                                           
+#define CAN_F4R1_FB23_Msk      (0x1U << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos      (24U)                                           
+#define CAN_F4R1_FB24_Msk      (0x1U << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos      (25U)                                           
+#define CAN_F4R1_FB25_Msk      (0x1U << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos      (26U)                                           
+#define CAN_F4R1_FB26_Msk      (0x1U << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos      (27U)                                           
+#define CAN_F4R1_FB27_Msk      (0x1U << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos      (28U)                                           
+#define CAN_F4R1_FB28_Msk      (0x1U << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos      (29U)                                           
+#define CAN_F4R1_FB29_Msk      (0x1U << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos      (30U)                                           
+#define CAN_F4R1_FB30_Msk      (0x1U << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos      (31U)                                           
+#define CAN_F4R1_FB31_Msk      (0x1U << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define CAN_F5R1_FB0_Pos       (0U)                                            
+#define CAN_F5R1_FB0_Msk       (0x1U << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos       (1U)                                            
+#define CAN_F5R1_FB1_Msk       (0x1U << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos       (2U)                                            
+#define CAN_F5R1_FB2_Msk       (0x1U << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos       (3U)                                            
+#define CAN_F5R1_FB3_Msk       (0x1U << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos       (4U)                                            
+#define CAN_F5R1_FB4_Msk       (0x1U << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos       (5U)                                            
+#define CAN_F5R1_FB5_Msk       (0x1U << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos       (6U)                                            
+#define CAN_F5R1_FB6_Msk       (0x1U << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos       (7U)                                            
+#define CAN_F5R1_FB7_Msk       (0x1U << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos       (8U)                                            
+#define CAN_F5R1_FB8_Msk       (0x1U << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos       (9U)                                            
+#define CAN_F5R1_FB9_Msk       (0x1U << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos      (10U)                                           
+#define CAN_F5R1_FB10_Msk      (0x1U << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos      (11U)                                           
+#define CAN_F5R1_FB11_Msk      (0x1U << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos      (12U)                                           
+#define CAN_F5R1_FB12_Msk      (0x1U << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos      (13U)                                           
+#define CAN_F5R1_FB13_Msk      (0x1U << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos      (14U)                                           
+#define CAN_F5R1_FB14_Msk      (0x1U << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos      (15U)                                           
+#define CAN_F5R1_FB15_Msk      (0x1U << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos      (16U)                                           
+#define CAN_F5R1_FB16_Msk      (0x1U << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos      (17U)                                           
+#define CAN_F5R1_FB17_Msk      (0x1U << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos      (18U)                                           
+#define CAN_F5R1_FB18_Msk      (0x1U << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos      (19U)                                           
+#define CAN_F5R1_FB19_Msk      (0x1U << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos      (20U)                                           
+#define CAN_F5R1_FB20_Msk      (0x1U << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos      (21U)                                           
+#define CAN_F5R1_FB21_Msk      (0x1U << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos      (22U)                                           
+#define CAN_F5R1_FB22_Msk      (0x1U << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos      (23U)                                           
+#define CAN_F5R1_FB23_Msk      (0x1U << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos      (24U)                                           
+#define CAN_F5R1_FB24_Msk      (0x1U << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos      (25U)                                           
+#define CAN_F5R1_FB25_Msk      (0x1U << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos      (26U)                                           
+#define CAN_F5R1_FB26_Msk      (0x1U << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos      (27U)                                           
+#define CAN_F5R1_FB27_Msk      (0x1U << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos      (28U)                                           
+#define CAN_F5R1_FB28_Msk      (0x1U << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos      (29U)                                           
+#define CAN_F5R1_FB29_Msk      (0x1U << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos      (30U)                                           
+#define CAN_F5R1_FB30_Msk      (0x1U << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos      (31U)                                           
+#define CAN_F5R1_FB31_Msk      (0x1U << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define CAN_F6R1_FB0_Pos       (0U)                                            
+#define CAN_F6R1_FB0_Msk       (0x1U << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos       (1U)                                            
+#define CAN_F6R1_FB1_Msk       (0x1U << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos       (2U)                                            
+#define CAN_F6R1_FB2_Msk       (0x1U << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos       (3U)                                            
+#define CAN_F6R1_FB3_Msk       (0x1U << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos       (4U)                                            
+#define CAN_F6R1_FB4_Msk       (0x1U << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos       (5U)                                            
+#define CAN_F6R1_FB5_Msk       (0x1U << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos       (6U)                                            
+#define CAN_F6R1_FB6_Msk       (0x1U << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos       (7U)                                            
+#define CAN_F6R1_FB7_Msk       (0x1U << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos       (8U)                                            
+#define CAN_F6R1_FB8_Msk       (0x1U << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos       (9U)                                            
+#define CAN_F6R1_FB9_Msk       (0x1U << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos      (10U)                                           
+#define CAN_F6R1_FB10_Msk      (0x1U << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos      (11U)                                           
+#define CAN_F6R1_FB11_Msk      (0x1U << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos      (12U)                                           
+#define CAN_F6R1_FB12_Msk      (0x1U << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos      (13U)                                           
+#define CAN_F6R1_FB13_Msk      (0x1U << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos      (14U)                                           
+#define CAN_F6R1_FB14_Msk      (0x1U << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos      (15U)                                           
+#define CAN_F6R1_FB15_Msk      (0x1U << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos      (16U)                                           
+#define CAN_F6R1_FB16_Msk      (0x1U << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos      (17U)                                           
+#define CAN_F6R1_FB17_Msk      (0x1U << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos      (18U)                                           
+#define CAN_F6R1_FB18_Msk      (0x1U << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos      (19U)                                           
+#define CAN_F6R1_FB19_Msk      (0x1U << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos      (20U)                                           
+#define CAN_F6R1_FB20_Msk      (0x1U << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos      (21U)                                           
+#define CAN_F6R1_FB21_Msk      (0x1U << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos      (22U)                                           
+#define CAN_F6R1_FB22_Msk      (0x1U << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos      (23U)                                           
+#define CAN_F6R1_FB23_Msk      (0x1U << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos      (24U)                                           
+#define CAN_F6R1_FB24_Msk      (0x1U << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos      (25U)                                           
+#define CAN_F6R1_FB25_Msk      (0x1U << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos      (26U)                                           
+#define CAN_F6R1_FB26_Msk      (0x1U << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos      (27U)                                           
+#define CAN_F6R1_FB27_Msk      (0x1U << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos      (28U)                                           
+#define CAN_F6R1_FB28_Msk      (0x1U << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos      (29U)                                           
+#define CAN_F6R1_FB29_Msk      (0x1U << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos      (30U)                                           
+#define CAN_F6R1_FB30_Msk      (0x1U << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos      (31U)                                           
+#define CAN_F6R1_FB31_Msk      (0x1U << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define CAN_F7R1_FB0_Pos       (0U)                                            
+#define CAN_F7R1_FB0_Msk       (0x1U << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos       (1U)                                            
+#define CAN_F7R1_FB1_Msk       (0x1U << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos       (2U)                                            
+#define CAN_F7R1_FB2_Msk       (0x1U << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos       (3U)                                            
+#define CAN_F7R1_FB3_Msk       (0x1U << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos       (4U)                                            
+#define CAN_F7R1_FB4_Msk       (0x1U << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos       (5U)                                            
+#define CAN_F7R1_FB5_Msk       (0x1U << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos       (6U)                                            
+#define CAN_F7R1_FB6_Msk       (0x1U << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos       (7U)                                            
+#define CAN_F7R1_FB7_Msk       (0x1U << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos       (8U)                                            
+#define CAN_F7R1_FB8_Msk       (0x1U << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos       (9U)                                            
+#define CAN_F7R1_FB9_Msk       (0x1U << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos      (10U)                                           
+#define CAN_F7R1_FB10_Msk      (0x1U << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos      (11U)                                           
+#define CAN_F7R1_FB11_Msk      (0x1U << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos      (12U)                                           
+#define CAN_F7R1_FB12_Msk      (0x1U << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos      (13U)                                           
+#define CAN_F7R1_FB13_Msk      (0x1U << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos      (14U)                                           
+#define CAN_F7R1_FB14_Msk      (0x1U << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos      (15U)                                           
+#define CAN_F7R1_FB15_Msk      (0x1U << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos      (16U)                                           
+#define CAN_F7R1_FB16_Msk      (0x1U << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos      (17U)                                           
+#define CAN_F7R1_FB17_Msk      (0x1U << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos      (18U)                                           
+#define CAN_F7R1_FB18_Msk      (0x1U << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos      (19U)                                           
+#define CAN_F7R1_FB19_Msk      (0x1U << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos      (20U)                                           
+#define CAN_F7R1_FB20_Msk      (0x1U << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos      (21U)                                           
+#define CAN_F7R1_FB21_Msk      (0x1U << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos      (22U)                                           
+#define CAN_F7R1_FB22_Msk      (0x1U << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos      (23U)                                           
+#define CAN_F7R1_FB23_Msk      (0x1U << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos      (24U)                                           
+#define CAN_F7R1_FB24_Msk      (0x1U << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos      (25U)                                           
+#define CAN_F7R1_FB25_Msk      (0x1U << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos      (26U)                                           
+#define CAN_F7R1_FB26_Msk      (0x1U << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos      (27U)                                           
+#define CAN_F7R1_FB27_Msk      (0x1U << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos      (28U)                                           
+#define CAN_F7R1_FB28_Msk      (0x1U << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos      (29U)                                           
+#define CAN_F7R1_FB29_Msk      (0x1U << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos      (30U)                                           
+#define CAN_F7R1_FB30_Msk      (0x1U << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos      (31U)                                           
+#define CAN_F7R1_FB31_Msk      (0x1U << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define CAN_F8R1_FB0_Pos       (0U)                                            
+#define CAN_F8R1_FB0_Msk       (0x1U << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos       (1U)                                            
+#define CAN_F8R1_FB1_Msk       (0x1U << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos       (2U)                                            
+#define CAN_F8R1_FB2_Msk       (0x1U << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos       (3U)                                            
+#define CAN_F8R1_FB3_Msk       (0x1U << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos       (4U)                                            
+#define CAN_F8R1_FB4_Msk       (0x1U << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos       (5U)                                            
+#define CAN_F8R1_FB5_Msk       (0x1U << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos       (6U)                                            
+#define CAN_F8R1_FB6_Msk       (0x1U << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos       (7U)                                            
+#define CAN_F8R1_FB7_Msk       (0x1U << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos       (8U)                                            
+#define CAN_F8R1_FB8_Msk       (0x1U << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos       (9U)                                            
+#define CAN_F8R1_FB9_Msk       (0x1U << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos      (10U)                                           
+#define CAN_F8R1_FB10_Msk      (0x1U << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos      (11U)                                           
+#define CAN_F8R1_FB11_Msk      (0x1U << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos      (12U)                                           
+#define CAN_F8R1_FB12_Msk      (0x1U << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos      (13U)                                           
+#define CAN_F8R1_FB13_Msk      (0x1U << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos      (14U)                                           
+#define CAN_F8R1_FB14_Msk      (0x1U << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos      (15U)                                           
+#define CAN_F8R1_FB15_Msk      (0x1U << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos      (16U)                                           
+#define CAN_F8R1_FB16_Msk      (0x1U << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos      (17U)                                           
+#define CAN_F8R1_FB17_Msk      (0x1U << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos      (18U)                                           
+#define CAN_F8R1_FB18_Msk      (0x1U << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos      (19U)                                           
+#define CAN_F8R1_FB19_Msk      (0x1U << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos      (20U)                                           
+#define CAN_F8R1_FB20_Msk      (0x1U << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos      (21U)                                           
+#define CAN_F8R1_FB21_Msk      (0x1U << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos      (22U)                                           
+#define CAN_F8R1_FB22_Msk      (0x1U << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos      (23U)                                           
+#define CAN_F8R1_FB23_Msk      (0x1U << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos      (24U)                                           
+#define CAN_F8R1_FB24_Msk      (0x1U << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos      (25U)                                           
+#define CAN_F8R1_FB25_Msk      (0x1U << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos      (26U)                                           
+#define CAN_F8R1_FB26_Msk      (0x1U << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos      (27U)                                           
+#define CAN_F8R1_FB27_Msk      (0x1U << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos      (28U)                                           
+#define CAN_F8R1_FB28_Msk      (0x1U << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos      (29U)                                           
+#define CAN_F8R1_FB29_Msk      (0x1U << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos      (30U)                                           
+#define CAN_F8R1_FB30_Msk      (0x1U << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos      (31U)                                           
+#define CAN_F8R1_FB31_Msk      (0x1U << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define CAN_F9R1_FB0_Pos       (0U)                                            
+#define CAN_F9R1_FB0_Msk       (0x1U << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos       (1U)                                            
+#define CAN_F9R1_FB1_Msk       (0x1U << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos       (2U)                                            
+#define CAN_F9R1_FB2_Msk       (0x1U << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos       (3U)                                            
+#define CAN_F9R1_FB3_Msk       (0x1U << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos       (4U)                                            
+#define CAN_F9R1_FB4_Msk       (0x1U << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos       (5U)                                            
+#define CAN_F9R1_FB5_Msk       (0x1U << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos       (6U)                                            
+#define CAN_F9R1_FB6_Msk       (0x1U << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos       (7U)                                            
+#define CAN_F9R1_FB7_Msk       (0x1U << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos       (8U)                                            
+#define CAN_F9R1_FB8_Msk       (0x1U << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos       (9U)                                            
+#define CAN_F9R1_FB9_Msk       (0x1U << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos      (10U)                                           
+#define CAN_F9R1_FB10_Msk      (0x1U << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos      (11U)                                           
+#define CAN_F9R1_FB11_Msk      (0x1U << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos      (12U)                                           
+#define CAN_F9R1_FB12_Msk      (0x1U << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos      (13U)                                           
+#define CAN_F9R1_FB13_Msk      (0x1U << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos      (14U)                                           
+#define CAN_F9R1_FB14_Msk      (0x1U << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos      (15U)                                           
+#define CAN_F9R1_FB15_Msk      (0x1U << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos      (16U)                                           
+#define CAN_F9R1_FB16_Msk      (0x1U << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos      (17U)                                           
+#define CAN_F9R1_FB17_Msk      (0x1U << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos      (18U)                                           
+#define CAN_F9R1_FB18_Msk      (0x1U << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos      (19U)                                           
+#define CAN_F9R1_FB19_Msk      (0x1U << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos      (20U)                                           
+#define CAN_F9R1_FB20_Msk      (0x1U << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos      (21U)                                           
+#define CAN_F9R1_FB21_Msk      (0x1U << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos      (22U)                                           
+#define CAN_F9R1_FB22_Msk      (0x1U << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos      (23U)                                           
+#define CAN_F9R1_FB23_Msk      (0x1U << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos      (24U)                                           
+#define CAN_F9R1_FB24_Msk      (0x1U << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos      (25U)                                           
+#define CAN_F9R1_FB25_Msk      (0x1U << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos      (26U)                                           
+#define CAN_F9R1_FB26_Msk      (0x1U << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos      (27U)                                           
+#define CAN_F9R1_FB27_Msk      (0x1U << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos      (28U)                                           
+#define CAN_F9R1_FB28_Msk      (0x1U << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos      (29U)                                           
+#define CAN_F9R1_FB29_Msk      (0x1U << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos      (30U)                                           
+#define CAN_F9R1_FB30_Msk      (0x1U << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos      (31U)                                           
+#define CAN_F9R1_FB31_Msk      (0x1U << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define CAN_F10R1_FB0_Pos      (0U)                                            
+#define CAN_F10R1_FB0_Msk      (0x1U << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos      (1U)                                            
+#define CAN_F10R1_FB1_Msk      (0x1U << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos      (2U)                                            
+#define CAN_F10R1_FB2_Msk      (0x1U << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos      (3U)                                            
+#define CAN_F10R1_FB3_Msk      (0x1U << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos      (4U)                                            
+#define CAN_F10R1_FB4_Msk      (0x1U << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos      (5U)                                            
+#define CAN_F10R1_FB5_Msk      (0x1U << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos      (6U)                                            
+#define CAN_F10R1_FB6_Msk      (0x1U << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos      (7U)                                            
+#define CAN_F10R1_FB7_Msk      (0x1U << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos      (8U)                                            
+#define CAN_F10R1_FB8_Msk      (0x1U << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos      (9U)                                            
+#define CAN_F10R1_FB9_Msk      (0x1U << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos     (10U)                                           
+#define CAN_F10R1_FB10_Msk     (0x1U << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos     (11U)                                           
+#define CAN_F10R1_FB11_Msk     (0x1U << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos     (12U)                                           
+#define CAN_F10R1_FB12_Msk     (0x1U << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos     (13U)                                           
+#define CAN_F10R1_FB13_Msk     (0x1U << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos     (14U)                                           
+#define CAN_F10R1_FB14_Msk     (0x1U << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos     (15U)                                           
+#define CAN_F10R1_FB15_Msk     (0x1U << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos     (16U)                                           
+#define CAN_F10R1_FB16_Msk     (0x1U << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos     (17U)                                           
+#define CAN_F10R1_FB17_Msk     (0x1U << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos     (18U)                                           
+#define CAN_F10R1_FB18_Msk     (0x1U << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos     (19U)                                           
+#define CAN_F10R1_FB19_Msk     (0x1U << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos     (20U)                                           
+#define CAN_F10R1_FB20_Msk     (0x1U << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos     (21U)                                           
+#define CAN_F10R1_FB21_Msk     (0x1U << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos     (22U)                                           
+#define CAN_F10R1_FB22_Msk     (0x1U << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos     (23U)                                           
+#define CAN_F10R1_FB23_Msk     (0x1U << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos     (24U)                                           
+#define CAN_F10R1_FB24_Msk     (0x1U << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos     (25U)                                           
+#define CAN_F10R1_FB25_Msk     (0x1U << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos     (26U)                                           
+#define CAN_F10R1_FB26_Msk     (0x1U << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos     (27U)                                           
+#define CAN_F10R1_FB27_Msk     (0x1U << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos     (28U)                                           
+#define CAN_F10R1_FB28_Msk     (0x1U << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos     (29U)                                           
+#define CAN_F10R1_FB29_Msk     (0x1U << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos     (30U)                                           
+#define CAN_F10R1_FB30_Msk     (0x1U << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos     (31U)                                           
+#define CAN_F10R1_FB31_Msk     (0x1U << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define CAN_F11R1_FB0_Pos      (0U)                                            
+#define CAN_F11R1_FB0_Msk      (0x1U << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos      (1U)                                            
+#define CAN_F11R1_FB1_Msk      (0x1U << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos      (2U)                                            
+#define CAN_F11R1_FB2_Msk      (0x1U << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos      (3U)                                            
+#define CAN_F11R1_FB3_Msk      (0x1U << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos      (4U)                                            
+#define CAN_F11R1_FB4_Msk      (0x1U << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos      (5U)                                            
+#define CAN_F11R1_FB5_Msk      (0x1U << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos      (6U)                                            
+#define CAN_F11R1_FB6_Msk      (0x1U << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos      (7U)                                            
+#define CAN_F11R1_FB7_Msk      (0x1U << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos      (8U)                                            
+#define CAN_F11R1_FB8_Msk      (0x1U << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos      (9U)                                            
+#define CAN_F11R1_FB9_Msk      (0x1U << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos     (10U)                                           
+#define CAN_F11R1_FB10_Msk     (0x1U << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos     (11U)                                           
+#define CAN_F11R1_FB11_Msk     (0x1U << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos     (12U)                                           
+#define CAN_F11R1_FB12_Msk     (0x1U << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos     (13U)                                           
+#define CAN_F11R1_FB13_Msk     (0x1U << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos     (14U)                                           
+#define CAN_F11R1_FB14_Msk     (0x1U << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos     (15U)                                           
+#define CAN_F11R1_FB15_Msk     (0x1U << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos     (16U)                                           
+#define CAN_F11R1_FB16_Msk     (0x1U << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos     (17U)                                           
+#define CAN_F11R1_FB17_Msk     (0x1U << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos     (18U)                                           
+#define CAN_F11R1_FB18_Msk     (0x1U << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos     (19U)                                           
+#define CAN_F11R1_FB19_Msk     (0x1U << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos     (20U)                                           
+#define CAN_F11R1_FB20_Msk     (0x1U << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos     (21U)                                           
+#define CAN_F11R1_FB21_Msk     (0x1U << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos     (22U)                                           
+#define CAN_F11R1_FB22_Msk     (0x1U << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos     (23U)                                           
+#define CAN_F11R1_FB23_Msk     (0x1U << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos     (24U)                                           
+#define CAN_F11R1_FB24_Msk     (0x1U << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos     (25U)                                           
+#define CAN_F11R1_FB25_Msk     (0x1U << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos     (26U)                                           
+#define CAN_F11R1_FB26_Msk     (0x1U << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos     (27U)                                           
+#define CAN_F11R1_FB27_Msk     (0x1U << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos     (28U)                                           
+#define CAN_F11R1_FB28_Msk     (0x1U << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos     (29U)                                           
+#define CAN_F11R1_FB29_Msk     (0x1U << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos     (30U)                                           
+#define CAN_F11R1_FB30_Msk     (0x1U << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos     (31U)                                           
+#define CAN_F11R1_FB31_Msk     (0x1U << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define CAN_F12R1_FB0_Pos      (0U)                                            
+#define CAN_F12R1_FB0_Msk      (0x1U << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos      (1U)                                            
+#define CAN_F12R1_FB1_Msk      (0x1U << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos      (2U)                                            
+#define CAN_F12R1_FB2_Msk      (0x1U << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos      (3U)                                            
+#define CAN_F12R1_FB3_Msk      (0x1U << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos      (4U)                                            
+#define CAN_F12R1_FB4_Msk      (0x1U << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos      (5U)                                            
+#define CAN_F12R1_FB5_Msk      (0x1U << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos      (6U)                                            
+#define CAN_F12R1_FB6_Msk      (0x1U << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos      (7U)                                            
+#define CAN_F12R1_FB7_Msk      (0x1U << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos      (8U)                                            
+#define CAN_F12R1_FB8_Msk      (0x1U << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos      (9U)                                            
+#define CAN_F12R1_FB9_Msk      (0x1U << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos     (10U)                                           
+#define CAN_F12R1_FB10_Msk     (0x1U << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos     (11U)                                           
+#define CAN_F12R1_FB11_Msk     (0x1U << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos     (12U)                                           
+#define CAN_F12R1_FB12_Msk     (0x1U << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos     (13U)                                           
+#define CAN_F12R1_FB13_Msk     (0x1U << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos     (14U)                                           
+#define CAN_F12R1_FB14_Msk     (0x1U << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos     (15U)                                           
+#define CAN_F12R1_FB15_Msk     (0x1U << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos     (16U)                                           
+#define CAN_F12R1_FB16_Msk     (0x1U << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos     (17U)                                           
+#define CAN_F12R1_FB17_Msk     (0x1U << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos     (18U)                                           
+#define CAN_F12R1_FB18_Msk     (0x1U << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos     (19U)                                           
+#define CAN_F12R1_FB19_Msk     (0x1U << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos     (20U)                                           
+#define CAN_F12R1_FB20_Msk     (0x1U << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos     (21U)                                           
+#define CAN_F12R1_FB21_Msk     (0x1U << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos     (22U)                                           
+#define CAN_F12R1_FB22_Msk     (0x1U << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos     (23U)                                           
+#define CAN_F12R1_FB23_Msk     (0x1U << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos     (24U)                                           
+#define CAN_F12R1_FB24_Msk     (0x1U << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos     (25U)                                           
+#define CAN_F12R1_FB25_Msk     (0x1U << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos     (26U)                                           
+#define CAN_F12R1_FB26_Msk     (0x1U << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos     (27U)                                           
+#define CAN_F12R1_FB27_Msk     (0x1U << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos     (28U)                                           
+#define CAN_F12R1_FB28_Msk     (0x1U << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos     (29U)                                           
+#define CAN_F12R1_FB29_Msk     (0x1U << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos     (30U)                                           
+#define CAN_F12R1_FB30_Msk     (0x1U << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos     (31U)                                           
+#define CAN_F12R1_FB31_Msk     (0x1U << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define CAN_F13R1_FB0_Pos      (0U)                                            
+#define CAN_F13R1_FB0_Msk      (0x1U << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos      (1U)                                            
+#define CAN_F13R1_FB1_Msk      (0x1U << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos      (2U)                                            
+#define CAN_F13R1_FB2_Msk      (0x1U << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos      (3U)                                            
+#define CAN_F13R1_FB3_Msk      (0x1U << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos      (4U)                                            
+#define CAN_F13R1_FB4_Msk      (0x1U << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos      (5U)                                            
+#define CAN_F13R1_FB5_Msk      (0x1U << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos      (6U)                                            
+#define CAN_F13R1_FB6_Msk      (0x1U << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos      (7U)                                            
+#define CAN_F13R1_FB7_Msk      (0x1U << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos      (8U)                                            
+#define CAN_F13R1_FB8_Msk      (0x1U << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos      (9U)                                            
+#define CAN_F13R1_FB9_Msk      (0x1U << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos     (10U)                                           
+#define CAN_F13R1_FB10_Msk     (0x1U << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos     (11U)                                           
+#define CAN_F13R1_FB11_Msk     (0x1U << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos     (12U)                                           
+#define CAN_F13R1_FB12_Msk     (0x1U << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos     (13U)                                           
+#define CAN_F13R1_FB13_Msk     (0x1U << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos     (14U)                                           
+#define CAN_F13R1_FB14_Msk     (0x1U << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos     (15U)                                           
+#define CAN_F13R1_FB15_Msk     (0x1U << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos     (16U)                                           
+#define CAN_F13R1_FB16_Msk     (0x1U << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos     (17U)                                           
+#define CAN_F13R1_FB17_Msk     (0x1U << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos     (18U)                                           
+#define CAN_F13R1_FB18_Msk     (0x1U << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos     (19U)                                           
+#define CAN_F13R1_FB19_Msk     (0x1U << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos     (20U)                                           
+#define CAN_F13R1_FB20_Msk     (0x1U << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos     (21U)                                           
+#define CAN_F13R1_FB21_Msk     (0x1U << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos     (22U)                                           
+#define CAN_F13R1_FB22_Msk     (0x1U << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos     (23U)                                           
+#define CAN_F13R1_FB23_Msk     (0x1U << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos     (24U)                                           
+#define CAN_F13R1_FB24_Msk     (0x1U << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos     (25U)                                           
+#define CAN_F13R1_FB25_Msk     (0x1U << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos     (26U)                                           
+#define CAN_F13R1_FB26_Msk     (0x1U << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos     (27U)                                           
+#define CAN_F13R1_FB27_Msk     (0x1U << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos     (28U)                                           
+#define CAN_F13R1_FB28_Msk     (0x1U << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos     (29U)                                           
+#define CAN_F13R1_FB29_Msk     (0x1U << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos     (30U)                                           
+#define CAN_F13R1_FB30_Msk     (0x1U << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos     (31U)                                           
+#define CAN_F13R1_FB31_Msk     (0x1U << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define CAN_F0R2_FB0_Pos       (0U)                                            
+#define CAN_F0R2_FB0_Msk       (0x1U << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos       (1U)                                            
+#define CAN_F0R2_FB1_Msk       (0x1U << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos       (2U)                                            
+#define CAN_F0R2_FB2_Msk       (0x1U << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos       (3U)                                            
+#define CAN_F0R2_FB3_Msk       (0x1U << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos       (4U)                                            
+#define CAN_F0R2_FB4_Msk       (0x1U << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos       (5U)                                            
+#define CAN_F0R2_FB5_Msk       (0x1U << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos       (6U)                                            
+#define CAN_F0R2_FB6_Msk       (0x1U << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos       (7U)                                            
+#define CAN_F0R2_FB7_Msk       (0x1U << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos       (8U)                                            
+#define CAN_F0R2_FB8_Msk       (0x1U << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos       (9U)                                            
+#define CAN_F0R2_FB9_Msk       (0x1U << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos      (10U)                                           
+#define CAN_F0R2_FB10_Msk      (0x1U << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos      (11U)                                           
+#define CAN_F0R2_FB11_Msk      (0x1U << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos      (12U)                                           
+#define CAN_F0R2_FB12_Msk      (0x1U << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos      (13U)                                           
+#define CAN_F0R2_FB13_Msk      (0x1U << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos      (14U)                                           
+#define CAN_F0R2_FB14_Msk      (0x1U << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos      (15U)                                           
+#define CAN_F0R2_FB15_Msk      (0x1U << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos      (16U)                                           
+#define CAN_F0R2_FB16_Msk      (0x1U << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos      (17U)                                           
+#define CAN_F0R2_FB17_Msk      (0x1U << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos      (18U)                                           
+#define CAN_F0R2_FB18_Msk      (0x1U << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos      (19U)                                           
+#define CAN_F0R2_FB19_Msk      (0x1U << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos      (20U)                                           
+#define CAN_F0R2_FB20_Msk      (0x1U << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos      (21U)                                           
+#define CAN_F0R2_FB21_Msk      (0x1U << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos      (22U)                                           
+#define CAN_F0R2_FB22_Msk      (0x1U << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos      (23U)                                           
+#define CAN_F0R2_FB23_Msk      (0x1U << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos      (24U)                                           
+#define CAN_F0R2_FB24_Msk      (0x1U << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos      (25U)                                           
+#define CAN_F0R2_FB25_Msk      (0x1U << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos      (26U)                                           
+#define CAN_F0R2_FB26_Msk      (0x1U << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos      (27U)                                           
+#define CAN_F0R2_FB27_Msk      (0x1U << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos      (28U)                                           
+#define CAN_F0R2_FB28_Msk      (0x1U << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos      (29U)                                           
+#define CAN_F0R2_FB29_Msk      (0x1U << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos      (30U)                                           
+#define CAN_F0R2_FB30_Msk      (0x1U << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos      (31U)                                           
+#define CAN_F0R2_FB31_Msk      (0x1U << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define CAN_F1R2_FB0_Pos       (0U)                                            
+#define CAN_F1R2_FB0_Msk       (0x1U << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos       (1U)                                            
+#define CAN_F1R2_FB1_Msk       (0x1U << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos       (2U)                                            
+#define CAN_F1R2_FB2_Msk       (0x1U << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos       (3U)                                            
+#define CAN_F1R2_FB3_Msk       (0x1U << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos       (4U)                                            
+#define CAN_F1R2_FB4_Msk       (0x1U << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos       (5U)                                            
+#define CAN_F1R2_FB5_Msk       (0x1U << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos       (6U)                                            
+#define CAN_F1R2_FB6_Msk       (0x1U << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos       (7U)                                            
+#define CAN_F1R2_FB7_Msk       (0x1U << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos       (8U)                                            
+#define CAN_F1R2_FB8_Msk       (0x1U << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos       (9U)                                            
+#define CAN_F1R2_FB9_Msk       (0x1U << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos      (10U)                                           
+#define CAN_F1R2_FB10_Msk      (0x1U << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos      (11U)                                           
+#define CAN_F1R2_FB11_Msk      (0x1U << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos      (12U)                                           
+#define CAN_F1R2_FB12_Msk      (0x1U << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos      (13U)                                           
+#define CAN_F1R2_FB13_Msk      (0x1U << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos      (14U)                                           
+#define CAN_F1R2_FB14_Msk      (0x1U << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos      (15U)                                           
+#define CAN_F1R2_FB15_Msk      (0x1U << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos      (16U)                                           
+#define CAN_F1R2_FB16_Msk      (0x1U << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos      (17U)                                           
+#define CAN_F1R2_FB17_Msk      (0x1U << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos      (18U)                                           
+#define CAN_F1R2_FB18_Msk      (0x1U << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos      (19U)                                           
+#define CAN_F1R2_FB19_Msk      (0x1U << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos      (20U)                                           
+#define CAN_F1R2_FB20_Msk      (0x1U << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos      (21U)                                           
+#define CAN_F1R2_FB21_Msk      (0x1U << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos      (22U)                                           
+#define CAN_F1R2_FB22_Msk      (0x1U << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos      (23U)                                           
+#define CAN_F1R2_FB23_Msk      (0x1U << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos      (24U)                                           
+#define CAN_F1R2_FB24_Msk      (0x1U << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos      (25U)                                           
+#define CAN_F1R2_FB25_Msk      (0x1U << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos      (26U)                                           
+#define CAN_F1R2_FB26_Msk      (0x1U << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos      (27U)                                           
+#define CAN_F1R2_FB27_Msk      (0x1U << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos      (28U)                                           
+#define CAN_F1R2_FB28_Msk      (0x1U << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos      (29U)                                           
+#define CAN_F1R2_FB29_Msk      (0x1U << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos      (30U)                                           
+#define CAN_F1R2_FB30_Msk      (0x1U << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos      (31U)                                           
+#define CAN_F1R2_FB31_Msk      (0x1U << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define CAN_F2R2_FB0_Pos       (0U)                                            
+#define CAN_F2R2_FB0_Msk       (0x1U << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos       (1U)                                            
+#define CAN_F2R2_FB1_Msk       (0x1U << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos       (2U)                                            
+#define CAN_F2R2_FB2_Msk       (0x1U << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos       (3U)                                            
+#define CAN_F2R2_FB3_Msk       (0x1U << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos       (4U)                                            
+#define CAN_F2R2_FB4_Msk       (0x1U << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos       (5U)                                            
+#define CAN_F2R2_FB5_Msk       (0x1U << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos       (6U)                                            
+#define CAN_F2R2_FB6_Msk       (0x1U << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos       (7U)                                            
+#define CAN_F2R2_FB7_Msk       (0x1U << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos       (8U)                                            
+#define CAN_F2R2_FB8_Msk       (0x1U << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos       (9U)                                            
+#define CAN_F2R2_FB9_Msk       (0x1U << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos      (10U)                                           
+#define CAN_F2R2_FB10_Msk      (0x1U << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos      (11U)                                           
+#define CAN_F2R2_FB11_Msk      (0x1U << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos      (12U)                                           
+#define CAN_F2R2_FB12_Msk      (0x1U << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos      (13U)                                           
+#define CAN_F2R2_FB13_Msk      (0x1U << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos      (14U)                                           
+#define CAN_F2R2_FB14_Msk      (0x1U << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos      (15U)                                           
+#define CAN_F2R2_FB15_Msk      (0x1U << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos      (16U)                                           
+#define CAN_F2R2_FB16_Msk      (0x1U << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos      (17U)                                           
+#define CAN_F2R2_FB17_Msk      (0x1U << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos      (18U)                                           
+#define CAN_F2R2_FB18_Msk      (0x1U << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos      (19U)                                           
+#define CAN_F2R2_FB19_Msk      (0x1U << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos      (20U)                                           
+#define CAN_F2R2_FB20_Msk      (0x1U << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos      (21U)                                           
+#define CAN_F2R2_FB21_Msk      (0x1U << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos      (22U)                                           
+#define CAN_F2R2_FB22_Msk      (0x1U << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos      (23U)                                           
+#define CAN_F2R2_FB23_Msk      (0x1U << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos      (24U)                                           
+#define CAN_F2R2_FB24_Msk      (0x1U << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos      (25U)                                           
+#define CAN_F2R2_FB25_Msk      (0x1U << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos      (26U)                                           
+#define CAN_F2R2_FB26_Msk      (0x1U << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos      (27U)                                           
+#define CAN_F2R2_FB27_Msk      (0x1U << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos      (28U)                                           
+#define CAN_F2R2_FB28_Msk      (0x1U << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos      (29U)                                           
+#define CAN_F2R2_FB29_Msk      (0x1U << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos      (30U)                                           
+#define CAN_F2R2_FB30_Msk      (0x1U << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos      (31U)                                           
+#define CAN_F2R2_FB31_Msk      (0x1U << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define CAN_F3R2_FB0_Pos       (0U)                                            
+#define CAN_F3R2_FB0_Msk       (0x1U << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos       (1U)                                            
+#define CAN_F3R2_FB1_Msk       (0x1U << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos       (2U)                                            
+#define CAN_F3R2_FB2_Msk       (0x1U << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos       (3U)                                            
+#define CAN_F3R2_FB3_Msk       (0x1U << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos       (4U)                                            
+#define CAN_F3R2_FB4_Msk       (0x1U << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos       (5U)                                            
+#define CAN_F3R2_FB5_Msk       (0x1U << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos       (6U)                                            
+#define CAN_F3R2_FB6_Msk       (0x1U << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos       (7U)                                            
+#define CAN_F3R2_FB7_Msk       (0x1U << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos       (8U)                                            
+#define CAN_F3R2_FB8_Msk       (0x1U << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos       (9U)                                            
+#define CAN_F3R2_FB9_Msk       (0x1U << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos      (10U)                                           
+#define CAN_F3R2_FB10_Msk      (0x1U << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos      (11U)                                           
+#define CAN_F3R2_FB11_Msk      (0x1U << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos      (12U)                                           
+#define CAN_F3R2_FB12_Msk      (0x1U << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos      (13U)                                           
+#define CAN_F3R2_FB13_Msk      (0x1U << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos      (14U)                                           
+#define CAN_F3R2_FB14_Msk      (0x1U << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos      (15U)                                           
+#define CAN_F3R2_FB15_Msk      (0x1U << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos      (16U)                                           
+#define CAN_F3R2_FB16_Msk      (0x1U << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos      (17U)                                           
+#define CAN_F3R2_FB17_Msk      (0x1U << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos      (18U)                                           
+#define CAN_F3R2_FB18_Msk      (0x1U << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos      (19U)                                           
+#define CAN_F3R2_FB19_Msk      (0x1U << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos      (20U)                                           
+#define CAN_F3R2_FB20_Msk      (0x1U << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos      (21U)                                           
+#define CAN_F3R2_FB21_Msk      (0x1U << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos      (22U)                                           
+#define CAN_F3R2_FB22_Msk      (0x1U << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos      (23U)                                           
+#define CAN_F3R2_FB23_Msk      (0x1U << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos      (24U)                                           
+#define CAN_F3R2_FB24_Msk      (0x1U << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos      (25U)                                           
+#define CAN_F3R2_FB25_Msk      (0x1U << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos      (26U)                                           
+#define CAN_F3R2_FB26_Msk      (0x1U << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos      (27U)                                           
+#define CAN_F3R2_FB27_Msk      (0x1U << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos      (28U)                                           
+#define CAN_F3R2_FB28_Msk      (0x1U << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos      (29U)                                           
+#define CAN_F3R2_FB29_Msk      (0x1U << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos      (30U)                                           
+#define CAN_F3R2_FB30_Msk      (0x1U << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos      (31U)                                           
+#define CAN_F3R2_FB31_Msk      (0x1U << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define CAN_F4R2_FB0_Pos       (0U)                                            
+#define CAN_F4R2_FB0_Msk       (0x1U << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos       (1U)                                            
+#define CAN_F4R2_FB1_Msk       (0x1U << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos       (2U)                                            
+#define CAN_F4R2_FB2_Msk       (0x1U << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos       (3U)                                            
+#define CAN_F4R2_FB3_Msk       (0x1U << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos       (4U)                                            
+#define CAN_F4R2_FB4_Msk       (0x1U << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos       (5U)                                            
+#define CAN_F4R2_FB5_Msk       (0x1U << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos       (6U)                                            
+#define CAN_F4R2_FB6_Msk       (0x1U << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos       (7U)                                            
+#define CAN_F4R2_FB7_Msk       (0x1U << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos       (8U)                                            
+#define CAN_F4R2_FB8_Msk       (0x1U << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos       (9U)                                            
+#define CAN_F4R2_FB9_Msk       (0x1U << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos      (10U)                                           
+#define CAN_F4R2_FB10_Msk      (0x1U << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos      (11U)                                           
+#define CAN_F4R2_FB11_Msk      (0x1U << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos      (12U)                                           
+#define CAN_F4R2_FB12_Msk      (0x1U << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos      (13U)                                           
+#define CAN_F4R2_FB13_Msk      (0x1U << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos      (14U)                                           
+#define CAN_F4R2_FB14_Msk      (0x1U << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos      (15U)                                           
+#define CAN_F4R2_FB15_Msk      (0x1U << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos      (16U)                                           
+#define CAN_F4R2_FB16_Msk      (0x1U << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos      (17U)                                           
+#define CAN_F4R2_FB17_Msk      (0x1U << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos      (18U)                                           
+#define CAN_F4R2_FB18_Msk      (0x1U << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos      (19U)                                           
+#define CAN_F4R2_FB19_Msk      (0x1U << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos      (20U)                                           
+#define CAN_F4R2_FB20_Msk      (0x1U << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos      (21U)                                           
+#define CAN_F4R2_FB21_Msk      (0x1U << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos      (22U)                                           
+#define CAN_F4R2_FB22_Msk      (0x1U << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos      (23U)                                           
+#define CAN_F4R2_FB23_Msk      (0x1U << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos      (24U)                                           
+#define CAN_F4R2_FB24_Msk      (0x1U << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos      (25U)                                           
+#define CAN_F4R2_FB25_Msk      (0x1U << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos      (26U)                                           
+#define CAN_F4R2_FB26_Msk      (0x1U << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos      (27U)                                           
+#define CAN_F4R2_FB27_Msk      (0x1U << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos      (28U)                                           
+#define CAN_F4R2_FB28_Msk      (0x1U << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos      (29U)                                           
+#define CAN_F4R2_FB29_Msk      (0x1U << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos      (30U)                                           
+#define CAN_F4R2_FB30_Msk      (0x1U << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos      (31U)                                           
+#define CAN_F4R2_FB31_Msk      (0x1U << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define CAN_F5R2_FB0_Pos       (0U)                                            
+#define CAN_F5R2_FB0_Msk       (0x1U << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos       (1U)                                            
+#define CAN_F5R2_FB1_Msk       (0x1U << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos       (2U)                                            
+#define CAN_F5R2_FB2_Msk       (0x1U << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos       (3U)                                            
+#define CAN_F5R2_FB3_Msk       (0x1U << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos       (4U)                                            
+#define CAN_F5R2_FB4_Msk       (0x1U << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos       (5U)                                            
+#define CAN_F5R2_FB5_Msk       (0x1U << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos       (6U)                                            
+#define CAN_F5R2_FB6_Msk       (0x1U << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos       (7U)                                            
+#define CAN_F5R2_FB7_Msk       (0x1U << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos       (8U)                                            
+#define CAN_F5R2_FB8_Msk       (0x1U << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos       (9U)                                            
+#define CAN_F5R2_FB9_Msk       (0x1U << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos      (10U)                                           
+#define CAN_F5R2_FB10_Msk      (0x1U << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos      (11U)                                           
+#define CAN_F5R2_FB11_Msk      (0x1U << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos      (12U)                                           
+#define CAN_F5R2_FB12_Msk      (0x1U << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos      (13U)                                           
+#define CAN_F5R2_FB13_Msk      (0x1U << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos      (14U)                                           
+#define CAN_F5R2_FB14_Msk      (0x1U << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos      (15U)                                           
+#define CAN_F5R2_FB15_Msk      (0x1U << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos      (16U)                                           
+#define CAN_F5R2_FB16_Msk      (0x1U << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos      (17U)                                           
+#define CAN_F5R2_FB17_Msk      (0x1U << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos      (18U)                                           
+#define CAN_F5R2_FB18_Msk      (0x1U << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos      (19U)                                           
+#define CAN_F5R2_FB19_Msk      (0x1U << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos      (20U)                                           
+#define CAN_F5R2_FB20_Msk      (0x1U << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos      (21U)                                           
+#define CAN_F5R2_FB21_Msk      (0x1U << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos      (22U)                                           
+#define CAN_F5R2_FB22_Msk      (0x1U << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos      (23U)                                           
+#define CAN_F5R2_FB23_Msk      (0x1U << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos      (24U)                                           
+#define CAN_F5R2_FB24_Msk      (0x1U << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos      (25U)                                           
+#define CAN_F5R2_FB25_Msk      (0x1U << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos      (26U)                                           
+#define CAN_F5R2_FB26_Msk      (0x1U << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos      (27U)                                           
+#define CAN_F5R2_FB27_Msk      (0x1U << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos      (28U)                                           
+#define CAN_F5R2_FB28_Msk      (0x1U << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos      (29U)                                           
+#define CAN_F5R2_FB29_Msk      (0x1U << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos      (30U)                                           
+#define CAN_F5R2_FB30_Msk      (0x1U << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos      (31U)                                           
+#define CAN_F5R2_FB31_Msk      (0x1U << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define CAN_F6R2_FB0_Pos       (0U)                                            
+#define CAN_F6R2_FB0_Msk       (0x1U << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos       (1U)                                            
+#define CAN_F6R2_FB1_Msk       (0x1U << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos       (2U)                                            
+#define CAN_F6R2_FB2_Msk       (0x1U << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos       (3U)                                            
+#define CAN_F6R2_FB3_Msk       (0x1U << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos       (4U)                                            
+#define CAN_F6R2_FB4_Msk       (0x1U << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos       (5U)                                            
+#define CAN_F6R2_FB5_Msk       (0x1U << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos       (6U)                                            
+#define CAN_F6R2_FB6_Msk       (0x1U << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos       (7U)                                            
+#define CAN_F6R2_FB7_Msk       (0x1U << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos       (8U)                                            
+#define CAN_F6R2_FB8_Msk       (0x1U << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos       (9U)                                            
+#define CAN_F6R2_FB9_Msk       (0x1U << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos      (10U)                                           
+#define CAN_F6R2_FB10_Msk      (0x1U << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos      (11U)                                           
+#define CAN_F6R2_FB11_Msk      (0x1U << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos      (12U)                                           
+#define CAN_F6R2_FB12_Msk      (0x1U << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos      (13U)                                           
+#define CAN_F6R2_FB13_Msk      (0x1U << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos      (14U)                                           
+#define CAN_F6R2_FB14_Msk      (0x1U << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos      (15U)                                           
+#define CAN_F6R2_FB15_Msk      (0x1U << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos      (16U)                                           
+#define CAN_F6R2_FB16_Msk      (0x1U << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos      (17U)                                           
+#define CAN_F6R2_FB17_Msk      (0x1U << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos      (18U)                                           
+#define CAN_F6R2_FB18_Msk      (0x1U << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos      (19U)                                           
+#define CAN_F6R2_FB19_Msk      (0x1U << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos      (20U)                                           
+#define CAN_F6R2_FB20_Msk      (0x1U << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos      (21U)                                           
+#define CAN_F6R2_FB21_Msk      (0x1U << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos      (22U)                                           
+#define CAN_F6R2_FB22_Msk      (0x1U << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos      (23U)                                           
+#define CAN_F6R2_FB23_Msk      (0x1U << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos      (24U)                                           
+#define CAN_F6R2_FB24_Msk      (0x1U << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos      (25U)                                           
+#define CAN_F6R2_FB25_Msk      (0x1U << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos      (26U)                                           
+#define CAN_F6R2_FB26_Msk      (0x1U << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos      (27U)                                           
+#define CAN_F6R2_FB27_Msk      (0x1U << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos      (28U)                                           
+#define CAN_F6R2_FB28_Msk      (0x1U << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos      (29U)                                           
+#define CAN_F6R2_FB29_Msk      (0x1U << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos      (30U)                                           
+#define CAN_F6R2_FB30_Msk      (0x1U << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos      (31U)                                           
+#define CAN_F6R2_FB31_Msk      (0x1U << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define CAN_F7R2_FB0_Pos       (0U)                                            
+#define CAN_F7R2_FB0_Msk       (0x1U << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos       (1U)                                            
+#define CAN_F7R2_FB1_Msk       (0x1U << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos       (2U)                                            
+#define CAN_F7R2_FB2_Msk       (0x1U << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos       (3U)                                            
+#define CAN_F7R2_FB3_Msk       (0x1U << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos       (4U)                                            
+#define CAN_F7R2_FB4_Msk       (0x1U << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos       (5U)                                            
+#define CAN_F7R2_FB5_Msk       (0x1U << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos       (6U)                                            
+#define CAN_F7R2_FB6_Msk       (0x1U << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos       (7U)                                            
+#define CAN_F7R2_FB7_Msk       (0x1U << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos       (8U)                                            
+#define CAN_F7R2_FB8_Msk       (0x1U << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos       (9U)                                            
+#define CAN_F7R2_FB9_Msk       (0x1U << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos      (10U)                                           
+#define CAN_F7R2_FB10_Msk      (0x1U << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos      (11U)                                           
+#define CAN_F7R2_FB11_Msk      (0x1U << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos      (12U)                                           
+#define CAN_F7R2_FB12_Msk      (0x1U << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos      (13U)                                           
+#define CAN_F7R2_FB13_Msk      (0x1U << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos      (14U)                                           
+#define CAN_F7R2_FB14_Msk      (0x1U << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos      (15U)                                           
+#define CAN_F7R2_FB15_Msk      (0x1U << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos      (16U)                                           
+#define CAN_F7R2_FB16_Msk      (0x1U << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos      (17U)                                           
+#define CAN_F7R2_FB17_Msk      (0x1U << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos      (18U)                                           
+#define CAN_F7R2_FB18_Msk      (0x1U << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos      (19U)                                           
+#define CAN_F7R2_FB19_Msk      (0x1U << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos      (20U)                                           
+#define CAN_F7R2_FB20_Msk      (0x1U << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos      (21U)                                           
+#define CAN_F7R2_FB21_Msk      (0x1U << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos      (22U)                                           
+#define CAN_F7R2_FB22_Msk      (0x1U << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos      (23U)                                           
+#define CAN_F7R2_FB23_Msk      (0x1U << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos      (24U)                                           
+#define CAN_F7R2_FB24_Msk      (0x1U << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos      (25U)                                           
+#define CAN_F7R2_FB25_Msk      (0x1U << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos      (26U)                                           
+#define CAN_F7R2_FB26_Msk      (0x1U << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos      (27U)                                           
+#define CAN_F7R2_FB27_Msk      (0x1U << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos      (28U)                                           
+#define CAN_F7R2_FB28_Msk      (0x1U << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos      (29U)                                           
+#define CAN_F7R2_FB29_Msk      (0x1U << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos      (30U)                                           
+#define CAN_F7R2_FB30_Msk      (0x1U << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos      (31U)                                           
+#define CAN_F7R2_FB31_Msk      (0x1U << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define CAN_F8R2_FB0_Pos       (0U)                                            
+#define CAN_F8R2_FB0_Msk       (0x1U << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos       (1U)                                            
+#define CAN_F8R2_FB1_Msk       (0x1U << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos       (2U)                                            
+#define CAN_F8R2_FB2_Msk       (0x1U << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos       (3U)                                            
+#define CAN_F8R2_FB3_Msk       (0x1U << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos       (4U)                                            
+#define CAN_F8R2_FB4_Msk       (0x1U << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos       (5U)                                            
+#define CAN_F8R2_FB5_Msk       (0x1U << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos       (6U)                                            
+#define CAN_F8R2_FB6_Msk       (0x1U << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos       (7U)                                            
+#define CAN_F8R2_FB7_Msk       (0x1U << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos       (8U)                                            
+#define CAN_F8R2_FB8_Msk       (0x1U << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos       (9U)                                            
+#define CAN_F8R2_FB9_Msk       (0x1U << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos      (10U)                                           
+#define CAN_F8R2_FB10_Msk      (0x1U << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos      (11U)                                           
+#define CAN_F8R2_FB11_Msk      (0x1U << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos      (12U)                                           
+#define CAN_F8R2_FB12_Msk      (0x1U << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos      (13U)                                           
+#define CAN_F8R2_FB13_Msk      (0x1U << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos      (14U)                                           
+#define CAN_F8R2_FB14_Msk      (0x1U << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos      (15U)                                           
+#define CAN_F8R2_FB15_Msk      (0x1U << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos      (16U)                                           
+#define CAN_F8R2_FB16_Msk      (0x1U << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos      (17U)                                           
+#define CAN_F8R2_FB17_Msk      (0x1U << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos      (18U)                                           
+#define CAN_F8R2_FB18_Msk      (0x1U << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos      (19U)                                           
+#define CAN_F8R2_FB19_Msk      (0x1U << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos      (20U)                                           
+#define CAN_F8R2_FB20_Msk      (0x1U << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos      (21U)                                           
+#define CAN_F8R2_FB21_Msk      (0x1U << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos      (22U)                                           
+#define CAN_F8R2_FB22_Msk      (0x1U << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos      (23U)                                           
+#define CAN_F8R2_FB23_Msk      (0x1U << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos      (24U)                                           
+#define CAN_F8R2_FB24_Msk      (0x1U << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos      (25U)                                           
+#define CAN_F8R2_FB25_Msk      (0x1U << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos      (26U)                                           
+#define CAN_F8R2_FB26_Msk      (0x1U << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos      (27U)                                           
+#define CAN_F8R2_FB27_Msk      (0x1U << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos      (28U)                                           
+#define CAN_F8R2_FB28_Msk      (0x1U << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos      (29U)                                           
+#define CAN_F8R2_FB29_Msk      (0x1U << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos      (30U)                                           
+#define CAN_F8R2_FB30_Msk      (0x1U << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos      (31U)                                           
+#define CAN_F8R2_FB31_Msk      (0x1U << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define CAN_F9R2_FB0_Pos       (0U)                                            
+#define CAN_F9R2_FB0_Msk       (0x1U << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos       (1U)                                            
+#define CAN_F9R2_FB1_Msk       (0x1U << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos       (2U)                                            
+#define CAN_F9R2_FB2_Msk       (0x1U << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos       (3U)                                            
+#define CAN_F9R2_FB3_Msk       (0x1U << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos       (4U)                                            
+#define CAN_F9R2_FB4_Msk       (0x1U << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos       (5U)                                            
+#define CAN_F9R2_FB5_Msk       (0x1U << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos       (6U)                                            
+#define CAN_F9R2_FB6_Msk       (0x1U << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos       (7U)                                            
+#define CAN_F9R2_FB7_Msk       (0x1U << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos       (8U)                                            
+#define CAN_F9R2_FB8_Msk       (0x1U << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos       (9U)                                            
+#define CAN_F9R2_FB9_Msk       (0x1U << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos      (10U)                                           
+#define CAN_F9R2_FB10_Msk      (0x1U << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos      (11U)                                           
+#define CAN_F9R2_FB11_Msk      (0x1U << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos      (12U)                                           
+#define CAN_F9R2_FB12_Msk      (0x1U << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos      (13U)                                           
+#define CAN_F9R2_FB13_Msk      (0x1U << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos      (14U)                                           
+#define CAN_F9R2_FB14_Msk      (0x1U << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos      (15U)                                           
+#define CAN_F9R2_FB15_Msk      (0x1U << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos      (16U)                                           
+#define CAN_F9R2_FB16_Msk      (0x1U << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos      (17U)                                           
+#define CAN_F9R2_FB17_Msk      (0x1U << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos      (18U)                                           
+#define CAN_F9R2_FB18_Msk      (0x1U << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos      (19U)                                           
+#define CAN_F9R2_FB19_Msk      (0x1U << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos      (20U)                                           
+#define CAN_F9R2_FB20_Msk      (0x1U << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos      (21U)                                           
+#define CAN_F9R2_FB21_Msk      (0x1U << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos      (22U)                                           
+#define CAN_F9R2_FB22_Msk      (0x1U << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos      (23U)                                           
+#define CAN_F9R2_FB23_Msk      (0x1U << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos      (24U)                                           
+#define CAN_F9R2_FB24_Msk      (0x1U << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos      (25U)                                           
+#define CAN_F9R2_FB25_Msk      (0x1U << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos      (26U)                                           
+#define CAN_F9R2_FB26_Msk      (0x1U << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos      (27U)                                           
+#define CAN_F9R2_FB27_Msk      (0x1U << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos      (28U)                                           
+#define CAN_F9R2_FB28_Msk      (0x1U << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos      (29U)                                           
+#define CAN_F9R2_FB29_Msk      (0x1U << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos      (30U)                                           
+#define CAN_F9R2_FB30_Msk      (0x1U << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos      (31U)                                           
+#define CAN_F9R2_FB31_Msk      (0x1U << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define CAN_F10R2_FB0_Pos      (0U)                                            
+#define CAN_F10R2_FB0_Msk      (0x1U << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos      (1U)                                            
+#define CAN_F10R2_FB1_Msk      (0x1U << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos      (2U)                                            
+#define CAN_F10R2_FB2_Msk      (0x1U << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos      (3U)                                            
+#define CAN_F10R2_FB3_Msk      (0x1U << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos      (4U)                                            
+#define CAN_F10R2_FB4_Msk      (0x1U << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos      (5U)                                            
+#define CAN_F10R2_FB5_Msk      (0x1U << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos      (6U)                                            
+#define CAN_F10R2_FB6_Msk      (0x1U << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos      (7U)                                            
+#define CAN_F10R2_FB7_Msk      (0x1U << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos      (8U)                                            
+#define CAN_F10R2_FB8_Msk      (0x1U << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos      (9U)                                            
+#define CAN_F10R2_FB9_Msk      (0x1U << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos     (10U)                                           
+#define CAN_F10R2_FB10_Msk     (0x1U << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos     (11U)                                           
+#define CAN_F10R2_FB11_Msk     (0x1U << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos     (12U)                                           
+#define CAN_F10R2_FB12_Msk     (0x1U << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos     (13U)                                           
+#define CAN_F10R2_FB13_Msk     (0x1U << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos     (14U)                                           
+#define CAN_F10R2_FB14_Msk     (0x1U << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos     (15U)                                           
+#define CAN_F10R2_FB15_Msk     (0x1U << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos     (16U)                                           
+#define CAN_F10R2_FB16_Msk     (0x1U << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos     (17U)                                           
+#define CAN_F10R2_FB17_Msk     (0x1U << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos     (18U)                                           
+#define CAN_F10R2_FB18_Msk     (0x1U << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos     (19U)                                           
+#define CAN_F10R2_FB19_Msk     (0x1U << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos     (20U)                                           
+#define CAN_F10R2_FB20_Msk     (0x1U << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos     (21U)                                           
+#define CAN_F10R2_FB21_Msk     (0x1U << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos     (22U)                                           
+#define CAN_F10R2_FB22_Msk     (0x1U << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos     (23U)                                           
+#define CAN_F10R2_FB23_Msk     (0x1U << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos     (24U)                                           
+#define CAN_F10R2_FB24_Msk     (0x1U << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos     (25U)                                           
+#define CAN_F10R2_FB25_Msk     (0x1U << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos     (26U)                                           
+#define CAN_F10R2_FB26_Msk     (0x1U << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos     (27U)                                           
+#define CAN_F10R2_FB27_Msk     (0x1U << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos     (28U)                                           
+#define CAN_F10R2_FB28_Msk     (0x1U << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos     (29U)                                           
+#define CAN_F10R2_FB29_Msk     (0x1U << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos     (30U)                                           
+#define CAN_F10R2_FB30_Msk     (0x1U << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos     (31U)                                           
+#define CAN_F10R2_FB31_Msk     (0x1U << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define CAN_F11R2_FB0_Pos      (0U)                                            
+#define CAN_F11R2_FB0_Msk      (0x1U << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos      (1U)                                            
+#define CAN_F11R2_FB1_Msk      (0x1U << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos      (2U)                                            
+#define CAN_F11R2_FB2_Msk      (0x1U << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos      (3U)                                            
+#define CAN_F11R2_FB3_Msk      (0x1U << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos      (4U)                                            
+#define CAN_F11R2_FB4_Msk      (0x1U << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos      (5U)                                            
+#define CAN_F11R2_FB5_Msk      (0x1U << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos      (6U)                                            
+#define CAN_F11R2_FB6_Msk      (0x1U << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos      (7U)                                            
+#define CAN_F11R2_FB7_Msk      (0x1U << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos      (8U)                                            
+#define CAN_F11R2_FB8_Msk      (0x1U << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos      (9U)                                            
+#define CAN_F11R2_FB9_Msk      (0x1U << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos     (10U)                                           
+#define CAN_F11R2_FB10_Msk     (0x1U << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos     (11U)                                           
+#define CAN_F11R2_FB11_Msk     (0x1U << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos     (12U)                                           
+#define CAN_F11R2_FB12_Msk     (0x1U << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos     (13U)                                           
+#define CAN_F11R2_FB13_Msk     (0x1U << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos     (14U)                                           
+#define CAN_F11R2_FB14_Msk     (0x1U << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos     (15U)                                           
+#define CAN_F11R2_FB15_Msk     (0x1U << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos     (16U)                                           
+#define CAN_F11R2_FB16_Msk     (0x1U << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos     (17U)                                           
+#define CAN_F11R2_FB17_Msk     (0x1U << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos     (18U)                                           
+#define CAN_F11R2_FB18_Msk     (0x1U << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos     (19U)                                           
+#define CAN_F11R2_FB19_Msk     (0x1U << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos     (20U)                                           
+#define CAN_F11R2_FB20_Msk     (0x1U << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos     (21U)                                           
+#define CAN_F11R2_FB21_Msk     (0x1U << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos     (22U)                                           
+#define CAN_F11R2_FB22_Msk     (0x1U << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos     (23U)                                           
+#define CAN_F11R2_FB23_Msk     (0x1U << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos     (24U)                                           
+#define CAN_F11R2_FB24_Msk     (0x1U << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos     (25U)                                           
+#define CAN_F11R2_FB25_Msk     (0x1U << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos     (26U)                                           
+#define CAN_F11R2_FB26_Msk     (0x1U << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos     (27U)                                           
+#define CAN_F11R2_FB27_Msk     (0x1U << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos     (28U)                                           
+#define CAN_F11R2_FB28_Msk     (0x1U << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos     (29U)                                           
+#define CAN_F11R2_FB29_Msk     (0x1U << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos     (30U)                                           
+#define CAN_F11R2_FB30_Msk     (0x1U << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos     (31U)                                           
+#define CAN_F11R2_FB31_Msk     (0x1U << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define CAN_F12R2_FB0_Pos      (0U)                                            
+#define CAN_F12R2_FB0_Msk      (0x1U << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos      (1U)                                            
+#define CAN_F12R2_FB1_Msk      (0x1U << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos      (2U)                                            
+#define CAN_F12R2_FB2_Msk      (0x1U << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos      (3U)                                            
+#define CAN_F12R2_FB3_Msk      (0x1U << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos      (4U)                                            
+#define CAN_F12R2_FB4_Msk      (0x1U << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos      (5U)                                            
+#define CAN_F12R2_FB5_Msk      (0x1U << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos      (6U)                                            
+#define CAN_F12R2_FB6_Msk      (0x1U << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos      (7U)                                            
+#define CAN_F12R2_FB7_Msk      (0x1U << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos      (8U)                                            
+#define CAN_F12R2_FB8_Msk      (0x1U << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos      (9U)                                            
+#define CAN_F12R2_FB9_Msk      (0x1U << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos     (10U)                                           
+#define CAN_F12R2_FB10_Msk     (0x1U << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos     (11U)                                           
+#define CAN_F12R2_FB11_Msk     (0x1U << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos     (12U)                                           
+#define CAN_F12R2_FB12_Msk     (0x1U << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos     (13U)                                           
+#define CAN_F12R2_FB13_Msk     (0x1U << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos     (14U)                                           
+#define CAN_F12R2_FB14_Msk     (0x1U << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos     (15U)                                           
+#define CAN_F12R2_FB15_Msk     (0x1U << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos     (16U)                                           
+#define CAN_F12R2_FB16_Msk     (0x1U << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos     (17U)                                           
+#define CAN_F12R2_FB17_Msk     (0x1U << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos     (18U)                                           
+#define CAN_F12R2_FB18_Msk     (0x1U << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos     (19U)                                           
+#define CAN_F12R2_FB19_Msk     (0x1U << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos     (20U)                                           
+#define CAN_F12R2_FB20_Msk     (0x1U << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos     (21U)                                           
+#define CAN_F12R2_FB21_Msk     (0x1U << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos     (22U)                                           
+#define CAN_F12R2_FB22_Msk     (0x1U << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos     (23U)                                           
+#define CAN_F12R2_FB23_Msk     (0x1U << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos     (24U)                                           
+#define CAN_F12R2_FB24_Msk     (0x1U << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos     (25U)                                           
+#define CAN_F12R2_FB25_Msk     (0x1U << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos     (26U)                                           
+#define CAN_F12R2_FB26_Msk     (0x1U << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos     (27U)                                           
+#define CAN_F12R2_FB27_Msk     (0x1U << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos     (28U)                                           
+#define CAN_F12R2_FB28_Msk     (0x1U << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos     (29U)                                           
+#define CAN_F12R2_FB29_Msk     (0x1U << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos     (30U)                                           
+#define CAN_F12R2_FB30_Msk     (0x1U << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos     (31U)                                           
+#define CAN_F12R2_FB31_Msk     (0x1U << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define CAN_F13R2_FB0_Pos      (0U)                                            
+#define CAN_F13R2_FB0_Msk      (0x1U << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos      (1U)                                            
+#define CAN_F13R2_FB1_Msk      (0x1U << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos      (2U)                                            
+#define CAN_F13R2_FB2_Msk      (0x1U << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos      (3U)                                            
+#define CAN_F13R2_FB3_Msk      (0x1U << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos      (4U)                                            
+#define CAN_F13R2_FB4_Msk      (0x1U << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos      (5U)                                            
+#define CAN_F13R2_FB5_Msk      (0x1U << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos      (6U)                                            
+#define CAN_F13R2_FB6_Msk      (0x1U << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos      (7U)                                            
+#define CAN_F13R2_FB7_Msk      (0x1U << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos      (8U)                                            
+#define CAN_F13R2_FB8_Msk      (0x1U << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos      (9U)                                            
+#define CAN_F13R2_FB9_Msk      (0x1U << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos     (10U)                                           
+#define CAN_F13R2_FB10_Msk     (0x1U << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos     (11U)                                           
+#define CAN_F13R2_FB11_Msk     (0x1U << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos     (12U)                                           
+#define CAN_F13R2_FB12_Msk     (0x1U << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos     (13U)                                           
+#define CAN_F13R2_FB13_Msk     (0x1U << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos     (14U)                                           
+#define CAN_F13R2_FB14_Msk     (0x1U << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos     (15U)                                           
+#define CAN_F13R2_FB15_Msk     (0x1U << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos     (16U)                                           
+#define CAN_F13R2_FB16_Msk     (0x1U << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos     (17U)                                           
+#define CAN_F13R2_FB17_Msk     (0x1U << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos     (18U)                                           
+#define CAN_F13R2_FB18_Msk     (0x1U << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos     (19U)                                           
+#define CAN_F13R2_FB19_Msk     (0x1U << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos     (20U)                                           
+#define CAN_F13R2_FB20_Msk     (0x1U << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos     (21U)                                           
+#define CAN_F13R2_FB21_Msk     (0x1U << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos     (22U)                                           
+#define CAN_F13R2_FB22_Msk     (0x1U << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos     (23U)                                           
+#define CAN_F13R2_FB23_Msk     (0x1U << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos     (24U)                                           
+#define CAN_F13R2_FB24_Msk     (0x1U << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos     (25U)                                           
+#define CAN_F13R2_FB25_Msk     (0x1U << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos     (26U)                                           
+#define CAN_F13R2_FB26_Msk     (0x1U << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos     (27U)                                           
+#define CAN_F13R2_FB27_Msk     (0x1U << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos     (28U)                                           
+#define CAN_F13R2_FB28_Msk     (0x1U << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos     (29U)                                           
+#define CAN_F13R2_FB29_Msk     (0x1U << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos     (30U)                                           
+#define CAN_F13R2_FB30_Msk     (0x1U << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos     (31U)                                           
+#define CAN_F13R2_FB31_Msk     (0x1U << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                     CRC calculation unit (CRC)                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos            (0U)                                          
+#define CRC_DR_DR_Msk            (0xFFFFFFFFU << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR              ((uint8_t)0xFFU)                              /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos         (0U)                                          
+#define CRC_CR_RESET_Msk         (0x1U << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos      (3U)                                          
+#define CRC_CR_POLYSIZE_Msk      (0x3U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0        (0x1U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1        (0x2U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos        (5U)                                          
+#define CRC_CR_REV_IN_Msk        (0x3U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0          (0x1U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1          (0x2U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos       (7U)                                          
+#define CRC_CR_REV_OUT_Msk       (0x1U << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos        (0U)                                          
+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFU << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos          (0U)                                          
+#define CRC_POL_POL_Msk          (0xFFFFFFFFU << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital to Analog Converter (DAC)                          */
+/*                                                                            */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available (may not be available on all DAC instances DACx) */
+
+
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos              (0U)                                       
+#define DAC_CR_EN1_Msk              (0x1U << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos            (1U)                                       
+#define DAC_CR_BOFF1_Msk            (0x1U << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
+#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos             (2U)                                       
+#define DAC_CR_TEN1_Msk             (0x1U << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos            (3U)                                       
+#define DAC_CR_TSEL1_Msk            (0x7U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0              (0x1U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1              (0x2U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2              (0x4U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos            (6U)                                       
+#define DAC_CR_WAVE1_Msk            (0x3U << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0              (0x1U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1              (0x2U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos            (8U)                                       
+#define DAC_CR_MAMP1_Msk            (0xFU << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0              (0x1U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1              (0x2U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2              (0x4U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3              (0x8U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos           (12U)                                      
+#define DAC_CR_DMAEN1_Msk           (0x1U << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos        (13U)                                      
+#define DAC_CR_DMAUDRIE1_Msk        (0x1U << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!< DAC channel1 DMA underrun IT enable */ 
+#define DAC_CR_EN2_Pos              (16U)                                      
+#define DAC_CR_EN2_Msk              (0x1U << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos            (17U)                                      
+#define DAC_CR_BOFF2_Msk            (0x1U << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
+#define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos             (18U)                                      
+#define DAC_CR_TEN2_Msk             (0x1U << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos            (19U)                                      
+#define DAC_CR_TSEL2_Msk            (0x7U << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0              (0x1U << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1              (0x2U << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2              (0x4U << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos            (22U)                                      
+#define DAC_CR_WAVE2_Msk            (0x3U << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0              (0x1U << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1              (0x2U << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos            (24U)                                      
+#define DAC_CR_MAMP2_Msk            (0xFU << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0              (0x1U << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1              (0x2U << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2              (0x4U << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3              (0x8U << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos           (28U)                                      
+#define DAC_CR_DMAEN2_Msk           (0x1U << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!< DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos        (29U)                                      
+#define DAC_CR_DMAUDRIE2_Msk        (0x1U << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!< DAC channel2 DMA underrun IT enable */ 
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)                                       
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)                                       
+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1U << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!< DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)                                       
+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)                                       
+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)                                       
+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFU << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!< DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)                                      
+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)                                      
+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)                                       
+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!< DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos       (0U)                                       
+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFU << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!< DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos       (0U)                                       
+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFU << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!< DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DMAUDR1_Pos          (13U)                                      
+#define DAC_SR_DMAUDR1_Msk          (0x1U << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2_Pos          (29U)                                      
+#define DAC_SR_DMAUDR2_Msk          (0x1U << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU (DBGMCU)                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)                      
+#define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk  
+#define DBGMCU_IDCODE_REV_ID_Pos                     (16U)                     
+#define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk  
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)                      
+#define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk   
+#define DBGMCU_CR_DBG_STOP_Pos                       (1U)                      
+#define DBGMCU_CR_DBG_STOP_Msk                       (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk    
+#define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)                      
+#define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk 
+#define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)                      
+#define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk  
+
+#define DBGMCU_CR_TRACE_MODE_Pos                     (6U)                      
+#define DBGMCU_CR_TRACE_MODE_Msk                     (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk  
+#define DBGMCU_CR_TRACE_MODE_0                       (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1                       (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)                     
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)                     
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)                     
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)                     
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk 
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)                     
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk 
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (30U)                     
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x40000000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk 
+#define DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos              (25U)                     
+#define DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk              (0x1U << DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN_STOP                  DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk 
+
+/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)                      
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk 
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)                      
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk 
+#define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos            (2U)                      
+#define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk            (0x1U << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM15_STOP                DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk 
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos            (3U)                      
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk            (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP                DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk 
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos            (4U)                      
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk            (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP                DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk 
+#define DBGMCU_APB2_FZ_DBG_TIM20_STOP_Pos            (5U)                      
+#define DBGMCU_APB2_FZ_DBG_TIM20_STOP_Msk            (0x1U << DBGMCU_APB2_FZ_DBG_TIM20_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB2_FZ_DBG_TIM20_STOP                DBGMCU_APB2_FZ_DBG_TIM20_STOP_Msk 
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller (DMA)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define DMA_ISR_GIF1_Pos       (0U)                                            
+#define DMA_ISR_GIF1_Msk       (0x1U << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
+#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos      (1U)                                            
+#define DMA_ISR_TCIF1_Msk      (0x1U << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
+#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos      (2U)                                            
+#define DMA_ISR_HTIF1_Msk      (0x1U << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
+#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos      (3U)                                            
+#define DMA_ISR_TEIF1_Msk      (0x1U << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
+#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos       (4U)                                            
+#define DMA_ISR_GIF2_Msk       (0x1U << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
+#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos      (5U)                                            
+#define DMA_ISR_TCIF2_Msk      (0x1U << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
+#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos      (6U)                                            
+#define DMA_ISR_HTIF2_Msk      (0x1U << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
+#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos      (7U)                                            
+#define DMA_ISR_TEIF2_Msk      (0x1U << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
+#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos       (8U)                                            
+#define DMA_ISR_GIF3_Msk       (0x1U << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
+#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos      (9U)                                            
+#define DMA_ISR_TCIF3_Msk      (0x1U << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
+#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos      (10U)                                           
+#define DMA_ISR_HTIF3_Msk      (0x1U << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
+#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos      (11U)                                           
+#define DMA_ISR_TEIF3_Msk      (0x1U << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
+#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos       (12U)                                           
+#define DMA_ISR_GIF4_Msk       (0x1U << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
+#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos      (13U)                                           
+#define DMA_ISR_TCIF4_Msk      (0x1U << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
+#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos      (14U)                                           
+#define DMA_ISR_HTIF4_Msk      (0x1U << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
+#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos      (15U)                                           
+#define DMA_ISR_TEIF4_Msk      (0x1U << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
+#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos       (16U)                                           
+#define DMA_ISR_GIF5_Msk       (0x1U << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
+#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos      (17U)                                           
+#define DMA_ISR_TCIF5_Msk      (0x1U << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
+#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos      (18U)                                           
+#define DMA_ISR_HTIF5_Msk      (0x1U << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
+#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos      (19U)                                           
+#define DMA_ISR_TEIF5_Msk      (0x1U << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
+#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos       (20U)                                           
+#define DMA_ISR_GIF6_Msk       (0x1U << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
+#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos      (21U)                                           
+#define DMA_ISR_TCIF6_Msk      (0x1U << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
+#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos      (22U)                                           
+#define DMA_ISR_HTIF6_Msk      (0x1U << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
+#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos      (23U)                                           
+#define DMA_ISR_TEIF6_Msk      (0x1U << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
+#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos       (24U)                                           
+#define DMA_ISR_GIF7_Msk       (0x1U << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
+#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos      (25U)                                           
+#define DMA_ISR_TCIF7_Msk      (0x1U << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
+#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos      (26U)                                           
+#define DMA_ISR_HTIF7_Msk      (0x1U << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
+#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos      (27U)                                           
+#define DMA_ISR_TEIF7_Msk      (0x1U << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
+#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define DMA_IFCR_CGIF1_Pos     (0U)                                            
+#define DMA_IFCR_CGIF1_Msk     (0x1U << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos    (1U)                                            
+#define DMA_IFCR_CTCIF1_Msk    (0x1U << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos    (2U)                                            
+#define DMA_IFCR_CHTIF1_Msk    (0x1U << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos    (3U)                                            
+#define DMA_IFCR_CTEIF1_Msk    (0x1U << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos     (4U)                                            
+#define DMA_IFCR_CGIF2_Msk     (0x1U << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos    (5U)                                            
+#define DMA_IFCR_CTCIF2_Msk    (0x1U << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos    (6U)                                            
+#define DMA_IFCR_CHTIF2_Msk    (0x1U << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos    (7U)                                            
+#define DMA_IFCR_CTEIF2_Msk    (0x1U << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos     (8U)                                            
+#define DMA_IFCR_CGIF3_Msk     (0x1U << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos    (9U)                                            
+#define DMA_IFCR_CTCIF3_Msk    (0x1U << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos    (10U)                                           
+#define DMA_IFCR_CHTIF3_Msk    (0x1U << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos    (11U)                                           
+#define DMA_IFCR_CTEIF3_Msk    (0x1U << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos     (12U)                                           
+#define DMA_IFCR_CGIF4_Msk     (0x1U << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos    (13U)                                           
+#define DMA_IFCR_CTCIF4_Msk    (0x1U << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos    (14U)                                           
+#define DMA_IFCR_CHTIF4_Msk    (0x1U << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos    (15U)                                           
+#define DMA_IFCR_CTEIF4_Msk    (0x1U << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos     (16U)                                           
+#define DMA_IFCR_CGIF5_Msk     (0x1U << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos    (17U)                                           
+#define DMA_IFCR_CTCIF5_Msk    (0x1U << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos    (18U)                                           
+#define DMA_IFCR_CHTIF5_Msk    (0x1U << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos    (19U)                                           
+#define DMA_IFCR_CTEIF5_Msk    (0x1U << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos     (20U)                                           
+#define DMA_IFCR_CGIF6_Msk     (0x1U << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos    (21U)                                           
+#define DMA_IFCR_CTCIF6_Msk    (0x1U << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos    (22U)                                           
+#define DMA_IFCR_CHTIF6_Msk    (0x1U << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos    (23U)                                           
+#define DMA_IFCR_CTEIF6_Msk    (0x1U << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos     (24U)                                           
+#define DMA_IFCR_CGIF7_Msk     (0x1U << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos    (25U)                                           
+#define DMA_IFCR_CTCIF7_Msk    (0x1U << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos    (26U)                                           
+#define DMA_IFCR_CHTIF7_Msk    (0x1U << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos    (27U)                                           
+#define DMA_IFCR_CTEIF7_Msk    (0x1U << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define DMA_CCR_EN_Pos         (0U)                                            
+#define DMA_CCR_EN_Msk         (0x1U << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
+#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
+#define DMA_CCR_TCIE_Pos       (1U)                                            
+#define DMA_CCR_TCIE_Msk       (0x1U << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
+#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
+#define DMA_CCR_HTIE_Pos       (2U)                                            
+#define DMA_CCR_HTIE_Msk       (0x1U << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
+#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
+#define DMA_CCR_TEIE_Pos       (3U)                                            
+#define DMA_CCR_TEIE_Msk       (0x1U << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
+#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
+#define DMA_CCR_DIR_Pos        (4U)                                            
+#define DMA_CCR_DIR_Msk        (0x1U << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
+#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
+#define DMA_CCR_CIRC_Pos       (5U)                                            
+#define DMA_CCR_CIRC_Msk       (0x1U << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
+#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
+#define DMA_CCR_PINC_Pos       (6U)                                            
+#define DMA_CCR_PINC_Msk       (0x1U << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
+#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
+#define DMA_CCR_MINC_Pos       (7U)                                            
+#define DMA_CCR_MINC_Msk       (0x1U << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
+#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
+
+#define DMA_CCR_PSIZE_Pos      (8U)                                            
+#define DMA_CCR_PSIZE_Msk      (0x3U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
+#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define DMA_CCR_PSIZE_0        (0x1U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1        (0x2U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos      (10U)                                           
+#define DMA_CCR_MSIZE_Msk      (0x3U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
+#define DMA_CCR_MSIZE_0        (0x1U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1        (0x2U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos         (12U)                                           
+#define DMA_CCR_PL_Msk         (0x3U << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
+#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0           (0x1U << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
+#define DMA_CCR_PL_1           (0x2U << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos    (14U)                                           
+#define DMA_CCR_MEM2MEM_Msk    (0x1U << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define DMA_CNDTR_NDT_Pos      (0U)                                            
+#define DMA_CNDTR_NDT_Msk      (0xFFFFU << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define DMA_CPAR_PA_Pos        (0U)                                            
+#define DMA_CPAR_PA_Msk        (0xFFFFFFFFU << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define DMA_CMAR_MA_Pos        (0U)                                            
+#define DMA_CMAR_MA_Msk        (0xFFFFFFFFU << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller (EXTI)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define EXTI_IMR_MR0_Pos           (0U)                                        
+#define EXTI_IMR_MR0_Msk           (0x1U << EXTI_IMR_MR0_Pos)                  /*!< 0x00000001 */
+#define EXTI_IMR_MR0               EXTI_IMR_MR0_Msk                            /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos           (1U)                                        
+#define EXTI_IMR_MR1_Msk           (0x1U << EXTI_IMR_MR1_Pos)                  /*!< 0x00000002 */
+#define EXTI_IMR_MR1               EXTI_IMR_MR1_Msk                            /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos           (2U)                                        
+#define EXTI_IMR_MR2_Msk           (0x1U << EXTI_IMR_MR2_Pos)                  /*!< 0x00000004 */
+#define EXTI_IMR_MR2               EXTI_IMR_MR2_Msk                            /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos           (3U)                                        
+#define EXTI_IMR_MR3_Msk           (0x1U << EXTI_IMR_MR3_Pos)                  /*!< 0x00000008 */
+#define EXTI_IMR_MR3               EXTI_IMR_MR3_Msk                            /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos           (4U)                                        
+#define EXTI_IMR_MR4_Msk           (0x1U << EXTI_IMR_MR4_Pos)                  /*!< 0x00000010 */
+#define EXTI_IMR_MR4               EXTI_IMR_MR4_Msk                            /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos           (5U)                                        
+#define EXTI_IMR_MR5_Msk           (0x1U << EXTI_IMR_MR5_Pos)                  /*!< 0x00000020 */
+#define EXTI_IMR_MR5               EXTI_IMR_MR5_Msk                            /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos           (6U)                                        
+#define EXTI_IMR_MR6_Msk           (0x1U << EXTI_IMR_MR6_Pos)                  /*!< 0x00000040 */
+#define EXTI_IMR_MR6               EXTI_IMR_MR6_Msk                            /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos           (7U)                                        
+#define EXTI_IMR_MR7_Msk           (0x1U << EXTI_IMR_MR7_Pos)                  /*!< 0x00000080 */
+#define EXTI_IMR_MR7               EXTI_IMR_MR7_Msk                            /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos           (8U)                                        
+#define EXTI_IMR_MR8_Msk           (0x1U << EXTI_IMR_MR8_Pos)                  /*!< 0x00000100 */
+#define EXTI_IMR_MR8               EXTI_IMR_MR8_Msk                            /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos           (9U)                                        
+#define EXTI_IMR_MR9_Msk           (0x1U << EXTI_IMR_MR9_Pos)                  /*!< 0x00000200 */
+#define EXTI_IMR_MR9               EXTI_IMR_MR9_Msk                            /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos          (10U)                                       
+#define EXTI_IMR_MR10_Msk          (0x1U << EXTI_IMR_MR10_Pos)                 /*!< 0x00000400 */
+#define EXTI_IMR_MR10              EXTI_IMR_MR10_Msk                           /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos          (11U)                                       
+#define EXTI_IMR_MR11_Msk          (0x1U << EXTI_IMR_MR11_Pos)                 /*!< 0x00000800 */
+#define EXTI_IMR_MR11              EXTI_IMR_MR11_Msk                           /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos          (12U)                                       
+#define EXTI_IMR_MR12_Msk          (0x1U << EXTI_IMR_MR12_Pos)                 /*!< 0x00001000 */
+#define EXTI_IMR_MR12              EXTI_IMR_MR12_Msk                           /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos          (13U)                                       
+#define EXTI_IMR_MR13_Msk          (0x1U << EXTI_IMR_MR13_Pos)                 /*!< 0x00002000 */
+#define EXTI_IMR_MR13              EXTI_IMR_MR13_Msk                           /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos          (14U)                                       
+#define EXTI_IMR_MR14_Msk          (0x1U << EXTI_IMR_MR14_Pos)                 /*!< 0x00004000 */
+#define EXTI_IMR_MR14              EXTI_IMR_MR14_Msk                           /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos          (15U)                                       
+#define EXTI_IMR_MR15_Msk          (0x1U << EXTI_IMR_MR15_Pos)                 /*!< 0x00008000 */
+#define EXTI_IMR_MR15              EXTI_IMR_MR15_Msk                           /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos          (16U)                                       
+#define EXTI_IMR_MR16_Msk          (0x1U << EXTI_IMR_MR16_Pos)                 /*!< 0x00010000 */
+#define EXTI_IMR_MR16              EXTI_IMR_MR16_Msk                           /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos          (17U)                                       
+#define EXTI_IMR_MR17_Msk          (0x1U << EXTI_IMR_MR17_Pos)                 /*!< 0x00020000 */
+#define EXTI_IMR_MR17              EXTI_IMR_MR17_Msk                           /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos          (18U)                                       
+#define EXTI_IMR_MR18_Msk          (0x1U << EXTI_IMR_MR18_Pos)                 /*!< 0x00040000 */
+#define EXTI_IMR_MR18              EXTI_IMR_MR18_Msk                           /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos          (19U)                                       
+#define EXTI_IMR_MR19_Msk          (0x1U << EXTI_IMR_MR19_Pos)                 /*!< 0x00080000 */
+#define EXTI_IMR_MR19              EXTI_IMR_MR19_Msk                           /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos          (20U)                                       
+#define EXTI_IMR_MR20_Msk          (0x1U << EXTI_IMR_MR20_Pos)                 /*!< 0x00100000 */
+#define EXTI_IMR_MR20              EXTI_IMR_MR20_Msk                           /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos          (21U)                                       
+#define EXTI_IMR_MR21_Msk          (0x1U << EXTI_IMR_MR21_Pos)                 /*!< 0x00200000 */
+#define EXTI_IMR_MR21              EXTI_IMR_MR21_Msk                           /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos          (22U)                                       
+#define EXTI_IMR_MR22_Msk          (0x1U << EXTI_IMR_MR22_Pos)                 /*!< 0x00400000 */
+#define EXTI_IMR_MR22              EXTI_IMR_MR22_Msk                           /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23_Pos          (23U)                                       
+#define EXTI_IMR_MR23_Msk          (0x1U << EXTI_IMR_MR23_Pos)                 /*!< 0x00800000 */
+#define EXTI_IMR_MR23              EXTI_IMR_MR23_Msk                           /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_MR24_Pos          (24U)                                       
+#define EXTI_IMR_MR24_Msk          (0x1U << EXTI_IMR_MR24_Pos)                 /*!< 0x01000000 */
+#define EXTI_IMR_MR24              EXTI_IMR_MR24_Msk                           /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR_MR25_Pos          (25U)                                       
+#define EXTI_IMR_MR25_Msk          (0x1U << EXTI_IMR_MR25_Pos)                 /*!< 0x02000000 */
+#define EXTI_IMR_MR25              EXTI_IMR_MR25_Msk                           /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_MR26_Pos          (26U)                                       
+#define EXTI_IMR_MR26_Msk          (0x1U << EXTI_IMR_MR26_Pos)                 /*!< 0x04000000 */
+#define EXTI_IMR_MR26              EXTI_IMR_MR26_Msk                           /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_MR27_Pos          (27U)                                       
+#define EXTI_IMR_MR27_Msk          (0x1U << EXTI_IMR_MR27_Pos)                 /*!< 0x08000000 */
+#define EXTI_IMR_MR27              EXTI_IMR_MR27_Msk                           /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR_MR28_Pos          (28U)                                       
+#define EXTI_IMR_MR28_Msk          (0x1U << EXTI_IMR_MR28_Pos)                 /*!< 0x10000000 */
+#define EXTI_IMR_MR28              EXTI_IMR_MR28_Msk                           /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_MR29_Pos          (29U)                                       
+#define EXTI_IMR_MR29_Msk          (0x1U << EXTI_IMR_MR29_Pos)                 /*!< 0x20000000 */
+#define EXTI_IMR_MR29              EXTI_IMR_MR29_Msk                           /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR_MR30_Pos          (30U)                                       
+#define EXTI_IMR_MR30_Msk          (0x1U << EXTI_IMR_MR30_Pos)                 /*!< 0x40000000 */
+#define EXTI_IMR_MR30              EXTI_IMR_MR30_Msk                           /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR_MR31_Pos          (31U)                                       
+#define EXTI_IMR_MR31_Msk          (0x1U << EXTI_IMR_MR31_Pos)                 /*!< 0x80000000 */
+#define EXTI_IMR_MR31              EXTI_IMR_MR31_Msk                           /*!< Interrupt Mask on line 31 */
+
+/* References Defines */
+#define  EXTI_IMR_IM0 EXTI_IMR_MR0
+#define  EXTI_IMR_IM1 EXTI_IMR_MR1
+#define  EXTI_IMR_IM2 EXTI_IMR_MR2
+#define  EXTI_IMR_IM3 EXTI_IMR_MR3
+#define  EXTI_IMR_IM4 EXTI_IMR_MR4
+#define  EXTI_IMR_IM5 EXTI_IMR_MR5
+#define  EXTI_IMR_IM6 EXTI_IMR_MR6
+#define  EXTI_IMR_IM7 EXTI_IMR_MR7
+#define  EXTI_IMR_IM8 EXTI_IMR_MR8
+#define  EXTI_IMR_IM9 EXTI_IMR_MR9
+#define  EXTI_IMR_IM10 EXTI_IMR_MR10
+#define  EXTI_IMR_IM11 EXTI_IMR_MR11
+#define  EXTI_IMR_IM12 EXTI_IMR_MR12
+#define  EXTI_IMR_IM13 EXTI_IMR_MR13
+#define  EXTI_IMR_IM14 EXTI_IMR_MR14
+#define  EXTI_IMR_IM15 EXTI_IMR_MR15
+#define  EXTI_IMR_IM16 EXTI_IMR_MR16
+#define  EXTI_IMR_IM17 EXTI_IMR_MR17
+#define  EXTI_IMR_IM18 EXTI_IMR_MR18
+#define  EXTI_IMR_IM19 EXTI_IMR_MR19
+#define  EXTI_IMR_IM20 EXTI_IMR_MR20
+#define  EXTI_IMR_IM21 EXTI_IMR_MR21
+#define  EXTI_IMR_IM22 EXTI_IMR_MR22
+#define  EXTI_IMR_IM23 EXTI_IMR_MR23
+#define  EXTI_IMR_IM24 EXTI_IMR_MR24
+#define  EXTI_IMR_IM25 EXTI_IMR_MR25
+#define  EXTI_IMR_IM26 EXTI_IMR_MR26
+#define  EXTI_IMR_IM27 EXTI_IMR_MR27
+#define  EXTI_IMR_IM28 EXTI_IMR_MR28
+#define  EXTI_IMR_IM29 EXTI_IMR_MR29
+#define  EXTI_IMR_IM30 EXTI_IMR_MR30
+#define  EXTI_IMR_IM31 EXTI_IMR_MR31
+
+#define EXTI_IMR_IM_Pos            (0U)                                        
+#define EXTI_IMR_IM_Msk            (0xFFFFFFFFU << EXTI_IMR_IM_Pos)            /*!< 0xFFFFFFFF */
+#define EXTI_IMR_IM                EXTI_IMR_IM_Msk                             /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define EXTI_EMR_MR0_Pos           (0U)                                        
+#define EXTI_EMR_MR0_Msk           (0x1U << EXTI_EMR_MR0_Pos)                  /*!< 0x00000001 */
+#define EXTI_EMR_MR0               EXTI_EMR_MR0_Msk                            /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos           (1U)                                        
+#define EXTI_EMR_MR1_Msk           (0x1U << EXTI_EMR_MR1_Pos)                  /*!< 0x00000002 */
+#define EXTI_EMR_MR1               EXTI_EMR_MR1_Msk                            /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos           (2U)                                        
+#define EXTI_EMR_MR2_Msk           (0x1U << EXTI_EMR_MR2_Pos)                  /*!< 0x00000004 */
+#define EXTI_EMR_MR2               EXTI_EMR_MR2_Msk                            /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos           (3U)                                        
+#define EXTI_EMR_MR3_Msk           (0x1U << EXTI_EMR_MR3_Pos)                  /*!< 0x00000008 */
+#define EXTI_EMR_MR3               EXTI_EMR_MR3_Msk                            /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos           (4U)                                        
+#define EXTI_EMR_MR4_Msk           (0x1U << EXTI_EMR_MR4_Pos)                  /*!< 0x00000010 */
+#define EXTI_EMR_MR4               EXTI_EMR_MR4_Msk                            /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos           (5U)                                        
+#define EXTI_EMR_MR5_Msk           (0x1U << EXTI_EMR_MR5_Pos)                  /*!< 0x00000020 */
+#define EXTI_EMR_MR5               EXTI_EMR_MR5_Msk                            /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos           (6U)                                        
+#define EXTI_EMR_MR6_Msk           (0x1U << EXTI_EMR_MR6_Pos)                  /*!< 0x00000040 */
+#define EXTI_EMR_MR6               EXTI_EMR_MR6_Msk                            /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos           (7U)                                        
+#define EXTI_EMR_MR7_Msk           (0x1U << EXTI_EMR_MR7_Pos)                  /*!< 0x00000080 */
+#define EXTI_EMR_MR7               EXTI_EMR_MR7_Msk                            /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos           (8U)                                        
+#define EXTI_EMR_MR8_Msk           (0x1U << EXTI_EMR_MR8_Pos)                  /*!< 0x00000100 */
+#define EXTI_EMR_MR8               EXTI_EMR_MR8_Msk                            /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos           (9U)                                        
+#define EXTI_EMR_MR9_Msk           (0x1U << EXTI_EMR_MR9_Pos)                  /*!< 0x00000200 */
+#define EXTI_EMR_MR9               EXTI_EMR_MR9_Msk                            /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos          (10U)                                       
+#define EXTI_EMR_MR10_Msk          (0x1U << EXTI_EMR_MR10_Pos)                 /*!< 0x00000400 */
+#define EXTI_EMR_MR10              EXTI_EMR_MR10_Msk                           /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos          (11U)                                       
+#define EXTI_EMR_MR11_Msk          (0x1U << EXTI_EMR_MR11_Pos)                 /*!< 0x00000800 */
+#define EXTI_EMR_MR11              EXTI_EMR_MR11_Msk                           /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos          (12U)                                       
+#define EXTI_EMR_MR12_Msk          (0x1U << EXTI_EMR_MR12_Pos)                 /*!< 0x00001000 */
+#define EXTI_EMR_MR12              EXTI_EMR_MR12_Msk                           /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos          (13U)                                       
+#define EXTI_EMR_MR13_Msk          (0x1U << EXTI_EMR_MR13_Pos)                 /*!< 0x00002000 */
+#define EXTI_EMR_MR13              EXTI_EMR_MR13_Msk                           /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos          (14U)                                       
+#define EXTI_EMR_MR14_Msk          (0x1U << EXTI_EMR_MR14_Pos)                 /*!< 0x00004000 */
+#define EXTI_EMR_MR14              EXTI_EMR_MR14_Msk                           /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos          (15U)                                       
+#define EXTI_EMR_MR15_Msk          (0x1U << EXTI_EMR_MR15_Pos)                 /*!< 0x00008000 */
+#define EXTI_EMR_MR15              EXTI_EMR_MR15_Msk                           /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos          (16U)                                       
+#define EXTI_EMR_MR16_Msk          (0x1U << EXTI_EMR_MR16_Pos)                 /*!< 0x00010000 */
+#define EXTI_EMR_MR16              EXTI_EMR_MR16_Msk                           /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos          (17U)                                       
+#define EXTI_EMR_MR17_Msk          (0x1U << EXTI_EMR_MR17_Pos)                 /*!< 0x00020000 */
+#define EXTI_EMR_MR17              EXTI_EMR_MR17_Msk                           /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos          (18U)                                       
+#define EXTI_EMR_MR18_Msk          (0x1U << EXTI_EMR_MR18_Pos)                 /*!< 0x00040000 */
+#define EXTI_EMR_MR18              EXTI_EMR_MR18_Msk                           /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos          (19U)                                       
+#define EXTI_EMR_MR19_Msk          (0x1U << EXTI_EMR_MR19_Pos)                 /*!< 0x00080000 */
+#define EXTI_EMR_MR19              EXTI_EMR_MR19_Msk                           /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos          (20U)                                       
+#define EXTI_EMR_MR20_Msk          (0x1U << EXTI_EMR_MR20_Pos)                 /*!< 0x00100000 */
+#define EXTI_EMR_MR20              EXTI_EMR_MR20_Msk                           /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos          (21U)                                       
+#define EXTI_EMR_MR21_Msk          (0x1U << EXTI_EMR_MR21_Pos)                 /*!< 0x00200000 */
+#define EXTI_EMR_MR21              EXTI_EMR_MR21_Msk                           /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos          (22U)                                       
+#define EXTI_EMR_MR22_Msk          (0x1U << EXTI_EMR_MR22_Pos)                 /*!< 0x00400000 */
+#define EXTI_EMR_MR22              EXTI_EMR_MR22_Msk                           /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23_Pos          (23U)                                       
+#define EXTI_EMR_MR23_Msk          (0x1U << EXTI_EMR_MR23_Pos)                 /*!< 0x00800000 */
+#define EXTI_EMR_MR23              EXTI_EMR_MR23_Msk                           /*!< Event Mask on line 23 */
+#define EXTI_EMR_MR24_Pos          (24U)                                       
+#define EXTI_EMR_MR24_Msk          (0x1U << EXTI_EMR_MR24_Pos)                 /*!< 0x01000000 */
+#define EXTI_EMR_MR24              EXTI_EMR_MR24_Msk                           /*!< Event Mask on line 24 */
+#define EXTI_EMR_MR25_Pos          (25U)                                       
+#define EXTI_EMR_MR25_Msk          (0x1U << EXTI_EMR_MR25_Pos)                 /*!< 0x02000000 */
+#define EXTI_EMR_MR25              EXTI_EMR_MR25_Msk                           /*!< Event Mask on line 25 */
+#define EXTI_EMR_MR26_Pos          (26U)                                       
+#define EXTI_EMR_MR26_Msk          (0x1U << EXTI_EMR_MR26_Pos)                 /*!< 0x04000000 */
+#define EXTI_EMR_MR26              EXTI_EMR_MR26_Msk                           /*!< Event Mask on line 26 */
+#define EXTI_EMR_MR27_Pos          (27U)                                       
+#define EXTI_EMR_MR27_Msk          (0x1U << EXTI_EMR_MR27_Pos)                 /*!< 0x08000000 */
+#define EXTI_EMR_MR27              EXTI_EMR_MR27_Msk                           /*!< Event Mask on line 27 */
+#define EXTI_EMR_MR28_Pos          (28U)                                       
+#define EXTI_EMR_MR28_Msk          (0x1U << EXTI_EMR_MR28_Pos)                 /*!< 0x10000000 */
+#define EXTI_EMR_MR28              EXTI_EMR_MR28_Msk                           /*!< Event Mask on line 28 */
+#define EXTI_EMR_MR29_Pos          (29U)                                       
+#define EXTI_EMR_MR29_Msk          (0x1U << EXTI_EMR_MR29_Pos)                 /*!< 0x20000000 */
+#define EXTI_EMR_MR29              EXTI_EMR_MR29_Msk                           /*!< Event Mask on line 29 */
+#define EXTI_EMR_MR30_Pos          (30U)                                       
+#define EXTI_EMR_MR30_Msk          (0x1U << EXTI_EMR_MR30_Pos)                 /*!< 0x40000000 */
+#define EXTI_EMR_MR30              EXTI_EMR_MR30_Msk                           /*!< Event Mask on line 30 */
+#define EXTI_EMR_MR31_Pos          (31U)                                       
+#define EXTI_EMR_MR31_Msk          (0x1U << EXTI_EMR_MR31_Pos)                 /*!< 0x80000000 */
+#define EXTI_EMR_MR31              EXTI_EMR_MR31_Msk                           /*!< Event Mask on line 31 */
+
+/* References Defines */
+#define  EXTI_EMR_EM0 EXTI_EMR_MR0
+#define  EXTI_EMR_EM1 EXTI_EMR_MR1
+#define  EXTI_EMR_EM2 EXTI_EMR_MR2
+#define  EXTI_EMR_EM3 EXTI_EMR_MR3
+#define  EXTI_EMR_EM4 EXTI_EMR_MR4
+#define  EXTI_EMR_EM5 EXTI_EMR_MR5
+#define  EXTI_EMR_EM6 EXTI_EMR_MR6
+#define  EXTI_EMR_EM7 EXTI_EMR_MR7
+#define  EXTI_EMR_EM8 EXTI_EMR_MR8
+#define  EXTI_EMR_EM9 EXTI_EMR_MR9
+#define  EXTI_EMR_EM10 EXTI_EMR_MR10
+#define  EXTI_EMR_EM11 EXTI_EMR_MR11
+#define  EXTI_EMR_EM12 EXTI_EMR_MR12
+#define  EXTI_EMR_EM13 EXTI_EMR_MR13
+#define  EXTI_EMR_EM14 EXTI_EMR_MR14
+#define  EXTI_EMR_EM15 EXTI_EMR_MR15
+#define  EXTI_EMR_EM16 EXTI_EMR_MR16
+#define  EXTI_EMR_EM17 EXTI_EMR_MR17
+#define  EXTI_EMR_EM18 EXTI_EMR_MR18
+#define  EXTI_EMR_EM19 EXTI_EMR_MR19
+#define  EXTI_EMR_EM20 EXTI_EMR_MR20
+#define  EXTI_EMR_EM21 EXTI_EMR_MR21
+#define  EXTI_EMR_EM22 EXTI_EMR_MR22
+#define  EXTI_EMR_EM23 EXTI_EMR_MR23
+#define  EXTI_EMR_EM24 EXTI_EMR_MR24
+#define  EXTI_EMR_EM25 EXTI_EMR_MR25
+#define  EXTI_EMR_EM26 EXTI_EMR_MR26
+#define  EXTI_EMR_EM27 EXTI_EMR_MR27
+#define  EXTI_EMR_EM28 EXTI_EMR_MR28
+#define  EXTI_EMR_EM29 EXTI_EMR_MR29
+#define  EXTI_EMR_EM30 EXTI_EMR_MR30
+#define  EXTI_EMR_EM31 EXTI_EMR_MR31
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define EXTI_RTSR_TR0_Pos          (0U)                                        
+#define EXTI_RTSR_TR0_Msk          (0x1U << EXTI_RTSR_TR0_Pos)                 /*!< 0x00000001 */
+#define EXTI_RTSR_TR0              EXTI_RTSR_TR0_Msk                           /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos          (1U)                                        
+#define EXTI_RTSR_TR1_Msk          (0x1U << EXTI_RTSR_TR1_Pos)                 /*!< 0x00000002 */
+#define EXTI_RTSR_TR1              EXTI_RTSR_TR1_Msk                           /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos          (2U)                                        
+#define EXTI_RTSR_TR2_Msk          (0x1U << EXTI_RTSR_TR2_Pos)                 /*!< 0x00000004 */
+#define EXTI_RTSR_TR2              EXTI_RTSR_TR2_Msk                           /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos          (3U)                                        
+#define EXTI_RTSR_TR3_Msk          (0x1U << EXTI_RTSR_TR3_Pos)                 /*!< 0x00000008 */
+#define EXTI_RTSR_TR3              EXTI_RTSR_TR3_Msk                           /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos          (4U)                                        
+#define EXTI_RTSR_TR4_Msk          (0x1U << EXTI_RTSR_TR4_Pos)                 /*!< 0x00000010 */
+#define EXTI_RTSR_TR4              EXTI_RTSR_TR4_Msk                           /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos          (5U)                                        
+#define EXTI_RTSR_TR5_Msk          (0x1U << EXTI_RTSR_TR5_Pos)                 /*!< 0x00000020 */
+#define EXTI_RTSR_TR5              EXTI_RTSR_TR5_Msk                           /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos          (6U)                                        
+#define EXTI_RTSR_TR6_Msk          (0x1U << EXTI_RTSR_TR6_Pos)                 /*!< 0x00000040 */
+#define EXTI_RTSR_TR6              EXTI_RTSR_TR6_Msk                           /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos          (7U)                                        
+#define EXTI_RTSR_TR7_Msk          (0x1U << EXTI_RTSR_TR7_Pos)                 /*!< 0x00000080 */
+#define EXTI_RTSR_TR7              EXTI_RTSR_TR7_Msk                           /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos          (8U)                                        
+#define EXTI_RTSR_TR8_Msk          (0x1U << EXTI_RTSR_TR8_Pos)                 /*!< 0x00000100 */
+#define EXTI_RTSR_TR8              EXTI_RTSR_TR8_Msk                           /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos          (9U)                                        
+#define EXTI_RTSR_TR9_Msk          (0x1U << EXTI_RTSR_TR9_Pos)                 /*!< 0x00000200 */
+#define EXTI_RTSR_TR9              EXTI_RTSR_TR9_Msk                           /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos         (10U)                                       
+#define EXTI_RTSR_TR10_Msk         (0x1U << EXTI_RTSR_TR10_Pos)                /*!< 0x00000400 */
+#define EXTI_RTSR_TR10             EXTI_RTSR_TR10_Msk                          /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos         (11U)                                       
+#define EXTI_RTSR_TR11_Msk         (0x1U << EXTI_RTSR_TR11_Pos)                /*!< 0x00000800 */
+#define EXTI_RTSR_TR11             EXTI_RTSR_TR11_Msk                          /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos         (12U)                                       
+#define EXTI_RTSR_TR12_Msk         (0x1U << EXTI_RTSR_TR12_Pos)                /*!< 0x00001000 */
+#define EXTI_RTSR_TR12             EXTI_RTSR_TR12_Msk                          /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos         (13U)                                       
+#define EXTI_RTSR_TR13_Msk         (0x1U << EXTI_RTSR_TR13_Pos)                /*!< 0x00002000 */
+#define EXTI_RTSR_TR13             EXTI_RTSR_TR13_Msk                          /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos         (14U)                                       
+#define EXTI_RTSR_TR14_Msk         (0x1U << EXTI_RTSR_TR14_Pos)                /*!< 0x00004000 */
+#define EXTI_RTSR_TR14             EXTI_RTSR_TR14_Msk                          /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos         (15U)                                       
+#define EXTI_RTSR_TR15_Msk         (0x1U << EXTI_RTSR_TR15_Pos)                /*!< 0x00008000 */
+#define EXTI_RTSR_TR15             EXTI_RTSR_TR15_Msk                          /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos         (16U)                                       
+#define EXTI_RTSR_TR16_Msk         (0x1U << EXTI_RTSR_TR16_Pos)                /*!< 0x00010000 */
+#define EXTI_RTSR_TR16             EXTI_RTSR_TR16_Msk                          /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos         (17U)                                       
+#define EXTI_RTSR_TR17_Msk         (0x1U << EXTI_RTSR_TR17_Pos)                /*!< 0x00020000 */
+#define EXTI_RTSR_TR17             EXTI_RTSR_TR17_Msk                          /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos         (18U)                                       
+#define EXTI_RTSR_TR18_Msk         (0x1U << EXTI_RTSR_TR18_Pos)                /*!< 0x00040000 */
+#define EXTI_RTSR_TR18             EXTI_RTSR_TR18_Msk                          /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos         (19U)                                       
+#define EXTI_RTSR_TR19_Msk         (0x1U << EXTI_RTSR_TR19_Pos)                /*!< 0x00080000 */
+#define EXTI_RTSR_TR19             EXTI_RTSR_TR19_Msk                          /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos         (20U)                                       
+#define EXTI_RTSR_TR20_Msk         (0x1U << EXTI_RTSR_TR20_Pos)                /*!< 0x00100000 */
+#define EXTI_RTSR_TR20             EXTI_RTSR_TR20_Msk                          /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos         (21U)                                       
+#define EXTI_RTSR_TR21_Msk         (0x1U << EXTI_RTSR_TR21_Pos)                /*!< 0x00200000 */
+#define EXTI_RTSR_TR21             EXTI_RTSR_TR21_Msk                          /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos         (22U)                                       
+#define EXTI_RTSR_TR22_Msk         (0x1U << EXTI_RTSR_TR22_Pos)                /*!< 0x00400000 */
+#define EXTI_RTSR_TR22             EXTI_RTSR_TR22_Msk                          /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR_TR29_Pos         (29U)                                       
+#define EXTI_RTSR_TR29_Msk         (0x1U << EXTI_RTSR_TR29_Pos)                /*!< 0x20000000 */
+#define EXTI_RTSR_TR29             EXTI_RTSR_TR29_Msk                          /*!< Rising trigger event configuration bit of line 29 */
+#define EXTI_RTSR_TR30_Pos         (30U)                                       
+#define EXTI_RTSR_TR30_Msk         (0x1U << EXTI_RTSR_TR30_Pos)                /*!< 0x40000000 */
+#define EXTI_RTSR_TR30             EXTI_RTSR_TR30_Msk                          /*!< Rising trigger event configuration bit of line 30 */
+#define EXTI_RTSR_TR31_Pos         (31U)                                       
+#define EXTI_RTSR_TR31_Msk         (0x1U << EXTI_RTSR_TR31_Pos)                /*!< 0x80000000 */
+#define EXTI_RTSR_TR31             EXTI_RTSR_TR31_Msk                          /*!< Rising trigger event configuration bit of line 31 */
+
+/* References Defines */
+#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
+#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
+#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
+#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
+#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
+#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
+#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
+#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
+#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
+#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
+#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
+#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
+#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
+#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
+#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
+#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
+#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
+#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
+#define EXTI_RTSR_RT20 EXTI_RTSR_TR20
+#define EXTI_RTSR_RT21 EXTI_RTSR_TR21
+#define EXTI_RTSR_RT22 EXTI_RTSR_TR22
+#define EXTI_RTSR_RT29 EXTI_RTSR_TR29
+#define EXTI_RTSR_RT30 EXTI_RTSR_TR30
+#define EXTI_RTSR_RT31 EXTI_RTSR_TR31
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define EXTI_FTSR_TR0_Pos          (0U)                                        
+#define EXTI_FTSR_TR0_Msk          (0x1U << EXTI_FTSR_TR0_Pos)                 /*!< 0x00000001 */
+#define EXTI_FTSR_TR0              EXTI_FTSR_TR0_Msk                           /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos          (1U)                                        
+#define EXTI_FTSR_TR1_Msk          (0x1U << EXTI_FTSR_TR1_Pos)                 /*!< 0x00000002 */
+#define EXTI_FTSR_TR1              EXTI_FTSR_TR1_Msk                           /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos          (2U)                                        
+#define EXTI_FTSR_TR2_Msk          (0x1U << EXTI_FTSR_TR2_Pos)                 /*!< 0x00000004 */
+#define EXTI_FTSR_TR2              EXTI_FTSR_TR2_Msk                           /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos          (3U)                                        
+#define EXTI_FTSR_TR3_Msk          (0x1U << EXTI_FTSR_TR3_Pos)                 /*!< 0x00000008 */
+#define EXTI_FTSR_TR3              EXTI_FTSR_TR3_Msk                           /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos          (4U)                                        
+#define EXTI_FTSR_TR4_Msk          (0x1U << EXTI_FTSR_TR4_Pos)                 /*!< 0x00000010 */
+#define EXTI_FTSR_TR4              EXTI_FTSR_TR4_Msk                           /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos          (5U)                                        
+#define EXTI_FTSR_TR5_Msk          (0x1U << EXTI_FTSR_TR5_Pos)                 /*!< 0x00000020 */
+#define EXTI_FTSR_TR5              EXTI_FTSR_TR5_Msk                           /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos          (6U)                                        
+#define EXTI_FTSR_TR6_Msk          (0x1U << EXTI_FTSR_TR6_Pos)                 /*!< 0x00000040 */
+#define EXTI_FTSR_TR6              EXTI_FTSR_TR6_Msk                           /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos          (7U)                                        
+#define EXTI_FTSR_TR7_Msk          (0x1U << EXTI_FTSR_TR7_Pos)                 /*!< 0x00000080 */
+#define EXTI_FTSR_TR7              EXTI_FTSR_TR7_Msk                           /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos          (8U)                                        
+#define EXTI_FTSR_TR8_Msk          (0x1U << EXTI_FTSR_TR8_Pos)                 /*!< 0x00000100 */
+#define EXTI_FTSR_TR8              EXTI_FTSR_TR8_Msk                           /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos          (9U)                                        
+#define EXTI_FTSR_TR9_Msk          (0x1U << EXTI_FTSR_TR9_Pos)                 /*!< 0x00000200 */
+#define EXTI_FTSR_TR9              EXTI_FTSR_TR9_Msk                           /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos         (10U)                                       
+#define EXTI_FTSR_TR10_Msk         (0x1U << EXTI_FTSR_TR10_Pos)                /*!< 0x00000400 */
+#define EXTI_FTSR_TR10             EXTI_FTSR_TR10_Msk                          /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos         (11U)                                       
+#define EXTI_FTSR_TR11_Msk         (0x1U << EXTI_FTSR_TR11_Pos)                /*!< 0x00000800 */
+#define EXTI_FTSR_TR11             EXTI_FTSR_TR11_Msk                          /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos         (12U)                                       
+#define EXTI_FTSR_TR12_Msk         (0x1U << EXTI_FTSR_TR12_Pos)                /*!< 0x00001000 */
+#define EXTI_FTSR_TR12             EXTI_FTSR_TR12_Msk                          /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos         (13U)                                       
+#define EXTI_FTSR_TR13_Msk         (0x1U << EXTI_FTSR_TR13_Pos)                /*!< 0x00002000 */
+#define EXTI_FTSR_TR13             EXTI_FTSR_TR13_Msk                          /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos         (14U)                                       
+#define EXTI_FTSR_TR14_Msk         (0x1U << EXTI_FTSR_TR14_Pos)                /*!< 0x00004000 */
+#define EXTI_FTSR_TR14             EXTI_FTSR_TR14_Msk                          /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos         (15U)                                       
+#define EXTI_FTSR_TR15_Msk         (0x1U << EXTI_FTSR_TR15_Pos)                /*!< 0x00008000 */
+#define EXTI_FTSR_TR15             EXTI_FTSR_TR15_Msk                          /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos         (16U)                                       
+#define EXTI_FTSR_TR16_Msk         (0x1U << EXTI_FTSR_TR16_Pos)                /*!< 0x00010000 */
+#define EXTI_FTSR_TR16             EXTI_FTSR_TR16_Msk                          /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos         (17U)                                       
+#define EXTI_FTSR_TR17_Msk         (0x1U << EXTI_FTSR_TR17_Pos)                /*!< 0x00020000 */
+#define EXTI_FTSR_TR17             EXTI_FTSR_TR17_Msk                          /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos         (18U)                                       
+#define EXTI_FTSR_TR18_Msk         (0x1U << EXTI_FTSR_TR18_Pos)                /*!< 0x00040000 */
+#define EXTI_FTSR_TR18             EXTI_FTSR_TR18_Msk                          /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos         (19U)                                       
+#define EXTI_FTSR_TR19_Msk         (0x1U << EXTI_FTSR_TR19_Pos)                /*!< 0x00080000 */
+#define EXTI_FTSR_TR19             EXTI_FTSR_TR19_Msk                          /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos         (20U)                                       
+#define EXTI_FTSR_TR20_Msk         (0x1U << EXTI_FTSR_TR20_Pos)                /*!< 0x00100000 */
+#define EXTI_FTSR_TR20             EXTI_FTSR_TR20_Msk                          /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos         (21U)                                       
+#define EXTI_FTSR_TR21_Msk         (0x1U << EXTI_FTSR_TR21_Pos)                /*!< 0x00200000 */
+#define EXTI_FTSR_TR21             EXTI_FTSR_TR21_Msk                          /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos         (22U)                                       
+#define EXTI_FTSR_TR22_Msk         (0x1U << EXTI_FTSR_TR22_Pos)                /*!< 0x00400000 */
+#define EXTI_FTSR_TR22             EXTI_FTSR_TR22_Msk                          /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR_TR29_Pos         (29U)                                       
+#define EXTI_FTSR_TR29_Msk         (0x1U << EXTI_FTSR_TR29_Pos)                /*!< 0x20000000 */
+#define EXTI_FTSR_TR29             EXTI_FTSR_TR29_Msk                          /*!< Falling trigger event configuration bit of line 29 */
+#define EXTI_FTSR_TR30_Pos         (30U)                                       
+#define EXTI_FTSR_TR30_Msk         (0x1U << EXTI_FTSR_TR30_Pos)                /*!< 0x40000000 */
+#define EXTI_FTSR_TR30             EXTI_FTSR_TR30_Msk                          /*!< Falling trigger event configuration bit of line 30 */
+#define EXTI_FTSR_TR31_Pos         (31U)                                       
+#define EXTI_FTSR_TR31_Msk         (0x1U << EXTI_FTSR_TR31_Pos)                /*!< 0x80000000 */
+#define EXTI_FTSR_TR31             EXTI_FTSR_TR31_Msk                          /*!< Falling trigger event configuration bit of line 31 */
+
+/* References Defines */
+#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
+#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
+#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
+#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
+#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
+#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
+#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
+#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
+#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
+#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
+#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
+#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
+#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
+#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
+#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
+#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
+#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
+#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
+#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
+#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
+#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
+#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
+#define  EXTI_FTSR_FT29 EXTI_FTSR_TR29
+#define  EXTI_FTSR_FT30 EXTI_FTSR_TR30
+#define  EXTI_FTSR_FT31 EXTI_FTSR_TR31
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define EXTI_SWIER_SWIER0_Pos      (0U)                                        
+#define EXTI_SWIER_SWIER0_Msk      (0x1U << EXTI_SWIER_SWIER0_Pos)             /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0          EXTI_SWIER_SWIER0_Msk                       /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos      (1U)                                        
+#define EXTI_SWIER_SWIER1_Msk      (0x1U << EXTI_SWIER_SWIER1_Pos)             /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1          EXTI_SWIER_SWIER1_Msk                       /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos      (2U)                                        
+#define EXTI_SWIER_SWIER2_Msk      (0x1U << EXTI_SWIER_SWIER2_Pos)             /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2          EXTI_SWIER_SWIER2_Msk                       /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos      (3U)                                        
+#define EXTI_SWIER_SWIER3_Msk      (0x1U << EXTI_SWIER_SWIER3_Pos)             /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3          EXTI_SWIER_SWIER3_Msk                       /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos      (4U)                                        
+#define EXTI_SWIER_SWIER4_Msk      (0x1U << EXTI_SWIER_SWIER4_Pos)             /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4          EXTI_SWIER_SWIER4_Msk                       /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos      (5U)                                        
+#define EXTI_SWIER_SWIER5_Msk      (0x1U << EXTI_SWIER_SWIER5_Pos)             /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5          EXTI_SWIER_SWIER5_Msk                       /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos      (6U)                                        
+#define EXTI_SWIER_SWIER6_Msk      (0x1U << EXTI_SWIER_SWIER6_Pos)             /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6          EXTI_SWIER_SWIER6_Msk                       /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos      (7U)                                        
+#define EXTI_SWIER_SWIER7_Msk      (0x1U << EXTI_SWIER_SWIER7_Pos)             /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7          EXTI_SWIER_SWIER7_Msk                       /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos      (8U)                                        
+#define EXTI_SWIER_SWIER8_Msk      (0x1U << EXTI_SWIER_SWIER8_Pos)             /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8          EXTI_SWIER_SWIER8_Msk                       /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos      (9U)                                        
+#define EXTI_SWIER_SWIER9_Msk      (0x1U << EXTI_SWIER_SWIER9_Pos)             /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9          EXTI_SWIER_SWIER9_Msk                       /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos     (10U)                                       
+#define EXTI_SWIER_SWIER10_Msk     (0x1U << EXTI_SWIER_SWIER10_Pos)            /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10         EXTI_SWIER_SWIER10_Msk                      /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos     (11U)                                       
+#define EXTI_SWIER_SWIER11_Msk     (0x1U << EXTI_SWIER_SWIER11_Pos)            /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11         EXTI_SWIER_SWIER11_Msk                      /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos     (12U)                                       
+#define EXTI_SWIER_SWIER12_Msk     (0x1U << EXTI_SWIER_SWIER12_Pos)            /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12         EXTI_SWIER_SWIER12_Msk                      /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos     (13U)                                       
+#define EXTI_SWIER_SWIER13_Msk     (0x1U << EXTI_SWIER_SWIER13_Pos)            /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13         EXTI_SWIER_SWIER13_Msk                      /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos     (14U)                                       
+#define EXTI_SWIER_SWIER14_Msk     (0x1U << EXTI_SWIER_SWIER14_Pos)            /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14         EXTI_SWIER_SWIER14_Msk                      /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos     (15U)                                       
+#define EXTI_SWIER_SWIER15_Msk     (0x1U << EXTI_SWIER_SWIER15_Pos)            /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15         EXTI_SWIER_SWIER15_Msk                      /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos     (16U)                                       
+#define EXTI_SWIER_SWIER16_Msk     (0x1U << EXTI_SWIER_SWIER16_Pos)            /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16         EXTI_SWIER_SWIER16_Msk                      /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos     (17U)                                       
+#define EXTI_SWIER_SWIER17_Msk     (0x1U << EXTI_SWIER_SWIER17_Pos)            /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17         EXTI_SWIER_SWIER17_Msk                      /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos     (18U)                                       
+#define EXTI_SWIER_SWIER18_Msk     (0x1U << EXTI_SWIER_SWIER18_Pos)            /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18         EXTI_SWIER_SWIER18_Msk                      /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos     (19U)                                       
+#define EXTI_SWIER_SWIER19_Msk     (0x1U << EXTI_SWIER_SWIER19_Pos)            /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19         EXTI_SWIER_SWIER19_Msk                      /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos     (20U)                                       
+#define EXTI_SWIER_SWIER20_Msk     (0x1U << EXTI_SWIER_SWIER20_Pos)            /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20         EXTI_SWIER_SWIER20_Msk                      /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos     (21U)                                       
+#define EXTI_SWIER_SWIER21_Msk     (0x1U << EXTI_SWIER_SWIER21_Pos)            /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21         EXTI_SWIER_SWIER21_Msk                      /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos     (22U)                                       
+#define EXTI_SWIER_SWIER22_Msk     (0x1U << EXTI_SWIER_SWIER22_Pos)            /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22         EXTI_SWIER_SWIER22_Msk                      /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER_SWIER29_Pos     (29U)                                       
+#define EXTI_SWIER_SWIER29_Msk     (0x1U << EXTI_SWIER_SWIER29_Pos)            /*!< 0x20000000 */
+#define EXTI_SWIER_SWIER29         EXTI_SWIER_SWIER29_Msk                      /*!< Software Interrupt on line 29 */
+#define EXTI_SWIER_SWIER30_Pos     (30U)                                       
+#define EXTI_SWIER_SWIER30_Msk     (0x1U << EXTI_SWIER_SWIER30_Pos)            /*!< 0x40000000 */
+#define EXTI_SWIER_SWIER30         EXTI_SWIER_SWIER30_Msk                      /*!< Software Interrupt on line 30 */
+#define EXTI_SWIER_SWIER31_Pos     (31U)                                       
+#define EXTI_SWIER_SWIER31_Msk     (0x1U << EXTI_SWIER_SWIER31_Pos)            /*!< 0x80000000 */
+#define EXTI_SWIER_SWIER31         EXTI_SWIER_SWIER31_Msk                      /*!< Software Interrupt on line 31 */
+
+/* References Defines */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
+#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
+#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
+#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
+#define  EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
+#define  EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
+#define  EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define EXTI_PR_PR0_Pos            (0U)                                        
+#define EXTI_PR_PR0_Msk            (0x1U << EXTI_PR_PR0_Pos)                   /*!< 0x00000001 */
+#define EXTI_PR_PR0                EXTI_PR_PR0_Msk                             /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos            (1U)                                        
+#define EXTI_PR_PR1_Msk            (0x1U << EXTI_PR_PR1_Pos)                   /*!< 0x00000002 */
+#define EXTI_PR_PR1                EXTI_PR_PR1_Msk                             /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos            (2U)                                        
+#define EXTI_PR_PR2_Msk            (0x1U << EXTI_PR_PR2_Pos)                   /*!< 0x00000004 */
+#define EXTI_PR_PR2                EXTI_PR_PR2_Msk                             /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos            (3U)                                        
+#define EXTI_PR_PR3_Msk            (0x1U << EXTI_PR_PR3_Pos)                   /*!< 0x00000008 */
+#define EXTI_PR_PR3                EXTI_PR_PR3_Msk                             /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos            (4U)                                        
+#define EXTI_PR_PR4_Msk            (0x1U << EXTI_PR_PR4_Pos)                   /*!< 0x00000010 */
+#define EXTI_PR_PR4                EXTI_PR_PR4_Msk                             /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos            (5U)                                        
+#define EXTI_PR_PR5_Msk            (0x1U << EXTI_PR_PR5_Pos)                   /*!< 0x00000020 */
+#define EXTI_PR_PR5                EXTI_PR_PR5_Msk                             /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos            (6U)                                        
+#define EXTI_PR_PR6_Msk            (0x1U << EXTI_PR_PR6_Pos)                   /*!< 0x00000040 */
+#define EXTI_PR_PR6                EXTI_PR_PR6_Msk                             /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos            (7U)                                        
+#define EXTI_PR_PR7_Msk            (0x1U << EXTI_PR_PR7_Pos)                   /*!< 0x00000080 */
+#define EXTI_PR_PR7                EXTI_PR_PR7_Msk                             /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos            (8U)                                        
+#define EXTI_PR_PR8_Msk            (0x1U << EXTI_PR_PR8_Pos)                   /*!< 0x00000100 */
+#define EXTI_PR_PR8                EXTI_PR_PR8_Msk                             /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos            (9U)                                        
+#define EXTI_PR_PR9_Msk            (0x1U << EXTI_PR_PR9_Pos)                   /*!< 0x00000200 */
+#define EXTI_PR_PR9                EXTI_PR_PR9_Msk                             /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos           (10U)                                       
+#define EXTI_PR_PR10_Msk           (0x1U << EXTI_PR_PR10_Pos)                  /*!< 0x00000400 */
+#define EXTI_PR_PR10               EXTI_PR_PR10_Msk                            /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos           (11U)                                       
+#define EXTI_PR_PR11_Msk           (0x1U << EXTI_PR_PR11_Pos)                  /*!< 0x00000800 */
+#define EXTI_PR_PR11               EXTI_PR_PR11_Msk                            /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos           (12U)                                       
+#define EXTI_PR_PR12_Msk           (0x1U << EXTI_PR_PR12_Pos)                  /*!< 0x00001000 */
+#define EXTI_PR_PR12               EXTI_PR_PR12_Msk                            /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos           (13U)                                       
+#define EXTI_PR_PR13_Msk           (0x1U << EXTI_PR_PR13_Pos)                  /*!< 0x00002000 */
+#define EXTI_PR_PR13               EXTI_PR_PR13_Msk                            /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos           (14U)                                       
+#define EXTI_PR_PR14_Msk           (0x1U << EXTI_PR_PR14_Pos)                  /*!< 0x00004000 */
+#define EXTI_PR_PR14               EXTI_PR_PR14_Msk                            /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos           (15U)                                       
+#define EXTI_PR_PR15_Msk           (0x1U << EXTI_PR_PR15_Pos)                  /*!< 0x00008000 */
+#define EXTI_PR_PR15               EXTI_PR_PR15_Msk                            /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos           (16U)                                       
+#define EXTI_PR_PR16_Msk           (0x1U << EXTI_PR_PR16_Pos)                  /*!< 0x00010000 */
+#define EXTI_PR_PR16               EXTI_PR_PR16_Msk                            /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos           (17U)                                       
+#define EXTI_PR_PR17_Msk           (0x1U << EXTI_PR_PR17_Pos)                  /*!< 0x00020000 */
+#define EXTI_PR_PR17               EXTI_PR_PR17_Msk                            /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos           (18U)                                       
+#define EXTI_PR_PR18_Msk           (0x1U << EXTI_PR_PR18_Pos)                  /*!< 0x00040000 */
+#define EXTI_PR_PR18               EXTI_PR_PR18_Msk                            /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos           (19U)                                       
+#define EXTI_PR_PR19_Msk           (0x1U << EXTI_PR_PR19_Pos)                  /*!< 0x00080000 */
+#define EXTI_PR_PR19               EXTI_PR_PR19_Msk                            /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos           (20U)                                       
+#define EXTI_PR_PR20_Msk           (0x1U << EXTI_PR_PR20_Pos)                  /*!< 0x00100000 */
+#define EXTI_PR_PR20               EXTI_PR_PR20_Msk                            /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos           (21U)                                       
+#define EXTI_PR_PR21_Msk           (0x1U << EXTI_PR_PR21_Pos)                  /*!< 0x00200000 */
+#define EXTI_PR_PR21               EXTI_PR_PR21_Msk                            /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos           (22U)                                       
+#define EXTI_PR_PR22_Msk           (0x1U << EXTI_PR_PR22_Pos)                  /*!< 0x00400000 */
+#define EXTI_PR_PR22               EXTI_PR_PR22_Msk                            /*!< Pending bit for line 22 */
+#define EXTI_PR_PR29_Pos           (29U)                                       
+#define EXTI_PR_PR29_Msk           (0x1U << EXTI_PR_PR29_Pos)                  /*!< 0x20000000 */
+#define EXTI_PR_PR29               EXTI_PR_PR29_Msk                            /*!< Pending bit for line 29 */
+#define EXTI_PR_PR30_Pos           (30U)                                       
+#define EXTI_PR_PR30_Msk           (0x1U << EXTI_PR_PR30_Pos)                  /*!< 0x40000000 */
+#define EXTI_PR_PR30               EXTI_PR_PR30_Msk                            /*!< Pending bit for line 30 */
+#define EXTI_PR_PR31_Pos           (31U)                                       
+#define EXTI_PR_PR31_Msk           (0x1U << EXTI_PR_PR31_Pos)                  /*!< 0x80000000 */
+#define EXTI_PR_PR31               EXTI_PR_PR31_Msk                            /*!< Pending bit for line 31 */
+
+/* References Defines */
+#define EXTI_PR_PIF0 EXTI_PR_PR0
+#define EXTI_PR_PIF1 EXTI_PR_PR1
+#define EXTI_PR_PIF2 EXTI_PR_PR2
+#define EXTI_PR_PIF3 EXTI_PR_PR3
+#define EXTI_PR_PIF4 EXTI_PR_PR4
+#define EXTI_PR_PIF5 EXTI_PR_PR5
+#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF7 EXTI_PR_PR7
+#define EXTI_PR_PIF8 EXTI_PR_PR8
+#define EXTI_PR_PIF9 EXTI_PR_PR9
+#define EXTI_PR_PIF10 EXTI_PR_PR10
+#define EXTI_PR_PIF11 EXTI_PR_PR11
+#define EXTI_PR_PIF12 EXTI_PR_PR12
+#define EXTI_PR_PIF13 EXTI_PR_PR13
+#define EXTI_PR_PIF14 EXTI_PR_PR14
+#define EXTI_PR_PIF15 EXTI_PR_PR15
+#define EXTI_PR_PIF16 EXTI_PR_PR16
+#define EXTI_PR_PIF17 EXTI_PR_PR17
+#define  EXTI_PR_PIF18 EXTI_PR_PR18
+#define  EXTI_PR_PIF19 EXTI_PR_PR19
+#define  EXTI_PR_PIF20 EXTI_PR_PR20
+#define  EXTI_PR_PIF21 EXTI_PR_PR21
+#define  EXTI_PR_PIF22 EXTI_PR_PR22
+#define  EXTI_PR_PIF29 EXTI_PR_PR29
+#define  EXTI_PR_PIF30 EXTI_PR_PR30
+#define  EXTI_PR_PIF31 EXTI_PR_PR31
+
+#define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */
+
+/*******************  Bit definition for EXTI_IMR2 register  ******************/
+#define EXTI_IMR2_MR32_Pos         (0U)                                        
+#define EXTI_IMR2_MR32_Msk         (0x1U << EXTI_IMR2_MR32_Pos)                /*!< 0x00000001 */
+#define EXTI_IMR2_MR32             EXTI_IMR2_MR32_Msk                          /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_MR33_Pos         (1U)                                        
+#define EXTI_IMR2_MR33_Msk         (0x1U << EXTI_IMR2_MR33_Pos)                /*!< 0x00000002 */
+#define EXTI_IMR2_MR33             EXTI_IMR2_MR33_Msk                          /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_MR34_Pos         (2U)                                        
+#define EXTI_IMR2_MR34_Msk         (0x1U << EXTI_IMR2_MR34_Pos)                /*!< 0x00000004 */
+#define EXTI_IMR2_MR34             EXTI_IMR2_MR34_Msk                          /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_MR35_Pos         (3U)                                        
+#define EXTI_IMR2_MR35_Msk         (0x1U << EXTI_IMR2_MR35_Pos)                /*!< 0x00000008 */
+#define EXTI_IMR2_MR35             EXTI_IMR2_MR35_Msk                          /*!< Interrupt Mask on line 35 */
+
+/* References Defines */
+#define  EXTI_IMR2_IM32 EXTI_IMR2_MR32
+#define  EXTI_IMR2_IM33 EXTI_IMR2_MR33
+#define  EXTI_IMR2_IM34 EXTI_IMR2_MR34
+#define  EXTI_IMR2_IM35 EXTI_IMR2_MR35
+
+#define EXTI_IMR2_IM_Pos           (0U)                                        
+#define EXTI_IMR2_IM_Msk           (0xFU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000F */
+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            
+
+/*******************  Bit definition for EXTI_EMR2 ****************************/
+#define EXTI_EMR2_MR32_Pos         (0U)                                        
+#define EXTI_EMR2_MR32_Msk         (0x1U << EXTI_EMR2_MR32_Pos)                /*!< 0x00000001 */
+#define EXTI_EMR2_MR32             EXTI_EMR2_MR32_Msk                          /*!< Event Mask on line 32 */
+#define EXTI_EMR2_MR33_Pos         (1U)                                        
+#define EXTI_EMR2_MR33_Msk         (0x1U << EXTI_EMR2_MR33_Pos)                /*!< 0x00000002 */
+#define EXTI_EMR2_MR33             EXTI_EMR2_MR33_Msk                          /*!< Event Mask on line 33 */
+#define EXTI_EMR2_MR34_Pos         (2U)                                        
+#define EXTI_EMR2_MR34_Msk         (0x1U << EXTI_EMR2_MR34_Pos)                /*!< 0x00000004 */
+#define EXTI_EMR2_MR34             EXTI_EMR2_MR34_Msk                          /*!< Event Mask on line 34 */
+#define EXTI_EMR2_MR35_Pos         (3U)                                        
+#define EXTI_EMR2_MR35_Msk         (0x1U << EXTI_EMR2_MR35_Pos)                /*!< 0x00000008 */
+#define EXTI_EMR2_MR35             EXTI_EMR2_MR35_Msk                          /*!< Event Mask on line 34 */
+
+/* References Defines */
+#define  EXTI_EMR2_EM32 EXTI_EMR2_MR32
+#define  EXTI_EMR2_EM33 EXTI_EMR2_MR33
+#define  EXTI_EMR2_EM34 EXTI_EMR2_MR34
+#define  EXTI_EMR2_EM35 EXTI_EMR2_MR35
+
+/******************  Bit definition for EXTI_RTSR2 register ********************/
+#define EXTI_RTSR2_TR32_Pos        (0U)                                        
+#define EXTI_RTSR2_TR32_Msk        (0x1U << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */
+#define EXTI_RTSR2_TR32            EXTI_RTSR2_TR32_Msk                         /*!< Rising trigger event configuration bit of line 32 */
+#define EXTI_RTSR2_TR33_Pos        (1U)                                        
+#define EXTI_RTSR2_TR33_Msk        (0x1U << EXTI_RTSR2_TR33_Pos)               /*!< 0x00000002 */
+#define EXTI_RTSR2_TR33            EXTI_RTSR2_TR33_Msk                         /*!< Rising trigger event configuration bit of line 33 */
+
+/* References Defines */
+#define  EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
+#define  EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
+
+/******************  Bit definition for EXTI_FTSR2 register  ******************/
+#define EXTI_FTSR2_TR32_Pos        (0U)                                        
+#define EXTI_FTSR2_TR32_Msk        (0x1U << EXTI_FTSR2_TR32_Pos)               /*!< 0x00000001 */
+#define EXTI_FTSR2_TR32            EXTI_FTSR2_TR32_Msk                         /*!< Falling trigger event configuration bit of line 32 */
+#define EXTI_FTSR2_TR33_Pos        (1U)                                        
+#define EXTI_FTSR2_TR33_Msk        (0x1U << EXTI_FTSR2_TR33_Pos)               /*!< 0x00000002 */
+#define EXTI_FTSR2_TR33            EXTI_FTSR2_TR33_Msk                         /*!< Falling trigger event configuration bit of line 33 */
+
+/* References Defines */
+#define  EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
+#define  EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
+
+/******************  Bit definition for EXTI_SWIER2 register  *****************/
+#define EXTI_SWIER2_SWIER32_Pos    (0U)                                        
+#define EXTI_SWIER2_SWIER32_Msk    (0x1U << EXTI_SWIER2_SWIER32_Pos)           /*!< 0x00000001 */
+#define EXTI_SWIER2_SWIER32        EXTI_SWIER2_SWIER32_Msk                     /*!< Software Interrupt on line 32 */
+#define EXTI_SWIER2_SWIER33_Pos    (1U)                                        
+#define EXTI_SWIER2_SWIER33_Msk    (0x1U << EXTI_SWIER2_SWIER33_Pos)           /*!< 0x00000002 */
+#define EXTI_SWIER2_SWIER33        EXTI_SWIER2_SWIER33_Msk                     /*!< Software Interrupt on line 33 */
+
+/* References Defines */
+#define  EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
+#define  EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
+
+/*******************  Bit definition for EXTI_PR2 register  *******************/
+#define EXTI_PR2_PR32_Pos          (0U)                                        
+#define EXTI_PR2_PR32_Msk          (0x1U << EXTI_PR2_PR32_Pos)                 /*!< 0x00000001 */
+#define EXTI_PR2_PR32              EXTI_PR2_PR32_Msk                           /*!< Pending bit for line 32 */
+#define EXTI_PR2_PR33_Pos          (1U)                                        
+#define EXTI_PR2_PR33_Msk          (0x1U << EXTI_PR2_PR33_Pos)                 /*!< 0x00000002 */
+#define EXTI_PR2_PR33              EXTI_PR2_PR33_Msk                           /*!< Pending bit for line 33 */
+
+/* References Defines */
+#define  EXTI_PR2_PIF32 EXTI_PR2_PR32
+#define  EXTI_PR2_PIF33 EXTI_PR2_PR33
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define FLASH_ACR_LATENCY_Pos                (0U)                              
+#define FLASH_ACR_LATENCY_Msk                (0x7U << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0                  (0x1U << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY_1                  (0x2U << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000002 */
+#define FLASH_ACR_LATENCY_2                  (0x4U << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000004 */
+
+#define FLASH_ACR_HLFCYA_Pos                 (3U)                              
+#define FLASH_ACR_HLFCYA_Msk                 (0x1U << FLASH_ACR_HLFCYA_Pos)    /*!< 0x00000008 */
+#define FLASH_ACR_HLFCYA                     FLASH_ACR_HLFCYA_Msk              /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE_Pos                 (4U)                              
+#define FLASH_ACR_PRFTBE_Msk                 (0x1U << FLASH_ACR_PRFTBE_Pos)    /*!< 0x00000010 */
+#define FLASH_ACR_PRFTBE                     FLASH_ACR_PRFTBE_Msk              /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS_Pos                 (5U)                              
+#define FLASH_ACR_PRFTBS_Msk                 (0x1U << FLASH_ACR_PRFTBS_Pos)    /*!< 0x00000020 */
+#define FLASH_ACR_PRFTBS                     FLASH_ACR_PRFTBS_Msk              /*!< Prefetch Buffer Status */
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define FLASH_KEYR_FKEYR_Pos                 (0U)                              
+#define FLASH_KEYR_FKEYR_Msk                 (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_KEYR_FKEYR                     FLASH_KEYR_FKEYR_Msk              /*!< FPEC Key */
+
+#define RDP_KEY_Pos    (0U)                                                    
+#define RDP_KEY_Msk    (0xA5U << RDP_KEY_Pos)                                  /*!< 0x000000A5 */
+#define RDP_KEY        RDP_KEY_Msk                                             /*!< RDP Key */
+#define FLASH_KEY1_Pos                       (0U)                              
+#define FLASH_KEY1_Msk                       (0x45670123U << FLASH_KEY1_Pos)   /*!< 0x45670123 */
+#define FLASH_KEY1                           FLASH_KEY1_Msk                    /*!< FPEC Key1 */
+#define FLASH_KEY2_Pos                       (0U)                              
+#define FLASH_KEY2_Msk                       (0xCDEF89ABU << FLASH_KEY2_Pos)   /*!< 0xCDEF89AB */
+#define FLASH_KEY2                           FLASH_KEY2_Msk                    /*!< FPEC Key2 */
+
+/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
+#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option Byte Key */
+
+#define  FLASH_OPTKEY1                       FLASH_KEY1                    /*!< Option Byte Key1 */
+#define  FLASH_OPTKEY2                       FLASH_KEY2                    /*!< Option Byte Key2 */
+
+/******************  Bit definition for FLASH_SR register  *******************/
+#define FLASH_SR_BSY_Pos                     (0U)                              
+#define FLASH_SR_BSY_Msk                     (0x1U << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
+#define FLASH_SR_PGERR_Pos                   (2U)                              
+#define FLASH_SR_PGERR_Msk                   (0x1U << FLASH_SR_PGERR_Pos)      /*!< 0x00000004 */
+#define FLASH_SR_PGERR                       FLASH_SR_PGERR_Msk                /*!< Programming Error */
+#define FLASH_SR_WRPERR_Pos                  (4U)                              
+#define FLASH_SR_WRPERR_Msk                  (0x1U << FLASH_SR_WRPERR_Pos)     /*!< 0x00000010 */
+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write Protection Error */
+#define FLASH_SR_EOP_Pos                     (5U)                              
+#define FLASH_SR_EOP_Msk                     (0x1U << FLASH_SR_EOP_Pos)        /*!< 0x00000020 */
+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End of operation */
+
+/*******************  Bit definition for FLASH_CR register  *******************/
+#define FLASH_CR_PG_Pos                      (0U)                              
+#define FLASH_CR_PG_Msk                      (0x1U << FLASH_CR_PG_Pos)         /*!< 0x00000001 */
+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Programming */
+#define FLASH_CR_PER_Pos                     (1U)                              
+#define FLASH_CR_PER_Msk                     (0x1U << FLASH_CR_PER_Pos)        /*!< 0x00000002 */
+#define FLASH_CR_PER                         FLASH_CR_PER_Msk                  /*!< Page Erase */
+#define FLASH_CR_MER_Pos                     (2U)                              
+#define FLASH_CR_MER_Msk                     (0x1U << FLASH_CR_MER_Pos)        /*!< 0x00000004 */
+#define FLASH_CR_MER                         FLASH_CR_MER_Msk                  /*!< Mass Erase */
+#define FLASH_CR_OPTPG_Pos                   (4U)                              
+#define FLASH_CR_OPTPG_Msk                   (0x1U << FLASH_CR_OPTPG_Pos)      /*!< 0x00000010 */
+#define FLASH_CR_OPTPG                       FLASH_CR_OPTPG_Msk                /*!< Option Byte Programming */
+#define FLASH_CR_OPTER_Pos                   (5U)                              
+#define FLASH_CR_OPTER_Msk                   (0x1U << FLASH_CR_OPTER_Pos)      /*!< 0x00000020 */
+#define FLASH_CR_OPTER                       FLASH_CR_OPTER_Msk                /*!< Option Byte Erase */
+#define FLASH_CR_STRT_Pos                    (6U)                              
+#define FLASH_CR_STRT_Msk                    (0x1U << FLASH_CR_STRT_Pos)       /*!< 0x00000040 */
+#define FLASH_CR_STRT                        FLASH_CR_STRT_Msk                 /*!< Start */
+#define FLASH_CR_LOCK_Pos                    (7U)                              
+#define FLASH_CR_LOCK_Msk                    (0x1U << FLASH_CR_LOCK_Pos)       /*!< 0x00000080 */
+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Lock */
+#define FLASH_CR_OPTWRE_Pos                  (9U)                              
+#define FLASH_CR_OPTWRE_Msk                  (0x1U << FLASH_CR_OPTWRE_Pos)     /*!< 0x00000200 */
+#define FLASH_CR_OPTWRE                      FLASH_CR_OPTWRE_Msk               /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE_Pos                   (10U)                             
+#define FLASH_CR_ERRIE_Msk                   (0x1U << FLASH_CR_ERRIE_Pos)      /*!< 0x00000400 */
+#define FLASH_CR_ERRIE                       FLASH_CR_ERRIE_Msk                /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE_Pos                   (12U)                             
+#define FLASH_CR_EOPIE_Msk                   (0x1U << FLASH_CR_EOPIE_Pos)      /*!< 0x00001000 */
+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End of operation interrupt enable */
+#define FLASH_CR_OBL_LAUNCH_Pos              (13U)                             
+#define FLASH_CR_OBL_LAUNCH_Msk              (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */
+#define FLASH_CR_OBL_LAUNCH                  FLASH_CR_OBL_LAUNCH_Msk           /*!< OptionBytes Loader Launch */
+
+/*******************  Bit definition for FLASH_AR register  *******************/
+#define FLASH_AR_FAR_Pos                     (0U)                              
+#define FLASH_AR_FAR_Msk                     (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_AR_FAR                         FLASH_AR_FAR_Msk                  /*!< Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define FLASH_OBR_OPTERR_Pos                 (0U)                              
+#define FLASH_OBR_OPTERR_Msk                 (0x1U << FLASH_OBR_OPTERR_Pos)    /*!< 0x00000001 */
+#define FLASH_OBR_OPTERR                     FLASH_OBR_OPTERR_Msk              /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT_Pos                  (1U)                              
+#define FLASH_OBR_RDPRT_Msk                  (0x3U << FLASH_OBR_RDPRT_Pos)     /*!< 0x00000006 */
+#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read protection */
+#define FLASH_OBR_RDPRT_1                    (0x1U << FLASH_OBR_RDPRT_Pos)     /*!< 0x00000002 */
+#define FLASH_OBR_RDPRT_2                    (0x3U << FLASH_OBR_RDPRT_Pos)     /*!< 0x00000006 */
+
+#define FLASH_OBR_USER_Pos                   (8U)                              
+#define FLASH_OBR_USER_Msk                   (0x77U << FLASH_OBR_USER_Pos)     /*!< 0x00007700 */
+#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
+#define FLASH_OBR_IWDG_SW_Pos                (8U)                              
+#define FLASH_OBR_IWDG_SW_Msk                (0x1U << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00000100 */
+#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP_Pos              (9U)                              
+#define FLASH_OBR_nRST_STOP_Msk              (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */
+#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY_Pos             (10U)                             
+#define FLASH_OBR_nRST_STDBY_Msk             (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */
+#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
+#define FLASH_OBR_nBOOT1_Pos                 (12U)                             
+#define FLASH_OBR_nBOOT1_Msk                 (0x1U << FLASH_OBR_nBOOT1_Pos)    /*!< 0x00001000 */
+#define FLASH_OBR_nBOOT1                     FLASH_OBR_nBOOT1_Msk              /*!< nBOOT1 */
+#define FLASH_OBR_VDDA_MONITOR_Pos           (13U)                             
+#define FLASH_OBR_VDDA_MONITOR_Msk           (0x1U << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */
+#define FLASH_OBR_VDDA_MONITOR               FLASH_OBR_VDDA_MONITOR_Msk        /*!< VDDA_MONITOR */
+#define FLASH_OBR_SRAM_PE_Pos                (14U)                             
+#define FLASH_OBR_SRAM_PE_Msk                (0x1U << FLASH_OBR_SRAM_PE_Pos)   /*!< 0x00004000 */
+#define FLASH_OBR_SRAM_PE                    FLASH_OBR_SRAM_PE_Msk             /*!< SRAM_PE */
+#define FLASH_OBR_DATA0_Pos                  (16U)                             
+#define FLASH_OBR_DATA0_Msk                  (0xFFU << FLASH_OBR_DATA0_Pos)    /*!< 0x00FF0000 */
+#define FLASH_OBR_DATA0                      FLASH_OBR_DATA0_Msk               /*!< Data0 */
+#define FLASH_OBR_DATA1_Pos                  (24U)                             
+#define FLASH_OBR_DATA1_Msk                  (0xFFU << FLASH_OBR_DATA1_Pos)    /*!< 0xFF000000 */
+#define FLASH_OBR_DATA1                      FLASH_OBR_DATA1_Msk               /*!< Data1 */
+
+/* Legacy defines */
+#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define FLASH_WRPR_WRP_Pos                   (0U)                              
+#define FLASH_WRPR_WRP_Msk                   (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_WRPR_WRP                       FLASH_WRPR_WRP_Msk                /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for OB_RDP register  **********************/
+#define OB_RDP_RDP_Pos       (0U)                                              
+#define OB_RDP_RDP_Msk       (0xFFU << OB_RDP_RDP_Pos)                         /*!< 0x000000FF */
+#define OB_RDP_RDP           OB_RDP_RDP_Msk                                    /*!< Read protection option byte */
+#define OB_RDP_nRDP_Pos      (8U)                                              
+#define OB_RDP_nRDP_Msk      (0xFFU << OB_RDP_nRDP_Pos)                        /*!< 0x0000FF00 */
+#define OB_RDP_nRDP          OB_RDP_nRDP_Msk                                   /*!< Read protection complemented option byte */
+
+/******************  Bit definition for OB_USER register  *********************/
+#define OB_USER_USER_Pos     (16U)                                             
+#define OB_USER_USER_Msk     (0xFFU << OB_USER_USER_Pos)                       /*!< 0x00FF0000 */
+#define OB_USER_USER         OB_USER_USER_Msk                                  /*!< User option byte */
+#define OB_USER_nUSER_Pos    (24U)                                             
+#define OB_USER_nUSER_Msk    (0xFFU << OB_USER_nUSER_Pos)                      /*!< 0xFF000000 */
+#define OB_USER_nUSER        OB_USER_nUSER_Msk                                 /*!< User complemented option byte */
+
+/******************  Bit definition for FLASH_WRP0 register  ******************/
+#define OB_WRP0_WRP0_Pos     (0U)                                              
+#define OB_WRP0_WRP0_Msk     (0xFFU << OB_WRP0_WRP0_Pos)                       /*!< 0x000000FF */
+#define OB_WRP0_WRP0         OB_WRP0_WRP0_Msk                                  /*!< Flash memory write protection option bytes */
+#define OB_WRP0_nWRP0_Pos    (8U)                                              
+#define OB_WRP0_nWRP0_Msk    (0xFFU << OB_WRP0_nWRP0_Pos)                      /*!< 0x0000FF00 */
+#define OB_WRP0_nWRP0        OB_WRP0_nWRP0_Msk                                 /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP1 register  ******************/
+#define OB_WRP1_WRP1_Pos     (16U)                                             
+#define OB_WRP1_WRP1_Msk     (0xFFU << OB_WRP1_WRP1_Pos)                       /*!< 0x00FF0000 */
+#define OB_WRP1_WRP1         OB_WRP1_WRP1_Msk                                  /*!< Flash memory write protection option bytes */
+#define OB_WRP1_nWRP1_Pos    (24U)                                             
+#define OB_WRP1_nWRP1_Msk    (0xFFU << OB_WRP1_nWRP1_Pos)                      /*!< 0xFF000000 */
+#define OB_WRP1_nWRP1        OB_WRP1_nWRP1_Msk                                 /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP2 register  ******************/
+#define OB_WRP2_WRP2_Pos     (0U)                                              
+#define OB_WRP2_WRP2_Msk     (0xFFU << OB_WRP2_WRP2_Pos)                       /*!< 0x000000FF */
+#define OB_WRP2_WRP2         OB_WRP2_WRP2_Msk                                  /*!< Flash memory write protection option bytes */
+#define OB_WRP2_nWRP2_Pos    (8U)                                              
+#define OB_WRP2_nWRP2_Msk    (0xFFU << OB_WRP2_nWRP2_Pos)                      /*!< 0x0000FF00 */
+#define OB_WRP2_nWRP2        OB_WRP2_nWRP2_Msk                                 /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP3 register  ******************/
+#define OB_WRP3_WRP3_Pos     (16U)                                             
+#define OB_WRP3_WRP3_Msk     (0xFFU << OB_WRP3_WRP3_Pos)                       /*!< 0x00FF0000 */
+#define OB_WRP3_WRP3         OB_WRP3_WRP3_Msk                                  /*!< Flash memory write protection option bytes */
+#define OB_WRP3_nWRP3_Pos    (24U)                                             
+#define OB_WRP3_nWRP3_Msk    (0xFFU << OB_WRP3_nWRP3_Pos)                      /*!< 0xFF000000 */
+#define OB_WRP3_nWRP3        OB_WRP3_nWRP3_Msk                                 /*!< Flash memory write protection complemented option bytes */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCRx register  *******************/
+#define FMC_BCRx_MBKEN_Pos          (0U)                                       
+#define FMC_BCRx_MBKEN_Msk          (0x1U << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCRx_MBKEN              FMC_BCRx_MBKEN_Msk                         /*!<Memory bank enable bit                 */
+#define FMC_BCRx_MUXEN_Pos          (1U)                                       
+#define FMC_BCRx_MUXEN_Msk          (0x1U << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCRx_MUXEN              FMC_BCRx_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCRx_MTYP_Pos           (2U)                                       
+#define FMC_BCRx_MTYP_Msk           (0x3U << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCRx_MTYP               FMC_BCRx_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCRx_MTYP_0             (0x1U << FMC_BCRx_MTYP_Pos)                /*!< 0x00000004 */
+#define FMC_BCRx_MTYP_1             (0x2U << FMC_BCRx_MTYP_Pos)                /*!< 0x00000008 */
+
+#define FMC_BCRx_MWID_Pos           (4U)                                       
+#define FMC_BCRx_MWID_Msk           (0x3U << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCRx_MWID               FMC_BCRx_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCRx_MWID_0             (0x1U << FMC_BCRx_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_BCRx_MWID_1             (0x2U << FMC_BCRx_MWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_BCRx_FACCEN_Pos         (6U)                                       
+#define FMC_BCRx_FACCEN_Msk         (0x1U << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCRx_FACCEN             FMC_BCRx_FACCEN_Msk                        /*!<Flash access enable        */
+#define FMC_BCRx_BURSTEN_Pos        (8U)                                       
+#define FMC_BCRx_BURSTEN_Msk        (0x1U << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCRx_BURSTEN            FMC_BCRx_BURSTEN_Msk                       /*!<Burst enable bit           */
+#define FMC_BCRx_WAITPOL_Pos        (9U)                                       
+#define FMC_BCRx_WAITPOL_Msk        (0x1U << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCRx_WAITPOL            FMC_BCRx_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
+#define FMC_BCRx_WRAPMOD_Pos        (10U)                                      
+#define FMC_BCRx_WRAPMOD_Msk        (0x1U << FMC_BCRx_WRAPMOD_Pos)             /*!< 0x00000400 */
+#define FMC_BCRx_WRAPMOD            FMC_BCRx_WRAPMOD_Msk                       /*!<Wrapped burst mode support */
+#define FMC_BCRx_WAITCFG_Pos        (11U)                                      
+#define FMC_BCRx_WAITCFG_Msk        (0x1U << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCRx_WAITCFG            FMC_BCRx_WAITCFG_Msk                       /*!<Wait timing configuration  */
+#define FMC_BCRx_WREN_Pos           (12U)                                      
+#define FMC_BCRx_WREN_Msk           (0x1U << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCRx_WREN               FMC_BCRx_WREN_Msk                          /*!<Write enable bit           */
+#define FMC_BCRx_WAITEN_Pos         (13U)                                      
+#define FMC_BCRx_WAITEN_Msk         (0x1U << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCRx_WAITEN             FMC_BCRx_WAITEN_Msk                        /*!<Wait enable bit            */
+#define FMC_BCRx_EXTMOD_Pos         (14U)                                      
+#define FMC_BCRx_EXTMOD_Msk         (0x1U << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCRx_EXTMOD             FMC_BCRx_EXTMOD_Msk                        /*!<Extended mode enable       */
+#define FMC_BCRx_ASYNCWAIT_Pos      (15U)                                      
+#define FMC_BCRx_ASYNCWAIT_Msk      (0x1U << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCRx_ASYNCWAIT          FMC_BCRx_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
+#define FMC_BCRx_CBURSTRW_Pos       (19U)                                      
+#define FMC_BCRx_CBURSTRW_Msk       (0x1U << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCRx_CBURSTRW           FMC_BCRx_CBURSTRW_Msk                      /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BCR1 register  *******************/
+#define FMC_BCR1_MBKEN_Pos          (0U)                                       
+#define FMC_BCR1_MBKEN_Msk          (0x1U << FMC_BCR1_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCR1_MBKEN              FMC_BCR1_MBKEN_Msk                         /*!<Memory bank enable bit                 */
+#define FMC_BCR1_MUXEN_Pos          (1U)                                       
+#define FMC_BCR1_MUXEN_Msk          (0x1U << FMC_BCR1_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCR1_MUXEN              FMC_BCR1_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCR1_MTYP_Pos           (2U)                                       
+#define FMC_BCR1_MTYP_Msk           (0x3U << FMC_BCR1_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCR1_MTYP               FMC_BCR1_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCR1_MTYP_0             (0x1U << FMC_BCR1_MTYP_Pos)                /*!< 0x00000004 */
+#define FMC_BCR1_MTYP_1             (0x2U << FMC_BCR1_MTYP_Pos)                /*!< 0x00000008 */
+
+#define FMC_BCR1_MWID_Pos           (4U)                                       
+#define FMC_BCR1_MWID_Msk           (0x3U << FMC_BCR1_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCR1_MWID               FMC_BCR1_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0             (0x1U << FMC_BCR1_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_BCR1_MWID_1             (0x2U << FMC_BCR1_MWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_BCR1_FACCEN_Pos         (6U)                                       
+#define FMC_BCR1_FACCEN_Msk         (0x1U << FMC_BCR1_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCR1_FACCEN             FMC_BCR1_FACCEN_Msk                        /*!<Flash access enable        */
+#define FMC_BCR1_BURSTEN_Pos        (8U)                                       
+#define FMC_BCR1_BURSTEN_Msk        (0x1U << FMC_BCR1_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCR1_BURSTEN            FMC_BCR1_BURSTEN_Msk                       /*!<Burst enable bit           */
+#define FMC_BCR1_WAITPOL_Pos        (9U)                                       
+#define FMC_BCR1_WAITPOL_Msk        (0x1U << FMC_BCR1_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCR1_WAITPOL            FMC_BCR1_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
+#define FMC_BCR1_WRAPMOD_Pos        (10U)                                      
+#define FMC_BCR1_WRAPMOD_Msk        (0x1U << FMC_BCR1_WRAPMOD_Pos)             /*!< 0x00000400 */
+#define FMC_BCR1_WRAPMOD            FMC_BCR1_WRAPMOD_Msk                       /*!<Wrapped burst mode support */
+#define FMC_BCR1_WAITCFG_Pos        (11U)                                      
+#define FMC_BCR1_WAITCFG_Msk        (0x1U << FMC_BCR1_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCR1_WAITCFG            FMC_BCR1_WAITCFG_Msk                       /*!<Wait timing configuration  */
+#define FMC_BCR1_WREN_Pos           (12U)                                      
+#define FMC_BCR1_WREN_Msk           (0x1U << FMC_BCR1_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCR1_WREN               FMC_BCR1_WREN_Msk                          /*!<Write enable bit           */
+#define FMC_BCR1_WAITEN_Pos         (13U)                                      
+#define FMC_BCR1_WAITEN_Msk         (0x1U << FMC_BCR1_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCR1_WAITEN             FMC_BCR1_WAITEN_Msk                        /*!<Wait enable bit            */
+#define FMC_BCR1_EXTMOD_Pos         (14U)                                      
+#define FMC_BCR1_EXTMOD_Msk         (0x1U << FMC_BCR1_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCR1_EXTMOD             FMC_BCR1_EXTMOD_Msk                        /*!<Extended mode enable       */
+#define FMC_BCR1_ASYNCWAIT_Pos      (15U)                                      
+#define FMC_BCR1_ASYNCWAIT_Msk      (0x1U << FMC_BCR1_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCR1_ASYNCWAIT          FMC_BCR1_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
+#define FMC_BCR1_CBURSTRW_Pos       (19U)                                      
+#define FMC_BCR1_CBURSTRW_Msk       (0x1U << FMC_BCR1_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCR1_CBURSTRW           FMC_BCR1_CBURSTRW_Msk                      /*!<Write burst enable         */
+#define FMC_BCR1_CCLKEN_Pos         (20U)                                      
+#define FMC_BCR1_CCLKEN_Msk         (0x1U << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN             FMC_BCR1_CCLKEN_Msk                        /*!<Continous clock enable     */
+
+/******************  Bit definition for FMC_BCR2 register  *******************/
+#define FMC_BCR2_MBKEN_Pos          (0U)                                       
+#define FMC_BCR2_MBKEN_Msk          (0x1U << FMC_BCR2_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCR2_MBKEN              FMC_BCR2_MBKEN_Msk                         /*!<Memory bank enable bit                 */
+#define FMC_BCR2_MUXEN_Pos          (1U)                                       
+#define FMC_BCR2_MUXEN_Msk          (0x1U << FMC_BCR2_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCR2_MUXEN              FMC_BCR2_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCR2_MTYP_Pos           (2U)                                       
+#define FMC_BCR2_MTYP_Msk           (0x3U << FMC_BCR2_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCR2_MTYP               FMC_BCR2_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCR2_MTYP_0             (0x1U << FMC_BCR2_MTYP_Pos)                /*!< 0x00000004 */
+#define FMC_BCR2_MTYP_1             (0x2U << FMC_BCR2_MTYP_Pos)                /*!< 0x00000008 */
+
+#define FMC_BCR2_MWID_Pos           (4U)                                       
+#define FMC_BCR2_MWID_Msk           (0x3U << FMC_BCR2_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCR2_MWID               FMC_BCR2_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0             (0x1U << FMC_BCR2_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_BCR2_MWID_1             (0x2U << FMC_BCR2_MWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_BCR2_FACCEN_Pos         (6U)                                       
+#define FMC_BCR2_FACCEN_Msk         (0x1U << FMC_BCR2_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCR2_FACCEN             FMC_BCR2_FACCEN_Msk                        /*!<Flash access enable        */
+#define FMC_BCR2_BURSTEN_Pos        (8U)                                       
+#define FMC_BCR2_BURSTEN_Msk        (0x1U << FMC_BCR2_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCR2_BURSTEN            FMC_BCR2_BURSTEN_Msk                       /*!<Burst enable bit           */
+#define FMC_BCR2_WAITPOL_Pos        (9U)                                       
+#define FMC_BCR2_WAITPOL_Msk        (0x1U << FMC_BCR2_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCR2_WAITPOL            FMC_BCR2_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
+#define FMC_BCR2_WRAPMOD_Pos        (10U)                                      
+#define FMC_BCR2_WRAPMOD_Msk        (0x1U << FMC_BCR2_WRAPMOD_Pos)             /*!< 0x00000400 */
+#define FMC_BCR2_WRAPMOD            FMC_BCR2_WRAPMOD_Msk                       /*!<Wrapped burst mode support */
+#define FMC_BCR2_WAITCFG_Pos        (11U)                                      
+#define FMC_BCR2_WAITCFG_Msk        (0x1U << FMC_BCR2_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCR2_WAITCFG            FMC_BCR2_WAITCFG_Msk                       /*!<Wait timing configuration  */
+#define FMC_BCR2_WREN_Pos           (12U)                                      
+#define FMC_BCR2_WREN_Msk           (0x1U << FMC_BCR2_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCR2_WREN               FMC_BCR2_WREN_Msk                          /*!<Write enable bit           */
+#define FMC_BCR2_WAITEN_Pos         (13U)                                      
+#define FMC_BCR2_WAITEN_Msk         (0x1U << FMC_BCR2_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCR2_WAITEN             FMC_BCR2_WAITEN_Msk                        /*!<Wait enable bit            */
+#define FMC_BCR2_EXTMOD_Pos         (14U)                                      
+#define FMC_BCR2_EXTMOD_Msk         (0x1U << FMC_BCR2_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCR2_EXTMOD             FMC_BCR2_EXTMOD_Msk                        /*!<Extended mode enable       */
+#define FMC_BCR2_ASYNCWAIT_Pos      (15U)                                      
+#define FMC_BCR2_ASYNCWAIT_Msk      (0x1U << FMC_BCR2_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCR2_ASYNCWAIT          FMC_BCR2_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
+#define FMC_BCR2_CBURSTRW_Pos       (19U)                                      
+#define FMC_BCR2_CBURSTRW_Msk       (0x1U << FMC_BCR2_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCR2_CBURSTRW           FMC_BCR2_CBURSTRW_Msk                      /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BCR3 register  *******************/
+#define FMC_BCR3_MBKEN_Pos          (0U)                                       
+#define FMC_BCR3_MBKEN_Msk          (0x1U << FMC_BCR3_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCR3_MBKEN              FMC_BCR3_MBKEN_Msk                         /*!<Memory bank enable bit                 */
+#define FMC_BCR3_MUXEN_Pos          (1U)                                       
+#define FMC_BCR3_MUXEN_Msk          (0x1U << FMC_BCR3_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCR3_MUXEN              FMC_BCR3_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCR3_MTYP_Pos           (2U)                                       
+#define FMC_BCR3_MTYP_Msk           (0x3U << FMC_BCR3_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCR3_MTYP               FMC_BCR3_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCR3_MTYP_0             (0x1U << FMC_BCR3_MTYP_Pos)                /*!< 0x00000004 */
+#define FMC_BCR3_MTYP_1             (0x2U << FMC_BCR3_MTYP_Pos)                /*!< 0x00000008 */
+
+#define FMC_BCR3_MWID_Pos           (4U)                                       
+#define FMC_BCR3_MWID_Msk           (0x3U << FMC_BCR3_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCR3_MWID               FMC_BCR3_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0             (0x1U << FMC_BCR3_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_BCR3_MWID_1             (0x2U << FMC_BCR3_MWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_BCR3_FACCEN_Pos         (6U)                                       
+#define FMC_BCR3_FACCEN_Msk         (0x1U << FMC_BCR3_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCR3_FACCEN             FMC_BCR3_FACCEN_Msk                        /*!<Flash access enable        */
+#define FMC_BCR3_BURSTEN_Pos        (8U)                                       
+#define FMC_BCR3_BURSTEN_Msk        (0x1U << FMC_BCR3_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCR3_BURSTEN            FMC_BCR3_BURSTEN_Msk                       /*!<Burst enable bit           */
+#define FMC_BCR3_WAITPOL_Pos        (9U)                                       
+#define FMC_BCR3_WAITPOL_Msk        (0x1U << FMC_BCR3_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCR3_WAITPOL            FMC_BCR3_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
+#define FMC_BCR3_WRAPMOD_Pos        (10U)                                      
+#define FMC_BCR3_WRAPMOD_Msk        (0x1U << FMC_BCR3_WRAPMOD_Pos)             /*!< 0x00000400 */
+#define FMC_BCR3_WRAPMOD            FMC_BCR3_WRAPMOD_Msk                       /*!<Wrapped burst mode support */
+#define FMC_BCR3_WAITCFG_Pos        (11U)                                      
+#define FMC_BCR3_WAITCFG_Msk        (0x1U << FMC_BCR3_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCR3_WAITCFG            FMC_BCR3_WAITCFG_Msk                       /*!<Wait timing configuration  */
+#define FMC_BCR3_WREN_Pos           (12U)                                      
+#define FMC_BCR3_WREN_Msk           (0x1U << FMC_BCR3_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCR3_WREN               FMC_BCR3_WREN_Msk                          /*!<Write enable bit           */
+#define FMC_BCR3_WAITEN_Pos         (13U)                                      
+#define FMC_BCR3_WAITEN_Msk         (0x1U << FMC_BCR3_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCR3_WAITEN             FMC_BCR3_WAITEN_Msk                        /*!<Wait enable bit            */
+#define FMC_BCR3_EXTMOD_Pos         (14U)                                      
+#define FMC_BCR3_EXTMOD_Msk         (0x1U << FMC_BCR3_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCR3_EXTMOD             FMC_BCR3_EXTMOD_Msk                        /*!<Extended mode enable       */
+#define FMC_BCR3_ASYNCWAIT_Pos      (15U)                                      
+#define FMC_BCR3_ASYNCWAIT_Msk      (0x1U << FMC_BCR3_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCR3_ASYNCWAIT          FMC_BCR3_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
+#define FMC_BCR3_CBURSTRW_Pos       (19U)                                      
+#define FMC_BCR3_CBURSTRW_Msk       (0x1U << FMC_BCR3_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCR3_CBURSTRW           FMC_BCR3_CBURSTRW_Msk                      /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BCR4 register  *******************/
+#define FMC_BCR4_MBKEN_Pos          (0U)                                       
+#define FMC_BCR4_MBKEN_Msk          (0x1U << FMC_BCR4_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCR4_MBKEN              FMC_BCR4_MBKEN_Msk                         /*!<Memory bank enable bit                 */
+#define FMC_BCR4_MUXEN_Pos          (1U)                                       
+#define FMC_BCR4_MUXEN_Msk          (0x1U << FMC_BCR4_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCR4_MUXEN              FMC_BCR4_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCR4_MTYP_Pos           (2U)                                       
+#define FMC_BCR4_MTYP_Msk           (0x3U << FMC_BCR4_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCR4_MTYP               FMC_BCR4_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCR4_MTYP_0             (0x1U << FMC_BCR4_MTYP_Pos)                /*!< 0x00000004 */
+#define FMC_BCR4_MTYP_1             (0x2U << FMC_BCR4_MTYP_Pos)                /*!< 0x00000008 */
+
+#define FMC_BCR4_MWID_Pos           (4U)                                       
+#define FMC_BCR4_MWID_Msk           (0x3U << FMC_BCR4_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCR4_MWID               FMC_BCR4_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0             (0x1U << FMC_BCR4_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_BCR4_MWID_1             (0x2U << FMC_BCR4_MWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_BCR4_FACCEN_Pos         (6U)                                       
+#define FMC_BCR4_FACCEN_Msk         (0x1U << FMC_BCR4_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCR4_FACCEN             FMC_BCR4_FACCEN_Msk                        /*!<Flash access enable        */
+#define FMC_BCR4_BURSTEN_Pos        (8U)                                       
+#define FMC_BCR4_BURSTEN_Msk        (0x1U << FMC_BCR4_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCR4_BURSTEN            FMC_BCR4_BURSTEN_Msk                       /*!<Burst enable bit           */
+#define FMC_BCR4_WAITPOL_Pos        (9U)                                       
+#define FMC_BCR4_WAITPOL_Msk        (0x1U << FMC_BCR4_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCR4_WAITPOL            FMC_BCR4_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
+#define FMC_BCR4_WRAPMOD_Pos        (10U)                                      
+#define FMC_BCR4_WRAPMOD_Msk        (0x1U << FMC_BCR4_WRAPMOD_Pos)             /*!< 0x00000400 */
+#define FMC_BCR4_WRAPMOD            FMC_BCR4_WRAPMOD_Msk                       /*!<Wrapped burst mode support */
+#define FMC_BCR4_WAITCFG_Pos        (11U)                                      
+#define FMC_BCR4_WAITCFG_Msk        (0x1U << FMC_BCR4_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCR4_WAITCFG            FMC_BCR4_WAITCFG_Msk                       /*!<Wait timing configuration  */
+#define FMC_BCR4_WREN_Pos           (12U)                                      
+#define FMC_BCR4_WREN_Msk           (0x1U << FMC_BCR4_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCR4_WREN               FMC_BCR4_WREN_Msk                          /*!<Write enable bit           */
+#define FMC_BCR4_WAITEN_Pos         (13U)                                      
+#define FMC_BCR4_WAITEN_Msk         (0x1U << FMC_BCR4_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCR4_WAITEN             FMC_BCR4_WAITEN_Msk                        /*!<Wait enable bit            */
+#define FMC_BCR4_EXTMOD_Pos         (14U)                                      
+#define FMC_BCR4_EXTMOD_Msk         (0x1U << FMC_BCR4_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCR4_EXTMOD             FMC_BCR4_EXTMOD_Msk                        /*!<Extended mode enable       */
+#define FMC_BCR4_ASYNCWAIT_Pos      (15U)                                      
+#define FMC_BCR4_ASYNCWAIT_Msk      (0x1U << FMC_BCR4_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCR4_ASYNCWAIT          FMC_BCR4_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
+#define FMC_BCR4_CBURSTRW_Pos       (19U)                                      
+#define FMC_BCR4_CBURSTRW_Msk       (0x1U << FMC_BCR4_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCR4_CBURSTRW           FMC_BCR4_CBURSTRW_Msk                      /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BTRx register  ******************/
+#define FMC_BTRx_ADDSET_Pos         (0U)                                       
+#define FMC_BTRx_ADDSET_Msk         (0xFU << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTRx_ADDSET             FMC_BTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTRx_ADDSET_0           (0x1U << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BTRx_ADDSET_1           (0x2U << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BTRx_ADDSET_2           (0x4U << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BTR_ADDSET_3            (0x00000008U)                              /*!<Bit 3 */
+
+#define FMC_BTRx_ADDHLD_Pos         (4U)                                       
+#define FMC_BTRx_ADDHLD_Msk         (0xFU << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTRx_ADDHLD             FMC_BTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define FMC_BTRx_ADDHLD_0           (0x1U << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BTRx_ADDHLD_1           (0x2U << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BTRx_ADDHLD_2           (0x4U << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BTRx_ADDHLD_3           (0x8U << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BTRx_DATAST_Pos         (8U)                                       
+#define FMC_BTRx_DATAST_Msk         (0xFFU << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTRx_DATAST             FMC_BTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR_DATAST_0            (0x00000100U)                              /*!<Bit 0 */
+#define FMC_BTRx_DATAST_1           (0x00000200U)                              /*!<Bit 1 */
+#define FMC_BTRx_DATAST_2           (0x00000400U)                              /*!<Bit 2 */
+#define FMC_BTRx_DATAST_3           (0x00000800U)                              /*!<Bit 3 */
+#define FMC_BTRx_DATAST_4           (0x00001000U)                              /*!<Bit 4 */
+#define FMC_BTRx_DATAST_5           (0x00002000U)                              /*!<Bit 5 */
+#define FMC_BTRx_DATAST_6           (0x00004000U)                              /*!<Bit 6 */
+#define FMC_BTRx_DATAST_7           (0x00008000U)                              /*!<Bit 7 */
+
+#define FMC_BTRx_BUSTURN_Pos        (16U)                                      
+#define FMC_BTRx_BUSTURN_Msk        (0xFU << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTRx_BUSTURN            FMC_BTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTRx_BUSTURN_0          (0x1U << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BTRx_BUSTURN_1          (0x2U << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BTRx_BUSTURN_2          (0x4U << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BTRx_BUSTURN_3          (0x8U << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BTRx_CLKDIV_Pos         (20U)                                      
+#define FMC_BTRx_CLKDIV_Msk         (0xFU << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTRx_CLKDIV             FMC_BTRx_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTRx_CLKDIV_0           (0x1U << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00100000 */
+#define FMC_BTRx_CLKDIV_1           (0x2U << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00200000 */
+#define FMC_BTRx_CLKDIV_2           (0x4U << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00400000 */
+#define FMC_BTRx_CLKDIV_3           (0x8U << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00800000 */
+
+#define FMC_BTRx_DATLAT_Pos         (24U)                                      
+#define FMC_BTRx_DATLAT_Msk         (0xFU << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTRx_DATLAT             FMC_BTRx_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTRx_DATLAT_0           (0x1U << FMC_BTRx_DATLAT_Pos)              /*!< 0x01000000 */
+#define FMC_BTRx_DATLAT_1           (0x2U << FMC_BTRx_DATLAT_Pos)              /*!< 0x02000000 */
+#define FMC_BTRx_DATLAT_2           (0x4U << FMC_BTRx_DATLAT_Pos)              /*!< 0x04000000 */
+#define FMC_BTRx_DATLAT_3           (0x8U << FMC_BTRx_DATLAT_Pos)              /*!< 0x08000000 */
+
+#define FMC_BTRx_ACCMOD_Pos         (28U)                                      
+#define FMC_BTRx_ACCMOD_Msk         (0x3U << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTRx_ACCMOD             FMC_BTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTRx_ACCMOD_0           (0x1U << FMC_BTRx_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BTRx_ACCMOD_1           (0x2U << FMC_BTRx_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BTR1 register  ******************/
+#define FMC_BTR1_ADDSET_Pos         (0U)                                       
+#define FMC_BTR1_ADDSET_Msk         (0xFU << FMC_BTR1_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTR1_ADDSET             FMC_BTR1_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0           (0x1U << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BTR1_ADDSET_1           (0x2U << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BTR1_ADDSET_2           (0x4U << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BTR1_ADDSET_3           (0x8U << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BTR1_ADDHLD_Pos         (4U)                                       
+#define FMC_BTR1_ADDHLD_Msk         (0xFU << FMC_BTR1_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTR1_ADDHLD             FMC_BTR1_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define FMC_BTR1_ADDHLD_0           (0x1U << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BTR1_ADDHLD_1           (0x2U << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BTR1_ADDHLD_2           (0x4U << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BTR1_ADDHLD_3           (0x8U << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BTR1_DATAST_Pos         (8U)                                       
+#define FMC_BTR1_DATAST_Msk         (0xFFU << FMC_BTR1_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTR1_DATAST             FMC_BTR1_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0           (0x01U << FMC_BTR1_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BTR1_DATAST_1           (0x02U << FMC_BTR1_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BTR1_DATAST_2           (0x04U << FMC_BTR1_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BTR1_DATAST_3           (0x08U << FMC_BTR1_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BTR1_DATAST_4           (0x10U << FMC_BTR1_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BTR1_DATAST_5           (0x20U << FMC_BTR1_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BTR1_DATAST_6           (0x40U << FMC_BTR1_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BTR1_DATAST_7           (0x80U << FMC_BTR1_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BTR1_BUSTURN_Pos        (16U)                                      
+#define FMC_BTR1_BUSTURN_Msk        (0xFU << FMC_BTR1_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTR1_BUSTURN            FMC_BTR1_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0          (0x1U << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BTR1_BUSTURN_1          (0x2U << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BTR1_BUSTURN_2          (0x4U << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BTR1_BUSTURN_3          (0x8U << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BTR1_CLKDIV_Pos         (20U)                                      
+#define FMC_BTR1_CLKDIV_Msk         (0xFU << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTR1_CLKDIV             FMC_BTR1_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0           (0x1U << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00100000 */
+#define FMC_BTR1_CLKDIV_1           (0x2U << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00200000 */
+#define FMC_BTR1_CLKDIV_2           (0x4U << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00400000 */
+#define FMC_BTR1_CLKDIV_3           (0x8U << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00800000 */
+
+#define FMC_BTR1_DATLAT_Pos         (24U)                                      
+#define FMC_BTR1_DATLAT_Msk         (0xFU << FMC_BTR1_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTR1_DATLAT             FMC_BTR1_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0           (0x1U << FMC_BTR1_DATLAT_Pos)              /*!< 0x01000000 */
+#define FMC_BTR1_DATLAT_1           (0x2U << FMC_BTR1_DATLAT_Pos)              /*!< 0x02000000 */
+#define FMC_BTR1_DATLAT_2           (0x4U << FMC_BTR1_DATLAT_Pos)              /*!< 0x04000000 */
+#define FMC_BTR1_DATLAT_3           (0x8U << FMC_BTR1_DATLAT_Pos)              /*!< 0x08000000 */
+
+#define FMC_BTR1_ACCMOD_Pos         (28U)                                      
+#define FMC_BTR1_ACCMOD_Msk         (0x3U << FMC_BTR1_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTR1_ACCMOD             FMC_BTR1_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0           (0x1U << FMC_BTR1_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BTR1_ACCMOD_1           (0x2U << FMC_BTR1_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BTR2 register  *******************/
+#define FMC_BTR2_ADDSET_Pos         (0U)                                       
+#define FMC_BTR2_ADDSET_Msk         (0xFU << FMC_BTR2_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTR2_ADDSET             FMC_BTR2_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0           (0x1U << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BTR2_ADDSET_1           (0x2U << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BTR2_ADDSET_2           (0x4U << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BTR2_ADDSET_3           (0x8U << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BTR2_ADDHLD_Pos         (4U)                                       
+#define FMC_BTR2_ADDHLD_Msk         (0xFU << FMC_BTR2_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTR2_ADDHLD             FMC_BTR2_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0           (0x1U << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BTR2_ADDHLD_1           (0x2U << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BTR2_ADDHLD_2           (0x4U << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BTR2_ADDHLD_3           (0x8U << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BTR2_DATAST_Pos         (8U)                                       
+#define FMC_BTR2_DATAST_Msk         (0xFFU << FMC_BTR2_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTR2_DATAST             FMC_BTR2_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0           (0x01U << FMC_BTR2_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BTR2_DATAST_1           (0x02U << FMC_BTR2_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BTR2_DATAST_2           (0x04U << FMC_BTR2_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BTR2_DATAST_3           (0x08U << FMC_BTR2_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BTR2_DATAST_4           (0x10U << FMC_BTR2_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BTR2_DATAST_5           (0x20U << FMC_BTR2_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BTR2_DATAST_6           (0x40U << FMC_BTR2_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BTR2_DATAST_7           (0x80U << FMC_BTR2_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BTR2_BUSTURN_Pos        (16U)                                      
+#define FMC_BTR2_BUSTURN_Msk        (0xFU << FMC_BTR2_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTR2_BUSTURN            FMC_BTR2_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0          (0x1U << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BTR2_BUSTURN_1          (0x2U << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BTR2_BUSTURN_2          (0x4U << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BTR2_BUSTURN_3          (0x8U << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BTR2_CLKDIV_Pos         (20U)                                      
+#define FMC_BTR2_CLKDIV_Msk         (0xFU << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTR2_CLKDIV             FMC_BTR2_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0           (0x1U << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00100000 */
+#define FMC_BTR2_CLKDIV_1           (0x2U << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00200000 */
+#define FMC_BTR2_CLKDIV_2           (0x4U << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00400000 */
+#define FMC_BTR2_CLKDIV_3           (0x8U << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00800000 */
+
+#define FMC_BTR2_DATLAT_Pos         (24U)                                      
+#define FMC_BTR2_DATLAT_Msk         (0xFU << FMC_BTR2_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTR2_DATLAT             FMC_BTR2_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0           (0x1U << FMC_BTR2_DATLAT_Pos)              /*!< 0x01000000 */
+#define FMC_BTR2_DATLAT_1           (0x2U << FMC_BTR2_DATLAT_Pos)              /*!< 0x02000000 */
+#define FMC_BTR2_DATLAT_2           (0x4U << FMC_BTR2_DATLAT_Pos)              /*!< 0x04000000 */
+#define FMC_BTR2_DATLAT_3           (0x8U << FMC_BTR2_DATLAT_Pos)              /*!< 0x08000000 */
+
+#define FMC_BTR2_ACCMOD_Pos         (28U)                                      
+#define FMC_BTR2_ACCMOD_Msk         (0x3U << FMC_BTR2_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTR2_ACCMOD             FMC_BTR2_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0           (0x1U << FMC_BTR2_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BTR2_ACCMOD_1           (0x2U << FMC_BTR2_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/*******************  Bit definition for FMC_BTR3 register  *******************/
+#define FMC_BTR3_ADDSET_Pos         (0U)                                       
+#define FMC_BTR3_ADDSET_Msk         (0xFU << FMC_BTR3_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTR3_ADDSET             FMC_BTR3_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0           (0x1U << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BTR3_ADDSET_1           (0x2U << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BTR3_ADDSET_2           (0x4U << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BTR3_ADDSET_3           (0x8U << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BTR3_ADDHLD_Pos         (4U)                                       
+#define FMC_BTR3_ADDHLD_Msk         (0xFU << FMC_BTR3_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTR3_ADDHLD             FMC_BTR3_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0           (0x1U << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BTR3_ADDHLD_1           (0x2U << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BTR3_ADDHLD_2           (0x4U << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BTR3_ADDHLD_3           (0x8U << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BTR3_DATAST_Pos         (8U)                                       
+#define FMC_BTR3_DATAST_Msk         (0xFFU << FMC_BTR3_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTR3_DATAST             FMC_BTR3_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0           (0x01U << FMC_BTR3_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BTR3_DATAST_1           (0x02U << FMC_BTR3_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BTR3_DATAST_2           (0x04U << FMC_BTR3_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BTR3_DATAST_3           (0x08U << FMC_BTR3_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BTR3_DATAST_4           (0x10U << FMC_BTR3_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BTR3_DATAST_5           (0x20U << FMC_BTR3_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BTR3_DATAST_6           (0x40U << FMC_BTR3_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BTR3_DATAST_7           (0x80U << FMC_BTR3_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BTR3_BUSTURN_Pos        (16U)                                      
+#define FMC_BTR3_BUSTURN_Msk        (0xFU << FMC_BTR3_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTR3_BUSTURN            FMC_BTR3_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0          (0x1U << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BTR3_BUSTURN_1          (0x2U << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BTR3_BUSTURN_2          (0x4U << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BTR3_BUSTURN_3          (0x8U << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BTR3_CLKDIV_Pos         (20U)                                      
+#define FMC_BTR3_CLKDIV_Msk         (0xFU << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTR3_CLKDIV             FMC_BTR3_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0           (0x1U << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00100000 */
+#define FMC_BTR3_CLKDIV_1           (0x2U << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00200000 */
+#define FMC_BTR3_CLKDIV_2           (0x4U << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00400000 */
+#define FMC_BTR3_CLKDIV_3           (0x8U << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00800000 */
+
+#define FMC_BTR3_DATLAT_Pos         (24U)                                      
+#define FMC_BTR3_DATLAT_Msk         (0xFU << FMC_BTR3_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTR3_DATLAT             FMC_BTR3_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0           (0x1U << FMC_BTR3_DATLAT_Pos)              /*!< 0x01000000 */
+#define FMC_BTR3_DATLAT_1           (0x2U << FMC_BTR3_DATLAT_Pos)              /*!< 0x02000000 */
+#define FMC_BTR3_DATLAT_2           (0x4U << FMC_BTR3_DATLAT_Pos)              /*!< 0x04000000 */
+#define FMC_BTR3_DATLAT_3           (0x8U << FMC_BTR3_DATLAT_Pos)              /*!< 0x08000000 */
+
+#define FMC_BTR3_ACCMOD_Pos         (28U)                                      
+#define FMC_BTR3_ACCMOD_Msk         (0x3U << FMC_BTR3_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTR3_ACCMOD             FMC_BTR3_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0           (0x1U << FMC_BTR3_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BTR3_ACCMOD_1           (0x2U << FMC_BTR3_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BTR4 register  *******************/
+#define FMC_BTR4_ADDSET_Pos         (0U)                                       
+#define FMC_BTR4_ADDSET_Msk         (0xFU << FMC_BTR4_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTR4_ADDSET             FMC_BTR4_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0           (0x1U << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BTR4_ADDSET_1           (0x2U << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BTR4_ADDSET_2           (0x4U << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BTR4_ADDSET_3           (0x8U << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BTR4_ADDHLD_Pos         (4U)                                       
+#define FMC_BTR4_ADDHLD_Msk         (0xFU << FMC_BTR4_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTR4_ADDHLD             FMC_BTR4_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0           (0x1U << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BTR4_ADDHLD_1           (0x2U << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BTR4_ADDHLD_2           (0x4U << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BTR4_ADDHLD_3           (0x8U << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BTR4_DATAST_Pos         (8U)                                       
+#define FMC_BTR4_DATAST_Msk         (0xFFU << FMC_BTR4_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTR4_DATAST             FMC_BTR4_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0           (0x01U << FMC_BTR4_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BTR4_DATAST_1           (0x02U << FMC_BTR4_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BTR4_DATAST_2           (0x04U << FMC_BTR4_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BTR4_DATAST_3           (0x08U << FMC_BTR4_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BTR4_DATAST_4           (0x10U << FMC_BTR4_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BTR4_DATAST_5           (0x20U << FMC_BTR4_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BTR4_DATAST_6           (0x40U << FMC_BTR4_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BTR4_DATAST_7           (0x80U << FMC_BTR4_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BTR4_BUSTURN_Pos        (16U)                                      
+#define FMC_BTR4_BUSTURN_Msk        (0xFU << FMC_BTR4_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTR4_BUSTURN            FMC_BTR4_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0          (0x1U << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BTR4_BUSTURN_1          (0x2U << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BTR4_BUSTURN_2          (0x4U << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BTR4_BUSTURN_3          (0x8U << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BTR4_CLKDIV_Pos         (20U)                                      
+#define FMC_BTR4_CLKDIV_Msk         (0xFU << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTR4_CLKDIV             FMC_BTR4_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0           (0x1U << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00100000 */
+#define FMC_BTR4_CLKDIV_1           (0x2U << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00200000 */
+#define FMC_BTR4_CLKDIV_2           (0x4U << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00400000 */
+#define FMC_BTR4_CLKDIV_3           (0x8U << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00800000 */
+
+#define FMC_BTR4_DATLAT_Pos         (24U)                                      
+#define FMC_BTR4_DATLAT_Msk         (0xFU << FMC_BTR4_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTR4_DATLAT             FMC_BTR4_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0           (0x1U << FMC_BTR4_DATLAT_Pos)              /*!< 0x01000000 */
+#define FMC_BTR4_DATLAT_1           (0x2U << FMC_BTR4_DATLAT_Pos)              /*!< 0x02000000 */
+#define FMC_BTR4_DATLAT_2           (0x4U << FMC_BTR4_DATLAT_Pos)              /*!< 0x04000000 */
+#define FMC_BTR4_DATLAT_3           (0x8U << FMC_BTR4_DATLAT_Pos)              /*!< 0x08000000 */
+
+#define FMC_BTR4_ACCMOD_Pos         (28U)                                      
+#define FMC_BTR4_ACCMOD_Msk         (0x3U << FMC_BTR4_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTR4_ACCMOD             FMC_BTR4_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0           (0x1U << FMC_BTR4_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BTR4_ACCMOD_1           (0x2U << FMC_BTR4_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTRx register  ******************/
+#define FMC_BWTRx_ADDSET_Pos        (0U)                                       
+#define FMC_BWTRx_ADDSET_Msk        (0xFU << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTRx_ADDSET            FMC_BWTRx_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTRx_ADDSET_0          (0x1U << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000001 */
+#define FMC_BWTRx_ADDSET_1          (0x2U << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000002 */
+#define FMC_BWTRx_ADDSET_2          (0x4U << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000004 */
+#define FMC_BWTRx_ADDSET_3          (0x8U << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000008 */
+
+#define FMC_BWTRx_ADDHLD_Pos        (4U)                                       
+#define FMC_BWTRx_ADDHLD_Msk        (0xFU << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTRx_ADDHLD            FMC_BWTRx_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTRx_ADDHLD_0          (0x1U << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000010 */
+#define FMC_BWTRx_ADDHLD_1          (0x2U << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000020 */
+#define FMC_BWTRx_ADDHLD_2          (0x4U << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000040 */
+#define FMC_BWTRx_ADDHLD_3          (0x8U << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000080 */
+
+#define FMC_BWTRx_DATAST_Pos        (8U)                                       
+#define FMC_BWTRx_DATAST_Msk        (0xFFU << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTRx_DATAST            FMC_BWTRx_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTRx_DATAST_0          (0x01U << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000100 */
+#define FMC_BWTRx_DATAST_1          (0x02U << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000200 */
+#define FMC_BWTRx_DATAST_2          (0x04U << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000400 */
+#define FMC_BWTRx_DATAST_3          (0x08U << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000800 */
+#define FMC_BWTRx_DATAST_4          (0x10U << FMC_BWTRx_DATAST_Pos)            /*!< 0x00001000 */
+#define FMC_BWTRx_DATAST_5          (0x20U << FMC_BWTRx_DATAST_Pos)            /*!< 0x00002000 */
+#define FMC_BWTRx_DATAST_6          (0x40U << FMC_BWTRx_DATAST_Pos)            /*!< 0x00004000 */
+#define FMC_BWTRx_DATAST_7          (0x80U << FMC_BWTRx_DATAST_Pos)            /*!< 0x00008000 */
+
+#define FMC_BWTRx_ACCMOD_Pos        (28U)                                      
+#define FMC_BWTRx_ACCMOD_Msk        (0x3U << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTRx_ACCMOD            FMC_BWTRx_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTRx_ACCMOD_0          (0x1U << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x10000000 */
+#define FMC_BWTRx_ACCMOD_1          (0x2U << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x20000000 */
+
+/* Old Bit definition for FMC_BWTRx register maintained for legacy purpose */
+#define  FMC_BWTRx_ADDSETx                  FMC_BWTRx_ADDSET
+#define  FMC_BWTRx_ADDSETx_0                FMC_BWTRx_ADDSET_0
+#define  FMC_BWTRx_ADDSETx_1                FMC_BWTRx_ADDSET_1
+#define  FMC_BWTRx_ADDSETx_2                FMC_BWTRx_ADDSET_2
+#define  FMC_BWTRx_ADDSETx_3                FMC_BWTRx_ADDSET_3
+
+#define  FMC_BWTRx_ADDHLDx                  FMC_BWTRx_ADDHLD
+#define  FMC_BWTRx_ADDHLDx_0                FMC_BWTRx_ADDHLD_0
+#define  FMC_BWTRx_ADDHLDx_1                FMC_BWTRx_ADDHLD_1
+#define  FMC_BWTRx_ADDHLDx_2                FMC_BWTRx_ADDHLD_2
+#define  FMC_BWTRx_ADDHLDx_3                FMC_BWTRx_ADDHLD_3
+
+#define  FMC_BWTRx_DATASTx                  FMC_BWTRx_DATAST
+#define  FMC_BWTRx_DATASTx_0                FMC_BWTRx_DATAST_0
+#define  FMC_BWTRx_DATASTx_1                FMC_BWTRx_DATAST_1
+#define  FMC_BWTRx_DATASTx_2                FMC_BWTRx_DATAST_2
+#define  FMC_BWTRx_DATASTx_3                FMC_BWTRx_DATAST_3
+#define  FMC_BWTRx_DATASTx_4                FMC_BWTRx_DATAST_4
+#define  FMC_BWTRx_DATASTx_5                FMC_BWTRx_DATAST_5
+#define  FMC_BWTRx_DATASTx_6                FMC_BWTRx_DATAST_6
+#define  FMC_BWTRx_DATASTx_7                FMC_BWTRx_DATAST_7
+
+#define  FMC_BWTRx_ACCMODx                  FMC_BWTRx_ACCMOD
+#define  FMC_BWTRx_ACCMODx_0                FMC_BWTRx_ACCMOD_0
+#define  FMC_BWTRx_ACCMODx_1                FMC_BWTRx_ACCMOD_1
+
+/******************  Bit definition for FMC_BWTR1 register  ******************/
+#define FMC_BWTR1_ADDSET_Pos        (0U)                                       
+#define FMC_BWTR1_ADDSET_Msk        (0xFU << FMC_BWTR1_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTR1_ADDSET            FMC_BWTR1_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0          (0x1U << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000001 */
+#define FMC_BWTR1_ADDSET_1          (0x2U << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000002 */
+#define FMC_BWTR1_ADDSET_2          (0x4U << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000004 */
+#define FMC_BWTR1_ADDSET_3          (0x8U << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000008 */
+
+#define FMC_BWTR1_ADDHLD_Pos        (4U)                                       
+#define FMC_BWTR1_ADDHLD_Msk        (0xFU << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTR1_ADDHLD            FMC_BWTR1_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0          (0x1U << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000010 */
+#define FMC_BWTR1_ADDHLD_1          (0x2U << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000020 */
+#define FMC_BWTR1_ADDHLD_2          (0x4U << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000040 */
+#define FMC_BWTR1_ADDHLD_3          (0x8U << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000080 */
+
+#define FMC_BWTR1_DATAST_Pos        (8U)                                       
+#define FMC_BWTR1_DATAST_Msk        (0xFFU << FMC_BWTR1_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTR1_DATAST            FMC_BWTR1_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0          (0x01U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000100 */
+#define FMC_BWTR1_DATAST_1          (0x02U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000200 */
+#define FMC_BWTR1_DATAST_2          (0x04U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000400 */
+#define FMC_BWTR1_DATAST_3          (0x08U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000800 */
+#define FMC_BWTR1_DATAST_4          (0x10U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00001000 */
+#define FMC_BWTR1_DATAST_5          (0x20U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00002000 */
+#define FMC_BWTR1_DATAST_6          (0x40U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00004000 */
+#define FMC_BWTR1_DATAST_7          (0x80U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00008000 */
+
+#define FMC_BWTR1_CLKDIV_Pos        (20U)                                      
+#define FMC_BWTR1_CLKDIV_Msk        (0xFU << FMC_BWTR1_CLKDIV_Pos)             /*!< 0x00F00000 */
+#define FMC_BWTR1_CLKDIV            FMC_BWTR1_CLKDIV_Msk                       /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR1_CLKDIV_0          (0x1U << FMC_BWTR1_CLKDIV_Pos)             /*!< 0x00100000 */
+#define FMC_BWTR1_CLKDIV_1          (0x2U << FMC_BWTR1_CLKDIV_Pos)             /*!< 0x00200000 */
+#define FMC_BWTR1_CLKDIV_2          (0x4U << FMC_BWTR1_CLKDIV_Pos)             /*!< 0x00400000 */
+#define FMC_BWTR1_CLKDIV_3          (0x8U << FMC_BWTR1_CLKDIV_Pos)             /*!< 0x00800000 */
+
+#define FMC_BWTR1_DATLAT_Pos        (24U)                                      
+#define FMC_BWTR1_DATLAT_Msk        (0xFU << FMC_BWTR1_DATLAT_Pos)             /*!< 0x0F000000 */
+#define FMC_BWTR1_DATLAT            FMC_BWTR1_DATLAT_Msk                       /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR1_DATLAT_0          (0x1U << FMC_BWTR1_DATLAT_Pos)             /*!< 0x01000000 */
+#define FMC_BWTR1_DATLAT_1          (0x2U << FMC_BWTR1_DATLAT_Pos)             /*!< 0x02000000 */
+#define FMC_BWTR1_DATLAT_2          (0x4U << FMC_BWTR1_DATLAT_Pos)             /*!< 0x04000000 */
+#define FMC_BWTR1_DATLAT_3          (0x8U << FMC_BWTR1_DATLAT_Pos)             /*!< 0x08000000 */
+
+#define FMC_BWTR1_ACCMOD_Pos        (28U)                                      
+#define FMC_BWTR1_ACCMOD_Msk        (0x3U << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTR1_ACCMOD            FMC_BWTR1_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0          (0x1U << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x10000000 */
+#define FMC_BWTR1_ACCMOD_1          (0x2U << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTR2 register  ******************/
+#define FMC_BWTR2_ADDSET_Pos        (0U)                                       
+#define FMC_BWTR2_ADDSET_Msk        (0xFU << FMC_BWTR2_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTR2_ADDSET            FMC_BWTR2_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0          (0x1U << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000001 */
+#define FMC_BWTR2_ADDSET_1          (0x2U << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000002 */
+#define FMC_BWTR2_ADDSET_2          (0x4U << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000004 */
+#define FMC_BWTR2_ADDSET_3          (0x8U << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000008 */
+
+#define FMC_BWTR2_ADDHLD_Pos        (4U)                                       
+#define FMC_BWTR2_ADDHLD_Msk        (0xFU << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTR2_ADDHLD            FMC_BWTR2_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0          (0x1U << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000010 */
+#define FMC_BWTR2_ADDHLD_1          (0x2U << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000020 */
+#define FMC_BWTR2_ADDHLD_2          (0x4U << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000040 */
+#define FMC_BWTR2_ADDHLD_3          (0x8U << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000080 */
+
+#define FMC_BWTR2_DATAST_Pos        (8U)                                       
+#define FMC_BWTR2_DATAST_Msk        (0xFFU << FMC_BWTR2_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTR2_DATAST            FMC_BWTR2_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0          (0x01U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000100 */
+#define FMC_BWTR2_DATAST_1          (0x02U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000200 */
+#define FMC_BWTR2_DATAST_2          (0x04U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000400 */
+#define FMC_BWTR2_DATAST_3          (0x08U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000800 */
+#define FMC_BWTR2_DATAST_4          (0x10U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00001000 */
+#define FMC_BWTR2_DATAST_5          (0x20U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00002000 */
+#define FMC_BWTR2_DATAST_6          (0x40U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00004000 */
+#define FMC_BWTR2_DATAST_7          (0x80U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00008000 */
+
+#define FMC_BWTR2_CLKDIV_Pos        (20U)                                      
+#define FMC_BWTR2_CLKDIV_Msk        (0xFU << FMC_BWTR2_CLKDIV_Pos)             /*!< 0x00F00000 */
+#define FMC_BWTR2_CLKDIV            FMC_BWTR2_CLKDIV_Msk                       /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR2_CLKDIV_0          (0x1U << FMC_BWTR2_CLKDIV_Pos)             /*!< 0x00100000 */
+#define FMC_BWTR2_CLKDIV_1          (0x2U << FMC_BWTR2_CLKDIV_Pos)             /*!< 0x00200000 */
+#define FMC_BWTR2_CLKDIV_2          (0x4U << FMC_BWTR2_CLKDIV_Pos)             /*!< 0x00400000 */
+#define FMC_BWTR2_CLKDIV_3          (0x8U << FMC_BWTR2_CLKDIV_Pos)             /*!< 0x00800000 */
+
+#define FMC_BWTR2_DATLAT_Pos        (24U)                                      
+#define FMC_BWTR2_DATLAT_Msk        (0xFU << FMC_BWTR2_DATLAT_Pos)             /*!< 0x0F000000 */
+#define FMC_BWTR2_DATLAT            FMC_BWTR2_DATLAT_Msk                       /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR2_DATLAT_0          (0x1U << FMC_BWTR2_DATLAT_Pos)             /*!< 0x01000000 */
+#define FMC_BWTR2_DATLAT_1          (0x2U << FMC_BWTR2_DATLAT_Pos)             /*!< 0x02000000 */
+#define FMC_BWTR2_DATLAT_2          (0x4U << FMC_BWTR2_DATLAT_Pos)             /*!< 0x04000000 */
+#define FMC_BWTR2_DATLAT_3          (0x8U << FMC_BWTR2_DATLAT_Pos)             /*!< 0x08000000 */
+
+#define FMC_BWTR2_ACCMOD_Pos        (28U)                                      
+#define FMC_BWTR2_ACCMOD_Msk        (0x3U << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTR2_ACCMOD            FMC_BWTR2_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0          (0x1U << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x10000000 */
+#define FMC_BWTR2_ACCMOD_1          (0x2U << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTR3 register  ******************/
+#define FMC_BWTR3_ADDSET_Pos        (0U)                                       
+#define FMC_BWTR3_ADDSET_Msk        (0xFU << FMC_BWTR3_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTR3_ADDSET            FMC_BWTR3_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0          (0x1U << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000001 */
+#define FMC_BWTR3_ADDSET_1          (0x2U << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000002 */
+#define FMC_BWTR3_ADDSET_2          (0x4U << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000004 */
+#define FMC_BWTR3_ADDSET_3          (0x8U << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000008 */
+
+#define FMC_BWTR3_ADDHLD_Pos        (4U)                                       
+#define FMC_BWTR3_ADDHLD_Msk        (0xFU << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTR3_ADDHLD            FMC_BWTR3_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0          (0x1U << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000010 */
+#define FMC_BWTR3_ADDHLD_1          (0x2U << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000020 */
+#define FMC_BWTR3_ADDHLD_2          (0x4U << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000040 */
+#define FMC_BWTR3_ADDHLD_3          (0x8U << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000080 */
+
+#define FMC_BWTR3_DATAST_Pos        (8U)                                       
+#define FMC_BWTR3_DATAST_Msk        (0xFFU << FMC_BWTR3_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTR3_DATAST            FMC_BWTR3_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0          (0x01U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000100 */
+#define FMC_BWTR3_DATAST_1          (0x02U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000200 */
+#define FMC_BWTR3_DATAST_2          (0x04U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000400 */
+#define FMC_BWTR3_DATAST_3          (0x08U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000800 */
+#define FMC_BWTR3_DATAST_4          (0x10U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00001000 */
+#define FMC_BWTR3_DATAST_5          (0x20U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00002000 */
+#define FMC_BWTR3_DATAST_6          (0x40U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00004000 */
+#define FMC_BWTR3_DATAST_7          (0x80U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00008000 */
+
+#define FMC_BWTR3_CLKDIV_Pos        (20U)                                      
+#define FMC_BWTR3_CLKDIV_Msk        (0xFU << FMC_BWTR3_CLKDIV_Pos)             /*!< 0x00F00000 */
+#define FMC_BWTR3_CLKDIV            FMC_BWTR3_CLKDIV_Msk                       /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR3_CLKDIV_0          (0x1U << FMC_BWTR3_CLKDIV_Pos)             /*!< 0x00100000 */
+#define FMC_BWTR3_CLKDIV_1          (0x2U << FMC_BWTR3_CLKDIV_Pos)             /*!< 0x00200000 */
+#define FMC_BWTR3_CLKDIV_2          (0x4U << FMC_BWTR3_CLKDIV_Pos)             /*!< 0x00400000 */
+#define FMC_BWTR3_CLKDIV_3          (0x8U << FMC_BWTR3_CLKDIV_Pos)             /*!< 0x00800000 */
+
+#define FMC_BWTR3_DATLAT_Pos        (24U)                                      
+#define FMC_BWTR3_DATLAT_Msk        (0xFU << FMC_BWTR3_DATLAT_Pos)             /*!< 0x0F000000 */
+#define FMC_BWTR3_DATLAT            FMC_BWTR3_DATLAT_Msk                       /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR3_DATLAT_0          (0x1U << FMC_BWTR3_DATLAT_Pos)             /*!< 0x01000000 */
+#define FMC_BWTR3_DATLAT_1          (0x2U << FMC_BWTR3_DATLAT_Pos)             /*!< 0x02000000 */
+#define FMC_BWTR3_DATLAT_2          (0x4U << FMC_BWTR3_DATLAT_Pos)             /*!< 0x04000000 */
+#define FMC_BWTR3_DATLAT_3          (0x8U << FMC_BWTR3_DATLAT_Pos)             /*!< 0x08000000 */
+
+#define FMC_BWTR3_ACCMOD_Pos        (28U)                                      
+#define FMC_BWTR3_ACCMOD_Msk        (0x3U << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTR3_ACCMOD            FMC_BWTR3_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0          (0x1U << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x10000000 */
+#define FMC_BWTR3_ACCMOD_1          (0x2U << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTR4 register  ******************/
+#define FMC_BWTR4_ADDSET_Pos        (0U)                                       
+#define FMC_BWTR4_ADDSET_Msk        (0xFU << FMC_BWTR4_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTR4_ADDSET            FMC_BWTR4_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0          (0x1U << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000001 */
+#define FMC_BWTR4_ADDSET_1          (0x2U << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000002 */
+#define FMC_BWTR4_ADDSET_2          (0x4U << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000004 */
+#define FMC_BWTR4_ADDSET_3          (0x8U << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000008 */
+
+#define FMC_BWTR4_ADDHLD_Pos        (4U)                                       
+#define FMC_BWTR4_ADDHLD_Msk        (0xFU << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTR4_ADDHLD            FMC_BWTR4_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0          (0x1U << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000010 */
+#define FMC_BWTR4_ADDHLD_1          (0x2U << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000020 */
+#define FMC_BWTR4_ADDHLD_2          (0x4U << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000040 */
+#define FMC_BWTR4_ADDHLD_3          (0x8U << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000080 */
+
+#define FMC_BWTR4_DATAST_Pos        (8U)                                       
+#define FMC_BWTR4_DATAST_Msk        (0xFFU << FMC_BWTR4_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTR4_DATAST            FMC_BWTR4_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0          (0x01U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000100 */
+#define FMC_BWTR4_DATAST_1          (0x02U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000200 */
+#define FMC_BWTR4_DATAST_2          (0x04U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000400 */
+#define FMC_BWTR4_DATAST_3          (0x08U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000800 */
+#define FMC_BWTR4_DATAST_4          (0x10U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00001000 */
+#define FMC_BWTR4_DATAST_5          (0x20U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00002000 */
+#define FMC_BWTR4_DATAST_6          (0x40U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00004000 */
+#define FMC_BWTR4_DATAST_7          (0x80U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00008000 */
+
+#define FMC_BWTR4_CLKDIV_Pos        (20U)                                      
+#define FMC_BWTR4_CLKDIV_Msk        (0xFU << FMC_BWTR4_CLKDIV_Pos)             /*!< 0x00F00000 */
+#define FMC_BWTR4_CLKDIV            FMC_BWTR4_CLKDIV_Msk                       /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR4_CLKDIV_0          (0x1U << FMC_BWTR4_CLKDIV_Pos)             /*!< 0x00100000 */
+#define FMC_BWTR4_CLKDIV_1          (0x2U << FMC_BWTR4_CLKDIV_Pos)             /*!< 0x00200000 */
+#define FMC_BWTR4_CLKDIV_2          (0x4U << FMC_BWTR4_CLKDIV_Pos)             /*!< 0x00400000 */
+#define FMC_BWTR4_CLKDIV_3          (0x8U << FMC_BWTR4_CLKDIV_Pos)             /*!< 0x00800000 */
+
+#define FMC_BWTR4_DATLAT_Pos        (24U)                                      
+#define FMC_BWTR4_DATLAT_Msk        (0xFU << FMC_BWTR4_DATLAT_Pos)             /*!< 0x0F000000 */
+#define FMC_BWTR4_DATLAT            FMC_BWTR4_DATLAT_Msk                       /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR4_DATLAT_0          (0x1U << FMC_BWTR4_DATLAT_Pos)             /*!< 0x01000000 */
+#define FMC_BWTR4_DATLAT_1          (0x2U << FMC_BWTR4_DATLAT_Pos)             /*!< 0x02000000 */
+#define FMC_BWTR4_DATLAT_2          (0x4U << FMC_BWTR4_DATLAT_Pos)             /*!< 0x04000000 */
+#define FMC_BWTR4_DATLAT_3          (0x8U << FMC_BWTR4_DATLAT_Pos)             /*!< 0x08000000 */
+
+#define FMC_BWTR4_ACCMOD_Pos        (28U)                                      
+#define FMC_BWTR4_ACCMOD_Msk        (0x3U << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTR4_ACCMOD            FMC_BWTR4_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0          (0x1U << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x10000000 */
+#define FMC_BWTR4_ACCMOD_1          (0x2U << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_PCRx register  *******************/
+#define FMC_PCRx_PWAITEN_Pos        (1U)                                       
+#define FMC_PCRx_PWAITEN_Msk        (0x1U << FMC_PCRx_PWAITEN_Pos)             /*!< 0x00000002 */
+#define FMC_PCRx_PWAITEN            FMC_PCRx_PWAITEN_Msk                       /*!<Wait feature enable bit                   */
+#define FMC_PCRx_PBKEN_Pos          (2U)                                       
+#define FMC_PCRx_PBKEN_Msk          (0x1U << FMC_PCRx_PBKEN_Pos)               /*!< 0x00000004 */
+#define FMC_PCRx_PBKEN              FMC_PCRx_PBKEN_Msk                         /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCRx_PTYP_Pos           (3U)                                       
+#define FMC_PCRx_PTYP_Msk           (0x1U << FMC_PCRx_PTYP_Pos)                /*!< 0x00000008 */
+#define FMC_PCRx_PTYP               FMC_PCRx_PTYP_Msk                          /*!<Memory type                               */
+
+#define FMC_PCRx_PWID_Pos           (4U)                                       
+#define FMC_PCRx_PWID_Msk           (0x3U << FMC_PCRx_PWID_Pos)                /*!< 0x00000030 */
+#define FMC_PCRx_PWID               FMC_PCRx_PWID_Msk                          /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCRx_PWID_0             (0x1U << FMC_PCRx_PWID_Pos)                /*!< 0x00000010 */
+#define FMC_PCRx_PWID_1             (0x2U << FMC_PCRx_PWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_PCRx_ECCEN_Pos          (6U)                                       
+#define FMC_PCRx_ECCEN_Msk          (0x1U << FMC_PCRx_ECCEN_Pos)               /*!< 0x00000040 */
+#define FMC_PCRx_ECCEN              FMC_PCRx_ECCEN_Msk                         /*!<ECC computation logic enable bit          */
+
+#define FMC_PCRx_TCLR_Pos           (9U)                                       
+#define FMC_PCRx_TCLR_Msk           (0xFU << FMC_PCRx_TCLR_Pos)                /*!< 0x00001E00 */
+#define FMC_PCRx_TCLR               FMC_PCRx_TCLR_Msk                          /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define FMC_PCRx_TCLR_0             (0x1U << FMC_PCRx_TCLR_Pos)                /*!< 0x00000200 */
+#define FMC_PCRx_TCLR_1             (0x2U << FMC_PCRx_TCLR_Pos)                /*!< 0x00000400 */
+#define FMC_PCRx_TCLR_2             (0x4U << FMC_PCRx_TCLR_Pos)                /*!< 0x00000800 */
+#define FMC_PCRx_TCLR_3             (0x8U << FMC_PCRx_TCLR_Pos)                /*!< 0x00001000 */
+
+#define FMC_PCRx_TAR_Pos            (13U)                                      
+#define FMC_PCRx_TAR_Msk            (0xFU << FMC_PCRx_TAR_Pos)                 /*!< 0x0001E000 */
+#define FMC_PCRx_TAR                FMC_PCRx_TAR_Msk                           /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define FMC_PCRx_TAR_0              (0x1U << FMC_PCRx_TAR_Pos)                 /*!< 0x00002000 */
+#define FMC_PCRx_TAR_1              (0x2U << FMC_PCRx_TAR_Pos)                 /*!< 0x00004000 */
+#define FMC_PCRx_TAR_2              (0x4U << FMC_PCRx_TAR_Pos)                 /*!< 0x00008000 */
+#define FMC_PCRx_TAR_3              (0x8U << FMC_PCRx_TAR_Pos)                 /*!< 0x00010000 */
+
+#define FMC_PCRx_ECCPS_Pos          (17U)                                      
+#define FMC_PCRx_ECCPS_Msk          (0x7U << FMC_PCRx_ECCPS_Pos)               /*!< 0x000E0000 */
+#define FMC_PCRx_ECCPS              FMC_PCRx_ECCPS_Msk                         /*!<ECCPS[1:0] bits (ECC page size)           */
+#define FMC_PCRx_ECCPS_0            (0x1U << FMC_PCRx_ECCPS_Pos)               /*!< 0x00020000 */
+#define FMC_PCRx_ECCPS_1            (0x2U << FMC_PCRx_ECCPS_Pos)               /*!< 0x00040000 */
+#define FMC_PCRx_ECCPS_2            (0x4U << FMC_PCRx_ECCPS_Pos)               /*!< 0x00080000 */
+
+/******************  Bit definition for FMC_PCR2 register  *******************/
+#define FMC_PCR2_PWAITEN_Pos        (1U)                                       
+#define FMC_PCR2_PWAITEN_Msk        (0x1U << FMC_PCR2_PWAITEN_Pos)             /*!< 0x00000002 */
+#define FMC_PCR2_PWAITEN            FMC_PCR2_PWAITEN_Msk                       /*!<Wait feature enable bit                   */
+#define FMC_PCR2_PBKEN_Pos          (2U)                                       
+#define FMC_PCR2_PBKEN_Msk          (0x1U << FMC_PCR2_PBKEN_Pos)               /*!< 0x00000004 */
+#define FMC_PCR2_PBKEN              FMC_PCR2_PBKEN_Msk                         /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR2_PTYP_Pos           (3U)                                       
+#define FMC_PCR2_PTYP_Msk           (0x1U << FMC_PCR2_PTYP_Pos)                /*!< 0x00000008 */
+#define FMC_PCR2_PTYP               FMC_PCR2_PTYP_Msk                          /*!<Memory type                               */
+
+#define FMC_PCR2_PWID_Pos           (4U)                                       
+#define FMC_PCR2_PWID_Msk           (0x3U << FMC_PCR2_PWID_Pos)                /*!< 0x00000030 */
+#define FMC_PCR2_PWID               FMC_PCR2_PWID_Msk                          /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR2_PWID_0             (0x1U << FMC_PCR2_PWID_Pos)                /*!< 0x00000010 */
+#define FMC_PCR2_PWID_1             (0x2U << FMC_PCR2_PWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_PCR2_ECCEN_Pos          (6U)                                       
+#define FMC_PCR2_ECCEN_Msk          (0x1U << FMC_PCR2_ECCEN_Pos)               /*!< 0x00000040 */
+#define FMC_PCR2_ECCEN              FMC_PCR2_ECCEN_Msk                         /*!<ECC computation logic enable bit          */
+
+#define FMC_PCR2_TCLR_Pos           (9U)                                       
+#define FMC_PCR2_TCLR_Msk           (0xFU << FMC_PCR2_TCLR_Pos)                /*!< 0x00001E00 */
+#define FMC_PCR2_TCLR               FMC_PCR2_TCLR_Msk                          /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define FMC_PCR2_TCLR_0             (0x1U << FMC_PCR2_TCLR_Pos)                /*!< 0x00000200 */
+#define FMC_PCR2_TCLR_1             (0x2U << FMC_PCR2_TCLR_Pos)                /*!< 0x00000400 */
+#define FMC_PCR2_TCLR_2             (0x4U << FMC_PCR2_TCLR_Pos)                /*!< 0x00000800 */
+#define FMC_PCR2_TCLR_3             (0x8U << FMC_PCR2_TCLR_Pos)                /*!< 0x00001000 */
+
+#define FMC_PCR2_TAR_Pos            (13U)                                      
+#define FMC_PCR2_TAR_Msk            (0xFU << FMC_PCR2_TAR_Pos)                 /*!< 0x0001E000 */
+#define FMC_PCR2_TAR                FMC_PCR2_TAR_Msk                           /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define FMC_PCR2_TAR_0              (0x1U << FMC_PCR2_TAR_Pos)                 /*!< 0x00002000 */
+#define FMC_PCR2_TAR_1              (0x2U << FMC_PCR2_TAR_Pos)                 /*!< 0x00004000 */
+#define FMC_PCR2_TAR_2              (0x4U << FMC_PCR2_TAR_Pos)                 /*!< 0x00008000 */
+#define FMC_PCR2_TAR_3              (0x8U << FMC_PCR2_TAR_Pos)                 /*!< 0x00010000 */
+
+#define FMC_PCR2_ECCPS_Pos          (17U)                                      
+#define FMC_PCR2_ECCPS_Msk          (0x7U << FMC_PCR2_ECCPS_Pos)               /*!< 0x000E0000 */
+#define FMC_PCR2_ECCPS              FMC_PCR2_ECCPS_Msk                         /*!<ECCPS[1:0] bits (ECC page size)           */
+#define FMC_PCR2_ECCPS_0            (0x1U << FMC_PCR2_ECCPS_Pos)               /*!< 0x00020000 */
+#define FMC_PCR2_ECCPS_1            (0x2U << FMC_PCR2_ECCPS_Pos)               /*!< 0x00040000 */
+#define FMC_PCR2_ECCPS_2            (0x4U << FMC_PCR2_ECCPS_Pos)               /*!< 0x00080000 */
+
+/******************  Bit definition for FMC_PCR3 register  *******************/
+#define FMC_PCR3_PWAITEN_Pos        (1U)                                       
+#define FMC_PCR3_PWAITEN_Msk        (0x1U << FMC_PCR3_PWAITEN_Pos)             /*!< 0x00000002 */
+#define FMC_PCR3_PWAITEN            FMC_PCR3_PWAITEN_Msk                       /*!<Wait feature enable bit                   */
+#define FMC_PCR3_PBKEN_Pos          (2U)                                       
+#define FMC_PCR3_PBKEN_Msk          (0x1U << FMC_PCR3_PBKEN_Pos)               /*!< 0x00000004 */
+#define FMC_PCR3_PBKEN              FMC_PCR3_PBKEN_Msk                         /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR3_PTYP_Pos           (3U)                                       
+#define FMC_PCR3_PTYP_Msk           (0x1U << FMC_PCR3_PTYP_Pos)                /*!< 0x00000008 */
+#define FMC_PCR3_PTYP               FMC_PCR3_PTYP_Msk                          /*!<Memory type                               */
+
+#define FMC_PCR3_PWID_Pos           (4U)                                       
+#define FMC_PCR3_PWID_Msk           (0x3U << FMC_PCR3_PWID_Pos)                /*!< 0x00000030 */
+#define FMC_PCR3_PWID               FMC_PCR3_PWID_Msk                          /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR3_PWID_0             (0x1U << FMC_PCR3_PWID_Pos)                /*!< 0x00000010 */
+#define FMC_PCR3_PWID_1             (0x2U << FMC_PCR3_PWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_PCR3_ECCEN_Pos          (6U)                                       
+#define FMC_PCR3_ECCEN_Msk          (0x1U << FMC_PCR3_ECCEN_Pos)               /*!< 0x00000040 */
+#define FMC_PCR3_ECCEN              FMC_PCR3_ECCEN_Msk                         /*!<ECC computation logic enable bit          */
+
+#define FMC_PCR3_TCLR_Pos           (9U)                                       
+#define FMC_PCR3_TCLR_Msk           (0xFU << FMC_PCR3_TCLR_Pos)                /*!< 0x00001E00 */
+#define FMC_PCR3_TCLR               FMC_PCR3_TCLR_Msk                          /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define FMC_PCR3_TCLR_0             (0x1U << FMC_PCR3_TCLR_Pos)                /*!< 0x00000200 */
+#define FMC_PCR3_TCLR_1             (0x2U << FMC_PCR3_TCLR_Pos)                /*!< 0x00000400 */
+#define FMC_PCR3_TCLR_2             (0x4U << FMC_PCR3_TCLR_Pos)                /*!< 0x00000800 */
+#define FMC_PCR3_TCLR_3             (0x8U << FMC_PCR3_TCLR_Pos)                /*!< 0x00001000 */
+
+#define FMC_PCR3_TAR_Pos            (13U)                                      
+#define FMC_PCR3_TAR_Msk            (0xFU << FMC_PCR3_TAR_Pos)                 /*!< 0x0001E000 */
+#define FMC_PCR3_TAR                FMC_PCR3_TAR_Msk                           /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define FMC_PCR3_TAR_0              (0x1U << FMC_PCR3_TAR_Pos)                 /*!< 0x00002000 */
+#define FMC_PCR3_TAR_1              (0x2U << FMC_PCR3_TAR_Pos)                 /*!< 0x00004000 */
+#define FMC_PCR3_TAR_2              (0x4U << FMC_PCR3_TAR_Pos)                 /*!< 0x00008000 */
+#define FMC_PCR3_TAR_3              (0x8U << FMC_PCR3_TAR_Pos)                 /*!< 0x00010000 */
+
+#define FMC_PCR3_ECCPS_Pos          (17U)                                      
+#define FMC_PCR3_ECCPS_Msk          (0x7U << FMC_PCR3_ECCPS_Pos)               /*!< 0x000E0000 */
+#define FMC_PCR3_ECCPS              FMC_PCR3_ECCPS_Msk                         /*!<ECCPS[2:0] bits (ECC page size)           */
+#define FMC_PCR3_ECCPS_0            (0x1U << FMC_PCR3_ECCPS_Pos)               /*!< 0x00020000 */
+#define FMC_PCR3_ECCPS_1            (0x2U << FMC_PCR3_ECCPS_Pos)               /*!< 0x00040000 */
+#define FMC_PCR3_ECCPS_2            (0x4U << FMC_PCR3_ECCPS_Pos)               /*!< 0x00080000 */
+
+/******************  Bit definition for FMC_PCR4 register  *******************/
+#define FMC_PCR4_PWAITEN_Pos        (1U)                                       
+#define FMC_PCR4_PWAITEN_Msk        (0x1U << FMC_PCR4_PWAITEN_Pos)             /*!< 0x00000002 */
+#define FMC_PCR4_PWAITEN            FMC_PCR4_PWAITEN_Msk                       /*!<Wait feature enable bit                   */
+#define FMC_PCR4_PBKEN_Pos          (2U)                                       
+#define FMC_PCR4_PBKEN_Msk          (0x1U << FMC_PCR4_PBKEN_Pos)               /*!< 0x00000004 */
+#define FMC_PCR4_PBKEN              FMC_PCR4_PBKEN_Msk                         /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR4_PTYP_Pos           (3U)                                       
+#define FMC_PCR4_PTYP_Msk           (0x1U << FMC_PCR4_PTYP_Pos)                /*!< 0x00000008 */
+#define FMC_PCR4_PTYP               FMC_PCR4_PTYP_Msk                          /*!<Memory type                               */
+
+#define FMC_PCR4_PWID_Pos           (4U)                                       
+#define FMC_PCR4_PWID_Msk           (0x3U << FMC_PCR4_PWID_Pos)                /*!< 0x00000030 */
+#define FMC_PCR4_PWID               FMC_PCR4_PWID_Msk                          /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR4_PWID_0             (0x1U << FMC_PCR4_PWID_Pos)                /*!< 0x00000010 */
+#define FMC_PCR4_PWID_1             (0x2U << FMC_PCR4_PWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_PCR4_ECCEN_Pos          (6U)                                       
+#define FMC_PCR4_ECCEN_Msk          (0x1U << FMC_PCR4_ECCEN_Pos)               /*!< 0x00000040 */
+#define FMC_PCR4_ECCEN              FMC_PCR4_ECCEN_Msk                         /*!<ECC computation logic enable bit          */
+
+#define FMC_PCR4_TCLR_Pos           (9U)                                       
+#define FMC_PCR4_TCLR_Msk           (0xFU << FMC_PCR4_TCLR_Pos)                /*!< 0x00001E00 */
+#define FMC_PCR4_TCLR               FMC_PCR4_TCLR_Msk                          /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define FMC_PCR4_TCLR_0             (0x1U << FMC_PCR4_TCLR_Pos)                /*!< 0x00000200 */
+#define FMC_PCR4_TCLR_1             (0x2U << FMC_PCR4_TCLR_Pos)                /*!< 0x00000400 */
+#define FMC_PCR4_TCLR_2             (0x4U << FMC_PCR4_TCLR_Pos)                /*!< 0x00000800 */
+#define FMC_PCR4_TCLR_3             (0x8U << FMC_PCR4_TCLR_Pos)                /*!< 0x00001000 */
+
+#define FMC_PCR4_TAR_Pos            (13U)                                      
+#define FMC_PCR4_TAR_Msk            (0xFU << FMC_PCR4_TAR_Pos)                 /*!< 0x0001E000 */
+#define FMC_PCR4_TAR                FMC_PCR4_TAR_Msk                           /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define FMC_PCR4_TAR_0              (0x1U << FMC_PCR4_TAR_Pos)                 /*!< 0x00002000 */
+#define FMC_PCR4_TAR_1              (0x2U << FMC_PCR4_TAR_Pos)                 /*!< 0x00004000 */
+#define FMC_PCR4_TAR_2              (0x4U << FMC_PCR4_TAR_Pos)                 /*!< 0x00008000 */
+#define FMC_PCR4_TAR_3              (0x8U << FMC_PCR4_TAR_Pos)                 /*!< 0x00010000 */
+
+#define FMC_PCR4_ECCPS_Pos          (17U)                                      
+#define FMC_PCR4_ECCPS_Msk          (0x7U << FMC_PCR4_ECCPS_Pos)               /*!< 0x000E0000 */
+#define FMC_PCR4_ECCPS              FMC_PCR4_ECCPS_Msk                         /*!<ECCPS[2:0] bits (ECC page size)           */
+#define FMC_PCR4_ECCPS_0            (0x1U << FMC_PCR4_ECCPS_Pos)               /*!< 0x00020000 */
+#define FMC_PCR4_ECCPS_1            (0x2U << FMC_PCR4_ECCPS_Pos)               /*!< 0x00040000 */
+#define FMC_PCR4_ECCPS_2            (0x4U << FMC_PCR4_ECCPS_Pos)               /*!< 0x00080000 */
+
+/*******************  Bit definition for FMC_SRx register  *******************/
+#define FMC_SRx_IRS_Pos             (0U)                                       
+#define FMC_SRx_IRS_Msk             (0x1U << FMC_SRx_IRS_Pos)                  /*!< 0x00000001 */
+#define FMC_SRx_IRS                 FMC_SRx_IRS_Msk                            /*!<Interrupt Rising Edge status                */
+#define FMC_SRx_ILS_Pos             (1U)                                       
+#define FMC_SRx_ILS_Msk             (0x1U << FMC_SRx_ILS_Pos)                  /*!< 0x00000002 */
+#define FMC_SRx_ILS                 FMC_SRx_ILS_Msk                            /*!<Interrupt Level status                      */
+#define FMC_SRx_IFS_Pos             (2U)                                       
+#define FMC_SRx_IFS_Msk             (0x1U << FMC_SRx_IFS_Pos)                  /*!< 0x00000004 */
+#define FMC_SRx_IFS                 FMC_SRx_IFS_Msk                            /*!<Interrupt Falling Edge status               */
+#define FMC_SRx_IREN_Pos            (3U)                                       
+#define FMC_SRx_IREN_Msk            (0x1U << FMC_SRx_IREN_Pos)                 /*!< 0x00000008 */
+#define FMC_SRx_IREN                FMC_SRx_IREN_Msk                           /*!<Interrupt Rising Edge detection Enable bit  */
+#define FMC_SRx_ILEN_Pos            (4U)                                       
+#define FMC_SRx_ILEN_Msk            (0x1U << FMC_SRx_ILEN_Pos)                 /*!< 0x00000010 */
+#define FMC_SRx_ILEN                FMC_SRx_ILEN_Msk                           /*!<Interrupt Level detection Enable bit        */
+#define FMC_SRx_IFEN_Pos            (5U)                                       
+#define FMC_SRx_IFEN_Msk            (0x1U << FMC_SRx_IFEN_Pos)                 /*!< 0x00000020 */
+#define FMC_SRx_IFEN                FMC_SRx_IFEN_Msk                           /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SRx_FEMPT_Pos           (6U)                                       
+#define FMC_SRx_FEMPT_Msk           (0x1U << FMC_SRx_FEMPT_Pos)                /*!< 0x00000040 */
+#define FMC_SRx_FEMPT               FMC_SRx_FEMPT_Msk                          /*!<FIFO empty                                  */
+
+/*******************  Bit definition for FMC_SR2 register  *******************/
+#define FMC_SR2_IRS_Pos             (0U)                                       
+#define FMC_SR2_IRS_Msk             (0x1U << FMC_SR2_IRS_Pos)                  /*!< 0x00000001 */
+#define FMC_SR2_IRS                 FMC_SR2_IRS_Msk                            /*!<Interrupt Rising Edge status                */
+#define FMC_SR2_ILS_Pos             (1U)                                       
+#define FMC_SR2_ILS_Msk             (0x1U << FMC_SR2_ILS_Pos)                  /*!< 0x00000002 */
+#define FMC_SR2_ILS                 FMC_SR2_ILS_Msk                            /*!<Interrupt Level status                      */
+#define FMC_SR2_IFS_Pos             (2U)                                       
+#define FMC_SR2_IFS_Msk             (0x1U << FMC_SR2_IFS_Pos)                  /*!< 0x00000004 */
+#define FMC_SR2_IFS                 FMC_SR2_IFS_Msk                            /*!<Interrupt Falling Edge status               */
+#define FMC_SR2_IREN_Pos            (3U)                                       
+#define FMC_SR2_IREN_Msk            (0x1U << FMC_SR2_IREN_Pos)                 /*!< 0x00000008 */
+#define FMC_SR2_IREN                FMC_SR2_IREN_Msk                           /*!<Interrupt Rising Edge detection Enable bit  */
+#define FMC_SR2_ILEN_Pos            (4U)                                       
+#define FMC_SR2_ILEN_Msk            (0x1U << FMC_SR2_ILEN_Pos)                 /*!< 0x00000010 */
+#define FMC_SR2_ILEN                FMC_SR2_ILEN_Msk                           /*!<Interrupt Level detection Enable bit        */
+#define FMC_SR2_IFEN_Pos            (5U)                                       
+#define FMC_SR2_IFEN_Msk            (0x1U << FMC_SR2_IFEN_Pos)                 /*!< 0x00000020 */
+#define FMC_SR2_IFEN                FMC_SR2_IFEN_Msk                           /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR2_FEMPT_Pos           (6U)                                       
+#define FMC_SR2_FEMPT_Msk           (0x1U << FMC_SR2_FEMPT_Pos)                /*!< 0x00000040 */
+#define FMC_SR2_FEMPT               FMC_SR2_FEMPT_Msk                          /*!<FIFO empty                                  */
+
+/*******************  Bit definition for FMC_SR3 register  *******************/
+#define FMC_SR3_IRS_Pos             (0U)                                       
+#define FMC_SR3_IRS_Msk             (0x1U << FMC_SR3_IRS_Pos)                  /*!< 0x00000001 */
+#define FMC_SR3_IRS                 FMC_SR3_IRS_Msk                            /*!<Interrupt Rising Edge status                */
+#define FMC_SR3_ILS_Pos             (1U)                                       
+#define FMC_SR3_ILS_Msk             (0x1U << FMC_SR3_ILS_Pos)                  /*!< 0x00000002 */
+#define FMC_SR3_ILS                 FMC_SR3_ILS_Msk                            /*!<Interrupt Level status                      */
+#define FMC_SR3_IFS_Pos             (2U)                                       
+#define FMC_SR3_IFS_Msk             (0x1U << FMC_SR3_IFS_Pos)                  /*!< 0x00000004 */
+#define FMC_SR3_IFS                 FMC_SR3_IFS_Msk                            /*!<Interrupt Falling Edge status               */
+#define FMC_SR3_IREN_Pos            (3U)                                       
+#define FMC_SR3_IREN_Msk            (0x1U << FMC_SR3_IREN_Pos)                 /*!< 0x00000008 */
+#define FMC_SR3_IREN                FMC_SR3_IREN_Msk                           /*!<Interrupt Rising Edge detection Enable bit  */
+#define FMC_SR3_ILEN_Pos            (4U)                                       
+#define FMC_SR3_ILEN_Msk            (0x1U << FMC_SR3_ILEN_Pos)                 /*!< 0x00000010 */
+#define FMC_SR3_ILEN                FMC_SR3_ILEN_Msk                           /*!<Interrupt Level detection Enable bit        */
+#define FMC_SR3_IFEN_Pos            (5U)                                       
+#define FMC_SR3_IFEN_Msk            (0x1U << FMC_SR3_IFEN_Pos)                 /*!< 0x00000020 */
+#define FMC_SR3_IFEN                FMC_SR3_IFEN_Msk                           /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR3_FEMPT_Pos           (6U)                                       
+#define FMC_SR3_FEMPT_Msk           (0x1U << FMC_SR3_FEMPT_Pos)                /*!< 0x00000040 */
+#define FMC_SR3_FEMPT               FMC_SR3_FEMPT_Msk                          /*!<FIFO empty                                  */
+
+/*******************  Bit definition for FMC_SR4 register  *******************/
+#define FMC_SR4_IRS_Pos             (0U)                                       
+#define FMC_SR4_IRS_Msk             (0x1U << FMC_SR4_IRS_Pos)                  /*!< 0x00000001 */
+#define FMC_SR4_IRS                 FMC_SR4_IRS_Msk                            /*!<Interrupt Rising Edge status                */
+#define FMC_SR4_ILS_Pos             (1U)                                       
+#define FMC_SR4_ILS_Msk             (0x1U << FMC_SR4_ILS_Pos)                  /*!< 0x00000002 */
+#define FMC_SR4_ILS                 FMC_SR4_ILS_Msk                            /*!<Interrupt Level status                      */
+#define FMC_SR4_IFS_Pos             (2U)                                       
+#define FMC_SR4_IFS_Msk             (0x1U << FMC_SR4_IFS_Pos)                  /*!< 0x00000004 */
+#define FMC_SR4_IFS                 FMC_SR4_IFS_Msk                            /*!<Interrupt Falling Edge status               */
+#define FMC_SR4_IREN_Pos            (3U)                                       
+#define FMC_SR4_IREN_Msk            (0x1U << FMC_SR4_IREN_Pos)                 /*!< 0x00000008 */
+#define FMC_SR4_IREN                FMC_SR4_IREN_Msk                           /*!<Interrupt Rising Edge detection Enable bit  */
+#define FMC_SR4_ILEN_Pos            (4U)                                       
+#define FMC_SR4_ILEN_Msk            (0x1U << FMC_SR4_ILEN_Pos)                 /*!< 0x00000010 */
+#define FMC_SR4_ILEN                FMC_SR4_ILEN_Msk                           /*!<Interrupt Level detection Enable bit        */
+#define FMC_SR4_IFEN_Pos            (5U)                                       
+#define FMC_SR4_IFEN_Msk            (0x1U << FMC_SR4_IFEN_Pos)                 /*!< 0x00000020 */
+#define FMC_SR4_IFEN                FMC_SR4_IFEN_Msk                           /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR4_FEMPT_Pos           (6U)                                       
+#define FMC_SR4_FEMPT_Msk           (0x1U << FMC_SR4_FEMPT_Pos)                /*!< 0x00000040 */
+#define FMC_SR4_FEMPT               FMC_SR4_FEMPT_Msk                          /*!<FIFO empty                                  */
+
+/******************  Bit definition for FMC_PMEMx register  ******************/
+#define FMC_PMEMx_MEMSETx_Pos       (0U)                                       
+#define FMC_PMEMx_MEMSETx_Msk       (0xFFU << FMC_PMEMx_MEMSETx_Pos)           /*!< 0x000000FF */
+#define FMC_PMEMx_MEMSETx           FMC_PMEMx_MEMSETx_Msk                      /*!<MEMSETx[7:0] bits (Common memory x setup time) */
+#define FMC_PMEMx_MEMSETx_0         (0x01U << FMC_PMEMx_MEMSETx_Pos)           /*!< 0x00000001 */
+#define FMC_PMEMx_MEMSETx_1         (0x02U << FMC_PMEMx_MEMSETx_Pos)           /*!< 0x00000002 */
+#define FMC_PMEMx_MEMSETx_2         (0x04U << FMC_PMEMx_MEMSETx_Pos)           /*!< 0x00000004 */
+#define FMC_PMEMx_MEMSETx_3         (0x08U << FMC_PMEMx_MEMSETx_Pos)           /*!< 0x00000008 */
+#define FMC_PMEMx_MEMSETx_4         (0x10U << FMC_PMEMx_MEMSETx_Pos)           /*!< 0x00000010 */
+#define FMC_PMEMx_MEMSETx_5         (0x20U << FMC_PMEMx_MEMSETx_Pos)           /*!< 0x00000020 */
+#define FMC_PMEMx_MEMSETx_6         (0x40U << FMC_PMEMx_MEMSETx_Pos)           /*!< 0x00000040 */
+#define FMC_PMEMx_MEMSETx_7         (0x80U << FMC_PMEMx_MEMSETx_Pos)           /*!< 0x00000080 */
+
+#define FMC_PMEMx_MEMWAITx_Pos      (8U)                                       
+#define FMC_PMEMx_MEMWAITx_Msk      (0xFFU << FMC_PMEMx_MEMWAITx_Pos)          /*!< 0x0000FF00 */
+#define FMC_PMEMx_MEMWAITx          FMC_PMEMx_MEMWAITx_Msk                     /*!<MEMWAITx[7:0] bits (Common memory x wait time) */
+#define FMC_PMEMx_MEMWAITx_0        (0x01U << FMC_PMEMx_MEMWAITx_Pos)          /*!< 0x00000100 */
+#define FMC_PMEMx_MEMWAITx_1        (0x02U << FMC_PMEMx_MEMWAITx_Pos)          /*!< 0x00000200 */
+#define FMC_PMEMx_MEMWAITx_2        (0x04U << FMC_PMEMx_MEMWAITx_Pos)          /*!< 0x00000400 */
+#define FMC_PMEMx_MEMWAITx_3        (0x08U << FMC_PMEMx_MEMWAITx_Pos)          /*!< 0x00000800 */
+#define FMC_PMEMx_MEMWAITx_4        (0x10U << FMC_PMEMx_MEMWAITx_Pos)          /*!< 0x00001000 */
+#define FMC_PMEMx_MEMWAITx_5        (0x20U << FMC_PMEMx_MEMWAITx_Pos)          /*!< 0x00002000 */
+#define FMC_PMEMx_MEMWAITx_6        (0x40U << FMC_PMEMx_MEMWAITx_Pos)          /*!< 0x00004000 */
+#define FMC_PMEMx_MEMWAITx_7        (0x80U << FMC_PMEMx_MEMWAITx_Pos)          /*!< 0x00008000 */
+
+#define FMC_PMEMx_MEMHOLDx_Pos      (16U)                                      
+#define FMC_PMEMx_MEMHOLDx_Msk      (0xFFU << FMC_PMEMx_MEMHOLDx_Pos)          /*!< 0x00FF0000 */
+#define FMC_PMEMx_MEMHOLDx          FMC_PMEMx_MEMHOLDx_Msk                     /*!<MEMHOLDx[7:0] bits (Common memory x hold time) */
+#define FMC_PMEMx_MEMHOLDx_0        (0x01U << FMC_PMEMx_MEMHOLDx_Pos)          /*!< 0x00010000 */
+#define FMC_PMEMx_MEMHOLDx_1        (0x02U << FMC_PMEMx_MEMHOLDx_Pos)          /*!< 0x00020000 */
+#define FMC_PMEMx_MEMHOLDx_2        (0x04U << FMC_PMEMx_MEMHOLDx_Pos)          /*!< 0x00040000 */
+#define FMC_PMEMx_MEMHOLDx_3        (0x08U << FMC_PMEMx_MEMHOLDx_Pos)          /*!< 0x00080000 */
+#define FMC_PMEMx_MEMHOLDx_4        (0x10U << FMC_PMEMx_MEMHOLDx_Pos)          /*!< 0x00100000 */
+#define FMC_PMEMx_MEMHOLDx_5        (0x20U << FMC_PMEMx_MEMHOLDx_Pos)          /*!< 0x00200000 */
+#define FMC_PMEMx_MEMHOLDx_6        (0x40U << FMC_PMEMx_MEMHOLDx_Pos)          /*!< 0x00400000 */
+#define FMC_PMEMx_MEMHOLDx_7        (0x80U << FMC_PMEMx_MEMHOLDx_Pos)          /*!< 0x00800000 */
+
+#define FMC_PMEMx_MEMHIZx_Pos       (24U)                                      
+#define FMC_PMEMx_MEMHIZx_Msk       (0xFFU << FMC_PMEMx_MEMHIZx_Pos)           /*!< 0xFF000000 */
+#define FMC_PMEMx_MEMHIZx           FMC_PMEMx_MEMHIZx_Msk                      /*!<MEMHIZx[7:0] bits (Common memory x databus HiZ time) */
+#define FMC_PMEMx_MEMHIZx_0         (0x01U << FMC_PMEMx_MEMHIZx_Pos)           /*!< 0x01000000 */
+#define FMC_PMEMx_MEMHIZx_1         (0x02U << FMC_PMEMx_MEMHIZx_Pos)           /*!< 0x02000000 */
+#define FMC_PMEMx_MEMHIZx_2         (0x04U << FMC_PMEMx_MEMHIZx_Pos)           /*!< 0x04000000 */
+#define FMC_PMEMx_MEMHIZx_3         (0x08U << FMC_PMEMx_MEMHIZx_Pos)           /*!< 0x08000000 */
+#define FMC_PMEMx_MEMHIZx_4         (0x10U << FMC_PMEMx_MEMHIZx_Pos)           /*!< 0x10000000 */
+#define FMC_PMEMx_MEMHIZx_5         (0x20U << FMC_PMEMx_MEMHIZx_Pos)           /*!< 0x20000000 */
+#define FMC_PMEMx_MEMHIZx_6         (0x40U << FMC_PMEMx_MEMHIZx_Pos)           /*!< 0x40000000 */
+#define FMC_PMEMx_MEMHIZx_7         (0x80U << FMC_PMEMx_MEMHIZx_Pos)           /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PMEM2 register  ******************/
+#define FMC_PMEM2_MEMSET2_Pos       (0U)                                       
+#define FMC_PMEM2_MEMSET2_Msk       (0xFFU << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x000000FF */
+#define FMC_PMEM2_MEMSET2           FMC_PMEM2_MEMSET2_Msk                      /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM2_MEMSET2_0         (0x01U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000001 */
+#define FMC_PMEM2_MEMSET2_1         (0x02U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000002 */
+#define FMC_PMEM2_MEMSET2_2         (0x04U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000004 */
+#define FMC_PMEM2_MEMSET2_3         (0x08U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000008 */
+#define FMC_PMEM2_MEMSET2_4         (0x10U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000010 */
+#define FMC_PMEM2_MEMSET2_5         (0x20U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000020 */
+#define FMC_PMEM2_MEMSET2_6         (0x40U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000040 */
+#define FMC_PMEM2_MEMSET2_7         (0x80U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000080 */
+
+#define FMC_PMEM2_MEMWAIT2_Pos      (8U)                                       
+#define FMC_PMEM2_MEMWAIT2_Msk      (0xFFU << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x0000FF00 */
+#define FMC_PMEM2_MEMWAIT2          FMC_PMEM2_MEMWAIT2_Msk                     /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM2_MEMWAIT2_0        (0x01U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000100 */
+#define FMC_PMEM2_MEMWAIT2_1        (0x02U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000200 */
+#define FMC_PMEM2_MEMWAIT2_2        (0x04U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000400 */
+#define FMC_PMEM2_MEMWAIT2_3        (0x08U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000800 */
+#define FMC_PMEM2_MEMWAIT2_4        (0x10U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00001000 */
+#define FMC_PMEM2_MEMWAIT2_5        (0x20U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00002000 */
+#define FMC_PMEM2_MEMWAIT2_6        (0x40U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00004000 */
+#define FMC_PMEM2_MEMWAIT2_7        (0x80U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00008000 */
+
+#define FMC_PMEM2_MEMHOLD2_Pos      (16U)                                      
+#define FMC_PMEM2_MEMHOLD2_Msk      (0xFFU << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00FF0000 */
+#define FMC_PMEM2_MEMHOLD2          FMC_PMEM2_MEMHOLD2_Msk                     /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM2_MEMHOLD2_0        (0x01U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00010000 */
+#define FMC_PMEM2_MEMHOLD2_1        (0x02U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00020000 */
+#define FMC_PMEM2_MEMHOLD2_2        (0x04U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00040000 */
+#define FMC_PMEM2_MEMHOLD2_3        (0x08U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00080000 */
+#define FMC_PMEM2_MEMHOLD2_4        (0x10U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00100000 */
+#define FMC_PMEM2_MEMHOLD2_5        (0x20U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00200000 */
+#define FMC_PMEM2_MEMHOLD2_6        (0x40U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00400000 */
+#define FMC_PMEM2_MEMHOLD2_7        (0x80U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00800000 */
+
+#define FMC_PMEM2_MEMHIZ2_Pos       (24U)                                      
+#define FMC_PMEM2_MEMHIZ2_Msk       (0xFFU << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0xFF000000 */
+#define FMC_PMEM2_MEMHIZ2           FMC_PMEM2_MEMHIZ2_Msk                      /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM2_MEMHIZ2_0         (0x01U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x01000000 */
+#define FMC_PMEM2_MEMHIZ2_1         (0x02U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x02000000 */
+#define FMC_PMEM2_MEMHIZ2_2         (0x04U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x04000000 */
+#define FMC_PMEM2_MEMHIZ2_3         (0x08U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x08000000 */
+#define FMC_PMEM2_MEMHIZ2_4         (0x10U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x10000000 */
+#define FMC_PMEM2_MEMHIZ2_5         (0x20U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x20000000 */
+#define FMC_PMEM2_MEMHIZ2_6         (0x40U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x40000000 */
+#define FMC_PMEM2_MEMHIZ2_7         (0x80U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PMEM3 register  ******************/
+#define FMC_PMEM3_MEMSET3_Pos       (0U)                                       
+#define FMC_PMEM3_MEMSET3_Msk       (0xFFU << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x000000FF */
+#define FMC_PMEM3_MEMSET3           FMC_PMEM3_MEMSET3_Msk                      /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FMC_PMEM3_MEMSET3_0         (0x01U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000001 */
+#define FMC_PMEM3_MEMSET3_1         (0x02U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000002 */
+#define FMC_PMEM3_MEMSET3_2         (0x04U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000004 */
+#define FMC_PMEM3_MEMSET3_3         (0x08U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000008 */
+#define FMC_PMEM3_MEMSET3_4         (0x10U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000010 */
+#define FMC_PMEM3_MEMSET3_5         (0x20U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000020 */
+#define FMC_PMEM3_MEMSET3_6         (0x40U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000040 */
+#define FMC_PMEM3_MEMSET3_7         (0x80U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000080 */
+
+#define FMC_PMEM3_MEMWAIT3_Pos      (8U)                                       
+#define FMC_PMEM3_MEMWAIT3_Msk      (0xFFU << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x0000FF00 */
+#define FMC_PMEM3_MEMWAIT3          FMC_PMEM3_MEMWAIT3_Msk                     /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FMC_PMEM3_MEMWAIT3_0        (0x01U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000100 */
+#define FMC_PMEM3_MEMWAIT3_1        (0x02U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000200 */
+#define FMC_PMEM3_MEMWAIT3_2        (0x04U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000400 */
+#define FMC_PMEM3_MEMWAIT3_3        (0x08U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000800 */
+#define FMC_PMEM3_MEMWAIT3_4        (0x10U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00001000 */
+#define FMC_PMEM3_MEMWAIT3_5        (0x20U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00002000 */
+#define FMC_PMEM3_MEMWAIT3_6        (0x40U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00004000 */
+#define FMC_PMEM3_MEMWAIT3_7        (0x80U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00008000 */
+
+#define FMC_PMEM3_MEMHOLD3_Pos      (16U)                                      
+#define FMC_PMEM3_MEMHOLD3_Msk      (0xFFU << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00FF0000 */
+#define FMC_PMEM3_MEMHOLD3          FMC_PMEM3_MEMHOLD3_Msk                     /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FMC_PMEM3_MEMHOLD3_0        (0x01U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00010000 */
+#define FMC_PMEM3_MEMHOLD3_1        (0x02U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00020000 */
+#define FMC_PMEM3_MEMHOLD3_2        (0x04U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00040000 */
+#define FMC_PMEM3_MEMHOLD3_3        (0x08U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00080000 */
+#define FMC_PMEM3_MEMHOLD3_4        (0x10U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00100000 */
+#define FMC_PMEM3_MEMHOLD3_5        (0x20U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00200000 */
+#define FMC_PMEM3_MEMHOLD3_6        (0x40U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00400000 */
+#define FMC_PMEM3_MEMHOLD3_7        (0x80U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00800000 */
+
+#define FMC_PMEM3_MEMHIZ3_Pos       (24U)                                      
+#define FMC_PMEM3_MEMHIZ3_Msk       (0xFFU << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0xFF000000 */
+#define FMC_PMEM3_MEMHIZ3           FMC_PMEM3_MEMHIZ3_Msk                      /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FMC_PMEM3_MEMHIZ3_0         (0x01U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x01000000 */
+#define FMC_PMEM3_MEMHIZ3_1         (0x02U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x02000000 */
+#define FMC_PMEM3_MEMHIZ3_2         (0x04U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x04000000 */
+#define FMC_PMEM3_MEMHIZ3_3         (0x08U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x08000000 */
+#define FMC_PMEM3_MEMHIZ3_4         (0x10U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x10000000 */
+#define FMC_PMEM3_MEMHIZ3_5         (0x20U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x20000000 */
+#define FMC_PMEM3_MEMHIZ3_6         (0x40U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x40000000 */
+#define FMC_PMEM3_MEMHIZ3_7         (0x80U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PMEM4 register  ******************/
+#define FMC_PMEM4_MEMSET4_Pos       (0U)                                       
+#define FMC_PMEM4_MEMSET4_Msk       (0xFFU << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x000000FF */
+#define FMC_PMEM4_MEMSET4           FMC_PMEM4_MEMSET4_Msk                      /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FMC_PMEM4_MEMSET4_0         (0x01U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000001 */
+#define FMC_PMEM4_MEMSET4_1         (0x02U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000002 */
+#define FMC_PMEM4_MEMSET4_2         (0x04U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000004 */
+#define FMC_PMEM4_MEMSET4_3         (0x08U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000008 */
+#define FMC_PMEM4_MEMSET4_4         (0x10U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000010 */
+#define FMC_PMEM4_MEMSET4_5         (0x20U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000020 */
+#define FMC_PMEM4_MEMSET4_6         (0x40U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000040 */
+#define FMC_PMEM4_MEMSET4_7         (0x80U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000080 */
+
+#define FMC_PMEM4_MEMWAIT4_Pos      (8U)                                       
+#define FMC_PMEM4_MEMWAIT4_Msk      (0xFFU << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x0000FF00 */
+#define FMC_PMEM4_MEMWAIT4          FMC_PMEM4_MEMWAIT4_Msk                     /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FMC_PMEM4_MEMWAIT4_0        (0x01U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000100 */
+#define FMC_PMEM4_MEMWAIT4_1        (0x02U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000200 */
+#define FMC_PMEM4_MEMWAIT4_2        (0x04U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000400 */
+#define FMC_PMEM4_MEMWAIT4_3        (0x08U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000800 */
+#define FMC_PMEM4_MEMWAIT4_4        (0x10U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00001000 */
+#define FMC_PMEM4_MEMWAIT4_5        (0x20U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00002000 */
+#define FMC_PMEM4_MEMWAIT4_6        (0x40U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00004000 */
+#define FMC_PMEM4_MEMWAIT4_7        (0x80U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00008000 */
+
+#define FMC_PMEM4_MEMHOLD4_Pos      (16U)                                      
+#define FMC_PMEM4_MEMHOLD4_Msk      (0xFFU << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00FF0000 */
+#define FMC_PMEM4_MEMHOLD4          FMC_PMEM4_MEMHOLD4_Msk                     /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FMC_PMEM4_MEMHOLD4_0        (0x01U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00010000 */
+#define FMC_PMEM4_MEMHOLD4_1        (0x02U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00020000 */
+#define FMC_PMEM4_MEMHOLD4_2        (0x04U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00040000 */
+#define FMC_PMEM4_MEMHOLD4_3        (0x08U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00080000 */
+#define FMC_PMEM4_MEMHOLD4_4        (0x10U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00100000 */
+#define FMC_PMEM4_MEMHOLD4_5        (0x20U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00200000 */
+#define FMC_PMEM4_MEMHOLD4_6        (0x40U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00400000 */
+#define FMC_PMEM4_MEMHOLD4_7        (0x80U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00800000 */
+
+#define FMC_PMEM4_MEMHIZ4_Pos       (24U)                                      
+#define FMC_PMEM4_MEMHIZ4_Msk       (0xFFU << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0xFF000000 */
+#define FMC_PMEM4_MEMHIZ4           FMC_PMEM4_MEMHIZ4_Msk                      /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FMC_PMEM4_MEMHIZ4_0         (0x01U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x01000000 */
+#define FMC_PMEM4_MEMHIZ4_1         (0x02U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x02000000 */
+#define FMC_PMEM4_MEMHIZ4_2         (0x04U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x04000000 */
+#define FMC_PMEM4_MEMHIZ4_3         (0x08U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x08000000 */
+#define FMC_PMEM4_MEMHIZ4_4         (0x10U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x10000000 */
+#define FMC_PMEM4_MEMHIZ4_5         (0x20U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x20000000 */
+#define FMC_PMEM4_MEMHIZ4_6         (0x40U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x40000000 */
+#define FMC_PMEM4_MEMHIZ4_7         (0x80U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATTx register  ******************/
+#define FMC_PATTx_ATTSETx_Pos       (0U)                                       
+#define FMC_PATTx_ATTSETx_Msk       (0xFFU << FMC_PATTx_ATTSETx_Pos)           /*!< 0x000000FF */
+#define FMC_PATTx_ATTSETx           FMC_PATTx_ATTSETx_Msk                      /*!<ATTSETx[7:0] bits (Attribute memory x setup time) */
+#define FMC_PATTx_ATTSETx_0         (0x01U << FMC_PATTx_ATTSETx_Pos)           /*!< 0x00000001 */
+#define FMC_PATTx_ATTSETx_1         (0x02U << FMC_PATTx_ATTSETx_Pos)           /*!< 0x00000002 */
+#define FMC_PATTx_ATTSETx_2         (0x04U << FMC_PATTx_ATTSETx_Pos)           /*!< 0x00000004 */
+#define FMC_PATTx_ATTSETx_3         (0x08U << FMC_PATTx_ATTSETx_Pos)           /*!< 0x00000008 */
+#define FMC_PATTx_ATTSETx_4         (0x10U << FMC_PATTx_ATTSETx_Pos)           /*!< 0x00000010 */
+#define FMC_PATTx_ATTSETx_5         (0x20U << FMC_PATTx_ATTSETx_Pos)           /*!< 0x00000020 */
+#define FMC_PATTx_ATTSETx_6         (0x40U << FMC_PATTx_ATTSETx_Pos)           /*!< 0x00000040 */
+#define FMC_PATTx_ATTSETx_7         (0x80U << FMC_PATTx_ATTSETx_Pos)           /*!< 0x00000080 */
+
+#define FMC_PATTx_ATTWAITx_Pos      (8U)                                       
+#define FMC_PATTx_ATTWAITx_Msk      (0xFFU << FMC_PATTx_ATTWAITx_Pos)          /*!< 0x0000FF00 */
+#define FMC_PATTx_ATTWAITx          FMC_PATTx_ATTWAITx_Msk                     /*!<ATTWAITx[7:0] bits (Attribute memory x wait time) */
+#define FMC_PATTx_ATTWAITx_0        (0x01U << FMC_PATTx_ATTWAITx_Pos)          /*!< 0x00000100 */
+#define FMC_PATTx_ATTWAITx_1        (0x02U << FMC_PATTx_ATTWAITx_Pos)          /*!< 0x00000200 */
+#define FMC_PATTx_ATTWAITx_2        (0x04U << FMC_PATTx_ATTWAITx_Pos)          /*!< 0x00000400 */
+#define FMC_PATTx_ATTWAITx_3        (0x08U << FMC_PATTx_ATTWAITx_Pos)          /*!< 0x00000800 */
+#define FMC_PATTx_ATTWAITx_4        (0x10U << FMC_PATTx_ATTWAITx_Pos)          /*!< 0x00001000 */
+#define FMC_PATTx_ATTWAITx_5        (0x20U << FMC_PATTx_ATTWAITx_Pos)          /*!< 0x00002000 */
+#define FMC_PATTx_ATTWAITx_6        (0x40U << FMC_PATTx_ATTWAITx_Pos)          /*!< 0x00004000 */
+#define FMC_PATTx_ATTWAITx_7        (0x80U << FMC_PATTx_ATTWAITx_Pos)          /*!< 0x00008000 */
+
+#define FMC_PATTx_ATTHOLDx_Pos      (16U)                                      
+#define FMC_PATTx_ATTHOLDx_Msk      (0xFFU << FMC_PATTx_ATTHOLDx_Pos)          /*!< 0x00FF0000 */
+#define FMC_PATTx_ATTHOLDx          FMC_PATTx_ATTHOLDx_Msk                     /*!<ATTHOLDx[7:0] bits (Attribute memory x hold time) */
+#define FMC_PATTx_ATTHOLDx_0        (0x01U << FMC_PATTx_ATTHOLDx_Pos)          /*!< 0x00010000 */
+#define FMC_PATTx_ATTHOLDx_1        (0x02U << FMC_PATTx_ATTHOLDx_Pos)          /*!< 0x00020000 */
+#define FMC_PATTx_ATTHOLDx_2        (0x04U << FMC_PATTx_ATTHOLDx_Pos)          /*!< 0x00040000 */
+#define FMC_PATTx_ATTHOLDx_3        (0x08U << FMC_PATTx_ATTHOLDx_Pos)          /*!< 0x00080000 */
+#define FMC_PATTx_ATTHOLDx_4        (0x10U << FMC_PATTx_ATTHOLDx_Pos)          /*!< 0x00100000 */
+#define FMC_PATTx_ATTHOLDx_5        (0x20U << FMC_PATTx_ATTHOLDx_Pos)          /*!< 0x00200000 */
+#define FMC_PATTx_ATTHOLDx_6        (0x40U << FMC_PATTx_ATTHOLDx_Pos)          /*!< 0x00400000 */
+#define FMC_PATTx_ATTHOLDx_7        (0x80U << FMC_PATTx_ATTHOLDx_Pos)          /*!< 0x00800000 */
+
+#define FMC_PATTx_ATTHIZx_Pos       (24U)                                      
+#define FMC_PATTx_ATTHIZx_Msk       (0xFFU << FMC_PATTx_ATTHIZx_Pos)           /*!< 0xFF000000 */
+#define FMC_PATTx_ATTHIZx           FMC_PATTx_ATTHIZx_Msk                      /*!<ATTHIZx[7:0] bits (Attribute memory x databus HiZ time) */
+#define FMC_PATTx_ATTHIZx_0         (0x01U << FMC_PATTx_ATTHIZx_Pos)           /*!< 0x01000000 */
+#define FMC_PATTx_ATTHIZx_1         (0x02U << FMC_PATTx_ATTHIZx_Pos)           /*!< 0x02000000 */
+#define FMC_PATTx_ATTHIZx_2         (0x04U << FMC_PATTx_ATTHIZx_Pos)           /*!< 0x04000000 */
+#define FMC_PATTx_ATTHIZx_3         (0x08U << FMC_PATTx_ATTHIZx_Pos)           /*!< 0x08000000 */
+#define FMC_PATTx_ATTHIZx_4         (0x10U << FMC_PATTx_ATTHIZx_Pos)           /*!< 0x10000000 */
+#define FMC_PATTx_ATTHIZx_5         (0x20U << FMC_PATTx_ATTHIZx_Pos)           /*!< 0x20000000 */
+#define FMC_PATTx_ATTHIZx_6         (0x40U << FMC_PATTx_ATTHIZx_Pos)           /*!< 0x40000000 */
+#define FMC_PATTx_ATTHIZx_7         (0x80U << FMC_PATTx_ATTHIZx_Pos)           /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT2 register  ******************/
+#define FMC_PATT2_ATTSET2_Pos       (0U)                                       
+#define FMC_PATT2_ATTSET2_Msk       (0xFFU << FMC_PATT2_ATTSET2_Pos)           /*!< 0x000000FF */
+#define FMC_PATT2_ATTSET2           FMC_PATT2_ATTSET2_Msk                      /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT2_ATTSET2_0         (0x01U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000001 */
+#define FMC_PATT2_ATTSET2_1         (0x02U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000002 */
+#define FMC_PATT2_ATTSET2_2         (0x04U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000004 */
+#define FMC_PATT2_ATTSET2_3         (0x08U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000008 */
+#define FMC_PATT2_ATTSET2_4         (0x10U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000010 */
+#define FMC_PATT2_ATTSET2_5         (0x20U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000020 */
+#define FMC_PATT2_ATTSET2_6         (0x40U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000040 */
+#define FMC_PATT2_ATTSET2_7         (0x80U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000080 */
+
+#define FMC_PATT2_ATTWAIT2_Pos      (8U)                                       
+#define FMC_PATT2_ATTWAIT2_Msk      (0xFFU << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x0000FF00 */
+#define FMC_PATT2_ATTWAIT2          FMC_PATT2_ATTWAIT2_Msk                     /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT2_ATTWAIT2_0        (0x01U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000100 */
+#define FMC_PATT2_ATTWAIT2_1        (0x02U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000200 */
+#define FMC_PATT2_ATTWAIT2_2        (0x04U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000400 */
+#define FMC_PATT2_ATTWAIT2_3        (0x08U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000800 */
+#define FMC_PATT2_ATTWAIT2_4        (0x10U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00001000 */
+#define FMC_PATT2_ATTWAIT2_5        (0x20U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00002000 */
+#define FMC_PATT2_ATTWAIT2_6        (0x40U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00004000 */
+#define FMC_PATT2_ATTWAIT2_7        (0x80U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00008000 */
+
+#define FMC_PATT2_ATTHOLD2_Pos      (16U)                                      
+#define FMC_PATT2_ATTHOLD2_Msk      (0xFFU << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00FF0000 */
+#define FMC_PATT2_ATTHOLD2          FMC_PATT2_ATTHOLD2_Msk                     /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT2_ATTHOLD2_0        (0x01U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00010000 */
+#define FMC_PATT2_ATTHOLD2_1        (0x02U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00020000 */
+#define FMC_PATT2_ATTHOLD2_2        (0x04U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00040000 */
+#define FMC_PATT2_ATTHOLD2_3        (0x08U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00080000 */
+#define FMC_PATT2_ATTHOLD2_4        (0x10U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00100000 */
+#define FMC_PATT2_ATTHOLD2_5        (0x20U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00200000 */
+#define FMC_PATT2_ATTHOLD2_6        (0x40U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00400000 */
+#define FMC_PATT2_ATTHOLD2_7        (0x80U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00800000 */
+
+#define FMC_PATT2_ATTHIZ2_Pos       (24U)                                      
+#define FMC_PATT2_ATTHIZ2_Msk       (0xFFU << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0xFF000000 */
+#define FMC_PATT2_ATTHIZ2           FMC_PATT2_ATTHIZ2_Msk                      /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT2_ATTHIZ2_0         (0x01U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x01000000 */
+#define FMC_PATT2_ATTHIZ2_1         (0x02U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x02000000 */
+#define FMC_PATT2_ATTHIZ2_2         (0x04U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x04000000 */
+#define FMC_PATT2_ATTHIZ2_3         (0x08U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x08000000 */
+#define FMC_PATT2_ATTHIZ2_4         (0x10U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x10000000 */
+#define FMC_PATT2_ATTHIZ2_5         (0x20U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x20000000 */
+#define FMC_PATT2_ATTHIZ2_6         (0x40U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x40000000 */
+#define FMC_PATT2_ATTHIZ2_7         (0x80U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT3 register  ******************/
+#define FMC_PATT3_ATTSET3_Pos       (0U)                                       
+#define FMC_PATT3_ATTSET3_Msk       (0xFFU << FMC_PATT3_ATTSET3_Pos)           /*!< 0x000000FF */
+#define FMC_PATT3_ATTSET3           FMC_PATT3_ATTSET3_Msk                      /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FMC_PATT3_ATTSET3_0         (0x01U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000001 */
+#define FMC_PATT3_ATTSET3_1         (0x02U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000002 */
+#define FMC_PATT3_ATTSET3_2         (0x04U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000004 */
+#define FMC_PATT3_ATTSET3_3         (0x08U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000008 */
+#define FMC_PATT3_ATTSET3_4         (0x10U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000010 */
+#define FMC_PATT3_ATTSET3_5         (0x20U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000020 */
+#define FMC_PATT3_ATTSET3_6         (0x40U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000040 */
+#define FMC_PATT3_ATTSET3_7         (0x80U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000080 */
+
+#define FMC_PATT3_ATTWAIT3_Pos      (8U)                                       
+#define FMC_PATT3_ATTWAIT3_Msk      (0xFFU << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x0000FF00 */
+#define FMC_PATT3_ATTWAIT3          FMC_PATT3_ATTWAIT3_Msk                     /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FMC_PATT3_ATTWAIT3_0        (0x01U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000100 */
+#define FMC_PATT3_ATTWAIT3_1        (0x02U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000200 */
+#define FMC_PATT3_ATTWAIT3_2        (0x04U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000400 */
+#define FMC_PATT3_ATTWAIT3_3        (0x08U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000800 */
+#define FMC_PATT3_ATTWAIT3_4        (0x10U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00001000 */
+#define FMC_PATT3_ATTWAIT3_5        (0x20U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00002000 */
+#define FMC_PATT3_ATTWAIT3_6        (0x40U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00004000 */
+#define FMC_PATT3_ATTWAIT3_7        (0x80U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00008000 */
+
+#define FMC_PATT3_ATTHOLD3_Pos      (16U)                                      
+#define FMC_PATT3_ATTHOLD3_Msk      (0xFFU << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00FF0000 */
+#define FMC_PATT3_ATTHOLD3          FMC_PATT3_ATTHOLD3_Msk                     /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FMC_PATT3_ATTHOLD3_0        (0x01U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00010000 */
+#define FMC_PATT3_ATTHOLD3_1        (0x02U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00020000 */
+#define FMC_PATT3_ATTHOLD3_2        (0x04U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00040000 */
+#define FMC_PATT3_ATTHOLD3_3        (0x08U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00080000 */
+#define FMC_PATT3_ATTHOLD3_4        (0x10U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00100000 */
+#define FMC_PATT3_ATTHOLD3_5        (0x20U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00200000 */
+#define FMC_PATT3_ATTHOLD3_6        (0x40U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00400000 */
+#define FMC_PATT3_ATTHOLD3_7        (0x80U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00800000 */
+
+#define FMC_PATT3_ATTHIZ3_Pos       (24U)                                      
+#define FMC_PATT3_ATTHIZ3_Msk       (0xFFU << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0xFF000000 */
+#define FMC_PATT3_ATTHIZ3           FMC_PATT3_ATTHIZ3_Msk                      /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FMC_PATT3_ATTHIZ3_0         (0x01U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x01000000 */
+#define FMC_PATT3_ATTHIZ3_1         (0x02U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x02000000 */
+#define FMC_PATT3_ATTHIZ3_2         (0x04U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x04000000 */
+#define FMC_PATT3_ATTHIZ3_3         (0x08U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x08000000 */
+#define FMC_PATT3_ATTHIZ3_4         (0x10U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x10000000 */
+#define FMC_PATT3_ATTHIZ3_5         (0x20U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x20000000 */
+#define FMC_PATT3_ATTHIZ3_6         (0x40U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x40000000 */
+#define FMC_PATT3_ATTHIZ3_7         (0x80U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT4 register  ******************/
+#define FMC_PATT4_ATTSET4_Pos       (0U)                                       
+#define FMC_PATT4_ATTSET4_Msk       (0xFFU << FMC_PATT4_ATTSET4_Pos)           /*!< 0x000000FF */
+#define FMC_PATT4_ATTSET4           FMC_PATT4_ATTSET4_Msk                      /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FMC_PATT4_ATTSET4_0         (0x01U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000001 */
+#define FMC_PATT4_ATTSET4_1         (0x02U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000002 */
+#define FMC_PATT4_ATTSET4_2         (0x04U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000004 */
+#define FMC_PATT4_ATTSET4_3         (0x08U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000008 */
+#define FMC_PATT4_ATTSET4_4         (0x10U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000010 */
+#define FMC_PATT4_ATTSET4_5         (0x20U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000020 */
+#define FMC_PATT4_ATTSET4_6         (0x40U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000040 */
+#define FMC_PATT4_ATTSET4_7         (0x80U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000080 */
+
+#define FMC_PATT4_ATTWAIT4_Pos      (8U)                                       
+#define FMC_PATT4_ATTWAIT4_Msk      (0xFFU << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x0000FF00 */
+#define FMC_PATT4_ATTWAIT4          FMC_PATT4_ATTWAIT4_Msk                     /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FMC_PATT4_ATTWAIT4_0        (0x01U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000100 */
+#define FMC_PATT4_ATTWAIT4_1        (0x02U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000200 */
+#define FMC_PATT4_ATTWAIT4_2        (0x04U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000400 */
+#define FMC_PATT4_ATTWAIT4_3        (0x08U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000800 */
+#define FMC_PATT4_ATTWAIT4_4        (0x10U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00001000 */
+#define FMC_PATT4_ATTWAIT4_5        (0x20U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00002000 */
+#define FMC_PATT4_ATTWAIT4_6        (0x40U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00004000 */
+#define FMC_PATT4_ATTWAIT4_7        (0x80U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00008000 */
+
+#define FMC_PATT4_ATTHOLD4_Pos      (16U)                                      
+#define FMC_PATT4_ATTHOLD4_Msk      (0xFFU << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00FF0000 */
+#define FMC_PATT4_ATTHOLD4          FMC_PATT4_ATTHOLD4_Msk                     /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FMC_PATT4_ATTHOLD4_0        (0x01U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00010000 */
+#define FMC_PATT4_ATTHOLD4_1        (0x02U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00020000 */
+#define FMC_PATT4_ATTHOLD4_2        (0x04U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00040000 */
+#define FMC_PATT4_ATTHOLD4_3        (0x08U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00080000 */
+#define FMC_PATT4_ATTHOLD4_4        (0x10U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00100000 */
+#define FMC_PATT4_ATTHOLD4_5        (0x20U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00200000 */
+#define FMC_PATT4_ATTHOLD4_6        (0x40U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00400000 */
+#define FMC_PATT4_ATTHOLD4_7        (0x80U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00800000 */
+
+#define FMC_PATT4_ATTHIZ4_Pos       (24U)                                      
+#define FMC_PATT4_ATTHIZ4_Msk       (0xFFU << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0xFF000000 */
+#define FMC_PATT4_ATTHIZ4           FMC_PATT4_ATTHIZ4_Msk                      /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FMC_PATT4_ATTHIZ4_0         (0x01U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x01000000 */
+#define FMC_PATT4_ATTHIZ4_1         (0x02U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x02000000 */
+#define FMC_PATT4_ATTHIZ4_2         (0x04U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x04000000 */
+#define FMC_PATT4_ATTHIZ4_3         (0x08U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x08000000 */
+#define FMC_PATT4_ATTHIZ4_4         (0x10U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x10000000 */
+#define FMC_PATT4_ATTHIZ4_5         (0x20U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x20000000 */
+#define FMC_PATT4_ATTHIZ4_6         (0x40U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x40000000 */
+#define FMC_PATT4_ATTHIZ4_7         (0x80U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PIO4 register  *******************/
+#define FMC_PIO4_IOSET4_Pos         (0U)                                       
+#define FMC_PIO4_IOSET4_Msk         (0xFFU << FMC_PIO4_IOSET4_Pos)             /*!< 0x000000FF */
+#define FMC_PIO4_IOSET4             FMC_PIO4_IOSET4_Msk                        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FMC_PIO4_IOSET4_0           (0x01U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000001 */
+#define FMC_PIO4_IOSET4_1           (0x02U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000002 */
+#define FMC_PIO4_IOSET4_2           (0x04U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000004 */
+#define FMC_PIO4_IOSET4_3           (0x08U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000008 */
+#define FMC_PIO4_IOSET4_4           (0x10U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000010 */
+#define FMC_PIO4_IOSET4_5           (0x20U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000020 */
+#define FMC_PIO4_IOSET4_6           (0x40U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000040 */
+#define FMC_PIO4_IOSET4_7           (0x80U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000080 */
+
+#define FMC_PIO4_IOWAIT4_Pos        (8U)                                       
+#define FMC_PIO4_IOWAIT4_Msk        (0xFFU << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x0000FF00 */
+#define FMC_PIO4_IOWAIT4            FMC_PIO4_IOWAIT4_Msk                       /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FMC_PIO4_IOWAIT4_0          (0x01U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000100 */
+#define FMC_PIO4_IOWAIT4_1          (0x02U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000200 */
+#define FMC_PIO4_IOWAIT4_2          (0x04U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000400 */
+#define FMC_PIO4_IOWAIT4_3          (0x08U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000800 */
+#define FMC_PIO4_IOWAIT4_4          (0x10U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00001000 */
+#define FMC_PIO4_IOWAIT4_5          (0x20U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00002000 */
+#define FMC_PIO4_IOWAIT4_6          (0x40U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00004000 */
+#define FMC_PIO4_IOWAIT4_7          (0x80U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00008000 */
+
+#define FMC_PIO4_IOHOLD4_Pos        (16U)                                      
+#define FMC_PIO4_IOHOLD4_Msk        (0xFFU << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00FF0000 */
+#define FMC_PIO4_IOHOLD4            FMC_PIO4_IOHOLD4_Msk                       /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FMC_PIO4_IOHOLD4_0          (0x01U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00010000 */
+#define FMC_PIO4_IOHOLD4_1          (0x02U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00020000 */
+#define FMC_PIO4_IOHOLD4_2          (0x04U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00040000 */
+#define FMC_PIO4_IOHOLD4_3          (0x08U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00080000 */
+#define FMC_PIO4_IOHOLD4_4          (0x10U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00100000 */
+#define FMC_PIO4_IOHOLD4_5          (0x20U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00200000 */
+#define FMC_PIO4_IOHOLD4_6          (0x40U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00400000 */
+#define FMC_PIO4_IOHOLD4_7          (0x80U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00800000 */
+
+#define FMC_PIO4_IOHIZ4_Pos         (24U)                                      
+#define FMC_PIO4_IOHIZ4_Msk         (0xFFU << FMC_PIO4_IOHIZ4_Pos)             /*!< 0xFF000000 */
+#define FMC_PIO4_IOHIZ4             FMC_PIO4_IOHIZ4_Msk                        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FMC_PIO4_IOHIZ4_0           (0x01U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x01000000 */
+#define FMC_PIO4_IOHIZ4_1           (0x02U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x02000000 */
+#define FMC_PIO4_IOHIZ4_2           (0x04U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x04000000 */
+#define FMC_PIO4_IOHIZ4_3           (0x08U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x08000000 */
+#define FMC_PIO4_IOHIZ4_4           (0x10U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x10000000 */
+#define FMC_PIO4_IOHIZ4_5           (0x20U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x20000000 */
+#define FMC_PIO4_IOHIZ4_6           (0x40U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x40000000 */
+#define FMC_PIO4_IOHIZ4_7           (0x80U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_ECCR2 register  ******************/
+#define FMC_ECCR2_ECC2_Pos          (0U)                                       
+#define FMC_ECCR2_ECC2_Msk          (0xFFFFFFFFU << FMC_ECCR2_ECC2_Pos)        /*!< 0xFFFFFFFF */
+#define FMC_ECCR2_ECC2              FMC_ECCR2_ECC2_Msk                         /*!<ECC result */
+
+/******************  Bit definition for FMC_ECCR3 register  ******************/
+#define FMC_ECCR3_ECC3_Pos          (0U)                                       
+#define FMC_ECCR3_ECC3_Msk          (0xFFFFFFFFU << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */
+#define FMC_ECCR3_ECC3              FMC_ECCR3_ECC3_Msk                         /*!<ECC result */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O (GPIO)                      */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0_Pos            (0U)                                  
+#define GPIO_MODER_MODER0_Msk            (0x3U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */
+#define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk                 
+#define GPIO_MODER_MODER0_0              (0x1U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1              (0x2U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos            (2U)                                  
+#define GPIO_MODER_MODER1_Msk            (0x3U << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */
+#define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk                 
+#define GPIO_MODER_MODER1_0              (0x1U << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1              (0x2U << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos            (4U)                                  
+#define GPIO_MODER_MODER2_Msk            (0x3U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */
+#define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk                 
+#define GPIO_MODER_MODER2_0              (0x1U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1              (0x2U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos            (6U)                                  
+#define GPIO_MODER_MODER3_Msk            (0x3U << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk                 
+#define GPIO_MODER_MODER3_0              (0x1U << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1              (0x2U << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos            (8U)                                  
+#define GPIO_MODER_MODER4_Msk            (0x3U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */
+#define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk                 
+#define GPIO_MODER_MODER4_0              (0x1U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1              (0x2U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos            (10U)                                 
+#define GPIO_MODER_MODER5_Msk            (0x3U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk                 
+#define GPIO_MODER_MODER5_0              (0x1U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1              (0x2U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos            (12U)                                 
+#define GPIO_MODER_MODER6_Msk            (0x3U << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */
+#define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk                 
+#define GPIO_MODER_MODER6_0              (0x1U << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1              (0x2U << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos            (14U)                                 
+#define GPIO_MODER_MODER7_Msk            (0x3U << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk                 
+#define GPIO_MODER_MODER7_0              (0x1U << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1              (0x2U << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos            (16U)                                 
+#define GPIO_MODER_MODER8_Msk            (0x3U << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */
+#define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk                 
+#define GPIO_MODER_MODER8_0              (0x1U << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1              (0x2U << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos            (18U)                                 
+#define GPIO_MODER_MODER9_Msk            (0x3U << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk                 
+#define GPIO_MODER_MODER9_0              (0x1U << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1              (0x2U << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos           (20U)                                 
+#define GPIO_MODER_MODER10_Msk           (0x3U << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */
+#define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk                
+#define GPIO_MODER_MODER10_0             (0x1U << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1             (0x2U << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos           (22U)                                 
+#define GPIO_MODER_MODER11_Msk           (0x3U << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk                
+#define GPIO_MODER_MODER11_0             (0x1U << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1             (0x2U << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos           (24U)                                 
+#define GPIO_MODER_MODER12_Msk           (0x3U << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */
+#define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk                
+#define GPIO_MODER_MODER12_0             (0x1U << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1             (0x2U << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos           (26U)                                 
+#define GPIO_MODER_MODER13_Msk           (0x3U << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk                
+#define GPIO_MODER_MODER13_0             (0x1U << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1             (0x2U << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos           (28U)                                 
+#define GPIO_MODER_MODER14_Msk           (0x3U << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */
+#define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk                
+#define GPIO_MODER_MODER14_0             (0x1U << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1             (0x2U << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos           (30U)                                 
+#define GPIO_MODER_MODER15_Msk           (0x3U << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk                
+#define GPIO_MODER_MODER15_0             (0x1U << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1             (0x2U << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */
+
+/******************  Bit definition for GPIO_OTYPER register  *****************/
+#define GPIO_OTYPER_OT_0                 (0x00000001U)                         
+#define GPIO_OTYPER_OT_1                 (0x00000002U)                         
+#define GPIO_OTYPER_OT_2                 (0x00000004U)                         
+#define GPIO_OTYPER_OT_3                 (0x00000008U)                         
+#define GPIO_OTYPER_OT_4                 (0x00000010U)                         
+#define GPIO_OTYPER_OT_5                 (0x00000020U)                         
+#define GPIO_OTYPER_OT_6                 (0x00000040U)                         
+#define GPIO_OTYPER_OT_7                 (0x00000080U)                         
+#define GPIO_OTYPER_OT_8                 (0x00000100U)                         
+#define GPIO_OTYPER_OT_9                 (0x00000200U)                         
+#define GPIO_OTYPER_OT_10                (0x00000400U)                         
+#define GPIO_OTYPER_OT_11                (0x00000800U)                         
+#define GPIO_OTYPER_OT_12                (0x00001000U)                         
+#define GPIO_OTYPER_OT_13                (0x00002000U)                         
+#define GPIO_OTYPER_OT_14                (0x00004000U)                         
+#define GPIO_OTYPER_OT_15                (0x00008000U)                         
+
+/****************  Bit definition for GPIO_OSPEEDR register  ******************/
+#define GPIO_OSPEEDER_OSPEEDR0_Pos       (0U)                                  
+#define GPIO_OSPEEDER_OSPEEDR0_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos)  /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDER_OSPEEDR0_Msk            
+#define GPIO_OSPEEDER_OSPEEDR0_0         (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos)  /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEEDR0_1         (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos)  /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEEDR1_Pos       (2U)                                  
+#define GPIO_OSPEEDER_OSPEEDR1_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos)  /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDER_OSPEEDR1_Msk            
+#define GPIO_OSPEEDER_OSPEEDR1_0         (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos)  /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEEDR1_1         (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos)  /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEEDR2_Pos       (4U)                                  
+#define GPIO_OSPEEDER_OSPEEDR2_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos)  /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDER_OSPEEDR2_Msk            
+#define GPIO_OSPEEDER_OSPEEDR2_0         (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos)  /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEEDR2_1         (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos)  /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEEDR3_Pos       (6U)                                  
+#define GPIO_OSPEEDER_OSPEEDR3_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos)  /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDER_OSPEEDR3_Msk            
+#define GPIO_OSPEEDER_OSPEEDR3_0         (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos)  /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEEDR3_1         (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos)  /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEEDR4_Pos       (8U)                                  
+#define GPIO_OSPEEDER_OSPEEDR4_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos)  /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDER_OSPEEDR4_Msk            
+#define GPIO_OSPEEDER_OSPEEDR4_0         (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos)  /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEEDR4_1         (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos)  /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEEDR5_Pos       (10U)                                 
+#define GPIO_OSPEEDER_OSPEEDR5_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos)  /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDER_OSPEEDR5_Msk            
+#define GPIO_OSPEEDER_OSPEEDR5_0         (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos)  /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEEDR5_1         (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos)  /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEEDR6_Pos       (12U)                                 
+#define GPIO_OSPEEDER_OSPEEDR6_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos)  /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDER_OSPEEDR6_Msk            
+#define GPIO_OSPEEDER_OSPEEDR6_0         (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos)  /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEEDR6_1         (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos)  /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEEDR7_Pos       (14U)                                 
+#define GPIO_OSPEEDER_OSPEEDR7_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos)  /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDER_OSPEEDR7_Msk            
+#define GPIO_OSPEEDER_OSPEEDR7_0         (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos)  /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEEDR7_1         (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos)  /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEEDR8_Pos       (16U)                                 
+#define GPIO_OSPEEDER_OSPEEDR8_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos)  /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDER_OSPEEDR8_Msk            
+#define GPIO_OSPEEDER_OSPEEDR8_0         (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos)  /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEEDR8_1         (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos)  /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEEDR9_Pos       (18U)                                 
+#define GPIO_OSPEEDER_OSPEEDR9_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos)  /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDER_OSPEEDR9_Msk            
+#define GPIO_OSPEEDER_OSPEEDR9_0         (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos)  /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEEDR9_1         (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos)  /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEEDR10_Pos      (20U)                                 
+#define GPIO_OSPEEDER_OSPEEDR10_Msk      (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDER_OSPEEDR10_Msk           
+#define GPIO_OSPEEDER_OSPEEDR10_0        (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEEDR10_1        (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEEDR11_Pos      (22U)                                 
+#define GPIO_OSPEEDER_OSPEEDR11_Msk      (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDER_OSPEEDR11_Msk           
+#define GPIO_OSPEEDER_OSPEEDR11_0        (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEEDR11_1        (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEEDR12_Pos      (24U)                                 
+#define GPIO_OSPEEDER_OSPEEDR12_Msk      (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDER_OSPEEDR12_Msk           
+#define GPIO_OSPEEDER_OSPEEDR12_0        (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEEDR12_1        (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEEDR13_Pos      (26U)                                 
+#define GPIO_OSPEEDER_OSPEEDR13_Msk      (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDER_OSPEEDR13_Msk           
+#define GPIO_OSPEEDER_OSPEEDR13_0        (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEEDR13_1        (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEEDR14_Pos      (28U)                                 
+#define GPIO_OSPEEDER_OSPEEDR14_Msk      (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDER_OSPEEDR14_Msk           
+#define GPIO_OSPEEDER_OSPEEDR14_0        (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEEDR14_1        (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEEDR15_Pos      (30U)                                 
+#define GPIO_OSPEEDER_OSPEEDR15_Msk      (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDER_OSPEEDR15_Msk           
+#define GPIO_OSPEEDER_OSPEEDR15_0        (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEEDR15_1        (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
+
+/*******************  Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0_Pos            (0U)                                  
+#define GPIO_PUPDR_PUPDR0_Msk            (0x3U << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPDR0_Msk                 
+#define GPIO_PUPDR_PUPDR0_0              (0x1U << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPDR0_1              (0x2U << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPDR1_Pos            (2U)                                  
+#define GPIO_PUPDR_PUPDR1_Msk            (0x3U << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPDR1_Msk                 
+#define GPIO_PUPDR_PUPDR1_0              (0x1U << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPDR1_1              (0x2U << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPDR2_Pos            (4U)                                  
+#define GPIO_PUPDR_PUPDR2_Msk            (0x3U << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPDR2_Msk                 
+#define GPIO_PUPDR_PUPDR2_0              (0x1U << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPDR2_1              (0x2U << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPDR3_Pos            (6U)                                  
+#define GPIO_PUPDR_PUPDR3_Msk            (0x3U << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPDR3_Msk                 
+#define GPIO_PUPDR_PUPDR3_0              (0x1U << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPDR3_1              (0x2U << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPDR4_Pos            (8U)                                  
+#define GPIO_PUPDR_PUPDR4_Msk            (0x3U << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPDR4_Msk                 
+#define GPIO_PUPDR_PUPDR4_0              (0x1U << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPDR4_1              (0x2U << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPDR5_Pos            (10U)                                 
+#define GPIO_PUPDR_PUPDR5_Msk            (0x3U << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPDR5_Msk                 
+#define GPIO_PUPDR_PUPDR5_0              (0x1U << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPDR5_1              (0x2U << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPDR6_Pos            (12U)                                 
+#define GPIO_PUPDR_PUPDR6_Msk            (0x3U << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPDR6_Msk                 
+#define GPIO_PUPDR_PUPDR6_0              (0x1U << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPDR6_1              (0x2U << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPDR7_Pos            (14U)                                 
+#define GPIO_PUPDR_PUPDR7_Msk            (0x3U << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPDR7_Msk                 
+#define GPIO_PUPDR_PUPDR7_0              (0x1U << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPDR7_1              (0x2U << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPDR8_Pos            (16U)                                 
+#define GPIO_PUPDR_PUPDR8_Msk            (0x3U << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPDR8_Msk                 
+#define GPIO_PUPDR_PUPDR8_0              (0x1U << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPDR8_1              (0x2U << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPDR9_Pos            (18U)                                 
+#define GPIO_PUPDR_PUPDR9_Msk            (0x3U << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPDR9_Msk                 
+#define GPIO_PUPDR_PUPDR9_0              (0x1U << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPDR9_1              (0x2U << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPDR10_Pos           (20U)                                 
+#define GPIO_PUPDR_PUPDR10_Msk           (0x3U << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPDR10_Msk                
+#define GPIO_PUPDR_PUPDR10_0             (0x1U << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPDR10_1             (0x2U << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPDR11_Pos           (22U)                                 
+#define GPIO_PUPDR_PUPDR11_Msk           (0x3U << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPDR11_Msk                
+#define GPIO_PUPDR_PUPDR11_0             (0x1U << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPDR11_1             (0x2U << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPDR12_Pos           (24U)                                 
+#define GPIO_PUPDR_PUPDR12_Msk           (0x3U << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPDR12_Msk                
+#define GPIO_PUPDR_PUPDR12_0             (0x1U << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPDR12_1             (0x2U << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPDR13_Pos           (26U)                                 
+#define GPIO_PUPDR_PUPDR13_Msk           (0x3U << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPDR13_Msk                
+#define GPIO_PUPDR_PUPDR13_0             (0x1U << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPDR13_1             (0x2U << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPDR14_Pos           (28U)                                 
+#define GPIO_PUPDR_PUPDR14_Msk           (0x3U << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPDR14_Msk                
+#define GPIO_PUPDR_PUPDR14_0             (0x1U << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPDR14_1             (0x2U << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPDR15_Pos           (30U)                                 
+#define GPIO_PUPDR_PUPDR15_Msk           (0x3U << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPDR15_Msk                
+#define GPIO_PUPDR_PUPDR15_0             (0x1U << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPDR15_1             (0x2U << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0x80000000 */
+
+/*******************  Bit definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_0                       (0x00000001U)                         
+#define GPIO_IDR_1                       (0x00000002U)                         
+#define GPIO_IDR_2                       (0x00000004U)                         
+#define GPIO_IDR_3                       (0x00000008U)                         
+#define GPIO_IDR_4                       (0x00000010U)                         
+#define GPIO_IDR_5                       (0x00000020U)                         
+#define GPIO_IDR_6                       (0x00000040U)                         
+#define GPIO_IDR_7                       (0x00000080U)                         
+#define GPIO_IDR_8                       (0x00000100U)                         
+#define GPIO_IDR_9                       (0x00000200U)                         
+#define GPIO_IDR_10                      (0x00000400U)                         
+#define GPIO_IDR_11                      (0x00000800U)                         
+#define GPIO_IDR_12                      (0x00001000U)                         
+#define GPIO_IDR_13                      (0x00002000U)                         
+#define GPIO_IDR_14                      (0x00004000U)                         
+#define GPIO_IDR_15                      (0x00008000U)                         
+
+/******************  Bit definition for GPIO_ODR register  ********************/
+#define GPIO_ODR_0                       (0x00000001U)                         
+#define GPIO_ODR_1                       (0x00000002U)                         
+#define GPIO_ODR_2                       (0x00000004U)                         
+#define GPIO_ODR_3                       (0x00000008U)                         
+#define GPIO_ODR_4                       (0x00000010U)                         
+#define GPIO_ODR_5                       (0x00000020U)                         
+#define GPIO_ODR_6                       (0x00000040U)                         
+#define GPIO_ODR_7                       (0x00000080U)                         
+#define GPIO_ODR_8                       (0x00000100U)                         
+#define GPIO_ODR_9                       (0x00000200U)                         
+#define GPIO_ODR_10                      (0x00000400U)                         
+#define GPIO_ODR_11                      (0x00000800U)                         
+#define GPIO_ODR_12                      (0x00001000U)                         
+#define GPIO_ODR_13                      (0x00002000U)                         
+#define GPIO_ODR_14                      (0x00004000U)                         
+#define GPIO_ODR_15                      (0x00008000U)                         
+
+/****************** Bit definition for GPIO_BSRR register  ********************/
+#define GPIO_BSRR_BS_0                   (0x00000001U)                         
+#define GPIO_BSRR_BS_1                   (0x00000002U)                         
+#define GPIO_BSRR_BS_2                   (0x00000004U)                         
+#define GPIO_BSRR_BS_3                   (0x00000008U)                         
+#define GPIO_BSRR_BS_4                   (0x00000010U)                         
+#define GPIO_BSRR_BS_5                   (0x00000020U)                         
+#define GPIO_BSRR_BS_6                   (0x00000040U)                         
+#define GPIO_BSRR_BS_7                   (0x00000080U)                         
+#define GPIO_BSRR_BS_8                   (0x00000100U)                         
+#define GPIO_BSRR_BS_9                   (0x00000200U)                         
+#define GPIO_BSRR_BS_10                  (0x00000400U)                         
+#define GPIO_BSRR_BS_11                  (0x00000800U)                         
+#define GPIO_BSRR_BS_12                  (0x00001000U)                         
+#define GPIO_BSRR_BS_13                  (0x00002000U)                         
+#define GPIO_BSRR_BS_14                  (0x00004000U)                         
+#define GPIO_BSRR_BS_15                  (0x00008000U)                         
+#define GPIO_BSRR_BR_0                   (0x00010000U)                         
+#define GPIO_BSRR_BR_1                   (0x00020000U)                         
+#define GPIO_BSRR_BR_2                   (0x00040000U)                         
+#define GPIO_BSRR_BR_3                   (0x00080000U)                         
+#define GPIO_BSRR_BR_4                   (0x00100000U)                         
+#define GPIO_BSRR_BR_5                   (0x00200000U)                         
+#define GPIO_BSRR_BR_6                   (0x00400000U)                         
+#define GPIO_BSRR_BR_7                   (0x00800000U)                         
+#define GPIO_BSRR_BR_8                   (0x01000000U)                         
+#define GPIO_BSRR_BR_9                   (0x02000000U)                         
+#define GPIO_BSRR_BR_10                  (0x04000000U)                         
+#define GPIO_BSRR_BR_11                  (0x08000000U)                         
+#define GPIO_BSRR_BR_12                  (0x10000000U)                         
+#define GPIO_BSRR_BR_13                  (0x20000000U)                         
+#define GPIO_BSRR_BR_14                  (0x40000000U)                         
+#define GPIO_BSRR_BR_15                  (0x80000000U)                         
+
+/****************** Bit definition for GPIO_LCKR register  ********************/
+#define GPIO_LCKR_LCK0_Pos               (0U)                                  
+#define GPIO_LCKR_LCK0_Msk               (0x1U << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk                    
+#define GPIO_LCKR_LCK1_Pos               (1U)                                  
+#define GPIO_LCKR_LCK1_Msk               (0x1U << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk                    
+#define GPIO_LCKR_LCK2_Pos               (2U)                                  
+#define GPIO_LCKR_LCK2_Msk               (0x1U << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk                    
+#define GPIO_LCKR_LCK3_Pos               (3U)                                  
+#define GPIO_LCKR_LCK3_Msk               (0x1U << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk                    
+#define GPIO_LCKR_LCK4_Pos               (4U)                                  
+#define GPIO_LCKR_LCK4_Msk               (0x1U << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk                    
+#define GPIO_LCKR_LCK5_Pos               (5U)                                  
+#define GPIO_LCKR_LCK5_Msk               (0x1U << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk                    
+#define GPIO_LCKR_LCK6_Pos               (6U)                                  
+#define GPIO_LCKR_LCK6_Msk               (0x1U << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk                    
+#define GPIO_LCKR_LCK7_Pos               (7U)                                  
+#define GPIO_LCKR_LCK7_Msk               (0x1U << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk                    
+#define GPIO_LCKR_LCK8_Pos               (8U)                                  
+#define GPIO_LCKR_LCK8_Msk               (0x1U << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk                    
+#define GPIO_LCKR_LCK9_Pos               (9U)                                  
+#define GPIO_LCKR_LCK9_Msk               (0x1U << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk                    
+#define GPIO_LCKR_LCK10_Pos              (10U)                                 
+#define GPIO_LCKR_LCK10_Msk              (0x1U << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk                   
+#define GPIO_LCKR_LCK11_Pos              (11U)                                 
+#define GPIO_LCKR_LCK11_Msk              (0x1U << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk                   
+#define GPIO_LCKR_LCK12_Pos              (12U)                                 
+#define GPIO_LCKR_LCK12_Msk              (0x1U << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk                   
+#define GPIO_LCKR_LCK13_Pos              (13U)                                 
+#define GPIO_LCKR_LCK13_Msk              (0x1U << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk                   
+#define GPIO_LCKR_LCK14_Pos              (14U)                                 
+#define GPIO_LCKR_LCK14_Msk              (0x1U << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk                   
+#define GPIO_LCKR_LCK15_Pos              (15U)                                 
+#define GPIO_LCKR_LCK15_Msk              (0x1U << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk                   
+#define GPIO_LCKR_LCKK_Pos               (16U)                                 
+#define GPIO_LCKR_LCKK_Msk               (0x1U << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk                    
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFRL0_Pos              (0U)                                  
+#define GPIO_AFRL_AFRL0_Msk              (0xFU << GPIO_AFRL_AFRL0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFRL0_Msk                   
+#define GPIO_AFRL_AFRL1_Pos              (4U)                                  
+#define GPIO_AFRL_AFRL1_Msk              (0xFU << GPIO_AFRL_AFRL1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFRL1_Msk                   
+#define GPIO_AFRL_AFRL2_Pos              (8U)                                  
+#define GPIO_AFRL_AFRL2_Msk              (0xFU << GPIO_AFRL_AFRL2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFRL2_Msk                   
+#define GPIO_AFRL_AFRL3_Pos              (12U)                                 
+#define GPIO_AFRL_AFRL3_Msk              (0xFU << GPIO_AFRL_AFRL3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFRL3_Msk                   
+#define GPIO_AFRL_AFRL4_Pos              (16U)                                 
+#define GPIO_AFRL_AFRL4_Msk              (0xFU << GPIO_AFRL_AFRL4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFRL4_Msk                   
+#define GPIO_AFRL_AFRL5_Pos              (20U)                                 
+#define GPIO_AFRL_AFRL5_Msk              (0xFU << GPIO_AFRL_AFRL5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFRL5_Msk                   
+#define GPIO_AFRL_AFRL6_Pos              (24U)                                 
+#define GPIO_AFRL_AFRL6_Msk              (0xFU << GPIO_AFRL_AFRL6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFRL6_Msk                   
+#define GPIO_AFRL_AFRL7_Pos              (28U)                                 
+#define GPIO_AFRL_AFRL7_Msk              (0xFU << GPIO_AFRL_AFRL7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFRL7_Msk                   
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFRH0_Pos              (0U)                                  
+#define GPIO_AFRH_AFRH0_Msk              (0xFU << GPIO_AFRH_AFRH0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFRH0_Msk                   
+#define GPIO_AFRH_AFRH1_Pos              (4U)                                  
+#define GPIO_AFRH_AFRH1_Msk              (0xFU << GPIO_AFRH_AFRH1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFRH1_Msk                   
+#define GPIO_AFRH_AFRH2_Pos              (8U)                                  
+#define GPIO_AFRH_AFRH2_Msk              (0xFU << GPIO_AFRH_AFRH2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFRH2_Msk                   
+#define GPIO_AFRH_AFRH3_Pos              (12U)                                 
+#define GPIO_AFRH_AFRH3_Msk              (0xFU << GPIO_AFRH_AFRH3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFRH3_Msk                   
+#define GPIO_AFRH_AFRH4_Pos              (16U)                                 
+#define GPIO_AFRH_AFRH4_Msk              (0xFU << GPIO_AFRH_AFRH4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFRH4_Msk                   
+#define GPIO_AFRH_AFRH5_Pos              (20U)                                 
+#define GPIO_AFRH_AFRH5_Msk              (0xFU << GPIO_AFRH_AFRH5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFRH5_Msk                   
+#define GPIO_AFRH_AFRH6_Pos              (24U)                                 
+#define GPIO_AFRH_AFRH6_Msk              (0xFU << GPIO_AFRH_AFRH6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFRH6_Msk                   
+#define GPIO_AFRH_AFRH7_Pos              (28U)                                 
+#define GPIO_AFRH_AFRH7_Msk              (0xFU << GPIO_AFRH_AFRH7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFRH7_Msk                   
+
+/****************** Bit definition for GPIO_BRR register  *********************/
+#define GPIO_BRR_BR_0                    (0x00000001U)                         
+#define GPIO_BRR_BR_1                    (0x00000002U)                         
+#define GPIO_BRR_BR_2                    (0x00000004U)                         
+#define GPIO_BRR_BR_3                    (0x00000008U)                         
+#define GPIO_BRR_BR_4                    (0x00000010U)                         
+#define GPIO_BRR_BR_5                    (0x00000020U)                         
+#define GPIO_BRR_BR_6                    (0x00000040U)                         
+#define GPIO_BRR_BR_7                    (0x00000080U)                         
+#define GPIO_BRR_BR_8                    (0x00000100U)                         
+#define GPIO_BRR_BR_9                    (0x00000200U)                         
+#define GPIO_BRR_BR_10                   (0x00000400U)                         
+#define GPIO_BRR_BR_11                   (0x00000800U)                         
+#define GPIO_BRR_BR_12                   (0x00001000U)                         
+#define GPIO_BRR_BR_13                   (0x00002000U)                         
+#define GPIO_BRR_BR_14                   (0x00004000U)                         
+#define GPIO_BRR_BR_15                   (0x00008000U)                         
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos               (0U)                                      
+#define I2C_CR1_PE_Msk               (0x1U << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos             (1U)                                      
+#define I2C_CR1_TXIE_Msk             (0x1U << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos             (2U)                                      
+#define I2C_CR1_RXIE_Msk             (0x1U << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos           (3U)                                      
+#define I2C_CR1_ADDRIE_Msk           (0x1U << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos           (4U)                                      
+#define I2C_CR1_NACKIE_Msk           (0x1U << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos           (5U)                                      
+#define I2C_CR1_STOPIE_Msk           (0x1U << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos             (6U)                                      
+#define I2C_CR1_TCIE_Msk             (0x1U << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos            (7U)                                      
+#define I2C_CR1_ERRIE_Msk            (0x1U << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos              (8U)                                      
+#define I2C_CR1_DNF_Msk              (0xFU << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos           (12U)                                     
+#define I2C_CR1_ANFOFF_Msk           (0x1U << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST_Pos            (13U)                                     
+#define I2C_CR1_SWRST_Msk            (0x1U << I2C_CR1_SWRST_Pos)               /*!< 0x00002000 */
+#define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset */
+#define I2C_CR1_TXDMAEN_Pos          (14U)                                     
+#define I2C_CR1_TXDMAEN_Msk          (0x1U << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos          (15U)                                     
+#define I2C_CR1_RXDMAEN_Msk          (0x1U << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos              (16U)                                     
+#define I2C_CR1_SBC_Msk              (0x1U << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos        (17U)                                     
+#define I2C_CR1_NOSTRETCH_Msk        (0x1U << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos            (18U)                                     
+#define I2C_CR1_WUPEN_Msk            (0x1U << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos             (19U)                                     
+#define I2C_CR1_GCEN_Msk             (0x1U << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos           (20U)                                     
+#define I2C_CR1_SMBHEN_Msk           (0x1U << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos           (21U)                                     
+#define I2C_CR1_SMBDEN_Msk           (0x1U << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos          (22U)                                     
+#define I2C_CR1_ALERTEN_Msk          (0x1U << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos            (23U)                                     
+#define I2C_CR1_PECEN_Msk            (0x1U << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
+
+/* Legacy defines */
+#define I2C_CR1_DFN I2C_CR1_DNF
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos             (0U)                                      
+#define I2C_CR2_SADD_Msk             (0x3FFU << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos           (10U)                                     
+#define I2C_CR2_RD_WRN_Msk           (0x1U << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos            (11U)                                     
+#define I2C_CR2_ADD10_Msk            (0x1U << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos          (12U)                                     
+#define I2C_CR2_HEAD10R_Msk          (0x1U << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos            (13U)                                     
+#define I2C_CR2_START_Msk            (0x1U << I2C_CR2_START_Pos)               /*!< 0x00002000 */
+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
+#define I2C_CR2_STOP_Pos             (14U)                                     
+#define I2C_CR2_STOP_Msk             (0x1U << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos             (15U)                                     
+#define I2C_CR2_NACK_Msk             (0x1U << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos           (16U)                                     
+#define I2C_CR2_NBYTES_Msk           (0xFFU << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos           (24U)                                     
+#define I2C_CR2_RELOAD_Msk           (0x1U << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos          (25U)                                     
+#define I2C_CR2_AUTOEND_Msk          (0x1U << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos          (26U)                                     
+#define I2C_CR2_PECBYTE_Msk          (0x1U << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos             (0U)                                      
+#define I2C_OAR1_OA1_Msk             (0x3FFU << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos         (10U)                                     
+#define I2C_OAR1_OA1MODE_Msk         (0x1U << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos           (15U)                                     
+#define I2C_OAR1_OA1EN_Msk           (0x1U << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  *******************/
+#define I2C_OAR2_OA2_Pos             (1U)                                      
+#define I2C_OAR2_OA2_Msk             (0x7FU << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
+#define I2C_OAR2_OA2MSK_Pos          (8U)                                      
+#define I2C_OAR2_OA2MSK_Msk          (0x7U << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
+#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
+#define I2C_OAR2_OA2MASK01_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK01_Msk       (0x1U << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
+#define I2C_OAR2_OA2MASK02_Pos       (9U)                                      
+#define I2C_OAR2_OA2MASK02_Msk       (0x1U << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK03_Msk       (0x3U << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos       (10U)                                     
+#define I2C_OAR2_OA2MASK04_Msk       (0x1U << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK05_Msk       (0x5U << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos       (9U)                                      
+#define I2C_OAR2_OA2MASK06_Msk       (0x3U << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
+#define I2C_OAR2_OA2MASK07_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK07_Msk       (0x7U << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
+#define I2C_OAR2_OA2EN_Pos           (15U)                                     
+#define I2C_OAR2_OA2EN_Msk           (0x1U << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
+
+/*******************  Bit definition for I2C_TIMINGR register *****************/
+#define I2C_TIMINGR_SCLL_Pos         (0U)                                      
+#define I2C_TIMINGR_SCLL_Msk         (0xFFU << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos         (8U)                                      
+#define I2C_TIMINGR_SCLH_Msk         (0xFFU << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos       (16U)                                     
+#define I2C_TIMINGR_SDADEL_Msk       (0xFU << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos       (20U)                                     
+#define I2C_TIMINGR_SCLDEL_Msk       (0xFU << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos        (28U)                                     
+#define I2C_TIMINGR_PRESC_Msk        (0xFU << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *****************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)                                      
+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)                                     
+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1U << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)                                     
+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)                                     
+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)                                     
+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1U << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos              (0U)                                      
+#define I2C_ISR_TXE_Msk              (0x1U << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos             (1U)                                      
+#define I2C_ISR_TXIS_Msk             (0x1U << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos             (2U)                                      
+#define I2C_ISR_RXNE_Msk             (0x1U << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos             (3U)                                      
+#define I2C_ISR_ADDR_Msk             (0x1U << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos            (4U)                                      
+#define I2C_ISR_NACKF_Msk            (0x1U << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos            (5U)                                      
+#define I2C_ISR_STOPF_Msk            (0x1U << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos               (6U)                                      
+#define I2C_ISR_TC_Msk               (0x1U << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos              (7U)                                      
+#define I2C_ISR_TCR_Msk              (0x1U << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos             (8U)                                      
+#define I2C_ISR_BERR_Msk             (0x1U << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
+#define I2C_ISR_ARLO_Pos             (9U)                                      
+#define I2C_ISR_ARLO_Msk             (0x1U << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos              (10U)                                     
+#define I2C_ISR_OVR_Msk              (0x1U << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos           (11U)                                     
+#define I2C_ISR_PECERR_Msk           (0x1U << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos          (12U)                                     
+#define I2C_ISR_TIMEOUT_Msk          (0x1U << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos            (13U)                                     
+#define I2C_ISR_ALERT_Msk            (0x1U << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos             (15U)                                     
+#define I2C_ISR_BUSY_Msk             (0x1U << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
+#define I2C_ISR_DIR_Pos              (16U)                                     
+#define I2C_ISR_DIR_Msk              (0x1U << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos          (17U)                                     
+#define I2C_ISR_ADDCODE_Msk          (0x7FU << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos           (3U)                                      
+#define I2C_ICR_ADDRCF_Msk           (0x1U << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos           (4U)                                      
+#define I2C_ICR_NACKCF_Msk           (0x1U << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos           (5U)                                      
+#define I2C_ICR_STOPCF_Msk           (0x1U << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos           (8U)                                      
+#define I2C_ICR_BERRCF_Msk           (0x1U << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos           (9U)                                      
+#define I2C_ICR_ARLOCF_Msk           (0x1U << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos            (10U)                                     
+#define I2C_ICR_OVRCF_Msk            (0x1U << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos            (11U)                                     
+#define I2C_ICR_PECCF_Msk            (0x1U << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos         (12U)                                     
+#define I2C_ICR_TIMOUTCF_Msk         (0x1U << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos          (13U)                                     
+#define I2C_ICR_ALERTCF_Msk          (0x1U << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  ********************/
+#define I2C_PECR_PEC_Pos             (0U)                                      
+#define I2C_PECR_PEC_Msk             (0xFFU << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos          (0U)                                      
+#define I2C_RXDR_RXDATA_Msk          (0xFFU << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos          (0U)                                      
+#define I2C_TXDR_TXDATA_Msk          (0xFFU << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG (IWDG)                      */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos      (0U)                                              
+#define IWDG_KR_KEY_Msk      (0xFFFFU << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos       (0U)                                              
+#define IWDG_PR_PR_Msk       (0x7U << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0         (0x1U << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
+#define IWDG_PR_PR_1         (0x2U << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
+#define IWDG_PR_PR_2         (0x4U << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos      (0U)                                              
+#define IWDG_RLR_RL_Msk      (0xFFFU << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos      (0U)                                              
+#define IWDG_SR_PVU_Msk      (0x1U << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos      (1U)                                              
+#define IWDG_SR_RVU_Msk      (0x1U << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos      (2U)                                              
+#define IWDG_SR_WVU_Msk      (0x1U << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_WINR_WIN_Pos    (0U)                                              
+#define IWDG_WINR_WIN_Msk    (0xFFFU << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
+/********************  Bit definition for PWR_CR register  ********************/
+#define PWR_CR_LPDS_Pos            (0U)                                        
+#define PWR_CR_LPDS_Msk            (0x1U << PWR_CR_LPDS_Pos)                   /*!< 0x00000001 */
+#define PWR_CR_LPDS                PWR_CR_LPDS_Msk                             /*!< Low-power Deepsleep */
+#define PWR_CR_PDDS_Pos            (1U)                                        
+#define PWR_CR_PDDS_Msk            (0x1U << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
+#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos            (2U)                                        
+#define PWR_CR_CWUF_Msk            (0x1U << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
+#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos            (3U)                                        
+#define PWR_CR_CSBF_Msk            (0x1U << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
+#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos            (4U)                                        
+#define PWR_CR_PVDE_Msk            (0x1U << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
+#define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos             (5U)                                        
+#define PWR_CR_PLS_Msk             (0x7U << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
+#define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0               (0x1U << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
+#define PWR_CR_PLS_1               (0x2U << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
+#define PWR_CR_PLS_2               (0x4U << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
+
+#define PWR_CR_DBP_Pos             (8U)                                        
+#define PWR_CR_DBP_Msk             (0x1U << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
+#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define PWR_CSR_WUF_Pos            (0U)                                        
+#define PWR_CSR_WUF_Msk            (0x1U << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
+#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos            (1U)                                        
+#define PWR_CSR_SBF_Msk            (0x1U << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
+#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos           (2U)                                        
+#define PWR_CSR_PVDO_Msk           (0x1U << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
+#define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF_Pos    (3U)                                        
+#define PWR_CSR_VREFINTRDYF_Msk    (0x1U << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
+
+#define PWR_CSR_EWUP1_Pos          (8U)                                        
+#define PWR_CSR_EWUP1_Msk          (0x1U << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
+#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2_Pos          (9U)                                        
+#define PWR_CSR_EWUP2_Msk          (0x1U << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
+#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3_Pos          (10U)                                       
+#define PWR_CSR_EWUP3_Msk          (0x1U << PWR_CSR_EWUP3_Pos)                 /*!< 0x00000400 */
+#define PWR_CSR_EWUP3              PWR_CSR_EWUP3_Msk                           /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions  (not present on all devices in the STM32F3 serie)
+*/
+#define RCC_PLLSRC_PREDIV1_SUPPORT  /*!< PREDIV support used as PLL source input  */
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_HSION_Pos                         (0U)                          
+#define RCC_CR_HSION_Msk                         (0x1U << RCC_CR_HSION_Pos)    /*!< 0x00000001 */
+#define RCC_CR_HSION                             RCC_CR_HSION_Msk              
+#define RCC_CR_HSIRDY_Pos                        (1U)                          
+#define RCC_CR_HSIRDY_Msk                        (0x1U << RCC_CR_HSIRDY_Pos)   /*!< 0x00000002 */
+#define RCC_CR_HSIRDY                            RCC_CR_HSIRDY_Msk             
+
+#define RCC_CR_HSITRIM_Pos                       (3U)                          
+#define RCC_CR_HSITRIM_Msk                       (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM                           RCC_CR_HSITRIM_Msk            
+#define RCC_CR_HSITRIM_0                         (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1                         (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2                         (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3                         (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4                         (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos                        (8U)                          
+#define RCC_CR_HSICAL_Msk                        (0xFFU << RCC_CR_HSICAL_Pos)  /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL                            RCC_CR_HSICAL_Msk             
+#define RCC_CR_HSICAL_0                          (0x01U << RCC_CR_HSICAL_Pos)  /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1                          (0x02U << RCC_CR_HSICAL_Pos)  /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2                          (0x04U << RCC_CR_HSICAL_Pos)  /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3                          (0x08U << RCC_CR_HSICAL_Pos)  /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4                          (0x10U << RCC_CR_HSICAL_Pos)  /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5                          (0x20U << RCC_CR_HSICAL_Pos)  /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6                          (0x40U << RCC_CR_HSICAL_Pos)  /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7                          (0x80U << RCC_CR_HSICAL_Pos)  /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos                         (16U)                         
+#define RCC_CR_HSEON_Msk                         (0x1U << RCC_CR_HSEON_Pos)    /*!< 0x00010000 */
+#define RCC_CR_HSEON                             RCC_CR_HSEON_Msk              
+#define RCC_CR_HSERDY_Pos                        (17U)                         
+#define RCC_CR_HSERDY_Msk                        (0x1U << RCC_CR_HSERDY_Pos)   /*!< 0x00020000 */
+#define RCC_CR_HSERDY                            RCC_CR_HSERDY_Msk             
+#define RCC_CR_HSEBYP_Pos                        (18U)                         
+#define RCC_CR_HSEBYP_Msk                        (0x1U << RCC_CR_HSEBYP_Pos)   /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                            RCC_CR_HSEBYP_Msk             
+#define RCC_CR_CSSON_Pos                         (19U)                         
+#define RCC_CR_CSSON_Msk                         (0x1U << RCC_CR_CSSON_Pos)    /*!< 0x00080000 */
+#define RCC_CR_CSSON                             RCC_CR_CSSON_Msk              
+#define RCC_CR_PLLON_Pos                         (24U)                         
+#define RCC_CR_PLLON_Msk                         (0x1U << RCC_CR_PLLON_Pos)    /*!< 0x01000000 */
+#define RCC_CR_PLLON                             RCC_CR_PLLON_Msk              
+#define RCC_CR_PLLRDY_Pos                        (25U)                         
+#define RCC_CR_PLLRDY_Msk                        (0x1U << RCC_CR_PLLRDY_Pos)   /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                            RCC_CR_PLLRDY_Msk             
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos                          (0U)                          
+#define RCC_CFGR_SW_Msk                          (0x3U << RCC_CFGR_SW_Pos)     /*!< 0x00000003 */
+#define RCC_CFGR_SW                              RCC_CFGR_SW_Msk               /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                            (0x1U << RCC_CFGR_SW_Pos)     /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                            (0x2U << RCC_CFGR_SW_Pos)     /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI                          (0x00000000U)                 /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE                          (0x00000001U)                 /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL                          (0x00000002U)                 /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos                         (2U)                          
+#define RCC_CFGR_SWS_Msk                         (0x3U << RCC_CFGR_SWS_Pos)    /*!< 0x0000000C */
+#define RCC_CFGR_SWS                             RCC_CFGR_SWS_Msk              /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                           (0x1U << RCC_CFGR_SWS_Pos)    /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1                           (0x2U << RCC_CFGR_SWS_Pos)    /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI                         (0x00000000U)                 /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE                         (0x00000004U)                 /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL                         (0x00000008U)                 /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos                        (4U)                          
+#define RCC_CFGR_HPRE_Msk                        (0xFU << RCC_CFGR_HPRE_Pos)   /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE                            RCC_CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0                          (0x1U << RCC_CFGR_HPRE_Pos)   /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1                          (0x2U << RCC_CFGR_HPRE_Pos)   /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2                          (0x4U << RCC_CFGR_HPRE_Pos)   /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3                          (0x8U << RCC_CFGR_HPRE_Pos)   /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1                       (0x00000000U)                 /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2                       (0x00000080U)                 /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4                       (0x00000090U)                 /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8                       (0x000000A0U)                 /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16                      (0x000000B0U)                 /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64                      (0x000000C0U)                 /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128                     (0x000000D0U)                 /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256                     (0x000000E0U)                 /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512                     (0x000000F0U)                 /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos                       (8U)                          
+#define RCC_CFGR_PPRE1_Msk                       (0x7U << RCC_CFGR_PPRE1_Pos)  /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1                           RCC_CFGR_PPRE1_Msk            /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0                         (0x1U << RCC_CFGR_PPRE1_Pos)  /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1                         (0x2U << RCC_CFGR_PPRE1_Pos)  /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2                         (0x4U << RCC_CFGR_PPRE1_Pos)  /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1                      (0x00000000U)                 /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2                      (0x00000400U)                 /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4                      (0x00000500U)                 /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8                      (0x00000600U)                 /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16                     (0x00000700U)                 /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos                       (11U)                         
+#define RCC_CFGR_PPRE2_Msk                       (0x7U << RCC_CFGR_PPRE2_Pos)  /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2                           RCC_CFGR_PPRE2_Msk            /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0                         (0x1U << RCC_CFGR_PPRE2_Pos)  /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1                         (0x2U << RCC_CFGR_PPRE2_Pos)  /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2                         (0x4U << RCC_CFGR_PPRE2_Pos)  /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1                      (0x00000000U)                 /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2                      (0x00002000U)                 /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4                      (0x00002800U)                 /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8                      (0x00003000U)                 /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16                     (0x00003800U)                 /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_PLLSRC_Pos                      (15U)                         
+#define RCC_CFGR_PLLSRC_Msk                      (0x3U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00018000 */
+#define RCC_CFGR_PLLSRC                          RCC_CFGR_PLLSRC_Msk           /*!< PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_PREDIV               (0x00008000U)                 /*!< HSI/PREDIV clock as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE_PREDIV               (0x00010000U)                 /*!< HSE/PREDIV clock selected as PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE_Pos                    (17U)                         
+#define RCC_CFGR_PLLXTPRE_Msk                    (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_PLLXTPRE                        RCC_CFGR_PLLXTPRE_Msk         /*!< HSE divider for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1        (0x00000000U)                 /*!< HSE/PREDIV clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2        (0x00020000U)                 /*!< HSE/PREDIV clock divided by 2 for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos                      (18U)                         
+#define RCC_CFGR_PLLMUL_Msk                      (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL                          RCC_CFGR_PLLMUL_Msk           /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0                        (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1                        (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2                        (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3                        (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL2                         (0x00000000U)                 /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMUL3                         (0x00040000U)                 /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMUL4                         (0x00080000U)                 /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMUL5                         (0x000C0000U)                 /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMUL6                         (0x00100000U)                 /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMUL7                         (0x00140000U)                 /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMUL8                         (0x00180000U)                 /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMUL9                         (0x001C0000U)                 /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMUL10                        (0x00200000U)                 /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMUL11                        (0x00240000U)                 /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMUL12                        (0x00280000U)                 /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMUL13                        (0x002C0000U)                 /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMUL14                        (0x00300000U)                 /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMUL15                        (0x00340000U)                 /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMUL16                        (0x00380000U)                 /*!< PLL input clock*16 */
+
+/*!< USB configuration */
+#define RCC_CFGR_USBPRE_Pos                      (22U)                         
+#define RCC_CFGR_USBPRE_Msk                      (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_USBPRE                          RCC_CFGR_USBPRE_Msk           /*!< USB prescaler */
+
+#define RCC_CFGR_USBPRE_DIV1_5                   (0x00000000U)                 /*!< USB prescaler is PLL clock divided by 1.5 */
+#define RCC_CFGR_USBPRE_DIV1                     (0x00400000U)                 /*!< USB prescaler is PLL clock divided by 1 */
+
+/*!< I2S configuration */
+#define RCC_CFGR_I2SSRC_Pos                      (23U)                         
+#define RCC_CFGR_I2SSRC_Msk                      (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_I2SSRC                          RCC_CFGR_I2SSRC_Msk           /*!< I2S external clock source selection */
+
+#define RCC_CFGR_I2SSRC_SYSCLK                   (0x00000000U)                 /*!< System clock selected as I2S clock source */
+#define RCC_CFGR_I2SSRC_EXT                      (0x00800000U)                 /*!< External clock selected as I2S clock source */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO_Pos                         (24U)                         
+#define RCC_CFGR_MCO_Msk                         (0x7U << RCC_CFGR_MCO_Pos)    /*!< 0x07000000 */
+#define RCC_CFGR_MCO                             RCC_CFGR_MCO_Msk              /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0                           (0x1U << RCC_CFGR_MCO_Pos)    /*!< 0x01000000 */
+#define RCC_CFGR_MCO_1                           (0x2U << RCC_CFGR_MCO_Pos)    /*!< 0x02000000 */
+#define RCC_CFGR_MCO_2                           (0x4U << RCC_CFGR_MCO_Pos)    /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO_NOCLOCK                     (0x00000000U)                 /*!< No clock */
+#define RCC_CFGR_MCO_LSI                         (0x02000000U)                 /*!< LSI clock selected as MCO source */
+#define RCC_CFGR_MCO_LSE                         (0x03000000U)                 /*!< LSE clock selected as MCO source */
+#define RCC_CFGR_MCO_SYSCLK                      (0x04000000U)                 /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI                         (0x05000000U)                 /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE                         (0x06000000U)                 /*!< HSE clock selected as MCO source  */
+#define RCC_CFGR_MCO_PLL                         (0x07000000U)                 /*!< PLL clock divided by 2 selected as MCO source */
+
+#define RCC_CFGR_MCOPRE_Pos                      (28U)                         
+#define RCC_CFGR_MCOPRE_Msk                      (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE                          RCC_CFGR_MCOPRE_Msk           /*!< MCOPRE[3:0] bits (Microcontroller Clock Output Prescaler) */
+#define RCC_CFGR_MCOPRE_0                        (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1                        (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2                        (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1                     (0x00000000U)                 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2                     (0x10000000U)                 /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4                     (0x20000000U)                 /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8                     (0x30000000U)                 /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16                    (0x40000000U)                 /*!< MCO is divided by 16 */
+#define RCC_CFGR_MCOPRE_DIV32                    (0x50000000U)                 /*!< MCO is divided by 32 */
+#define RCC_CFGR_MCOPRE_DIV64                    (0x60000000U)                 /*!< MCO is divided by 64 */
+#define RCC_CFGR_MCOPRE_DIV128                   (0x70000000U)                 /*!< MCO is divided by 128 */
+
+#define RCC_CFGR_PLLNODIV_Pos                    (31U)                         
+#define RCC_CFGR_PLLNODIV_Msk                    (0x1U << RCC_CFGR_PLLNODIV_Pos) /*!< 0x80000000 */
+#define RCC_CFGR_PLLNODIV                        RCC_CFGR_PLLNODIV_Msk         /*!< Do not divide PLL to MCO */
+
+/* Reference defines */
+#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO
+#define RCC_CFGR_MCOSEL_0                    RCC_CFGR_MCO_0
+#define RCC_CFGR_MCOSEL_1                    RCC_CFGR_MCO_1
+#define RCC_CFGR_MCOSEL_2                    RCC_CFGR_MCO_2
+#define RCC_CFGR_MCOSEL_NOCLOCK              RCC_CFGR_MCO_NOCLOCK
+#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCO_LSI
+#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCO_LSE
+#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCO_SYSCLK
+#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCO_HSI
+#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCO_HSE
+#define RCC_CFGR_MCOSEL_PLL_DIV2             RCC_CFGR_MCO_PLL
+
+/*********************  Bit definition for RCC_CIR register  ********************/
+#define RCC_CIR_LSIRDYF_Pos                      (0U)                          
+#define RCC_CIR_LSIRDYF_Msk                      (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF                          RCC_CIR_LSIRDYF_Msk           /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF_Pos                      (1U)                          
+#define RCC_CIR_LSERDYF_Msk                      (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF                          RCC_CIR_LSERDYF_Msk           /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF_Pos                      (2U)                          
+#define RCC_CIR_HSIRDYF_Msk                      (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF                          RCC_CIR_HSIRDYF_Msk           /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF_Pos                      (3U)                          
+#define RCC_CIR_HSERDYF_Msk                      (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF                          RCC_CIR_HSERDYF_Msk           /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF_Pos                      (4U)                          
+#define RCC_CIR_PLLRDYF_Msk                      (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF                          RCC_CIR_PLLRDYF_Msk           /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF_Pos                         (7U)                          
+#define RCC_CIR_CSSF_Msk                         (0x1U << RCC_CIR_CSSF_Pos)    /*!< 0x00000080 */
+#define RCC_CIR_CSSF                             RCC_CIR_CSSF_Msk              /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE_Pos                     (8U)                          
+#define RCC_CIR_LSIRDYIE_Msk                     (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE                         RCC_CIR_LSIRDYIE_Msk          /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE_Pos                     (9U)                          
+#define RCC_CIR_LSERDYIE_Msk                     (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE                         RCC_CIR_LSERDYIE_Msk          /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE_Pos                     (10U)                         
+#define RCC_CIR_HSIRDYIE_Msk                     (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE                         RCC_CIR_HSIRDYIE_Msk          /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE_Pos                     (11U)                         
+#define RCC_CIR_HSERDYIE_Msk                     (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE                         RCC_CIR_HSERDYIE_Msk          /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE_Pos                     (12U)                         
+#define RCC_CIR_PLLRDYIE_Msk                     (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE                         RCC_CIR_PLLRDYIE_Msk          /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC_Pos                      (16U)                         
+#define RCC_CIR_LSIRDYC_Msk                      (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC                          RCC_CIR_LSIRDYC_Msk           /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC_Pos                      (17U)                         
+#define RCC_CIR_LSERDYC_Msk                      (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC                          RCC_CIR_LSERDYC_Msk           /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC_Pos                      (18U)                         
+#define RCC_CIR_HSIRDYC_Msk                      (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC                          RCC_CIR_HSIRDYC_Msk           /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC_Pos                      (19U)                         
+#define RCC_CIR_HSERDYC_Msk                      (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC                          RCC_CIR_HSERDYC_Msk           /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC_Pos                      (20U)                         
+#define RCC_CIR_PLLRDYC_Msk                      (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC                          RCC_CIR_PLLRDYC_Msk           /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC_Pos                         (23U)                         
+#define RCC_CIR_CSSC_Msk                         (0x1U << RCC_CIR_CSSC_Pos)    /*!< 0x00800000 */
+#define RCC_CIR_CSSC                             RCC_CIR_CSSC_Msk              /*!< Clock Security System Interrupt Clear */
+
+/******************  Bit definition for RCC_APB2RSTR register  *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos               (0U)                          
+#define RCC_APB2RSTR_SYSCFGRST_Msk               (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM1RST_Pos                 (11U)                         
+#define RCC_APB2RSTR_TIM1RST_Msk                 (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos                 (12U)                         
+#define RCC_APB2RSTR_SPI1RST_Msk                 (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 reset */
+#define RCC_APB2RSTR_TIM8RST_Pos                 (13U)                         
+#define RCC_APB2RSTR_TIM8RST_Msk                 (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_TIM8RST                     RCC_APB2RSTR_TIM8RST_Msk      /*!< TIM8 reset */
+#define RCC_APB2RSTR_USART1RST_Pos               (14U)                         
+#define RCC_APB2RSTR_USART1RST_Msk               (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 reset */
+#define RCC_APB2RSTR_SPI4RST_Pos                 (15U)                         
+#define RCC_APB2RSTR_SPI4RST_Msk                 (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00008000 */
+#define RCC_APB2RSTR_SPI4RST                     RCC_APB2RSTR_SPI4RST_Msk      /*!< SPI4 reset */
+#define RCC_APB2RSTR_TIM15RST_Pos                (16U)                         
+#define RCC_APB2RSTR_TIM15RST_Msk                (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST                    RCC_APB2RSTR_TIM15RST_Msk     /*!< TIM15 reset */
+#define RCC_APB2RSTR_TIM16RST_Pos                (17U)                         
+#define RCC_APB2RSTR_TIM16RST_Msk                (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 reset */
+#define RCC_APB2RSTR_TIM17RST_Pos                (18U)                         
+#define RCC_APB2RSTR_TIM17RST_Msk                (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 reset */
+#define RCC_APB2RSTR_TIM20RST_Pos                (20U)                         
+#define RCC_APB2RSTR_TIM20RST_Msk                (0x1U << RCC_APB2RSTR_TIM20RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_TIM20RST                    RCC_APB2RSTR_TIM20RST_Msk     /*!< TIM20 reset */
+
+/******************  Bit definition for RCC_APB1RSTR register  ******************/
+#define RCC_APB1RSTR_TIM2RST_Pos                 (0U)                          
+#define RCC_APB1RSTR_TIM2RST_Msk                 (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST                     RCC_APB1RSTR_TIM2RST_Msk      /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos                 (1U)                          
+#define RCC_APB1RSTR_TIM3RST_Msk                 (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 reset */
+#define RCC_APB1RSTR_TIM4RST_Pos                 (2U)                          
+#define RCC_APB1RSTR_TIM4RST_Msk                 (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST                     RCC_APB1RSTR_TIM4RST_Msk      /*!< Timer 4 reset */
+#define RCC_APB1RSTR_TIM6RST_Pos                 (4U)                          
+#define RCC_APB1RSTR_TIM6RST_Msk                 (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST                     RCC_APB1RSTR_TIM6RST_Msk      /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST_Pos                 (5U)                          
+#define RCC_APB1RSTR_TIM7RST_Msk                 (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST                     RCC_APB1RSTR_TIM7RST_Msk      /*!< Timer 7 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos                 (11U)                         
+#define RCC_APB1RSTR_WWDGRST_Msk                 (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_SPI2RST_Pos                 (14U)                         
+#define RCC_APB1RSTR_SPI2RST_Msk                 (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST                     RCC_APB1RSTR_SPI2RST_Msk      /*!< SPI2 reset */
+#define RCC_APB1RSTR_SPI3RST_Pos                 (15U)                         
+#define RCC_APB1RSTR_SPI3RST_Msk                 (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST                     RCC_APB1RSTR_SPI3RST_Msk      /*!< SPI3 reset */
+#define RCC_APB1RSTR_USART2RST_Pos               (17U)                         
+#define RCC_APB1RSTR_USART2RST_Msk               (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST                   RCC_APB1RSTR_USART2RST_Msk    /*!< USART 2 reset */
+#define RCC_APB1RSTR_USART3RST_Pos               (18U)                         
+#define RCC_APB1RSTR_USART3RST_Msk               (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST                   RCC_APB1RSTR_USART3RST_Msk    /*!< USART 3 reset */
+#define RCC_APB1RSTR_UART4RST_Pos                (19U)                         
+#define RCC_APB1RSTR_UART4RST_Msk                (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART4RST                    RCC_APB1RSTR_UART4RST_Msk     /*!< UART 4 reset */
+#define RCC_APB1RSTR_UART5RST_Pos                (20U)                         
+#define RCC_APB1RSTR_UART5RST_Msk                (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART5RST                    RCC_APB1RSTR_UART5RST_Msk     /*!< UART 5 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos                 (21U)                         
+#define RCC_APB1RSTR_I2C1RST_Msk                 (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos                 (22U)                         
+#define RCC_APB1RSTR_I2C2RST_Msk                 (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST                     RCC_APB1RSTR_I2C2RST_Msk      /*!< I2C 2 reset */
+#define RCC_APB1RSTR_USBRST_Pos                  (23U)                         
+#define RCC_APB1RSTR_USBRST_Msk                  (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_USBRST                      RCC_APB1RSTR_USBRST_Msk       /*!< USB reset */
+#define RCC_APB1RSTR_CANRST_Pos                  (25U)                         
+#define RCC_APB1RSTR_CANRST_Msk                  (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR_CANRST                      RCC_APB1RSTR_CANRST_Msk       /*!< CAN reset */
+#define RCC_APB1RSTR_PWRRST_Pos                  (28U)                         
+#define RCC_APB1RSTR_PWRRST_Msk                  (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR reset */
+#define RCC_APB1RSTR_DAC1RST_Pos                 (29U)                         
+#define RCC_APB1RSTR_DAC1RST_Msk                 (0x1U << RCC_APB1RSTR_DAC1RST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DAC1RST                     RCC_APB1RSTR_DAC1RST_Msk      /*!< DAC 1 reset */
+#define RCC_APB1RSTR_I2C3RST_Pos                 (30U)                         
+#define RCC_APB1RSTR_I2C3RST_Msk                 (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR_I2C3RST                     RCC_APB1RSTR_I2C3RST_Msk      /*!< I2C 3 reset */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define RCC_AHBENR_DMA1EN_Pos                    (0U)                          
+#define RCC_AHBENR_DMA1EN_Msk                    (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMA1EN                        RCC_AHBENR_DMA1EN_Msk         /*!< DMA1 clock enable */
+#define RCC_AHBENR_DMA2EN_Pos                    (1U)                          
+#define RCC_AHBENR_DMA2EN_Msk                    (0x1U << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */
+#define RCC_AHBENR_DMA2EN                        RCC_AHBENR_DMA2EN_Msk         /*!< DMA2 clock enable */
+#define RCC_AHBENR_SRAMEN_Pos                    (2U)                          
+#define RCC_AHBENR_SRAMEN_Msk                    (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHBENR_SRAMEN                        RCC_AHBENR_SRAMEN_Msk         /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN_Pos                   (4U)                          
+#define RCC_AHBENR_FLITFEN_Msk                   (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
+#define RCC_AHBENR_FLITFEN                       RCC_AHBENR_FLITFEN_Msk        /*!< FLITF clock enable */
+#define RCC_AHBENR_FMCEN_Pos                     (5U)                          
+#define RCC_AHBENR_FMCEN_Msk                     (0x1U << RCC_AHBENR_FMCEN_Pos) /*!< 0x00000020 */
+#define RCC_AHBENR_FMCEN                         RCC_AHBENR_FMCEN_Msk          /*!< FMC clock enable */
+#define RCC_AHBENR_CRCEN_Pos                     (6U)                          
+#define RCC_AHBENR_CRCEN_Msk                     (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
+#define RCC_AHBENR_CRCEN                         RCC_AHBENR_CRCEN_Msk          /*!< CRC clock enable */
+#define RCC_AHBENR_GPIOHEN_Pos                   (16U)                         
+#define RCC_AHBENR_GPIOHEN_Msk                   (0x1U << RCC_AHBENR_GPIOHEN_Pos) /*!< 0x00010000 */
+#define RCC_AHBENR_GPIOHEN                       RCC_AHBENR_GPIOHEN_Msk        /*!< GPIOH clock enable */
+#define RCC_AHBENR_GPIOAEN_Pos                   (17U)                         
+#define RCC_AHBENR_GPIOAEN_Msk                   (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */
+#define RCC_AHBENR_GPIOAEN                       RCC_AHBENR_GPIOAEN_Msk        /*!< GPIOA clock enable */
+#define RCC_AHBENR_GPIOBEN_Pos                   (18U)                         
+#define RCC_AHBENR_GPIOBEN_Msk                   (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */
+#define RCC_AHBENR_GPIOBEN                       RCC_AHBENR_GPIOBEN_Msk        /*!< GPIOB clock enable */
+#define RCC_AHBENR_GPIOCEN_Pos                   (19U)                         
+#define RCC_AHBENR_GPIOCEN_Msk                   (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */
+#define RCC_AHBENR_GPIOCEN                       RCC_AHBENR_GPIOCEN_Msk        /*!< GPIOC clock enable */
+#define RCC_AHBENR_GPIODEN_Pos                   (20U)                         
+#define RCC_AHBENR_GPIODEN_Msk                   (0x1U << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */
+#define RCC_AHBENR_GPIODEN                       RCC_AHBENR_GPIODEN_Msk        /*!< GPIOD clock enable */
+#define RCC_AHBENR_GPIOEEN_Pos                   (21U)                         
+#define RCC_AHBENR_GPIOEEN_Msk                   (0x1U << RCC_AHBENR_GPIOEEN_Pos) /*!< 0x00200000 */
+#define RCC_AHBENR_GPIOEEN                       RCC_AHBENR_GPIOEEN_Msk        /*!< GPIOE clock enable */
+#define RCC_AHBENR_GPIOFEN_Pos                   (22U)                         
+#define RCC_AHBENR_GPIOFEN_Msk                   (0x1U << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */
+#define RCC_AHBENR_GPIOFEN                       RCC_AHBENR_GPIOFEN_Msk        /*!< GPIOF clock enable */
+#define RCC_AHBENR_GPIOGEN_Pos                   (23U)                         
+#define RCC_AHBENR_GPIOGEN_Msk                   (0x1U << RCC_AHBENR_GPIOGEN_Pos) /*!< 0x00800000 */
+#define RCC_AHBENR_GPIOGEN                       RCC_AHBENR_GPIOGEN_Msk        /*!< GPIOG clock enable */
+#define RCC_AHBENR_TSCEN_Pos                     (24U)                         
+#define RCC_AHBENR_TSCEN_Msk                     (0x1U << RCC_AHBENR_TSCEN_Pos) /*!< 0x01000000 */
+#define RCC_AHBENR_TSCEN                         RCC_AHBENR_TSCEN_Msk          /*!< TS clock enable */
+#define RCC_AHBENR_ADC12EN_Pos                   (28U)                         
+#define RCC_AHBENR_ADC12EN_Msk                   (0x1U << RCC_AHBENR_ADC12EN_Pos) /*!< 0x10000000 */
+#define RCC_AHBENR_ADC12EN                       RCC_AHBENR_ADC12EN_Msk        /*!< ADC1/ ADC2 clock enable */
+#define RCC_AHBENR_ADC34EN_Pos                   (29U)                         
+#define RCC_AHBENR_ADC34EN_Msk                   (0x1U << RCC_AHBENR_ADC34EN_Pos) /*!< 0x20000000 */
+#define RCC_AHBENR_ADC34EN                       RCC_AHBENR_ADC34EN_Msk        /*!< ADC3/ ADC4 clock enable */
+
+/*****************  Bit definition for RCC_APB2ENR register  ******************/
+#define RCC_APB2ENR_SYSCFGEN_Pos                 (0U)                          
+#define RCC_APB2ENR_SYSCFGEN_Msk                 (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN                     RCC_APB2ENR_SYSCFGEN_Msk      /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM1EN_Pos                   (11U)                         
+#define RCC_APB2ENR_TIM1EN_Msk                   (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN                       RCC_APB2ENR_TIM1EN_Msk        /*!< TIM1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos                   (12U)                         
+#define RCC_APB2ENR_SPI1EN_Msk                   (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                       RCC_APB2ENR_SPI1EN_Msk        /*!< SPI1 clock enable */
+#define RCC_APB2ENR_TIM8EN_Pos                   (13U)                         
+#define RCC_APB2ENR_TIM8EN_Msk                   (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_TIM8EN                       RCC_APB2ENR_TIM8EN_Msk        /*!< TIM8 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos                 (14U)                         
+#define RCC_APB2ENR_USART1EN_Msk                 (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN                     RCC_APB2ENR_USART1EN_Msk      /*!< USART1 clock enable */
+#define RCC_APB2ENR_SPI4EN_Pos                   (15U)                         
+#define RCC_APB2ENR_SPI4EN_Msk                   (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00008000 */
+#define RCC_APB2ENR_SPI4EN                       RCC_APB2ENR_SPI4EN_Msk        /*!< SPI4 clock enable */
+#define RCC_APB2ENR_TIM15EN_Pos                  (16U)                         
+#define RCC_APB2ENR_TIM15EN_Msk                  (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN                      RCC_APB2ENR_TIM15EN_Msk       /*!< TIM15 clock enable */
+#define RCC_APB2ENR_TIM16EN_Pos                  (17U)                         
+#define RCC_APB2ENR_TIM16EN_Msk                  (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN                      RCC_APB2ENR_TIM16EN_Msk       /*!< TIM16 clock enable */
+#define RCC_APB2ENR_TIM17EN_Pos                  (18U)                         
+#define RCC_APB2ENR_TIM17EN_Msk                  (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN                      RCC_APB2ENR_TIM17EN_Msk       /*!< TIM17 clock enable */
+#define RCC_APB2ENR_TIM20EN_Pos                  (20U)                         
+#define RCC_APB2ENR_TIM20EN_Msk                  (0x1U << RCC_APB2ENR_TIM20EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_TIM20EN                      RCC_APB2ENR_TIM20EN_Msk       /*!< TIM20 clock enable */
+
+/******************  Bit definition for RCC_APB1ENR register  ******************/
+#define RCC_APB1ENR_TIM2EN_Pos                   (0U)                          
+#define RCC_APB1ENR_TIM2EN_Msk                   (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN                       RCC_APB1ENR_TIM2EN_Msk        /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM3EN_Pos                   (1U)                          
+#define RCC_APB1ENR_TIM3EN_Msk                   (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN                       RCC_APB1ENR_TIM3EN_Msk        /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM4EN_Pos                   (2U)                          
+#define RCC_APB1ENR_TIM4EN_Msk                   (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN                       RCC_APB1ENR_TIM4EN_Msk        /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_TIM6EN_Pos                   (4U)                          
+#define RCC_APB1ENR_TIM6EN_Msk                   (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN                       RCC_APB1ENR_TIM6EN_Msk        /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN_Pos                   (5U)                          
+#define RCC_APB1ENR_TIM7EN_Msk                   (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN                       RCC_APB1ENR_TIM7EN_Msk        /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos                   (11U)                         
+#define RCC_APB1ENR_WWDGEN_Msk                   (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN                       RCC_APB1ENR_WWDGEN_Msk        /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos                   (14U)                         
+#define RCC_APB1ENR_SPI2EN_Msk                   (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN                       RCC_APB1ENR_SPI2EN_Msk        /*!< SPI2 clock enable */
+#define RCC_APB1ENR_SPI3EN_Pos                   (15U)                         
+#define RCC_APB1ENR_SPI3EN_Msk                   (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN                       RCC_APB1ENR_SPI3EN_Msk        /*!< SPI3 clock enable */
+#define RCC_APB1ENR_USART2EN_Pos                 (17U)                         
+#define RCC_APB1ENR_USART2EN_Msk                 (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN                     RCC_APB1ENR_USART2EN_Msk      /*!< USART 2 clock enable */
+#define RCC_APB1ENR_USART3EN_Pos                 (18U)                         
+#define RCC_APB1ENR_USART3EN_Msk                 (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN                     RCC_APB1ENR_USART3EN_Msk      /*!< USART 3 clock enable */
+#define RCC_APB1ENR_UART4EN_Pos                  (19U)                         
+#define RCC_APB1ENR_UART4EN_Msk                  (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_UART4EN                      RCC_APB1ENR_UART4EN_Msk       /*!< UART 4 clock enable */
+#define RCC_APB1ENR_UART5EN_Pos                  (20U)                         
+#define RCC_APB1ENR_UART5EN_Msk                  (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_UART5EN                      RCC_APB1ENR_UART5EN_Msk       /*!< UART 5 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos                   (21U)                         
+#define RCC_APB1ENR_I2C1EN_Msk                   (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN                       RCC_APB1ENR_I2C1EN_Msk        /*!< I2C 1 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos                   (22U)                         
+#define RCC_APB1ENR_I2C2EN_Msk                   (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN                       RCC_APB1ENR_I2C2EN_Msk        /*!< I2C 2 clock enable */
+#define RCC_APB1ENR_USBEN_Pos                    (23U)                         
+#define RCC_APB1ENR_USBEN_Msk                    (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_USBEN                        RCC_APB1ENR_USBEN_Msk         /*!< USB clock enable */
+#define RCC_APB1ENR_CANEN_Pos                    (25U)                         
+#define RCC_APB1ENR_CANEN_Msk                    (0x1U << RCC_APB1ENR_CANEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR_CANEN                        RCC_APB1ENR_CANEN_Msk         /*!< CAN clock enable */
+#define RCC_APB1ENR_PWREN_Pos                    (28U)                         
+#define RCC_APB1ENR_PWREN_Msk                    (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN                        RCC_APB1ENR_PWREN_Msk         /*!< PWR clock enable */
+#define RCC_APB1ENR_DAC1EN_Pos                   (29U)                         
+#define RCC_APB1ENR_DAC1EN_Msk                   (0x1U << RCC_APB1ENR_DAC1EN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DAC1EN                       RCC_APB1ENR_DAC1EN_Msk        /*!< DAC 1 clock enable */
+#define RCC_APB1ENR_I2C3EN_Pos                   (30U)                         
+#define RCC_APB1ENR_I2C3EN_Msk                   (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR_I2C3EN                       RCC_APB1ENR_I2C3EN_Msk        /*!< I2C 3 clock enable */
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define RCC_BDCR_LSE_Pos                         (0U)                          
+#define RCC_BDCR_LSE_Msk                         (0x7U << RCC_BDCR_LSE_Pos)    /*!< 0x00000007 */
+#define RCC_BDCR_LSE                             RCC_BDCR_LSE_Msk              /*!< External Low Speed oscillator [2:0] bits */
+#define RCC_BDCR_LSEON_Pos                       (0U)                          
+#define RCC_BDCR_LSEON_Msk                       (0x1U << RCC_BDCR_LSEON_Pos)  /*!< 0x00000001 */
+#define RCC_BDCR_LSEON                           RCC_BDCR_LSEON_Msk            /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY_Pos                      (1U)                          
+#define RCC_BDCR_LSERDY_Msk                      (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY                          RCC_BDCR_LSERDY_Msk           /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP_Pos                      (2U)                          
+#define RCC_BDCR_LSEBYP_Msk                      (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP                          RCC_BDCR_LSEBYP_Msk           /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_LSEDRV_Pos                      (3U)                          
+#define RCC_BDCR_LSEDRV_Msk                      (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
+#define RCC_BDCR_LSEDRV                          RCC_BDCR_LSEDRV_Msk           /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_BDCR_LSEDRV_0                        (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
+#define RCC_BDCR_LSEDRV_1                        (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
+
+#define RCC_BDCR_RTCSEL_Pos                      (8U)                          
+#define RCC_BDCR_RTCSEL_Msk                      (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL                          RCC_BDCR_RTCSEL_Msk           /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0                        (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1                        (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+/*!< RTC configuration */
+#define RCC_BDCR_RTCSEL_NOCLOCK                  (0x00000000U)                 /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE                      (0x00000100U)                 /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI                      (0x00000200U)                 /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE                      (0x00000300U)                 /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define RCC_BDCR_RTCEN_Pos                       (15U)                         
+#define RCC_BDCR_RTCEN_Msk                       (0x1U << RCC_BDCR_RTCEN_Pos)  /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN                           RCC_BDCR_RTCEN_Msk            /*!< RTC clock enable */
+#define RCC_BDCR_BDRST_Pos                       (16U)                         
+#define RCC_BDCR_BDRST_Msk                       (0x1U << RCC_BDCR_BDRST_Pos)  /*!< 0x00010000 */
+#define RCC_BDCR_BDRST                           RCC_BDCR_BDRST_Msk            /*!< Backup domain software reset  */
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define RCC_CSR_LSION_Pos                        (0U)                          
+#define RCC_CSR_LSION_Msk                        (0x1U << RCC_CSR_LSION_Pos)   /*!< 0x00000001 */
+#define RCC_CSR_LSION                            RCC_CSR_LSION_Msk             /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos                       (1U)                          
+#define RCC_CSR_LSIRDY_Msk                       (0x1U << RCC_CSR_LSIRDY_Pos)  /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                           RCC_CSR_LSIRDY_Msk            /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_V18PWRRSTF_Pos                   (23U)                         
+#define RCC_CSR_V18PWRRSTF_Msk                   (0x1U << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_V18PWRRSTF                       RCC_CSR_V18PWRRSTF_Msk        /*!< V1.8 power domain reset flag */
+#define RCC_CSR_RMVF_Pos                         (24U)                         
+#define RCC_CSR_RMVF_Msk                         (0x1U << RCC_CSR_RMVF_Pos)    /*!< 0x01000000 */
+#define RCC_CSR_RMVF                             RCC_CSR_RMVF_Msk              /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF_Pos                      (25U)                         
+#define RCC_CSR_OBLRSTF_Msk                      (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF                          RCC_CSR_OBLRSTF_Msk           /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF_Pos                      (26U)                         
+#define RCC_CSR_PINRSTF_Msk                      (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF                          RCC_CSR_PINRSTF_Msk           /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos                      (27U)                         
+#define RCC_CSR_PORRSTF_Msk                      (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF                          RCC_CSR_PORRSTF_Msk           /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos                      (28U)                         
+#define RCC_CSR_SFTRSTF_Msk                      (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF                          RCC_CSR_SFTRSTF_Msk           /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos                     (29U)                         
+#define RCC_CSR_IWDGRSTF_Msk                     (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF                         RCC_CSR_IWDGRSTF_Msk          /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos                     (30U)                         
+#define RCC_CSR_WWDGRSTF_Msk                     (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF                         RCC_CSR_WWDGRSTF_Msk          /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos                     (31U)                         
+#define RCC_CSR_LPWRRSTF_Msk                     (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF                         RCC_CSR_LPWRRSTF_Msk          /*!< Low-Power reset flag */
+
+/* Legacy defines */
+#define  RCC_CSR_VREGRSTF                    RCC_CSR_V18PWRRSTF
+
+/*******************  Bit definition for RCC_AHBRSTR register  ****************/
+#define RCC_AHBRSTR_FMCRST_Pos                   (5U)                          
+#define RCC_AHBRSTR_FMCRST_Msk                   (0x1U << RCC_AHBRSTR_FMCRST_Pos) /*!< 0x00000020 */
+#define RCC_AHBRSTR_FMCRST                       RCC_AHBRSTR_FMCRST_Msk        /*!< FMC reset */
+#define RCC_AHBRSTR_GPIOHRST_Pos                 (16U)                         
+#define RCC_AHBRSTR_GPIOHRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00010000 */
+#define RCC_AHBRSTR_GPIOHRST                     RCC_AHBRSTR_GPIOHRST_Msk      /*!< GPIOH reset */
+#define RCC_AHBRSTR_GPIOARST_Pos                 (17U)                         
+#define RCC_AHBRSTR_GPIOARST_Msk                 (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
+#define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA reset */
+#define RCC_AHBRSTR_GPIOBRST_Pos                 (18U)                         
+#define RCC_AHBRSTR_GPIOBRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
+#define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB reset */
+#define RCC_AHBRSTR_GPIOCRST_Pos                 (19U)                         
+#define RCC_AHBRSTR_GPIOCRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
+#define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC reset */
+#define RCC_AHBRSTR_GPIODRST_Pos                 (20U)                         
+#define RCC_AHBRSTR_GPIODRST_Msk                 (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
+#define RCC_AHBRSTR_GPIODRST                     RCC_AHBRSTR_GPIODRST_Msk      /*!< GPIOD reset */
+#define RCC_AHBRSTR_GPIOERST_Pos                 (21U)                         
+#define RCC_AHBRSTR_GPIOERST_Msk                 (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00200000 */
+#define RCC_AHBRSTR_GPIOERST                     RCC_AHBRSTR_GPIOERST_Msk      /*!< GPIOE reset */
+#define RCC_AHBRSTR_GPIOFRST_Pos                 (22U)                         
+#define RCC_AHBRSTR_GPIOFRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
+#define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF reset */
+#define RCC_AHBRSTR_GPIOGRST_Pos                 (23U)                         
+#define RCC_AHBRSTR_GPIOGRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00800000 */
+#define RCC_AHBRSTR_GPIOGRST                     RCC_AHBRSTR_GPIOGRST_Msk      /*!< GPIOG reset */
+#define RCC_AHBRSTR_TSCRST_Pos                   (24U)                         
+#define RCC_AHBRSTR_TSCRST_Msk                   (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
+#define RCC_AHBRSTR_TSCRST                       RCC_AHBRSTR_TSCRST_Msk        /*!< TSC reset */
+#define RCC_AHBRSTR_ADC12RST_Pos                 (28U)                         
+#define RCC_AHBRSTR_ADC12RST_Msk                 (0x1U << RCC_AHBRSTR_ADC12RST_Pos) /*!< 0x10000000 */
+#define RCC_AHBRSTR_ADC12RST                     RCC_AHBRSTR_ADC12RST_Msk      /*!< ADC1 & ADC2 reset */
+#define RCC_AHBRSTR_ADC34RST_Pos                 (29U)                         
+#define RCC_AHBRSTR_ADC34RST_Msk                 (0x1U << RCC_AHBRSTR_ADC34RST_Pos) /*!< 0x20000000 */
+#define RCC_AHBRSTR_ADC34RST                     RCC_AHBRSTR_ADC34RST_Msk      /*!< ADC3 & ADC4 reset */
+
+/*******************  Bit definition for RCC_CFGR2 register  ******************/
+/*!< PREDIV configuration */
+#define RCC_CFGR2_PREDIV_Pos                     (0U)                          
+#define RCC_CFGR2_PREDIV_Msk                     (0xFU << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */
+#define RCC_CFGR2_PREDIV                         RCC_CFGR2_PREDIV_Msk          /*!< PREDIV[3:0] bits */
+#define RCC_CFGR2_PREDIV_0                       (0x1U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */
+#define RCC_CFGR2_PREDIV_1                       (0x2U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */
+#define RCC_CFGR2_PREDIV_2                       (0x4U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */
+#define RCC_CFGR2_PREDIV_3                       (0x8U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR2_PREDIV_DIV1                    (0x00000000U)                 /*!< PREDIV input clock not divided */
+#define RCC_CFGR2_PREDIV_DIV2                    (0x00000001U)                 /*!< PREDIV input clock divided by 2 */
+#define RCC_CFGR2_PREDIV_DIV3                    (0x00000002U)                 /*!< PREDIV input clock divided by 3 */
+#define RCC_CFGR2_PREDIV_DIV4                    (0x00000003U)                 /*!< PREDIV input clock divided by 4 */
+#define RCC_CFGR2_PREDIV_DIV5                    (0x00000004U)                 /*!< PREDIV input clock divided by 5 */
+#define RCC_CFGR2_PREDIV_DIV6                    (0x00000005U)                 /*!< PREDIV input clock divided by 6 */
+#define RCC_CFGR2_PREDIV_DIV7                    (0x00000006U)                 /*!< PREDIV input clock divided by 7 */
+#define RCC_CFGR2_PREDIV_DIV8                    (0x00000007U)                 /*!< PREDIV input clock divided by 8 */
+#define RCC_CFGR2_PREDIV_DIV9                    (0x00000008U)                 /*!< PREDIV input clock divided by 9 */
+#define RCC_CFGR2_PREDIV_DIV10                   (0x00000009U)                 /*!< PREDIV input clock divided by 10 */
+#define RCC_CFGR2_PREDIV_DIV11                   (0x0000000AU)                 /*!< PREDIV input clock divided by 11 */
+#define RCC_CFGR2_PREDIV_DIV12                   (0x0000000BU)                 /*!< PREDIV input clock divided by 12 */
+#define RCC_CFGR2_PREDIV_DIV13                   (0x0000000CU)                 /*!< PREDIV input clock divided by 13 */
+#define RCC_CFGR2_PREDIV_DIV14                   (0x0000000DU)                 /*!< PREDIV input clock divided by 14 */
+#define RCC_CFGR2_PREDIV_DIV15                   (0x0000000EU)                 /*!< PREDIV input clock divided by 15 */
+#define RCC_CFGR2_PREDIV_DIV16                   (0x0000000FU)                 /*!< PREDIV input clock divided by 16 */
+
+/*!< ADCPRE12 configuration */
+#define RCC_CFGR2_ADCPRE12_Pos                   (4U)                          
+#define RCC_CFGR2_ADCPRE12_Msk                   (0x1FU << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x000001F0 */
+#define RCC_CFGR2_ADCPRE12                       RCC_CFGR2_ADCPRE12_Msk        /*!< ADCPRE12[8:4] bits */
+#define RCC_CFGR2_ADCPRE12_0                     (0x01U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000010 */
+#define RCC_CFGR2_ADCPRE12_1                     (0x02U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000020 */
+#define RCC_CFGR2_ADCPRE12_2                     (0x04U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000040 */
+#define RCC_CFGR2_ADCPRE12_3                     (0x08U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000080 */
+#define RCC_CFGR2_ADCPRE12_4                     (0x10U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000100 */
+
+#define RCC_CFGR2_ADCPRE12_NO                    (0x00000000U)                 /*!< ADC12 clock disabled, ADC12 can use AHB clock */
+#define RCC_CFGR2_ADCPRE12_DIV1                  (0x00000100U)                 /*!< ADC12 PLL clock divided by 1 */
+#define RCC_CFGR2_ADCPRE12_DIV2                  (0x00000110U)                 /*!< ADC12 PLL clock divided by 2 */
+#define RCC_CFGR2_ADCPRE12_DIV4                  (0x00000120U)                 /*!< ADC12 PLL clock divided by 4 */
+#define RCC_CFGR2_ADCPRE12_DIV6                  (0x00000130U)                 /*!< ADC12 PLL clock divided by 6 */
+#define RCC_CFGR2_ADCPRE12_DIV8                  (0x00000140U)                 /*!< ADC12 PLL clock divided by 8 */
+#define RCC_CFGR2_ADCPRE12_DIV10                 (0x00000150U)                 /*!< ADC12 PLL clock divided by 10 */
+#define RCC_CFGR2_ADCPRE12_DIV12                 (0x00000160U)                 /*!< ADC12 PLL clock divided by 12 */
+#define RCC_CFGR2_ADCPRE12_DIV16                 (0x00000170U)                 /*!< ADC12 PLL clock divided by 16 */
+#define RCC_CFGR2_ADCPRE12_DIV32                 (0x00000180U)                 /*!< ADC12 PLL clock divided by 32 */
+#define RCC_CFGR2_ADCPRE12_DIV64                 (0x00000190U)                 /*!< ADC12 PLL clock divided by 64 */
+#define RCC_CFGR2_ADCPRE12_DIV128                (0x000001A0U)                 /*!< ADC12 PLL clock divided by 128 */
+#define RCC_CFGR2_ADCPRE12_DIV256                (0x000001B0U)                 /*!< ADC12 PLL clock divided by 256 */
+
+/*!< ADCPRE34 configuration */
+#define RCC_CFGR2_ADCPRE34_Pos                   (9U)                          
+#define RCC_CFGR2_ADCPRE34_Msk                   (0x1FU << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00003E00 */
+#define RCC_CFGR2_ADCPRE34                       RCC_CFGR2_ADCPRE34_Msk        /*!< ADCPRE34[13:5] bits */
+#define RCC_CFGR2_ADCPRE34_0                     (0x01U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00000200 */
+#define RCC_CFGR2_ADCPRE34_1                     (0x02U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00000400 */
+#define RCC_CFGR2_ADCPRE34_2                     (0x04U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00000800 */
+#define RCC_CFGR2_ADCPRE34_3                     (0x08U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00001000 */
+#define RCC_CFGR2_ADCPRE34_4                     (0x10U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR2_ADCPRE34_NO                    (0x00000000U)                 /*!< ADC34 clock disabled, ADC34 can use AHB clock */
+#define RCC_CFGR2_ADCPRE34_DIV1                  (0x00002000U)                 /*!< ADC34 PLL clock divided by 1 */
+#define RCC_CFGR2_ADCPRE34_DIV2                  (0x00002200U)                 /*!< ADC34 PLL clock divided by 2 */
+#define RCC_CFGR2_ADCPRE34_DIV4                  (0x00002400U)                 /*!< ADC34 PLL clock divided by 4 */
+#define RCC_CFGR2_ADCPRE34_DIV6                  (0x00002600U)                 /*!< ADC34 PLL clock divided by 6 */
+#define RCC_CFGR2_ADCPRE34_DIV8                  (0x00002800U)                 /*!< ADC34 PLL clock divided by 8 */
+#define RCC_CFGR2_ADCPRE34_DIV10                 (0x00002A00U)                 /*!< ADC34 PLL clock divided by 10 */
+#define RCC_CFGR2_ADCPRE34_DIV12                 (0x00002C00U)                 /*!< ADC34 PLL clock divided by 12 */
+#define RCC_CFGR2_ADCPRE34_DIV16                 (0x00002E00U)                 /*!< ADC34 PLL clock divided by 16 */
+#define RCC_CFGR2_ADCPRE34_DIV32                 (0x00003000U)                 /*!< ADC34 PLL clock divided by 32 */
+#define RCC_CFGR2_ADCPRE34_DIV64                 (0x00003200U)                 /*!< ADC34 PLL clock divided by 64 */
+#define RCC_CFGR2_ADCPRE34_DIV128                (0x00003400U)                 /*!< ADC34 PLL clock divided by 128 */
+#define RCC_CFGR2_ADCPRE34_DIV256                (0x00003600U)                 /*!< ADC34 PLL clock divided by 256 */
+
+/*******************  Bit definition for RCC_CFGR3 register  ******************/
+#define RCC_CFGR3_USART1SW_Pos                   (0U)                          
+#define RCC_CFGR3_USART1SW_Msk                   (0x3U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR3_USART1SW                       RCC_CFGR3_USART1SW_Msk        /*!< USART1SW[1:0] bits */
+#define RCC_CFGR3_USART1SW_0                     (0x1U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR3_USART1SW_1                     (0x2U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR3_USART1SW_PCLK2                 (0x00000000U)                 /*!< PCLK2 clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_SYSCLK                (0x00000001U)                 /*!< System clock selected as USART1 clock source */
+#define RCC_CFGR3_USART1SW_LSE                   (0x00000002U)                 /*!< LSE oscillator clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_HSI                   (0x00000003U)                 /*!< HSI oscillator clock used as USART1 clock source */
+/* Legacy defines */
+#define  RCC_CFGR3_USART1SW_PCLK             RCC_CFGR3_USART1SW_PCLK2
+
+#define RCC_CFGR3_I2CSW_Pos                      (4U)                          
+#define RCC_CFGR3_I2CSW_Msk                      (0x7U << RCC_CFGR3_I2CSW_Pos) /*!< 0x00000070 */
+#define RCC_CFGR3_I2CSW                          RCC_CFGR3_I2CSW_Msk           /*!< I2CSW bits */
+#define RCC_CFGR3_I2C1SW_Pos                     (4U)                          
+#define RCC_CFGR3_I2C1SW_Msk                     (0x1U << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */
+#define RCC_CFGR3_I2C1SW                         RCC_CFGR3_I2C1SW_Msk          /*!< I2C1SW bits */
+#define RCC_CFGR3_I2C2SW_Pos                     (5U)                          
+#define RCC_CFGR3_I2C2SW_Msk                     (0x1U << RCC_CFGR3_I2C2SW_Pos) /*!< 0x00000020 */
+#define RCC_CFGR3_I2C2SW                         RCC_CFGR3_I2C2SW_Msk          /*!< I2C2SW bits */
+#define RCC_CFGR3_I2C3SW_Pos                     (6U)                          
+#define RCC_CFGR3_I2C3SW_Msk                     (0x1U << RCC_CFGR3_I2C3SW_Pos) /*!< 0x00000040 */
+#define RCC_CFGR3_I2C3SW                         RCC_CFGR3_I2C3SW_Msk          /*!< I2C3SW bits */
+
+#define RCC_CFGR3_I2C1SW_HSI                     (0x00000000U)                 /*!< HSI oscillator clock used as I2C1 clock source */
+#define RCC_CFGR3_I2C1SW_SYSCLK_Pos              (4U)                          
+#define RCC_CFGR3_I2C1SW_SYSCLK_Msk              (0x1U << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */
+#define RCC_CFGR3_I2C1SW_SYSCLK                  RCC_CFGR3_I2C1SW_SYSCLK_Msk   /*!< System clock selected as I2C1 clock source */
+#define RCC_CFGR3_I2C2SW_HSI                     (0x00000000U)                 /*!< HSI oscillator clock used as I2C2 clock source */
+#define RCC_CFGR3_I2C2SW_SYSCLK_Pos              (5U)                          
+#define RCC_CFGR3_I2C2SW_SYSCLK_Msk              (0x1U << RCC_CFGR3_I2C2SW_SYSCLK_Pos) /*!< 0x00000020 */
+#define RCC_CFGR3_I2C2SW_SYSCLK                  RCC_CFGR3_I2C2SW_SYSCLK_Msk   /*!< System clock selected as I2C2 clock source */
+#define RCC_CFGR3_I2C3SW_HSI                     (0x00000000U)                 /*!< HSI oscillator clock used as I2C3 clock source */
+#define RCC_CFGR3_I2C3SW_SYSCLK_Pos              (6U)                          
+#define RCC_CFGR3_I2C3SW_SYSCLK_Msk              (0x1U << RCC_CFGR3_I2C3SW_SYSCLK_Pos) /*!< 0x00000040 */
+#define RCC_CFGR3_I2C3SW_SYSCLK                  RCC_CFGR3_I2C3SW_SYSCLK_Msk   /*!< System clock selected as I2C3 clock source */
+
+#define RCC_CFGR3_TIMSW_Pos                      (8U)                          
+#define RCC_CFGR3_TIMSW_Msk                      (0xAFU << RCC_CFGR3_TIMSW_Pos) /*!< 0x0000AF00 */
+#define RCC_CFGR3_TIMSW                          RCC_CFGR3_TIMSW_Msk           /*!< TIMSW bits */
+#define RCC_CFGR3_TIM1SW_Pos                     (8U)                          
+#define RCC_CFGR3_TIM1SW_Msk                     (0x1U << RCC_CFGR3_TIM1SW_Pos) /*!< 0x00000100 */
+#define RCC_CFGR3_TIM1SW                         RCC_CFGR3_TIM1SW_Msk          /*!< TIM1SW bits */
+#define RCC_CFGR3_TIM8SW_Pos                     (9U)                          
+#define RCC_CFGR3_TIM8SW_Msk                     (0x1U << RCC_CFGR3_TIM8SW_Pos) /*!< 0x00000200 */
+#define RCC_CFGR3_TIM8SW                         RCC_CFGR3_TIM8SW_Msk          /*!< TIM8SW bits */
+#define RCC_CFGR3_TIM15SW_Pos                    (10U)                         
+#define RCC_CFGR3_TIM15SW_Msk                    (0x1U << RCC_CFGR3_TIM15SW_Pos) /*!< 0x00000400 */
+#define RCC_CFGR3_TIM15SW                        RCC_CFGR3_TIM15SW_Msk         /*!< TIM15SW bits */
+#define RCC_CFGR3_TIM16SW_Pos                    (11U)                         
+#define RCC_CFGR3_TIM16SW_Msk                    (0x1U << RCC_CFGR3_TIM16SW_Pos) /*!< 0x00000800 */
+#define RCC_CFGR3_TIM16SW                        RCC_CFGR3_TIM16SW_Msk         /*!< TIM16SW bits */
+#define RCC_CFGR3_TIM17SW_Pos                    (13U)                         
+#define RCC_CFGR3_TIM17SW_Msk                    (0x1U << RCC_CFGR3_TIM17SW_Pos) /*!< 0x00002000 */
+#define RCC_CFGR3_TIM17SW                        RCC_CFGR3_TIM17SW_Msk         /*!< TIM17SW bits */
+#define RCC_CFGR3_TIM20SW_Pos                    (15U)                         
+#define RCC_CFGR3_TIM20SW_Msk                    (0x1U << RCC_CFGR3_TIM20SW_Pos) /*!< 0x00008000 */
+#define RCC_CFGR3_TIM20SW                        RCC_CFGR3_TIM20SW_Msk         /*!< TIM20SW bits */
+#define RCC_CFGR3_TIM2SW_Pos                     (24U)                         
+#define RCC_CFGR3_TIM2SW_Msk                     (0x1U << RCC_CFGR3_TIM2SW_Pos) /*!< 0x01000000 */
+#define RCC_CFGR3_TIM2SW                         RCC_CFGR3_TIM2SW_Msk          /*!< TIM2SW bits */
+#define RCC_CFGR3_TIM34SW_Pos                    (25U)                         
+#define RCC_CFGR3_TIM34SW_Msk                    (0x1U << RCC_CFGR3_TIM34SW_Pos) /*!< 0x02000000 */
+#define RCC_CFGR3_TIM34SW                        RCC_CFGR3_TIM34SW_Msk         /*!< TIM34SW bits */
+#define RCC_CFGR3_TIM1SW_PCLK2                   (0x00000000U)                 /*!< PCLK2 used as TIM1 clock source */
+#define RCC_CFGR3_TIM1SW_PLL_Pos                 (8U)                          
+#define RCC_CFGR3_TIM1SW_PLL_Msk                 (0x1U << RCC_CFGR3_TIM1SW_PLL_Pos) /*!< 0x00000100 */
+#define RCC_CFGR3_TIM1SW_PLL                     RCC_CFGR3_TIM1SW_PLL_Msk      /*!< PLL clock used as TIM1 clock source */
+#define RCC_CFGR3_TIM8SW_PCLK2                   (0x00000000U)                 /*!< PCLK2 used as TIM8 clock source */
+#define RCC_CFGR3_TIM8SW_PLL_Pos                 (9U)                          
+#define RCC_CFGR3_TIM8SW_PLL_Msk                 (0x1U << RCC_CFGR3_TIM8SW_PLL_Pos) /*!< 0x00000200 */
+#define RCC_CFGR3_TIM8SW_PLL                     RCC_CFGR3_TIM8SW_PLL_Msk      /*!< PLL clock used as TIM8 clock source */
+#define RCC_CFGR3_TIM15SW_PCLK2                  (0x00000000U)                 /*!< PCLK2 used as TIM15 clock source */
+#define RCC_CFGR3_TIM15SW_PLL_Pos                (10U)                         
+#define RCC_CFGR3_TIM15SW_PLL_Msk                (0x1U << RCC_CFGR3_TIM15SW_PLL_Pos) /*!< 0x00000400 */
+#define RCC_CFGR3_TIM15SW_PLL                    RCC_CFGR3_TIM15SW_PLL_Msk     /*!< PLL clock used as TIM15 clock source */
+#define RCC_CFGR3_TIM16SW_PCLK2                  (0x00000000U)                 /*!< PCLK2 used as TIM16 clock source */
+#define RCC_CFGR3_TIM16SW_PLL_Pos                (11U)                         
+#define RCC_CFGR3_TIM16SW_PLL_Msk                (0x1U << RCC_CFGR3_TIM16SW_PLL_Pos) /*!< 0x00000800 */
+#define RCC_CFGR3_TIM16SW_PLL                    RCC_CFGR3_TIM16SW_PLL_Msk     /*!< PLL clock used as TIM16 clock source */
+#define RCC_CFGR3_TIM17SW_PCLK2                  (0x00000000U)                 /*!< PCLK2 used as TIM17 clock source */
+#define RCC_CFGR3_TIM17SW_PLL_Pos                (13U)                         
+#define RCC_CFGR3_TIM17SW_PLL_Msk                (0x1U << RCC_CFGR3_TIM17SW_PLL_Pos) /*!< 0x00002000 */
+#define RCC_CFGR3_TIM17SW_PLL                    RCC_CFGR3_TIM17SW_PLL_Msk     /*!< PLL clock used as TIM17 clock source */
+#define RCC_CFGR3_TIM20SW_PCLK2                  (0x00000000U)                 /*!< PCLK2 used as TIM20 clock source */
+#define RCC_CFGR3_TIM20SW_PLL_Pos                (15U)                         
+#define RCC_CFGR3_TIM20SW_PLL_Msk                (0x1U << RCC_CFGR3_TIM20SW_PLL_Pos) /*!< 0x00008000 */
+#define RCC_CFGR3_TIM20SW_PLL                    RCC_CFGR3_TIM20SW_PLL_Msk     /*!< PLL clock used as TIM20 clock source */
+
+#define RCC_CFGR3_USART2SW_Pos                   (16U)                         
+#define RCC_CFGR3_USART2SW_Msk                   (0x3U << RCC_CFGR3_USART2SW_Pos) /*!< 0x00030000 */
+#define RCC_CFGR3_USART2SW                       RCC_CFGR3_USART2SW_Msk        /*!< USART2SW[1:0] bits */
+#define RCC_CFGR3_USART2SW_0                     (0x1U << RCC_CFGR3_USART2SW_Pos) /*!< 0x00010000 */
+#define RCC_CFGR3_USART2SW_1                     (0x2U << RCC_CFGR3_USART2SW_Pos) /*!< 0x00020000 */
+
+#define RCC_CFGR3_USART2SW_PCLK                  (0x00000000U)                 /*!< PCLK1 clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_SYSCLK                (0x00010000U)                 /*!< System clock selected as USART2 clock source */
+#define RCC_CFGR3_USART2SW_LSE                   (0x00020000U)                 /*!< LSE oscillator clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_HSI                   (0x00030000U)                 /*!< HSI oscillator clock used as USART2 clock source */
+
+#define RCC_CFGR3_USART3SW_Pos                   (18U)                         
+#define RCC_CFGR3_USART3SW_Msk                   (0x3U << RCC_CFGR3_USART3SW_Pos) /*!< 0x000C0000 */
+#define RCC_CFGR3_USART3SW                       RCC_CFGR3_USART3SW_Msk        /*!< USART3SW[1:0] bits */
+#define RCC_CFGR3_USART3SW_0                     (0x1U << RCC_CFGR3_USART3SW_Pos) /*!< 0x00040000 */
+#define RCC_CFGR3_USART3SW_1                     (0x2U << RCC_CFGR3_USART3SW_Pos) /*!< 0x00080000 */
+
+#define RCC_CFGR3_USART3SW_PCLK                  (0x00000000U)                 /*!< PCLK1 clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_SYSCLK                (0x00040000U)                 /*!< System clock selected as USART3 clock source */
+#define RCC_CFGR3_USART3SW_LSE                   (0x00080000U)                 /*!< LSE oscillator clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_HSI                   (0x000C0000U)                 /*!< HSI oscillator clock used as USART3 clock source */
+
+#define RCC_CFGR3_UART4SW_Pos                    (20U)                         
+#define RCC_CFGR3_UART4SW_Msk                    (0x3U << RCC_CFGR3_UART4SW_Pos) /*!< 0x00300000 */
+#define RCC_CFGR3_UART4SW                        RCC_CFGR3_UART4SW_Msk         /*!< UART4SW[1:0] bits */
+#define RCC_CFGR3_UART4SW_0                      (0x1U << RCC_CFGR3_UART4SW_Pos) /*!< 0x00100000 */
+#define RCC_CFGR3_UART4SW_1                      (0x2U << RCC_CFGR3_UART4SW_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR3_UART4SW_PCLK                   (0x00000000U)                 /*!< PCLK1 clock used as UART4 clock source */
+#define RCC_CFGR3_UART4SW_SYSCLK                 (0x00100000U)                 /*!< System clock selected as UART4 clock source */
+#define RCC_CFGR3_UART4SW_LSE                    (0x00200000U)                 /*!< LSE oscillator clock used as UART4 clock source */
+#define RCC_CFGR3_UART4SW_HSI                    (0x00300000U)                 /*!< HSI oscillator clock used as UART4 clock source */
+
+#define RCC_CFGR3_UART5SW_Pos                    (22U)                         
+#define RCC_CFGR3_UART5SW_Msk                    (0x3U << RCC_CFGR3_UART5SW_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR3_UART5SW                        RCC_CFGR3_UART5SW_Msk         /*!< UART5SW[1:0] bits */
+#define RCC_CFGR3_UART5SW_0                      (0x1U << RCC_CFGR3_UART5SW_Pos) /*!< 0x00400000 */
+#define RCC_CFGR3_UART5SW_1                      (0x2U << RCC_CFGR3_UART5SW_Pos) /*!< 0x00800000 */
+
+#define RCC_CFGR3_UART5SW_PCLK                   (0x00000000U)                 /*!< PCLK1 clock used as UART5 clock source */
+#define RCC_CFGR3_UART5SW_SYSCLK                 (0x00400000U)                 /*!< System clock selected as UART5 clock source */
+#define RCC_CFGR3_UART5SW_LSE                    (0x00800000U)                 /*!< LSE oscillator clock used as UART5 clock source */
+#define RCC_CFGR3_UART5SW_HSI                    (0x00C00000U)                 /*!< HSI oscillator clock used as UART5 clock source */
+
+#define RCC_CFGR3_TIM2SW_PCLK1                   (0x00000000U)                 /*!< PCLK1 used as TIM2 clock source */
+#define RCC_CFGR3_TIM2SW_PLL_Pos                 (24U)                         
+#define RCC_CFGR3_TIM2SW_PLL_Msk                 (0x1U << RCC_CFGR3_TIM2SW_PLL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR3_TIM2SW_PLL                     RCC_CFGR3_TIM2SW_PLL_Msk      /*!< PLL clock used as TIM2 clock source */
+
+#define RCC_CFGR3_TIM34SW_PCLK1                  (0x00000000U)                 /*!< PCLK1 used as TIM3/TIM4 clock source */
+#define RCC_CFGR3_TIM34SW_PLL_Pos                (25U)                         
+#define RCC_CFGR3_TIM34SW_PLL_Msk                (0x1U << RCC_CFGR3_TIM34SW_PLL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR3_TIM34SW_PLL                    RCC_CFGR3_TIM34SW_PLL_Msk     /*!< PLL clock used as TIM3/TIM4 clock source */
+
+/* Legacy defines */
+#define  RCC_CFGR3_TIM1SW_HCLK                RCC_CFGR3_TIM1SW_PCLK2
+#define  RCC_CFGR3_TIM8SW_HCLK                RCC_CFGR3_TIM8SW_PCLK2
+#define  RCC_CFGR3_TIM15SW_HCLK               RCC_CFGR3_TIM15SW_PCLK2
+#define  RCC_CFGR3_TIM16SW_HCLK               RCC_CFGR3_TIM16SW_PCLK2
+#define  RCC_CFGR3_TIM17SW_HCLK               RCC_CFGR3_TIM17SW_PCLK2
+#define  RCC_CFGR3_TIM20SW_HCLK               RCC_CFGR3_TIM20SW_PCLK2
+#define  RCC_CFGR3_TIM2SW_HCLK                RCC_CFGR3_TIM2SW_PCLK1
+#define  RCC_CFGR3_TIM34SW_HCLK               RCC_CFGR3_TIM34SW_PCLK1
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions  (not present on all devices in the STM32F3 serie)
+*/
+#define RTC_TAMPER1_SUPPORT  /*!< TAMPER 1 feature support */
+#define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */
+#define RTC_TAMPER3_SUPPORT  /*!< TAMPER 3 feature support */
+#define RTC_BACKUP_SUPPORT   /*!< BACKUP register feature support */
+#define RTC_WAKEUP_SUPPORT   /*!< WAKEUP feature support */
+
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                (22U)                                     
+#define RTC_TR_PM_Msk                (0x1U << RTC_TR_PM_Pos)                   /*!< 0x00400000 */
+#define RTC_TR_PM                    RTC_TR_PM_Msk                             
+#define RTC_TR_HT_Pos                (20U)                                     
+#define RTC_TR_HT_Msk                (0x3U << RTC_TR_HT_Pos)                   /*!< 0x00300000 */
+#define RTC_TR_HT                    RTC_TR_HT_Msk                             
+#define RTC_TR_HT_0                  (0x1U << RTC_TR_HT_Pos)                   /*!< 0x00100000 */
+#define RTC_TR_HT_1                  (0x2U << RTC_TR_HT_Pos)                   /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                (16U)                                     
+#define RTC_TR_HU_Msk                (0xFU << RTC_TR_HU_Pos)                   /*!< 0x000F0000 */
+#define RTC_TR_HU                    RTC_TR_HU_Msk                             
+#define RTC_TR_HU_0                  (0x1U << RTC_TR_HU_Pos)                   /*!< 0x00010000 */
+#define RTC_TR_HU_1                  (0x2U << RTC_TR_HU_Pos)                   /*!< 0x00020000 */
+#define RTC_TR_HU_2                  (0x4U << RTC_TR_HU_Pos)                   /*!< 0x00040000 */
+#define RTC_TR_HU_3                  (0x8U << RTC_TR_HU_Pos)                   /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos               (12U)                                     
+#define RTC_TR_MNT_Msk               (0x7U << RTC_TR_MNT_Pos)                  /*!< 0x00007000 */
+#define RTC_TR_MNT                   RTC_TR_MNT_Msk                            
+#define RTC_TR_MNT_0                 (0x1U << RTC_TR_MNT_Pos)                  /*!< 0x00001000 */
+#define RTC_TR_MNT_1                 (0x2U << RTC_TR_MNT_Pos)                  /*!< 0x00002000 */
+#define RTC_TR_MNT_2                 (0x4U << RTC_TR_MNT_Pos)                  /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos               (8U)                                      
+#define RTC_TR_MNU_Msk               (0xFU << RTC_TR_MNU_Pos)                  /*!< 0x00000F00 */
+#define RTC_TR_MNU                   RTC_TR_MNU_Msk                            
+#define RTC_TR_MNU_0                 (0x1U << RTC_TR_MNU_Pos)                  /*!< 0x00000100 */
+#define RTC_TR_MNU_1                 (0x2U << RTC_TR_MNU_Pos)                  /*!< 0x00000200 */
+#define RTC_TR_MNU_2                 (0x4U << RTC_TR_MNU_Pos)                  /*!< 0x00000400 */
+#define RTC_TR_MNU_3                 (0x8U << RTC_TR_MNU_Pos)                  /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                (4U)                                      
+#define RTC_TR_ST_Msk                (0x7U << RTC_TR_ST_Pos)                   /*!< 0x00000070 */
+#define RTC_TR_ST                    RTC_TR_ST_Msk                             
+#define RTC_TR_ST_0                  (0x1U << RTC_TR_ST_Pos)                   /*!< 0x00000010 */
+#define RTC_TR_ST_1                  (0x2U << RTC_TR_ST_Pos)                   /*!< 0x00000020 */
+#define RTC_TR_ST_2                  (0x4U << RTC_TR_ST_Pos)                   /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                (0U)                                      
+#define RTC_TR_SU_Msk                (0xFU << RTC_TR_SU_Pos)                   /*!< 0x0000000F */
+#define RTC_TR_SU                    RTC_TR_SU_Msk                             
+#define RTC_TR_SU_0                  (0x1U << RTC_TR_SU_Pos)                   /*!< 0x00000001 */
+#define RTC_TR_SU_1                  (0x2U << RTC_TR_SU_Pos)                   /*!< 0x00000002 */
+#define RTC_TR_SU_2                  (0x4U << RTC_TR_SU_Pos)                   /*!< 0x00000004 */
+#define RTC_TR_SU_3                  (0x8U << RTC_TR_SU_Pos)                   /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                (20U)                                     
+#define RTC_DR_YT_Msk                (0xFU << RTC_DR_YT_Pos)                   /*!< 0x00F00000 */
+#define RTC_DR_YT                    RTC_DR_YT_Msk                             
+#define RTC_DR_YT_0                  (0x1U << RTC_DR_YT_Pos)                   /*!< 0x00100000 */
+#define RTC_DR_YT_1                  (0x2U << RTC_DR_YT_Pos)                   /*!< 0x00200000 */
+#define RTC_DR_YT_2                  (0x4U << RTC_DR_YT_Pos)                   /*!< 0x00400000 */
+#define RTC_DR_YT_3                  (0x8U << RTC_DR_YT_Pos)                   /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                (16U)                                     
+#define RTC_DR_YU_Msk                (0xFU << RTC_DR_YU_Pos)                   /*!< 0x000F0000 */
+#define RTC_DR_YU                    RTC_DR_YU_Msk                             
+#define RTC_DR_YU_0                  (0x1U << RTC_DR_YU_Pos)                   /*!< 0x00010000 */
+#define RTC_DR_YU_1                  (0x2U << RTC_DR_YU_Pos)                   /*!< 0x00020000 */
+#define RTC_DR_YU_2                  (0x4U << RTC_DR_YU_Pos)                   /*!< 0x00040000 */
+#define RTC_DR_YU_3                  (0x8U << RTC_DR_YU_Pos)                   /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos               (13U)                                     
+#define RTC_DR_WDU_Msk               (0x7U << RTC_DR_WDU_Pos)                  /*!< 0x0000E000 */
+#define RTC_DR_WDU                   RTC_DR_WDU_Msk                            
+#define RTC_DR_WDU_0                 (0x1U << RTC_DR_WDU_Pos)                  /*!< 0x00002000 */
+#define RTC_DR_WDU_1                 (0x2U << RTC_DR_WDU_Pos)                  /*!< 0x00004000 */
+#define RTC_DR_WDU_2                 (0x4U << RTC_DR_WDU_Pos)                  /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                (12U)                                     
+#define RTC_DR_MT_Msk                (0x1U << RTC_DR_MT_Pos)                   /*!< 0x00001000 */
+#define RTC_DR_MT                    RTC_DR_MT_Msk                             
+#define RTC_DR_MU_Pos                (8U)                                      
+#define RTC_DR_MU_Msk                (0xFU << RTC_DR_MU_Pos)                   /*!< 0x00000F00 */
+#define RTC_DR_MU                    RTC_DR_MU_Msk                             
+#define RTC_DR_MU_0                  (0x1U << RTC_DR_MU_Pos)                   /*!< 0x00000100 */
+#define RTC_DR_MU_1                  (0x2U << RTC_DR_MU_Pos)                   /*!< 0x00000200 */
+#define RTC_DR_MU_2                  (0x4U << RTC_DR_MU_Pos)                   /*!< 0x00000400 */
+#define RTC_DR_MU_3                  (0x8U << RTC_DR_MU_Pos)                   /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                (4U)                                      
+#define RTC_DR_DT_Msk                (0x3U << RTC_DR_DT_Pos)                   /*!< 0x00000030 */
+#define RTC_DR_DT                    RTC_DR_DT_Msk                             
+#define RTC_DR_DT_0                  (0x1U << RTC_DR_DT_Pos)                   /*!< 0x00000010 */
+#define RTC_DR_DT_1                  (0x2U << RTC_DR_DT_Pos)                   /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                (0U)                                      
+#define RTC_DR_DU_Msk                (0xFU << RTC_DR_DU_Pos)                   /*!< 0x0000000F */
+#define RTC_DR_DU                    RTC_DR_DU_Msk                             
+#define RTC_DR_DU_0                  (0x1U << RTC_DR_DU_Pos)                   /*!< 0x00000001 */
+#define RTC_DR_DU_1                  (0x2U << RTC_DR_DU_Pos)                   /*!< 0x00000002 */
+#define RTC_DR_DU_2                  (0x4U << RTC_DR_DU_Pos)                   /*!< 0x00000004 */
+#define RTC_DR_DU_3                  (0x8U << RTC_DR_DU_Pos)                   /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_COE_Pos               (23U)                                     
+#define RTC_CR_COE_Msk               (0x1U << RTC_CR_COE_Pos)                  /*!< 0x00800000 */
+#define RTC_CR_COE                   RTC_CR_COE_Msk                            
+#define RTC_CR_OSEL_Pos              (21U)                                     
+#define RTC_CR_OSEL_Msk              (0x3U << RTC_CR_OSEL_Pos)                 /*!< 0x00600000 */
+#define RTC_CR_OSEL                  RTC_CR_OSEL_Msk                           
+#define RTC_CR_OSEL_0                (0x1U << RTC_CR_OSEL_Pos)                 /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                (0x2U << RTC_CR_OSEL_Pos)                 /*!< 0x00400000 */
+#define RTC_CR_POL_Pos               (20U)                                     
+#define RTC_CR_POL_Msk               (0x1U << RTC_CR_POL_Pos)                  /*!< 0x00100000 */
+#define RTC_CR_POL                   RTC_CR_POL_Msk                            
+#define RTC_CR_COSEL_Pos             (19U)                                     
+#define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
+#define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          
+#define RTC_CR_BCK_Pos               (18U)                                     
+#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */
+#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            
+#define RTC_CR_SUB1H_Pos             (17U)                                     
+#define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
+#define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          
+#define RTC_CR_ADD1H_Pos             (16U)                                     
+#define RTC_CR_ADD1H_Msk             (0x1U << RTC_CR_ADD1H_Pos)                /*!< 0x00010000 */
+#define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk                          
+#define RTC_CR_TSIE_Pos              (15U)                                     
+#define RTC_CR_TSIE_Msk              (0x1U << RTC_CR_TSIE_Pos)                 /*!< 0x00008000 */
+#define RTC_CR_TSIE                  RTC_CR_TSIE_Msk                           
+#define RTC_CR_WUTIE_Pos             (14U)                                     
+#define RTC_CR_WUTIE_Msk             (0x1U << RTC_CR_WUTIE_Pos)                /*!< 0x00004000 */
+#define RTC_CR_WUTIE                 RTC_CR_WUTIE_Msk                          
+#define RTC_CR_ALRBIE_Pos            (13U)                                     
+#define RTC_CR_ALRBIE_Msk            (0x1U << RTC_CR_ALRBIE_Pos)               /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                RTC_CR_ALRBIE_Msk                         
+#define RTC_CR_ALRAIE_Pos            (12U)                                     
+#define RTC_CR_ALRAIE_Msk            (0x1U << RTC_CR_ALRAIE_Pos)               /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk                         
+#define RTC_CR_TSE_Pos               (11U)                                     
+#define RTC_CR_TSE_Msk               (0x1U << RTC_CR_TSE_Pos)                  /*!< 0x00000800 */
+#define RTC_CR_TSE                   RTC_CR_TSE_Msk                            
+#define RTC_CR_WUTE_Pos              (10U)                                     
+#define RTC_CR_WUTE_Msk              (0x1U << RTC_CR_WUTE_Pos)                 /*!< 0x00000400 */
+#define RTC_CR_WUTE                  RTC_CR_WUTE_Msk                           
+#define RTC_CR_ALRBE_Pos             (9U)                                      
+#define RTC_CR_ALRBE_Msk             (0x1U << RTC_CR_ALRBE_Pos)                /*!< 0x00000200 */
+#define RTC_CR_ALRBE                 RTC_CR_ALRBE_Msk                          
+#define RTC_CR_ALRAE_Pos             (8U)                                      
+#define RTC_CR_ALRAE_Msk             (0x1U << RTC_CR_ALRAE_Pos)                /*!< 0x00000100 */
+#define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk                          
+#define RTC_CR_FMT_Pos               (6U)                                      
+#define RTC_CR_FMT_Msk               (0x1U << RTC_CR_FMT_Pos)                  /*!< 0x00000040 */
+#define RTC_CR_FMT                   RTC_CR_FMT_Msk                            
+#define RTC_CR_BYPSHAD_Pos           (5U)                                      
+#define RTC_CR_BYPSHAD_Msk           (0x1U << RTC_CR_BYPSHAD_Pos)              /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk                        
+#define RTC_CR_REFCKON_Pos           (4U)                                      
+#define RTC_CR_REFCKON_Msk           (0x1U << RTC_CR_REFCKON_Pos)              /*!< 0x00000010 */
+#define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk                        
+#define RTC_CR_TSEDGE_Pos            (3U)                                      
+#define RTC_CR_TSEDGE_Msk            (0x1U << RTC_CR_TSEDGE_Pos)               /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk                         
+#define RTC_CR_WUCKSEL_Pos           (0U)                                      
+#define RTC_CR_WUCKSEL_Msk           (0x7U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL               RTC_CR_WUCKSEL_Msk                        
+#define RTC_CR_WUCKSEL_0             (0x1U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF_Pos          (16U)                                     
+#define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */
+#define RTC_ISR_RECALPF              RTC_ISR_RECALPF_Msk                       
+#define RTC_ISR_TAMP3F_Pos           (15U)                                     
+#define RTC_ISR_TAMP3F_Msk           (0x1U << RTC_ISR_TAMP3F_Pos)              /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F               RTC_ISR_TAMP3F_Msk                        
+#define RTC_ISR_TAMP2F_Pos           (14U)                                     
+#define RTC_ISR_TAMP2F_Msk           (0x1U << RTC_ISR_TAMP2F_Pos)              /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F               RTC_ISR_TAMP2F_Msk                        
+#define RTC_ISR_TAMP1F_Pos           (13U)                                     
+#define RTC_ISR_TAMP1F_Msk           (0x1U << RTC_ISR_TAMP1F_Pos)              /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F               RTC_ISR_TAMP1F_Msk                        
+#define RTC_ISR_TSOVF_Pos            (12U)                                     
+#define RTC_ISR_TSOVF_Msk            (0x1U << RTC_ISR_TSOVF_Pos)               /*!< 0x00001000 */
+#define RTC_ISR_TSOVF                RTC_ISR_TSOVF_Msk                         
+#define RTC_ISR_TSF_Pos              (11U)                                     
+#define RTC_ISR_TSF_Msk              (0x1U << RTC_ISR_TSF_Pos)                 /*!< 0x00000800 */
+#define RTC_ISR_TSF                  RTC_ISR_TSF_Msk                           
+#define RTC_ISR_WUTF_Pos             (10U)                                     
+#define RTC_ISR_WUTF_Msk             (0x1U << RTC_ISR_WUTF_Pos)                /*!< 0x00000400 */
+#define RTC_ISR_WUTF                 RTC_ISR_WUTF_Msk                          
+#define RTC_ISR_ALRBF_Pos            (9U)                                      
+#define RTC_ISR_ALRBF_Msk            (0x1U << RTC_ISR_ALRBF_Pos)               /*!< 0x00000200 */
+#define RTC_ISR_ALRBF                RTC_ISR_ALRBF_Msk                         
+#define RTC_ISR_ALRAF_Pos            (8U)                                      
+#define RTC_ISR_ALRAF_Msk            (0x1U << RTC_ISR_ALRAF_Pos)               /*!< 0x00000100 */
+#define RTC_ISR_ALRAF                RTC_ISR_ALRAF_Msk                         
+#define RTC_ISR_INIT_Pos             (7U)                                      
+#define RTC_ISR_INIT_Msk             (0x1U << RTC_ISR_INIT_Pos)                /*!< 0x00000080 */
+#define RTC_ISR_INIT                 RTC_ISR_INIT_Msk                          
+#define RTC_ISR_INITF_Pos            (6U)                                      
+#define RTC_ISR_INITF_Msk            (0x1U << RTC_ISR_INITF_Pos)               /*!< 0x00000040 */
+#define RTC_ISR_INITF                RTC_ISR_INITF_Msk                         
+#define RTC_ISR_RSF_Pos              (5U)                                      
+#define RTC_ISR_RSF_Msk              (0x1U << RTC_ISR_RSF_Pos)                 /*!< 0x00000020 */
+#define RTC_ISR_RSF                  RTC_ISR_RSF_Msk                           
+#define RTC_ISR_INITS_Pos            (4U)                                      
+#define RTC_ISR_INITS_Msk            (0x1U << RTC_ISR_INITS_Pos)               /*!< 0x00000010 */
+#define RTC_ISR_INITS                RTC_ISR_INITS_Msk                         
+#define RTC_ISR_SHPF_Pos             (3U)                                      
+#define RTC_ISR_SHPF_Msk             (0x1U << RTC_ISR_SHPF_Pos)                /*!< 0x00000008 */
+#define RTC_ISR_SHPF                 RTC_ISR_SHPF_Msk                          
+#define RTC_ISR_WUTWF_Pos            (2U)                                      
+#define RTC_ISR_WUTWF_Msk            (0x1U << RTC_ISR_WUTWF_Pos)               /*!< 0x00000004 */
+#define RTC_ISR_WUTWF                RTC_ISR_WUTWF_Msk                         
+#define RTC_ISR_ALRBWF_Pos           (1U)                                      
+#define RTC_ISR_ALRBWF_Msk           (0x1U << RTC_ISR_ALRBWF_Pos)              /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF               RTC_ISR_ALRBWF_Msk                        
+#define RTC_ISR_ALRAWF_Pos           (0U)                                      
+#define RTC_ISR_ALRAWF_Msk           (0x1U << RTC_ISR_ALRAWF_Pos)              /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF               RTC_ISR_ALRAWF_Msk                        
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos        (16U)                                     
+#define RTC_PRER_PREDIV_A_Msk        (0x7FU << RTC_PRER_PREDIV_A_Pos)          /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk                     
+#define RTC_PRER_PREDIV_S_Pos        (0U)                                      
+#define RTC_PRER_PREDIV_S_Msk        (0x7FFFU << RTC_PRER_PREDIV_S_Pos)        /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk                     
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos             (0U)                                      
+#define RTC_WUTR_WUT_Msk             (0xFFFFU << RTC_WUTR_WUT_Pos)             /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                 RTC_WUTR_WUT_Msk                          
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos          (31U)                                     
+#define RTC_ALRMAR_MSK4_Msk          (0x1U << RTC_ALRMAR_MSK4_Pos)             /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk                       
+#define RTC_ALRMAR_WDSEL_Pos         (30U)                                     
+#define RTC_ALRMAR_WDSEL_Msk         (0x1U << RTC_ALRMAR_WDSEL_Pos)            /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk                      
+#define RTC_ALRMAR_DT_Pos            (28U)                                     
+#define RTC_ALRMAR_DT_Msk            (0x3U << RTC_ALRMAR_DT_Pos)               /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk                         
+#define RTC_ALRMAR_DT_0              (0x1U << RTC_ALRMAR_DT_Pos)               /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1              (0x2U << RTC_ALRMAR_DT_Pos)               /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos            (24U)                                     
+#define RTC_ALRMAR_DU_Msk            (0xFU << RTC_ALRMAR_DU_Pos)               /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk                         
+#define RTC_ALRMAR_DU_0              (0x1U << RTC_ALRMAR_DU_Pos)               /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1              (0x2U << RTC_ALRMAR_DU_Pos)               /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2              (0x4U << RTC_ALRMAR_DU_Pos)               /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3              (0x8U << RTC_ALRMAR_DU_Pos)               /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos          (23U)                                     
+#define RTC_ALRMAR_MSK3_Msk          (0x1U << RTC_ALRMAR_MSK3_Pos)             /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk                       
+#define RTC_ALRMAR_PM_Pos            (22U)                                     
+#define RTC_ALRMAR_PM_Msk            (0x1U << RTC_ALRMAR_PM_Pos)               /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk                         
+#define RTC_ALRMAR_HT_Pos            (20U)                                     
+#define RTC_ALRMAR_HT_Msk            (0x3U << RTC_ALRMAR_HT_Pos)               /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk                         
+#define RTC_ALRMAR_HT_0              (0x1U << RTC_ALRMAR_HT_Pos)               /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1              (0x2U << RTC_ALRMAR_HT_Pos)               /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos            (16U)                                     
+#define RTC_ALRMAR_HU_Msk            (0xFU << RTC_ALRMAR_HU_Pos)               /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk                         
+#define RTC_ALRMAR_HU_0              (0x1U << RTC_ALRMAR_HU_Pos)               /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1              (0x2U << RTC_ALRMAR_HU_Pos)               /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2              (0x4U << RTC_ALRMAR_HU_Pos)               /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3              (0x8U << RTC_ALRMAR_HU_Pos)               /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos          (15U)                                     
+#define RTC_ALRMAR_MSK2_Msk          (0x1U << RTC_ALRMAR_MSK2_Pos)             /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk                       
+#define RTC_ALRMAR_MNT_Pos           (12U)                                     
+#define RTC_ALRMAR_MNT_Msk           (0x7U << RTC_ALRMAR_MNT_Pos)              /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk                        
+#define RTC_ALRMAR_MNT_0             (0x1U << RTC_ALRMAR_MNT_Pos)              /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1             (0x2U << RTC_ALRMAR_MNT_Pos)              /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2             (0x4U << RTC_ALRMAR_MNT_Pos)              /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos           (8U)                                      
+#define RTC_ALRMAR_MNU_Msk           (0xFU << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk                        
+#define RTC_ALRMAR_MNU_0             (0x1U << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1             (0x2U << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2             (0x4U << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3             (0x8U << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos          (7U)                                      
+#define RTC_ALRMAR_MSK1_Msk          (0x1U << RTC_ALRMAR_MSK1_Pos)             /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk                       
+#define RTC_ALRMAR_ST_Pos            (4U)                                      
+#define RTC_ALRMAR_ST_Msk            (0x7U << RTC_ALRMAR_ST_Pos)               /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk                         
+#define RTC_ALRMAR_ST_0              (0x1U << RTC_ALRMAR_ST_Pos)               /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1              (0x2U << RTC_ALRMAR_ST_Pos)               /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2              (0x4U << RTC_ALRMAR_ST_Pos)               /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos            (0U)                                      
+#define RTC_ALRMAR_SU_Msk            (0xFU << RTC_ALRMAR_SU_Pos)               /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk                         
+#define RTC_ALRMAR_SU_0              (0x1U << RTC_ALRMAR_SU_Pos)               /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1              (0x2U << RTC_ALRMAR_SU_Pos)               /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2              (0x4U << RTC_ALRMAR_SU_Pos)               /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3              (0x8U << RTC_ALRMAR_SU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos          (31U)                                     
+#define RTC_ALRMBR_MSK4_Msk          (0x1U << RTC_ALRMBR_MSK4_Pos)             /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4              RTC_ALRMBR_MSK4_Msk                       
+#define RTC_ALRMBR_WDSEL_Pos         (30U)                                     
+#define RTC_ALRMBR_WDSEL_Msk         (0x1U << RTC_ALRMBR_WDSEL_Pos)            /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL             RTC_ALRMBR_WDSEL_Msk                      
+#define RTC_ALRMBR_DT_Pos            (28U)                                     
+#define RTC_ALRMBR_DT_Msk            (0x3U << RTC_ALRMBR_DT_Pos)               /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                RTC_ALRMBR_DT_Msk                         
+#define RTC_ALRMBR_DT_0              (0x1U << RTC_ALRMBR_DT_Pos)               /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1              (0x2U << RTC_ALRMBR_DT_Pos)               /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos            (24U)                                     
+#define RTC_ALRMBR_DU_Msk            (0xFU << RTC_ALRMBR_DU_Pos)               /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                RTC_ALRMBR_DU_Msk                         
+#define RTC_ALRMBR_DU_0              (0x1U << RTC_ALRMBR_DU_Pos)               /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1              (0x2U << RTC_ALRMBR_DU_Pos)               /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2              (0x4U << RTC_ALRMBR_DU_Pos)               /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3              (0x8U << RTC_ALRMBR_DU_Pos)               /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos          (23U)                                     
+#define RTC_ALRMBR_MSK3_Msk          (0x1U << RTC_ALRMBR_MSK3_Pos)             /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3              RTC_ALRMBR_MSK3_Msk                       
+#define RTC_ALRMBR_PM_Pos            (22U)                                     
+#define RTC_ALRMBR_PM_Msk            (0x1U << RTC_ALRMBR_PM_Pos)               /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                RTC_ALRMBR_PM_Msk                         
+#define RTC_ALRMBR_HT_Pos            (20U)                                     
+#define RTC_ALRMBR_HT_Msk            (0x3U << RTC_ALRMBR_HT_Pos)               /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                RTC_ALRMBR_HT_Msk                         
+#define RTC_ALRMBR_HT_0              (0x1U << RTC_ALRMBR_HT_Pos)               /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1              (0x2U << RTC_ALRMBR_HT_Pos)               /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos            (16U)                                     
+#define RTC_ALRMBR_HU_Msk            (0xFU << RTC_ALRMBR_HU_Pos)               /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                RTC_ALRMBR_HU_Msk                         
+#define RTC_ALRMBR_HU_0              (0x1U << RTC_ALRMBR_HU_Pos)               /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1              (0x2U << RTC_ALRMBR_HU_Pos)               /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2              (0x4U << RTC_ALRMBR_HU_Pos)               /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3              (0x8U << RTC_ALRMBR_HU_Pos)               /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos          (15U)                                     
+#define RTC_ALRMBR_MSK2_Msk          (0x1U << RTC_ALRMBR_MSK2_Pos)             /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2              RTC_ALRMBR_MSK2_Msk                       
+#define RTC_ALRMBR_MNT_Pos           (12U)                                     
+#define RTC_ALRMBR_MNT_Msk           (0x7U << RTC_ALRMBR_MNT_Pos)              /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT               RTC_ALRMBR_MNT_Msk                        
+#define RTC_ALRMBR_MNT_0             (0x1U << RTC_ALRMBR_MNT_Pos)              /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1             (0x2U << RTC_ALRMBR_MNT_Pos)              /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2             (0x4U << RTC_ALRMBR_MNT_Pos)              /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos           (8U)                                      
+#define RTC_ALRMBR_MNU_Msk           (0xFU << RTC_ALRMBR_MNU_Pos)              /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU               RTC_ALRMBR_MNU_Msk                        
+#define RTC_ALRMBR_MNU_0             (0x1U << RTC_ALRMBR_MNU_Pos)              /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1             (0x2U << RTC_ALRMBR_MNU_Pos)              /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2             (0x4U << RTC_ALRMBR_MNU_Pos)              /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3             (0x8U << RTC_ALRMBR_MNU_Pos)              /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos          (7U)                                      
+#define RTC_ALRMBR_MSK1_Msk          (0x1U << RTC_ALRMBR_MSK1_Pos)             /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1              RTC_ALRMBR_MSK1_Msk                       
+#define RTC_ALRMBR_ST_Pos            (4U)                                      
+#define RTC_ALRMBR_ST_Msk            (0x7U << RTC_ALRMBR_ST_Pos)               /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                RTC_ALRMBR_ST_Msk                         
+#define RTC_ALRMBR_ST_0              (0x1U << RTC_ALRMBR_ST_Pos)               /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1              (0x2U << RTC_ALRMBR_ST_Pos)               /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2              (0x4U << RTC_ALRMBR_ST_Pos)               /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos            (0U)                                      
+#define RTC_ALRMBR_SU_Msk            (0xFU << RTC_ALRMBR_SU_Pos)               /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                RTC_ALRMBR_SU_Msk                         
+#define RTC_ALRMBR_SU_0              (0x1U << RTC_ALRMBR_SU_Pos)               /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1              (0x2U << RTC_ALRMBR_SU_Pos)               /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2              (0x4U << RTC_ALRMBR_SU_Pos)               /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3              (0x8U << RTC_ALRMBR_SU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos              (0U)                                      
+#define RTC_WPR_KEY_Msk              (0xFFU << RTC_WPR_KEY_Pos)                /*!< 0x000000FF */
+#define RTC_WPR_KEY                  RTC_WPR_KEY_Msk                           
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos               (0U)                                      
+#define RTC_SSR_SS_Msk               (0xFFFFU << RTC_SSR_SS_Pos)               /*!< 0x0000FFFF */
+#define RTC_SSR_SS                   RTC_SSR_SS_Msk                            
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos         (0U)                                      
+#define RTC_SHIFTR_SUBFS_Msk         (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)         /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk                      
+#define RTC_SHIFTR_ADD1S_Pos         (31U)                                     
+#define RTC_SHIFTR_ADD1S_Msk         (0x1U << RTC_SHIFTR_ADD1S_Pos)            /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk                      
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos              (22U)                                     
+#define RTC_TSTR_PM_Msk              (0x1U << RTC_TSTR_PM_Pos)                 /*!< 0x00400000 */
+#define RTC_TSTR_PM                  RTC_TSTR_PM_Msk                           
+#define RTC_TSTR_HT_Pos              (20U)                                     
+#define RTC_TSTR_HT_Msk              (0x3U << RTC_TSTR_HT_Pos)                 /*!< 0x00300000 */
+#define RTC_TSTR_HT                  RTC_TSTR_HT_Msk                           
+#define RTC_TSTR_HT_0                (0x1U << RTC_TSTR_HT_Pos)                 /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                (0x2U << RTC_TSTR_HT_Pos)                 /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos              (16U)                                     
+#define RTC_TSTR_HU_Msk              (0xFU << RTC_TSTR_HU_Pos)                 /*!< 0x000F0000 */
+#define RTC_TSTR_HU                  RTC_TSTR_HU_Msk                           
+#define RTC_TSTR_HU_0                (0x1U << RTC_TSTR_HU_Pos)                 /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                (0x2U << RTC_TSTR_HU_Pos)                 /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                (0x4U << RTC_TSTR_HU_Pos)                 /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                (0x8U << RTC_TSTR_HU_Pos)                 /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos             (12U)                                     
+#define RTC_TSTR_MNT_Msk             (0x7U << RTC_TSTR_MNT_Pos)                /*!< 0x00007000 */
+#define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk                          
+#define RTC_TSTR_MNT_0               (0x1U << RTC_TSTR_MNT_Pos)                /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1               (0x2U << RTC_TSTR_MNT_Pos)                /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2               (0x4U << RTC_TSTR_MNT_Pos)                /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos             (8U)                                      
+#define RTC_TSTR_MNU_Msk             (0xFU << RTC_TSTR_MNU_Pos)                /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk                          
+#define RTC_TSTR_MNU_0               (0x1U << RTC_TSTR_MNU_Pos)                /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1               (0x2U << RTC_TSTR_MNU_Pos)                /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2               (0x4U << RTC_TSTR_MNU_Pos)                /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3               (0x8U << RTC_TSTR_MNU_Pos)                /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos              (4U)                                      
+#define RTC_TSTR_ST_Msk              (0x7U << RTC_TSTR_ST_Pos)                 /*!< 0x00000070 */
+#define RTC_TSTR_ST                  RTC_TSTR_ST_Msk                           
+#define RTC_TSTR_ST_0                (0x1U << RTC_TSTR_ST_Pos)                 /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                (0x2U << RTC_TSTR_ST_Pos)                 /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                (0x4U << RTC_TSTR_ST_Pos)                 /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos              (0U)                                      
+#define RTC_TSTR_SU_Msk              (0xFU << RTC_TSTR_SU_Pos)                 /*!< 0x0000000F */
+#define RTC_TSTR_SU                  RTC_TSTR_SU_Msk                           
+#define RTC_TSTR_SU_0                (0x1U << RTC_TSTR_SU_Pos)                 /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                (0x2U << RTC_TSTR_SU_Pos)                 /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                (0x4U << RTC_TSTR_SU_Pos)                 /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                (0x8U << RTC_TSTR_SU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos             (13U)                                     
+#define RTC_TSDR_WDU_Msk             (0x7U << RTC_TSDR_WDU_Pos)                /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk                          
+#define RTC_TSDR_WDU_0               (0x1U << RTC_TSDR_WDU_Pos)                /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1               (0x2U << RTC_TSDR_WDU_Pos)                /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2               (0x4U << RTC_TSDR_WDU_Pos)                /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos              (12U)                                     
+#define RTC_TSDR_MT_Msk              (0x1U << RTC_TSDR_MT_Pos)                 /*!< 0x00001000 */
+#define RTC_TSDR_MT                  RTC_TSDR_MT_Msk                           
+#define RTC_TSDR_MU_Pos              (8U)                                      
+#define RTC_TSDR_MU_Msk              (0xFU << RTC_TSDR_MU_Pos)                 /*!< 0x00000F00 */
+#define RTC_TSDR_MU                  RTC_TSDR_MU_Msk                           
+#define RTC_TSDR_MU_0                (0x1U << RTC_TSDR_MU_Pos)                 /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                (0x2U << RTC_TSDR_MU_Pos)                 /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                (0x4U << RTC_TSDR_MU_Pos)                 /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                (0x8U << RTC_TSDR_MU_Pos)                 /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos              (4U)                                      
+#define RTC_TSDR_DT_Msk              (0x3U << RTC_TSDR_DT_Pos)                 /*!< 0x00000030 */
+#define RTC_TSDR_DT                  RTC_TSDR_DT_Msk                           
+#define RTC_TSDR_DT_0                (0x1U << RTC_TSDR_DT_Pos)                 /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                (0x2U << RTC_TSDR_DT_Pos)                 /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos              (0U)                                      
+#define RTC_TSDR_DU_Msk              (0xFU << RTC_TSDR_DU_Pos)                 /*!< 0x0000000F */
+#define RTC_TSDR_DU                  RTC_TSDR_DU_Msk                           
+#define RTC_TSDR_DU_0                (0x1U << RTC_TSDR_DU_Pos)                 /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                (0x2U << RTC_TSDR_DU_Pos)                 /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                (0x4U << RTC_TSDR_DU_Pos)                 /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                (0x8U << RTC_TSDR_DU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos             (0U)                                      
+#define RTC_TSSSR_SS_Msk             (0xFFFFU << RTC_TSSSR_SS_Pos)             /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk                          
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP_Pos            (15U)                                     
+#define RTC_CALR_CALP_Msk            (0x1U << RTC_CALR_CALP_Pos)               /*!< 0x00008000 */
+#define RTC_CALR_CALP                RTC_CALR_CALP_Msk                         
+#define RTC_CALR_CALW8_Pos           (14U)                                     
+#define RTC_CALR_CALW8_Msk           (0x1U << RTC_CALR_CALW8_Pos)              /*!< 0x00004000 */
+#define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk                        
+#define RTC_CALR_CALW16_Pos          (13U)                                     
+#define RTC_CALR_CALW16_Msk          (0x1U << RTC_CALR_CALW16_Pos)             /*!< 0x00002000 */
+#define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk                       
+#define RTC_CALR_CALM_Pos            (0U)                                      
+#define RTC_CALR_CALM_Msk            (0x1FFU << RTC_CALR_CALM_Pos)             /*!< 0x000001FF */
+#define RTC_CALR_CALM                RTC_CALR_CALM_Msk                         
+#define RTC_CALR_CALM_0              (0x001U << RTC_CALR_CALM_Pos)             /*!< 0x00000001 */
+#define RTC_CALR_CALM_1              (0x002U << RTC_CALR_CALM_Pos)             /*!< 0x00000002 */
+#define RTC_CALR_CALM_2              (0x004U << RTC_CALR_CALM_Pos)             /*!< 0x00000004 */
+#define RTC_CALR_CALM_3              (0x008U << RTC_CALR_CALM_Pos)             /*!< 0x00000008 */
+#define RTC_CALR_CALM_4              (0x010U << RTC_CALR_CALM_Pos)             /*!< 0x00000010 */
+#define RTC_CALR_CALM_5              (0x020U << RTC_CALR_CALM_Pos)             /*!< 0x00000020 */
+#define RTC_CALR_CALM_6              (0x040U << RTC_CALR_CALM_Pos)             /*!< 0x00000040 */
+#define RTC_CALR_CALM_7              (0x080U << RTC_CALR_CALM_Pos)             /*!< 0x00000080 */
+#define RTC_CALR_CALM_8              (0x100U << RTC_CALR_CALM_Pos)             /*!< 0x00000100 */
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_PC15MODE_Pos       (23U)                                     
+#define RTC_TAFCR_PC15MODE_Msk       (0x1U << RTC_TAFCR_PC15MODE_Pos)          /*!< 0x00800000 */
+#define RTC_TAFCR_PC15MODE           RTC_TAFCR_PC15MODE_Msk                    
+#define RTC_TAFCR_PC15VALUE_Pos      (22U)                                     
+#define RTC_TAFCR_PC15VALUE_Msk      (0x1U << RTC_TAFCR_PC15VALUE_Pos)         /*!< 0x00400000 */
+#define RTC_TAFCR_PC15VALUE          RTC_TAFCR_PC15VALUE_Msk                   
+#define RTC_TAFCR_PC14MODE_Pos       (21U)                                     
+#define RTC_TAFCR_PC14MODE_Msk       (0x1U << RTC_TAFCR_PC14MODE_Pos)          /*!< 0x00200000 */
+#define RTC_TAFCR_PC14MODE           RTC_TAFCR_PC14MODE_Msk                    
+#define RTC_TAFCR_PC14VALUE_Pos      (20U)                                     
+#define RTC_TAFCR_PC14VALUE_Msk      (0x1U << RTC_TAFCR_PC14VALUE_Pos)         /*!< 0x00100000 */
+#define RTC_TAFCR_PC14VALUE          RTC_TAFCR_PC14VALUE_Msk                   
+#define RTC_TAFCR_PC13MODE_Pos       (19U)                                     
+#define RTC_TAFCR_PC13MODE_Msk       (0x1U << RTC_TAFCR_PC13MODE_Pos)          /*!< 0x00080000 */
+#define RTC_TAFCR_PC13MODE           RTC_TAFCR_PC13MODE_Msk                    
+#define RTC_TAFCR_PC13VALUE_Pos      (18U)                                     
+#define RTC_TAFCR_PC13VALUE_Msk      (0x1U << RTC_TAFCR_PC13VALUE_Pos)         /*!< 0x00040000 */
+#define RTC_TAFCR_PC13VALUE          RTC_TAFCR_PC13VALUE_Msk                   
+#define RTC_TAFCR_TAMPPUDIS_Pos      (15U)                                     
+#define RTC_TAFCR_TAMPPUDIS_Msk      (0x1U << RTC_TAFCR_TAMPPUDIS_Pos)         /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS          RTC_TAFCR_TAMPPUDIS_Msk                   
+#define RTC_TAFCR_TAMPPRCH_Pos       (13U)                                     
+#define RTC_TAFCR_TAMPPRCH_Msk       (0x3U << RTC_TAFCR_TAMPPRCH_Pos)          /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH           RTC_TAFCR_TAMPPRCH_Msk                    
+#define RTC_TAFCR_TAMPPRCH_0         (0x1U << RTC_TAFCR_TAMPPRCH_Pos)          /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1         (0x2U << RTC_TAFCR_TAMPPRCH_Pos)          /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos        (11U)                                     
+#define RTC_TAFCR_TAMPFLT_Msk        (0x3U << RTC_TAFCR_TAMPFLT_Pos)           /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT            RTC_TAFCR_TAMPFLT_Msk                     
+#define RTC_TAFCR_TAMPFLT_0          (0x1U << RTC_TAFCR_TAMPFLT_Pos)           /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1          (0x2U << RTC_TAFCR_TAMPFLT_Pos)           /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos       (8U)                                      
+#define RTC_TAFCR_TAMPFREQ_Msk       (0x7U << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ           RTC_TAFCR_TAMPFREQ_Msk                    
+#define RTC_TAFCR_TAMPFREQ_0         (0x1U << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1         (0x2U << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2         (0x4U << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos         (7U)                                      
+#define RTC_TAFCR_TAMPTS_Msk         (0x1U << RTC_TAFCR_TAMPTS_Pos)            /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS             RTC_TAFCR_TAMPTS_Msk                      
+#define RTC_TAFCR_TAMP3TRG_Pos       (6U)                                      
+#define RTC_TAFCR_TAMP3TRG_Msk       (0x1U << RTC_TAFCR_TAMP3TRG_Pos)          /*!< 0x00000040 */
+#define RTC_TAFCR_TAMP3TRG           RTC_TAFCR_TAMP3TRG_Msk                    
+#define RTC_TAFCR_TAMP3E_Pos         (5U)                                      
+#define RTC_TAFCR_TAMP3E_Msk         (0x1U << RTC_TAFCR_TAMP3E_Pos)            /*!< 0x00000020 */
+#define RTC_TAFCR_TAMP3E             RTC_TAFCR_TAMP3E_Msk                      
+#define RTC_TAFCR_TAMP2TRG_Pos       (4U)                                      
+#define RTC_TAFCR_TAMP2TRG_Msk       (0x1U << RTC_TAFCR_TAMP2TRG_Pos)          /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG           RTC_TAFCR_TAMP2TRG_Msk                    
+#define RTC_TAFCR_TAMP2E_Pos         (3U)                                      
+#define RTC_TAFCR_TAMP2E_Msk         (0x1U << RTC_TAFCR_TAMP2E_Pos)            /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E             RTC_TAFCR_TAMP2E_Msk                      
+#define RTC_TAFCR_TAMPIE_Pos         (2U)                                      
+#define RTC_TAFCR_TAMPIE_Msk         (0x1U << RTC_TAFCR_TAMPIE_Pos)            /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE             RTC_TAFCR_TAMPIE_Msk                      
+#define RTC_TAFCR_TAMP1TRG_Pos       (1U)                                      
+#define RTC_TAFCR_TAMP1TRG_Msk       (0x1U << RTC_TAFCR_TAMP1TRG_Pos)          /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG           RTC_TAFCR_TAMP1TRG_Msk                    
+#define RTC_TAFCR_TAMP1E_Pos         (0U)                                      
+#define RTC_TAFCR_TAMP1E_Msk         (0x1U << RTC_TAFCR_TAMP1E_Pos)            /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E             RTC_TAFCR_TAMP1E_Msk                      
+
+/* Reference defines */
+#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_PC13VALUE
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos      (24U)                                     
+#define RTC_ALRMASSR_MASKSS_Msk      (0xFU << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk                   
+#define RTC_ALRMASSR_MASKSS_0        (0x1U << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1        (0x2U << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2        (0x4U << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3        (0x8U << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos          (0U)                                      
+#define RTC_ALRMASSR_SS_Msk          (0x7FFFU << RTC_ALRMASSR_SS_Pos)          /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk                       
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos      (24U)                                     
+#define RTC_ALRMBSSR_MASKSS_Msk      (0xFU << RTC_ALRMBSSR_MASKSS_Pos)         /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS          RTC_ALRMBSSR_MASKSS_Msk                   
+#define RTC_ALRMBSSR_MASKSS_0        (0x1U << RTC_ALRMBSSR_MASKSS_Pos)         /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1        (0x2U << RTC_ALRMBSSR_MASKSS_Pos)         /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2        (0x4U << RTC_ALRMBSSR_MASKSS_Pos)         /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3        (0x8U << RTC_ALRMBSSR_MASKSS_Pos)         /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos          (0U)                                      
+#define RTC_ALRMBSSR_SS_Msk          (0x7FFFU << RTC_ALRMBSSR_SS_Pos)          /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS              RTC_ALRMBSSR_SS_Msk                       
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R_Pos                (0U)                                      
+#define RTC_BKP0R_Msk                (0xFFFFFFFFU << RTC_BKP0R_Pos)            /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                    RTC_BKP0R_Msk                             
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R_Pos                (0U)                                      
+#define RTC_BKP1R_Msk                (0xFFFFFFFFU << RTC_BKP1R_Pos)            /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                    RTC_BKP1R_Msk                             
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R_Pos                (0U)                                      
+#define RTC_BKP2R_Msk                (0xFFFFFFFFU << RTC_BKP2R_Pos)            /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                    RTC_BKP2R_Msk                             
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R_Pos                (0U)                                      
+#define RTC_BKP3R_Msk                (0xFFFFFFFFU << RTC_BKP3R_Pos)            /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                    RTC_BKP3R_Msk                             
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R_Pos                (0U)                                      
+#define RTC_BKP4R_Msk                (0xFFFFFFFFU << RTC_BKP4R_Pos)            /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                    RTC_BKP4R_Msk                             
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R_Pos                (0U)                                      
+#define RTC_BKP5R_Msk                (0xFFFFFFFFU << RTC_BKP5R_Pos)            /*!< 0xFFFFFFFF */
+#define RTC_BKP5R                    RTC_BKP5R_Msk                             
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R_Pos                (0U)                                      
+#define RTC_BKP6R_Msk                (0xFFFFFFFFU << RTC_BKP6R_Pos)            /*!< 0xFFFFFFFF */
+#define RTC_BKP6R                    RTC_BKP6R_Msk                             
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R_Pos                (0U)                                      
+#define RTC_BKP7R_Msk                (0xFFFFFFFFU << RTC_BKP7R_Pos)            /*!< 0xFFFFFFFF */
+#define RTC_BKP7R                    RTC_BKP7R_Msk                             
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R_Pos                (0U)                                      
+#define RTC_BKP8R_Msk                (0xFFFFFFFFU << RTC_BKP8R_Pos)            /*!< 0xFFFFFFFF */
+#define RTC_BKP8R                    RTC_BKP8R_Msk                             
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R_Pos                (0U)                                      
+#define RTC_BKP9R_Msk                (0xFFFFFFFFU << RTC_BKP9R_Pos)            /*!< 0xFFFFFFFF */
+#define RTC_BKP9R                    RTC_BKP9R_Msk                             
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R_Pos               (0U)                                      
+#define RTC_BKP10R_Msk               (0xFFFFFFFFU << RTC_BKP10R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP10R                   RTC_BKP10R_Msk                            
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R_Pos               (0U)                                      
+#define RTC_BKP11R_Msk               (0xFFFFFFFFU << RTC_BKP11R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP11R                   RTC_BKP11R_Msk                            
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R_Pos               (0U)                                      
+#define RTC_BKP12R_Msk               (0xFFFFFFFFU << RTC_BKP12R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP12R                   RTC_BKP12R_Msk                            
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R_Pos               (0U)                                      
+#define RTC_BKP13R_Msk               (0xFFFFFFFFU << RTC_BKP13R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP13R                   RTC_BKP13R_Msk                            
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R_Pos               (0U)                                      
+#define RTC_BKP14R_Msk               (0xFFFFFFFFU << RTC_BKP14R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP14R                   RTC_BKP14R_Msk                            
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R_Pos               (0U)                                      
+#define RTC_BKP15R_Msk               (0xFFFFFFFFU << RTC_BKP15R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP15R                   RTC_BKP15R_Msk                            
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER                       16
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ */
+#define SPI_I2S_SUPPORT                       /*!< I2S support */
+#define SPI_I2S_FULLDUPLEX_SUPPORT            /*!< I2S Full-Duplex support */
+
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_CPHA_Pos            (0U)                                       
+#define SPI_CR1_CPHA_Msk            (0x1U << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
+#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos            (1U)                                       
+#define SPI_CR1_CPOL_Msk            (0x1U << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
+#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos            (2U)                                       
+#define SPI_CR1_MSTR_Msk            (0x1U << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
+#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
+#define SPI_CR1_BR_Pos              (3U)                                       
+#define SPI_CR1_BR_Msk              (0x7U << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
+#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0                (0x1U << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
+#define SPI_CR1_BR_1                (0x2U << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
+#define SPI_CR1_BR_2                (0x4U << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
+#define SPI_CR1_SPE_Pos             (6U)                                       
+#define SPI_CR1_SPE_Msk             (0x1U << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos        (7U)                                       
+#define SPI_CR1_LSBFIRST_Msk        (0x1U << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
+#define SPI_CR1_SSI_Pos             (8U)                                       
+#define SPI_CR1_SSI_Msk             (0x1U << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos             (9U)                                       
+#define SPI_CR1_SSM_Msk             (0x1U << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
+#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos          (10U)                                      
+#define SPI_CR1_RXONLY_Msk          (0x1U << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
+#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
+#define SPI_CR1_CRCL_Pos            (11U)                                      
+#define SPI_CR1_CRCL_Msk            (0x1U << SPI_CR1_CRCL_Pos)                 /*!< 0x00000800 */
+#define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
+#define SPI_CR1_CRCNEXT_Pos         (12U)                                      
+#define SPI_CR1_CRCNEXT_Msk         (0x1U << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos           (13U)                                      
+#define SPI_CR1_CRCEN_Msk           (0x1U << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
+#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos          (14U)                                      
+#define SPI_CR1_BIDIOE_Msk          (0x1U << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos        (15U)                                      
+#define SPI_CR1_BIDIMODE_Msk        (0x1U << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_RXDMAEN_Pos         (0U)                                       
+#define SPI_CR2_RXDMAEN_Msk         (0x1U << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos         (1U)                                       
+#define SPI_CR2_TXDMAEN_Msk         (0x1U << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos            (2U)                                       
+#define SPI_CR2_SSOE_Msk            (0x1U << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
+#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
+#define SPI_CR2_NSSP_Pos            (3U)                                       
+#define SPI_CR2_NSSP_Msk            (0x1U << SPI_CR2_NSSP_Pos)                 /*!< 0x00000008 */
+#define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF_Pos             (4U)                                       
+#define SPI_CR2_FRF_Msk             (0x1U << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
+#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos           (5U)                                       
+#define SPI_CR2_ERRIE_Msk           (0x1U << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
+#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos          (6U)                                       
+#define SPI_CR2_RXNEIE_Msk          (0x1U << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos           (7U)                                       
+#define SPI_CR2_TXEIE_Msk           (0x1U << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
+#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS_Pos              (8U)                                       
+#define SPI_CR2_DS_Msk              (0xFU << SPI_CR2_DS_Pos)                   /*!< 0x00000F00 */
+#define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0                (0x1U << SPI_CR2_DS_Pos)                   /*!< 0x00000100 */
+#define SPI_CR2_DS_1                (0x2U << SPI_CR2_DS_Pos)                   /*!< 0x00000200 */
+#define SPI_CR2_DS_2                (0x4U << SPI_CR2_DS_Pos)                   /*!< 0x00000400 */
+#define SPI_CR2_DS_3                (0x8U << SPI_CR2_DS_Pos)                   /*!< 0x00000800 */
+#define SPI_CR2_FRXTH_Pos           (12U)                                      
+#define SPI_CR2_FRXTH_Msk           (0x1U << SPI_CR2_FRXTH_Pos)                /*!< 0x00001000 */
+#define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX_Pos          (13U)                                      
+#define SPI_CR2_LDMARX_Msk          (0x1U << SPI_CR2_LDMARX_Pos)               /*!< 0x00002000 */
+#define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX_Pos          (14U)                                      
+#define SPI_CR2_LDMATX_Msk          (0x1U << SPI_CR2_LDMATX_Pos)               /*!< 0x00004000 */
+#define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXNE_Pos             (0U)                                       
+#define SPI_SR_RXNE_Msk             (0x1U << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
+#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos              (1U)                                       
+#define SPI_SR_TXE_Msk              (0x1U << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
+#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos           (2U)                                       
+#define SPI_SR_CHSIDE_Msk           (0x1U << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
+#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
+#define SPI_SR_UDR_Pos              (3U)                                       
+#define SPI_SR_UDR_Msk              (0x1U << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos           (4U)                                       
+#define SPI_SR_CRCERR_Msk           (0x1U << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
+#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos             (5U)                                       
+#define SPI_SR_MODF_Msk             (0x1U << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
+#define SPI_SR_OVR_Pos              (6U)                                       
+#define SPI_SR_OVR_Msk              (0x1U << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
+#define SPI_SR_BSY_Pos              (7U)                                       
+#define SPI_SR_BSY_Msk              (0x1U << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
+#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
+#define SPI_SR_FRE_Pos              (8U)                                       
+#define SPI_SR_FRE_Msk              (0x1U << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
+#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
+#define SPI_SR_FRLVL_Pos            (9U)                                       
+#define SPI_SR_FRLVL_Msk            (0x3U << SPI_SR_FRLVL_Pos)                 /*!< 0x00000600 */
+#define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0              (0x1U << SPI_SR_FRLVL_Pos)                 /*!< 0x00000200 */
+#define SPI_SR_FRLVL_1              (0x2U << SPI_SR_FRLVL_Pos)                 /*!< 0x00000400 */
+#define SPI_SR_FTLVL_Pos            (11U)                                      
+#define SPI_SR_FTLVL_Msk            (0x3U << SPI_SR_FTLVL_Pos)                 /*!< 0x00001800 */
+#define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0              (0x1U << SPI_SR_FTLVL_Pos)                 /*!< 0x00000800 */
+#define SPI_SR_FTLVL_1              (0x2U << SPI_SR_FTLVL_Pos)                 /*!< 0x00001000 */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define SPI_DR_DR_Pos               (0U)                                       
+#define SPI_DR_DR_Msk               (0xFFFFU << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
+#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define SPI_CRCPR_CRCPOLY_Pos       (0U)                                       
+#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define SPI_RXCRCR_RXCRC_Pos        (0U)                                       
+#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define SPI_TXCRCR_TXCRC_Pos        (0U)                                       
+#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define SPI_I2SCFGR_CHLEN_Pos       (0U)                                       
+#define SPI_I2SCFGR_CHLEN_Msk       (0x1U << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN_Pos      (1U)                                       
+#define SPI_I2SCFGR_DATLEN_Msk      (0x3U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0        (0x1U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1        (0x2U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
+#define SPI_I2SCFGR_CKPOL_Pos       (3U)                                       
+#define SPI_I2SCFGR_CKPOL_Msk       (0x1U << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)                                       
+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0        (0x1U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1        (0x2U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)                                       
+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1U << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG_Pos      (8U)                                       
+#define SPI_I2SCFGR_I2SCFG_Msk      (0x3U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0        (0x1U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1        (0x2U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
+#define SPI_I2SCFGR_I2SE_Pos        (10U)                                      
+#define SPI_I2SCFGR_I2SE_Msk        (0x1U << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos      (11U)                                      
+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1U << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define SPI_I2SPR_I2SDIV_Pos        (0U)                                       
+#define SPI_I2SPR_I2SDIV_Msk        (0xFFU << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos           (8U)                                       
+#define SPI_I2SPR_ODD_Msk           (0x1U << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
+#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos         (9U)                                       
+#define SPI_I2SPR_MCKOE_Msk         (0x1U << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        System Configuration(SYSCFG)                        */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
+#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
+#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x7U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000007 */
+#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0                  (0x00000001U)                 /*!< Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1                  (0x00000002U)                 /*!< Bit 1 */
+#define SYSCFG_CFGR1_MEM_MODE_2                  (0x00000004U)                 /*!< Bit 2 */
+#define SYSCFG_CFGR1_USB_IT_RMP_Pos              (5U)                          
+#define SYSCFG_CFGR1_USB_IT_RMP_Msk              (0x1U << SYSCFG_CFGR1_USB_IT_RMP_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR1_USB_IT_RMP                  SYSCFG_CFGR1_USB_IT_RMP_Msk   /*!< USB interrupt remap */
+#define SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos           (6U)                          
+#define SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk           (0x1U << SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos) /*!< 0x00000040 */
+#define SYSCFG_CFGR1_TIM1_ITR3_RMP               SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk /*!< Timer 1 ITR3 selection */
+#define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos          (7U)                          
+#define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk          (0x1U << SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos) /*!< 0x00000080 */
+#define SYSCFG_CFGR1_DAC1_TRIG1_RMP              SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk /*!< DAC1 Trigger1 remap */
+#define SYSCFG_CFGR1_DMA_RMP_Pos                 (8U)                          
+#define SYSCFG_CFGR1_DMA_RMP_Msk                 (0x79U << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x00007900 */
+#define SYSCFG_CFGR1_DMA_RMP                     SYSCFG_CFGR1_DMA_RMP_Msk      /*!< DMA remap mask */
+#define SYSCFG_CFGR1_ADC24_DMA_RMP_Pos           (8U)                          
+#define SYSCFG_CFGR1_ADC24_DMA_RMP_Msk           (0x1U << SYSCFG_CFGR1_ADC24_DMA_RMP_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_ADC24_DMA_RMP               SYSCFG_CFGR1_ADC24_DMA_RMP_Msk /*!< ADC2 and ADC4 DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos           (11U)                         
+#define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk           (0x1U << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP               SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos           (12U)                         
+#define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk           (0x1U << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP               SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos     (13U)                         
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk     (0x1U << SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos) /*!< 0x00002000 */
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP         SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk /*!< Timer 6 / DAC1 Ch1 DMA remap */
+#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos     (14U)                         
+#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk     (0x1U << SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos) /*!< 0x00004000 */
+#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP         SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk /*!< Timer 7 / DAC1 Ch2 DMA remap */
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos             (16U)                         
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk             (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
+#define SYSCFG_CFGR1_I2C_PB6_FMP                 SYSCFG_CFGR1_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos             (17U)                         
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk             (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
+#define SYSCFG_CFGR1_I2C_PB7_FMP                 SYSCFG_CFGR1_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos             (18U)                         
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk             (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
+#define SYSCFG_CFGR1_I2C_PB8_FMP                 SYSCFG_CFGR1_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos             (19U)                         
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk             (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
+#define SYSCFG_CFGR1_I2C_PB9_FMP                 SYSCFG_CFGR1_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP_Pos                (20U)                         
+#define SYSCFG_CFGR1_I2C1_FMP_Msk                (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
+#define SYSCFG_CFGR1_I2C1_FMP                    SYSCFG_CFGR1_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR1_I2C2_FMP_Pos                (21U)                         
+#define SYSCFG_CFGR1_I2C2_FMP_Msk                (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
+#define SYSCFG_CFGR1_I2C2_FMP                    SYSCFG_CFGR1_I2C2_FMP_Msk     /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR1_ENCODER_MODE_Pos            (22U)                         
+#define SYSCFG_CFGR1_ENCODER_MODE_Msk            (0x3U << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00C00000 */
+#define SYSCFG_CFGR1_ENCODER_MODE                SYSCFG_CFGR1_ENCODER_MODE_Msk /*!< Encoder Mode */
+#define SYSCFG_CFGR1_ENCODER_MODE_0              (0x1U << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00400000 */
+#define SYSCFG_CFGR1_ENCODER_MODE_1              (0x2U << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00800000 */
+#define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos       (22U)                         
+#define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk       (0x1U << SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos) /*!< 0x00400000 */
+#define SYSCFG_CFGR1_ENCODER_MODE_TIM2           SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
+#define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos       (23U)                         
+#define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk       (0x1U << SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos) /*!< 0x00800000 */
+#define SYSCFG_CFGR1_ENCODER_MODE_TIM3           SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
+#define SYSCFG_CFGR1_I2C3_FMP_Pos                (24U)                         
+#define SYSCFG_CFGR1_I2C3_FMP_Msk                (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x01000000 */
+#define SYSCFG_CFGR1_I2C3_FMP                    SYSCFG_CFGR1_I2C3_FMP_Msk     /*!< I2C3 Fast mode plus */
+#define SYSCFG_CFGR1_FPU_IE_Pos                  (26U)                         
+#define SYSCFG_CFGR1_FPU_IE_Msk                  (0x3FU << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0xFC000000 */
+#define SYSCFG_CFGR1_FPU_IE                      SYSCFG_CFGR1_FPU_IE_Msk       /*!< Floating Point Unit Interrupt Enable */
+#define SYSCFG_CFGR1_FPU_IE_0                    (0x01U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x04000000 */
+#define SYSCFG_CFGR1_FPU_IE_1                    (0x02U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x08000000 */
+#define SYSCFG_CFGR1_FPU_IE_2                    (0x04U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x10000000 */
+#define SYSCFG_CFGR1_FPU_IE_3                    (0x08U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x20000000 */
+#define SYSCFG_CFGR1_FPU_IE_4                    (0x10U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x40000000 */
+#define SYSCFG_CFGR1_FPU_IE_5                    (0x20U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x80000000 */
+
+/*****************  Bit definition for SYSCFG_RCR register  *******************/
+#define SYSCFG_RCR_PAGE0_Pos                     (0U)                          
+#define SYSCFG_RCR_PAGE0_Msk                     (0x1U << SYSCFG_RCR_PAGE0_Pos) /*!< 0x00000001 */
+#define SYSCFG_RCR_PAGE0                         SYSCFG_RCR_PAGE0_Msk          /*!< ICODE SRAM Write protection page 0 */
+#define SYSCFG_RCR_PAGE1_Pos                     (1U)                          
+#define SYSCFG_RCR_PAGE1_Msk                     (0x1U << SYSCFG_RCR_PAGE1_Pos) /*!< 0x00000002 */
+#define SYSCFG_RCR_PAGE1                         SYSCFG_RCR_PAGE1_Msk          /*!< ICODE SRAM Write protection page 1 */
+#define SYSCFG_RCR_PAGE2_Pos                     (2U)                          
+#define SYSCFG_RCR_PAGE2_Msk                     (0x1U << SYSCFG_RCR_PAGE2_Pos) /*!< 0x00000004 */
+#define SYSCFG_RCR_PAGE2                         SYSCFG_RCR_PAGE2_Msk          /*!< ICODE SRAM Write protection page 2 */
+#define SYSCFG_RCR_PAGE3_Pos                     (3U)                          
+#define SYSCFG_RCR_PAGE3_Msk                     (0x1U << SYSCFG_RCR_PAGE3_Pos) /*!< 0x00000008 */
+#define SYSCFG_RCR_PAGE3                         SYSCFG_RCR_PAGE3_Msk          /*!< ICODE SRAM Write protection page 3 */
+#define SYSCFG_RCR_PAGE4_Pos                     (4U)                          
+#define SYSCFG_RCR_PAGE4_Msk                     (0x1U << SYSCFG_RCR_PAGE4_Pos) /*!< 0x00000010 */
+#define SYSCFG_RCR_PAGE4                         SYSCFG_RCR_PAGE4_Msk          /*!< ICODE SRAM Write protection page 4 */
+#define SYSCFG_RCR_PAGE5_Pos                     (5U)                          
+#define SYSCFG_RCR_PAGE5_Msk                     (0x1U << SYSCFG_RCR_PAGE5_Pos) /*!< 0x00000020 */
+#define SYSCFG_RCR_PAGE5                         SYSCFG_RCR_PAGE5_Msk          /*!< ICODE SRAM Write protection page 5 */
+#define SYSCFG_RCR_PAGE6_Pos                     (6U)                          
+#define SYSCFG_RCR_PAGE6_Msk                     (0x1U << SYSCFG_RCR_PAGE6_Pos) /*!< 0x00000040 */
+#define SYSCFG_RCR_PAGE6                         SYSCFG_RCR_PAGE6_Msk          /*!< ICODE SRAM Write protection page 6 */
+#define SYSCFG_RCR_PAGE7_Pos                     (7U)                          
+#define SYSCFG_RCR_PAGE7_Msk                     (0x1U << SYSCFG_RCR_PAGE7_Pos) /*!< 0x00000080 */
+#define SYSCFG_RCR_PAGE7                         SYSCFG_RCR_PAGE7_Msk          /*!< ICODE SRAM Write protection page 7 */
+#define SYSCFG_RCR_PAGE8_Pos                     (8U)                          
+#define SYSCFG_RCR_PAGE8_Msk                     (0x1U << SYSCFG_RCR_PAGE8_Pos) /*!< 0x00000100 */
+#define SYSCFG_RCR_PAGE8                         SYSCFG_RCR_PAGE8_Msk          /*!< ICODE SRAM Write protection page 8 */
+#define SYSCFG_RCR_PAGE9_Pos                     (9U)                          
+#define SYSCFG_RCR_PAGE9_Msk                     (0x1U << SYSCFG_RCR_PAGE9_Pos) /*!< 0x00000200 */
+#define SYSCFG_RCR_PAGE9                         SYSCFG_RCR_PAGE9_Msk          /*!< ICODE SRAM Write protection page 9 */
+#define SYSCFG_RCR_PAGE10_Pos                    (10U)                         
+#define SYSCFG_RCR_PAGE10_Msk                    (0x1U << SYSCFG_RCR_PAGE10_Pos) /*!< 0x00000400 */
+#define SYSCFG_RCR_PAGE10                        SYSCFG_RCR_PAGE10_Msk         /*!< ICODE SRAM Write protection page 10 */
+#define SYSCFG_RCR_PAGE11_Pos                    (11U)                         
+#define SYSCFG_RCR_PAGE11_Msk                    (0x1U << SYSCFG_RCR_PAGE11_Pos) /*!< 0x00000800 */
+#define SYSCFG_RCR_PAGE11                        SYSCFG_RCR_PAGE11_Msk         /*!< ICODE SRAM Write protection page 11 */
+#define SYSCFG_RCR_PAGE12_Pos                    (12U)                         
+#define SYSCFG_RCR_PAGE12_Msk                    (0x1U << SYSCFG_RCR_PAGE12_Pos) /*!< 0x00001000 */
+#define SYSCFG_RCR_PAGE12                        SYSCFG_RCR_PAGE12_Msk         /*!< ICODE SRAM Write protection page 12 */
+#define SYSCFG_RCR_PAGE13_Pos                    (13U)                         
+#define SYSCFG_RCR_PAGE13_Msk                    (0x1U << SYSCFG_RCR_PAGE13_Pos) /*!< 0x00002000 */
+#define SYSCFG_RCR_PAGE13                        SYSCFG_RCR_PAGE13_Msk         /*!< ICODE SRAM Write protection page 13 */
+#define SYSCFG_RCR_PAGE14_Pos                    (14U)                         
+#define SYSCFG_RCR_PAGE14_Msk                    (0x1U << SYSCFG_RCR_PAGE14_Pos) /*!< 0x00004000 */
+#define SYSCFG_RCR_PAGE14                        SYSCFG_RCR_PAGE14_Msk         /*!< ICODE SRAM Write protection page 14 */
+#define SYSCFG_RCR_PAGE15_Pos                    (15U)                         
+#define SYSCFG_RCR_PAGE15_Msk                    (0x1U << SYSCFG_RCR_PAGE15_Pos) /*!< 0x00008000 */
+#define SYSCFG_RCR_PAGE15                        SYSCFG_RCR_PAGE15_Msk         /*!< ICODE SRAM Write protection page 15 */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
+#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
+#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
+#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
+#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
+
+/*!<*
+  * @brief  EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD                  (0x00000003U)                 /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE                  (0x00000004U)                 /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF                  (0x00000005U)                 /*!< PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG                  (0x00000006U)                 /*!< PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000007U)                 /*!< PH[0] pin */
+
+/*!<*
+  * @brief  EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD                  (0x00000030U)                 /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE                  (0x00000040U)                 /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF                  (0x00000050U)                 /*!< PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG                  (0x00000060U)                 /*!< PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000070U)                 /*!< PH[1] pin */
+
+/*!<*
+  * @brief  EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE                  (0x00000400U)                 /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF                  (0x00000500U)                 /*!< PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG                  (0x00000600U)                 /*!< PG[2] pin */
+
+/*!<*
+  * @brief  EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD                  (0x00003000U)                 /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE                  (0x00004000U)                 /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF                  (0x00005000U)                 /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG                  (0x00006000U)                 /*!< PG[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
+#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
+#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
+#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
+#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
+
+/*!<*
+  * @brief  EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD                  (0x00000003U)                 /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE                  (0x00000004U)                 /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF                  (0x00000005U)                 /*!< PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG                  (0x00000006U)                 /*!< PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH                  (0x00000007U)                 /*!< PH[4] pin */
+
+/*!<*
+  * @brief  EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD                  (0x00000030U)                 /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE                  (0x00000040U)                 /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF                  (0x00000050U)                 /*!< PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG                  (0x00000060U)                 /*!< PG[5] pin */
+
+/*!<*
+  * @brief  EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD                  (0x00000300U)                 /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE                  (0x00000400U)                 /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF                  (0x00000500U)                 /*!< PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG                  (0x00000600U)                 /*!< PG[6] pin */
+
+/*!<*
+  * @brief  EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD                  (0x00003000U)                 /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE                  (0x00004000U)                 /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF                  (0x00005000U)                 /*!< PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG                  (0x00006000U)                 /*!< PG[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
+#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
+#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
+#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
+#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
+
+/*!<*
+  * @brief  EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD                  (0x00000003U)                 /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE                  (0x00000004U)                 /*!< PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF                  (0x00000005U)                 /*!< PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG                  (0x00000006U)                 /*!< PG[8] pin */
+
+/*!<*
+  * @brief  EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD                  (0x00000030U)                 /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE                  (0x00000040U)                 /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF                  (0x00000050U)                 /*!< PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG                  (0x00000060U)                 /*!< PG[9] pin */
+
+/*!<*
+  * @brief  EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD                 (0x00000300U)                 /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE                 (0x00000400U)                 /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF                 (0x00000500U)                 /*!< PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG                 (0x00000600U)                 /*!< PG[10] pin */
+
+/*!<*
+  * @brief  EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD                 (0x00003000U)                 /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE                 (0x00004000U)                 /*!< PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF                 (0x00005000U)                 /*!< PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG                 (0x00006000U)                 /*!< PG[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
+#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
+#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
+#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
+#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
+
+/*!<*
+  * @brief  EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD                 (0x00000003U)                 /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE                 (0x00000004U)                 /*!< PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF                 (0x00000005U)                 /*!< PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG                 (0x00000006U)                 /*!< PG[12] pin */
+
+/*!<*
+  * @brief  EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD                 (0x00000030U)                 /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE                 (0x00000040U)                 /*!< PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF                 (0x00000050U)                 /*!< PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG                 (0x00000060U)                 /*!< PG[13] pin */
+
+/*!<*
+  * @brief  EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD                 (0x00000300U)                 /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE                 (0x00000400U)                 /*!< PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF                 (0x00000500U)                 /*!< PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG                 (0x00000600U)                 /*!< PG[14] pin */
+
+/*!<*
+  * @brief  EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD                 (0x00003000U)                 /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE                 (0x00004000U)                 /*!< PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF                 (0x00005000U)                 /*!< PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG                 (0x00006000U)                 /*!< PG[15] pin */
+
+/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK_Pos             (0U)                          
+#define SYSCFG_CFGR2_LOCKUP_LOCK_Msk             (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_LOCKUP_LOCK                 SYSCFG_CFGR2_LOCKUP_LOCK_Msk  /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos        (1U)                          
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk        (0x1U << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK            SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
+#define SYSCFG_CFGR2_PVD_LOCK_Pos                (2U)                          
+#define SYSCFG_CFGR2_PVD_LOCK_Msk                (0x1U << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
+#define SYSCFG_CFGR2_PVD_LOCK                    SYSCFG_CFGR2_PVD_LOCK_Msk     /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
+#define SYSCFG_CFGR2_BYP_ADDR_PAR_Pos            (4U)                          
+#define SYSCFG_CFGR2_BYP_ADDR_PAR_Msk            (0x1U << SYSCFG_CFGR2_BYP_ADDR_PAR_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR2_BYP_ADDR_PAR                SYSCFG_CFGR2_BYP_ADDR_PAR_Msk /*!< Disables the adddress parity check on RAM */
+#define SYSCFG_CFGR2_SRAM_PE_Pos                 (8U)                          
+#define SYSCFG_CFGR2_SRAM_PE_Msk                 (0x1U << SYSCFG_CFGR2_SRAM_PE_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR2_SRAM_PE                     SYSCFG_CFGR2_SRAM_PE_Msk      /*!< SRAM Parity error flag */
+/*****************  Bit definition for SYSCFG_CFGR4 register  *****************/
+#define SYSCFG_CFGR4_ADC12_EXT2_RMP_Pos          (0U)                          
+#define SYSCFG_CFGR4_ADC12_EXT2_RMP_Msk          (0x1U << SYSCFG_CFGR4_ADC12_EXT2_RMP_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR4_ADC12_EXT2_RMP              SYSCFG_CFGR4_ADC12_EXT2_RMP_Msk /*!< ADC12 regular channel EXT2 remap */
+#define SYSCFG_CFGR4_ADC12_EXT3_RMP_Pos          (1U)                          
+#define SYSCFG_CFGR4_ADC12_EXT3_RMP_Msk          (0x1U << SYSCFG_CFGR4_ADC12_EXT3_RMP_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR4_ADC12_EXT3_RMP              SYSCFG_CFGR4_ADC12_EXT3_RMP_Msk /*!< ADC12 regular channel EXT3 remap */
+#define SYSCFG_CFGR4_ADC12_EXT5_RMP_Pos          (2U)                          
+#define SYSCFG_CFGR4_ADC12_EXT5_RMP_Msk          (0x1U << SYSCFG_CFGR4_ADC12_EXT5_RMP_Pos) /*!< 0x00000004 */
+#define SYSCFG_CFGR4_ADC12_EXT5_RMP              SYSCFG_CFGR4_ADC12_EXT5_RMP_Msk /*!< ADC12 regular channel EXT5 remap */
+#define SYSCFG_CFGR4_ADC12_EXT13_RMP_Pos         (3U)                          
+#define SYSCFG_CFGR4_ADC12_EXT13_RMP_Msk         (0x1U << SYSCFG_CFGR4_ADC12_EXT13_RMP_Pos) /*!< 0x00000008 */
+#define SYSCFG_CFGR4_ADC12_EXT13_RMP             SYSCFG_CFGR4_ADC12_EXT13_RMP_Msk /*!< ADC12 regular channel EXT13 remap */
+#define SYSCFG_CFGR4_ADC12_EXT15_RMP_Pos         (4U)                          
+#define SYSCFG_CFGR4_ADC12_EXT15_RMP_Msk         (0x1U << SYSCFG_CFGR4_ADC12_EXT15_RMP_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR4_ADC12_EXT15_RMP             SYSCFG_CFGR4_ADC12_EXT15_RMP_Msk /*!< ADC12 regular channel EXT15 remap */
+#define SYSCFG_CFGR4_ADC12_JEXT3_RMP_Pos         (5U)                          
+#define SYSCFG_CFGR4_ADC12_JEXT3_RMP_Msk         (0x1U << SYSCFG_CFGR4_ADC12_JEXT3_RMP_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR4_ADC12_JEXT3_RMP             SYSCFG_CFGR4_ADC12_JEXT3_RMP_Msk /*!< ADC12 injected channel JEXT3 remap */
+#define SYSCFG_CFGR4_ADC12_JEXT6_RMP_Pos         (6U)                          
+#define SYSCFG_CFGR4_ADC12_JEXT6_RMP_Msk         (0x1U << SYSCFG_CFGR4_ADC12_JEXT6_RMP_Pos) /*!< 0x00000040 */
+#define SYSCFG_CFGR4_ADC12_JEXT6_RMP             SYSCFG_CFGR4_ADC12_JEXT6_RMP_Msk /*!< ADC12 injected channel JEXT6 remap */
+#define SYSCFG_CFGR4_ADC12_JEXT13_RMP_Pos        (7U)                          
+#define SYSCFG_CFGR4_ADC12_JEXT13_RMP_Msk        (0x1U << SYSCFG_CFGR4_ADC12_JEXT13_RMP_Pos) /*!< 0x00000080 */
+#define SYSCFG_CFGR4_ADC12_JEXT13_RMP            SYSCFG_CFGR4_ADC12_JEXT13_RMP_Msk /*!< ADC12 injected channel JEXT13 remap */
+#define SYSCFG_CFGR4_ADC34_EXT5_RMP_Pos          (8U)                          
+#define SYSCFG_CFGR4_ADC34_EXT5_RMP_Msk          (0x1U << SYSCFG_CFGR4_ADC34_EXT5_RMP_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR4_ADC34_EXT5_RMP              SYSCFG_CFGR4_ADC34_EXT5_RMP_Msk /*!< ADC34 regular channel EXT5 remap */
+#define SYSCFG_CFGR4_ADC34_EXT6_RMP_Pos          (9U)                          
+#define SYSCFG_CFGR4_ADC34_EXT6_RMP_Msk          (0x1U << SYSCFG_CFGR4_ADC34_EXT6_RMP_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR4_ADC34_EXT6_RMP              SYSCFG_CFGR4_ADC34_EXT6_RMP_Msk /*!< ADC34 regular channel EXT6 remap */
+#define SYSCFG_CFGR4_ADC34_EXT15_RMP_Pos         (10U)                         
+#define SYSCFG_CFGR4_ADC34_EXT15_RMP_Msk         (0x1U << SYSCFG_CFGR4_ADC34_EXT15_RMP_Pos) /*!< 0x00000400 */
+#define SYSCFG_CFGR4_ADC34_EXT15_RMP             SYSCFG_CFGR4_ADC34_EXT15_RMP_Msk /*!< ADC34 regular channel EXT15 remap */
+#define SYSCFG_CFGR4_ADC34_JEXT5_RMP_Pos         (11U)                         
+#define SYSCFG_CFGR4_ADC34_JEXT5_RMP_Msk         (0x1U << SYSCFG_CFGR4_ADC34_JEXT5_RMP_Pos) /*!< 0x00000800 */
+#define SYSCFG_CFGR4_ADC34_JEXT5_RMP             SYSCFG_CFGR4_ADC34_JEXT5_RMP_Msk /*!< ADC34 injected channel JEXT5 remap */
+#define SYSCFG_CFGR4_ADC34_JEXT11_RMP_Pos        (12U)                         
+#define SYSCFG_CFGR4_ADC34_JEXT11_RMP_Msk        (0x1U << SYSCFG_CFGR4_ADC34_JEXT11_RMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR4_ADC34_JEXT11_RMP            SYSCFG_CFGR4_ADC34_JEXT11_RMP_Msk /*!< ADC34 injected channel JEXT11 remap */
+#define SYSCFG_CFGR4_ADC34_JEXT14_RMP_Pos        (13U)                         
+#define SYSCFG_CFGR4_ADC34_JEXT14_RMP_Msk        (0x1U << SYSCFG_CFGR4_ADC34_JEXT14_RMP_Pos) /*!< 0x00002000 */
+#define SYSCFG_CFGR4_ADC34_JEXT14_RMP            SYSCFG_CFGR4_ADC34_JEXT14_RMP_Msk /*!< ADC34 injected channel JEXT14 remap */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)                                         
+#define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)                                         
+#define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)                                         
+#define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)                                         
+#define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)                                         
+#define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+
+#define TIM_CR1_CMS_Pos           (5U)                                         
+#define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos          (7U)                                         
+#define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos           (8U)                                         
+#define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
+
+#define TIM_CR1_UIFREMAP_Pos      (11U)                                        
+#define TIM_CR1_UIFREMAP_Msk      (0x1U << TIM_CR1_UIFREMAP_Pos)               /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)                                         
+#define TIM_CR2_CCPC_Msk          (0x1U << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos          (2U)                                         
+#define TIM_CR2_CCUS_Msk          (0x1U << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)                                         
+#define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos           (4U)                                         
+#define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos          (7U)                                         
+#define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)                                         
+#define TIM_CR2_OIS1_Msk          (0x1U << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos         (9U)                                         
+#define TIM_CR2_OIS1N_Msk         (0x1U << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)                                        
+#define TIM_CR2_OIS2_Msk          (0x1U << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos         (11U)                                        
+#define TIM_CR2_OIS2N_Msk         (0x1U << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)                                        
+#define TIM_CR2_OIS3_Msk          (0x1U << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos         (13U)                                        
+#define TIM_CR2_OIS3N_Msk         (0x1U << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)                                        
+#define TIM_CR2_OIS4_Msk          (0x1U << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5_Pos          (16U)                                        
+#define TIM_CR2_OIS5_Msk          (0x1U << TIM_CR2_OIS5_Pos)                   /*!< 0x00010000 */
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS6_Pos          (18U)                                        
+#define TIM_CR2_OIS6_Msk          (0x1U << TIM_CR2_OIS6_Pos)                   /*!< 0x00040000 */
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
+
+#define TIM_CR2_MMS2_Pos          (20U)                                        
+#define TIM_CR2_MMS2_Msk          (0xFU << TIM_CR2_MMS2_Pos)                   /*!< 0x00F00000 */
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0            (0x1U << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1            (0x2U << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2            (0x4U << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3            (0x8U << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)                                         
+#define TIM_SMCR_SMS_Msk          (0x10007U << TIM_SMCR_SMS_Pos)               /*!< 0x00010007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x00000001U)                                /*!<Bit 0 */
+#define TIM_SMCR_SMS_1            (0x00000002U)                                /*!<Bit 1 */
+#define TIM_SMCR_SMS_2            (0x00000004U)                                /*!<Bit 2 */
+#define TIM_SMCR_SMS_3            (0x00010000U)                                /*!<Bit 3 */
+
+#define TIM_SMCR_OCCS_Pos         (3U)                                         
+#define TIM_SMCR_OCCS_Msk         (0x1U << TIM_SMCR_OCCS_Pos)                  /*!< 0x00000008 */
+#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos           (4U)                                         
+#define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos          (7U)                                         
+#define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos          (8U)                                         
+#define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos         (12U)                                        
+#define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos          (14U)                                        
+#define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)                                        
+#define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)                                         
+#define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)                                         
+#define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)                                         
+#define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)                                         
+#define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)                                         
+#define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos        (5U)                                         
+#define TIM_DIER_COMIE_Msk        (0x1U << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)                                         
+#define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos          (7U)                                         
+#define TIM_DIER_BIE_Msk          (0x1U << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)                                         
+#define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)                                         
+#define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)                                        
+#define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)                                        
+#define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)                                        
+#define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)                                        
+#define TIM_DIER_COMDE_Msk        (0x1U << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)                                        
+#define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)                                         
+#define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)                                         
+#define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)                                         
+#define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)                                         
+#define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)                                         
+#define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos          (5U)                                         
+#define TIM_SR_COMIF_Msk          (0x1U << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)                                         
+#define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos            (7U)                                         
+#define TIM_SR_BIF_Msk            (0x1U << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos           (8U)                                         
+#define TIM_SR_B2IF_Msk           (0x1U << TIM_SR_B2IF_Pos)                    /*!< 0x00000100 */
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)                                         
+#define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)                                        
+#define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)                                        
+#define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)                                        
+#define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_CC5IF_Pos          (16U)                                        
+#define TIM_SR_CC5IF_Msk          (0x1U << TIM_SR_CC5IF_Pos)                   /*!< 0x00010000 */
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos          (17U)                                        
+#define TIM_SR_CC6IF_Msk          (0x1U << TIM_SR_CC6IF_Pos)                   /*!< 0x00020000 */
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)                                         
+#define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)                                         
+#define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)                                         
+#define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)                                         
+#define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)                                         
+#define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos          (5U)                                         
+#define TIM_EGR_COMG_Msk          (0x1U << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)                                         
+#define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos            (7U)                                         
+#define TIM_EGR_BG_Msk            (0x1U << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
+#define TIM_EGR_B2G_Pos           (8U)                                         
+#define TIM_EGR_B2G_Msk           (0x1U << TIM_EGR_B2G_Pos)                    /*!< 0x00000100 */
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)                                         
+#define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos       (2U)                                         
+#define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)                                         
+#define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos        (4U)                                         
+#define TIM_CCMR1_OC1M_Msk        (0x1007U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x00000010U)                                /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1          (0x00000020U)                                /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2          (0x00000040U)                                /*!<Bit 2 */
+#define TIM_CCMR1_OC1M_3          (0x00010000U)                                /*!<Bit 3 */
+
+#define TIM_CCMR1_OC1CE_Pos       (7U)                                         
+#define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos        (8U)                                         
+#define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos       (10U)                                        
+#define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)                                        
+#define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos        (12U)                                        
+#define TIM_CCMR1_OC2M_Msk        (0x1007U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x00001000U)                                /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1          (0x00002000U)                                /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2          (0x00004000U)                                /*!<Bit 2 */
+#define TIM_CCMR1_OC2M_3          (0x01000000U)                                /*!<Bit 3 */
+
+#define TIM_CCMR1_OC2CE_Pos       (15U)                                        
+#define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos      (2U)                                         
+#define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos        (4U)                                         
+#define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos      (10U)                                        
+#define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos        (12U)                                        
+#define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)                                         
+#define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos       (2U)                                         
+#define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)                                         
+#define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos        (4U)                                         
+#define TIM_CCMR2_OC3M_Msk        (0x1007U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x00000010U)                                /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1          (0x00000020U)                                /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2          (0x00000040U)                                /*!<Bit 2 */
+#define TIM_CCMR2_OC3M_3          (0x00010000U)                                /*!<Bit 3 */
+
+#define TIM_CCMR2_OC3CE_Pos       (7U)                                         
+#define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos        (8U)                                         
+#define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos       (10U)                                        
+#define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)                                        
+#define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos        (12U)                                        
+#define TIM_CCMR2_OC4M_Msk        (0x1007U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x00001000U)                                /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1          (0x00002000U)                                /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2          (0x00004000U)                                /*!<Bit 2 */
+#define TIM_CCMR2_OC4M_3          (0x01000000U)                                /*!<Bit 3 */
+
+#define TIM_CCMR2_OC4CE_Pos       (15U)                                        
+#define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos      (2U)                                         
+#define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos        (4U)                                         
+#define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos      (10U)                                        
+#define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos        (12U)                                        
+#define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)                                         
+#define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)                                         
+#define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos        (2U)                                         
+#define TIM_CCER_CC1NE_Msk        (0x1U << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos        (3U)                                         
+#define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)                                         
+#define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)                                         
+#define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos        (6U)                                         
+#define TIM_CCER_CC2NE_Msk        (0x1U << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos        (7U)                                         
+#define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)                                         
+#define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)                                         
+#define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos        (10U)                                        
+#define TIM_CCER_CC3NE_Msk        (0x1U << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos        (11U)                                        
+#define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)                                        
+#define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)                                        
+#define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos        (15U)                                        
+#define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos         (16U)                                        
+#define TIM_CCER_CC5E_Msk         (0x1U << TIM_CCER_CC5E_Pos)                  /*!< 0x00010000 */
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos         (17U)                                        
+#define TIM_CCER_CC5P_Msk         (0x1U << TIM_CCER_CC5P_Pos)                  /*!< 0x00020000 */
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos         (20U)                                        
+#define TIM_CCER_CC6E_Msk         (0x1U << TIM_CCER_CC6E_Pos)                  /*!< 0x00100000 */
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos         (21U)                                        
+#define TIM_CCER_CC6P_Msk         (0x1U << TIM_CCER_CC6P_Pos)                  /*!< 0x00200000 */
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)                                         
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFU << TIM_CNT_CNT_Pos)             /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos        (31U)                                        
+#define TIM_CNT_UIFCPY_Msk        (0x1U << TIM_CNT_UIFCPY_Pos)                 /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)                                         
+#define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)                                         
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFU << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)                                         
+#define TIM_RCR_REP_Msk           (0xFFFFU << TIM_RCR_REP_Pos)                 /*!< 0x0000FFFF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)                                         
+#define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)                                         
+#define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)                                         
+#define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)                                         
+#define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define TIM_CCR5_CCR5_Pos         (0U)                                         
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos)           /*!< 0xFFFFFFFF */
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos        (29U)                                        
+#define TIM_CCR5_GC5C1_Msk        (0x1U << TIM_CCR5_GC5C1_Pos)                 /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos        (30U)                                        
+#define TIM_CCR5_GC5C2_Msk        (0x1U << TIM_CCR5_GC5C2_Pos)                 /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos        (31U)                                        
+#define TIM_CCR5_GC5C3_Msk        (0x1U << TIM_CCR5_GC5C3_Pos)                 /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define TIM_CCR6_CCR6_Pos         (0U)                                         
+#define TIM_CCR6_CCR6_Msk         (0xFFFFU << TIM_CCR6_CCR6_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)                                         
+#define TIM_BDTR_DTG_Msk          (0xFFU << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos         (8U)                                         
+#define TIM_BDTR_LOCK_Msk         (0x3U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos         (10U)                                        
+#define TIM_BDTR_OSSI_Msk         (0x1U << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)                                        
+#define TIM_BDTR_OSSR_Msk         (0x1U << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)                                        
+#define TIM_BDTR_BKE_Msk          (0x1U << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */
+#define TIM_BDTR_BKP_Pos          (13U)                                        
+#define TIM_BDTR_BKP_Msk          (0x1U << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */
+#define TIM_BDTR_AOE_Pos          (14U)                                        
+#define TIM_BDTR_AOE_Msk          (0x1U << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)                                        
+#define TIM_BDTR_MOE_Msk          (0x1U << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos          (16U)                                        
+#define TIM_BDTR_BKF_Msk          (0xFU << TIM_BDTR_BKF_Pos)                   /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */
+#define TIM_BDTR_BK2F_Pos         (20U)                                        
+#define TIM_BDTR_BK2F_Msk         (0xFU << TIM_BDTR_BK2F_Pos)                  /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */
+
+#define TIM_BDTR_BK2E_Pos         (24U)                                        
+#define TIM_BDTR_BK2E_Msk         (0x1U << TIM_BDTR_BK2E_Pos)                  /*!< 0x01000000 */
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */
+#define TIM_BDTR_BK2P_Pos         (25U)                                        
+#define TIM_BDTR_BK2P_Msk         (0x1U << TIM_BDTR_BK2P_Pos)                  /*!< 0x02000000 */
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)                                         
+#define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos           (8U)                                         
+#define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)                                         
+#define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM16_OR register  *********************/
+#define TIM16_OR_TI1_RMP_Pos      (0U)                                         
+#define TIM16_OR_TI1_RMP_Msk      (0x3U << TIM16_OR_TI1_RMP_Pos)               /*!< 0x00000003 */
+#define TIM16_OR_TI1_RMP          TIM16_OR_TI1_RMP_Msk                         /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
+#define TIM16_OR_TI1_RMP_0        (0x1U << TIM16_OR_TI1_RMP_Pos)               /*!< 0x00000001 */
+#define TIM16_OR_TI1_RMP_1        (0x2U << TIM16_OR_TI1_RMP_Pos)               /*!< 0x00000002 */
+
+/*******************  Bit definition for TIM1_OR register  *********************/
+#define TIM1_OR_ETR_RMP_Pos      (0U)                                          
+#define TIM1_OR_ETR_RMP_Msk      (0xFU << TIM1_OR_ETR_RMP_Pos)                 /*!< 0x0000000F */
+#define TIM1_OR_ETR_RMP          TIM1_OR_ETR_RMP_Msk                           /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
+#define TIM1_OR_ETR_RMP_0        (0x1U << TIM1_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
+#define TIM1_OR_ETR_RMP_1        (0x2U << TIM1_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
+#define TIM1_OR_ETR_RMP_2        (0x4U << TIM1_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
+#define TIM1_OR_ETR_RMP_3        (0x8U << TIM1_OR_ETR_RMP_Pos)                 /*!< 0x00000008 */
+
+/*******************  Bit definition for TIM8_OR register  *********************/
+#define TIM8_OR_ETR_RMP_Pos      (0U)                                          
+#define TIM8_OR_ETR_RMP_Msk      (0xFU << TIM8_OR_ETR_RMP_Pos)                 /*!< 0x0000000F */
+#define TIM8_OR_ETR_RMP          TIM8_OR_ETR_RMP_Msk                           /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
+#define TIM8_OR_ETR_RMP_0        (0x1U << TIM8_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
+#define TIM8_OR_ETR_RMP_1        (0x2U << TIM8_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
+#define TIM8_OR_ETR_RMP_2        (0x4U << TIM8_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
+#define TIM8_OR_ETR_RMP_3        (0x8U << TIM8_OR_ETR_RMP_Pos)                 /*!< 0x00000008 */
+
+/*******************  Bit definition for TIM20_OR register  *******************/
+#define TIM20_OR_ETR_RMP_Pos      (0U)                                         
+#define TIM20_OR_ETR_RMP_Msk      (0xFU << TIM20_OR_ETR_RMP_Pos)               /*!< 0x0000000F */
+#define TIM20_OR_ETR_RMP          TIM20_OR_ETR_RMP_Msk                         /*!<ETR_RMP[3:0] bits (TIM20 ETR remap) */
+#define TIM20_OR_ETR_RMP_0        (0x1U << TIM20_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
+#define TIM20_OR_ETR_RMP_1        (0x2U << TIM20_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
+#define TIM20_OR_ETR_RMP_2        (0x4U << TIM20_OR_ETR_RMP_Pos)               /*!< 0x00000004 */
+#define TIM20_OR_ETR_RMP_3        (0x8U << TIM20_OR_ETR_RMP_Pos)               /*!< 0x00000008 */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define TIM_CCMR3_OC5FE_Pos       (2U)                                         
+#define TIM_CCMR3_OC5FE_Msk       (0x1U << TIM_CCMR3_OC5FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos       (3U)                                         
+#define TIM_CCMR3_OC5PE_Msk       (0x1U << TIM_CCMR3_OC5PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M_Pos        (4U)                                         
+#define TIM_CCMR3_OC5M_Msk        (0x1007U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0          (0x0001U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1          (0x0002U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2          (0x0004U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3          (0x1000U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR3_OC5CE_Pos       (7U)                                         
+#define TIM_CCMR3_OC5CE_Msk       (0x1U << TIM_CCMR3_OC5CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE_Pos       (10U)                                        
+#define TIM_CCMR3_OC6FE_Msk       (0x1U << TIM_CCMR3_OC6FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos       (11U)                                        
+#define TIM_CCMR3_OC6PE_Msk       (0x1U << TIM_CCMR3_OC6PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
+
+#define TIM_CCMR3_OC6M_Pos        (12U)                                        
+#define TIM_CCMR3_OC6M_Msk        (0x1007U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[2:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMR3_OC6M_0          (0x0001U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1          (0x0002U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2          (0x0004U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3          (0x1000U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR3_OC6CE_Pos       (15U)                                        
+#define TIM_CCMR3_OC6CE_Msk       (0x1U << TIM_CCMR3_OC6CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Touch Sensing Controller (TSC)                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TSC_CR register  *********************/
+#define TSC_CR_TSCE_Pos          (0U)                                          
+#define TSC_CR_TSCE_Msk          (0x1U << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
+#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
+#define TSC_CR_START_Pos         (1U)                                          
+#define TSC_CR_START_Msk         (0x1U << TSC_CR_START_Pos)                    /*!< 0x00000002 */
+#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
+#define TSC_CR_AM_Pos            (2U)                                          
+#define TSC_CR_AM_Msk            (0x1U << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
+#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL_Pos       (3U)                                          
+#define TSC_CR_SYNCPOL_Msk       (0x1U << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
+#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF_Pos         (4U)                                          
+#define TSC_CR_IODEF_Msk         (0x1U << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
+#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
+
+#define TSC_CR_MCV_Pos           (5U)                                          
+#define TSC_CR_MCV_Msk           (0x7U << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
+#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0             (0x1U << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
+#define TSC_CR_MCV_1             (0x2U << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
+#define TSC_CR_MCV_2             (0x4U << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
+
+#define TSC_CR_PGPSC_Pos         (12U)                                         
+#define TSC_CR_PGPSC_Msk         (0x7U << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
+#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0           (0x1U << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
+#define TSC_CR_PGPSC_1           (0x2U << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
+#define TSC_CR_PGPSC_2           (0x4U << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
+
+#define TSC_CR_SSPSC_Pos         (15U)                                         
+#define TSC_CR_SSPSC_Msk         (0x1U << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
+#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE_Pos           (16U)                                         
+#define TSC_CR_SSE_Msk           (0x1U << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
+#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD_Pos           (17U)                                         
+#define TSC_CR_SSD_Msk           (0x7FU << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
+#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0             (0x01U << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
+#define TSC_CR_SSD_1             (0x02U << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
+#define TSC_CR_SSD_2             (0x04U << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
+#define TSC_CR_SSD_3             (0x08U << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
+#define TSC_CR_SSD_4             (0x10U << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
+#define TSC_CR_SSD_5             (0x20U << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
+#define TSC_CR_SSD_6             (0x40U << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
+
+#define TSC_CR_CTPL_Pos          (24U)                                         
+#define TSC_CR_CTPL_Msk          (0xFU << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
+#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0            (0x1U << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
+#define TSC_CR_CTPL_1            (0x2U << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
+#define TSC_CR_CTPL_2            (0x4U << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
+#define TSC_CR_CTPL_3            (0x8U << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
+
+#define TSC_CR_CTPH_Pos          (28U)                                         
+#define TSC_CR_CTPH_Msk          (0xFU << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
+#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0            (0x1U << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
+#define TSC_CR_CTPH_1            (0x2U << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
+#define TSC_CR_CTPH_2            (0x4U << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
+#define TSC_CR_CTPH_3            (0x8U << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
+
+/*******************  Bit definition for TSC_IER register  ********************/
+#define TSC_IER_EOAIE_Pos        (0U)                                          
+#define TSC_IER_EOAIE_Msk        (0x1U << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
+#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE_Pos        (1U)                                          
+#define TSC_IER_MCEIE_Msk        (0x1U << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
+#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
+
+/*******************  Bit definition for TSC_ICR register  ********************/
+#define TSC_ICR_EOAIC_Pos        (0U)                                          
+#define TSC_ICR_EOAIC_Msk        (0x1U << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
+#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC_Pos        (1U)                                          
+#define TSC_ICR_MCEIC_Msk        (0x1U << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
+#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
+
+/*******************  Bit definition for TSC_ISR register  ********************/
+#define TSC_ISR_EOAF_Pos         (0U)                                          
+#define TSC_ISR_EOAF_Msk         (0x1U << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
+#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
+#define TSC_ISR_MCEF_Pos         (1U)                                          
+#define TSC_ISR_MCEF_Msk         (0x1U << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
+#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
+
+/*******************  Bit definition for TSC_IOHCR register  ******************/
+#define TSC_IOHCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOHCR_G1_IO1_Msk     (0x1U << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOHCR_G1_IO2_Msk     (0x1U << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOHCR_G1_IO3_Msk     (0x1U << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOHCR_G1_IO4_Msk     (0x1U << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOHCR_G2_IO1_Msk     (0x1U << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOHCR_G2_IO2_Msk     (0x1U << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOHCR_G2_IO3_Msk     (0x1U << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOHCR_G2_IO4_Msk     (0x1U << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOHCR_G3_IO1_Msk     (0x1U << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOHCR_G3_IO2_Msk     (0x1U << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOHCR_G3_IO3_Msk     (0x1U << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOHCR_G3_IO4_Msk     (0x1U << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOHCR_G4_IO1_Msk     (0x1U << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOHCR_G4_IO2_Msk     (0x1U << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOHCR_G4_IO3_Msk     (0x1U << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOHCR_G4_IO4_Msk     (0x1U << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOHCR_G5_IO1_Msk     (0x1U << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOHCR_G5_IO2_Msk     (0x1U << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOHCR_G5_IO3_Msk     (0x1U << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOHCR_G5_IO4_Msk     (0x1U << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOHCR_G6_IO1_Msk     (0x1U << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOHCR_G6_IO2_Msk     (0x1U << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOHCR_G6_IO3_Msk     (0x1U << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOHCR_G6_IO4_Msk     (0x1U << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOHCR_G7_IO1_Msk     (0x1U << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOHCR_G7_IO2_Msk     (0x1U << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOHCR_G7_IO3_Msk     (0x1U << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOHCR_G7_IO4_Msk     (0x1U << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1_Pos     (28U)                                         
+#define TSC_IOHCR_G8_IO1_Msk     (0x1U << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
+#define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2_Pos     (29U)                                         
+#define TSC_IOHCR_G8_IO2_Msk     (0x1U << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
+#define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3_Pos     (30U)                                         
+#define TSC_IOHCR_G8_IO3_Msk     (0x1U << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
+#define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4_Pos     (31U)                                         
+#define TSC_IOHCR_G8_IO4_Msk     (0x1U << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
+#define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/*******************  Bit definition for TSC_IOASCR register  *****************/
+#define TSC_IOASCR_G1_IO1_Pos    (0U)                                          
+#define TSC_IOASCR_G1_IO1_Msk    (0x1U << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
+#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2_Pos    (1U)                                          
+#define TSC_IOASCR_G1_IO2_Msk    (0x1U << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
+#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3_Pos    (2U)                                          
+#define TSC_IOASCR_G1_IO3_Msk    (0x1U << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
+#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4_Pos    (3U)                                          
+#define TSC_IOASCR_G1_IO4_Msk    (0x1U << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
+#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1_Pos    (4U)                                          
+#define TSC_IOASCR_G2_IO1_Msk    (0x1U << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
+#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2_Pos    (5U)                                          
+#define TSC_IOASCR_G2_IO2_Msk    (0x1U << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
+#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3_Pos    (6U)                                          
+#define TSC_IOASCR_G2_IO3_Msk    (0x1U << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
+#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4_Pos    (7U)                                          
+#define TSC_IOASCR_G2_IO4_Msk    (0x1U << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
+#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1_Pos    (8U)                                          
+#define TSC_IOASCR_G3_IO1_Msk    (0x1U << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
+#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2_Pos    (9U)                                          
+#define TSC_IOASCR_G3_IO2_Msk    (0x1U << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
+#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3_Pos    (10U)                                         
+#define TSC_IOASCR_G3_IO3_Msk    (0x1U << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
+#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4_Pos    (11U)                                         
+#define TSC_IOASCR_G3_IO4_Msk    (0x1U << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
+#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1_Pos    (12U)                                         
+#define TSC_IOASCR_G4_IO1_Msk    (0x1U << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
+#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2_Pos    (13U)                                         
+#define TSC_IOASCR_G4_IO2_Msk    (0x1U << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
+#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3_Pos    (14U)                                         
+#define TSC_IOASCR_G4_IO3_Msk    (0x1U << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
+#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4_Pos    (15U)                                         
+#define TSC_IOASCR_G4_IO4_Msk    (0x1U << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
+#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1_Pos    (16U)                                         
+#define TSC_IOASCR_G5_IO1_Msk    (0x1U << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
+#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2_Pos    (17U)                                         
+#define TSC_IOASCR_G5_IO2_Msk    (0x1U << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
+#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3_Pos    (18U)                                         
+#define TSC_IOASCR_G5_IO3_Msk    (0x1U << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
+#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4_Pos    (19U)                                         
+#define TSC_IOASCR_G5_IO4_Msk    (0x1U << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
+#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1_Pos    (20U)                                         
+#define TSC_IOASCR_G6_IO1_Msk    (0x1U << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
+#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2_Pos    (21U)                                         
+#define TSC_IOASCR_G6_IO2_Msk    (0x1U << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
+#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3_Pos    (22U)                                         
+#define TSC_IOASCR_G6_IO3_Msk    (0x1U << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
+#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4_Pos    (23U)                                         
+#define TSC_IOASCR_G6_IO4_Msk    (0x1U << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
+#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1_Pos    (24U)                                         
+#define TSC_IOASCR_G7_IO1_Msk    (0x1U << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
+#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2_Pos    (25U)                                         
+#define TSC_IOASCR_G7_IO2_Msk    (0x1U << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
+#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3_Pos    (26U)                                         
+#define TSC_IOASCR_G7_IO3_Msk    (0x1U << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
+#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4_Pos    (27U)                                         
+#define TSC_IOASCR_G7_IO4_Msk    (0x1U << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
+#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1_Pos    (28U)                                         
+#define TSC_IOASCR_G8_IO1_Msk    (0x1U << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
+#define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2_Pos    (29U)                                         
+#define TSC_IOASCR_G8_IO2_Msk    (0x1U << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
+#define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3_Pos    (30U)                                         
+#define TSC_IOASCR_G8_IO3_Msk    (0x1U << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
+#define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4_Pos    (31U)                                         
+#define TSC_IOASCR_G8_IO4_Msk    (0x1U << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
+#define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
+
+/*******************  Bit definition for TSC_IOSCR register  ******************/
+#define TSC_IOSCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOSCR_G1_IO1_Msk     (0x1U << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOSCR_G1_IO2_Msk     (0x1U << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOSCR_G1_IO3_Msk     (0x1U << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOSCR_G1_IO4_Msk     (0x1U << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOSCR_G2_IO1_Msk     (0x1U << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOSCR_G2_IO2_Msk     (0x1U << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOSCR_G2_IO3_Msk     (0x1U << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOSCR_G2_IO4_Msk     (0x1U << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOSCR_G3_IO1_Msk     (0x1U << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOSCR_G3_IO2_Msk     (0x1U << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOSCR_G3_IO3_Msk     (0x1U << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOSCR_G3_IO4_Msk     (0x1U << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOSCR_G4_IO1_Msk     (0x1U << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOSCR_G4_IO2_Msk     (0x1U << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOSCR_G4_IO3_Msk     (0x1U << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOSCR_G4_IO4_Msk     (0x1U << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOSCR_G5_IO1_Msk     (0x1U << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOSCR_G5_IO2_Msk     (0x1U << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOSCR_G5_IO3_Msk     (0x1U << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOSCR_G5_IO4_Msk     (0x1U << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOSCR_G6_IO1_Msk     (0x1U << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOSCR_G6_IO2_Msk     (0x1U << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOSCR_G6_IO3_Msk     (0x1U << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOSCR_G6_IO4_Msk     (0x1U << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOSCR_G7_IO1_Msk     (0x1U << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOSCR_G7_IO2_Msk     (0x1U << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOSCR_G7_IO3_Msk     (0x1U << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOSCR_G7_IO4_Msk     (0x1U << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1_Pos     (28U)                                         
+#define TSC_IOSCR_G8_IO1_Msk     (0x1U << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
+#define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2_Pos     (29U)                                         
+#define TSC_IOSCR_G8_IO2_Msk     (0x1U << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
+#define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3_Pos     (30U)                                         
+#define TSC_IOSCR_G8_IO3_Msk     (0x1U << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
+#define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4_Pos     (31U)                                         
+#define TSC_IOSCR_G8_IO4_Msk     (0x1U << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
+#define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
+
+/*******************  Bit definition for TSC_IOCCR register  ******************/
+#define TSC_IOCCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOCCR_G1_IO1_Msk     (0x1U << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOCCR_G1_IO2_Msk     (0x1U << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOCCR_G1_IO3_Msk     (0x1U << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOCCR_G1_IO4_Msk     (0x1U << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOCCR_G2_IO1_Msk     (0x1U << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOCCR_G2_IO2_Msk     (0x1U << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOCCR_G2_IO3_Msk     (0x1U << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOCCR_G2_IO4_Msk     (0x1U << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOCCR_G3_IO1_Msk     (0x1U << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOCCR_G3_IO2_Msk     (0x1U << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOCCR_G3_IO3_Msk     (0x1U << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOCCR_G3_IO4_Msk     (0x1U << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOCCR_G4_IO1_Msk     (0x1U << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOCCR_G4_IO2_Msk     (0x1U << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOCCR_G4_IO3_Msk     (0x1U << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOCCR_G4_IO4_Msk     (0x1U << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOCCR_G5_IO1_Msk     (0x1U << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOCCR_G5_IO2_Msk     (0x1U << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOCCR_G5_IO3_Msk     (0x1U << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOCCR_G5_IO4_Msk     (0x1U << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOCCR_G6_IO1_Msk     (0x1U << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOCCR_G6_IO2_Msk     (0x1U << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOCCR_G6_IO3_Msk     (0x1U << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOCCR_G6_IO4_Msk     (0x1U << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOCCR_G7_IO1_Msk     (0x1U << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOCCR_G7_IO2_Msk     (0x1U << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOCCR_G7_IO3_Msk     (0x1U << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOCCR_G7_IO4_Msk     (0x1U << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1_Pos     (28U)                                         
+#define TSC_IOCCR_G8_IO1_Msk     (0x1U << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
+#define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2_Pos     (29U)                                         
+#define TSC_IOCCR_G8_IO2_Msk     (0x1U << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
+#define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3_Pos     (30U)                                         
+#define TSC_IOCCR_G8_IO3_Msk     (0x1U << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
+#define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4_Pos     (31U)                                         
+#define TSC_IOCCR_G8_IO4_Msk     (0x1U << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
+#define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
+
+/*******************  Bit definition for TSC_IOGCSR register  *****************/
+#define TSC_IOGCSR_G1E_Pos       (0U)                                          
+#define TSC_IOGCSR_G1E_Msk       (0x1U << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
+#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E_Pos       (1U)                                          
+#define TSC_IOGCSR_G2E_Msk       (0x1U << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
+#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E_Pos       (2U)                                          
+#define TSC_IOGCSR_G3E_Msk       (0x1U << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
+#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E_Pos       (3U)                                          
+#define TSC_IOGCSR_G4E_Msk       (0x1U << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
+#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E_Pos       (4U)                                          
+#define TSC_IOGCSR_G5E_Msk       (0x1U << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
+#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E_Pos       (5U)                                          
+#define TSC_IOGCSR_G6E_Msk       (0x1U << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
+#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E_Pos       (6U)                                          
+#define TSC_IOGCSR_G7E_Msk       (0x1U << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
+#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E_Pos       (7U)                                          
+#define TSC_IOGCSR_G8E_Msk       (0x1U << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
+#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S_Pos       (16U)                                         
+#define TSC_IOGCSR_G1S_Msk       (0x1U << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
+#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S_Pos       (17U)                                         
+#define TSC_IOGCSR_G2S_Msk       (0x1U << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
+#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S_Pos       (18U)                                         
+#define TSC_IOGCSR_G3S_Msk       (0x1U << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
+#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S_Pos       (19U)                                         
+#define TSC_IOGCSR_G4S_Msk       (0x1U << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
+#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S_Pos       (20U)                                         
+#define TSC_IOGCSR_G5S_Msk       (0x1U << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
+#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S_Pos       (21U)                                         
+#define TSC_IOGCSR_G6S_Msk       (0x1U << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
+#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S_Pos       (22U)                                         
+#define TSC_IOGCSR_G7S_Msk       (0x1U << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
+#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S_Pos       (23U)                                         
+#define TSC_IOGCSR_G8S_Msk       (0x1U << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
+#define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
+
+/*******************  Bit definition for TSC_IOGXCR register  *****************/
+#define TSC_IOGXCR_CNT_Pos       (0U)                                          
+#define TSC_IOGXCR_CNT_Msk       (0x3FFFU << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
+#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+*/
+
+/* Support of 7 bits data length feature */
+#define USART_7BITS_SUPPORT
+
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos              (0U)                                     
+#define USART_CR1_UE_Msk              (0x1U << USART_CR1_UE_Pos)               /*!< 0x00000001 */
+#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
+#define USART_CR1_UESM_Pos            (1U)                                     
+#define USART_CR1_UESM_Msk            (0x1U << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
+#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos              (2U)                                     
+#define USART_CR1_RE_Msk              (0x1U << USART_CR1_RE_Pos)               /*!< 0x00000004 */
+#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
+#define USART_CR1_TE_Pos              (3U)                                     
+#define USART_CR1_TE_Msk              (0x1U << USART_CR1_TE_Pos)               /*!< 0x00000008 */
+#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos          (4U)                                     
+#define USART_CR1_IDLEIE_Msk          (0x1U << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
+#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos          (5U)                                     
+#define USART_CR1_RXNEIE_Msk          (0x1U << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
+#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos            (6U)                                     
+#define USART_CR1_TCIE_Msk            (0x1U << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
+#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos           (7U)                                     
+#define USART_CR1_TXEIE_Msk           (0x1U << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
+#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos            (8U)                                     
+#define USART_CR1_PEIE_Msk            (0x1U << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
+#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos              (9U)                                     
+#define USART_CR1_PS_Msk              (0x1U << USART_CR1_PS_Pos)               /*!< 0x00000200 */
+#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
+#define USART_CR1_PCE_Pos             (10U)                                    
+#define USART_CR1_PCE_Msk             (0x1U << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
+#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos            (11U)                                    
+#define USART_CR1_WAKE_Msk            (0x1U << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
+#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
+#define USART_CR1_M0_Pos              (12U)                                    
+#define USART_CR1_M0_Msk              (0x1U << USART_CR1_M0_Pos)               /*!< 0x00001000 */
+#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length bit 0 */
+#define USART_CR1_MME_Pos             (13U)                                    
+#define USART_CR1_MME_Msk             (0x1U << USART_CR1_MME_Pos)              /*!< 0x00002000 */
+#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos            (14U)                                    
+#define USART_CR1_CMIE_Msk            (0x1U << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
+#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos           (15U)                                    
+#define USART_CR1_OVER8_Msk           (0x1U << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
+#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos            (16U)                                    
+#define USART_CR1_DEDT_Msk            (0x1FU << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
+#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0              (0x01U << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
+#define USART_CR1_DEDT_1              (0x02U << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
+#define USART_CR1_DEDT_2              (0x04U << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
+#define USART_CR1_DEDT_3              (0x08U << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
+#define USART_CR1_DEDT_4              (0x10U << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos            (21U)                                    
+#define USART_CR1_DEAT_Msk            (0x1FU << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
+#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0              (0x01U << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
+#define USART_CR1_DEAT_1              (0x02U << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
+#define USART_CR1_DEAT_2              (0x04U << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
+#define USART_CR1_DEAT_3              (0x08U << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
+#define USART_CR1_DEAT_4              (0x10U << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos           (26U)                                    
+#define USART_CR1_RTOIE_Msk           (0x1U << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
+#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos           (27U)                                    
+#define USART_CR1_EOBIE_Msk           (0x1U << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
+#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos              (28U)                                    
+#define USART_CR1_M1_Msk              (0x1U << USART_CR1_M1_Pos)               /*!< 0x10000000 */
+#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length bit 1 */
+#define USART_CR1_M_Pos               (12U)                                    
+#define USART_CR1_M_Msk               (0x10001U << USART_CR1_M_Pos)            /*!< 0x10001000 */
+#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< [M1:M0] Word length */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_ADDM7_Pos           (4U)                                     
+#define USART_CR2_ADDM7_Msk           (0x1U << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
+#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos            (5U)                                     
+#define USART_CR2_LBDL_Msk            (0x1U << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
+#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos           (6U)                                     
+#define USART_CR2_LBDIE_Msk           (0x1U << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
+#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos            (8U)                                     
+#define USART_CR2_LBCL_Msk            (0x1U << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
+#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos            (9U)                                     
+#define USART_CR2_CPHA_Msk            (0x1U << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
+#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos            (10U)                                    
+#define USART_CR2_CPOL_Msk            (0x1U << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
+#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos           (11U)                                    
+#define USART_CR2_CLKEN_Msk           (0x1U << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
+#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
+#define USART_CR2_STOP_Pos            (12U)                                    
+#define USART_CR2_STOP_Msk            (0x3U << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
+#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0              (0x1U << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
+#define USART_CR2_STOP_1              (0x2U << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos           (14U)                                    
+#define USART_CR2_LINEN_Msk           (0x1U << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
+#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos            (15U)                                    
+#define USART_CR2_SWAP_Msk            (0x1U << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
+#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos           (16U)                                    
+#define USART_CR2_RXINV_Msk           (0x1U << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
+#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos           (17U)                                    
+#define USART_CR2_TXINV_Msk           (0x1U << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
+#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos         (18U)                                    
+#define USART_CR2_DATAINV_Msk         (0x1U << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
+#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos        (19U)                                    
+#define USART_CR2_MSBFIRST_Msk        (0x1U << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos           (20U)                                    
+#define USART_CR2_ABREN_Msk           (0x1U << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
+#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos         (21U)                                    
+#define USART_CR2_ABRMODE_Msk         (0x3U << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
+#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0           (0x1U << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1           (0x2U << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos           (23U)                                    
+#define USART_CR2_RTOEN_Msk           (0x1U << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
+#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos             (24U)                                    
+#define USART_CR2_ADD_Msk             (0xFFU << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
+#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos             (0U)                                     
+#define USART_CR3_EIE_Msk             (0x1U << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
+#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos            (1U)                                     
+#define USART_CR3_IREN_Msk            (0x1U << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
+#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos            (2U)                                     
+#define USART_CR3_IRLP_Msk            (0x1U << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
+#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos           (3U)                                     
+#define USART_CR3_HDSEL_Msk           (0x1U << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
+#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos            (4U)                                     
+#define USART_CR3_NACK_Msk            (0x1U << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
+#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos            (5U)                                     
+#define USART_CR3_SCEN_Msk            (0x1U << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
+#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos            (6U)                                     
+#define USART_CR3_DMAR_Msk            (0x1U << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
+#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos            (7U)                                     
+#define USART_CR3_DMAT_Msk            (0x1U << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
+#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos            (8U)                                     
+#define USART_CR3_RTSE_Msk            (0x1U << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
+#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos            (9U)                                     
+#define USART_CR3_CTSE_Msk            (0x1U << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
+#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos           (10U)                                    
+#define USART_CR3_CTSIE_Msk           (0x1U << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
+#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos          (11U)                                    
+#define USART_CR3_ONEBIT_Msk          (0x1U << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
+#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos          (12U)                                    
+#define USART_CR3_OVRDIS_Msk          (0x1U << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
+#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos            (13U)                                    
+#define USART_CR3_DDRE_Msk            (0x1U << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
+#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos             (14U)                                    
+#define USART_CR3_DEM_Msk             (0x1U << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
+#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos             (15U)                                    
+#define USART_CR3_DEP_Msk             (0x1U << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
+#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos         (17U)                                    
+#define USART_CR3_SCARCNT_Msk         (0x7U << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0           (0x1U << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1           (0x2U << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2           (0x4U << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos             (20U)                                    
+#define USART_CR3_WUS_Msk             (0x3U << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
+#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0               (0x1U << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
+#define USART_CR3_WUS_1               (0x2U << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos           (22U)                                    
+#define USART_CR3_WUFIE_Msk           (0x1U << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
+#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_FRACTION_Pos    (0U)                                     
+#define USART_BRR_DIV_FRACTION_Msk    (0xFU << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos    (4U)                                     
+#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFU << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos            (0U)                                     
+#define USART_GTPR_PSC_Msk            (0xFFU << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
+#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos             (8U)                                     
+#define USART_GTPR_GT_Msk             (0xFFU << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
+#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
+
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos            (0U)                                     
+#define USART_RTOR_RTO_Msk            (0xFFFFFFU << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos           (24U)                                    
+#define USART_RTOR_BLEN_Msk           (0xFFU << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
+#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos           (0U)                                     
+#define USART_RQR_ABRRQ_Msk           (0x1U << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
+#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos           (1U)                                     
+#define USART_RQR_SBKRQ_Msk           (0x1U << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
+#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos            (2U)                                     
+#define USART_RQR_MMRQ_Msk            (0x1U << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
+#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos           (3U)                                     
+#define USART_RQR_RXFRQ_Msk           (0x1U << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
+#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos           (4U)                                     
+#define USART_RQR_TXFRQ_Msk           (0x1U << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
+#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos              (0U)                                     
+#define USART_ISR_PE_Msk              (0x1U << USART_ISR_PE_Pos)               /*!< 0x00000001 */
+#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
+#define USART_ISR_FE_Pos              (1U)                                     
+#define USART_ISR_FE_Msk              (0x1U << USART_ISR_FE_Pos)               /*!< 0x00000002 */
+#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
+#define USART_ISR_NE_Pos              (2U)                                     
+#define USART_ISR_NE_Msk              (0x1U << USART_ISR_NE_Pos)               /*!< 0x00000004 */
+#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos             (3U)                                     
+#define USART_ISR_ORE_Msk             (0x1U << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
+#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos            (4U)                                     
+#define USART_ISR_IDLE_Msk            (0x1U << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
+#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos            (5U)                                     
+#define USART_ISR_RXNE_Msk            (0x1U << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
+#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos              (6U)                                     
+#define USART_ISR_TC_Msk              (0x1U << USART_ISR_TC_Pos)               /*!< 0x00000040 */
+#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos             (7U)                                     
+#define USART_ISR_TXE_Msk             (0x1U << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
+#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos            (8U)                                     
+#define USART_ISR_LBDF_Msk            (0x1U << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
+#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos           (9U)                                     
+#define USART_ISR_CTSIF_Msk           (0x1U << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
+#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos             (10U)                                    
+#define USART_ISR_CTS_Msk             (0x1U << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
+#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
+#define USART_ISR_RTOF_Pos            (11U)                                    
+#define USART_ISR_RTOF_Msk            (0x1U << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
+#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos            (12U)                                    
+#define USART_ISR_EOBF_Msk            (0x1U << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
+#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos            (14U)                                    
+#define USART_ISR_ABRE_Msk            (0x1U << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
+#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos            (15U)                                    
+#define USART_ISR_ABRF_Msk            (0x1U << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
+#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos            (16U)                                    
+#define USART_ISR_BUSY_Msk            (0x1U << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
+#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
+#define USART_ISR_CMF_Pos             (17U)                                    
+#define USART_ISR_CMF_Msk             (0x1U << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
+#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos            (18U)                                    
+#define USART_ISR_SBKF_Msk            (0x1U << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
+#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos             (19U)                                    
+#define USART_ISR_RWU_Msk             (0x1U << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
+#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos             (20U)                                    
+#define USART_ISR_WUF_Msk             (0x1U << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
+#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos           (21U)                                    
+#define USART_ISR_TEACK_Msk           (0x1U << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
+#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos           (22U)                                    
+#define USART_ISR_REACK_Msk           (0x1U << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
+#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos            (0U)                                     
+#define USART_ICR_PECF_Msk            (0x1U << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
+#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos            (1U)                                     
+#define USART_ICR_FECF_Msk            (0x1U << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
+#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos             (2U)                                     
+#define USART_ICR_NCF_Msk             (0x1U << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
+#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos           (3U)                                     
+#define USART_ICR_ORECF_Msk           (0x1U << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
+#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos          (4U)                                     
+#define USART_ICR_IDLECF_Msk          (0x1U << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
+#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos            (6U)                                     
+#define USART_ICR_TCCF_Msk            (0x1U << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
+#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos           (8U)                                     
+#define USART_ICR_LBDCF_Msk           (0x1U << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
+#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos           (9U)                                     
+#define USART_ICR_CTSCF_Msk           (0x1U << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
+#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos           (11U)                                    
+#define USART_ICR_RTOCF_Msk           (0x1U << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
+#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos           (12U)                                    
+#define USART_ICR_EOBCF_Msk           (0x1U << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
+#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos            (17U)                                    
+#define USART_ICR_CMCF_Msk            (0x1U << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
+#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos            (20U)                                    
+#define USART_ICR_WUCF_Msk            (0x1U << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
+#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR_Pos             (0U)                                     
+#define USART_RDR_RDR_Msk             (0x1FFU << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
+#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR_Pos             (0U)                                     
+#define USART_TDR_TDR_Msk             (0x1FFU << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
+#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         USB Device General registers                       */
+/*                                                                            */
+/******************************************************************************/
+#define USB_CNTR                             (USB_BASE + 0x40U)             /*!< Control register */
+#define USB_ISTR                             (USB_BASE + 0x44U)             /*!< Interrupt status register */
+#define USB_FNR                              (USB_BASE + 0x48U)             /*!< Frame number register */
+#define USB_DADDR                            (USB_BASE + 0x4CU)             /*!< Device address register */
+#define USB_BTABLE                           (USB_BASE + 0x50U)             /*!< Buffer Table address register */
+#define USB_LPMCSR                           (USB_BASE + 0x54U)             /*!< LPM Control and Status register */
+
+/****************************  ISTR interrupt events  *************************/
+#define USB_ISTR_CTR                         ((uint16_t)0x8000U)               /*!< Correct TRansfer (clear-only bit) */
+#define USB_ISTR_PMAOVR                      ((uint16_t)0x4000U)               /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_ERR                         ((uint16_t)0x2000U)               /*!< ERRor (clear-only bit) */
+#define USB_ISTR_WKUP                        ((uint16_t)0x1000U)               /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_SUSP                        ((uint16_t)0x0800U)               /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_RESET                       ((uint16_t)0x0400U)               /*!< RESET (clear-only bit) */
+#define USB_ISTR_SOF                         ((uint16_t)0x0200U)               /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_ESOF                        ((uint16_t)0x0100U)               /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_L1REQ                       ((uint16_t)0x0080U)               /*!< LPM L1 state request  */
+#define USB_ISTR_DIR                         ((uint16_t)0x0010U)               /*!< DIRection of transaction (read-only bit)  */
+#define USB_ISTR_EP_ID                       ((uint16_t)0x000FU)               /*!< EndPoint IDentifier (read-only bit)  */
+
+/* Legacy defines */
+#define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR
+
+#define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
+#define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
+#define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
+#define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
+#define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
+#define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
+#define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
+#define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
+
+/* Legacy defines */
+#define USB_CLR_PMAOVRM USB_CLR_PMAOVR
+
+/*************************  CNTR control register bits definitions  ***********/
+#define USB_CNTR_CTRM                        ((uint16_t)0x8000U)               /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVR                      ((uint16_t)0x4000U)               /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM                        ((uint16_t)0x2000U)               /*!< ERRor Mask */
+#define USB_CNTR_WKUPM                       ((uint16_t)0x1000U)               /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM                       ((uint16_t)0x0800U)               /*!< SUSPend Mask */
+#define USB_CNTR_RESETM                      ((uint16_t)0x0400U)               /*!< RESET Mask   */
+#define USB_CNTR_SOFM                        ((uint16_t)0x0200U)               /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM                       ((uint16_t)0x0100U)               /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_L1REQM                      ((uint16_t)0x0080U)               /*!< LPM L1 state request interrupt mask */
+#define USB_CNTR_L1RESUME                    ((uint16_t)0x0020U)               /*!< LPM L1 Resume request */
+#define USB_CNTR_RESUME                      ((uint16_t)0x0010U)               /*!< RESUME request */
+#define USB_CNTR_FSUSP                       ((uint16_t)0x0008U)               /*!< Force SUSPend */
+#define USB_CNTR_LPMODE                      ((uint16_t)0x0004U)               /*!< Low-power MODE */
+#define USB_CNTR_PDWN                        ((uint16_t)0x0002U)               /*!< Power DoWN */
+#define USB_CNTR_FRES                        ((uint16_t)0x0001U)               /*!< Force USB RESet */
+
+/* Legacy defines */
+#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR
+#define USB_CNTR_LP_MODE USB_CNTR_LPMODE
+
+/***************************  LPM register bits definitions  ******************/
+#define USB_LPMCSR_BESL                      ((uint16_t)0x00F0U)               /*!< BESL value received with last ACKed LPM Token  */ 
+#define USB_LPMCSR_REMWAKE                   ((uint16_t)0x0008U)               /*!< bRemoteWake value received with last ACKed LPM Token */ 
+#define USB_LPMCSR_LPMACK                    ((uint16_t)0x0002U)               /*!< LPM Token acknowledge enable*/
+#define USB_LPMCSR_LMPEN                     ((uint16_t)0x0001U)               /*!< LPM support enable  */
+
+/********************  FNR Frame Number Register bit definitions   ************/
+#define USB_FNR_RXDP                         ((uint16_t)0x8000U)               /*!< status of D+ data line */
+#define USB_FNR_RXDM                         ((uint16_t)0x4000U)               /*!< status of D- data line */
+#define USB_FNR_LCK                          ((uint16_t)0x2000U)               /*!< LoCKed */
+#define USB_FNR_LSOF                         ((uint16_t)0x1800U)               /*!< Lost SOF */
+#define USB_FNR_FN                           ((uint16_t)0x07FFU)               /*!< Frame Number */
+
+/********************  DADDR Device ADDRess bit definitions    ****************/
+#define USB_DADDR_EF                         ((uint8_t)0x80U)                  /*!< USB device address Enable Function */
+#define USB_DADDR_ADD                        ((uint8_t)0x7FU)                  /*!< USB device address */
+
+/******************************  Endpoint register    *************************/
+#define USB_EP0R                             USB_BASE                    /*!< endpoint 0 register address */
+#define USB_EP1R                             (USB_BASE + 0x04U)           /*!< endpoint 1 register address */
+#define USB_EP2R                             (USB_BASE + 0x08U)           /*!< endpoint 2 register address */
+#define USB_EP3R                             (USB_BASE + 0x0CU)           /*!< endpoint 3 register address */
+#define USB_EP4R                             (USB_BASE + 0x10U)           /*!< endpoint 4 register address */
+#define USB_EP5R                             (USB_BASE + 0x14U)           /*!< endpoint 5 register address */
+#define USB_EP6R                             (USB_BASE + 0x18U)           /*!< endpoint 6 register address */
+#define USB_EP7R                             (USB_BASE + 0x1CU)           /*!< endpoint 7 register address */
+/* bit positions */ 
+#define USB_EP_CTR_RX                        ((uint16_t)0x8000U)               /*!<  EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX                       ((uint16_t)0x4000U)               /*!<  EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT                        ((uint16_t)0x3000U)               /*!<  EndPoint RX STATus bit field */
+#define USB_EP_SETUP                         ((uint16_t)0x0800U)               /*!<  EndPoint SETUP */
+#define USB_EP_T_FIELD                       ((uint16_t)0x0600U)               /*!<  EndPoint TYPE */
+#define USB_EP_KIND                          ((uint16_t)0x0100U)               /*!<  EndPoint KIND */
+#define USB_EP_CTR_TX                        ((uint16_t)0x0080U)               /*!<  EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX                       ((uint16_t)0x0040U)               /*!<  EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT                        ((uint16_t)0x0030U)               /*!<  EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD                     ((uint16_t)0x000FU)               /*!<  EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK                     ((uint16_t)0x0600U)               /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK                          ((uint16_t)0x0000U)               /*!< EndPoint BULK */
+#define USB_EP_CONTROL                       ((uint16_t)0x0200U)               /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS                   ((uint16_t)0x0400U)               /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT                     ((uint16_t)0x0600U)               /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
+                                                                 
+#define USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
+                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS                        ((uint16_t)0x0000U)               /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL                      ((uint16_t)0x0010U)               /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK                        ((uint16_t)0x0020U)               /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID                      ((uint16_t)0x0030U)               /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1                       ((uint16_t)0x0010U)               /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2                       ((uint16_t)0x0020U)               /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
+                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS                        ((uint16_t)0x0000U)               /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL                      ((uint16_t)0x1000U)               /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK                        ((uint16_t)0x2000U)               /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID                      ((uint16_t)0x3000U)               /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1                       ((uint16_t)0x1000U)               /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2                       ((uint16_t)0x2000U)               /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos           (0U)                                           
+#define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
+#define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
+#define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
+#define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
+#define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
+#define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
+#define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
+
+/* Legacy defines */
+#define  WWDG_CR_T0 WWDG_CR_T_0
+#define  WWDG_CR_T1 WWDG_CR_T_1
+#define  WWDG_CR_T2 WWDG_CR_T_2
+#define  WWDG_CR_T3 WWDG_CR_T_3
+#define  WWDG_CR_T4 WWDG_CR_T_4
+#define  WWDG_CR_T5 WWDG_CR_T_5
+#define  WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos        (7U)                                           
+#define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos          (0U)                                           
+#define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
+#define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
+#define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
+#define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
+#define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
+#define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
+#define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
+
+/* Legacy defines */
+#define  WWDG_CFR_W0 WWDG_CFR_W_0
+#define  WWDG_CFR_W1 WWDG_CFR_W_1
+#define  WWDG_CFR_W2 WWDG_CFR_W_2
+#define  WWDG_CFR_W3 WWDG_CFR_W_3
+#define  WWDG_CFR_W4 WWDG_CFR_W_4
+#define  WWDG_CFR_W5 WWDG_CFR_W_5
+#define  WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos      (7U)                                           
+#define WWDG_CFR_WDGTB_Msk      (0x3U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
+
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos        (9U)                                           
+#define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos        (0U)                                           
+#define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
+
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+                                       ((INSTANCE) == ADC2) || \
+                                       ((INSTANCE) == ADC3) || \
+                                       ((INSTANCE) == ADC4))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+                                                    ((INSTANCE) == ADC3))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) || \
+                                          ((INSTANCE) == ADC34_COMMON))
+
+/****************************** CAN Instances *********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
+
+/****************************** COMP Instances ********************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+                                        ((INSTANCE) == COMP2) || \
+                                        ((INSTANCE) == COMP3) || \
+                                        ((INSTANCE) == COMP4) || \
+                                        ((INSTANCE) == COMP5) || \
+                                        ((INSTANCE) == COMP6) || \
+                                        ((INSTANCE) == COMP7))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) (((COMMON_INSTANCE) == COMP12_COMMON) || \
+                                                  ((COMMON_INSTANCE) == COMP34_COMMON) || \
+                                                  ((COMMON_INSTANCE) == COMP56_COMMON))
+
+
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
+                                               ((INSTANCE) == COMP4) || \
+                                               ((INSTANCE) == COMP6))
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+#define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == DAC1) &&                   \
+     (((CHANNEL) == DAC_CHANNEL_1) ||          \
+      ((CHANNEL) == DAC_CHANNEL_2))))
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+                                       ((INSTANCE) == DMA1_Channel2) || \
+                                       ((INSTANCE) == DMA1_Channel3) || \
+                                       ((INSTANCE) == DMA1_Channel4) || \
+                                       ((INSTANCE) == DMA1_Channel5) || \
+                                       ((INSTANCE) == DMA1_Channel6) || \
+                                       ((INSTANCE) == DMA1_Channel7) || \
+                                       ((INSTANCE) == DMA2_Channel1) || \
+                                       ((INSTANCE) == DMA2_Channel2) || \
+                                       ((INSTANCE) == DMA2_Channel3) || \
+                                       ((INSTANCE) == DMA2_Channel4) || \
+                                       ((INSTANCE) == DMA2_Channel5))
+
+/****************************** GPIO Instances ********************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
+                                         ((INSTANCE) == GPIOB) || \
+                                         ((INSTANCE) == GPIOC) || \
+                                         ((INSTANCE) == GPIOD) || \
+                                         ((INSTANCE) == GPIOE) || \
+                                         ((INSTANCE) == GPIOF) || \
+                                         ((INSTANCE) == GPIOG) || \
+                                         ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   (((INSTANCE) == GPIOA) || \
+                                         ((INSTANCE) == GPIOB) || \
+                                         ((INSTANCE) == GPIOC) || \
+                                         ((INSTANCE) == GPIOD) || \
+                                         ((INSTANCE) == GPIOE) || \
+                                         ((INSTANCE) == GPIOF) || \
+                                         ((INSTANCE) == GPIOG) || \
+                                         ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                         ((INSTANCE) == GPIOB) || \
+                                         ((INSTANCE) == GPIOC) || \
+                                         ((INSTANCE) == GPIOD) || \
+                                         ((INSTANCE) == GPIOE) || \
+                                         ((INSTANCE) == GPIOF) || \
+                                         ((INSTANCE) == GPIOG) || \
+                                         ((INSTANCE) == GPIOH))
+
+/****************************** I2C Instances *********************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2) || \
+                                       ((INSTANCE) == I2C3))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/****************************** I2S Instances *********************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3))
+#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext) || \
+                                           ((INSTANCE) == I2S3ext))
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
+                                         ((INSTANCE) == OPAMP2) || \
+                                         ((INSTANCE) == OPAMP3) || \
+                                         ((INSTANCE) == OPAMP4))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                         ((INSTANCE) == I2C2) || \
+                                         ((INSTANCE) == I2C3))
+
+/****************************** SPI Instances *********************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3) || \
+                                       ((INSTANCE) == SPI4))
+
+/******************* TIM Instances : All supported instances ******************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM6)    || \
+   ((INSTANCE) == TIM7)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17)   || \
+   ((INSTANCE) == TIM20))
+
+/******************* TIM Instances : at least 1 capture/compare channel *******/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17)   || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 2 capture/compare channels *******/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 3 capture/compare channels *******/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 4 capture/compare channels *******/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM20))
+    
+/************************** TIM Instances : Advanced-control timers ***********/
+
+/****************** TIM Instances : supporting clock selection ****************/
+#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting external clock mode 2 **********/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting Hall interface *****************/
+#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM20))
+   
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM20))      
+   
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM8)  || \
+                                            ((INSTANCE) == TIM20))       
+
+/****************** TIM Instances : supporting input XOR function *************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting master mode ********************/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM6)    || \
+   ((INSTANCE) == TIM7)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting slave mode *********************/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
+    (((INSTANCE) == TIM1)    || \
+     ((INSTANCE) == TIM2)    || \
+     ((INSTANCE) == TIM3)    || \
+     ((INSTANCE) == TIM4)    || \
+     ((INSTANCE) == TIM6)    || \
+     ((INSTANCE) == TIM7)    || \
+     ((INSTANCE) == TIM8)    || \
+     ((INSTANCE) == TIM15)   || \
+     ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
+    ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : supporting DMA burst **********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+    (((INSTANCE) == TIM1)    || \
+     ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+     ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17)   || \
+     ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+      (((INSTANCE) == TIM1)    || \
+       ((INSTANCE) == TIM8)    || \
+       ((INSTANCE) == TIM15)   || \
+       ((INSTANCE) == TIM16)   || \
+       ((INSTANCE) == TIM17)   || \
+       ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting input/output channel(s) ********/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+    ||                                         \
+    (((INSTANCE) == TIM2) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM3) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM4) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM8) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+    ||                                         \
+    (((INSTANCE) == TIM15) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+    ||                                         \
+    (((INSTANCE) == TIM16) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((INSTANCE) == TIM17) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((INSTANCE) == TIM20) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM8) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM15) &&                   \
+      ((CHANNEL) == TIM_CHANNEL_1))             \
+    ||                                          \
+    (((INSTANCE) == TIM16) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM17) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM20) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17)   || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17)   || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting DMA generation on Update events*/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM6)    || \
+   ((INSTANCE) == TIM7)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17)   || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting DMA generation on Capture/Compare events */
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17)   || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17)   || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting remapping capability ***********/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM20))
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART3))
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                            ((INSTANCE) == USART2) || \
+                                                            ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                      ((INSTANCE) == USART2) || \
+                                      ((INSTANCE) == USART3) || \
+                                      ((INSTANCE) == UART4)  || \
+                                      ((INSTANCE) == UART5))
+                                      
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                 ((INSTANCE) == USART2) || \
+                                                 ((INSTANCE) == USART3) || \
+                                                 ((INSTANCE) == UART4)  || \
+                                                 ((INSTANCE) == UART5))                                       
+                                      
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                          ((INSTANCE) == USART2) || \
+                                          ((INSTANCE) == USART3) || \
+                                          ((INSTANCE) == UART4)  || \
+                                          ((INSTANCE) == UART5))
+                                          
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                      ((INSTANCE) == USART2) || \
+                                                      ((INSTANCE) == USART3) || \
+                                                      ((INSTANCE) == UART4)  || \
+                                                      ((INSTANCE) == UART5))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART3))
+
+/****************** UART Instances : Auto Baud Rate detection *****************/
+#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                           ((INSTANCE) == USART2) || \
+                                                           ((INSTANCE) == USART3))
+
+/****************** UART Instances : Driver Enable ****************************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                  ((INSTANCE) == USART2) || \
+                                                  ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5))
+
+/******************** UART Instances : Support of continuous communication using DMA ****/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
+
+/****************************** USB Instances *********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
+
+/**
+  * @}
+  */
+
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32F3xx device product       */
+/*  lines, the aliases defined below are put in place to overcome the         */
+/*  differences in the interrupt handlers and IRQn definitions.               */
+/*  No need to update developed interrupt code when moving across             */ 
+/*  product lines within the same STM32F3 Family                              */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_IRQn        ADC1_2_IRQn
+#define SDADC1_IRQn      ADC4_IRQn
+#define COMP1_2_IRQn     COMP1_2_3_IRQn
+#define COMP2_IRQn       COMP1_2_3_IRQn
+#define COMP_IRQn        COMP1_2_3_IRQn
+#define COMP4_6_IRQn     COMP4_5_6_IRQn
+#define HRTIM1_FLT_IRQn  I2C3_ER_IRQn
+#define HRTIM1_TIME_IRQn I2C3_EV_IRQn
+#define TIM15_IRQn       TIM1_BRK_TIM15_IRQn
+#define TIM18_DAC2_IRQn  TIM1_CC_IRQn
+#define TIM17_IRQn       TIM1_TRG_COM_TIM17_IRQn
+#define TIM16_IRQn       TIM1_UP_TIM16_IRQn
+#define TIM19_IRQn       TIM20_UP_IRQn
+#define TIM6_DAC1_IRQn   TIM6_DAC_IRQn
+#define TIM7_DAC2_IRQn   TIM7_IRQn
+#define TIM12_IRQn       TIM8_BRK_IRQn
+#define TIM14_IRQn       TIM8_TRG_COM_IRQn
+#define TIM13_IRQn       TIM8_UP_IRQn
+#define CEC_IRQn         USBWakeUp_IRQn
+#define USBWakeUp_IRQn   USBWakeUp_RMP_IRQn
+#define CAN_TX_IRQn      USB_HP_CAN_TX_IRQn
+#define CAN_RX0_IRQn     USB_LP_CAN_RX0_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler        ADC1_2_IRQHandler
+#define SDADC1_IRQHandler      ADC4_IRQHandler
+#define COMP1_2_IRQHandler     COMP1_2_3_IRQHandler
+#define COMP2_IRQHandler       COMP1_2_3_IRQHandler
+#define COMP_IRQHandler        COMP1_2_3_IRQHandler
+#define COMP4_6_IRQHandler     COMP4_5_6_IRQHandler
+#define HRTIM1_FLT_IRQHandler  I2C3_ER_IRQHandler
+#define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler
+#define TIM15_IRQHandler       TIM1_BRK_TIM15_IRQHandler
+#define TIM18_DAC2_IRQHandler  TIM1_CC_IRQHandler
+#define TIM17_IRQHandler       TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM16_IRQHandler       TIM1_UP_TIM16_IRQHandler
+#define TIM19_IRQHandler       TIM20_UP_IRQHandler
+#define TIM6_DAC1_IRQHandler   TIM6_DAC_IRQHandler
+#define TIM7_DAC2_IRQHandler   TIM7_IRQHandler
+#define TIM12_IRQHandler       TIM8_BRK_IRQHandler
+#define TIM14_IRQHandler       TIM8_TRG_COM_IRQHandler
+#define TIM13_IRQHandler       TIM8_UP_IRQHandler
+#define CEC_IRQHandler         USBWakeUp_IRQHandler
+#define USBWakeUp_IRQHandler   USBWakeUp_RMP_IRQHandler
+#define CAN_TX_IRQHandler      USB_HP_CAN_TX_IRQHandler
+#define CAN_RX0_IRQHandler     USB_LP_CAN_RX0_IRQHandler
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F303xE_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/stm32f3xx.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,252 @@
+/**
+  ******************************************************************************
+  * @file    stm32f3xx.h
+  * @author  MCD Application Team
+  * @version V2.3.0
+  * @date    29-April-2015
+  * @brief   CMSIS STM32F3xx Device Peripheral Access Layer Header File.           
+  *            
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32F3xx device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral’s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_HAL_DRIVER"
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f3xx
+  * @{
+  */
+    
+#ifndef __STM32F3xx_H
+#define __STM32F3xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+   
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32F3)
+#define STM32F3
+#endif /* STM32F3 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+
+#if !defined (STM32F301x8) && !defined (STM32F302x8) && !defined (STM32F318xx) && \
+    !defined (STM32F302xC) && !defined (STM32F303xC) && !defined (STM32F358xx) && \
+    !defined (STM32F303x8) && !defined (STM32F334x8) && !defined (STM32F328xx) && \
+    !defined (STM32F302xE) && !defined (STM32F303xE) && !defined (STM32F398xx) && \
+    !defined (STM32F373xC) && !defined (STM32F378xx)
+    
+  /* #define STM32F301x8 */   /*!< STM32F301K6, STM32F301K8, STM32F301C6, STM32F301C8,
+                                   STM32F301R6 and STM32F301R8 Devices */
+  /* #define STM32F302x8 */   /*!< STM32F302K6, STM32F302K8, STM32F302C6, STM32F302C8,
+                                   STM32F302R6 and STM32F302R8 Devices */
+  /* #define STM32F302xC */   /*!< STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC,
+                                   STM32F302VB and STM32F302VC Devices */
+  /* #define STM32F302xE */   /*!< STM32F302RE, STM32F302VE, STM32F302ZE, STM32F302RD,
+                                   STM32F302VD and STM32F302ZD Devices */
+  /* #define STM32F303x8 */   /*!< STM32F303K6, STM32F303K8, STM32F303C6, STM32F303C8, 
+                                   STM32F303R6 and STM32F303R8 Devices */
+  /* #define STM32F303xC */   /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC,
+                                   STM32F303VB and STM32F303VC Devices */
+#define STM32F303xE   /*!< STM32F303RE, STM32F303VE, STM32F303ZE, STM32F303RD,
+                                   STM32F303VD and STM32F303ZD Devices */
+  /* #define STM32F373xC */   /*!< STM32F373C8, STM32F373CB, STM32F373CC,
+                                   STM32F373R8, STM32F373RB, STM32F373RC,
+                                   STM32F373V8, STM32F373VB and STM32F373VC Devices */
+  /* #define STM32F334x8 */   /*!< STM32F334K4, STM32F334K6, STM32F334K8,
+                                   STM32F334C4, STM32F334C6, STM32F334C8,
+                                   STM32F334R4, STM32F334R6 and STM32F334R8 Devices */
+  /* #define STM32F318xx */   /*!< STM32F318K8, STM32F318C8: STM32F301x8 with regulator off: STM32F318xx Devices */
+  /* #define STM32F328xx */   /*!< STM32F328C8, STM32F328R8: STM32F334x8 with regulator off: STM32F328xx Devices */
+  /* #define STM32F358xx */   /*!< STM32F358CC, STM32F358RC, STM32F358VC: STM32F303xC with regulator off: STM32F358xx Devices */
+  /* #define STM32F378xx */   /*!< STM32F378CC, STM32F378RC, STM32F378VC: STM32F373xC with regulator off: STM32F378xx Devices */
+  /* #define STM32F398xx */   /*!< STM32F398VE: STM32F303xE with regulator off: STM32F398xx Devices */
+#endif
+   
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V2.3.0
+  */
+#define __STM32F3_CMSIS_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
+#define __STM32F3_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
+#define __STM32F3_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F3_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32F3_CMSIS_VERSION        ((__STM32F3_CMSIS_VERSION_MAIN     << 24)\
+                                       |(__STM32F3_CMSIS_VERSION_SUB1 << 16)\
+                                       |(__STM32F3_CMSIS_VERSION_SUB2 << 8 )\
+                                       |(__STM32F3_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32F301x8)
+  #include "stm32f301x8.h"
+#elif defined(STM32F302x8)
+  #include "stm32f302x8.h"
+#elif defined(STM32F302xC)
+  #include "stm32f302xc.h"
+#elif defined(STM32F302xE)
+  #include "stm32f302xe.h"
+#elif defined(STM32F303x8)
+  #include "stm32f303x8.h"
+#elif defined(STM32F303xC)
+  #include "stm32f303xc.h"
+#elif defined(STM32F303xE)
+  #include "stm32f303xe.h"
+#elif defined(STM32F373xC)
+  #include "stm32f373xc.h"
+#elif defined(STM32F334x8)
+  #include "stm32f334x8.h"
+#elif defined(STM32F318xx)
+  #include "stm32f318xx.h"
+#elif defined(STM32F328xx)
+  #include "stm32f328xx.h"
+#elif defined(STM32F358xx)
+  #include "stm32f358xx.h"
+#elif defined(STM32F378xx)
+  #include "stm32f378xx.h"
+#elif defined(STM32F398xx)
+  #include "stm32f398xx.h"
+#else
+ #error "Please select first the target STM32F3xx device used in your application (in stm32f3xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */ 
+typedef enum 
+{
+  RESET = 0, 
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum 
+{
+  DISABLE = 0, 
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum 
+{
+  ERROR = 0, 
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
+
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f3xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F3xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/system_stm32f3xx.c	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,459 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f3xx.c
+  * @author  MCD Application Team
+  * @version V2.3.0
+  * @date    29-April-2015
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *
+  * 1. This file provides two functions and one global variable to be called from
+  *    user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f3xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
+  *                                    | (external 8 MHz clock) | (internal 8 MHz)
+  *                                    | 2- PLL_HSE_XTAL        |
+  *                                    | (external 8 MHz xtal)  |
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 36                     | 32
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * USB capable (48 MHz precise clock) | NO                     | NO
+  *-----------------------------------------------------------------------------
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f3xx_system
+  * @{
+  */
+
+/** @addtogroup STM32F3xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f3xx.h"
+#include "hal_tick.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F3xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F3xx_System_Private_Defines
+  * @{
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
+                                  This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F3xx_System_Private_Macros
+  * @{
+  */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F3xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock there is no need to
+               call the 2 first functions listed above, since SystemCoreClock variable is 
+               updated automatically.
+  */
+uint32_t SystemCoreClock = 72000000;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F3xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and the PLL configuration is reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= 0x00000001U;
+
+  /* Reset CFGR register */
+  RCC->CFGR &= 0xF87FC00CU;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= 0xFEF6FFFFU;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+  RCC->CFGR &= 0xFF80FFFFU;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= 0xFFFFFFF0U;
+
+  /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+  RCC->CFGR3 &= 0xFF00FCCCU;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000U;
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* Configure the Cube driver */
+  SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
+  HAL_Init();
+
+  /* Configure the System clock source, PLL Multiplier and Divider factors,
+     AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+
+  /* Reset the timer to avoid issues after the RAM initialization */
+  TIM_MST_RESET_ON;
+  TIM_MST_RESET_OFF;
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+
+#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
+        predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+      if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
+      {
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
+      }
+      else
+      {
+        /* HSI oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
+      }
+#else      
+      if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
+      }
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+      break;
+    default: /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).             
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+  /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+  if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+  {
+    /* 2- If fail try to start with HSE and external xtal */
+    #if USE_PLL_HSE_XTAL != 0
+    if (SetSysClock_PLL_HSE(0) == 0)
+    #endif
+    {
+      /* 3- If fail start with HSI clock */
+      if (SetSysClock_PLL_HSI() == 0)
+      {
+        while(1)
+        {
+          // [TODO] Put something here to tell the user that a problem occured...
+        }
+      }
+    }
+  }
+  
+  /* Output clock on MCO1 pin(PA8) for debugging purpose */
+  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  /* Enable HSE oscillator and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+  if (bypass == 0)
+  {
+    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+  }
+  else
+  {
+    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+  }
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PREDIV          = RCC_PREDIV_DIV1;
+  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+ 
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+
+  /* Output clock on MCO1 pin(PA8) for debugging purpose */
+  //if (bypass == 0)
+  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
+  //else
+  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
+  
+  return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  /* Enable HSI oscillator and activate PLL with HSI as source */
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PREDIV          = RCC_PREDIV_DIV2;
+  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+ 
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 64 MHz
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 32 MHz
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+
+  /* Output clock on MCO1 pin(PA8) for debugging purpose */
+  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
+
+  return 1; // OK
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/system_stm32f3xx.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,126 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f3xx.h
+  * @author  MCD Application Team
+  * @version V2.3.0
+  * @date    29-April-2015
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f3xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F3XX_H
+#define __SYSTEM_STM32F3XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F3xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F3xx_System_Exported_types
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      3) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) by calling HAL API function HAL_RCC_ClockConfig()
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+extern const uint8_t AHBPrescTable[16];   /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8];    /*!< APB prescalers table values */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F3xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F3xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F3xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F3XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_ARM_STD/startup_stm32f769xx.S	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,479 @@
+;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;* File Name          : startup_stm32f769xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.1.0
+;* Date               : 22-April-2016
+;* Description        : STM32F769xx devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM7 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+__initial_sp    EQU     0x20080000 ; Top of RAM
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+                DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+                DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FMC_IRQHandler                    ; FMC                                             
+                DCD     SDMMC1_IRQHandler                  ; SDMMC1                                            
+                DCD     TIM5_IRQHandler                   ; TIM5                                            
+                DCD     SPI3_IRQHandler                   ; SPI3                                            
+                DCD     UART4_IRQHandler                  ; UART4                                           
+                DCD     UART5_IRQHandler                  ; UART5                                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+                DCD     TIM7_IRQHandler                   ; TIM7                   
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
+                DCD     ETH_IRQHandler                    ; Ethernet                                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
+                DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
+                DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
+                DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
+                DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+                DCD     USART6_IRQHandler                 ; USART6                                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
+                DCD     DCMI_IRQHandler                   ; DCMI                                            
+                DCD     0                                 ; Reserved                                     
+                DCD     RNG_IRQHandler                    ; Rng
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     UART7_IRQHandler                  ; UART7
+                DCD     UART8_IRQHandler                  ; UART8
+                DCD     SPI4_IRQHandler                   ; SPI4
+                DCD     SPI5_IRQHandler                   ; SPI5
+                DCD     SPI6_IRQHandler                   ; SPI6
+                DCD     SAI1_IRQHandler                   ; SAI1
+                DCD     LTDC_IRQHandler                   ; LTDC
+                DCD     LTDC_ER_IRQHandler                ; LTDC error
+                DCD     DMA2D_IRQHandler                  ; DMA2D
+                DCD     SAI2_IRQHandler                   ; SAI2
+                DCD     QUADSPI_IRQHandler                ; QUADSPI
+                DCD     LPTIM1_IRQHandler                 ; LPTIM1
+                DCD     CEC_IRQHandler                    ; HDMI_CEC
+                DCD     I2C4_EV_IRQHandler                ; I2C4 Event
+                DCD     I2C4_ER_IRQHandler                ; I2C4 Error 
+                DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+                DCD     DSI_IRQHandler                    ; DSI
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+                DCD     SDMMC2_IRQHandler                 ; SDMMC2
+                DCD     CAN3_TX_IRQHandler                ; CAN3 TX
+                DCD     CAN3_RX0_IRQHandler               ; CAN3 RX0
+                DCD     CAN3_RX1_IRQHandler               ; CAN3 RX1
+                DCD     CAN3_SCE_IRQHandler               ; CAN3 SCE
+                DCD     JPEG_IRQHandler                   ; JPEG
+                DCD     MDIOS_IRQHandler                  ; MDIOS
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                        
+                EXPORT  PVD_IRQHandler                    [WEAK]                      
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]         
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                         
+                EXPORT  RCC_IRQHandler                    [WEAK]                                            
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                             
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI4_IRQHandler                  [WEAK]                                            
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]                                
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  ADC_IRQHandler                    [WEAK]                         
+                EXPORT  CAN1_TX_IRQHandler                [WEAK]                                                
+                EXPORT  CAN1_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN1_RX1_IRQHandler               [WEAK]                                                
+                EXPORT  CAN1_SCE_IRQHandler               [WEAK]                                                
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_TIM9_IRQHandler          [WEAK]                  
+                EXPORT  TIM1_UP_TIM10_IRQHandler          [WEAK]                
+                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler     [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                  
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FMC_IRQHandler                    [WEAK]                                             
+                EXPORT  SDMMC1_IRQHandler                 [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  CAN2_TX_IRQHandler                [WEAK]                                               
+                EXPORT  CAN2_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_RX1_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_SCE_IRQHandler               [WEAK]                                               
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                                       
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]                                                                                  
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  UART7_IRQHandler                  [WEAK]
+                EXPORT  UART8_IRQHandler                  [WEAK]
+                EXPORT  SPI4_IRQHandler                   [WEAK]
+                EXPORT  SPI5_IRQHandler                   [WEAK]
+                EXPORT  SPI6_IRQHandler                   [WEAK]
+                EXPORT  SAI1_IRQHandler                   [WEAK]
+                EXPORT  LTDC_IRQHandler                   [WEAK]
+                EXPORT  LTDC_ER_IRQHandler                [WEAK]
+                EXPORT  DMA2D_IRQHandler                  [WEAK]
+                EXPORT  SAI2_IRQHandler                   [WEAK]   
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  CEC_IRQHandler                    [WEAK]   
+                EXPORT  I2C4_EV_IRQHandler                [WEAK]
+                EXPORT  I2C4_ER_IRQHandler                [WEAK] 
+                EXPORT  SPDIF_RX_IRQHandler               [WEAK]
+                EXPORT  DSI_IRQHandler                    [WEAK]
+                EXPORT  DFSDM1_FLT0_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT1_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT2_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT3_IRQHandler            [WEAK]
+                EXPORT  SDMMC2_IRQHandler                 [WEAK]
+                EXPORT  CAN3_TX_IRQHandler                [WEAK]
+                EXPORT  CAN3_RX0_IRQHandler               [WEAK]
+                EXPORT  CAN3_RX1_IRQHandler               [WEAK]
+                EXPORT  CAN3_SCE_IRQHandler               [WEAK]
+                EXPORT  JPEG_IRQHandler                   [WEAK]
+                EXPORT  MDIOS_IRQHandler                  [WEAK]
+                
+WWDG_IRQHandler                                                       
+PVD_IRQHandler                                      
+TAMP_STAMP_IRQHandler                  
+RTC_WKUP_IRQHandler                                
+FLASH_IRQHandler                                                       
+RCC_IRQHandler                                                            
+EXTI0_IRQHandler                                                          
+EXTI1_IRQHandler                                                           
+EXTI2_IRQHandler                                                          
+EXTI3_IRQHandler                                                         
+EXTI4_IRQHandler                                                          
+DMA1_Stream0_IRQHandler                                       
+DMA1_Stream1_IRQHandler                                          
+DMA1_Stream2_IRQHandler                                          
+DMA1_Stream3_IRQHandler                                          
+DMA1_Stream4_IRQHandler                                          
+DMA1_Stream5_IRQHandler                                          
+DMA1_Stream6_IRQHandler                                          
+ADC_IRQHandler                                         
+CAN1_TX_IRQHandler                                                            
+CAN1_RX0_IRQHandler                                                          
+CAN1_RX1_IRQHandler                                                           
+CAN1_SCE_IRQHandler                                                           
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_TIM9_IRQHandler                        
+TIM1_UP_TIM10_IRQHandler                      
+TIM1_TRG_COM_TIM11_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                            
+OTG_FS_WKUP_IRQHandler                                
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FMC_IRQHandler                                                            
+SDMMC1_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+CAN2_TX_IRQHandler                                                           
+CAN2_RX0_IRQHandler                                                          
+CAN2_RX1_IRQHandler                                                          
+CAN2_SCE_IRQHandler                                                          
+OTG_FS_IRQHandler                                                    
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler                           
+OTG_HS_EP1_IN_IRQHandler                            
+OTG_HS_WKUP_IRQHandler                                
+OTG_HS_IRQHandler                                                   
+DCMI_IRQHandler                                                                                                                
+RNG_IRQHandler
+FPU_IRQHandler  
+UART7_IRQHandler                  
+UART8_IRQHandler                  
+SPI4_IRQHandler                   
+SPI5_IRQHandler                   
+SPI6_IRQHandler                   
+SAI1_IRQHandler                   
+LTDC_IRQHandler                   
+LTDC_ER_IRQHandler                 
+DMA2D_IRQHandler   
+SAI2_IRQHandler        
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DSI_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SDMMC2_IRQHandler
+CAN3_TX_IRQHandler
+CAN3_RX0_IRQHandler
+CAN3_RX1_IRQHandler
+CAN3_SCE_IRQHandler
+JPEG_IRQHandler
+MDIOS_IRQHandler
+                B       .
+
+                ENDP
+
+                ALIGN
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_ARM_STD/stm32f769ni.sct	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2016, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F769NI: 2048 KB FLASH (0x200000) + 512 KB SRAM (0x80000)
+LR_IROM1 0x08000000 0x200000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x200000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; Total: 126 vectors = 504 bytes (0x1F8) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x1F8) (0x80000-0x1F8)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_ARM_STD/sys.cpp	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model, 
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_GCC_ARM/STM32F769NI.ld	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,153 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{ 
+  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
+  RAM (rwx)  : ORIGIN = 0x200001F8, LENGTH = 512K - 0x1F8
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+    _sidata = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        _sdata = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+        _edata = .;
+
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        _sbss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+        _ebss = .;
+    } > RAM
+
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_GCC_ARM/startup_stm32f769xx.S	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,644 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f769xx.s
+  * @author    MCD Application Team
+  * @version   V1.1.0
+  * @date      22-April-2016
+  * @brief     STM32F769xx Devices vector table for GCC based toolchain. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M7 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+    
+  .syntax unified
+  .cpu cortex-m7
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */  
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+  ldr   sp, =_estack      /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system initialization function.*/
+  bl  SystemInit   
+/* Call static constructors */
+  //bl __libc_init_array
+/* Call the application's entry point.*/
+  //bl  main
+  // Calling the crt0 'cold-start' entry point. There __libc_init_array is called
+  // and when existing hardware_init_hook() and software_init_hook() before 
+  // starting main(). software_init_hook() is available and has to be called due 
+  // to initializsation when using rtos.
+  bl _start
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M7. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+   
+   
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */
+  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
+  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */
+  .word     FLASH_IRQHandler                  /* FLASH                        */
+  .word     RCC_IRQHandler                    /* RCC                          */
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */
+  .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */
+  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */
+  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */
+  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */
+  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */
+  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */
+  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
+  .word     TIM2_IRQHandler                   /* TIM2                         */
+  .word     TIM3_IRQHandler                   /* TIM3                         */
+  .word     TIM4_IRQHandler                   /* TIM4                         */
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */
+  .word     SPI1_IRQHandler                   /* SPI1                         */
+  .word     SPI2_IRQHandler                   /* SPI2                         */
+  .word     USART1_IRQHandler                 /* USART1                       */
+  .word     USART2_IRQHandler                 /* USART2                       */
+  .word     USART3_IRQHandler                 /* USART3                       */
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */
+  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */
+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */
+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */
+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */
+  .word     FMC_IRQHandler                    /* FMC                          */
+  .word     SDMMC1_IRQHandler                 /* SDMMC1                       */
+  .word     TIM5_IRQHandler                   /* TIM5                         */
+  .word     SPI3_IRQHandler                   /* SPI3                         */
+  .word     UART4_IRQHandler                  /* UART4                        */
+  .word     UART5_IRQHandler                  /* UART5                        */
+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */
+  .word     TIM7_IRQHandler                   /* TIM7                         */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */
+  .word     ETH_IRQHandler                    /* Ethernet                     */
+  .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */
+  .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */
+  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */
+  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */
+  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */
+  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */
+  .word     USART6_IRQHandler                 /* USART6                       */
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */
+  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */
+  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */
+  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */
+  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */
+  .word     DCMI_IRQHandler                   /* DCMI                         */
+  .word     0                                 /* Reserved                     */
+  .word     RNG_IRQHandler                    /* RNG                          */
+  .word     FPU_IRQHandler                    /* FPU                          */
+  .word     UART7_IRQHandler                  /* UART7                        */
+  .word     UART8_IRQHandler                  /* UART8                        */
+  .word     SPI4_IRQHandler                   /* SPI4                         */
+  .word     SPI5_IRQHandler                   /* SPI5                         */
+  .word     SPI6_IRQHandler                   /* SPI6                         */
+  .word     SAI1_IRQHandler                   /* SAI1                         */
+  .word     LTDC_IRQHandler                   /* LTDC                         */
+  .word     LTDC_ER_IRQHandler                /* LTDC error                   */
+  .word     DMA2D_IRQHandler                  /* DMA2D                        */
+  .word     SAI2_IRQHandler                   /* SAI2                         */
+  .word     QUADSPI_IRQHandler                /* QUADSPI                      */
+  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
+  .word     CEC_IRQHandler                    /* HDMI_CEC                     */
+  .word     I2C4_EV_IRQHandler                /* I2C4 Event                   */
+  .word     I2C4_ER_IRQHandler                /* I2C4 Error                   */
+  .word     SPDIF_RX_IRQHandler               /* SPDIF_RX                     */
+  .word     DSI_IRQHandler                    /* DSI                          */
+  .word     DFSDM1_FLT0_IRQHandler            /* DFSDM1 Filter 0 global Interrupt */
+  .word     DFSDM1_FLT1_IRQHandler            /* DFSDM1 Filter 1 global Interrupt */
+  .word     DFSDM1_FLT2_IRQHandler            /* DFSDM1 Filter 2 global Interrupt */
+  .word     DFSDM1_FLT3_IRQHandler            /* DFSDM1 Filter 3 global Interrupt */
+  .word     SDMMC2_IRQHandler                 /* SDMMC2                       */
+  .word     CAN3_TX_IRQHandler                /* CAN3 TX                      */
+  .word     CAN3_RX0_IRQHandler               /* CAN3 RX0                     */
+  .word     CAN3_RX1_IRQHandler               /* CAN3 RX1                     */
+  .word     CAN3_SCE_IRQHandler               /* CAN3 SCE                     */
+  .word     JPEG_IRQHandler                   /* JPEG                         */
+  .word     MDIOS_IRQHandler                  /* MDIOS                        */
+  
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler                   
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+                  
+   .weak      PVD_IRQHandler      
+   .thumb_set PVD_IRQHandler,Default_Handler
+               
+   .weak      TAMP_STAMP_IRQHandler            
+   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+            
+   .weak      RTC_WKUP_IRQHandler                  
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+            
+   .weak      FLASH_IRQHandler         
+   .thumb_set FLASH_IRQHandler,Default_Handler
+                  
+   .weak      RCC_IRQHandler      
+   .thumb_set RCC_IRQHandler,Default_Handler
+                  
+   .weak      EXTI0_IRQHandler         
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+                  
+   .weak      EXTI1_IRQHandler         
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+                     
+   .weak      EXTI2_IRQHandler         
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+                 
+   .weak      EXTI3_IRQHandler         
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+                        
+   .weak      EXTI4_IRQHandler         
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream0_IRQHandler               
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+         
+   .weak      DMA1_Stream1_IRQHandler               
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream2_IRQHandler               
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream3_IRQHandler               
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler 
+                 
+   .weak      DMA1_Stream4_IRQHandler              
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream5_IRQHandler               
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream6_IRQHandler               
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      ADC_IRQHandler      
+   .thumb_set ADC_IRQHandler,Default_Handler
+               
+   .weak      CAN1_TX_IRQHandler   
+   .thumb_set CAN1_TX_IRQHandler,Default_Handler
+            
+   .weak      CAN1_RX0_IRQHandler                  
+   .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN1_RX1_IRQHandler                  
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+            
+   .weak      CAN1_SCE_IRQHandler                  
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+            
+   .weak      EXTI9_5_IRQHandler   
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+            
+   .weak      TIM1_BRK_TIM9_IRQHandler            
+   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+            
+   .weak      TIM1_UP_TIM10_IRQHandler            
+   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+
+   .weak      TIM1_TRG_COM_TIM11_IRQHandler      
+   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+      
+   .weak      TIM1_CC_IRQHandler   
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+                  
+   .weak      TIM2_IRQHandler            
+   .thumb_set TIM2_IRQHandler,Default_Handler
+                  
+   .weak      TIM3_IRQHandler            
+   .thumb_set TIM3_IRQHandler,Default_Handler
+                  
+   .weak      TIM4_IRQHandler            
+   .thumb_set TIM4_IRQHandler,Default_Handler
+                  
+   .weak      I2C1_EV_IRQHandler   
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+                     
+   .weak      I2C1_ER_IRQHandler   
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+                     
+   .weak      I2C2_EV_IRQHandler   
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+                  
+   .weak      I2C2_ER_IRQHandler   
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+                           
+   .weak      SPI1_IRQHandler            
+   .thumb_set SPI1_IRQHandler,Default_Handler
+                        
+   .weak      SPI2_IRQHandler            
+   .thumb_set SPI2_IRQHandler,Default_Handler
+                  
+   .weak      USART1_IRQHandler      
+   .thumb_set USART1_IRQHandler,Default_Handler
+                     
+   .weak      USART2_IRQHandler      
+   .thumb_set USART2_IRQHandler,Default_Handler
+                     
+   .weak      USART3_IRQHandler      
+   .thumb_set USART3_IRQHandler,Default_Handler
+                  
+   .weak      EXTI15_10_IRQHandler               
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+               
+   .weak      RTC_Alarm_IRQHandler               
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+            
+   .weak      OTG_FS_WKUP_IRQHandler         
+   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      TIM8_BRK_TIM12_IRQHandler         
+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+         
+   .weak      TIM8_UP_TIM13_IRQHandler            
+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+         
+   .weak      TIM8_TRG_COM_TIM14_IRQHandler      
+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+      
+   .weak      TIM8_CC_IRQHandler   
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream7_IRQHandler               
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+                     
+   .weak      FMC_IRQHandler            
+   .thumb_set FMC_IRQHandler,Default_Handler
+                     
+   .weak      SDMMC1_IRQHandler            
+   .thumb_set SDMMC1_IRQHandler,Default_Handler
+                     
+   .weak      TIM5_IRQHandler            
+   .thumb_set TIM5_IRQHandler,Default_Handler
+                     
+   .weak      SPI3_IRQHandler            
+   .thumb_set SPI3_IRQHandler,Default_Handler
+                     
+   .weak      UART4_IRQHandler         
+   .thumb_set UART4_IRQHandler,Default_Handler
+                  
+   .weak      UART5_IRQHandler         
+   .thumb_set UART5_IRQHandler,Default_Handler
+                  
+   .weak      TIM6_DAC_IRQHandler                  
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+               
+   .weak      TIM7_IRQHandler            
+   .thumb_set TIM7_IRQHandler,Default_Handler
+         
+   .weak      DMA2_Stream0_IRQHandler               
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+               
+   .weak      DMA2_Stream1_IRQHandler               
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream2_IRQHandler               
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream3_IRQHandler               
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream4_IRQHandler               
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+   
+   .weak      DMA2_Stream4_IRQHandler               
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler   
+
+   .weak      ETH_IRQHandler   
+   .thumb_set ETH_IRQHandler,Default_Handler
+   
+   .weak      ETH_WKUP_IRQHandler   
+   .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler   
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler   
+                           
+   .weak      CAN2_RX0_IRQHandler                  
+   .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_RX1_IRQHandler                  
+   .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_SCE_IRQHandler                  
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+                           
+   .weak      OTG_FS_IRQHandler      
+   .thumb_set OTG_FS_IRQHandler,Default_Handler
+                     
+   .weak      DMA2_Stream5_IRQHandler               
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream6_IRQHandler               
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream7_IRQHandler               
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+                  
+   .weak      USART6_IRQHandler      
+   .thumb_set USART6_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_EV_IRQHandler   
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_ER_IRQHandler   
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+                        
+   .weak      OTG_HS_EP1_OUT_IRQHandler         
+   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_EP1_IN_IRQHandler            
+   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_WKUP_IRQHandler         
+   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      OTG_HS_IRQHandler      
+   .thumb_set OTG_HS_IRQHandler,Default_Handler
+                  
+   .weak      DCMI_IRQHandler            
+   .thumb_set DCMI_IRQHandler,Default_Handler
+
+   .weak      RNG_IRQHandler            
+   .thumb_set RNG_IRQHandler,Default_Handler   
+
+   .weak      FPU_IRQHandler                  
+   .thumb_set FPU_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler                  
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler                  
+   .thumb_set UART8_IRQHandler,Default_Handler   
+
+   .weak      SPI4_IRQHandler            
+   .thumb_set SPI4_IRQHandler,Default_Handler
+   
+   .weak      SPI5_IRQHandler            
+   .thumb_set SPI5_IRQHandler,Default_Handler
+
+   .weak      SPI6_IRQHandler            
+   .thumb_set SPI6_IRQHandler,Default_Handler   
+
+   .weak      SAI1_IRQHandler            
+   .thumb_set SAI1_IRQHandler,Default_Handler
+   
+   .weak      LTDC_IRQHandler            
+   .thumb_set LTDC_IRQHandler,Default_Handler
+
+   .weak      LTDC_ER_IRQHandler            
+   .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+   .weak      DMA2D_IRQHandler            
+   .thumb_set DMA2D_IRQHandler,Default_Handler   
+
+   .weak      SAI2_IRQHandler            
+   .thumb_set SAI2_IRQHandler,Default_Handler
+   
+   .weak      QUADSPI_IRQHandler            
+   .thumb_set QUADSPI_IRQHandler,Default_Handler
+ 
+   .weak      LPTIM1_IRQHandler            
+   .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+   .weak      CEC_IRQHandler            
+   .thumb_set CEC_IRQHandler,Default_Handler
+   
+   .weak      I2C4_EV_IRQHandler            
+   .thumb_set I2C4_EV_IRQHandler,Default_Handler 
+ 
+   .weak      I2C4_ER_IRQHandler            
+   .thumb_set I2C4_ER_IRQHandler,Default_Handler
+   
+   .weak      SPDIF_RX_IRQHandler            
+   .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+   .weak      DSI_IRQHandler            
+   .thumb_set DSI_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT0_IRQHandler            
+   .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT1_IRQHandler            
+   .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT2_IRQHandler            
+   .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT3_IRQHandler            
+   .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+   .weak      SDMMC2_IRQHandler            
+   .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+   .weak      CAN3_TX_IRQHandler            
+   .thumb_set CAN3_TX_IRQHandler,Default_Handler
+
+   .weak      CAN3_RX0_IRQHandler            
+   .thumb_set CAN3_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN3_RX1_IRQHandler            
+   .thumb_set CAN3_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN3_SCE_IRQHandler            
+   .thumb_set CAN3_SCE_IRQHandler,Default_Handler
+
+   .weak      JPEG_IRQHandler            
+   .thumb_set JPEG_IRQHandler,Default_Handler
+
+   .weak      MDIOS_IRQHandler            
+   .thumb_set MDIOS_IRQHandler,Default_Handler   
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/        
+ 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_IAR/startup_stm32f769xx.S	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,804 @@
+;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;* File Name          : startup_stm32f769xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.1
+;* Date               : 22-April-2016
+;* Description        : STM32F769xx devices vector table for EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M7 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* 
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+        DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+        DCD     FLASH_IRQHandler                  ; FLASH                                           
+        DCD     RCC_IRQHandler                    ; RCC                                             
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+        DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+        DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+        DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+        DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+        DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+        DCD     TIM2_IRQHandler                   ; TIM2                                            
+        DCD     TIM3_IRQHandler                   ; TIM3                                            
+        DCD     TIM4_IRQHandler                   ; TIM4                                            
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+        DCD     SPI1_IRQHandler                   ; SPI1                                            
+        DCD     SPI2_IRQHandler                   ; SPI2                                            
+        DCD     USART1_IRQHandler                 ; USART1                                          
+        DCD     USART2_IRQHandler                 ; USART2                                          
+        DCD     USART3_IRQHandler                 ; USART3                                          
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+        DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
+        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
+        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+        DCD     FMC_IRQHandler                    ; FMC                                            
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1                                            
+        DCD     TIM5_IRQHandler                   ; TIM5                                            
+        DCD     SPI3_IRQHandler                   ; SPI3                                            
+        DCD     UART4_IRQHandler                  ; UART4                                           
+        DCD     UART5_IRQHandler                  ; UART5                                           
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+        DCD     TIM7_IRQHandler                   ; TIM7                   
+        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
+        DCD     ETH_IRQHandler                    ; Ethernet                                        
+        DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
+        DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
+        DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
+        DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
+        DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
+        DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+        DCD     USART6_IRQHandler                 ; USART6                                           
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+        DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
+        DCD     DCMI_IRQHandler                   ; DCMI                                            
+        DCD     0                                 ; Reserved                                     
+        DCD     RNG_IRQHandler                    ; Rng
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     UART7_IRQHandler                  ; UART7
+        DCD     UART8_IRQHandler                  ; UART8
+        DCD     SPI4_IRQHandler                   ; SPI4
+        DCD     SPI5_IRQHandler                   ; SPI5
+        DCD     SPI6_IRQHandler                   ; SPI6
+        DCD     SAI1_IRQHandler                   ; SAI1
+        DCD     LTDC_IRQHandler                   ; LTDC
+        DCD     LTDC_ER_IRQHandler                ; LTDC error
+        DCD     DMA2D_IRQHandler                  ; DMA2D
+        DCD     SAI2_IRQHandler                   ; SAI2
+        DCD     QUADSPI_IRQHandler                ; QUADSPI
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1
+        DCD     CEC_IRQHandler                    ; HDMI_CEC
+        DCD     I2C4_EV_IRQHandler                ; I2C4 Event                                             
+        DCD     I2C4_ER_IRQHandler                ; I2C4 Error 
+        DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX		
+        DCD     DSI_IRQHandler                    ; DSI  	
+        DCD     DFSDM0_IRQHandler	          ; DFSDM Filter1                                            
+        DCD     DFSDM1_IRQHandler	          ; DFSDM Filter2                                            
+        DCD     DFSDM2_IRQHandler	          ; DFSDM Filter3                                            
+        DCD     DFSDM3_IRQHandler	          ; DFSDM Filter4
+        DCD     SDMMC2_IRQHandler                 ; SDMMC2   
+        DCD     CAN3_TX_IRQHandler                ; CAN3 TX                                                
+        DCD     CAN3_RX0_IRQHandler               ; CAN3 RX0                                               
+        DCD     CAN3_RX1_IRQHandler               ; CAN3 RX1                                               
+        DCD     CAN3_SCE_IRQHandler               ; CAN3 SCE 
+        DCD     JPEG_IRQHandler                   ; JPEG
+        DCD     MDIOS_IRQHandler                  ; MDIOS
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler  
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_IRQHandler  
+        B PVD_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TAMP_STAMP_IRQHandler  
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+RTC_WKUP_IRQHandler  
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler  
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler  
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler  
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler  
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler  
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+EXTI4_IRQHandler  
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream0_IRQHandler  
+        B DMA1_Stream0_IRQHandler
+
+        PUBWEAK DMA1_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream1_IRQHandler  
+        B DMA1_Stream1_IRQHandler
+
+        PUBWEAK DMA1_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream2_IRQHandler  
+        B DMA1_Stream2_IRQHandler
+
+        PUBWEAK DMA1_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream3_IRQHandler  
+        B DMA1_Stream3_IRQHandler
+
+        PUBWEAK DMA1_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream4_IRQHandler  
+        B DMA1_Stream4_IRQHandler
+
+        PUBWEAK DMA1_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream5_IRQHandler  
+        B DMA1_Stream5_IRQHandler
+
+        PUBWEAK DMA1_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream6_IRQHandler  
+        B DMA1_Stream6_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler  
+        B ADC_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+CAN1_TX_IRQHandler  
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+CAN1_RX0_IRQHandler  
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+CAN1_RX1_IRQHandler  
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+CAN1_SCE_IRQHandler  
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+EXTI9_5_IRQHandler  
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM1_BRK_TIM9_IRQHandler  
+        B TIM1_BRK_TIM9_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM1_UP_TIM10_IRQHandler  
+        B TIM1_UP_TIM10_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM1_TRG_COM_TIM11_IRQHandler  
+        B TIM1_TRG_COM_TIM11_IRQHandler
+        
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM1_CC_IRQHandler  
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler  
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler  
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler  
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C1_EV_IRQHandler  
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C1_ER_IRQHandler  
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C2_EV_IRQHandler  
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C2_ER_IRQHandler  
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler  
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler  
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler  
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler  
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler  
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)   
+EXTI15_10_IRQHandler  
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)   
+RTC_Alarm_IRQHandler  
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK OTG_FS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+OTG_FS_WKUP_IRQHandler  
+        B OTG_FS_WKUP_IRQHandler
+      
+        PUBWEAK TIM8_BRK_TIM12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM8_BRK_TIM12_IRQHandler  
+        B TIM8_BRK_TIM12_IRQHandler
+
+        PUBWEAK TIM8_UP_TIM13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM8_UP_TIM13_IRQHandler  
+        B TIM8_UP_TIM13_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM8_TRG_COM_TIM14_IRQHandler  
+        B TIM8_TRG_COM_TIM14_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+TIM8_CC_IRQHandler  
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK DMA1_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream7_IRQHandler  
+        B DMA1_Stream7_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler  
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler  
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler  
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler  
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler  
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler  
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)   
+TIM6_DAC_IRQHandler  
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)   
+TIM7_IRQHandler  
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream0_IRQHandler  
+        B DMA2_Stream0_IRQHandler
+
+        PUBWEAK DMA2_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream1_IRQHandler  
+        B DMA2_Stream1_IRQHandler
+
+        PUBWEAK DMA2_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream2_IRQHandler  
+        B DMA2_Stream2_IRQHandler
+
+        PUBWEAK DMA2_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream3_IRQHandler  
+        B DMA2_Stream3_IRQHandler
+
+        PUBWEAK DMA2_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream4_IRQHandler  
+        B DMA2_Stream4_IRQHandler
+
+        PUBWEAK ETH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler  
+        B ETH_IRQHandler
+
+        PUBWEAK ETH_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+ETH_WKUP_IRQHandler  
+        B ETH_WKUP_IRQHandler
+
+        PUBWEAK CAN2_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+CAN2_TX_IRQHandler  
+        B CAN2_TX_IRQHandler
+
+        PUBWEAK CAN2_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+CAN2_RX0_IRQHandler  
+        B CAN2_RX0_IRQHandler
+
+        PUBWEAK CAN2_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+CAN2_RX1_IRQHandler  
+        B CAN2_RX1_IRQHandler
+
+        PUBWEAK CAN2_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+CAN2_SCE_IRQHandler  
+        B CAN2_SCE_IRQHandler
+
+        PUBWEAK OTG_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler  
+        B OTG_FS_IRQHandler
+
+        PUBWEAK DMA2_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream5_IRQHandler  
+        B DMA2_Stream5_IRQHandler
+
+        PUBWEAK DMA2_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream6_IRQHandler  
+        B DMA2_Stream6_IRQHandler
+
+        PUBWEAK DMA2_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream7_IRQHandler  
+        B DMA2_Stream7_IRQHandler
+
+        PUBWEAK USART6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler  
+        B USART6_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C3_EV_IRQHandler  
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C3_ER_IRQHandler  
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+OTG_HS_EP1_OUT_IRQHandler  
+        B OTG_HS_EP1_OUT_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_IN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+OTG_HS_EP1_IN_IRQHandler  
+        B OTG_HS_EP1_IN_IRQHandler
+
+        PUBWEAK OTG_HS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+OTG_HS_WKUP_IRQHandler  
+        B OTG_HS_WKUP_IRQHandler
+
+        PUBWEAK OTG_HS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler  
+        B OTG_HS_IRQHandler
+
+        PUBWEAK DCMI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler  
+        B DCMI_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+RNG_IRQHandler  
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+FPU_IRQHandler  
+        B FPU_IRQHandler
+
+        PUBWEAK UART7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)      
+UART7_IRQHandler 
+        B UART7_IRQHandler  
+
+        PUBWEAK UART8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+UART8_IRQHandler             
+        B UART8_IRQHandler
+        
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SPI4_IRQHandler
+        B SPI4_IRQHandler                 
+
+        PUBWEAK SPI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SPI5_IRQHandler   
+        B SPI5_IRQHandler                  
+
+        PUBWEAK SPI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SPI6_IRQHandler 
+        B SPI6_IRQHandler                    
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SAI1_IRQHandler  
+        B SAI1_IRQHandler                  
+
+        PUBWEAK LTDC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LTDC_IRQHandler 
+        B LTDC_IRQHandler                     
+
+        PUBWEAK LTDC_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LTDC_ER_IRQHandler 
+        B LTDC_ER_IRQHandler                 
+
+        PUBWEAK DMA2D_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DMA2D_IRQHandler 
+        B DMA2D_IRQHandler                  
+
+       PUBWEAK SAI2_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1) 
+SAI2_IRQHandler 
+        B SAI2_IRQHandler          
+
+       PUBWEAK QUADSPI_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1) 
+QUADSPI_IRQHandler 
+        B QUADSPI_IRQHandler       
+        
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LPTIM1_IRQHandler 
+        B LPTIM1_IRQHandler   
+        
+        PUBWEAK CEC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+CEC_IRQHandler 
+        B CEC_IRQHandler 
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C4_EV_IRQHandler 
+        B I2C4_EV_IRQHandler   
+        
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C4_ER_IRQHandler 
+        B I2C4_ER_IRQHandler 
+ 
+        PUBWEAK SPDIF_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SPDIF_RX_IRQHandler 
+        B SPDIF_RX_IRQHandler
+
+        PUBWEAK DSI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DSI_IRQHandler 
+        B DSI_IRQHandler
+		
+        PUBWEAK DFSDM0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DFSDM0_IRQHandler 
+        B DFSDM0_IRQHandler
+
+        PUBWEAK DFSDM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DFSDM1_IRQHandler 
+        B DFSDM1_IRQHandler
+
+        PUBWEAK DFSDM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DFSDM2_IRQHandler 
+        B DFSDM2_IRQHandler
+
+        PUBWEAK DFSDM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DFSDM3_IRQHandler 
+        B DFSDM3_IRQHandler
+
+        PUBWEAK SDMMC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SDMMC2_IRQHandler 
+        B SDMMC2_IRQHandler
+
+        PUBWEAK CAN3_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+CAN3_TX_IRQHandler 
+        B CAN3_TX_IRQHandler
+
+        PUBWEAK CAN3_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+CAN3_RX0_IRQHandler 
+        B CAN3_RX0_IRQHandler
+
+        PUBWEAK CAN3_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+CAN3_RX1_IRQHandler 
+        B CAN3_RX1_IRQHandler
+
+        PUBWEAK CAN3_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+CAN3_SCE_IRQHandler 
+        B CAN3_SCE_IRQHandler
+
+        PUBWEAK JPEG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+JPEG_IRQHandler 
+        B JPEG_IRQHandler
+
+        PUBWEAK MDIOS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+MDIOS_IRQHandler 
+        B MDIOS_IRQHandler			
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_IAR/stm32f769ni.icf	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,35 @@
+/* [ROM = 2048kb = 0x200000] */
+define symbol __intvec_start__     = 0x08000000;
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__   = 0x081FFFFF;
+
+/* [RAM = 512kb = 0x80000] Vector table dynamic copy: 126 vectors = 504 bytes (0x1F8) to be reserved in RAM */
+define symbol __NVIC_start__          = 0x20000000;
+define symbol __NVIC_end__            = 0x200001F7; /* Aligned on 8 bytes */
+define symbol __region_RAM_start__    = 0x200001F8;
+define symbol __region_RAM_end__      = 0x2007FFFF;
+
+define symbol __region_ITCMRAM_start__ = 0x00000000;
+define symbol __region_ITCMRAM_end__   = 0x00003FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+define region ITCMRAM_region = mem:[from __region_ITCMRAM_start__ to __region_ITCMRAM_end__];
+
+/* Stack and Heap */
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __size_cstack__ = 0x8000;
+define symbol __size_heap__   = 0x8000;
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, block STACKHEAP };

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/cmsis.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32f7xx.h"
+#include "cmsis_nvic.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/cmsis_nvic.c	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS   (0x20000000)  // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000)  // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    uint32_t *vectors = (uint32_t *)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = vectors;
+        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+        for (i=0; i<NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+    }
+    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/cmsis_nvic.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */ 
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 98 vectors = 392 bytes from 0x40 to 0x1C7
+// Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM
+#define NVIC_NUM_VECTORS      114
+#define NVIC_USER_IRQ_OFFSET  16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/hal_tick.c	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,144 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.c
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#include "hal_tick.h"
+
+// 0=NO, 1=PG6 toggles at each tick
+#define DEBUG_TICK 0
+
+TIM_HandleTypeDef TimMasterHandle;
+uint32_t PreviousVal = 0;
+
+void HAL_IncTick(void);
+void us_ticker_irq_handler(void);
+
+void timer_irq_handler(void) {
+    // Channel 1 for mbed timeout
+    if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
+        if (__HAL_TIM_GET_IT_SOURCE(&TimMasterHandle, TIM_IT_CC1) == SET) {
+            __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
+            us_ticker_irq_handler();
+        }
+    }
+
+    // Channel 2 for HAL tick
+    if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC2) == SET) {
+        if (__HAL_TIM_GET_IT_SOURCE(&TimMasterHandle, TIM_IT_CC2) == SET) {
+            __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
+            uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
+            if ((val - PreviousVal) >= HAL_TICK_DELAY) {
+                // Increment HAL variable
+                HAL_IncTick();
+                // Prepare next interrupt
+                __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
+                PreviousVal = val;
+#if DEBUG_TICK > 0
+                HAL_GPIO_TogglePin(GPIOG, GPIO_PIN_6);
+#endif
+            }
+        }
+    }
+}
+
+// Reconfigure the HAL tick using a standard timer instead of systick.
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    uint32_t PclkFreq;
+
+    // Get clock configuration
+    // Note: PclkFreq contains here the Latency (not used after)
+    HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &PclkFreq);
+
+    // Get TIM5 clock value
+    PclkFreq = HAL_RCC_GetPCLK1Freq();
+
+    // Enable timer clock
+    TIM_MST_RCC;
+
+    // Reset timer
+    TIM_MST_RESET_ON;
+    TIM_MST_RESET_OFF;
+
+    // Configure time base
+    TimMasterHandle.Instance = TIM_MST;
+    TimMasterHandle.Init.Period = 0xFFFFFFFF;
+
+    // TIMxCLK = PCLKx when the APB prescaler = 1 else TIMxCLK = 2 * PCLKx
+    if (RCC_ClkInitStruct.APB1CLKDivider == RCC_HCLK_DIV1)
+      TimMasterHandle.Init.Prescaler = (uint16_t)((PclkFreq) / 1000000) - 1; // 1 us tick
+    else
+      TimMasterHandle.Init.Prescaler = (uint16_t)((PclkFreq * 2) / 1000000) - 1; // 1 us tick  
+
+    TimMasterHandle.Init.ClockDivision     = 0;
+    TimMasterHandle.Init.CounterMode       = TIM_COUNTERMODE_UP;
+    TimMasterHandle.Init.RepetitionCounter = 0;
+    HAL_TIM_OC_Init(&TimMasterHandle);
+
+    NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
+    NVIC_EnableIRQ(TIM_MST_IRQ);
+
+    // Channel 1 for mbed timeout
+    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+    // Channel 2 for HAL tick
+    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
+    PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
+    __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
+    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+
+#if DEBUG_TICK > 0
+    __GPIOG_CLK_ENABLE();
+    GPIO_InitTypeDef GPIO_InitStruct;
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
+    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+#endif
+
+    return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/hal_tick.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,62 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.h
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f7xx.h"
+#include "cmsis_nvic.h"
+   
+#define TIM_MST      TIM5
+#define TIM_MST_IRQ  TIM5_IRQn
+#define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f769xx.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,11332 @@
+/**
+  ******************************************************************************
+  * @file    stm32f769xx.h
+  * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    22-April-2016
+  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32f769xx
+  * @{
+  */
+    
+#ifndef __STM32F769xx_H
+#define __STM32F769xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+  
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief STM32F7xx Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+typedef enum
+{
+/******  Cortex-M7 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M7 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M7 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M7 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M7 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M7 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M7 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M7 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
+  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
+  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
+  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
+  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
+  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
+  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
+  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
+  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
+  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
+  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
+  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
+  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */
+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */
+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */
+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */
+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */
+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */
+  DSI_IRQn                    = 98,     /*!< DSI global Interrupt                                              */
+  DFSDM1_FLT0_IRQn	          = 99,     /*!< DFSDM1 Filter 0 global Interrupt                                  */
+  DFSDM1_FLT1_IRQn	          = 100,    /*!< DFSDM1 Filter 1 global Interrupt                                  */
+  DFSDM1_FLT2_IRQn	          = 101,    /*!< DFSDM1 Filter 2 global Interrupt                                  */
+  DFSDM1_FLT3_IRQn	          = 102,    /*!< DFSDM1 Filter 3 global Interrupt                                  */
+  SDMMC2_IRQn                 = 103,    /*!< SDMMC2 global Interrupt                                           */
+  CAN3_TX_IRQn                = 104,    /*!< CAN3 TX Interrupt                                                 */
+  CAN3_RX0_IRQn               = 105,    /*!< CAN3 RX0 Interrupt                                                */
+  CAN3_RX1_IRQn               = 106,    /*!< CAN3 RX1 Interrupt                                                */
+  CAN3_SCE_IRQn               = 107,    /*!< CAN3 SCE Interrupt                                                */
+  JPEG_IRQn                   = 108,    /*!< JPEG global Interrupt                                             */
+  MDIOS_IRQn                  = 109     /*!< MDIO Slave global Interrupt                                       */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+/**
+ * @brief Configuration of the Cortex-M7 Processor and Core Peripherals 
+ */
+#define __CM7_REV                 0x0100U  /*!< Cortex-M7 revision r1p0                       */
+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
+  
+  
+#include "system_stm32f7xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
+  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
+  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
+  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
+  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
+  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
+  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
+  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
+  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
+  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
+  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
+  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
+  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
+  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
+  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
+  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
+  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
+  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
+                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/** 
+  * @brief Controller Area Network TxMailBox 
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FIFOMailBox 
+  */
+  
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FilterRegister 
+  */
+  
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/** 
+  * @brief Controller Area Network 
+  */
+  
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+/** 
+  * @brief HDMI-CEC 
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
+  __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
+  __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
+}CEC_TypeDef;
+
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t  DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t   IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t        RESERVED0;   /*!< Reserved, 0x05                                                    */
+  uint16_t       RESERVED1;   /*!< Reserved, 0x06                                                    */
+  __IO uint32_t  CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t       RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t  INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t  POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+  * @brief DFSDM module registers
+  */
+typedef struct
+{
+  __IO uint32_t FLTCR1;         /*!< DFSDM control register1,                          Address offset: 0x100 */
+  __IO uint32_t FLTCR2;         /*!< DFSDM control register2,                          Address offset: 0x104 */
+  __IO uint32_t FLTISR;         /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
+  __IO uint32_t FLTICR;         /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
+  __IO uint32_t FLTJCHGR;       /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
+  __IO uint32_t FLTFCR;         /*!< DFSDM filter control register,                    Address offset: 0x114 */
+  __IO uint32_t FLTJDATAR;      /*!< DFSDM data register for injected group,           Address offset: 0x118 */
+  __IO uint32_t FLTRDATAR;      /*!< DFSDM data register for regular group,            Address offset: 0x11C */
+  __IO uint32_t FLTAWHTR;       /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
+  __IO uint32_t FLTAWLTR;       /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
+  __IO uint32_t FLTAWSR;        /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
+  __IO uint32_t FLTAWCFR;       /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
+  __IO uint32_t FLTEXMAX;       /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
+  __IO uint32_t FLTEXMIN;       /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
+  __IO uint32_t FLTCNVTIMR;     /*!< DFSDM conversion timer,                           Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+  * @brief DFSDM channel configuration registers
+  */
+typedef struct
+{
+  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
+  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
+  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and
+                                  short circuit detector register,                  Address offset: 0x08 */
+  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
+  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
+  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
+  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
+  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DCMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/** 
+  * @brief DMA2D Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+
+/** 
+  * @brief Ethernet MAC
+  */
+
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACFFR;
+  __IO uint32_t MACHTHR;
+  __IO uint32_t MACHTLR;
+  __IO uint32_t MACMIIAR;
+  __IO uint32_t MACMIIDR;
+  __IO uint32_t MACFCR;
+  __IO uint32_t MACVLANTR;             /*    8 */
+  uint32_t      RESERVED0[2];
+  __IO uint32_t MACRWUFFR;             /*   11 */
+  __IO uint32_t MACPMTCSR;
+  uint32_t      RESERVED1[2];
+  __IO uint32_t MACSR;                 /*   15 */
+  __IO uint32_t MACIMR;
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;               /*   24 */
+  uint32_t      RESERVED2[40];
+  __IO uint32_t MMCCR;                 /*   65 */
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;               /*   69 */
+  uint32_t      RESERVED3[14];
+  __IO uint32_t MMCTGFSCCR;            /*   84 */
+  __IO uint32_t MMCTGFMSCCR;
+  uint32_t      RESERVED4[5];
+  __IO uint32_t MMCTGFCR;
+  uint32_t      RESERVED5[10];
+  __IO uint32_t MMCRFCECR;
+  __IO uint32_t MMCRFAECR;
+  uint32_t      RESERVED6[10];
+  __IO uint32_t MMCRGUFCR;
+  uint32_t      RESERVED7[334];
+  __IO uint32_t PTPTSCR;
+  __IO uint32_t PTPSSIR;
+  __IO uint32_t PTPTSHR;
+  __IO uint32_t PTPTSLR;
+  __IO uint32_t PTPTSHUR;
+  __IO uint32_t PTPTSLUR;
+  __IO uint32_t PTPTSAR;
+  __IO uint32_t PTPTTHR;
+  __IO uint32_t PTPTTLR;
+  __IO uint32_t RESERVED8;
+  __IO uint32_t PTPTSSR;
+  uint32_t      RESERVED9[565];
+  __IO uint32_t DMABMR;
+  __IO uint32_t DMATPDR;
+  __IO uint32_t DMARPDR;
+  __IO uint32_t DMARDLAR;
+  __IO uint32_t DMATDLAR;
+  __IO uint32_t DMASR;
+  __IO uint32_t DMAOMR;
+  __IO uint32_t DMAIER;
+  __IO uint32_t DMAMFBOCR;
+  __IO uint32_t DMARSWTR;
+  uint32_t      RESERVED10[8];
+  __IO uint32_t DMACHTDR;
+  __IO uint32_t DMACHRDR;
+  __IO uint32_t DMACHTBAR;
+  __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
+  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
+  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
+  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
+  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;      /*!< FLASH access control register,     Address offset: 0x00 */
+  __IO uint32_t KEYR;     /*!< FLASH key register,                Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,         Address offset: 0x08 */
+  __IO uint32_t SR;       /*!< FLASH status register,             Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< FLASH control register,            Address offset: 0x10 */
+  __IO uint32_t OPTCR;    /*!< FLASH option control register ,    Address offset: 0x14 */
+  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1 ,  Address offset: 0x18 */
+} FLASH_TypeDef;
+
+
+
+/** 
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
+} FMC_Bank1_TypeDef; 
+
+/** 
+  * @brief Flexible Memory Controller Bank1E
+  */
+  
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/** 
+  * @brief Flexible Memory Controller Bank3
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
+  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
+  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
+  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                          */
+  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+ 
+/** 
+  * @brief Flexible Memory Controller Bank5_6
+  */
+  
+typedef struct
+{
+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
+} FMC_Bank5_6_TypeDef; 
+
+
+/** 
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/** 
+  * @brief System configuration controller
+  */
+  
+typedef struct
+{
+  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+  uint32_t      RESERVED;     /*!< Reserved, 0x18                                                               */
+  __IO uint32_t CBR;          /*!< SYSCFG Class B register,                           Address offset: 0x1C      */
+  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
+} SYSCFG_TypeDef;
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */  
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */  
+} I2C_TypeDef;
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+
+/** 
+  * @brief LCD-TFT Display Controller
+  */
+  
+typedef struct
+{
+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */
+} LTDC_TypeDef;  
+
+/** 
+  * @brief LCD-TFT Display layer x Controller
+  */
+  
+typedef struct
+{  
+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
+  uint32_t      RESERVED0[2];  /*!< Reserved */
+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
+  uint32_t      RESERVED1[3];  /*!< Reserved */
+  __IO uint32_t CLUTWR;        /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
+  __IO uint32_t CSR1;  /*!< PWR power control/status register 2, Address offset: 0x04 */
+  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x08 */
+  __IO uint32_t CSR2;  /*!< PWR power control/status register 2, Address offset: 0x0C */
+} PWR_TypeDef;
+
+
+/** 
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
+  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
+  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
+  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
+  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
+  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
+  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
+  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
+  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
+  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
+  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
+  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
+  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
+  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
+  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
+  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
+  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
+  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
+  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
+  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
+  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
+  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
+  __IO uint32_t DCKCFGR1;      /*!< RCC Dedicated Clocks configuration register1,                 Address offset: 0x8C */
+  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x90 */
+
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+       uint32_t reserved;   /*!< Reserved  */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
+} RTC_TypeDef;
+
+
+/** 
+  * @brief Serial Audio Interface
+  */
+  
+typedef struct
+{
+  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/** 
+  * @brief SPDIF-RX Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */  
+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */ 
+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */
+} SPDIFRX_TypeDef;
+
+
+/** 
+  * @brief SD host Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDMMClock control register,     Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
+  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */
+} SDMMC_TypeDef;
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
+  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
+  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
+  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
+  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
+  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
+} SPI_TypeDef;
+
+/** 
+  * @brief QUAD Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
+  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
+  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
+  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
+  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
+  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
+  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
+  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
+  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
+  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */                  
+  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
+  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */    
+} QUADSPI_TypeDef;
+
+/** 
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
+  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare mode register5,       Address offset: 0x58 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare mode register6,       Address offset: 0x5C */
+  __IO uint32_t AF1;         /*!< TIM Alternate function option register 1, Address offset: 0x60 */
+  __IO uint32_t AF2;         /*!< TIM Alternate function option register 2, Address offset: 0x64 */
+
+} TIM_TypeDef;
+
+/** 
+  * @brief LPTIMIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                       Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< LPTIM Control register,                             Address offset: 0x10 */
+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                             Address offset: 0x14 */
+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                             Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+ 
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */                                               
+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+} USART_TypeDef;
+
+
+/** 
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/** 
+  * @brief RNG
+  */
+  
+typedef struct 
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+  * @}
+  */
+
+/** 
+  * @brief USB_OTG_Core_Registers
+  */
+typedef struct
+{
+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
+  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */
+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
+  uint32_t  Reserved6;                /*!< Reserved                                     050h */ 
+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+
+/** 
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
+  uint32_t  Reserved20;          /*!< Reserved                     820h */
+  uint32_t Reserved9;            /*!< Reserved                     824h */
+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */  
+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */   
+} USB_OTG_DeviceTypeDef;
+
+
+/** 
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct 
+{
+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+
+/** 
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+
+/** 
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct 
+{
+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
+} USB_OTG_HostTypeDef;
+
+/** 
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
+  uint32_t Reserved[2];           /*!< Reserved                                      */
+} USB_OTG_HostChannelTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @brief JPEG Codec
+  */
+typedef struct
+{
+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */
+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */
+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */
+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */ 
+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */ 
+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */ 
+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */ 
+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */
+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */
+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */ 
+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */ 
+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */ 
+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */
+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */
+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */
+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */
+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */
+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */
+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */
+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */
+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */
+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */
+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */
+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */
+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */
+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0,                 Address offset: 500h-65Ch */
+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1,                 Address offset: 660h-7BCh */
+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encoder, DC Huffman table 0,                 Address offset: 7C0h-7DCh */
+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encoder, DC Huffman table 1,                 Address offset: 7E0h-7FCh */
+
+} JPEG_TypeDef;
+
+/**
+  * @brief MDIOS
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;               /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 00h       */
+  __IO uint32_t WRFR;             /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 04h       */
+  __IO uint32_t CWRFR;            /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 08h       */
+  __IO uint32_t RDFR;             /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 0Ch       */ 
+  __IO uint32_t CRDFR;            /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 10h       */   
+  __IO uint32_t SR;               /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 14h       */
+  __IO uint32_t CLRFR;            /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 18h       */   	
+  uint32_t RESERVED0[57];         /* Reserved                                          Address offset: 1Ch       */	
+  __IO uint32_t DINR0;            /*!< MDIOS Input Data Register (MDIOS_DINR0),        Address offset: 100h      */    
+  __IO uint32_t DINR1;            /*!< MDIOS Input Data Register (MDIOS_DINR1),        Address offset: 104h      */     
+  __IO uint32_t DINR2;            /*!< MDIOS Input Data Register (MDIOS_DINR2),        Address offset: 108h      */    
+  __IO uint32_t DINR3;            /*!< MDIOS Input Data Register (MDIOS_DINR3),        Address offset: 10Ch      */     
+  __IO uint32_t DINR4;            /*!< MDIOS Input Data Register (MDIOS_DINR4),        Address offset: 110h      */     
+  __IO uint32_t DINR5;            /*!< MDIOS Input Data Register (MDIOS_DINR5),        Address offset: 114h      */     
+  __IO uint32_t DINR6;            /*!< MDIOS Input Data Register (MDIOS_DINR6),        Address offset: 118h      */  
+  __IO uint32_t DINR7;            /*!< MDIOS Input Data Register (MDIOS_DINR7),        Address offset: 11Ch      */ 
+  __IO uint32_t DINR8;            /*!< MDIOS Input Data Register (MDIOS_DINR8),        Address offset: 120h      */ 
+  __IO uint32_t DINR9;            /*!< MDIOS Input Data Register (MDIOS_DINR9),        Address offset: 124h      */ 
+  __IO uint32_t DINR10;           /*!< MDIOS Input Data Register (MDIOS_DINR10),       Address offset: 128h      */ 
+  __IO uint32_t DINR11;           /*!< MDIOS Input Data Register (MDIOS_DINR11),       Address offset: 12Ch      */ 
+  __IO uint32_t DINR12;           /*!< MDIOS Input Data Register (MDIOS_DINR12),       Address offset: 130h      */ 
+  __IO uint32_t DINR13;           /*!< MDIOS Input Data Register (MDIOS_DINR13),       Address offset: 134h      */ 
+  __IO uint32_t DINR14;           /*!< MDIOS Input Data Register (MDIOS_DINR14),       Address offset: 138h      */ 
+  __IO uint32_t DINR15;           /*!< MDIOS Input Data Register (MDIOS_DINR15),       Address offset: 13Ch      */ 
+  __IO uint32_t DINR16;           /*!< MDIOS Input Data Register (MDIOS_DINR16),       Address offset: 140h      */ 
+  __IO uint32_t DINR17;           /*!< MDIOS Input Data Register (MDIOS_DINR17),       Address offset: 144h      */ 
+  __IO uint32_t DINR18;           /*!< MDIOS Input Data Register (MDIOS_DINR18),       Address offset: 148h      */ 
+  __IO uint32_t DINR19;           /*!< MDIOS Input Data Register (MDIOS_DINR19),       Address offset: 14Ch      */ 
+  __IO uint32_t DINR20;           /*!< MDIOS Input Data Register (MDIOS_DINR20),       Address offset: 150h      */ 
+  __IO uint32_t DINR21;           /*!< MDIOS Input Data Register (MDIOS_DINR21),       Address offset: 154h      */ 
+  __IO uint32_t DINR22;           /*!< MDIOS Input Data Register (MDIOS_DINR22),       Address offset: 158h      */ 
+  __IO uint32_t DINR23;           /*!< MDIOS Input Data Register (MDIOS_DINR23),       Address offset: 15Ch      */ 
+  __IO uint32_t DINR24;           /*!< MDIOS Input Data Register (MDIOS_DINR24),       Address offset: 160h      */ 
+  __IO uint32_t DINR25;           /*!< MDIOS Input Data Register (MDIOS_DINR25),       Address offset: 164h      */ 
+  __IO uint32_t DINR26;           /*!< MDIOS Input Data Register (MDIOS_DINR26),       Address offset: 168h      */ 
+  __IO uint32_t DINR27;           /*!< MDIOS Input Data Register (MDIOS_DINR27),       Address offset: 16Ch      */ 
+  __IO uint32_t DINR28;           /*!< MDIOS Input Data Register (MDIOS_DINR28),       Address offset: 170h      */ 
+  __IO uint32_t DINR29;           /*!< MDIOS Input Data Register (MDIOS_DINR29),       Address offset: 174h      */ 
+  __IO uint32_t DINR30;           /*!< MDIOS Input Data Register (MDIOS_DINR30),       Address offset: 178h      */ 
+  __IO uint32_t DINR31;           /*!< MDIOS Input Data Register (MDIOS_DINR31),       Address offset: 17Ch      */ 
+  __IO uint32_t DOUTR0;           /*!< MDIOS Output Data Register (MDIOS_DOUTR0),      Address offset: 180h      */   
+  __IO uint32_t DOUTR1;           /*!< MDIOS Output Data Register (MDIOS_DOUTR1),      Address offset: 184h      */   
+  __IO uint32_t DOUTR2;           /*!< MDIOS Output Data Register (MDIOS_DOUTR2),      Address offset: 188h      */    
+  __IO uint32_t DOUTR3;           /*!< MDIOS Output Data Register (MDIOS_DOUTR3),      Address offset: 18Ch      */    
+  __IO uint32_t DOUTR4;           /*!< MDIOS Output Data Register (MDIOS_DOUTR4),      Address offset: 190h      */   
+  __IO uint32_t DOUTR5;           /*!< MDIOS Output Data Register (MDIOS_DOUTR5),      Address offset: 194h      */    
+  __IO uint32_t DOUTR6;           /*!< MDIOS Output Data Register (MDIOS_DOUTR6),      Address offset: 198h      */    
+  __IO uint32_t DOUTR7;           /*!< MDIOS Output Data Register (MDIOS_DOUTR7),      Address offset: 19Ch      */
+  __IO uint32_t DOUTR8;           /*!< MDIOS Output Data Register (MDIOS_DOUTR8),      Address offset: 1A0h      */
+  __IO uint32_t DOUTR9;           /*!< MDIOS Output Data Register (MDIOS_DOUTR9),      Address offset: 1A4h      */
+  __IO uint32_t DOUTR10;          /*!< MDIOS Output Data Register (MDIOS_DOUTR10),     Address offset: 1A8h      */
+  __IO uint32_t DOUTR11;          /*!< MDIOS Output Data Register (MDIOS_DOUTR11),     Address offset: 1ACh      */
+  __IO uint32_t DOUTR12;          /*!< MDIOS Output Data Register (MDIOS_DOUTR12),     Address offset: 1B0h      */
+  __IO uint32_t DOUTR13;          /*!< MDIOS Output Data Register (MDIOS_DOUTR13),     Address offset: 1B4h      */
+  __IO uint32_t DOUTR14;          /*!< MDIOS Output Data Register (MDIOS_DOUTR14),     Address offset: 1B8h      */
+  __IO uint32_t DOUTR15;          /*!< MDIOS Output Data Register (MDIOS_DOUTR15),     Address offset: 1BCh      */
+  __IO uint32_t DOUTR16;          /*!< MDIOS Output Data Register (MDIOS_DOUTR16),     Address offset: 1C0h      */
+  __IO uint32_t DOUTR17;          /*!< MDIOS Output Data Register (MDIOS_DOUTR17),     Address offset: 1C4h      */
+  __IO uint32_t DOUTR18;          /*!< MDIOS Output Data Register (MDIOS_DOUTR18),     Address offset: 1C8h      */
+  __IO uint32_t DOUTR19;          /*!< MDIOS Output Data Register (MDIOS_DOUTR19),     Address offset: 1CCh      */
+  __IO uint32_t DOUTR20;          /*!< MDIOS Output Data Register (MDIOS_DOUTR20),     Address offset: 1D0h      */
+  __IO uint32_t DOUTR21;          /*!< MDIOS Output Data Register (MDIOS_DOUTR21),     Address offset: 1D4h      */
+  __IO uint32_t DOUTR22;          /*!< MDIOS Output Data Register (MDIOS_DOUTR22),     Address offset: 1D8h      */
+  __IO uint32_t DOUTR23;          /*!< MDIOS Output Data Register (MDIOS_DOUTR23),     Address offset: 1DCh      */
+  __IO uint32_t DOUTR24;          /*!< MDIOS Output Data Register (MDIOS_DOUTR24),     Address offset: 1E0h      */
+  __IO uint32_t DOUTR25;          /*!< MDIOS Output Data Register (MDIOS_DOUTR25),     Address offset: 1E4h      */
+  __IO uint32_t DOUTR26;          /*!< MDIOS Output Data Register (MDIOS_DOUTR26),     Address offset: 1E8h      */
+  __IO uint32_t DOUTR27;          /*!< MDIOS Output Data Register (MDIOS_DOUTR27),     Address offset: 1ECh      */
+  __IO uint32_t DOUTR28;          /*!< MDIOS Output Data Register (MDIOS_DOUTR28),     Address offset: 1F0h      */
+  __IO uint32_t DOUTR29;          /*!< MDIOS Output Data Register (MDIOS_DOUTR29),     Address offset: 1F4h      */
+  __IO uint32_t DOUTR30;          /*!< MDIOS Output Data Register (MDIOS_DOUTR30),     Address offset: 1F8h      */
+  __IO uint32_t DOUTR31;          /*!< MDIOS Output Data Register (MDIOS_DOUTR31),     Address offset: 1FCh      */
+} MDIOS_TypeDef;
+
+/** 
+  * @brief DSI Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t VR;            /*!< DSI Host Version Register,                                 Address offset: 0x00      */
+  __IO uint32_t CR;            /*!< DSI Host Control Register,                                 Address offset: 0x04      */
+  __IO uint32_t CCR;           /*!< DSI HOST Clock Control Register,                           Address offset: 0x08      */
+  __IO uint32_t LVCIDR;        /*!< DSI Host LTDC VCID Register,                               Address offset: 0x0C      */
+  __IO uint32_t LCOLCR;        /*!< DSI Host LTDC Color Coding Register,                       Address offset: 0x10      */ 
+  __IO uint32_t LPCR;          /*!< DSI Host LTDC Polarity Configuration Register,             Address offset: 0x14      */
+  __IO uint32_t LPMCR;         /*!< DSI Host Low-Power Mode Configuration Register,            Address offset: 0x18      */
+  uint32_t      RESERVED0[4];  /*!< Reserved, 0x1C - 0x2B                                                                */
+  __IO uint32_t PCR;           /*!< DSI Host Protocol Configuration Register,                  Address offset: 0x2C      */ 
+  __IO uint32_t GVCIDR;        /*!< DSI Host Generic VCID Register,                            Address offset: 0x30      */
+  __IO uint32_t MCR;           /*!< DSI Host Mode Configuration Register,                      Address offset: 0x34      */
+  __IO uint32_t VMCR;          /*!< DSI Host Video Mode Configuration Register,                Address offset: 0x38      */
+  __IO uint32_t VPCR;          /*!< DSI Host Video Packet Configuration Register,              Address offset: 0x3C      */
+  __IO uint32_t VCCR;          /*!< DSI Host Video Chunks Configuration Register,              Address offset: 0x40      */
+  __IO uint32_t VNPCR;         /*!< DSI Host Video Null Packet Configuration Register,         Address offset: 0x44      */
+  __IO uint32_t VHSACR;        /*!< DSI Host Video HSA Configuration Register,                 Address offset: 0x48      */
+  __IO uint32_t VHBPCR;        /*!< DSI Host Video HBP Configuration Register,                 Address offset: 0x4C      */
+  __IO uint32_t VLCR;          /*!< DSI Host Video Line Configuration Register,                Address offset: 0x50      */
+  __IO uint32_t VVSACR;        /*!< DSI Host Video VSA Configuration Register,                 Address offset: 0x54      */
+  __IO uint32_t VVBPCR;        /*!< DSI Host Video VBP Configuration Register,                 Address offset: 0x58      */
+  __IO uint32_t VVFPCR;        /*!< DSI Host Video VFP Configuration Register,                 Address offset: 0x5C      */
+  __IO uint32_t VVACR;         /*!< DSI Host Video VA Configuration Register,                  Address offset: 0x60      */
+  __IO uint32_t LCCR;          /*!< DSI Host LTDC Command Configuration Register,              Address offset: 0x64      */ 
+  __IO uint32_t CMCR;          /*!< DSI Host Command Mode Configuration Register,              Address offset: 0x68      */
+  __IO uint32_t GHCR;          /*!< DSI Host Generic Header Configuration Register,            Address offset: 0x6C      */
+  __IO uint32_t GPDR;          /*!< DSI Host Generic Payload Data Register,                    Address offset: 0x70      */
+  __IO uint32_t GPSR;          /*!< DSI Host Generic Packet Status Register,                   Address offset: 0x74      */
+  __IO uint32_t TCCR[6];       /*!< DSI Host Timeout Counter Configuration Register,           Address offset: 0x78-0x8F */
+  __IO uint32_t TDCR;          /*!< DSI Host 3D Configuration Register,                        Address offset: 0x90      */ 
+  __IO uint32_t CLCR;          /*!< DSI Host Clock Lane Configuration Register,                Address offset: 0x94      */
+  __IO uint32_t CLTCR;         /*!< DSI Host Clock Lane Timer Configuration Register,          Address offset: 0x98      */
+  __IO uint32_t DLTCR;         /*!< DSI Host Data Lane Timer Configuration Register,           Address offset: 0x9C      */
+  __IO uint32_t PCTLR;         /*!< DSI Host PHY Control Register,                             Address offset: 0xA0      */ 
+  __IO uint32_t PCONFR;        /*!< DSI Host PHY Configuration Register,                       Address offset: 0xA4      */ 
+  __IO uint32_t PUCR;          /*!< DSI Host PHY ULPS Control Register,                        Address offset: 0xA8      */
+  __IO uint32_t PTTCR;         /*!< DSI Host PHY TX Triggers Configuration Register,           Address offset: 0xAC      */
+  __IO uint32_t PSR;           /*!< DSI Host PHY Status Register,                              Address offset: 0xB0      */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0xB4 - 0xBB                                                                */
+  __IO uint32_t ISR[2];        /*!< DSI Host Interrupt & Status Register,                      Address offset: 0xBC-0xC3 */
+  __IO uint32_t IER[2];        /*!< DSI Host Interrupt Enable Register,                        Address offset: 0xC4-0xCB */
+  uint32_t      RESERVED2[3];  /*!< Reserved, 0xD0 - 0xD7                                                                */
+  __IO uint32_t FIR[2];        /*!< DSI Host Force Interrupt Register,                         Address offset: 0xD8-0xDF */
+  uint32_t      RESERVED3[8];  /*!< Reserved, 0xE0 - 0xFF                                                                */
+  __IO uint32_t VSCR;          /*!< DSI Host Video Shadow Control Register,                    Address offset: 0x100     */
+  uint32_t      RESERVED4[2];  /*!< Reserved, 0x104 - 0x10B                                                              */
+  __IO uint32_t LCVCIDR;       /*!< DSI Host LTDC Current VCID Register,                       Address offset: 0x10C     */
+  __IO uint32_t LCCCR;         /*!< DSI Host LTDC Current Color Coding Register,               Address offset: 0x110     */
+  uint32_t      RESERVED5;     /*!< Reserved, 0x114                                                                      */
+  __IO uint32_t LPMCCR;        /*!< DSI Host Low-power Mode Current Configuration Register,    Address offset: 0x118     */
+  uint32_t      RESERVED6[7];  /*!< Reserved, 0x11C - 0x137                                                              */
+  __IO uint32_t VMCCR;         /*!< DSI Host Video Mode Current Configuration Register,        Address offset: 0x138     */
+  __IO uint32_t VPCCR;         /*!< DSI Host Video Packet Current Configuration Register,      Address offset: 0x13C     */
+  __IO uint32_t VCCCR;         /*!< DSI Host Video Chuncks Current Configuration Register,     Address offset: 0x140     */
+  __IO uint32_t VNPCCR;        /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144     */
+  __IO uint32_t VHSACCR;       /*!< DSI Host Video HSA Current Configuration Register,         Address offset: 0x148     */
+  __IO uint32_t VHBPCCR;       /*!< DSI Host Video HBP Current Configuration Register,         Address offset: 0x14C     */
+  __IO uint32_t VLCCR;         /*!< DSI Host Video Line Current Configuration Register,        Address offset: 0x150     */
+  __IO uint32_t VVSACCR;       /*!< DSI Host Video VSA Current Configuration Register,         Address offset: 0x154     */ 
+  __IO uint32_t VVBPCCR;       /*!< DSI Host Video VBP Current Configuration Register,         Address offset: 0x158     */
+  __IO uint32_t VVFPCCR;       /*!< DSI Host Video VFP Current Configuration Register,         Address offset: 0x15C     */
+  __IO uint32_t VVACCR;        /*!< DSI Host Video VA Current Configuration Register,          Address offset: 0x160     */
+  uint32_t      RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F                                                              */
+  __IO uint32_t TDCCR;         /*!< DSI Host 3D Current Configuration Register,                Address offset: 0x190     */ 
+  uint32_t      RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF                                                               */
+  __IO uint32_t WCFGR;          /*!< DSI Wrapper Configuration Register,                       Address offset: 0x400       */
+  __IO uint32_t WCR;            /*!< DSI Wrapper Control Register,                             Address offset: 0x404       */
+  __IO uint32_t WIER;           /*!< DSI Wrapper Interrupt Enable Register,                    Address offset: 0x408       */
+  __IO uint32_t WISR;           /*!< DSI Wrapper Interrupt and Status Register,                Address offset: 0x40C       */
+  __IO uint32_t WIFCR;          /*!< DSI Wrapper Interrupt Flag Clear Register,                Address offset: 0x410       */
+  uint32_t      RESERVED9;      /*!< Reserved, 0x414                                                                       */
+  __IO uint32_t WPCR[5];        /*!< DSI Wrapper PHY Configuration Register,                   Address offset: 0x418-0x42B */
+  uint32_t      RESERVED10;     /*!< Reserved, 0x42C                                                                       */
+  __IO uint32_t WRPCR;          /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430                 */
+} DSI_TypeDef;
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define RAMITCM_BASE           0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM  */
+#define FLASHITCM_BASE         0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory  accessible over ITCM              */                       
+#define FLASHAXI_BASE          0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */                       
+#define RAMDTCM_BASE           0x20000000U /*!< Base address of : 128KB system data RAM accessible over DTCM                            */
+#define PERIPH_BASE            0x40000000U /*!< Base address of : AHB/ABP Peripherals                                                   */
+#define BKPSRAM_BASE           0x40024000U /*!< Base address of : Backup SRAM(4 KB)                                                     */
+#define QSPI_BASE              0x90000000U /*!< Base address of : QSPI memories  accessible over AXI                                    */
+#define FMC_R_BASE             0xA0000000U /*!< Base address of : FMC Control registers                                                 */
+#define QSPI_R_BASE            0xA0001000U /*!< Base address of : QSPI Control  registers                                               */
+#define SRAM1_BASE             0x20020000U /*!< Base address of : 368KB RAM1 accessible over AXI/AHB                                    */
+#define SRAM2_BASE             0x2007C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB                                     */
+#define FLASH_END              0x081FFFFFU /*!< FLASH end address */
+
+/* Legacy define */
+#define FLASH_BASE     FLASHAXI_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE        PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
+#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400U)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
+#define CAN3_BASE             (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
+#define SPDIFRX_BASE          (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
+#define I2C4_BASE             (APB1PERIPH_BASE + 0x6000U)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
+#define CEC_BASE              (APB1PERIPH_BASE + 0x6C00U)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
+#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)
+#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
+#define SDMMC2_BASE           (APB2PERIPH_BASE + 0x1C00U)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
+#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
+#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
+#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)
+#define SAI2_BASE             (APB2PERIPH_BASE + 0x5C00U)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)
+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004U)
+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024U)
+#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800U)
+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84U)
+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104U)
+#define DSI_BASE              (APB2PERIPH_BASE + 0x6C00U)
+#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x7400U)
+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00U)
+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20U)
+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40U)
+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60U)
+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80U)
+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0U)
+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0U)
+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0U)
+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100U)
+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180U)
+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200U)
+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280U)
+#define MDIOS_BASE            (APB2PERIPH_BASE + 0x7800U)
+/*!< AHB1 peripherals */
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
+#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)
+#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
+#define UID_BASE              0x1FF0F420U                   /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE        0x1FF0F442U                   /*!< FLASH Size register base address */
+#define PACKAGESIZE_BASE      0x1FFF7BF0U                   /*!< Package size register base address */
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
+#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)
+#define ETH_MAC_BASE          (ETH_BASE)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)
+#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)
+/*!< AHB2 peripherals */
+#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
+#define JPEG_BASE           (AHB2PERIPH_BASE + 0x51000U)
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)
+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE               0x40040000U
+#define USB_OTG_FS_PERIPH_BASE               0x50000000U
+
+#define USB_OTG_GLOBAL_BASE                  0x000U
+#define USB_OTG_DEVICE_BASE                  0x800U
+#define USB_OTG_IN_ENDPOINT_BASE             0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
+#define USB_OTG_EP_REG_SIZE                  0x20U
+#define USB_OTG_HOST_BASE                    0x400U
+#define USB_OTG_HOST_PORT_BASE               0x440U
+#define USB_OTG_HOST_CHANNEL_BASE            0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
+#define USB_OTG_PCGCCTL_BASE                 0xE00U
+#define USB_OTG_FIFO_BASE                    0x1000U
+#define USB_OTG_FIFO_SIZE                    0x1000U
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE) 
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
+#define CEC                 ((CEC_TypeDef *) CEC_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define UART7               ((USART_TypeDef *) UART7_BASE)
+#define UART8               ((USART_TypeDef *) UART8_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define USART6              ((USART_TypeDef *) USART6_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
+#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+#define CAN3                ((CAN_TypeDef *) CAN3_BASE)
+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)
+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)
+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
+#define JPEG                ((JPEG_TypeDef *) JPEG_BASE)
+#define DSI                 ((DSI_TypeDef *)DSI_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+  
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for ADC_SR register  ********************/
+#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag                                 */
+#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion                                    */
+#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion                   */
+#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag                          */
+#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag                           */
+#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag                                         */
+
+/*******************  Bit definition for ADC_CR1 register  ********************/
+#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC                             */
+#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable                    */
+#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels               */
+#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion                  */
+#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels               */
+#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels              */
+#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels          */
+#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels           */
+#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution)                           */
+#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
+  
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF                                       */
+#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion                                        */
+#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode                                    */
+#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC)                           */
+#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection                                  */
+#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment                                               */
+#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
+
+/******************  Bit definition for ADC_SMPR1 register  *******************/
+#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
+
+/******************  Bit definition for ADC_SMPR2 register  *******************/
+#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
+
+/******************  Bit definition for ADC_JOFR1 register  *******************/
+#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_JOFR2 register  *******************/
+#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_JOFR3 register  *******************/
+#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_JOFR4 register  *******************/
+#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_SQR1 register  *******************/
+#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
+
+/*******************  Bit definition for ADC_SQR2 register  *******************/
+#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
+
+/*******************  Bit definition for ADC_SQR3 register  *******************/
+#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
+
+/*******************  Bit definition for ADC_JSQR register  *******************/
+#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
+
+/*******************  Bit definition for ADC_JDR1 register  *******************/
+#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR2 register  *******************/
+#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR3 register  *******************/
+#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR4 register  *******************/
+#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
+
+/*******************  Bit definition for ADC_CSR register  ********************/
+#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag               */
+#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion                  */
+#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag        */
+#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag         */
+#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 Overrun flag                       */
+#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag               */
+#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion                  */
+#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag        */
+#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag         */
+#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 Overrun flag                       */
+#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag               */
+#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion                  */
+#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag        */
+#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag         */
+#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 Overrun flag                       */
+
+/* Legacy defines */
+#define  ADC_CSR_DOVR1                       ADC_CSR_OVR1
+#define  ADC_CSR_DOVR2                       ADC_CSR_OVR2
+#define  ADC_CSR_DOVR3                       ADC_CSR_OVR3
+
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
+
+/*******************  Bit definition for ADC_CDR register  ********************/
+#define  ADC_CDR_DATA1                       0x0000FFFFU         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                       0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request            */
+#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request                */
+#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority            */
+#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode          */
+#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission       */
+#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode             */
+#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management      */
+#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset       */
+                                                                           
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define  CAN_MSR_INAK                        0x00000001U        /*!<Initialization Acknowledge  */
+#define  CAN_MSR_SLAK                        0x00000002U        /*!<Sleep Acknowledge           */
+#define  CAN_MSR_ERRI                        0x00000004U        /*!<Error Interrupt             */
+#define  CAN_MSR_WKUI                        0x00000008U        /*!<Wakeup Interrupt            */
+#define  CAN_MSR_SLAKI                       0x00000010U        /*!<Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         0x00000100U        /*!<Transmit Mode               */
+#define  CAN_MSR_RXM                         0x00000200U        /*!<Receive Mode                */
+#define  CAN_MSR_SAMP                        0x00000400U        /*!<Last Sample Point           */
+#define  CAN_MSR_RX                          0x00000800U        /*!<CAN Rx Signal               */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0      */
+#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0     */
+#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0   */
+#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0  */
+#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0      */
+#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1      */
+#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1     */
+#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1   */
+#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1  */
+#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1     */
+#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2      */
+#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2    */
+#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2  */
+#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2     */
+#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code                    */
+
+#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
+#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
+
+#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define  CAN_RF0R_FMP0                       0x00000003U        /*!<FIFO 0 Message Pending        */
+#define  CAN_RF0R_FULL0                      0x00000008U        /*!<FIFO 0 Full                   */
+#define  CAN_RF0R_FOVR0                      0x00000010U        /*!<FIFO 0 Overrun                */
+#define  CAN_RF0R_RFOM0                      0x00000020U        /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define  CAN_RF1R_FMP1                       0x00000003U        /*!<FIFO 1 Message Pending        */
+#define  CAN_RF1R_FULL1                      0x00000008U        /*!<FIFO 1 Full                   */
+#define  CAN_RF1R_FOVR1                      0x00000010U        /*!<FIFO 1 Overrun                */
+#define  CAN_RF1R_RFOM1                      0x00000020U        /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable   */
+#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable              */
+#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable           */
+#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable   */
+#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable              */
+#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable           */
+#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable          */
+#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable          */
+#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable                */
+#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable        */
+#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable                  */
+#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable                 */
+#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable                  */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
+#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
+#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
+
+#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
+#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
+#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
+
+#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler           */
+#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1                */
+#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
+#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
+#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
+#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
+#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2                */
+#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
+#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
+#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
+#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width  */
+#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
+#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
+#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug)        */
+#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode                   */
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
+#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
+#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension                       */
+#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
+#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code     */
+#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp   */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
+#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
+#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension                       */
+#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
+#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code     */
+#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp   */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
+#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
+#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension                       */
+#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier                        */
+#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/  
+#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code      */
+#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time  */
+#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp    */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
+#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension                       */
+#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
+#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
+#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension                       */
+#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier                        */
+#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code   */
+#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define  CAN_FMR_FINIT                       ((uint8_t)0x01U)               /*!<Filter Init Mode */
+#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define  CAN_FM1R_FBM                        0x3FFFU            /*!<Filter Mode */
+#define  CAN_FM1R_FBM0                       0x0001U            /*!<Filter Init Mode bit 0  */
+#define  CAN_FM1R_FBM1                       0x0002U            /*!<Filter Init Mode bit 1  */
+#define  CAN_FM1R_FBM2                       0x0004U            /*!<Filter Init Mode bit 2  */
+#define  CAN_FM1R_FBM3                       0x0008U            /*!<Filter Init Mode bit 3  */
+#define  CAN_FM1R_FBM4                       0x0010U            /*!<Filter Init Mode bit 4  */
+#define  CAN_FM1R_FBM5                       0x0020U            /*!<Filter Init Mode bit 5  */
+#define  CAN_FM1R_FBM6                       0x0040U            /*!<Filter Init Mode bit 6  */
+#define  CAN_FM1R_FBM7                       0x0080U            /*!<Filter Init Mode bit 7  */
+#define  CAN_FM1R_FBM8                       0x0100U            /*!<Filter Init Mode bit 8  */
+#define  CAN_FM1R_FBM9                       0x0200U            /*!<Filter Init Mode bit 9  */
+#define  CAN_FM1R_FBM10                      0x0400U            /*!<Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      0x0800U            /*!<Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      0x1000U            /*!<Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      0x2000U            /*!<Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define  CAN_FS1R_FSC                        0x00003FFFU        /*!<Filter Scale Configuration        */
+#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0  */
+#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1  */
+#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2  */
+#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3  */
+#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4  */
+#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5  */
+#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6  */
+#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7  */
+#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8  */
+#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9  */
+#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define  CAN_FFA1R_FFA                       0x00003FFFU        /*!<Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                      0x00000001U        /*!<Filter FIFO Assignment for Filter 0 */
+#define  CAN_FFA1R_FFA1                      0x00000002U        /*!<Filter FIFO Assignment for Filter 1 */
+#define  CAN_FFA1R_FFA2                      0x00000004U        /*!<Filter FIFO Assignment for Filter 2 */
+#define  CAN_FFA1R_FFA3                      0x00000008U        /*!<Filter FIFO Assignment for Filter 3 */
+#define  CAN_FFA1R_FFA4                      0x00000010U        /*!<Filter FIFO Assignment for Filter 4 */
+#define  CAN_FFA1R_FFA5                      0x00000020U        /*!<Filter FIFO Assignment for Filter 5 */
+#define  CAN_FFA1R_FFA6                      0x00000040U        /*!<Filter FIFO Assignment for Filter 6 */
+#define  CAN_FFA1R_FFA7                      0x00000080U        /*!<Filter FIFO Assignment for Filter 7 */
+#define  CAN_FFA1R_FFA8                      0x00000100U        /*!<Filter FIFO Assignment for Filter 8 */
+#define  CAN_FFA1R_FFA9                      0x00000200U        /*!<Filter FIFO Assignment for Filter 9 */
+#define  CAN_FFA1R_FFA10                     0x00000400U        /*!<Filter FIFO Assignment for Filter 10 */
+#define  CAN_FFA1R_FFA11                     0x00000800U        /*!<Filter FIFO Assignment for Filter 11 */
+#define  CAN_FFA1R_FFA12                     0x00001000U        /*!<Filter FIFO Assignment for Filter 12 */
+#define  CAN_FFA1R_FFA13                     0x00002000U        /*!<Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define  CAN_FA1R_FACT                       0x00003FFFU        /*!<Filter Active    */
+#define  CAN_FA1R_FACT0                      0x00000001U        /*!<Filter 0 Active  */
+#define  CAN_FA1R_FACT1                      0x00000002U        /*!<Filter 1 Active  */
+#define  CAN_FA1R_FACT2                      0x00000004U        /*!<Filter 2 Active  */
+#define  CAN_FA1R_FACT3                      0x00000008U        /*!<Filter 3 Active  */
+#define  CAN_FA1R_FACT4                      0x00000010U        /*!<Filter 4 Active  */
+#define  CAN_FA1R_FACT5                      0x00000020U        /*!<Filter 5 Active  */
+#define  CAN_FA1R_FACT6                      0x00000040U        /*!<Filter 6 Active  */
+#define  CAN_FA1R_FACT7                      0x00000080U        /*!<Filter 7 Active  */
+#define  CAN_FA1R_FACT8                      0x00000100U        /*!<Filter 8 Active  */
+#define  CAN_FA1R_FACT9                      0x00000200U        /*!<Filter 9 Active  */
+#define  CAN_FA1R_FACT10                     0x00000400U        /*!<Filter 10 Active */
+#define  CAN_FA1R_FACT11                     0x00000800U        /*!<Filter 11 Active */
+#define  CAN_FA1R_FACT12                     0x00001000U        /*!<Filter 12 Active */
+#define  CAN_FA1R_FACT13                     0x00002000U        /*!<Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 HDMI-CEC (CEC)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CEC_CR register  *********************/
+#define  CEC_CR_CECEN                        0x00000001U       /*!< CEC Enable                         */
+#define  CEC_CR_TXSOM                        0x00000002U       /*!< CEC Tx Start Of Message            */
+#define  CEC_CR_TXEOM                        0x00000004U       /*!< CEC Tx End Of Message              */
+
+/*******************  Bit definition for CEC_CFGR register  *******************/
+#define  CEC_CFGR_SFT                        0x00000007U       /*!< CEC Signal Free Time               */
+#define  CEC_CFGR_RXTOL                      0x00000008U       /*!< CEC Tolerance                      */
+#define  CEC_CFGR_BRESTP                     0x00000010U       /*!< CEC Rx Stop                        */
+#define  CEC_CFGR_BREGEN                     0x00000020U       /*!< CEC Bit Rising Error generation    */
+#define  CEC_CFGR_LBPEGEN                    0x00000040U       /*!< CEC Long Period Error generation   */
+#define  CEC_CFGR_BRDNOGEN                   0x00000080U       /*!< CEC Broadcast no Error generation  */
+#define  CEC_CFGR_SFTOPT                     0x00000100U       /*!< CEC Signal Free Time optional      */
+#define  CEC_CFGR_OAR                        0x7FFF0000U       /*!< CEC Own Address                    */
+#define  CEC_CFGR_LSTN                       0x80000000U       /*!< CEC Listen mode                    */
+
+/*******************  Bit definition for CEC_TXDR register  *******************/
+#define  CEC_TXDR_TXD                        0x000000FFU       /*!< CEC Tx Data                        */
+
+/*******************  Bit definition for CEC_RXDR register  *******************/
+#define  CEC_TXDR_RXD                        0x000000FFU       /*!< CEC Rx Data                        */
+
+/*******************  Bit definition for CEC_ISR register  ********************/
+#define  CEC_ISR_RXBR                        0x00000001U       /*!< CEC Rx-Byte Received                   */
+#define  CEC_ISR_RXEND                       0x00000002U       /*!< CEC End Of Reception                   */
+#define  CEC_ISR_RXOVR                       0x00000004U       /*!< CEC Rx-Overrun                         */
+#define  CEC_ISR_BRE                         0x00000008U       /*!< CEC Rx Bit Rising Error                */
+#define  CEC_ISR_SBPE                        0x00000010U       /*!< CEC Rx Short Bit period Error          */
+#define  CEC_ISR_LBPE                        0x00000020U       /*!< CEC Rx Long Bit period Error           */
+#define  CEC_ISR_RXACKE                      0x00000040U       /*!< CEC Rx Missing Acknowledge             */
+#define  CEC_ISR_ARBLST                      0x00000080U       /*!< CEC Arbitration Lost                   */
+#define  CEC_ISR_TXBR                        0x00000100U       /*!< CEC Tx Byte Request                    */
+#define  CEC_ISR_TXEND                       0x00000200U       /*!< CEC End of Transmission                */
+#define  CEC_ISR_TXUDR                       0x00000400U       /*!< CEC Tx-Buffer Underrun                 */
+#define  CEC_ISR_TXERR                       0x00000800U       /*!< CEC Tx-Error                           */
+#define  CEC_ISR_TXACKE                      0x00001000U       /*!< CEC Tx Missing Acknowledge             */
+
+/*******************  Bit definition for CEC_IER register  ********************/
+#define  CEC_IER_RXBRIE                      0x00000001U       /*!< CEC Rx-Byte Received IT Enable         */
+#define  CEC_IER_RXENDIE                     0x00000002U       /*!< CEC End Of Reception IT Enable         */
+#define  CEC_IER_RXOVRIE                     0x00000004U       /*!< CEC Rx-Overrun IT Enable               */
+#define  CEC_IER_BREIE                       0x00000008U       /*!< CEC Rx Bit Rising Error IT Enable      */
+#define  CEC_IER_SBPEIE                      0x00000010U       /*!< CEC Rx Short Bit period Error IT Enable*/
+#define  CEC_IER_LBPEIE                      0x00000020U       /*!< CEC Rx Long Bit period Error IT Enable */
+#define  CEC_IER_RXACKEIE                    0x00000040U       /*!< CEC Rx Missing Acknowledge IT Enable   */
+#define  CEC_IER_ARBLSTIE                    0x00000080U       /*!< CEC Arbitration Lost IT Enable         */
+#define  CEC_IER_TXBRIE                      0x00000100U       /*!< CEC Tx Byte Request  IT Enable         */
+#define  CEC_IER_TXENDIE                     0x00000200U       /*!< CEC End of Transmission IT Enable      */
+#define  CEC_IER_TXUDRIE                     0x00000400U       /*!< CEC Tx-Buffer Underrun IT Enable       */
+#define  CEC_IER_TXERRIE                     0x00000800U       /*!< CEC Tx-Error IT Enable                 */
+#define  CEC_IER_TXACKEIE                    0x00001000U       /*!< CEC Tx Missing Acknowledge IT Enable   */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           0xFFFFFFFFU     /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         0x000000FFU     /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        0x00000001U     /*!< RESET the CRC computation unit bit */
+#define  CRC_CR_POLYSIZE                     0x00000018U     /*!< Polynomial size bits               */
+#define  CRC_CR_POLYSIZE_0                   0x00000008U     /*!< Polynomial size bit 0              */
+#define  CRC_CR_POLYSIZE_1                   0x00000010U     /*!< Polynomial size bit 1              */
+#define  CRC_CR_REV_IN                       0x00000060U     /*!< REV_IN Reverse Input Data bits     */
+#define  CRC_CR_REV_IN_0                     0x00000020U     /*!< Bit 0 */
+#define  CRC_CR_REV_IN_1                     0x00000040U     /*!< Bit 1 */
+#define  CRC_CR_REV_OUT                      0x00000080U     /*!< REV_OUT Reverse Output Data bits   */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define  CRC_INIT_INIT                       0xFFFFFFFFU     /*!< Initial CRC value bits         */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define  CRC_POL_POL                         0xFFFFFFFFU     /*!< Coefficients of the polynomial */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CR register  ********************/
+#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable                         */
+#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable          */
+#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable                 */
+#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
+#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
+#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
+#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
+#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
+#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
+#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
+#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
+#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
+#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
+#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable                     */
+#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable  */
+#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable                         */
+#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable          */
+#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable                 */
+#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
+#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
+#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
+#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
+#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
+#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
+#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
+#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
+#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
+#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enable                    */
+#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable */
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital Filter for Sigma Delta Modulators                  */
+/*                                                                            */
+/******************************************************************************/
+
+/****************   DFSDM channel configuration registers  ********************/
+
+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
+#define  DFSDM_CHCFGR1_DFSDMEN                0x80000000U            /*!< Global enable for DFSDM interface */
+#define  DFSDM_CHCFGR1_CKOUTSRC               0x40000000U            /*!< Output serial clock source selection */
+#define  DFSDM_CHCFGR1_CKOUTDIV               0x00FF0000U            /*!< CKOUTDIV[7:0] output serial clock divider */
+#define  DFSDM_CHCFGR1_DATPACK                0x0000C000U            /*!< DATPACK[1:0] Data packing mode */
+#define  DFSDM_CHCFGR1_DATPACK_1              0x00008000U            /*!< Data packing mode, Bit 1 */
+#define  DFSDM_CHCFGR1_DATPACK_0              0x00004000U            /*!< Data packing mode, Bit 0 */
+#define  DFSDM_CHCFGR1_DATMPX                 0x00003000U            /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define  DFSDM_CHCFGR1_DATMPX_1               0x00002000U            /*!< Input data multiplexer for channel y, Bit 1 */
+#define  DFSDM_CHCFGR1_DATMPX_0               0x00001000U            /*!< Input data multiplexer for channel y, Bit 0 */
+#define  DFSDM_CHCFGR1_CHINSEL                0x00000100U            /*!< Serial inputs selection for channel y */
+#define  DFSDM_CHCFGR1_CHEN                   0x00000080U            /*!< Channel y enable */
+#define  DFSDM_CHCFGR1_CKABEN                 0x00000040U            /*!< Clock absence detector enable on channel y */
+#define  DFSDM_CHCFGR1_SCDEN                  0x00000020U            /*!< Short circuit detector enable on channel y */
+#define  DFSDM_CHCFGR1_SPICKSEL               0x0000000CU            /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define  DFSDM_CHCFGR1_SPICKSEL_1             0x00000008U            /*!< SPI clock select for channel y, Bit 1 */
+#define  DFSDM_CHCFGR1_SPICKSEL_0             0x00000004U            /*!< SPI clock select for channel y, Bit 0 */
+#define  DFSDM_CHCFGR1_SITP                   0x00000003U            /*!< SITP[1:0] Serial interface type for channel y */
+#define  DFSDM_CHCFGR1_SITP_1                 0x00000002U            /*!< Serial interface type for channel y, Bit 1 */
+#define  DFSDM_CHCFGR1_SITP_0                 0x00000001U            /*!< Serial interface type for channel y, Bit 0 */
+
+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
+#define  DFSDM_CHCFGR2_OFFSET                 0xFFFFFF00U            /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define  DFSDM_CHCFGR2_DTRBS                  0x000000F8U            /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/
+#define  DFSDM_CHAWSCDR_AWFORD                0x00C00000U            /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define  DFSDM_CHAWSCDR_AWFORD_1              0x00800000U            /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
+#define  DFSDM_CHAWSCDR_AWFORD_0              0x00400000U            /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
+#define  DFSDM_CHAWSCDR_AWFOSR                0x001F0000U            /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define  DFSDM_CHAWSCDR_BKSCD                 0x0000F000U            /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define  DFSDM_CHAWSCDR_SCDT                  0x000000FFU            /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/****************  Bit definition for DFSDM_CHWDATR register *******************/
+#define  DFSDM_CHWDATR_WDATA                  0x0000FFFFU            /*!< WDATA[15:0] Input channel y watchdog data */
+
+/****************  Bit definition for DFSDM_CHDATINR register *****************/
+#define  DFSDM_CHDATINR_INDAT0                0x0000FFFFU            /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define  DFSDM_CHDATINR_INDAT1                0xFFFF0000U            /*!< INDAT0[15:0] Input data for channel y */
+
+/************************   DFSDM module registers  ****************************/
+
+/********************  Bit definition for DFSDM_FLTCR1 register *******************/
+#define  DFSDM_FLTCR1_AWFSEL                  0x40000000U            /*!< Analog watchdog fast mode select */
+#define  DFSDM_FLTCR1_FAST                    0x20000000U            /*!< Fast conversion mode selection */
+#define  DFSDM_FLTCR1_RCH                     0x07000000U            /*!< RCH[2:0] Regular channel selection */
+#define  DFSDM_FLTCR1_RDMAEN                  0x00200000U            /*!< DMA channel enabled to read data for the regular conversion */
+#define  DFSDM_FLTCR1_RSYNC                   0x00080000U            /*!< Launch regular conversion synchronously with DFSDMx */
+#define  DFSDM_FLTCR1_RCONT                   0x00040000U            /*!< Continuous mode selection for regular conversions */
+#define  DFSDM_FLTCR1_RSWSTART                0x00020000U            /*!< Software start of a conversion on the regular channel */
+#define  DFSDM_FLTCR1_JEXTEN                  0x00006000U            /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define  DFSDM_FLTCR1_JEXTEN_1                0x00004000U            /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
+#define  DFSDM_FLTCR1_JEXTEN_0                0x00002000U            /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
+#define  DFSDM_FLTCR1_JEXTSEL                 0x00001F00U            /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
+#define  DFSDM_FLTCR1_JEXTSEL_0               0x00000100U            /*!< Trigger signal selection for launching injected conversions, Bit 0 */
+#define  DFSDM_FLTCR1_JEXTSEL_1               0x00000200U            /*!< Trigger signal selection for launching injected conversions, Bit 1 */
+#define  DFSDM_FLTCR1_JEXTSEL_2               0x00000400U            /*!< Trigger signal selection for launching injected conversions, Bit 2 */
+#define  DFSDM_FLTCR1_JEXTSEL_3               0x00000800U            /*!< Trigger signal selection for launching injected conversions, Bit 3 */
+#define  DFSDM_FLTCR1_JEXTSEL_4               0x00001000U            /*!< Trigger signal selection for launching injected conversions, Bit 4 */
+#define  DFSDM_FLTCR1_JDMAEN                  0x00000020U            /*!< DMA channel enabled to read data for the injected channel group */
+#define  DFSDM_FLTCR1_JSCAN                   0x00000010U            /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define  DFSDM_FLTCR1_JSYNC                   0x00000008U            /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
+#define  DFSDM_FLTCR1_JSWSTART                0x00000002U            /*!< Start the conversion of the injected group of channels */
+#define  DFSDM_FLTCR1_DFEN                    0x00000001U            /*!< DFSDM enable */
+
+/********************  Bit definition for DFSDM_FLTCR2 register *******************/
+#define  DFSDM_FLTCR2_AWDCH                   0x00FF0000U            /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define  DFSDM_FLTCR2_EXCH                    0x0000FF00U            /*!< EXCH[7:0] Extreme detector channel selection */
+#define  DFSDM_FLTCR2_CKABIE                  0x00000040U            /*!< Clock absence interrupt enable */
+#define  DFSDM_FLTCR2_SCDIE                   0x00000020U            /*!< Short circuit detector interrupt enable */
+#define  DFSDM_FLTCR2_AWDIE                   0x00000010U            /*!< Analog watchdog interrupt enable */
+#define  DFSDM_FLTCR2_ROVRIE                  0x00000008U            /*!< Regular data overrun interrupt enable */
+#define  DFSDM_FLTCR2_JOVRIE                  0x00000004U            /*!< Injected data overrun interrupt enable */
+#define  DFSDM_FLTCR2_REOCIE                  0x00000002U            /*!< Regular end of conversion interrupt enable */
+#define  DFSDM_FLTCR2_JEOCIE                  0x00000001U            /*!< Injected end of conversion interrupt enable */
+
+/********************  Bit definition for DFSDM_FLTISR register *******************/
+#define  DFSDM_FLTISR_SCDF                    0xFF000000U            /*!< SCDF[7:0] Short circuit detector flag */
+#define  DFSDM_FLTISR_CKABF                   0x00FF0000U            /*!< CKABF[7:0] Clock absence flag */
+#define  DFSDM_FLTISR_RCIP                    0x00004000U            /*!< Regular conversion in progress status */
+#define  DFSDM_FLTISR_JCIP                    0x00002000U            /*!< Injected conversion in progress status */
+#define  DFSDM_FLTISR_AWDF                    0x00000010U            /*!< Analog watchdog */
+#define  DFSDM_FLTISR_ROVRF                   0x00000008U            /*!< Regular conversion overrun flag */
+#define  DFSDM_FLTISR_JOVRF                   0x00000004U            /*!< Injected conversion overrun flag */
+#define  DFSDM_FLTISR_REOCF                   0x00000002U            /*!< End of regular conversion flag */
+#define  DFSDM_FLTISR_JEOCF                   0x00000001U            /*!< End of injected conversion flag */
+
+/********************  Bit definition for DFSDM_FLTICR register *******************/
+#define  DFSDM_FLTICR_CLRSCSDF                0xFF000000U            /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define  DFSDM_FLTICR_CLRCKABF                0x00FF0000U            /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define  DFSDM_FLTICR_CLRROVRF                0x00000008U            /*!< Clear the regular conversion overrun flag */
+#define  DFSDM_FLTICR_CLRJOVRF                0x00000004U            /*!< Clear the injected conversion overrun flag */
+
+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/
+#define  DFSDM_FLTJCHGR_JCHG                  0x000000FFU            /*!< JCHG[7:0] Injected channel group selection */
+
+/********************  Bit definition for DFSDM_FLTFCR register *******************/
+#define  DFSDM_FLTFCR_FORD                    0xE0000000U            /*!< FORD[2:0] Sinc filter order */
+#define  DFSDM_FLTFCR_FORD_2                  0x80000000U            /*!< Sinc filter order, Bit 2 */
+#define  DFSDM_FLTFCR_FORD_1                  0x40000000U            /*!< Sinc filter order, Bit 1 */
+#define  DFSDM_FLTFCR_FORD_0                  0x20000000U            /*!< Sinc filter order, Bit 0 */
+#define  DFSDM_FLTFCR_FOSR                    0x03FF0000U            /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define  DFSDM_FLTFCR_IOSR                    0x000000FFU            /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/
+#define  DFSDM_FLTJDATAR_JDATA                0xFFFFFF00U            /*!< JDATA[23:0] Injected group conversion data */
+#define  DFSDM_FLTJDATAR_JDATACH              0x00000007U            /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/
+#define  DFSDM_FLTRDATAR_RDATA                0xFFFFFF00U            /*!< RDATA[23:0] Regular channel conversion data */
+#define  DFSDM_FLTRDATAR_RPEND                0x00000010U            /*!< RPEND Regular channel pending data */
+#define  DFSDM_FLTRDATAR_RDATACH              0x00000007U            /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/
+#define  DFSDM_FLTAWHTR_AWHT                  0xFFFFFF00U             /*!< AWHT[23:0] Analog watchdog high threshold */
+#define  DFSDM_FLTAWHTR_BKAWH                 0x0000000FU             /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/
+#define  DFSDM_FLTAWLTR_AWLT                  0xFFFFFF00U             /*!< AWLT[23:0] Analog watchdog low threshold */
+#define  DFSDM_FLTAWLTR_BKAWL                 0x0000000FU             /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/******************  Bit definition for DFSDM_FLTAWSR register ******************/
+#define  DFSDM_FLTAWSR_AWHTF                  0x0000FF00U             /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define  DFSDM_FLTAWSR_AWLTF                  0x000000FFU             /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/******************  Bit definition for DFSDM_FLTAWCFR register *****************/
+#define  DFSDM_FLTAWCFR_CLRAWHTF              0x0000FF00U             /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define  DFSDM_FLTAWCFR_CLRAWLTF              0x000000FFU             /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/
+#define  DFSDM_FLTEXMAX_EXMAX                 0xFFFFFF00U             /*!< EXMAX[23:0] Extreme detector maximum value */
+#define  DFSDM_FLTEXMAX_EXMAXCH               0x00000007U             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/
+#define  DFSDM_FLTEXMIN_EXMIN                 0xFFFFFF00U             /*!< EXMIN[23:0] Extreme detector minimum value */
+#define  DFSDM_FLTEXMIN_EXMINCH               0x00000007U             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/
+#define  DFSDM_FLTCNVTIMR_CNVCNT              0xFFFFFFF0U             /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE                      0x00000001U
+#define DCMI_CR_CM                           0x00000002U
+#define DCMI_CR_CROP                         0x00000004U
+#define DCMI_CR_JPEG                         0x00000008U
+#define DCMI_CR_ESS                          0x00000010U
+#define DCMI_CR_PCKPOL                       0x00000020U
+#define DCMI_CR_HSPOL                        0x00000040U
+#define DCMI_CR_VSPOL                        0x00000080U
+#define DCMI_CR_FCRC_0                       0x00000100U
+#define DCMI_CR_FCRC_1                       0x00000200U
+#define DCMI_CR_EDM_0                        0x00000400U
+#define DCMI_CR_EDM_1                        0x00000800U
+#define DCMI_CR_CRE                          0x00001000U
+#define DCMI_CR_ENABLE                       0x00004000U
+#define DCMI_CR_BSM                          0x00030000U
+#define DCMI_CR_BSM_0                        0x00010000U
+#define DCMI_CR_BSM_1                        0x00020000U
+#define DCMI_CR_OEBS                         0x00040000U
+#define DCMI_CR_LSM                          0x00080000U
+#define DCMI_CR_OELS                         0x00100000U
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC                        0x00000001U
+#define DCMI_SR_VSYNC                        0x00000002U
+#define DCMI_SR_FNE                          0x00000004U
+
+/********************  Bits definition for DCMI_RIS register   ****************/
+#define DCMI_RIS_FRAME_RIS                   0x00000001U
+#define DCMI_RIS_OVR_RIS                     0x00000002U
+#define DCMI_RIS_ERR_RIS                     0x00000004U
+#define DCMI_RIS_VSYNC_RIS                   0x00000008U
+#define DCMI_RIS_LINE_RIS                    0x00000010U
+
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE                    0x00000001U
+#define DCMI_IER_OVR_IE                      0x00000002U
+#define DCMI_IER_ERR_IE                      0x00000004U
+#define DCMI_IER_VSYNC_IE                    0x00000008U
+#define DCMI_IER_LINE_IE                     0x00000010U
+
+
+/********************  Bits definition for DCMI_MIS register  *****************/
+#define DCMI_MIS_FRAME_MIS                   0x00000001U
+#define DCMI_MIS_OVR_MIS                     0x00000002U
+#define DCMI_MIS_ERR_MIS                     0x00000004U
+#define DCMI_MIS_VSYNC_MIS                   0x00000008U
+#define DCMI_MIS_LINE_MIS                    0x00000010U
+
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC                   0x00000001U
+#define DCMI_ICR_OVR_ISC                     0x00000002U
+#define DCMI_ICR_ERR_ISC                     0x00000004U
+#define DCMI_ICR_VSYNC_ISC                   0x00000008U
+#define DCMI_ICR_LINE_ISC                    0x00000010U
+
+
+/********************  Bits definition for DCMI_ESCR register  ******************/
+#define DCMI_ESCR_FSC                        0x000000FFU
+#define DCMI_ESCR_LSC                        0x0000FF00U
+#define DCMI_ESCR_LEC                        0x00FF0000U
+#define DCMI_ESCR_FEC                        0xFF000000U
+
+/********************  Bits definition for DCMI_ESUR register  ******************/
+#define DCMI_ESUR_FSU                        0x000000FFU
+#define DCMI_ESUR_LSU                        0x0000FF00U
+#define DCMI_ESUR_LEU                        0x00FF0000U
+#define DCMI_ESUR_FEU                        0xFF000000U
+
+/********************  Bits definition for DCMI_CWSTRT register  ******************/
+#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
+#define DCMI_CWSTRT_VST                      0x1FFF0000U
+
+/********************  Bits definition for DCMI_CWSIZE register  ******************/
+#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
+#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
+
+/********************  Bits definition for DCMI_DR register  ******************/
+#define DCMI_DR_BYTE0                        0x000000FFU
+#define DCMI_DR_BYTE1                        0x0000FF00U
+#define DCMI_DR_BYTE2                        0x00FF0000U
+#define DCMI_DR_BYTE3                        0xFF000000U
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMA_SxCR register  *****************/ 
+#define DMA_SxCR_CHSEL                       0x1E000000U
+#define DMA_SxCR_CHSEL_0                     0x02000000U
+#define DMA_SxCR_CHSEL_1                     0x04000000U
+#define DMA_SxCR_CHSEL_2                     0x08000000U 
+#define DMA_SxCR_CHSEL_3                     0x10000000U
+#define DMA_SxCR_MBURST                      0x01800000U
+#define DMA_SxCR_MBURST_0                    0x00800000U
+#define DMA_SxCR_MBURST_1                    0x01000000U
+#define DMA_SxCR_PBURST                      0x00600000U
+#define DMA_SxCR_PBURST_0                    0x00200000U
+#define DMA_SxCR_PBURST_1                    0x00400000U
+#define DMA_SxCR_CT                          0x00080000U  
+#define DMA_SxCR_DBM                         0x00040000U
+#define DMA_SxCR_PL                          0x00030000U
+#define DMA_SxCR_PL_0                        0x00010000U
+#define DMA_SxCR_PL_1                        0x00020000U
+#define DMA_SxCR_PINCOS                      0x00008000U
+#define DMA_SxCR_MSIZE                       0x00006000U
+#define DMA_SxCR_MSIZE_0                     0x00002000U
+#define DMA_SxCR_MSIZE_1                     0x00004000U
+#define DMA_SxCR_PSIZE                       0x00001800U
+#define DMA_SxCR_PSIZE_0                     0x00000800U
+#define DMA_SxCR_PSIZE_1                     0x00001000U
+#define DMA_SxCR_MINC                        0x00000400U
+#define DMA_SxCR_PINC                        0x00000200U
+#define DMA_SxCR_CIRC                        0x00000100U
+#define DMA_SxCR_DIR                         0x000000C0U
+#define DMA_SxCR_DIR_0                       0x00000040U
+#define DMA_SxCR_DIR_1                       0x00000080U
+#define DMA_SxCR_PFCTRL                      0x00000020U
+#define DMA_SxCR_TCIE                        0x00000010U
+#define DMA_SxCR_HTIE                        0x00000008U
+#define DMA_SxCR_TEIE                        0x00000004U
+#define DMA_SxCR_DMEIE                       0x00000002U
+#define DMA_SxCR_EN                          0x00000001U
+
+/********************  Bits definition for DMA_SxCNDTR register  **************/
+#define DMA_SxNDT                            0x0000FFFFU
+#define DMA_SxNDT_0                          0x00000001U
+#define DMA_SxNDT_1                          0x00000002U
+#define DMA_SxNDT_2                          0x00000004U
+#define DMA_SxNDT_3                          0x00000008U
+#define DMA_SxNDT_4                          0x00000010U
+#define DMA_SxNDT_5                          0x00000020U
+#define DMA_SxNDT_6                          0x00000040U
+#define DMA_SxNDT_7                          0x00000080U
+#define DMA_SxNDT_8                          0x00000100U
+#define DMA_SxNDT_9                          0x00000200U
+#define DMA_SxNDT_10                         0x00000400U
+#define DMA_SxNDT_11                         0x00000800U
+#define DMA_SxNDT_12                         0x00001000U
+#define DMA_SxNDT_13                         0x00002000U
+#define DMA_SxNDT_14                         0x00004000U
+#define DMA_SxNDT_15                         0x00008000U
+
+/********************  Bits definition for DMA_SxFCR register  ****************/ 
+#define DMA_SxFCR_FEIE                       0x00000080U
+#define DMA_SxFCR_FS                         0x00000038U
+#define DMA_SxFCR_FS_0                       0x00000008U
+#define DMA_SxFCR_FS_1                       0x00000010U
+#define DMA_SxFCR_FS_2                       0x00000020U
+#define DMA_SxFCR_DMDIS                      0x00000004U
+#define DMA_SxFCR_FTH                        0x00000003U
+#define DMA_SxFCR_FTH_0                      0x00000001U
+#define DMA_SxFCR_FTH_1                      0x00000002U
+
+/********************  Bits definition for DMA_LISR register  *****************/ 
+#define DMA_LISR_TCIF3                       0x08000000U
+#define DMA_LISR_HTIF3                       0x04000000U
+#define DMA_LISR_TEIF3                       0x02000000U
+#define DMA_LISR_DMEIF3                      0x01000000U
+#define DMA_LISR_FEIF3                       0x00400000U
+#define DMA_LISR_TCIF2                       0x00200000U
+#define DMA_LISR_HTIF2                       0x00100000U
+#define DMA_LISR_TEIF2                       0x00080000U
+#define DMA_LISR_DMEIF2                      0x00040000U
+#define DMA_LISR_FEIF2                       0x00010000U
+#define DMA_LISR_TCIF1                       0x00000800U
+#define DMA_LISR_HTIF1                       0x00000400U
+#define DMA_LISR_TEIF1                       0x00000200U
+#define DMA_LISR_DMEIF1                      0x00000100U
+#define DMA_LISR_FEIF1                       0x00000040U
+#define DMA_LISR_TCIF0                       0x00000020U
+#define DMA_LISR_HTIF0                       0x00000010U
+#define DMA_LISR_TEIF0                       0x00000008U
+#define DMA_LISR_DMEIF0                      0x00000004U
+#define DMA_LISR_FEIF0                       0x00000001U
+
+/********************  Bits definition for DMA_HISR register  *****************/ 
+#define DMA_HISR_TCIF7                       0x08000000U
+#define DMA_HISR_HTIF7                       0x04000000U
+#define DMA_HISR_TEIF7                       0x02000000U
+#define DMA_HISR_DMEIF7                      0x01000000U
+#define DMA_HISR_FEIF7                       0x00400000U
+#define DMA_HISR_TCIF6                       0x00200000U
+#define DMA_HISR_HTIF6                       0x00100000U
+#define DMA_HISR_TEIF6                       0x00080000U
+#define DMA_HISR_DMEIF6                      0x00040000U
+#define DMA_HISR_FEIF6                       0x00010000U
+#define DMA_HISR_TCIF5                       0x00000800U
+#define DMA_HISR_HTIF5                       0x00000400U
+#define DMA_HISR_TEIF5                       0x00000200U
+#define DMA_HISR_DMEIF5                      0x00000100U
+#define DMA_HISR_FEIF5                       0x00000040U
+#define DMA_HISR_TCIF4                       0x00000020U
+#define DMA_HISR_HTIF4                       0x00000010U
+#define DMA_HISR_TEIF4                       0x00000008U
+#define DMA_HISR_DMEIF4                      0x00000004U
+#define DMA_HISR_FEIF4                       0x00000001U
+
+/********************  Bits definition for DMA_LIFCR register  ****************/ 
+#define DMA_LIFCR_CTCIF3                     0x08000000U
+#define DMA_LIFCR_CHTIF3                     0x04000000U
+#define DMA_LIFCR_CTEIF3                     0x02000000U
+#define DMA_LIFCR_CDMEIF3                    0x01000000U
+#define DMA_LIFCR_CFEIF3                     0x00400000U
+#define DMA_LIFCR_CTCIF2                     0x00200000U
+#define DMA_LIFCR_CHTIF2                     0x00100000U
+#define DMA_LIFCR_CTEIF2                     0x00080000U
+#define DMA_LIFCR_CDMEIF2                    0x00040000U
+#define DMA_LIFCR_CFEIF2                     0x00010000U
+#define DMA_LIFCR_CTCIF1                     0x00000800U
+#define DMA_LIFCR_CHTIF1                     0x00000400U
+#define DMA_LIFCR_CTEIF1                     0x00000200U
+#define DMA_LIFCR_CDMEIF1                    0x00000100U
+#define DMA_LIFCR_CFEIF1                     0x00000040U
+#define DMA_LIFCR_CTCIF0                     0x00000020U
+#define DMA_LIFCR_CHTIF0                     0x00000010U
+#define DMA_LIFCR_CTEIF0                     0x00000008U
+#define DMA_LIFCR_CDMEIF0                    0x00000004U
+#define DMA_LIFCR_CFEIF0                     0x00000001U
+
+/********************  Bits definition for DMA_HIFCR  register  ****************/ 
+#define DMA_HIFCR_CTCIF7                     0x08000000U
+#define DMA_HIFCR_CHTIF7                     0x04000000U
+#define DMA_HIFCR_CTEIF7                     0x02000000U
+#define DMA_HIFCR_CDMEIF7                    0x01000000U
+#define DMA_HIFCR_CFEIF7                     0x00400000U
+#define DMA_HIFCR_CTCIF6                     0x00200000U
+#define DMA_HIFCR_CHTIF6                     0x00100000U
+#define DMA_HIFCR_CTEIF6                     0x00080000U
+#define DMA_HIFCR_CDMEIF6                    0x00040000U
+#define DMA_HIFCR_CFEIF6                     0x00010000U
+#define DMA_HIFCR_CTCIF5                     0x00000800U
+#define DMA_HIFCR_CHTIF5                     0x00000400U
+#define DMA_HIFCR_CTEIF5                     0x00000200U
+#define DMA_HIFCR_CDMEIF5                    0x00000100U
+#define DMA_HIFCR_CFEIF5                     0x00000040U
+#define DMA_HIFCR_CTCIF4                     0x00000020U
+#define DMA_HIFCR_CHTIF4                     0x00000010U
+#define DMA_HIFCR_CTEIF4                     0x00000008U
+#define DMA_HIFCR_CDMEIF4                    0x00000004U
+#define DMA_HIFCR_CFEIF4                     0x00000001U
+
+/******************************************************************************/
+/*                                                                            */
+/*                         AHB Master DMA2D Controller (DMA2D)                */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DMA2D_CR register  ******************/
+
+#define DMA2D_CR_START                     0x00000001U               /*!< Start transfer                          */
+#define DMA2D_CR_SUSP                      0x00000002U               /*!< Suspend transfer                        */
+#define DMA2D_CR_ABORT                     0x00000004U               /*!< Abort transfer                          */
+#define DMA2D_CR_TEIE                      0x00000100U               /*!< Transfer Error Interrupt Enable         */
+#define DMA2D_CR_TCIE                      0x00000200U               /*!< Transfer Complete Interrupt Enable      */
+#define DMA2D_CR_TWIE                      0x00000400U               /*!< Transfer Watermark Interrupt Enable     */
+#define DMA2D_CR_CAEIE                     0x00000800U               /*!< CLUT Access Error Interrupt Enable      */
+#define DMA2D_CR_CTCIE                     0x00001000U               /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE                      0x00002000U               /*!< Configuration Error Interrupt Enable    */
+#define DMA2D_CR_MODE                      0x00030000U               /*!< DMA2D Mode[1:0]                         */
+#define DMA2D_CR_MODE_0                    0x00010000U               /*!< DMA2D Mode bit 0                        */
+#define DMA2D_CR_MODE_1                    0x00020000U               /*!< DMA2D Mode bit 1                        */
+
+/********************  Bit definition for DMA2D_ISR register  *****************/
+
+#define DMA2D_ISR_TEIF                     0x00000001U               /*!< Transfer Error Interrupt Flag         */
+#define DMA2D_ISR_TCIF                     0x00000002U               /*!< Transfer Complete Interrupt Flag      */
+#define DMA2D_ISR_TWIF                     0x00000004U               /*!< Transfer Watermark Interrupt Flag     */
+#define DMA2D_ISR_CAEIF                    0x00000008U               /*!< CLUT Access Error Interrupt Flag      */
+#define DMA2D_ISR_CTCIF                    0x00000010U               /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF                     0x00000020U               /*!< Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_IFCR register  ****************/
+
+#define DMA2D_IFCR_CTEIF                   0x00000001U               /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFCR_CTCIF                   0x00000002U               /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFCR_CTWIF                   0x00000004U               /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFCR_CAECIF                  0x00000008U               /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFCR_CCTCIF                  0x00000010U               /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF                   0x00000020U               /*!< Clears Configuration Error Interrupt Flag    */
+
+/* Legacy defines */
+#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_FGMAR register  ***************/
+
+#define DMA2D_FGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_FGOR register  ****************/
+
+#define DMA2D_FGOR_LO                      0x00003FFFU               /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_BGMAR register  ***************/
+
+#define DMA2D_BGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGOR register  ****************/
+
+#define DMA2D_BGOR_LO                      0x00003FFFU               /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_FGPFCCR register  *************/
+
+#define DMA2D_FGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
+#define DMA2D_FGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
+#define DMA2D_FGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
+#define DMA2D_FGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START                0x00000020U               /*!< Start */
+#define DMA2D_FGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
+#define DMA2D_FGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
+#define DMA2D_FGPFCCR_AI                   0x00100000U               /*!< Foreground Input Alpha Inverted */
+#define DMA2D_FGPFCCR_RBS                  0x00200000U               /*!< Foreground Input Red Blue Swap */
+#define DMA2D_FGPFCCR_ALPHA                0xFF000000U               /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_FGCOLR register  **************/
+
+#define DMA2D_FGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
+#define DMA2D_FGCOLR_RED                   0x00FF0000U               /*!< Red Value */   
+
+/********************  Bit definition for DMA2D_BGPFCCR register  *************/
+
+#define DMA2D_BGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
+#define DMA2D_BGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
+#define DMA2D_BGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
+#define DMA2D_BGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START                0x00000020U               /*!< Start */
+#define DMA2D_BGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
+#define DMA2D_BGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
+#define DMA2D_BGPFCCR_AI                   0x00100000U               /*!< background Input Alpha Inverted */
+#define DMA2D_BGPFCCR_RBS                  0x00200000U               /*!< Background Input Red Blue Swap */
+#define DMA2D_BGPFCCR_ALPHA                0xFF000000U               /*!< background Input Alpha value */
+
+/********************  Bit definition for DMA2D_BGCOLR register  **************/
+
+#define DMA2D_BGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
+#define DMA2D_BGCOLR_RED                   0x00FF0000U               /*!< Red Value */
+
+/********************  Bit definition for DMA2D_FGCMAR register  **************/
+
+#define DMA2D_FGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGCMAR register  **************/
+
+#define DMA2D_BGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OPFCCR register  **************/
+
+#define DMA2D_OPFCCR_CM                    0x00000007U               /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0                  0x00000001U               /*!< Color mode CM bit 0 */
+#define DMA2D_OPFCCR_CM_1                  0x00000002U               /*!< Color mode CM bit 1 */
+#define DMA2D_OPFCCR_CM_2                  0x00000004U               /*!< Color mode CM bit 2 */
+#define DMA2D_OPFCCR_AI                    0x00100000U               /*!< Output Alpha Inverted */
+#define DMA2D_OPFCCR_RBS                   0x00200000U               /*!< Output Red Blue Swap */
+
+/********************  Bit definition for DMA2D_OCOLR register  ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1                 0x000000FFU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1                0x0000FF00U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_1                  0x00FF0000U               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1                0xFF000000U               /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2                 0x0000001FU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2                0x000007E0U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_2                  0x0000F800U               /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3                 0x0000001FU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3                0x000003E0U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_3                  0x00007C00U               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3                0x00008000U               /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4                 0x0000000FU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4                0x000000F0U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_4                  0x00000F00U               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4                0x0000F000U               /*!< Alpha Channel Value */
+
+/********************  Bit definition for DMA2D_OMAR register  ****************/
+
+#define DMA2D_OMAR_MA                      0xFFFFFFFFU               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OOR register  *****************/
+
+#define DMA2D_OOR_LO                       0x00003FFFU               /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_NLR register  *****************/
+
+#define DMA2D_NLR_NL                       0x0000FFFFU               /*!< Number of Lines */
+#define DMA2D_NLR_PL                       0x3FFF0000U               /*!< Pixel per Lines */
+
+/********************  Bit definition for DMA2D_LWR register  *****************/
+
+#define DMA2D_LWR_LW                       0x0000FFFFU               /*!< Line Watermark */
+
+/********************  Bit definition for DMA2D_AMTCR register  ***************/
+
+#define DMA2D_AMTCR_EN                     0x00000001U               /*!< Enable */
+#define DMA2D_AMTCR_DT                     0x0000FF00U               /*!< Dead Time */
+
+
+/********************  Bit definition for DMA2D_FGCLUT register  **************/
+                                                                     
+/********************  Bit definition for DMA2D_BGCLUT register  **************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR23                       0x00800000U        /*!< Interrupt Mask on line 23 */
+#define  EXTI_IMR_MR24                       0x01000000U        /*!< Interrupt Mask on line 24 */
+
+/* Reference Defines */
+#define  EXTI_IMR_IM0                        EXTI_IMR_MR0                     
+#define  EXTI_IMR_IM1                        EXTI_IMR_MR1 
+#define  EXTI_IMR_IM2                        EXTI_IMR_MR2 
+#define  EXTI_IMR_IM3                        EXTI_IMR_MR3 
+#define  EXTI_IMR_IM4                        EXTI_IMR_MR4 
+#define  EXTI_IMR_IM5                        EXTI_IMR_MR5 
+#define  EXTI_IMR_IM6                        EXTI_IMR_MR6 
+#define  EXTI_IMR_IM7                        EXTI_IMR_MR7 
+#define  EXTI_IMR_IM8                        EXTI_IMR_MR8 
+#define  EXTI_IMR_IM9                        EXTI_IMR_MR9 
+#define  EXTI_IMR_IM10                       EXTI_IMR_MR10
+#define  EXTI_IMR_IM11                       EXTI_IMR_MR11
+#define  EXTI_IMR_IM12                       EXTI_IMR_MR12
+#define  EXTI_IMR_IM13                       EXTI_IMR_MR13
+#define  EXTI_IMR_IM14                       EXTI_IMR_MR14
+#define  EXTI_IMR_IM15                       EXTI_IMR_MR15
+#define  EXTI_IMR_IM16                       EXTI_IMR_MR16
+#define  EXTI_IMR_IM17                       EXTI_IMR_MR17
+#define  EXTI_IMR_IM18                       EXTI_IMR_MR18
+#define  EXTI_IMR_IM19                       EXTI_IMR_MR19
+#define  EXTI_IMR_IM20                       EXTI_IMR_MR20
+#define  EXTI_IMR_IM21                       EXTI_IMR_MR21
+#define  EXTI_IMR_IM22                       EXTI_IMR_MR22
+#define  EXTI_IMR_IM23                       EXTI_IMR_MR23
+#define  EXTI_IMR_IM24                       EXTI_IMR_MR24
+
+#define  EXTI_IMR_IM                         0x01FFFFFFU        /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR23                       0x00800000U        /*!< Event Mask on line 23 */
+#define  EXTI_EMR_MR24                       0x01000000U        /*!< Event Mask on line 24 */
+
+/* Reference Defines */
+#define  EXTI_EMR_EM0                        EXTI_EMR_MR0                         
+#define  EXTI_EMR_EM1                        EXTI_EMR_MR1 
+#define  EXTI_EMR_EM2                        EXTI_EMR_MR2 
+#define  EXTI_EMR_EM3                        EXTI_EMR_MR3 
+#define  EXTI_EMR_EM4                        EXTI_EMR_MR4 
+#define  EXTI_EMR_EM5                        EXTI_EMR_MR5 
+#define  EXTI_EMR_EM6                        EXTI_EMR_MR6 
+#define  EXTI_EMR_EM7                        EXTI_EMR_MR7 
+#define  EXTI_EMR_EM8                        EXTI_EMR_MR8 
+#define  EXTI_EMR_EM9                        EXTI_EMR_MR9 
+#define  EXTI_EMR_EM10                       EXTI_EMR_MR10
+#define  EXTI_EMR_EM11                       EXTI_EMR_MR11
+#define  EXTI_EMR_EM12                       EXTI_EMR_MR12
+#define  EXTI_EMR_EM13                       EXTI_EMR_MR13
+#define  EXTI_EMR_EM14                       EXTI_EMR_MR14
+#define  EXTI_EMR_EM15                       EXTI_EMR_MR15
+#define  EXTI_EMR_EM16                       EXTI_EMR_MR16
+#define  EXTI_EMR_EM17                       EXTI_EMR_MR17
+#define  EXTI_EMR_EM18                       EXTI_EMR_MR18
+#define  EXTI_EMR_EM19                       EXTI_EMR_MR19
+#define  EXTI_EMR_EM20                       EXTI_EMR_MR20
+#define  EXTI_EMR_EM21                       EXTI_EMR_MR21
+#define  EXTI_EMR_EM22                       EXTI_EMR_MR22
+#define  EXTI_EMR_EM23                       EXTI_EMR_MR23
+#define  EXTI_EMR_EM24                       EXTI_EMR_MR24
+
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR23                      0x00800000U        /*!< Rising trigger event configuration bit of line 23 */
+#define  EXTI_RTSR_TR24                      0x01000000U        /*!< Rising trigger event configuration bit of line 24 */
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR23                      0x00800000U        /*!< Falling trigger event configuration bit of line 23 */
+#define  EXTI_FTSR_TR24                      0x01000000U        /*!< Falling trigger event configuration bit of line 24 */
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER23                  0x00800000U        /*!< Software Interrupt on line 23 */
+#define  EXTI_SWIER_SWIER24                  0x01000000U        /*!< Software Interrupt on line 24 */
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR23                        0x00800000U        /*!< Pending bit for line 23 */
+#define  EXTI_PR_PR24                        0x01000000U        /*!< Pending bit for line 24 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief FLASH Total Sectors Number
+*/
+#define FLASH_SECTOR_TOTAL  24
+
+/*******************  Bits definition for FLASH_ACR register  *****************/
+#define FLASH_ACR_LATENCY                    0x0000000FU
+#define FLASH_ACR_LATENCY_0WS                0x00000000U
+#define FLASH_ACR_LATENCY_1WS                0x00000001U
+#define FLASH_ACR_LATENCY_2WS                0x00000002U
+#define FLASH_ACR_LATENCY_3WS                0x00000003U
+#define FLASH_ACR_LATENCY_4WS                0x00000004U
+#define FLASH_ACR_LATENCY_5WS                0x00000005U
+#define FLASH_ACR_LATENCY_6WS                0x00000006U
+#define FLASH_ACR_LATENCY_7WS                0x00000007U
+#define FLASH_ACR_LATENCY_8WS                0x00000008U
+#define FLASH_ACR_LATENCY_9WS                0x00000009U
+#define FLASH_ACR_LATENCY_10WS               0x0000000AU
+#define FLASH_ACR_LATENCY_11WS               0x0000000BU
+#define FLASH_ACR_LATENCY_12WS               0x0000000CU
+#define FLASH_ACR_LATENCY_13WS               0x0000000DU
+#define FLASH_ACR_LATENCY_14WS               0x0000000EU
+#define FLASH_ACR_LATENCY_15WS               0x0000000FU
+#define FLASH_ACR_PRFTEN                     0x00000100U
+#define FLASH_ACR_ARTEN                      0x00000200U
+#define FLASH_ACR_ARTRST                     0x00000800U
+
+/*******************  Bits definition for FLASH_SR register  ******************/
+#define FLASH_SR_EOP                         0x00000001U
+#define FLASH_SR_OPERR                       0x00000002U
+#define FLASH_SR_WRPERR                      0x00000010U
+#define FLASH_SR_PGAERR                      0x00000020U
+#define FLASH_SR_PGPERR                      0x00000040U
+#define FLASH_SR_ERSERR                      0x00000080U
+#define FLASH_SR_BSY                         0x00010000U
+
+/*******************  Bits definition for FLASH_CR register  ******************/
+#define FLASH_CR_PG                          0x00000001U
+#define FLASH_CR_SER                         0x00000002U
+#define FLASH_CR_MER                         0x00000004U
+#define FLASH_CR_MER1                        FLASH_CR_MER
+#define FLASH_CR_SNB                         0x000000F8U
+#define FLASH_CR_SNB_0                       0x00000008U
+#define FLASH_CR_SNB_1                       0x00000010U
+#define FLASH_CR_SNB_2                       0x00000020U
+#define FLASH_CR_SNB_3                       0x00000040U
+#define FLASH_CR_SNB_4                       0x00000080U
+#define FLASH_CR_PSIZE                       0x00000300U
+#define FLASH_CR_PSIZE_0                     0x00000100U
+#define FLASH_CR_PSIZE_1                     0x00000200U
+#define FLASH_CR_MER2                        0x00008000U
+#define FLASH_CR_STRT                        0x00010000U
+#define FLASH_CR_EOPIE                       0x01000000U
+#define FLASH_CR_ERRIE                       0x02000000U
+#define FLASH_CR_LOCK                        0x80000000U
+
+/*******************  Bits definition for FLASH_OPTCR register  ***************/
+#define FLASH_OPTCR_OPTLOCK                 0x00000001U
+#define FLASH_OPTCR_OPTSTRT                 0x00000002U
+#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
+#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
+#define FLASH_OPTCR_WWDG_SW                 0x00000010U
+#define FLASH_OPTCR_IWDG_SW                 0x00000020U
+#define FLASH_OPTCR_nRST_STOP               0x00000040U
+#define FLASH_OPTCR_nRST_STDBY              0x00000080U
+#define FLASH_OPTCR_RDP                     0x0000FF00U
+#define FLASH_OPTCR_RDP_0                   0x00000100U
+#define FLASH_OPTCR_RDP_1                   0x00000200U
+#define FLASH_OPTCR_RDP_2                   0x00000400U
+#define FLASH_OPTCR_RDP_3                   0x00000800U
+#define FLASH_OPTCR_RDP_4                   0x00001000U
+#define FLASH_OPTCR_RDP_5                   0x00002000U
+#define FLASH_OPTCR_RDP_6                   0x00004000U
+#define FLASH_OPTCR_RDP_7                   0x00008000U
+#define FLASH_OPTCR_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0                  0x00010000U
+#define FLASH_OPTCR_nWRP_1                  0x00020000U
+#define FLASH_OPTCR_nWRP_2                  0x00040000U
+#define FLASH_OPTCR_nWRP_3                  0x00080000U
+#define FLASH_OPTCR_nWRP_4                  0x00100000U
+#define FLASH_OPTCR_nWRP_5                  0x00200000U
+#define FLASH_OPTCR_nWRP_6                  0x00400000U
+#define FLASH_OPTCR_nWRP_7                  0x00800000U
+#define FLASH_OPTCR_nWRP_8                  0x01000000U
+#define FLASH_OPTCR_nWRP_9                  0x02000000U
+#define FLASH_OPTCR_nWRP_10                 0x04000000U
+#define FLASH_OPTCR_nWRP_11                 0x08000000U
+#define FLASH_OPTCR_nDBOOT                  0x10000000U
+#define FLASH_OPTCR_nDBANK                  0x20000000U
+#define FLASH_OPTCR_IWDG_STDBY              0x40000000U
+#define FLASH_OPTCR_IWDG_STOP               0x80000000U
+
+/*******************  Bits definition for FLASH_OPTCR1 register  ***************/
+#define FLASH_OPTCR1_BOOT_ADD0              0x0000FFFFU
+#define FLASH_OPTCR1_BOOT_ADD1              0xFFFF0000U
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCR1 register  *******************/
+#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
+#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
+#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size             */
+#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
+#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
+#define  FMC_BCR1_WFDIS                     0x00200000U        /*!<Write FIFO Disable         */
+
+/******************  Bit definition for FMC_BCR2 register  *******************/
+#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
+#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
+#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size             */
+#define  FMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BCR3 register  *******************/
+#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
+#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
+#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size             */
+#define  FMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BCR4 register  *******************/
+#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
+#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
+#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size             */
+#define  FMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BTR1 register  ******************/
+#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
+#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
+#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
+#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
+#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
+#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
+#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BTR2 register  *******************/
+#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
+#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
+#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
+#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
+#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
+#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
+#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
+
+/*******************  Bit definition for FMC_BTR3 register  *******************/
+#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
+#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
+#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
+#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
+#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
+#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
+#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BTR4 register  *******************/
+#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
+#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
+#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
+#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
+#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
+#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
+#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR1 register  ******************/
+#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
+#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
+#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
+#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
+#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR2 register  ******************/
+#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
+#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
+#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
+#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
+#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR3 register  ******************/
+#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
+#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
+#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
+#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
+#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR4 register  ******************/
+#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
+#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
+#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
+#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
+#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_PCR register  *******************/
+#define  FMC_PCR_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
+#define  FMC_PCR_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FMC_PCR_PTYP                      0x00000008U        /*!<Memory type                               */
+#define  FMC_PCR_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FMC_PCR_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_PCR_PWID_1                    0x00000020U        /*!<Bit 1 */
+#define  FMC_PCR_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
+#define  FMC_PCR_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define  FMC_PCR_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FMC_PCR_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FMC_PCR_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FMC_PCR_TCLR_3                    0x00001000U        /*!<Bit 3 */
+#define  FMC_PCR_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define  FMC_PCR_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FMC_PCR_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FMC_PCR_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FMC_PCR_TAR_3                     0x00010000U        /*!<Bit 3 */
+#define  FMC_PCR_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
+#define  FMC_PCR_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FMC_PCR_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FMC_PCR_ECCPS_2                   0x00080000U        /*!<Bit 2 */
+
+/*******************  Bit definition for FMC_SR register  *******************/
+#define  FMC_SR_IRS                        0x01U              /*!<Interrupt Rising Edge status                */
+#define  FMC_SR_ILS                        0x02U              /*!<Interrupt Level status                      */
+#define  FMC_SR_IFS                        0x04U              /*!<Interrupt Falling Edge status               */
+#define  FMC_SR_IREN                       0x08U              /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FMC_SR_ILEN                       0x10U              /*!<Interrupt Level detection Enable bit        */
+#define  FMC_SR_IFEN                       0x20U              /*!<Interrupt Falling Edge detection Enable bit */
+#define  FMC_SR_FEMPT                      0x40U              /*!<FIFO empty                                  */
+
+/******************  Bit definition for FMC_PMEM register  ******************/
+#define  FMC_PMEM_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define  FMC_PMEM_MEMSET3_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMSET3_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMSET3_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMSET3_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMSET3_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMSET3_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMSET3_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMSET3_7                0x00000080U        /*!<Bit 7 */
+#define  FMC_PMEM_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define  FMC_PMEM_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
+#define  FMC_PMEM_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define  FMC_PMEM_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
+#define  FMC_PMEM_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define  FMC_PMEM_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_PATT register  ******************/
+#define  FMC_PATT_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define  FMC_PATT_ATTSET3_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PATT_ATTSET3_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PATT_ATTSET3_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PATT_ATTSET3_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PATT_ATTSET3_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PATT_ATTSET3_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PATT_ATTSET3_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PATT_ATTSET3_7                0x00000080U        /*!<Bit 7 */
+#define  FMC_PATT_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define  FMC_PATT_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PATT_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PATT_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PATT_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PATT_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PATT_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PATT_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PATT_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
+#define  FMC_PATT_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define  FMC_PATT_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PATT_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PATT_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PATT_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PATT_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PATT_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PATT_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PATT_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
+#define  FMC_PATT_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define  FMC_PATT_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PATT_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PATT_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PATT_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PATT_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PATT_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PATT_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PATT_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_ECCR register  ******************/
+#define  FMC_ECCR_ECC3                     0xFFFFFFFFU        /*!<ECC result */
+
+/******************  Bit definition for FMC_SDCR1 register  ******************/
+#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
+#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
+#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
+#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
+#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
+#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
+#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
+#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
+#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
+#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
+#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
+#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
+#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
+#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_SDCR2 register  ******************/
+#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
+#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
+#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
+#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
+#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
+#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
+#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
+#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
+#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
+#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
+#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
+#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
+#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_SDTR1 register  ******************/
+#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
+#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
+#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
+#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
+#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
+#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
+#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
+#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
+#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
+#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
+
+/******************  Bit definition for FMC_SDTR2 register  ******************/
+#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
+#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
+#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
+#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
+#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
+#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
+#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
+#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
+#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
+#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
+
+/******************  Bit definition for FMC_SDCMR register  ******************/
+#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
+#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDCMR_MODE_2                   0x00000003U        /*!<Bit 2 */
+#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
+#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
+#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
+#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
+#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
+#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
+#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
+
+/******************  Bit definition for FMC_SDRTR register  ******************/
+#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
+#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
+#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
+
+/******************  Bit definition for FMC_SDSR register  ******************/
+#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
+#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
+#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
+#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
+#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
+#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0                    0x00000003U
+#define GPIO_MODER_MODER0_0                  0x00000001U
+#define GPIO_MODER_MODER0_1                  0x00000002U
+#define GPIO_MODER_MODER1                    0x0000000CU
+#define GPIO_MODER_MODER1_0                  0x00000004U
+#define GPIO_MODER_MODER1_1                  0x00000008U
+#define GPIO_MODER_MODER2                    0x00000030U
+#define GPIO_MODER_MODER2_0                  0x00000010U
+#define GPIO_MODER_MODER2_1                  0x00000020U
+#define GPIO_MODER_MODER3                    0x000000C0U
+#define GPIO_MODER_MODER3_0                  0x00000040U
+#define GPIO_MODER_MODER3_1                  0x00000080U
+#define GPIO_MODER_MODER4                    0x00000300U
+#define GPIO_MODER_MODER4_0                  0x00000100U
+#define GPIO_MODER_MODER4_1                  0x00000200U
+#define GPIO_MODER_MODER5                    0x00000C00U
+#define GPIO_MODER_MODER5_0                  0x00000400U
+#define GPIO_MODER_MODER5_1                  0x00000800U
+#define GPIO_MODER_MODER6                    0x00003000U
+#define GPIO_MODER_MODER6_0                  0x00001000U
+#define GPIO_MODER_MODER6_1                  0x00002000U
+#define GPIO_MODER_MODER7                    0x0000C000U
+#define GPIO_MODER_MODER7_0                  0x00004000U
+#define GPIO_MODER_MODER7_1                  0x00008000U
+#define GPIO_MODER_MODER8                    0x00030000U
+#define GPIO_MODER_MODER8_0                  0x00010000U
+#define GPIO_MODER_MODER8_1                  0x00020000U
+#define GPIO_MODER_MODER9                    0x000C0000U
+#define GPIO_MODER_MODER9_0                  0x00040000U
+#define GPIO_MODER_MODER9_1                  0x00080000U
+#define GPIO_MODER_MODER10                   0x00300000U
+#define GPIO_MODER_MODER10_0                 0x00100000U
+#define GPIO_MODER_MODER10_1                 0x00200000U
+#define GPIO_MODER_MODER11                   0x00C00000U
+#define GPIO_MODER_MODER11_0                 0x00400000U
+#define GPIO_MODER_MODER11_1                 0x00800000U
+#define GPIO_MODER_MODER12                   0x03000000U
+#define GPIO_MODER_MODER12_0                 0x01000000U
+#define GPIO_MODER_MODER12_1                 0x02000000U
+#define GPIO_MODER_MODER13                   0x0C000000U
+#define GPIO_MODER_MODER13_0                 0x04000000U
+#define GPIO_MODER_MODER13_1                 0x08000000U
+#define GPIO_MODER_MODER14                   0x30000000U
+#define GPIO_MODER_MODER14_0                 0x10000000U
+#define GPIO_MODER_MODER14_1                 0x20000000U
+#define GPIO_MODER_MODER15                   0xC0000000U
+#define GPIO_MODER_MODER15_0                 0x40000000U
+#define GPIO_MODER_MODER15_1                 0x80000000U
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT_0                     0x00000001U
+#define GPIO_OTYPER_OT_1                     0x00000002U
+#define GPIO_OTYPER_OT_2                     0x00000004U
+#define GPIO_OTYPER_OT_3                     0x00000008U
+#define GPIO_OTYPER_OT_4                     0x00000010U
+#define GPIO_OTYPER_OT_5                     0x00000020U
+#define GPIO_OTYPER_OT_6                     0x00000040U
+#define GPIO_OTYPER_OT_7                     0x00000080U
+#define GPIO_OTYPER_OT_8                     0x00000100U
+#define GPIO_OTYPER_OT_9                     0x00000200U
+#define GPIO_OTYPER_OT_10                    0x00000400U
+#define GPIO_OTYPER_OT_11                    0x00000800U
+#define GPIO_OTYPER_OT_12                    0x00001000U
+#define GPIO_OTYPER_OT_13                    0x00002000U
+#define GPIO_OTYPER_OT_14                    0x00004000U
+#define GPIO_OTYPER_OT_15                    0x00008000U
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
+#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
+#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
+#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
+#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
+#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
+#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
+#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
+#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
+#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
+#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
+#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
+#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
+#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
+#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
+#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPDR0                    0x00000003U
+#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
+#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
+#define GPIO_PUPDR_PUPDR1                    0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
+#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
+#define GPIO_PUPDR_PUPDR2                    0x00000030U
+#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
+#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
+#define GPIO_PUPDR_PUPDR3                    0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
+#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
+#define GPIO_PUPDR_PUPDR4                    0x00000300U
+#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
+#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
+#define GPIO_PUPDR_PUPDR5                    0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
+#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
+#define GPIO_PUPDR_PUPDR6                    0x00003000U
+#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
+#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
+#define GPIO_PUPDR_PUPDR7                    0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
+#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
+#define GPIO_PUPDR_PUPDR8                    0x00030000U
+#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
+#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
+#define GPIO_PUPDR_PUPDR9                    0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
+#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
+#define GPIO_PUPDR_PUPDR10                   0x00300000U
+#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
+#define GPIO_PUPDR_PUPDR11                   0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
+#define GPIO_PUPDR_PUPDR12                   0x03000000U
+#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
+#define GPIO_PUPDR_PUPDR13                   0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
+#define GPIO_PUPDR_PUPDR14                   0x30000000U
+#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
+#define GPIO_PUPDR_PUPDR15                   0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_IDR_0                       0x00000001U
+#define GPIO_IDR_IDR_1                       0x00000002U
+#define GPIO_IDR_IDR_2                       0x00000004U
+#define GPIO_IDR_IDR_3                       0x00000008U
+#define GPIO_IDR_IDR_4                       0x00000010U
+#define GPIO_IDR_IDR_5                       0x00000020U
+#define GPIO_IDR_IDR_6                       0x00000040U
+#define GPIO_IDR_IDR_7                       0x00000080U
+#define GPIO_IDR_IDR_8                       0x00000100U
+#define GPIO_IDR_IDR_9                       0x00000200U
+#define GPIO_IDR_IDR_10                      0x00000400U
+#define GPIO_IDR_IDR_11                      0x00000800U
+#define GPIO_IDR_IDR_12                      0x00001000U
+#define GPIO_IDR_IDR_13                      0x00002000U
+#define GPIO_IDR_IDR_14                      0x00004000U
+#define GPIO_IDR_IDR_15                      0x00008000U
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_ODR_0                       0x00000001U
+#define GPIO_ODR_ODR_1                       0x00000002U
+#define GPIO_ODR_ODR_2                       0x00000004U
+#define GPIO_ODR_ODR_3                       0x00000008U
+#define GPIO_ODR_ODR_4                       0x00000010U
+#define GPIO_ODR_ODR_5                       0x00000020U
+#define GPIO_ODR_ODR_6                       0x00000040U
+#define GPIO_ODR_ODR_7                       0x00000080U
+#define GPIO_ODR_ODR_8                       0x00000100U
+#define GPIO_ODR_ODR_9                       0x00000200U
+#define GPIO_ODR_ODR_10                      0x00000400U
+#define GPIO_ODR_ODR_11                      0x00000800U
+#define GPIO_ODR_ODR_12                      0x00001000U
+#define GPIO_ODR_ODR_13                      0x00002000U
+#define GPIO_ODR_ODR_14                      0x00004000U
+#define GPIO_ODR_ODR_15                      0x00008000U
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS_0                       0x00000001U
+#define GPIO_BSRR_BS_1                       0x00000002U
+#define GPIO_BSRR_BS_2                       0x00000004U
+#define GPIO_BSRR_BS_3                       0x00000008U
+#define GPIO_BSRR_BS_4                       0x00000010U
+#define GPIO_BSRR_BS_5                       0x00000020U
+#define GPIO_BSRR_BS_6                       0x00000040U
+#define GPIO_BSRR_BS_7                       0x00000080U
+#define GPIO_BSRR_BS_8                       0x00000100U
+#define GPIO_BSRR_BS_9                       0x00000200U
+#define GPIO_BSRR_BS_10                      0x00000400U
+#define GPIO_BSRR_BS_11                      0x00000800U
+#define GPIO_BSRR_BS_12                      0x00001000U
+#define GPIO_BSRR_BS_13                      0x00002000U
+#define GPIO_BSRR_BS_14                      0x00004000U
+#define GPIO_BSRR_BS_15                      0x00008000U
+#define GPIO_BSRR_BR_0                       0x00010000U
+#define GPIO_BSRR_BR_1                       0x00020000U
+#define GPIO_BSRR_BR_2                       0x00040000U
+#define GPIO_BSRR_BR_3                       0x00080000U
+#define GPIO_BSRR_BR_4                       0x00100000U
+#define GPIO_BSRR_BR_5                       0x00200000U
+#define GPIO_BSRR_BR_6                       0x00400000U
+#define GPIO_BSRR_BR_7                       0x00800000U
+#define GPIO_BSRR_BR_8                       0x01000000U
+#define GPIO_BSRR_BR_9                       0x02000000U
+#define GPIO_BSRR_BR_10                      0x04000000U
+#define GPIO_BSRR_BR_11                      0x08000000U
+#define GPIO_BSRR_BR_12                      0x10000000U
+#define GPIO_BSRR_BR_13                      0x20000000U
+#define GPIO_BSRR_BR_14                      0x40000000U
+#define GPIO_BSRR_BR_15                      0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0                       0x00000001U
+#define GPIO_LCKR_LCK1                       0x00000002U
+#define GPIO_LCKR_LCK2                       0x00000004U
+#define GPIO_LCKR_LCK3                       0x00000008U
+#define GPIO_LCKR_LCK4                       0x00000010U
+#define GPIO_LCKR_LCK5                       0x00000020U
+#define GPIO_LCKR_LCK6                       0x00000040U
+#define GPIO_LCKR_LCK7                       0x00000080U
+#define GPIO_LCKR_LCK8                       0x00000100U
+#define GPIO_LCKR_LCK9                       0x00000200U
+#define GPIO_LCKR_LCK10                      0x00000400U
+#define GPIO_LCKR_LCK11                      0x00000800U
+#define GPIO_LCKR_LCK12                      0x00001000U
+#define GPIO_LCKR_LCK13                      0x00002000U
+#define GPIO_LCKR_LCK14                      0x00004000U
+#define GPIO_LCKR_LCK15                      0x00008000U
+#define GPIO_LCKR_LCKK                       0x00010000U
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define  I2C_CR1_PE                          0x00000001U        /*!< Peripheral enable                   */
+#define  I2C_CR1_TXIE                        0x00000002U        /*!< TX interrupt enable                 */
+#define  I2C_CR1_RXIE                        0x00000004U        /*!< RX interrupt enable                 */
+#define  I2C_CR1_ADDRIE                      0x00000008U        /*!< Address match interrupt enable      */
+#define  I2C_CR1_NACKIE                      0x00000010U        /*!< NACK received interrupt enable      */
+#define  I2C_CR1_STOPIE                      0x00000020U        /*!< STOP detection interrupt enable     */
+#define  I2C_CR1_TCIE                        0x00000040U        /*!< Transfer complete interrupt enable  */
+#define  I2C_CR1_ERRIE                       0x00000080U        /*!< Errors interrupt enable             */
+#define  I2C_CR1_DNF                         0x00000F00U        /*!< Digital noise filter                */
+#define  I2C_CR1_ANFOFF                      0x00001000U        /*!< Analog noise filter OFF             */
+#define  I2C_CR1_TXDMAEN                     0x00004000U        /*!< DMA transmission requests enable    */
+#define  I2C_CR1_RXDMAEN                     0x00008000U        /*!< DMA reception requests enable       */
+#define  I2C_CR1_SBC                         0x00010000U        /*!< Slave byte control                  */
+#define  I2C_CR1_NOSTRETCH                   0x00020000U        /*!< Clock stretching disable            */
+#define  I2C_CR1_GCEN                        0x00080000U        /*!< General call enable                 */
+#define  I2C_CR1_SMBHEN                      0x00100000U        /*!< SMBus host address enable           */
+#define  I2C_CR1_SMBDEN                      0x00200000U        /*!< SMBus device default address enable */
+#define  I2C_CR1_ALERTEN                     0x00400000U        /*!< SMBus alert enable                  */
+#define  I2C_CR1_PECEN                       0x00800000U        /*!< PEC enable                          */
+
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_SADD                        0x000003FFU        /*!< Slave address (master mode)                             */
+#define  I2C_CR2_RD_WRN                      0x00000400U        /*!< Transfer direction (master mode)                        */
+#define  I2C_CR2_ADD10                       0x00000800U        /*!< 10-bit addressing mode (master mode)                    */
+#define  I2C_CR2_HEAD10R                     0x00001000U        /*!< 10-bit address header only read direction (master mode) */
+#define  I2C_CR2_START                       0x00002000U        /*!< START generation                                        */
+#define  I2C_CR2_STOP                        0x00004000U        /*!< STOP generation (master mode)                           */
+#define  I2C_CR2_NACK                        0x00008000U        /*!< NACK generation (slave mode)                            */
+#define  I2C_CR2_NBYTES                      0x00FF0000U        /*!< Number of bytes                                         */
+#define  I2C_CR2_RELOAD                      0x01000000U        /*!< NBYTES reload mode                                      */
+#define  I2C_CR2_AUTOEND                     0x02000000U        /*!< Automatic end mode (master mode)                        */
+#define  I2C_CR2_PECBYTE                     0x04000000U        /*!< Packet error checking byte                              */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define  I2C_OAR1_OA1                        0x000003FFU        /*!< Interface own address 1   */
+#define  I2C_OAR1_OA1MODE                    0x00000400U        /*!< Own address 1 10-bit mode */
+#define  I2C_OAR1_OA1EN                      0x00008000U        /*!< Own address 1 enable      */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define  I2C_OAR2_OA2                        0x000000FEU        /*!< Interface own address 2 */
+#define  I2C_OAR2_OA2MSK                     0x00000700U        /*!< Own address 2 masks     */
+#define  I2C_OAR2_OA2NOMASK                  0x00000000U        /*!< No mask */
+#define  I2C_OAR2_OA2MASK01                  0x00000100U        /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define  I2C_OAR2_OA2MASK02                  0x00000200U        /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define  I2C_OAR2_OA2MASK03                  0x00000300U        /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define  I2C_OAR2_OA2MASK04                  0x00000400U        /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define  I2C_OAR2_OA2MASK05                  0x00000500U        /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define  I2C_OAR2_OA2MASK06                  0x00000600U        /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define  I2C_OAR2_OA2MASK07                  0x00000700U        /*!< OA2[7:1] is masked, No comparison is done */
+#define  I2C_OAR2_OA2EN                      0x00008000U        /*!< Own address 2 enable    */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define  I2C_TIMINGR_SCLL                    0x000000FFU        /*!< SCL low period (master mode)  */
+#define  I2C_TIMINGR_SCLH                    0x0000FF00U        /*!< SCL high period (master mode) */
+#define  I2C_TIMINGR_SDADEL                  0x000F0000U        /*!< Data hold time                */
+#define  I2C_TIMINGR_SCLDEL                  0x00F00000U        /*!< Data setup time               */
+#define  I2C_TIMINGR_PRESC                   0xF0000000U        /*!< Timings prescaler             */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define  I2C_TIMEOUTR_TIMEOUTA               0x00000FFFU        /*!< Bus timeout A                 */
+#define  I2C_TIMEOUTR_TIDLE                  0x00001000U        /*!< Idle clock timeout detection  */
+#define  I2C_TIMEOUTR_TIMOUTEN               0x00008000U        /*!< Clock timeout enable          */
+#define  I2C_TIMEOUTR_TIMEOUTB               0x0FFF0000U        /*!< Bus timeout B                 */
+#define  I2C_TIMEOUTR_TEXTEN                 0x80000000U        /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define  I2C_ISR_TXE                         0x00000001U        /*!< Transmit data register empty    */
+#define  I2C_ISR_TXIS                        0x00000002U        /*!< Transmit interrupt status       */
+#define  I2C_ISR_RXNE                        0x00000004U        /*!< Receive data register not empty */
+#define  I2C_ISR_ADDR                        0x00000008U        /*!< Address matched (slave mode)    */
+#define  I2C_ISR_NACKF                       0x00000010U        /*!< NACK received flag              */
+#define  I2C_ISR_STOPF                       0x00000020U        /*!< STOP detection flag             */
+#define  I2C_ISR_TC                          0x00000040U        /*!< Transfer complete (master mode) */
+#define  I2C_ISR_TCR                         0x00000080U        /*!< Transfer complete reload        */
+#define  I2C_ISR_BERR                        0x00000100U        /*!< Bus error                       */
+#define  I2C_ISR_ARLO                        0x00000200U        /*!< Arbitration lost                */
+#define  I2C_ISR_OVR                         0x00000400U        /*!< Overrun/Underrun                */
+#define  I2C_ISR_PECERR                      0x00000800U        /*!< PEC error in reception          */
+#define  I2C_ISR_TIMEOUT                     0x00001000U        /*!< Timeout or Tlow detection flag  */
+#define  I2C_ISR_ALERT                       0x00002000U        /*!< SMBus alert                     */
+#define  I2C_ISR_BUSY                        0x00008000U        /*!< Bus busy                        */
+#define  I2C_ISR_DIR                         0x00010000U        /*!< Transfer direction (slave mode) */
+#define  I2C_ISR_ADDCODE                     0x00FE0000U        /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define  I2C_ICR_ADDRCF                      0x00000008U        /*!< Address matched clear flag      */
+#define  I2C_ICR_NACKCF                      0x00000010U        /*!< NACK clear flag                 */
+#define  I2C_ICR_STOPCF                      0x00000020U        /*!< STOP detection clear flag       */
+#define  I2C_ICR_BERRCF                      0x00000100U        /*!< Bus error clear flag            */
+#define  I2C_ICR_ARLOCF                      0x00000200U        /*!< Arbitration lost clear flag     */
+#define  I2C_ICR_OVRCF                       0x00000400U        /*!< Overrun/Underrun clear flag     */
+#define  I2C_ICR_PECCF                       0x00000800U        /*!< PAC error clear flag            */
+#define  I2C_ICR_TIMOUTCF                    0x00001000U        /*!< Timeout clear flag              */
+#define  I2C_ICR_ALERTCF                     0x00002000U        /*!< Alert clear flag                */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define  I2C_PECR_PEC                        0x000000FFU        /*!< PEC register        */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define  I2C_RXDR_RXDATA                     0x000000FFU        /*!< 8-bit receive data  */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define  I2C_TXDR_TXDATA                     0x000000FFU        /*!< 8-bit transmit data */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         0x01U               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         0x02U               /*!< Watchdog counter reload value update */
+#define  IWDG_SR_WVU                         0x04U               /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_WINR_WIN                       0x0FFFU             /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      LCD-TFT Display Controller (LTDC)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for LTDC_SSCR register  *****************/
+
+#define LTDC_SSCR_VSH                       0x000007FFU              /*!< Vertical Synchronization Height  */
+#define LTDC_SSCR_HSW                       0x0FFF0000U              /*!< Horizontal Synchronization Width */
+
+/********************  Bit definition for LTDC_BPCR register  *****************/
+
+#define LTDC_BPCR_AVBP                      0x000007FFU              /*!< Accumulated Vertical Back Porch   */
+#define LTDC_BPCR_AHBP                      0x0FFF0000U              /*!< Accumulated Horizontal Back Porch */
+
+/********************  Bit definition for LTDC_AWCR register  *****************/
+
+#define LTDC_AWCR_AAH                       0x000007FFU              /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW                       0x0FFF0000U              /*!< Accumulated Active Width */
+
+/********************  Bit definition for LTDC_TWCR register  *****************/
+
+#define LTDC_TWCR_TOTALH                    0x000007FFU              /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW                    0x0FFF0000U              /*!< Total Width */
+
+/********************  Bit definition for LTDC_GCR register  ******************/
+
+#define LTDC_GCR_LTDCEN                     0x00000001U              /*!< LCD-TFT controller enable bit       */
+#define LTDC_GCR_DBW                        0x00000070U              /*!< Dither Blue Width                   */
+#define LTDC_GCR_DGW                        0x00000700U              /*!< Dither Green Width                  */
+#define LTDC_GCR_DRW                        0x00007000U              /*!< Dither Red Width                    */
+#define LTDC_GCR_DEN                        0x00010000U              /*!< Dither Enable                       */
+#define LTDC_GCR_PCPOL                      0x10000000U              /*!< Pixel Clock Polarity                */
+#define LTDC_GCR_DEPOL                      0x20000000U              /*!< Data Enable Polarity                */
+#define LTDC_GCR_VSPOL                      0x40000000U              /*!< Vertical Synchronization Polarity   */
+#define LTDC_GCR_HSPOL                      0x80000000U              /*!< Horizontal Synchronization Polarity */
+
+
+/********************  Bit definition for LTDC_SRCR register  *****************/
+
+#define LTDC_SRCR_IMR                      0x00000001U               /*!< Immediate Reload         */
+#define LTDC_SRCR_VBR                      0x00000002U               /*!< Vertical Blanking Reload */
+
+/********************  Bit definition for LTDC_BCCR register  *****************/
+
+#define LTDC_BCCR_BCBLUE                    0x000000FFU              /*!< Background Blue value  */
+#define LTDC_BCCR_BCGREEN                   0x0000FF00U              /*!< Background Green value */
+#define LTDC_BCCR_BCRED                     0x00FF0000U              /*!< Background Red value   */
+
+/********************  Bit definition for LTDC_IER register  ******************/
+
+#define LTDC_IER_LIE                        0x00000001U              /*!< Line Interrupt Enable            */
+#define LTDC_IER_FUIE                       0x00000002U              /*!< FIFO Underrun Interrupt Enable   */
+#define LTDC_IER_TERRIE                     0x00000004U              /*!< Transfer Error Interrupt Enable  */
+#define LTDC_IER_RRIE                       0x00000008U              /*!< Register Reload interrupt enable */
+
+/********************  Bit definition for LTDC_ISR register  ******************/
+
+#define LTDC_ISR_LIF                        0x00000001U              /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF                       0x00000002U              /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF                     0x00000004U              /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF                       0x00000008U              /*!< Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_ICR register  ******************/
+
+#define LTDC_ICR_CLIF                       0x00000001U              /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF                      0x00000002U              /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF                    0x00000004U              /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF                      0x00000008U              /*!< Clears Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_LIPCR register  ****************/
+
+#define LTDC_LIPCR_LIPOS                    0x000007FFU              /*!< Line Interrupt Position */
+
+/********************  Bit definition for LTDC_CPSR register  *****************/
+
+#define LTDC_CPSR_CYPOS                     0x0000FFFFU              /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS                     0xFFFF0000U              /*!< Current X Position */
+
+/********************  Bit definition for LTDC_CDSR register  *****************/
+
+#define LTDC_CDSR_VDES                      0x00000001U              /*!< Vertical Data Enable Status       */
+#define LTDC_CDSR_HDES                      0x00000002U              /*!< Horizontal Data Enable Status     */
+#define LTDC_CDSR_VSYNCS                    0x00000004U              /*!< Vertical Synchronization Status   */
+#define LTDC_CDSR_HSYNCS                    0x00000008U              /*!< Horizontal Synchronization Status */
+
+/********************  Bit definition for LTDC_LxCR register  *****************/
+
+#define LTDC_LxCR_LEN                       0x00000001U              /*!< Layer Enable              */
+#define LTDC_LxCR_COLKEN                    0x00000002U              /*!< Color Keying Enable       */
+#define LTDC_LxCR_CLUTEN                    0x00000010U              /*!< Color Lockup Table Enable */
+
+/********************  Bit definition for LTDC_LxWHPCR register  **************/
+
+#define LTDC_LxWHPCR_WHSTPOS                0x00000FFFU              /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS                0xFFFF0000U              /*!< Window Horizontal Stop Position  */
+
+/********************  Bit definition for LTDC_LxWVPCR register  **************/
+
+#define LTDC_LxWVPCR_WVSTPOS                0x00000FFFU              /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS                0xFFFF0000U              /*!< Window Vertical Stop Position  */
+
+/********************  Bit definition for LTDC_LxCKCR register  ***************/
+
+#define LTDC_LxCKCR_CKBLUE                  0x000000FFU              /*!< Color Key Blue value  */
+#define LTDC_LxCKCR_CKGREEN                 0x0000FF00U              /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED                   0x00FF0000U              /*!< Color Key Red value   */
+
+/********************  Bit definition for LTDC_LxPFCR register  ***************/
+
+#define LTDC_LxPFCR_PF                      0x00000007U              /*!< Pixel Format */
+
+/********************  Bit definition for LTDC_LxCACR register  ***************/
+
+#define LTDC_LxCACR_CONSTA                  0x000000FFU              /*!< Constant Alpha */
+
+/********************  Bit definition for LTDC_LxDCCR register  ***************/
+
+#define LTDC_LxDCCR_DCBLUE                  0x000000FFU              /*!< Default Color Blue  */
+#define LTDC_LxDCCR_DCGREEN                 0x0000FF00U              /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED                   0x00FF0000U              /*!< Default Color Red   */
+#define LTDC_LxDCCR_DCALPHA                 0xFF000000U              /*!< Default Color Alpha */
+                                
+/********************  Bit definition for LTDC_LxBFCR register  ***************/
+
+#define LTDC_LxBFCR_BF2                     0x00000007U              /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1                     0x00000700U              /*!< Blending Factor 1 */
+
+/********************  Bit definition for LTDC_LxCFBAR register  **************/
+
+#define LTDC_LxCFBAR_CFBADD                 0xFFFFFFFFU              /*!< Color Frame Buffer Start Address */
+
+/********************  Bit definition for LTDC_LxCFBLR register  **************/
+
+#define LTDC_LxCFBLR_CFBLL                  0x00001FFFU              /*!< Color Frame Buffer Line Length    */
+#define LTDC_LxCFBLR_CFBP                   0x1FFF0000U              /*!< Color Frame Buffer Pitch in bytes */
+
+/********************  Bit definition for LTDC_LxCFBLNR register  *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR               0x000007FFU              /*!< Frame Buffer Line Number */
+
+/********************  Bit definition for LTDC_LxCLUTWR register  *************/
+
+#define LTDC_LxCLUTWR_BLUE                  0x000000FFU              /*!< Blue value   */
+#define LTDC_LxCLUTWR_GREEN                 0x0000FF00U              /*!< Green value  */
+#define LTDC_LxCLUTWR_RED                   0x00FF0000U              /*!< Red value    */
+#define LTDC_LxCLUTWR_CLUTADD               0xFF000000U              /*!< CLUT address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for PWR_CR1 register  ********************/
+#define  PWR_CR1_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR1_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
+#define  PWR_CR1_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
+#define  PWR_CR1_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
+#define  PWR_CR1_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR1_PLS_0                        0x00000020U     /*!< Bit 0 */
+#define  PWR_CR1_PLS_1                        0x00000040U     /*!< Bit 1 */
+#define  PWR_CR1_PLS_2                        0x00000080U     /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define  PWR_CR1_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
+#define  PWR_CR1_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
+#define  PWR_CR1_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
+#define  PWR_CR1_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
+#define  PWR_CR1_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
+#define  PWR_CR1_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
+#define  PWR_CR1_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
+#define  PWR_CR1_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
+#define  PWR_CR1_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
+#define  PWR_CR1_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
+#define  PWR_CR1_LPUDS                        0x00000400U     /*!< Low-power regulator in deepsleep under-drive mode          */
+#define  PWR_CR1_MRUDS                        0x00000800U     /*!< Main regulator in deepsleep under-drive mode               */
+#define  PWR_CR1_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */ 
+#define  PWR_CR1_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define  PWR_CR1_VOS_0                        0x00004000U     /*!< Bit 0 */
+#define  PWR_CR1_VOS_1                        0x00008000U     /*!< Bit 1 */
+#define  PWR_CR1_ODEN                         0x00010000U     /*!< Over Drive enable                   */
+#define  PWR_CR1_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled           */
+#define  PWR_CR1_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode     */
+#define  PWR_CR1_UDEN_0                       0x00040000U     /*!< Bit 0                               */
+#define  PWR_CR1_UDEN_1                       0x00080000U     /*!< Bit 1                               */
+
+/*******************  Bit definition for PWR_CSR1 register  ********************/
+#define  PWR_CSR1_WUIF                        0x00000001U     /*!< Wake up internal Flag                            */
+#define  PWR_CSR1_SBF                         0x00000002U     /*!< Standby Flag                                     */
+#define  PWR_CSR1_PVDO                        0x00000004U     /*!< PVD Output                                       */
+#define  PWR_CSR1_BRR                         0x00000008U     /*!< Backup regulator ready                           */
+#define  PWR_CSR1_EIWUP                       0x00000100U     /*!< Enable internal wakeup                           */
+#define  PWR_CSR1_BRE                         0x00000200U     /*!< Backup regulator enable                          */
+#define  PWR_CSR1_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
+#define  PWR_CSR1_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
+#define  PWR_CSR1_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
+#define  PWR_CSR1_UDRDY                       0x000C0000U     /*!< Under Drive ready                                */
+
+
+/********************  Bit definition for PWR_CR2 register  ********************/
+#define  PWR_CR2_CWUPF1                         0x00000001U     /*!< Clear Wakeup Pin Flag for PA0      */
+#define  PWR_CR2_CWUPF2                         0x00000002U     /*!< Clear Wakeup Pin Flag for PA2      */
+#define  PWR_CR2_CWUPF3                         0x00000004U     /*!< Clear Wakeup Pin Flag for PC1      */
+#define  PWR_CR2_CWUPF4                         0x00000008U     /*!< Clear Wakeup Pin Flag for PC13     */
+#define  PWR_CR2_CWUPF5                         0x00000010U     /*!< Clear Wakeup Pin Flag for PI8      */
+#define  PWR_CR2_CWUPF6                         0x00000020U     /*!< Clear Wakeup Pin Flag for PI11     */
+#define  PWR_CR2_WUPP1                          0x00000100U     /*!< Wakeup Pin Polarity bit for PA0    */
+#define  PWR_CR2_WUPP2                          0x00000200U     /*!< Wakeup Pin Polarity bit for PA2    */
+#define  PWR_CR2_WUPP3                          0x00000400U     /*!< Wakeup Pin Polarity bit for PC1    */
+#define  PWR_CR2_WUPP4                          0x00000800U     /*!< Wakeup Pin Polarity bit for PC13   */
+#define  PWR_CR2_WUPP5                          0x00001000U     /*!< Wakeup Pin Polarity bit for PI8    */
+#define  PWR_CR2_WUPP6                          0x00002000U     /*!< Wakeup Pin Polarity bit for PI11   */
+
+/*******************  Bit definition for PWR_CSR2 register  ********************/
+#define  PWR_CSR2_WUPF1                         0x00000001U     /*!< Wakeup Pin Flag for PA0            */
+#define  PWR_CSR2_WUPF2                         0x00000002U     /*!< Wakeup Pin Flag for PA2            */
+#define  PWR_CSR2_WUPF3                         0x00000004U     /*!< Wakeup Pin Flag for PC1            */
+#define  PWR_CSR2_WUPF4                         0x00000008U     /*!< Wakeup Pin Flag for PC13           */
+#define  PWR_CSR2_WUPF5                         0x00000010U     /*!< Wakeup Pin Flag for PI8            */
+#define  PWR_CSR2_WUPF6                         0x00000020U     /*!< Wakeup Pin Flag for PI11           */
+#define  PWR_CSR2_EWUP1                         0x00000100U     /*!< Enable Wakeup Pin PA0              */
+#define  PWR_CSR2_EWUP2                         0x00000200U     /*!< Enable Wakeup Pin PA2              */
+#define  PWR_CSR2_EWUP3                         0x00000400U     /*!< Enable Wakeup Pin PC1              */
+#define  PWR_CSR2_EWUP4                         0x00000800U     /*!< Enable Wakeup Pin PC13             */
+#define  PWR_CSR2_EWUP5                         0x00001000U     /*!< Enable Wakeup Pin PI8              */
+#define  PWR_CSR2_EWUP6                         0x00002000U     /*!< Enable Wakeup Pin PI11             */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    QUADSPI                                 */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for QUADSPI_CR register  *******************/
+#define  QUADSPI_CR_EN                           0x00000001U            /*!< Enable                            */
+#define  QUADSPI_CR_ABORT                        0x00000002U            /*!< Abort request                     */
+#define  QUADSPI_CR_DMAEN                        0x00000004U            /*!< DMA Enable                        */
+#define  QUADSPI_CR_TCEN                         0x00000008U            /*!< Timeout Counter Enable            */
+#define  QUADSPI_CR_SSHIFT                       0x00000010U            /*!< Sample Shift                      */
+#define  QUADSPI_CR_DFM                          0x00000040U            /*!< Dual Flash Mode                   */
+#define  QUADSPI_CR_FSEL                         0x00000080U            /*!< Flash Select                      */
+#define  QUADSPI_CR_FTHRES                       0x00001F00U            /*!< FTHRES[4:0] FIFO Level            */
+#define  QUADSPI_CR_FTHRES_0                     0x00000100U            /*!< Bit 0 */
+#define  QUADSPI_CR_FTHRES_1                     0x00000200U            /*!< Bit 1 */
+#define  QUADSPI_CR_FTHRES_2                     0x00000400U            /*!< Bit 2 */
+#define  QUADSPI_CR_FTHRES_3                     0x00000800U            /*!< Bit 3 */
+#define  QUADSPI_CR_FTHRES_4                     0x00001000U            /*!< Bit 4 */
+#define  QUADSPI_CR_TEIE                         0x00010000U            /*!< Transfer Error Interrupt Enable    */
+#define  QUADSPI_CR_TCIE                         0x00020000U            /*!< Transfer Complete Interrupt Enable */
+#define  QUADSPI_CR_FTIE                         0x00040000U            /*!< FIFO Threshold Interrupt Enable    */
+#define  QUADSPI_CR_SMIE                         0x00080000U            /*!< Status Match Interrupt Enable      */
+#define  QUADSPI_CR_TOIE                         0x00100000U            /*!< TimeOut Interrupt Enable           */
+#define  QUADSPI_CR_APMS                         0x00400000U            /*!< Bit 1                              */
+#define  QUADSPI_CR_PMM                          0x00800000U            /*!< Polling Match Mode                 */
+#define  QUADSPI_CR_PRESCALER                    0xFF000000U            /*!< PRESCALER[7:0] Clock prescaler     */
+#define  QUADSPI_CR_PRESCALER_0                  0x01000000U            /*!< Bit 0 */
+#define  QUADSPI_CR_PRESCALER_1                  0x02000000U            /*!< Bit 1 */
+#define  QUADSPI_CR_PRESCALER_2                  0x04000000U            /*!< Bit 2 */
+#define  QUADSPI_CR_PRESCALER_3                  0x08000000U            /*!< Bit 3 */
+#define  QUADSPI_CR_PRESCALER_4                  0x10000000U            /*!< Bit 4 */
+#define  QUADSPI_CR_PRESCALER_5                  0x20000000U            /*!< Bit 5 */
+#define  QUADSPI_CR_PRESCALER_6                  0x40000000U            /*!< Bit 6 */
+#define  QUADSPI_CR_PRESCALER_7                  0x80000000U            /*!< Bit 7 */
+
+/*****************  Bit definition for QUADSPI_DCR register  ******************/
+#define  QUADSPI_DCR_CKMODE                      0x00000001U            /*!< Mode 0 / Mode 3                 */
+#define  QUADSPI_DCR_CSHT                        0x00000700U            /*!< CSHT[2:0]: ChipSelect High Time */
+#define  QUADSPI_DCR_CSHT_0                      0x00000100U            /*!< Bit 0 */
+#define  QUADSPI_DCR_CSHT_1                      0x00000200U            /*!< Bit 1 */
+#define  QUADSPI_DCR_CSHT_2                      0x00000400U            /*!< Bit 2 */
+#define  QUADSPI_DCR_FSIZE                       0x001F0000U            /*!< FSIZE[4:0]: Flash Size          */
+#define  QUADSPI_DCR_FSIZE_0                     0x00010000U            /*!< Bit 0 */
+#define  QUADSPI_DCR_FSIZE_1                     0x00020000U            /*!< Bit 1 */
+#define  QUADSPI_DCR_FSIZE_2                     0x00040000U            /*!< Bit 2 */
+#define  QUADSPI_DCR_FSIZE_3                     0x00080000U            /*!< Bit 3 */
+#define  QUADSPI_DCR_FSIZE_4                     0x00100000U            /*!< Bit 4 */
+
+/******************  Bit definition for QUADSPI_SR register  *******************/
+#define  QUADSPI_SR_TEF                          0x00000001U             /*!< Transfer Error Flag    */
+#define  QUADSPI_SR_TCF                          0x00000002U             /*!< Transfer Complete Flag */
+#define  QUADSPI_SR_FTF                          0x00000004U             /*!< FIFO Threshlod Flag    */
+#define  QUADSPI_SR_SMF                          0x00000008U             /*!< Status Match Flag      */
+#define  QUADSPI_SR_TOF                          0x00000010U             /*!< Timeout Flag           */
+#define  QUADSPI_SR_BUSY                         0x00000020U             /*!< Busy                   */
+#define  QUADSPI_SR_FLEVEL                       0x00001F00U             /*!< FIFO Threshlod Flag    */
+#define  QUADSPI_SR_FLEVEL_0                     0x00000100U             /*!< Bit 0 */
+#define  QUADSPI_SR_FLEVEL_1                     0x00000200U             /*!< Bit 1 */
+#define  QUADSPI_SR_FLEVEL_2                     0x00000400U             /*!< Bit 2 */
+#define  QUADSPI_SR_FLEVEL_3                     0x00000800U             /*!< Bit 3 */
+#define  QUADSPI_SR_FLEVEL_4                     0x00001000U             /*!< Bit 4 */
+
+/******************  Bit definition for QUADSPI_FCR register  ******************/
+#define  QUADSPI_FCR_CTEF                        0x00000001U             /*!< Clear Transfer Error Flag    */
+#define  QUADSPI_FCR_CTCF                        0x00000002U             /*!< Clear Transfer Complete Flag */
+#define  QUADSPI_FCR_CSMF                        0x00000008U             /*!< Clear Status Match Flag      */
+#define  QUADSPI_FCR_CTOF                        0x00000010U             /*!< Clear Timeout Flag           */
+
+/******************  Bit definition for QUADSPI_DLR register  ******************/
+#define  QUADSPI_DLR_DL                          0xFFFFFFFFU             /*!< DL[31:0]: Data Length */
+
+/******************  Bit definition for QUADSPI_CCR register  ******************/
+#define  QUADSPI_CCR_INSTRUCTION                  0x000000FFU            /*!< INSTRUCTION[7:0]: Instruction    */
+#define  QUADSPI_CCR_INSTRUCTION_0                0x00000001U            /*!< Bit 0 */
+#define  QUADSPI_CCR_INSTRUCTION_1                0x00000002U            /*!< Bit 1 */
+#define  QUADSPI_CCR_INSTRUCTION_2                0x00000004U            /*!< Bit 2 */
+#define  QUADSPI_CCR_INSTRUCTION_3                0x00000008U            /*!< Bit 3 */
+#define  QUADSPI_CCR_INSTRUCTION_4                0x00000010U            /*!< Bit 4 */
+#define  QUADSPI_CCR_INSTRUCTION_5                0x00000020U            /*!< Bit 5 */
+#define  QUADSPI_CCR_INSTRUCTION_6                0x00000040U            /*!< Bit 6 */
+#define  QUADSPI_CCR_INSTRUCTION_7                0x00000080U            /*!< Bit 7 */
+#define  QUADSPI_CCR_IMODE                        0x00000300U            /*!< IMODE[1:0]: Instruction Mode      */
+#define  QUADSPI_CCR_IMODE_0                      0x00000100U            /*!< Bit 0 */
+#define  QUADSPI_CCR_IMODE_1                      0x00000200U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ADMODE                       0x00000C00U            /*!< ADMODE[1:0]: Address Mode         */
+#define  QUADSPI_CCR_ADMODE_0                     0x00000400U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ADMODE_1                     0x00000800U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ADSIZE                       0x00003000U            /*!< ADSIZE[1:0]: Address Size         */
+#define  QUADSPI_CCR_ADSIZE_0                     0x00001000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ADSIZE_1                     0x00002000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ABMODE                       0x0000C000U            /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define  QUADSPI_CCR_ABMODE_0                     0x00004000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ABMODE_1                     0x00008000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ABSIZE                       0x00030000U            /*!< ABSIZE[1:0]: Instruction Mode     */
+#define  QUADSPI_CCR_ABSIZE_0                     0x00010000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ABSIZE_1                     0x00020000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_DCYC                         0x007C0000U            /*!< DCYC[4:0]: Dummy Cycles           */
+#define  QUADSPI_CCR_DCYC_0                       0x00040000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_DCYC_1                       0x00080000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_DCYC_2                       0x00100000U            /*!< Bit 2 */
+#define  QUADSPI_CCR_DCYC_3                       0x00200000U            /*!< Bit 3 */
+#define  QUADSPI_CCR_DCYC_4                       0x00400000U            /*!< Bit 4 */
+#define  QUADSPI_CCR_DMODE                        0x03000000U            /*!< DMODE[1:0]: Data Mode              */
+#define  QUADSPI_CCR_DMODE_0                      0x01000000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_DMODE_1                      0x02000000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_FMODE                        0x0C000000U            /*!< FMODE[1:0]: Functional Mode        */
+#define  QUADSPI_CCR_FMODE_0                      0x04000000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_FMODE_1                      0x08000000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_SIOO                         0x10000000U            /*!< SIOO: Send Instruction Only Once Mode */
+#define  QUADSPI_CCR_DHHC                         0x40000000U            /*!< DHHC: Delay Half Hclk Cycle           */
+#define  QUADSPI_CCR_DDRM                         0x80000000U            /*!< DDRM: Double Data Rate Mode           */ 
+/******************  Bit definition for QUADSPI_AR register  *******************/
+#define  QUADSPI_AR_ADDRESS                       0xFFFFFFFFU            /*!< ADDRESS[31:0]: Address */
+
+/******************  Bit definition for QUADSPI_ABR register  ******************/
+#define  QUADSPI_ABR_ALTERNATE                    0xFFFFFFFFU            /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/******************  Bit definition for QUADSPI_DR register  *******************/
+#define  QUADSPI_DR_DATA                          0xFFFFFFFFU            /*!< DATA[31:0]: Data */
+
+/******************  Bit definition for QUADSPI_PSMKR register  ****************/
+#define  QUADSPI_PSMKR_MASK                       0xFFFFFFFFU            /*!< MASK[31:0]: Status Mask */
+
+/******************  Bit definition for QUADSPI_PSMAR register  ****************/
+#define  QUADSPI_PSMAR_MATCH                      0xFFFFFFFFU            /*!< MATCH[31:0]: Status Match */
+
+/******************  Bit definition for QUADSPI_PIR register  *****************/
+#define  QUADSPI_PIR_INTERVAL                     0x0000FFFFU            /*!< INTERVAL[15:0]: Polling Interval */
+
+/******************  Bit definition for QUADSPI_LPTR register  *****************/
+#define  QUADSPI_LPTR_TIMEOUT                     0x0000FFFFU            /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        0x00000001U
+#define  RCC_CR_HSIRDY                       0x00000002U
+#define  RCC_CR_HSITRIM                      0x000000F8U
+#define  RCC_CR_HSITRIM_0                    0x00000008U /*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    0x00000010U /*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    0x00000020U /*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    0x00000040U /*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    0x00000080U /*!<Bit 4 */
+#define  RCC_CR_HSICAL                       0x0000FF00U
+#define  RCC_CR_HSICAL_0                     0x00000100U /*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     0x00000200U /*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     0x00000400U /*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     0x00000800U /*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     0x00001000U /*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     0x00002000U /*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     0x00004000U /*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     0x00008000U /*!<Bit 7 */
+#define  RCC_CR_HSEON                        0x00010000U
+#define  RCC_CR_HSERDY                       0x00020000U
+#define  RCC_CR_HSEBYP                       0x00040000U
+#define  RCC_CR_CSSON                        0x00080000U
+#define  RCC_CR_PLLON                        0x01000000U
+#define  RCC_CR_PLLRDY                       0x02000000U
+#define  RCC_CR_PLLI2SON                     0x04000000U
+#define  RCC_CR_PLLI2SRDY                    0x08000000U
+#define  RCC_CR_PLLSAION                     0x10000000U
+#define  RCC_CR_PLLSAIRDY                    0x20000000U
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+#define  RCC_PLLCFGR_PLLM                    0x0000003FU
+#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
+#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
+#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
+#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
+#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
+#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
+#define  RCC_PLLCFGR_PLLN                    0x00007FC0U
+#define  RCC_PLLCFGR_PLLN_0                  0x00000040U
+#define  RCC_PLLCFGR_PLLN_1                  0x00000080U
+#define  RCC_PLLCFGR_PLLN_2                  0x00000100U
+#define  RCC_PLLCFGR_PLLN_3                  0x00000200U
+#define  RCC_PLLCFGR_PLLN_4                  0x00000400U
+#define  RCC_PLLCFGR_PLLN_5                  0x00000800U
+#define  RCC_PLLCFGR_PLLN_6                  0x00001000U
+#define  RCC_PLLCFGR_PLLN_7                  0x00002000U
+#define  RCC_PLLCFGR_PLLN_8                  0x00004000U
+#define  RCC_PLLCFGR_PLLP                    0x00030000U
+#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
+#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
+#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
+#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
+#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
+#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
+#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
+#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
+
+#define  RCC_PLLCFGR_PLLR                    0x70000000U
+#define  RCC_PLLCFGR_PLLR_0                  0x10000000U
+#define  RCC_PLLCFGR_PLLR_1                  0x20000000U
+#define  RCC_PLLCFGR_PLLR_2                  0x40000000U
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
+#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
+#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
+
+#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define  RCC_CFGR_RTCPRE                     0x001F0000U
+#define  RCC_CFGR_RTCPRE_0                   0x00010000U
+#define  RCC_CFGR_RTCPRE_1                   0x00020000U
+#define  RCC_CFGR_RTCPRE_2                   0x00040000U
+#define  RCC_CFGR_RTCPRE_3                   0x00080000U
+#define  RCC_CFGR_RTCPRE_4                   0x00100000U
+
+/*!< MCO1 configuration */
+#define  RCC_CFGR_MCO1                       0x00600000U
+#define  RCC_CFGR_MCO1_0                     0x00200000U
+#define  RCC_CFGR_MCO1_1                     0x00400000U
+
+#define  RCC_CFGR_I2SSRC                     0x00800000U
+
+#define  RCC_CFGR_MCO1PRE                    0x07000000U
+#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
+#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
+#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
+
+#define  RCC_CFGR_MCO2PRE                    0x38000000U
+#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
+#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
+#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
+
+#define  RCC_CFGR_MCO2                       0xC0000000U
+#define  RCC_CFGR_MCO2_0                     0x40000000U
+#define  RCC_CFGR_MCO2_1                     0x80000000U
+
+/********************  Bit definition for RCC_CIR register  *******************/
+#define  RCC_CIR_LSIRDYF                     0x00000001U
+#define  RCC_CIR_LSERDYF                     0x00000002U
+#define  RCC_CIR_HSIRDYF                     0x00000004U
+#define  RCC_CIR_HSERDYF                     0x00000008U
+#define  RCC_CIR_PLLRDYF                     0x00000010U
+#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
+#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
+#define  RCC_CIR_CSSF                        0x00000080U
+#define  RCC_CIR_LSIRDYIE                    0x00000100U
+#define  RCC_CIR_LSERDYIE                    0x00000200U
+#define  RCC_CIR_HSIRDYIE                    0x00000400U
+#define  RCC_CIR_HSERDYIE                    0x00000800U
+#define  RCC_CIR_PLLRDYIE                    0x00001000U
+#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
+#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
+#define  RCC_CIR_LSIRDYC                     0x00010000U
+#define  RCC_CIR_LSERDYC                     0x00020000U
+#define  RCC_CIR_HSIRDYC                     0x00040000U
+#define  RCC_CIR_HSERDYC                     0x00080000U
+#define  RCC_CIR_PLLRDYC                     0x00100000U
+#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
+#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
+#define  RCC_CIR_CSSC                        0x00800000U
+
+/********************  Bit definition for RCC_AHB1RSTR register  **************/
+#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
+#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
+#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
+#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
+#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
+#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
+#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
+#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
+#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
+#define  RCC_AHB1RSTR_GPIOJRST               0x00000200U
+#define  RCC_AHB1RSTR_GPIOKRST               0x00000400U
+#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
+#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
+#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
+#define  RCC_AHB1RSTR_DMA2DRST               0x00800000U
+#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
+#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
+
+/********************  Bit definition for RCC_AHB2RSTR register  **************/
+#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
+#define  RCC_AHB2RSTR_JPEGRST                0x00000002U
+#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
+#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
+
+/********************  Bit definition for RCC_AHB3RSTR register  **************/
+
+#define  RCC_AHB3RSTR_FMCRST                 0x00000001U
+#define  RCC_AHB3RSTR_QSPIRST                0x00000002U
+
+/********************  Bit definition for RCC_APB1RSTR register  **************/
+#define  RCC_APB1RSTR_TIM2RST                0x00000001U
+#define  RCC_APB1RSTR_TIM3RST                0x00000002U
+#define  RCC_APB1RSTR_TIM4RST                0x00000004U
+#define  RCC_APB1RSTR_TIM5RST                0x00000008U
+#define  RCC_APB1RSTR_TIM6RST                0x00000010U
+#define  RCC_APB1RSTR_TIM7RST                0x00000020U
+#define  RCC_APB1RSTR_TIM12RST               0x00000040U
+#define  RCC_APB1RSTR_TIM13RST               0x00000080U
+#define  RCC_APB1RSTR_TIM14RST               0x00000100U
+#define  RCC_APB1RSTR_LPTIM1RST              0x00000200U
+#define  RCC_APB1RSTR_WWDGRST                0x00000800U
+#define  RCC_APB1RSTR_CAN3RST                0x00002000U
+#define  RCC_APB1RSTR_SPI2RST                0x00004000U
+#define  RCC_APB1RSTR_SPI3RST                0x00008000U
+#define  RCC_APB1RSTR_SPDIFRXRST             0x00010000U
+#define  RCC_APB1RSTR_USART2RST              0x00020000U
+#define  RCC_APB1RSTR_USART3RST              0x00040000U
+#define  RCC_APB1RSTR_UART4RST               0x00080000U
+#define  RCC_APB1RSTR_UART5RST               0x00100000U
+#define  RCC_APB1RSTR_I2C1RST                0x00200000U
+#define  RCC_APB1RSTR_I2C2RST                0x00400000U
+#define  RCC_APB1RSTR_I2C3RST                0x00800000U
+#define  RCC_APB1RSTR_I2C4RST                0x01000000U
+#define  RCC_APB1RSTR_CAN1RST                0x02000000U
+#define  RCC_APB1RSTR_CAN2RST                0x04000000U
+#define  RCC_APB1RSTR_CECRST                 0x08000000U
+#define  RCC_APB1RSTR_PWRRST                 0x10000000U
+#define  RCC_APB1RSTR_DACRST                 0x20000000U
+#define  RCC_APB1RSTR_UART7RST               0x40000000U
+#define  RCC_APB1RSTR_UART8RST               0x80000000U
+
+/********************  Bit definition for RCC_APB2RSTR register  **************/
+#define  RCC_APB2RSTR_TIM1RST                0x00000001U
+#define  RCC_APB2RSTR_TIM8RST                0x00000002U
+#define  RCC_APB2RSTR_USART1RST              0x00000010U
+#define  RCC_APB2RSTR_USART6RST              0x00000020U
+#define  RCC_APB2RSTR_SDMMC2RST              0x00000080U
+#define  RCC_APB2RSTR_ADCRST                 0x00000100U
+#define  RCC_APB2RSTR_SDMMC1RST              0x00000800U
+#define  RCC_APB2RSTR_SPI1RST                0x00001000U
+#define  RCC_APB2RSTR_SPI4RST                0x00002000U
+#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
+#define  RCC_APB2RSTR_TIM9RST                0x00010000U
+#define  RCC_APB2RSTR_TIM10RST               0x00020000U
+#define  RCC_APB2RSTR_TIM11RST               0x00040000U
+#define  RCC_APB2RSTR_SPI5RST                0x00100000U
+#define  RCC_APB2RSTR_SPI6RST                0x00200000U
+#define  RCC_APB2RSTR_SAI1RST                0x00400000U
+#define  RCC_APB2RSTR_SAI2RST                0x00800000U
+#define  RCC_APB2RSTR_LTDCRST                0x04000000U
+#define  RCC_APB2RSTR_DSIRST                 0x08000000U
+#define  RCC_APB2RSTR_DFSDM1RST              0x20000000U
+#define  RCC_APB2RSTR_MDIORST                0x40000000U
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
+#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
+#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
+#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
+#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
+#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
+#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
+#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
+#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
+#define  RCC_AHB1ENR_GPIOJEN                 0x00000200U
+#define  RCC_AHB1ENR_GPIOKEN                 0x00000400U
+#define  RCC_AHB1ENR_CRCEN                   0x00001000U
+#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
+#define  RCC_AHB1ENR_DTCMRAMEN               0x00100000U
+#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
+#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
+#define  RCC_AHB1ENR_DMA2DEN                 0x00800000U
+#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
+#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
+#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
+#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
+#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
+#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
+#define  RCC_AHB2ENR_JPEGEN                  0x00000002U
+#define  RCC_AHB2ENR_RNGEN                   0x00000040U
+#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
+
+/********************  Bit definition for RCC_AHB3ENR register  ***************/
+#define  RCC_AHB3ENR_FMCEN                  0x00000001U
+#define  RCC_AHB3ENR_QSPIEN                 0x00000002U
+
+/********************  Bit definition for RCC_APB1ENR register  ***************/
+#define  RCC_APB1ENR_TIM2EN                  0x00000001U
+#define  RCC_APB1ENR_TIM3EN                  0x00000002U
+#define  RCC_APB1ENR_TIM4EN                  0x00000004U
+#define  RCC_APB1ENR_TIM5EN                  0x00000008U
+#define  RCC_APB1ENR_TIM6EN                  0x00000010U
+#define  RCC_APB1ENR_TIM7EN                  0x00000020U
+#define  RCC_APB1ENR_TIM12EN                 0x00000040U
+#define  RCC_APB1ENR_TIM13EN                 0x00000080U
+#define  RCC_APB1ENR_TIM14EN                 0x00000100U
+#define  RCC_APB1ENR_LPTIM1EN                0x00000200U
+#define  RCC_APB1ENR_RTCEN                   0x00000400U
+#define  RCC_APB1ENR_WWDGEN                  0x00000800U
+#define  RCC_APB1ENR_CAN3EN                  0x00002000U
+#define  RCC_APB1ENR_SPI2EN                  0x00004000U
+#define  RCC_APB1ENR_SPI3EN                  0x00008000U
+#define  RCC_APB1ENR_SPDIFRXEN               0x00010000U
+#define  RCC_APB1ENR_USART2EN                0x00020000U
+#define  RCC_APB1ENR_USART3EN                0x00040000U
+#define  RCC_APB1ENR_UART4EN                 0x00080000U
+#define  RCC_APB1ENR_UART5EN                 0x00100000U
+#define  RCC_APB1ENR_I2C1EN                  0x00200000U
+#define  RCC_APB1ENR_I2C2EN                  0x00400000U
+#define  RCC_APB1ENR_I2C3EN                  0x00800000U
+#define  RCC_APB1ENR_I2C4EN                  0x01000000U
+#define  RCC_APB1ENR_CAN1EN                  0x02000000U
+#define  RCC_APB1ENR_CAN2EN                  0x04000000U
+#define  RCC_APB1ENR_CECEN                   0x08000000U
+#define  RCC_APB1ENR_PWREN                   0x10000000U
+#define  RCC_APB1ENR_DACEN                   0x20000000U
+#define  RCC_APB1ENR_UART7EN                 0x40000000U
+#define  RCC_APB1ENR_UART8EN                 0x80000000U
+
+/********************  Bit definition for RCC_APB2ENR register  ***************/
+#define  RCC_APB2ENR_TIM1EN                  0x00000001U
+#define  RCC_APB2ENR_TIM8EN                  0x00000002U
+#define  RCC_APB2ENR_USART1EN                0x00000010U
+#define  RCC_APB2ENR_USART6EN                0x00000020U
+#define  RCC_APB2ENR_SDMMC2EN                0x00000080U
+#define  RCC_APB2ENR_ADC1EN                  0x00000100U
+#define  RCC_APB2ENR_ADC2EN                  0x00000200U
+#define  RCC_APB2ENR_ADC3EN                  0x00000400U
+#define  RCC_APB2ENR_SDMMC1EN                0x00000800U
+#define  RCC_APB2ENR_SPI1EN                  0x00001000U
+#define  RCC_APB2ENR_SPI4EN                  0x00002000U
+#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
+#define  RCC_APB2ENR_TIM9EN                  0x00010000U
+#define  RCC_APB2ENR_TIM10EN                 0x00020000U
+#define  RCC_APB2ENR_TIM11EN                 0x00040000U
+#define  RCC_APB2ENR_SPI5EN                  0x00100000U
+#define  RCC_APB2ENR_SPI6EN                  0x00200000U
+#define  RCC_APB2ENR_SAI1EN                  0x00400000U
+#define  RCC_APB2ENR_SAI2EN                  0x00800000U
+#define  RCC_APB2ENR_LTDCEN                  0x04000000U
+#define  RCC_APB2ENR_DSIEN                   0x08000000U
+#define  RCC_APB2ENR_DFSDM1EN                0x20000000U
+#define  RCC_APB2ENR_MDIOEN                  0x40000000U
+
+/********************  Bit definition for RCC_AHB1LPENR register  *************/
+#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
+#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
+#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
+#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
+#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
+#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
+#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
+#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
+#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
+#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
+#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
+#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
+#define  RCC_AHB1LPENR_AXILPEN               0x00002000U
+#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
+#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
+#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
+#define  RCC_AHB1LPENR_DTCMLPEN              0x00100000U
+#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
+#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
+#define  RCC_AHB1LPENR_DMA2DLPEN             0x00800000U
+#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
+#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
+#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
+#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
+#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
+#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
+
+/********************  Bit definition for RCC_AHB2LPENR register  *************/
+#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
+#define  RCC_AHB2LPENR_JPEGLPEN              0x00000002U
+#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
+#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
+
+/********************  Bit definition for RCC_AHB3LPENR register  *************/
+#define  RCC_AHB3LPENR_FMCLPEN               0x00000001U
+#define  RCC_AHB3LPENR_QSPILPEN              0x00000002U
+/********************  Bit definition for RCC_APB1LPENR register  *************/
+#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
+#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
+#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
+#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
+#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
+#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
+#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
+#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
+#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
+#define  RCC_APB1LPENR_LPTIM1LPEN            0x00000200U
+#define  RCC_APB1LPENR_RTCLPEN               0x00000400U
+#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
+#define  RCC_APB1LPENR_CAN3LPEN              0x00002000U
+#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
+#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
+#define  RCC_APB1LPENR_SPDIFRXLPEN           0x00010000U
+#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
+#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
+#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
+#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
+#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
+#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
+#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
+#define  RCC_APB1LPENR_I2C4LPEN              0x01000000U
+#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
+#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
+#define  RCC_APB1LPENR_CECLPEN               0x08000000U
+#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
+#define  RCC_APB1LPENR_DACLPEN               0x20000000U
+#define  RCC_APB1LPENR_UART7LPEN             0x40000000U
+#define  RCC_APB1LPENR_UART8LPEN             0x80000000U
+
+/********************  Bit definition for RCC_APB2LPENR register  *************/
+#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
+#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
+#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
+#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
+#define  RCC_APB2LPENR_SDMMC2LPEN            0x00000080U
+#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
+#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
+#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
+#define  RCC_APB2LPENR_SDMMC1LPEN            0x00000800U
+#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
+#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
+#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
+#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
+#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
+#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
+#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
+#define  RCC_APB2LPENR_SPI6LPEN              0x00200000U
+#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
+#define  RCC_APB2LPENR_SAI2LPEN              0x00800000U
+#define  RCC_APB2LPENR_LTDCLPEN              0x04000000U
+#define  RCC_APB2LPENR_DSILPEN               0x08000000U
+#define  RCC_APB2LPENR_DFSDM1LPEN            0x20000000U
+#define  RCC_APB2LPENR_MDIOLPEN              0x40000000U
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define  RCC_BDCR_LSEON                      0x00000001U
+#define  RCC_BDCR_LSERDY                     0x00000002U
+#define  RCC_BDCR_LSEBYP                     0x00000004U
+#define  RCC_BDCR_LSEDRV                     0x00000018U
+#define  RCC_BDCR_LSEDRV_0                   0x00000008U
+#define  RCC_BDCR_LSEDRV_1                   0x00000010U
+#define  RCC_BDCR_RTCSEL                     0x00000300U
+#define  RCC_BDCR_RTCSEL_0                   0x00000100U
+#define  RCC_BDCR_RTCSEL_1                   0x00000200U
+#define  RCC_BDCR_RTCEN                      0x00008000U
+#define  RCC_BDCR_BDRST                      0x00010000U
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define  RCC_CSR_LSION                       0x00000001U
+#define  RCC_CSR_LSIRDY                      0x00000002U
+#define  RCC_CSR_RMVF                        0x01000000U
+#define  RCC_CSR_BORRSTF                     0x02000000U
+#define  RCC_CSR_PINRSTF                     0x04000000U
+#define  RCC_CSR_PORRSTF                     0x08000000U
+#define  RCC_CSR_SFTRSTF                     0x10000000U
+#define  RCC_CSR_IWDGRSTF                    0x20000000U
+#define  RCC_CSR_WWDGRSTF                    0x40000000U
+#define  RCC_CSR_LPWRRSTF                    0x80000000U
+
+/********************  Bit definition for RCC_SSCGR register  *****************/
+#define  RCC_SSCGR_MODPER                    0x00001FFFU
+#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
+#define  RCC_SSCGR_SPREADSEL                 0x40000000U
+#define  RCC_SSCGR_SSCGEN                    0x80000000U
+
+/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
+#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
+#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
+#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
+#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
+#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
+#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
+#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
+#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
+#define  RCC_PLLI2SCFGR_PLLI2SP              0x00030000U
+#define  RCC_PLLI2SCFGR_PLLI2SP_0            0x00010000U
+#define  RCC_PLLI2SCFGR_PLLI2SP_1            0x00020000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
+
+/********************  Bit definition for RCC_PLLSAICFGR register  ************/
+#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
+#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
+#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
+#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
+#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
+#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
+#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
+#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
+#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
+#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
+#define  RCC_PLLSAICFGR_PLLSAIP              0x00030000U
+#define  RCC_PLLSAICFGR_PLLSAIP_0            0x00010000U
+#define  RCC_PLLSAICFGR_PLLSAIP_1            0x00020000U
+#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
+#define  RCC_PLLSAICFGR_PLLSAIR              0x70000000U
+#define  RCC_PLLSAICFGR_PLLSAIR_0            0x10000000U
+#define  RCC_PLLSAICFGR_PLLSAIR_1            0x20000000U
+#define  RCC_PLLSAICFGR_PLLSAIR_2            0x40000000U
+
+/********************  Bit definition for RCC_DCKCFGR1 register  ***************/
+#define  RCC_DCKCFGR1_PLLI2SDIVQ             0x0000001FU
+#define  RCC_DCKCFGR1_PLLI2SDIVQ_0           0x00000001U
+#define  RCC_DCKCFGR1_PLLI2SDIVQ_1           0x00000002U
+#define  RCC_DCKCFGR1_PLLI2SDIVQ_2           0x00000004U
+#define  RCC_DCKCFGR1_PLLI2SDIVQ_3           0x00000008U
+#define  RCC_DCKCFGR1_PLLI2SDIVQ_4           0x00000010U
+
+#define  RCC_DCKCFGR1_PLLSAIDIVQ             0x00001F00U
+#define  RCC_DCKCFGR1_PLLSAIDIVQ_0           0x00000100U
+#define  RCC_DCKCFGR1_PLLSAIDIVQ_1           0x00000200U
+#define  RCC_DCKCFGR1_PLLSAIDIVQ_2           0x00000400U
+#define  RCC_DCKCFGR1_PLLSAIDIVQ_3           0x00000800U
+#define  RCC_DCKCFGR1_PLLSAIDIVQ_4           0x00001000U
+
+#define  RCC_DCKCFGR1_PLLSAIDIVR             0x00030000U
+#define  RCC_DCKCFGR1_PLLSAIDIVR_0           0x00010000U
+#define  RCC_DCKCFGR1_PLLSAIDIVR_1           0x00020000U
+
+#define  RCC_DCKCFGR1_SAI1SEL                0x00300000U
+#define  RCC_DCKCFGR1_SAI1SEL_0              0x00100000U
+#define  RCC_DCKCFGR1_SAI1SEL_1              0x00200000U
+
+#define  RCC_DCKCFGR1_SAI2SEL                0x00C00000U
+#define  RCC_DCKCFGR1_SAI2SEL_0              0x00400000U
+#define  RCC_DCKCFGR1_SAI2SEL_1              0x00800000U
+
+#define  RCC_DCKCFGR1_TIMPRE                 0x01000000U
+#define  RCC_DCKCFGR1_DFSDM1SEL              0x02000000U
+#define  RCC_DCKCFGR1_ADFSDM1SEL             0x04000000U
+
+/********************  Bit definition for RCC_DCKCFGR2 register  ***************/
+#define  RCC_DCKCFGR2_USART1SEL              0x00000003U
+#define  RCC_DCKCFGR2_USART1SEL_0            0x00000001U
+#define  RCC_DCKCFGR2_USART1SEL_1            0x00000002U
+#define  RCC_DCKCFGR2_USART2SEL              0x0000000CU
+#define  RCC_DCKCFGR2_USART2SEL_0            0x00000004U
+#define  RCC_DCKCFGR2_USART2SEL_1            0x00000008U
+#define  RCC_DCKCFGR2_USART3SEL              0x00000030U
+#define  RCC_DCKCFGR2_USART3SEL_0            0x00000010U
+#define  RCC_DCKCFGR2_USART3SEL_1            0x00000020U
+#define  RCC_DCKCFGR2_UART4SEL               0x000000C0U
+#define  RCC_DCKCFGR2_UART4SEL_0             0x00000040U
+#define  RCC_DCKCFGR2_UART4SEL_1             0x00000080U
+#define  RCC_DCKCFGR2_UART5SEL               0x00000300U
+#define  RCC_DCKCFGR2_UART5SEL_0             0x00000100U
+#define  RCC_DCKCFGR2_UART5SEL_1             0x00000200U
+#define  RCC_DCKCFGR2_USART6SEL              0x00000C00U
+#define  RCC_DCKCFGR2_USART6SEL_0            0x00000400U
+#define  RCC_DCKCFGR2_USART6SEL_1            0x00000800U
+#define  RCC_DCKCFGR2_UART7SEL               0x00003000U
+#define  RCC_DCKCFGR2_UART7SEL_0             0x00001000U
+#define  RCC_DCKCFGR2_UART7SEL_1             0x00002000U
+#define  RCC_DCKCFGR2_UART8SEL               0x0000C000U
+#define  RCC_DCKCFGR2_UART8SEL_0             0x00004000U
+#define  RCC_DCKCFGR2_UART8SEL_1             0x00008000U
+#define  RCC_DCKCFGR2_I2C1SEL                0x00030000U
+#define  RCC_DCKCFGR2_I2C1SEL_0              0x00010000U
+#define  RCC_DCKCFGR2_I2C1SEL_1              0x00020000U
+#define  RCC_DCKCFGR2_I2C2SEL                0x000C0000U
+#define  RCC_DCKCFGR2_I2C2SEL_0              0x00040000U
+#define  RCC_DCKCFGR2_I2C2SEL_1              0x00080000U
+#define  RCC_DCKCFGR2_I2C3SEL                0x00300000U
+#define  RCC_DCKCFGR2_I2C3SEL_0              0x00100000U
+#define  RCC_DCKCFGR2_I2C3SEL_1              0x00200000U
+#define  RCC_DCKCFGR2_I2C4SEL                0x00C00000U
+#define  RCC_DCKCFGR2_I2C4SEL_0              0x00400000U
+#define  RCC_DCKCFGR2_I2C4SEL_1              0x00800000U
+#define  RCC_DCKCFGR2_LPTIM1SEL              0x03000000U
+#define  RCC_DCKCFGR2_LPTIM1SEL_0            0x01000000U
+#define  RCC_DCKCFGR2_LPTIM1SEL_1            0x02000000U
+#define  RCC_DCKCFGR2_CECSEL                 0x04000000U
+#define  RCC_DCKCFGR2_CK48MSEL               0x08000000U
+#define  RCC_DCKCFGR2_SDMMC1SEL              0x10000000U
+#define  RCC_DCKCFGR2_SDMMC2SEL              0x20000000U
+#define  RCC_DCKCFGR2_DSISEL                 0x40000000U
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN                         0x00000004U
+#define RNG_CR_IE                            0x00000008U
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY                          0x00000001U
+#define RNG_SR_CECS                          0x00000002U
+#define RNG_SR_SECS                          0x00000004U
+#define RNG_SR_CEIS                          0x00000020U
+#define RNG_SR_SEIS                          0x00000040U
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM                            0x00400000U
+#define RTC_TR_HT                            0x00300000U
+#define RTC_TR_HT_0                          0x00100000U
+#define RTC_TR_HT_1                          0x00200000U
+#define RTC_TR_HU                            0x000F0000U
+#define RTC_TR_HU_0                          0x00010000U
+#define RTC_TR_HU_1                          0x00020000U
+#define RTC_TR_HU_2                          0x00040000U
+#define RTC_TR_HU_3                          0x00080000U
+#define RTC_TR_MNT                           0x00007000U
+#define RTC_TR_MNT_0                         0x00001000U
+#define RTC_TR_MNT_1                         0x00002000U
+#define RTC_TR_MNT_2                         0x00004000U
+#define RTC_TR_MNU                           0x00000F00U
+#define RTC_TR_MNU_0                         0x00000100U
+#define RTC_TR_MNU_1                         0x00000200U
+#define RTC_TR_MNU_2                         0x00000400U
+#define RTC_TR_MNU_3                         0x00000800U
+#define RTC_TR_ST                            0x00000070U
+#define RTC_TR_ST_0                          0x00000010U
+#define RTC_TR_ST_1                          0x00000020U
+#define RTC_TR_ST_2                          0x00000040U
+#define RTC_TR_SU                            0x0000000FU
+#define RTC_TR_SU_0                          0x00000001U
+#define RTC_TR_SU_1                          0x00000002U
+#define RTC_TR_SU_2                          0x00000004U
+#define RTC_TR_SU_3                          0x00000008U
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT                            0x00F00000U
+#define RTC_DR_YT_0                          0x00100000U
+#define RTC_DR_YT_1                          0x00200000U
+#define RTC_DR_YT_2                          0x00400000U
+#define RTC_DR_YT_3                          0x00800000U
+#define RTC_DR_YU                            0x000F0000U
+#define RTC_DR_YU_0                          0x00010000U
+#define RTC_DR_YU_1                          0x00020000U
+#define RTC_DR_YU_2                          0x00040000U
+#define RTC_DR_YU_3                          0x00080000U
+#define RTC_DR_WDU                           0x0000E000U
+#define RTC_DR_WDU_0                         0x00002000U
+#define RTC_DR_WDU_1                         0x00004000U
+#define RTC_DR_WDU_2                         0x00008000U
+#define RTC_DR_MT                            0x00001000U
+#define RTC_DR_MU                            0x00000F00U
+#define RTC_DR_MU_0                          0x00000100U
+#define RTC_DR_MU_1                          0x00000200U
+#define RTC_DR_MU_2                          0x00000400U
+#define RTC_DR_MU_3                          0x00000800U
+#define RTC_DR_DT                            0x00000030U
+#define RTC_DR_DT_0                          0x00000010U
+#define RTC_DR_DT_1                          0x00000020U
+#define RTC_DR_DU                            0x0000000FU
+#define RTC_DR_DU_0                          0x00000001U
+#define RTC_DR_DU_1                          0x00000002U
+#define RTC_DR_DU_2                          0x00000004U
+#define RTC_DR_DU_3                          0x00000008U
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_ITSE                          0x01000000U 
+#define RTC_CR_COE                           0x00800000U
+#define RTC_CR_OSEL                          0x00600000U
+#define RTC_CR_OSEL_0                        0x00200000U
+#define RTC_CR_OSEL_1                        0x00400000U
+#define RTC_CR_POL                           0x00100000U
+#define RTC_CR_COSEL                         0x00080000U
+#define RTC_CR_BCK                           0x00040000U
+#define RTC_CR_SUB1H                         0x00020000U
+#define RTC_CR_ADD1H                         0x00010000U
+#define RTC_CR_TSIE                          0x00008000U
+#define RTC_CR_WUTIE                         0x00004000U
+#define RTC_CR_ALRBIE                        0x00002000U
+#define RTC_CR_ALRAIE                        0x00001000U
+#define RTC_CR_TSE                           0x00000800U
+#define RTC_CR_WUTE                          0x00000400U
+#define RTC_CR_ALRBE                         0x00000200U
+#define RTC_CR_ALRAE                         0x00000100U
+#define RTC_CR_FMT                           0x00000040U
+#define RTC_CR_BYPSHAD                       0x00000020U
+#define RTC_CR_REFCKON                       0x00000010U
+#define RTC_CR_TSEDGE                        0x00000008U
+#define RTC_CR_WUCKSEL                       0x00000007U
+#define RTC_CR_WUCKSEL_0                     0x00000001U
+#define RTC_CR_WUCKSEL_1                     0x00000002U
+#define RTC_CR_WUCKSEL_2                     0x00000004U
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_ITSF                         0x00020000U
+#define RTC_ISR_RECALPF                      0x00010000U
+#define RTC_ISR_TAMP3F                       0x00008000U
+#define RTC_ISR_TAMP2F                       0x00004000U
+#define RTC_ISR_TAMP1F                       0x00002000U
+#define RTC_ISR_TSOVF                        0x00001000U
+#define RTC_ISR_TSF                          0x00000800U
+#define RTC_ISR_WUTF                         0x00000400U
+#define RTC_ISR_ALRBF                        0x00000200U
+#define RTC_ISR_ALRAF                        0x00000100U
+#define RTC_ISR_INIT                         0x00000080U
+#define RTC_ISR_INITF                        0x00000040U
+#define RTC_ISR_RSF                          0x00000020U
+#define RTC_ISR_INITS                        0x00000010U
+#define RTC_ISR_SHPF                         0x00000008U
+#define RTC_ISR_WUTWF                        0x00000004U
+#define RTC_ISR_ALRBWF                       0x00000002U
+#define RTC_ISR_ALRAWF                       0x00000001U
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    0x007F0000U
+#define RTC_PRER_PREDIV_S                    0x00007FFFU
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT                         0x0000FFFFU
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      0x80000000U
+#define RTC_ALRMAR_WDSEL                     0x40000000U
+#define RTC_ALRMAR_DT                        0x30000000U
+#define RTC_ALRMAR_DT_0                      0x10000000U
+#define RTC_ALRMAR_DT_1                      0x20000000U
+#define RTC_ALRMAR_DU                        0x0F000000U
+#define RTC_ALRMAR_DU_0                      0x01000000U
+#define RTC_ALRMAR_DU_1                      0x02000000U
+#define RTC_ALRMAR_DU_2                      0x04000000U
+#define RTC_ALRMAR_DU_3                      0x08000000U
+#define RTC_ALRMAR_MSK3                      0x00800000U
+#define RTC_ALRMAR_PM                        0x00400000U
+#define RTC_ALRMAR_HT                        0x00300000U
+#define RTC_ALRMAR_HT_0                      0x00100000U
+#define RTC_ALRMAR_HT_1                      0x00200000U
+#define RTC_ALRMAR_HU                        0x000F0000U
+#define RTC_ALRMAR_HU_0                      0x00010000U
+#define RTC_ALRMAR_HU_1                      0x00020000U
+#define RTC_ALRMAR_HU_2                      0x00040000U
+#define RTC_ALRMAR_HU_3                      0x00080000U
+#define RTC_ALRMAR_MSK2                      0x00008000U
+#define RTC_ALRMAR_MNT                       0x00007000U
+#define RTC_ALRMAR_MNT_0                     0x00001000U
+#define RTC_ALRMAR_MNT_1                     0x00002000U
+#define RTC_ALRMAR_MNT_2                     0x00004000U
+#define RTC_ALRMAR_MNU                       0x00000F00U
+#define RTC_ALRMAR_MNU_0                     0x00000100U
+#define RTC_ALRMAR_MNU_1                     0x00000200U
+#define RTC_ALRMAR_MNU_2                     0x00000400U
+#define RTC_ALRMAR_MNU_3                     0x00000800U
+#define RTC_ALRMAR_MSK1                      0x00000080U
+#define RTC_ALRMAR_ST                        0x00000070U
+#define RTC_ALRMAR_ST_0                      0x00000010U
+#define RTC_ALRMAR_ST_1                      0x00000020U
+#define RTC_ALRMAR_ST_2                      0x00000040U
+#define RTC_ALRMAR_SU                        0x0000000FU
+#define RTC_ALRMAR_SU_0                      0x00000001U
+#define RTC_ALRMAR_SU_1                      0x00000002U
+#define RTC_ALRMAR_SU_2                      0x00000004U
+#define RTC_ALRMAR_SU_3                      0x00000008U
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4                      0x80000000U
+#define RTC_ALRMBR_WDSEL                     0x40000000U
+#define RTC_ALRMBR_DT                        0x30000000U
+#define RTC_ALRMBR_DT_0                      0x10000000U
+#define RTC_ALRMBR_DT_1                      0x20000000U
+#define RTC_ALRMBR_DU                        0x0F000000U
+#define RTC_ALRMBR_DU_0                      0x01000000U
+#define RTC_ALRMBR_DU_1                      0x02000000U
+#define RTC_ALRMBR_DU_2                      0x04000000U
+#define RTC_ALRMBR_DU_3                      0x08000000U
+#define RTC_ALRMBR_MSK3                      0x00800000U
+#define RTC_ALRMBR_PM                        0x00400000U
+#define RTC_ALRMBR_HT                        0x00300000U
+#define RTC_ALRMBR_HT_0                      0x00100000U
+#define RTC_ALRMBR_HT_1                      0x00200000U
+#define RTC_ALRMBR_HU                        0x000F0000U
+#define RTC_ALRMBR_HU_0                      0x00010000U
+#define RTC_ALRMBR_HU_1                      0x00020000U
+#define RTC_ALRMBR_HU_2                      0x00040000U
+#define RTC_ALRMBR_HU_3                      0x00080000U
+#define RTC_ALRMBR_MSK2                      0x00008000U
+#define RTC_ALRMBR_MNT                       0x00007000U
+#define RTC_ALRMBR_MNT_0                     0x00001000U
+#define RTC_ALRMBR_MNT_1                     0x00002000U
+#define RTC_ALRMBR_MNT_2                     0x00004000U
+#define RTC_ALRMBR_MNU                       0x00000F00U
+#define RTC_ALRMBR_MNU_0                     0x00000100U
+#define RTC_ALRMBR_MNU_1                     0x00000200U
+#define RTC_ALRMBR_MNU_2                     0x00000400U
+#define RTC_ALRMBR_MNU_3                     0x00000800U
+#define RTC_ALRMBR_MSK1                      0x00000080U
+#define RTC_ALRMBR_ST                        0x00000070U
+#define RTC_ALRMBR_ST_0                      0x00000010U
+#define RTC_ALRMBR_ST_1                      0x00000020U
+#define RTC_ALRMBR_ST_2                      0x00000040U
+#define RTC_ALRMBR_SU                        0x0000000FU
+#define RTC_ALRMBR_SU_0                      0x00000001U
+#define RTC_ALRMBR_SU_1                      0x00000002U
+#define RTC_ALRMBR_SU_2                      0x00000004U
+#define RTC_ALRMBR_SU_3                      0x00000008U
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          0x000000FFU
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS                           0x0000FFFFU
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     0x00007FFFU
+#define RTC_SHIFTR_ADD1S                     0x80000000U
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          0x00400000U
+#define RTC_TSTR_HT                          0x00300000U
+#define RTC_TSTR_HT_0                        0x00100000U
+#define RTC_TSTR_HT_1                        0x00200000U
+#define RTC_TSTR_HU                          0x000F0000U
+#define RTC_TSTR_HU_0                        0x00010000U
+#define RTC_TSTR_HU_1                        0x00020000U
+#define RTC_TSTR_HU_2                        0x00040000U
+#define RTC_TSTR_HU_3                        0x00080000U
+#define RTC_TSTR_MNT                         0x00007000U
+#define RTC_TSTR_MNT_0                       0x00001000U
+#define RTC_TSTR_MNT_1                       0x00002000U
+#define RTC_TSTR_MNT_2                       0x00004000U
+#define RTC_TSTR_MNU                         0x00000F00U
+#define RTC_TSTR_MNU_0                       0x00000100U
+#define RTC_TSTR_MNU_1                       0x00000200U
+#define RTC_TSTR_MNU_2                       0x00000400U
+#define RTC_TSTR_MNU_3                       0x00000800U
+#define RTC_TSTR_ST                          0x00000070U
+#define RTC_TSTR_ST_0                        0x00000010U
+#define RTC_TSTR_ST_1                        0x00000020U
+#define RTC_TSTR_ST_2                        0x00000040U
+#define RTC_TSTR_SU                          0x0000000FU
+#define RTC_TSTR_SU_0                        0x00000001U
+#define RTC_TSTR_SU_1                        0x00000002U
+#define RTC_TSTR_SU_2                        0x00000004U
+#define RTC_TSTR_SU_3                        0x00000008U
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         0x0000E000U
+#define RTC_TSDR_WDU_0                       0x00002000U
+#define RTC_TSDR_WDU_1                       0x00004000U
+#define RTC_TSDR_WDU_2                       0x00008000U
+#define RTC_TSDR_MT                          0x00001000U
+#define RTC_TSDR_MU                          0x00000F00U
+#define RTC_TSDR_MU_0                        0x00000100U
+#define RTC_TSDR_MU_1                        0x00000200U
+#define RTC_TSDR_MU_2                        0x00000400U
+#define RTC_TSDR_MU_3                        0x00000800U
+#define RTC_TSDR_DT                          0x00000030U
+#define RTC_TSDR_DT_0                        0x00000010U
+#define RTC_TSDR_DT_1                        0x00000020U
+#define RTC_TSDR_DU                          0x0000000FU
+#define RTC_TSDR_DU_0                        0x00000001U
+#define RTC_TSDR_DU_1                        0x00000002U
+#define RTC_TSDR_DU_2                        0x00000004U
+#define RTC_TSDR_DU_3                        0x00000008U
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS                         0x0000FFFFU
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP                        0x00008000U
+#define RTC_CALR_CALW8                       0x00004000U
+#define RTC_CALR_CALW16                      0x00002000U
+#define RTC_CALR_CALM                        0x000001FFU
+#define RTC_CALR_CALM_0                      0x00000001U
+#define RTC_CALR_CALM_1                      0x00000002U
+#define RTC_CALR_CALM_2                      0x00000004U
+#define RTC_CALR_CALM_3                      0x00000008U
+#define RTC_CALR_CALM_4                      0x00000010U
+#define RTC_CALR_CALM_5                      0x00000020U
+#define RTC_CALR_CALM_6                      0x00000040U
+#define RTC_CALR_CALM_7                      0x00000080U
+#define RTC_CALR_CALM_8                      0x00000100U
+
+/********************  Bits definition for RTC_TAMPCR register  ****************/
+#define RTC_TAMPCR_TAMP3MF                   0x01000000U
+#define RTC_TAMPCR_TAMP3NOERASE              0x00800000U
+#define RTC_TAMPCR_TAMP3IE                   0x00400000U
+#define RTC_TAMPCR_TAMP2MF                   0x00200000U
+#define RTC_TAMPCR_TAMP2NOERASE              0x00100000U
+#define RTC_TAMPCR_TAMP2IE                   0x00080000U
+#define RTC_TAMPCR_TAMP1MF                   0x00040000U
+#define RTC_TAMPCR_TAMP1NOERASE              0x00020000U
+#define RTC_TAMPCR_TAMP1IE                   0x00010000U
+#define RTC_TAMPCR_TAMPPUDIS                 0x00008000U
+#define RTC_TAMPCR_TAMPPRCH                  0x00006000U
+#define RTC_TAMPCR_TAMPPRCH_0                0x00002000U
+#define RTC_TAMPCR_TAMPPRCH_1                0x00004000U
+#define RTC_TAMPCR_TAMPFLT                   0x00001800U
+#define RTC_TAMPCR_TAMPFLT_0                 0x00000800U
+#define RTC_TAMPCR_TAMPFLT_1                 0x00001000U
+#define RTC_TAMPCR_TAMPFREQ                  0x00000700U
+#define RTC_TAMPCR_TAMPFREQ_0                0x00000100U
+#define RTC_TAMPCR_TAMPFREQ_1                0x00000200U
+#define RTC_TAMPCR_TAMPFREQ_2                0x00000400U
+#define RTC_TAMPCR_TAMPTS                    0x00000080U
+#define RTC_TAMPCR_TAMP3TRG                  0x00000040U
+#define RTC_TAMPCR_TAMP3E                    0x00000020U
+#define RTC_TAMPCR_TAMP2TRG                  0x00000010U
+#define RTC_TAMPCR_TAMP2E                    0x00000008U
+#define RTC_TAMPCR_TAMPIE                    0x00000004U
+#define RTC_TAMPCR_TAMP1TRG                  0x00000002U
+#define RTC_TAMPCR_TAMP1E                    0x00000001U
+
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0                0x01000000U
+#define RTC_ALRMASSR_MASKSS_1                0x02000000U
+#define RTC_ALRMASSR_MASKSS_2                0x04000000U
+#define RTC_ALRMASSR_MASKSS_3                0x08000000U
+#define RTC_ALRMASSR_SS                      0x00007FFFU
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
+#define RTC_ALRMBSSR_SS                      0x00007FFFU
+
+/********************  Bits definition for RTC_OR register  ****************/
+#define RTC_OR_TSINSEL                       0x00000006U
+#define RTC_OR_TSINSEL_0                     0x00000002U
+#define RTC_OR_TSINSEL_1                     0x00000004U
+#define RTC_OR_ALARMTYPE                     0x00000008U
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R                           0xFFFFFFFFU
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER                       0x00000020U
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SAI_GCR register  *******************/
+#define  SAI_GCR_SYNCIN                      0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define  SAI_GCR_SYNCIN_0                    0x00000001U        /*!<Bit 0 */
+#define  SAI_GCR_SYNCIN_1                    0x00000002U        /*!<Bit 1 */
+                                             
+#define  SAI_GCR_SYNCOUT                     0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define  SAI_GCR_SYNCOUT_0                   0x00000010U        /*!<Bit 0 */
+#define  SAI_GCR_SYNCOUT_1                   0x00000020U        /*!<Bit 1 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define  SAI_xCR1_MODE                       0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define  SAI_xCR1_MODE_0                     0x00000001U        /*!<Bit 0 */
+#define  SAI_xCR1_MODE_1                     0x00000002U        /*!<Bit 1 */
+                                             
+#define  SAI_xCR1_PRTCFG                     0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define  SAI_xCR1_PRTCFG_0                   0x00000004U        /*!<Bit 0 */
+#define  SAI_xCR1_PRTCFG_1                   0x00000008U        /*!<Bit 1 */
+                                             
+#define  SAI_xCR1_DS                         0x000000E0U        /*!<DS[1:0] bits (Data Size) */
+#define  SAI_xCR1_DS_0                       0x00000020U        /*!<Bit 0 */
+#define  SAI_xCR1_DS_1                       0x00000040U        /*!<Bit 1 */
+#define  SAI_xCR1_DS_2                       0x00000080U        /*!<Bit 2 */
+                                             
+#define  SAI_xCR1_LSBFIRST                   0x00000100U        /*!<LSB First Configuration  */
+#define  SAI_xCR1_CKSTR                      0x00000200U        /*!<ClocK STRobing edge      */
+                                             
+#define  SAI_xCR1_SYNCEN                     0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define  SAI_xCR1_SYNCEN_0                   0x00000400U        /*!<Bit 0 */
+#define  SAI_xCR1_SYNCEN_1                   0x00000800U        /*!<Bit 1 */
+                                             
+#define  SAI_xCR1_MONO                       0x00001000U        /*!<Mono mode                  */
+#define  SAI_xCR1_OUTDRIV                    0x00002000U        /*!<Output Drive               */
+#define  SAI_xCR1_SAIEN                      0x00010000U        /*!<Audio Block enable         */
+#define  SAI_xCR1_DMAEN                      0x00020000U        /*!<DMA enable                 */
+#define  SAI_xCR1_NODIV                      0x00080000U        /*!<No Divider Configuration   */
+                                             
+#define  SAI_xCR1_MCKDIV                     0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
+#define  SAI_xCR1_MCKDIV_0                   0x00100000U        /*!<Bit 0  */
+#define  SAI_xCR1_MCKDIV_1                   0x00200000U        /*!<Bit 1  */
+#define  SAI_xCR1_MCKDIV_2                   0x00400000U        /*!<Bit 2  */
+#define  SAI_xCR1_MCKDIV_3                   0x00800000U        /*!<Bit 3  */
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define  SAI_xCR2_FTH                        0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
+#define  SAI_xCR2_FTH_0                      0x00000001U        /*!<Bit 0 */
+#define  SAI_xCR2_FTH_1                      0x00000002U        /*!<Bit 1 */
+#define  SAI_xCR2_FTH_2                      0x00000004U        /*!<Bit 2 */
+                                             
+#define  SAI_xCR2_FFLUSH                     0x00000008U        /*!<Fifo FLUSH                       */
+#define  SAI_xCR2_TRIS                       0x00000010U        /*!<TRIState Management on data line */
+#define  SAI_xCR2_MUTE                       0x00000020U        /*!<Mute mode                        */
+#define  SAI_xCR2_MUTEVAL                    0x00000040U        /*!<Muate value                      */
+                                             
+#define  SAI_xCR2_MUTECNT                    0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
+#define  SAI_xCR2_MUTECNT_0                  0x00000080U        /*!<Bit 0 */
+#define  SAI_xCR2_MUTECNT_1                  0x00000100U        /*!<Bit 1 */
+#define  SAI_xCR2_MUTECNT_2                  0x00000200U        /*!<Bit 2 */
+#define  SAI_xCR2_MUTECNT_3                  0x00000400U        /*!<Bit 3 */
+#define  SAI_xCR2_MUTECNT_4                  0x00000800U        /*!<Bit 4 */
+#define  SAI_xCR2_MUTECNT_5                  0x00001000U        /*!<Bit 5 */
+                                             
+#define  SAI_xCR2_CPL                        0x00002000U        /*!< Complement Bit             */
+                                             
+#define  SAI_xCR2_COMP                       0x0000C000U        /*!<COMP[1:0] (Companding mode) */
+#define  SAI_xCR2_COMP_0                     0x00004000U        /*!<Bit 0 */
+#define  SAI_xCR2_COMP_1                     0x00008000U        /*!<Bit 1 */
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define  SAI_xFRCR_FRL                       0x000000FFU        /*!<FRL[1:0](Frame length)  */
+#define  SAI_xFRCR_FRL_0                     0x00000001U        /*!<Bit 0 */
+#define  SAI_xFRCR_FRL_1                     0x00000002U        /*!<Bit 1 */
+#define  SAI_xFRCR_FRL_2                     0x00000004U        /*!<Bit 2 */
+#define  SAI_xFRCR_FRL_3                     0x00000008U        /*!<Bit 3 */
+#define  SAI_xFRCR_FRL_4                     0x00000010U        /*!<Bit 4 */
+#define  SAI_xFRCR_FRL_5                     0x00000020U        /*!<Bit 5 */
+#define  SAI_xFRCR_FRL_6                     0x00000040U        /*!<Bit 6 */
+#define  SAI_xFRCR_FRL_7                     0x00000080U        /*!<Bit 7 */
+                                                        
+#define  SAI_xFRCR_FSALL                     0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
+#define  SAI_xFRCR_FSALL_0                   0x00000100U        /*!<Bit 0 */
+#define  SAI_xFRCR_FSALL_1                   0x00000200U        /*!<Bit 1 */
+#define  SAI_xFRCR_FSALL_2                   0x00000400U        /*!<Bit 2 */
+#define  SAI_xFRCR_FSALL_3                   0x00000800U        /*!<Bit 3 */
+#define  SAI_xFRCR_FSALL_4                   0x00001000U        /*!<Bit 4 */
+#define  SAI_xFRCR_FSALL_5                   0x00002000U        /*!<Bit 5 */
+#define  SAI_xFRCR_FSALL_6                   0x00004000U        /*!<Bit 6 */
+                                                        
+#define  SAI_xFRCR_FSDEF                     0x00010000U        /*!<Frame Synchronization Definition  */
+#define  SAI_xFRCR_FSPOL                     0x00020000U        /*!<Frame Synchronization POLarity    */
+#define  SAI_xFRCR_FSOFF                     0x00040000U        /*!<Frame Synchronization OFFset      */
+                                             
+/* Legacy define */                          
+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define  SAI_xSLOTR_FBOFF                    0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
+#define  SAI_xSLOTR_FBOFF_0                  0x00000001U        /*!<Bit 0 */
+#define  SAI_xSLOTR_FBOFF_1                  0x00000002U        /*!<Bit 1 */
+#define  SAI_xSLOTR_FBOFF_2                  0x00000004U        /*!<Bit 2 */
+#define  SAI_xSLOTR_FBOFF_3                  0x00000008U        /*!<Bit 3 */
+#define  SAI_xSLOTR_FBOFF_4                  0x00000010U        /*!<Bit 4 */
+                                            
+#define  SAI_xSLOTR_SLOTSZ                   0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
+#define  SAI_xSLOTR_SLOTSZ_0                 0x00000040U        /*!<Bit 0 */
+#define  SAI_xSLOTR_SLOTSZ_1                 0x00000080U        /*!<Bit 1 */
+                                            
+#define  SAI_xSLOTR_NBSLOT                   0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define  SAI_xSLOTR_NBSLOT_0                 0x00000100U        /*!<Bit 0 */
+#define  SAI_xSLOTR_NBSLOT_1                 0x00000200U        /*!<Bit 1 */
+#define  SAI_xSLOTR_NBSLOT_2                 0x00000400U        /*!<Bit 2 */
+#define  SAI_xSLOTR_NBSLOT_3                 0x00000800U        /*!<Bit 3 */
+                                            
+#define  SAI_xSLOTR_SLOTEN                   0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define  SAI_xIMR_OVRUDRIE                   0x00000001U        /*!<Overrun underrun interrupt enable                              */
+#define  SAI_xIMR_MUTEDETIE                  0x00000002U        /*!<Mute detection interrupt enable                                */
+#define  SAI_xIMR_WCKCFGIE                   0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
+#define  SAI_xIMR_FREQIE                     0x00000008U        /*!<FIFO request interrupt enable                                  */
+#define  SAI_xIMR_CNRDYIE                    0x00000010U        /*!<Codec not ready interrupt enable                               */
+#define  SAI_xIMR_AFSDETIE                   0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
+#define  SAI_xIMR_LFSDETIE                   0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define  SAI_xSR_OVRUDR                      0x00000001U         /*!<Overrun underrun                               */
+#define  SAI_xSR_MUTEDET                     0x00000002U         /*!<Mute detection                                 */
+#define  SAI_xSR_WCKCFG                      0x00000004U         /*!<Wrong Clock Configuration                      */
+#define  SAI_xSR_FREQ                        0x00000008U         /*!<FIFO request                                   */
+#define  SAI_xSR_CNRDY                       0x00000010U         /*!<Codec not ready                                */
+#define  SAI_xSR_AFSDET                      0x00000020U         /*!<Anticipated frame synchronization detection    */
+#define  SAI_xSR_LFSDET                      0x00000040U         /*!<Late frame synchronization detection           */
+                                             
+#define  SAI_xSR_FLVL                        0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define  SAI_xSR_FLVL_0                      0x00010000U         /*!<Bit 0 */
+#define  SAI_xSR_FLVL_1                      0x00020000U         /*!<Bit 1 */
+#define  SAI_xSR_FLVL_2                      0x00040000U         /*!<Bit 2 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define  SAI_xCLRFR_COVRUDR                  0x00000001U        /*!<Clear Overrun underrun                               */
+#define  SAI_xCLRFR_CMUTEDET                 0x00000002U        /*!<Clear Mute detection                                 */
+#define  SAI_xCLRFR_CWCKCFG                  0x00000004U        /*!<Clear Wrong Clock Configuration                      */
+#define  SAI_xCLRFR_CFREQ                    0x00000008U        /*!<Clear FIFO request                                   */
+#define  SAI_xCLRFR_CCNRDY                   0x00000010U        /*!<Clear Codec not ready                                */
+#define  SAI_xCLRFR_CAFSDET                  0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
+#define  SAI_xCLRFR_CLFSDET                  0x00000040U        /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  *********************/
+#define  SAI_xDR_DATA                        0xFFFFFFFFU        
+
+/******************************************************************************/
+/*                                                                            */
+/*                              SPDIF-RX Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SPDIF_CR register  *******************/
+#define  SPDIFRX_CR_SPDIFEN                0x00000003U        /*!<Peripheral Block Enable                      */
+#define  SPDIFRX_CR_RXDMAEN                0x00000004U        /*!<Receiver DMA Enable for data flow            */
+#define  SPDIFRX_CR_RXSTEO                 0x00000008U        /*!<Stereo Mode                                  */
+#define  SPDIFRX_CR_DRFMT                  0x00000030U        /*!<RX Data format                               */
+#define  SPDIFRX_CR_PMSK                   0x00000040U        /*!<Mask Parity error bit                        */
+#define  SPDIFRX_CR_VMSK                   0x00000080U        /*!<Mask of Validity bit                         */
+#define  SPDIFRX_CR_CUMSK                  0x00000100U        /*!<Mask of channel status and user bits         */
+#define  SPDIFRX_CR_PTMSK                  0x00000200U        /*!<Mask of Preamble Type bits                   */
+#define  SPDIFRX_CR_CBDMAEN                0x00000400U        /*!<Control Buffer DMA ENable for control flow   */
+#define  SPDIFRX_CR_CHSEL                  0x00000800U        /*!<Channel Selection                            */
+#define  SPDIFRX_CR_NBTR                   0x00003000U        /*!<Maximum allowed re-tries during synchronization phase */
+#define  SPDIFRX_CR_WFA                    0x00004000U        /*!<Wait For Activity     */
+#define  SPDIFRX_CR_INSEL                  0x00070000U        /*!<SPDIF input selection */
+
+/*******************  Bit definition for SPDIFRX_IMR register  *******************/
+#define  SPDIFRX_IMR_RXNEIE                0x00000001U        /*!<RXNE interrupt enable                              */
+#define  SPDIFRX_IMR_CSRNEIE               0x00000002U        /*!<Control Buffer Ready Interrupt Enable              */
+#define  SPDIFRX_IMR_PERRIE                0x00000004U        /*!<Parity error interrupt enable                      */
+#define  SPDIFRX_IMR_OVRIE                 0x00000008U        /*!<Overrun error Interrupt Enable                     */
+#define  SPDIFRX_IMR_SBLKIE                0x00000010U        /*!<Synchronization Block Detected Interrupt Enable    */
+#define  SPDIFRX_IMR_SYNCDIE               0x00000020U        /*!<Synchronization Done                               */
+#define  SPDIFRX_IMR_IFEIE                 0x00000040U        /*!<Serial Interface Error Interrupt Enable            */
+
+/*******************  Bit definition for SPDIFRX_SR register  *******************/
+#define  SPDIFRX_SR_RXNE                   0x00000001U       /*!<Read data register not empty                          */
+#define  SPDIFRX_SR_CSRNE                  0x00000002U       /*!<The Control Buffer register is not empty              */
+#define  SPDIFRX_SR_PERR                   0x00000004U       /*!<Parity error                                          */
+#define  SPDIFRX_SR_OVR                    0x00000008U       /*!<Overrun error                                         */
+#define  SPDIFRX_SR_SBD                    0x00000010U       /*!<Synchronization Block Detected                        */
+#define  SPDIFRX_SR_SYNCD                  0x00000020U       /*!<Synchronization Done                                  */
+#define  SPDIFRX_SR_FERR                   0x00000040U       /*!<Framing error                                         */
+#define  SPDIFRX_SR_SERR                   0x00000080U       /*!<Synchronization error                                 */
+#define  SPDIFRX_SR_TERR                   0x00000100U       /*!<Time-out error                                        */
+#define  SPDIFRX_SR_WIDTH5                 0x7FFF0000U       /*!<Duration of 5 symbols counted with spdif_clk          */
+
+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
+#define  SPDIFRX_IFCR_PERRCF               0x00000004U       /*!<Clears the Parity error flag                         */
+#define  SPDIFRX_IFCR_OVRCF                0x00000008U       /*!<Clears the Overrun error flag                        */
+#define  SPDIFRX_IFCR_SBDCF                0x00000010U       /*!<Clears the Synchronization Block Detected flag       */
+#define  SPDIFRX_IFCR_SYNCDCF              0x00000020U       /*!<Clears the Synchronization Done flag                 */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
+#define  SPDIFRX_DR0_DR                    0x00FFFFFFU        /*!<Data value            */
+#define  SPDIFRX_DR0_PE                    0x01000000U        /*!<Parity Error bit      */
+#define  SPDIFRX_DR0_V                     0x02000000U        /*!<Validity bit          */
+#define  SPDIFRX_DR0_U                     0x04000000U        /*!<User bit              */
+#define  SPDIFRX_DR0_C                     0x08000000U        /*!<Channel Status bit    */
+#define  SPDIFRX_DR0_PT                    0x30000000U        /*!<Preamble Type         */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
+#define  SPDIFRX_DR1_DR                    0xFFFFFF00U        /*!<Data value            */
+#define  SPDIFRX_DR1_PT                    0x00000030U        /*!<Preamble Type         */
+#define  SPDIFRX_DR1_C                     0x00000008U        /*!<Channel Status bit    */
+#define  SPDIFRX_DR1_U                     0x00000004U        /*!<User bit              */
+#define  SPDIFRX_DR1_V                     0x00000002U        /*!<Validity bit          */
+#define  SPDIFRX_DR1_PE                    0x00000001U        /*!<Parity Error bit      */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
+#define  SPDIFRX_DR1_DRNL1                 0xFFFF0000U        /*!<Data value Channel B      */
+#define  SPDIFRX_DR1_DRNL2                 0x0000FFFFU        /*!<Data value Channel A      */
+
+/*******************  Bit definition for SPDIFRX_CSR register   *******************/
+#define  SPDIFRX_CSR_USR                   0x0000FFFFU        /*!<User data information           */
+#define  SPDIFRX_CSR_CS                    0x00FF0000U        /*!<Channel A status information    */
+#define  SPDIFRX_CSR_SOB                   0x01000000U        /*!<Start Of Block                  */
+
+/*******************  Bit definition for SPDIFRX_DIR register    *******************/
+#define  SPDIFRX_DIR_THI                   0x000013FFU        /*!<Threshold LOW      */
+#define  SPDIFRX_DIR_TLO                   0x1FFF0000U        /*!<Threshold HIGH     */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          SD host Interface                                 */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDMMC_POWER register  ******************/
+#define  SDMMC_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDMMC_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
+#define  SDMMC_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
+
+/******************  Bit definition for SDMMC_CLKCR register  ******************/
+#define  SDMMC_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
+#define  SDMMC_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
+#define  SDMMC_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
+#define  SDMMC_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
+         
+#define  SDMMC_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDMMC_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
+#define  SDMMC_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
+         
+#define  SDMMC_CLKCR_NEGEDGE                  0x2000U            /*!<SDMMC_CK dephasing selection bit */
+#define  SDMMC_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
+
+/*******************  Bit definition for SDMMC_ARG register  *******************/
+#define  SDMMC_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
+
+/*******************  Bit definition for SDMMC_CMD register  *******************/
+#define  SDMMC_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
+         
+#define  SDMMC_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDMMC_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
+#define  SDMMC_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
+         
+#define  SDMMC_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDMMC_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDMMC_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDMMC_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
+
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
+#define  SDMMC_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
+
+/******************  Bit definition for SDMMC_RESP0 register  ******************/
+#define  SDMMC_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP1 register  ******************/
+#define  SDMMC_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP2 register  ******************/
+#define  SDMMC_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP3 register  ******************/
+#define  SDMMC_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP4 register  ******************/
+#define  SDMMC_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
+
+/******************  Bit definition for SDMMC_DTIMER register  *****************/
+#define  SDMMC_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
+
+/******************  Bit definition for SDMMC_DLEN register  *******************/
+#define  SDMMC_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
+
+/******************  Bit definition for SDMMC_DCTRL register  ******************/
+#define  SDMMC_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
+#define  SDMMC_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
+#define  SDMMC_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
+#define  SDMMC_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
+
+#define  SDMMC_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDMMC_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
+#define  SDMMC_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
+#define  SDMMC_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
+#define  SDMMC_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
+
+#define  SDMMC_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
+#define  SDMMC_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
+#define  SDMMC_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
+#define  SDMMC_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
+
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/
+#define  SDMMC_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
+
+/******************  Bit definition for SDMMC_STA registe  ********************/
+#define  SDMMC_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
+#define  SDMMC_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
+#define  SDMMC_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
+#define  SDMMC_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
+#define  SDMMC_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
+#define  SDMMC_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
+#define  SDMMC_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
+#define  SDMMC_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
+#define  SDMMC_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDMMC_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
+#define  SDMMC_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
+#define  SDMMC_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
+#define  SDMMC_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
+#define  SDMMC_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDMMC_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDMMC_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
+#define  SDMMC_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
+#define  SDMMC_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
+#define  SDMMC_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
+#define  SDMMC_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
+#define  SDMMC_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
+#define  SDMMC_STA_SDIOIT                     0x00400000U        /*!<SDMMC interrupt received                       */
+
+/*******************  Bit definition for SDMMC_ICR register  *******************/
+#define  SDMMC_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
+#define  SDMMC_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
+#define  SDMMC_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
+#define  SDMMC_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
+#define  SDMMC_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
+#define  SDMMC_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
+#define  SDMMC_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
+#define  SDMMC_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
+#define  SDMMC_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
+#define  SDMMC_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
+#define  SDMMC_ICR_SDIOITC                    0x00400000U        /*!<SDMMCIT flag clear bit   */
+
+/******************  Bit definition for SDMMC_MASK register  *******************/
+#define  SDMMC_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDMMC_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDMMC_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
+#define  SDMMC_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
+#define  SDMMC_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDMMC_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDMMC_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
+#define  SDMMC_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
+#define  SDMMC_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
+#define  SDMMC_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
+#define  SDMMC_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
+#define  SDMMC_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDMMC_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
+#define  SDMMC_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDMMC_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDMMC_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDMMC_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDMMC_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDMMC_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDMMC_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDMMC_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDMMC_MASK_SDIOITIE                  0x00400000U        /*!<SDMMC Mode Interrupt Received interrupt Enable */
+
+/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/
+#define  SDMMC_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDMMC_FIFO register  *******************/
+#define  SDMMC_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        0x00000001U        /*!< Clock Phase                        */
+#define  SPI_CR1_CPOL                        0x00000002U        /*!< Clock Polarity                     */
+#define  SPI_CR1_MSTR                        0x00000004U        /*!< Master Selection                   */
+#define  SPI_CR1_BR                          0x00000038U        /*!< BR[2:0] bits (Baud Rate Control)   */
+#define  SPI_CR1_BR_0                        0x00000008U        /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        0x00000010U        /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        0x00000020U        /*!< Bit 2 */
+#define  SPI_CR1_SPE                         0x00000040U        /*!< SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    0x00000080U        /*!< Frame Format                        */
+#define  SPI_CR1_SSI                         0x00000100U        /*!< Internal slave select               */
+#define  SPI_CR1_SSM                         0x00000200U        /*!< Software slave management           */
+#define  SPI_CR1_RXONLY                      0x00000400U        /*!< Receive only                        */
+#define  SPI_CR1_CRCL                        0x00000800U        /*!< CRC Length                          */
+#define  SPI_CR1_CRCNEXT                     0x00001000U        /*!< Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       0x00002000U        /*!< Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      0x00004000U        /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    0x00008000U        /*!< Bidirectional data mode enable      */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     0x00000001U        /*!< Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     0x00000002U        /*!< Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        0x00000004U        /*!< SS Output Enable                     */
+#define  SPI_CR2_NSSP                        0x00000008U        /*!< NSS pulse management Enable          */
+#define  SPI_CR2_FRF                         0x00000010U        /*!< Frame Format Enable                  */
+#define  SPI_CR2_ERRIE                       0x00000020U        /*!< Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      0x00000040U        /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       0x00000080U        /*!< Tx buffer Empty Interrupt Enable     */
+#define  SPI_CR2_DS                          0x00000F00U        /*!< DS[3:0] Data Size                    */
+#define  SPI_CR2_DS_0                        0x00000100U        /*!< Bit 0 */
+#define  SPI_CR2_DS_1                        0x00000200U        /*!< Bit 1 */
+#define  SPI_CR2_DS_2                        0x00000400U        /*!< Bit 2 */
+#define  SPI_CR2_DS_3                        0x00000800U        /*!< Bit 3 */
+#define  SPI_CR2_FRXTH                       0x00001000U        /*!< FIFO reception Threshold           */
+#define  SPI_CR2_LDMARX                      0x00002000U        /*!< Last DMA transfer for reception    */
+#define  SPI_CR2_LDMATX                      0x00004000U        /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         0x00000001U        /*!< Receive buffer Not Empty  */
+#define  SPI_SR_TXE                          0x00000002U        /*!< Transmit buffer Empty     */
+#define  SPI_SR_CHSIDE                       0x00000004U        /*!< Channel side              */
+#define  SPI_SR_UDR                          0x00000008U        /*!< Underrun flag             */
+#define  SPI_SR_CRCERR                       0x00000010U        /*!< CRC Error flag            */
+#define  SPI_SR_MODF                         0x00000020U        /*!< Mode fault                */
+#define  SPI_SR_OVR                          0x00000040U        /*!< Overrun flag              */
+#define  SPI_SR_BSY                          0x00000080U        /*!< Busy flag                 */
+#define  SPI_SR_FRE                          0x00000100U        /*!< TI frame format error     */
+#define  SPI_SR_FRLVL                        0x00000600U        /*!< FIFO Reception Level      */
+#define  SPI_SR_FRLVL_0                      0x00000200U        /*!< Bit 0 */
+#define  SPI_SR_FRLVL_1                      0x00000400U        /*!< Bit 1 */
+#define  SPI_SR_FTLVL                        0x00001800U        /*!< FIFO Transmission Level   */
+#define  SPI_SR_FTLVL_0                      0x00000800U        /*!< Bit 0 */
+#define  SPI_SR_FTLVL_1                      0x00001000U        /*!< Bit 1 */  
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           0xFFFFU            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   0xFFFFU            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    0xFFFFU            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    0xFFFFU            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   0x00000001U        /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_DATLEN                  0x00000006U        /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                0x00000002U        /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                0x00000004U        /*!<Bit 1 */
+#define  SPI_I2SCFGR_CKPOL                   0x00000008U        /*!<steady state clock polarity                       */
+#define  SPI_I2SCFGR_I2SSTD                  0x00000030U        /*!<I2SSTD[1:0] bits (I2S standard selection)         */
+#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U        /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U        /*!<Bit 1 */
+#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U        /*!<PCM frame synchronization                         */
+#define  SPI_I2SCFGR_I2SCFG                  0x00000300U        /*!<I2SCFG[1:0] bits (I2S configuration mode)         */
+#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U        /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U        /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SE                    0x00000400U        /*!<I2S Enable                                        */
+#define  SPI_I2SCFGR_I2SMOD                  0x00000800U        /*!<I2S mode selection                                */
+#define  SPI_I2SCFGR_ASTRTEN                 0x00001000U        /*!<Asynchronous start enable                        */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    0x00FFU            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       0x0100U            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     0x0200U            /*!<Master Clock Output Enable   */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
+#define SYSCFG_MEMRMP_MEM_BOOT         0x00000001U /*!< Boot information after Reset */
+
+#define SYSCFG_MEMRMP_SWP_FB           0x00000100U /*!< User Flash Bank swap    */
+
+#define SYSCFG_MEMRMP_SWP_FMC          0x00000C00U /*!< FMC Memory Mapping swapping */
+#define SYSCFG_MEMRMP_SWP_FMC_0        0x00000400U 
+#define SYSCFG_MEMRMP_SWP_FMC_1        0x00000800U 
+
+/******************  Bit definition for SYSCFG_PMC register  ******************/
+#define SYSCFG_PMC_I2C1_FMP             0x00000001U /*!< I2C1_FMP I2C1 Fast Mode + Enable */
+#define SYSCFG_PMC_I2C2_FMP             0x00000002U /*!< I2C2_FMP I2C2 Fast Mode + Enable */
+#define SYSCFG_PMC_I2C3_FMP             0x00000004U /*!< I2C3_FMP I2C3 Fast Mode + Enable */
+#define SYSCFG_PMC_I2C4_FMP             0x00000008U /*!< I2C4_FMP I2C4 Fast Mode + Enable */
+#define SYSCFG_PMC_I2C_PB6_FMP          0x00000010U /*!< PB6_FMP Fast Mode + Enable */
+#define SYSCFG_PMC_I2C_PB7_FMP          0x00000020U /*!< PB7_FMP Fast Mode + Enable */
+#define SYSCFG_PMC_I2C_PB8_FMP          0x00000040U /*!< PB8_FMP Fast Mode + Enable */
+#define SYSCFG_PMC_I2C_PB9_FMP          0x00000080U /*!< PB9_FMP Fast Mode + Enable */
+
+#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
+
+#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
+/** 
+  * @brief   EXTI0 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
+
+/** 
+  * @brief   EXTI1 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
+
+/** 
+  * @brief   EXTI2 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
+
+/** 
+  * @brief   EXTI3 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
+/** 
+  * @brief   EXTI4 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
+
+/** 
+  * @brief   EXTI5 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
+
+/** 
+  * @brief   EXTI6 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
+
+/** 
+  * @brief   EXTI7 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
+           
+/** 
+  * @brief   EXTI8 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
+
+/** 
+  * @brief   EXTI9 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
+
+/** 
+  * @brief   EXTI10 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
+
+/** 
+  * @brief   EXTI11 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
+
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
+/** 
+  * @brief   EXTI12 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
+
+/** 
+  * @brief   EXTI13 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        0x0080U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        0x0090U /*!<PJ[13] pin */
+
+/** 
+  * @brief   EXTI14 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
+
+/** 
+  * @brief   EXTI15 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
+
+/******************  Bit definition for SYSCFG_CBR register  ******************/  
+#define SYSCFG_CBR_CLL                  0x00000001U /*!<Core Lockup Lock */
+#define SYSCFG_CBR_PVDL                 0x00000004U /*!<PVD Lock         */
+
+/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
+#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell power-down */
+#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell ready flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
+#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
+#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
+
+#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
+
+#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
+#define  TIM_CR1_UIFREMAP                    0x0800U            /*!<UIF status bit */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        0x00000001U            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        0x00000004U            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        0x00000008U            /*!<Capture/Compare DMA Selection            */
+
+#define  TIM_CR2_OIS5                        0x00010000U            /*!<Output Idle state 4 (OC4 output) */
+#define  TIM_CR2_OIS6                        0x00040000U            /*!<Output Idle state 4 (OC4 output) */
+
+#define  TIM_CR2_MMS                         0x0070U           /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       0x0010U           /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       0x0020U           /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       0x0040U           /*!<Bit 2 */
+
+#define  TIM_CR2_MMS2                        0x00F00000U            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS2_0                      0x00100000U            /*!<Bit 0 */
+#define  TIM_CR2_MMS2_1                      0x00200000U            /*!<Bit 1 */
+#define  TIM_CR2_MMS2_2                      0x00400000U            /*!<Bit 2 */
+#define  TIM_CR2_MMS2_3                      0x00800000U            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        0x00010007U            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      0x00000001U            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      0x00000002U            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      0x00000004U            /*!<Bit 2 */
+#define  TIM_SMCR_SMS_3                      0x00010000U            /*!<Bit 3 */
+#define  TIM_SMCR_OCCS                       0x00000008U            /*!< OCREF clear selection */
+
+#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
+
+#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
+#define  TIM_SR_B2IF                         0x0100U            /*!<Break2 interrupt Flag               */
+#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          0x00000001U               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        0x00000002U               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        0x00000004U               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        0x00000008U               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        0x00000010U               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        0x00000020U               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          0x00000040U               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          0x00000080U               /*!<Break Generation                          */
+#define  TIM_EGR_B2G                         0x00000100U              /*!<Break2 Generation                          */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      0x00000003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    0x00000001U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    0x00000002U            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     0x00000004U            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     0x00000008U            /*!<Output Compare 1 Preload enable              */
+
+#define  TIM_CCMR1_OC1M                      0x00010070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    0x00000010U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    0x00000020U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    0x00000040U            /*!<Bit 2 */
+#define  TIM_CCMR1_OC1M_3                    0x00010000U            /*!<Bit 3 */
+
+#define  TIM_CCMR1_OC1CE                     0x00000080U            /*!<Output Compare 1Clear Enable                 */
+
+#define  TIM_CCMR1_CC2S                      0x00000300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    0x00000100U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    0x00000200U            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     0x00000400U            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     0x00000800U            /*!<Output Compare 2 Preload enable              */
+
+#define  TIM_CCMR1_OC2M                      0x01007000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    0x00001000U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    0x00002000U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    0x00004000U            /*!<Bit 2 */
+#define  TIM_CCMR1_OC2M_3                    0x01000000U            /*!<Bit 3 */
+
+#define  TIM_CCMR1_OC2CE                     0x00008000U            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      0x00000003U        /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    0x00000001U        /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    0x00000002U        /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     0x00000004U        /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     0x00000008U        /*!<Output Compare 3 Preload enable        */
+
+#define  TIM_CCMR2_OC3M                      0x00010070U        /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    0x00000010U        /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    0x00000020U        /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    0x00000040U        /*!<Bit 2 */
+#define  TIM_CCMR2_OC3M_3                    0x00010000U        /*!<Bit 3 */
+
+
+
+#define  TIM_CCMR2_OC3CE                     0x00000080U        /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      0x00000300U        /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    0x00000100U        /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    0x00000200U        /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     0x00000400U        /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     0x00000800U        /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      0x01007000U        /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    0x00001000U        /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    0x00002000U        /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    0x00004000U        /*!<Bit 2 */
+#define  TIM_CCMR2_OC4M_3                    0x01000000U        /*!<Bit 3 */
+
+#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       0x00000001U            /*!<Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       0x00000002U            /*!<Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      0x00000004U            /*!<Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      0x00000008U            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       0x00000010U            /*!<Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       0x00000020U            /*!<Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      0x00000040U            /*!<Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      0x00000080U            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       0x00000100U            /*!<Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       0x00000200U            /*!<Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      0x00000400U            /*!<Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      0x00000800U            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       0x00001000U            /*!<Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       0x00002000U            /*!<Capture/Compare 4 output Polarity */
+#define  TIM_CCER_CC4NP                      0x00008000U            /*!<Capture/Compare 4 Complementary output Polarity */
+#define  TIM_CCER_CC5E                       0x00010000U            /*!<Capture/Compare 5 output enable */
+#define  TIM_CCER_CC5P                       0x00020000U            /*!<Capture/Compare 5 output Polarity */
+#define  TIM_CCER_CC6E                       0x00100000U            /*!<Capture/Compare 6 output enable */
+#define  TIM_CCER_CC6P                       0x00200000U            /*!<Capture/Compare 6 output Polarity */
+
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFFU)               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        0x000000FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      0x00000001U            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      0x00000002U            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      0x00000004U            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      0x00000008U            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      0x00000010U            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      0x00000020U            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      0x00000040U            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      0x00000080U            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       0x00000300U            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     0x00000100U            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     0x00000200U            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       0x00000400U            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       0x00000800U            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        0x00001000U            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        0x00002000U            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        0x00004000U            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        0x00008000U            /*!<Main Output enable                */
+#define  TIM_BDTR_BKF                        0x000F0000U            /*!<Break Filter for Break1 */
+#define  TIM_BDTR_BK2F                       0x00F00000U            /*!<Break Filter for Break2 */
+#define  TIM_BDTR_BK2E                       0x01000000U            /*!<Break enable for Break2 */
+#define  TIM_BDTR_BK2P                       0x02000000U            /*!<Break Polarity for Break2 */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
+
+/*******************  Bit definition for TIM_OR regiter  *********************/
+#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define  TIM_CCMR3_OC5FE                     0x00000004U            /*!<Output Compare 5 Fast enable */
+#define  TIM_CCMR3_OC5PE                     0x00000008U            /*!<Output Compare 5 Preload enable */
+
+#define  TIM_CCMR3_OC5M                      0x00010070U            /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define  TIM_CCMR3_OC5M_0                    0x00000010U            /*!<Bit 0 */
+#define  TIM_CCMR3_OC5M_1                    0x00000020U            /*!<Bit 1 */
+#define  TIM_CCMR3_OC5M_2                    0x00000040U            /*!<Bit 2 */
+#define  TIM_CCMR3_OC5M_3                    0x00010000U            /*!<Bit 3 */
+
+#define  TIM_CCMR3_OC5CE                     0x00000080U            /*!<Output Compare 5 Clear Enable */
+
+#define  TIM_CCMR3_OC6FE                     0x00000400U            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR3_OC6PE                     0x00000800U            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR3_OC6M                      0x01007000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR3_OC6M_0                    0x00001000U            /*!<Bit 0 */
+#define  TIM_CCMR3_OC6M_1                    0x00002000U            /*!<Bit 1 */
+#define  TIM_CCMR3_OC6M_2                    0x00004000U            /*!<Bit 2 */
+#define  TIM_CCMR3_OC6M_3                    0x01000000U            /*!<Bit 3 */
+
+#define  TIM_CCMR3_OC6CE                     0x00008000U            /*!<Output Compare 4 Clear Enable */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define  TIM_CCR5_CCR5                       0xFFFFFFFFU        /*!<Capture/Compare 5 Value */
+#define  TIM_CCR5_GC5C1                      0x20000000U        /*!<Group Channel 5 and Channel 1 */
+#define  TIM_CCR5_GC5C2                      0x40000000U        /*!<Group Channel 5 and Channel 2 */
+#define  TIM_CCR5_GC5C3                      0x80000000U        /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define  TIM_CCR6_CCR6                       ((uint16_t)0xFFFFU)            /*!<Capture/Compare 6 Value */
+
+/*******************  Bit definition for TIM1_AF1 register  *******************/
+#define TIM1_AF1_BKINE                       0x00000001U        /*!<BRK BKIN input enable */
+#define TIM1_AF1_BKDF1BKE                    0x00000100U        /*!<BRK DFSDM1_BREAK enable */
+
+/*******************  Bit definition for TIM1_AF2 register  *******************/
+#define TIM1_AF2_BK2INE                      0x00000001U        /*!<BRK2 BKIN input enable */
+#define TIM1_AF2_BK2DF1BKE                   0x00000100U        /*!<BRK2 DFSDM1_BREAK enable */
+
+/*******************  Bit definition for TIM8_AF1 register  *******************/
+#define TIM8_AF1_BKINE                       0x00000001U        /*!<BRK BKIN input enable */
+#define TIM8_AF1_BKDF1BKE                    0x00000100U        /*!<BRK DFSDM1_BREAK enable */
+
+/*******************  Bit definition for TIM8_AF2 register  *******************/
+#define TIM8_AF2_BK2INE                      0x00000001U        /*!<BRK2 BKIN2 input enable */
+#define TIM8_AF2_BK2DF1BKE                   0x00000100U        /*!<BRK2 DFSDM1_BREAK enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTIM)                            */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define  LPTIM_ISR_CMPM                         0x00000001U            /*!< Compare match                       */
+#define  LPTIM_ISR_ARRM                         0x00000002U            /*!< Autoreload match                    */
+#define  LPTIM_ISR_EXTTRIG                      0x00000004U            /*!< External trigger edge event         */
+#define  LPTIM_ISR_CMPOK                        0x00000008U            /*!< Compare register update OK          */
+#define  LPTIM_ISR_ARROK                        0x00000010U            /*!< Autoreload register update OK       */
+#define  LPTIM_ISR_UP                           0x00000020U            /*!< Counter direction change down to up */
+#define  LPTIM_ISR_DOWN                         0x00000040U            /*!< Counter direction change up to down */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define  LPTIM_ICR_CMPMCF                       0x00000001U            /*!< Compare match Clear Flag                       */
+#define  LPTIM_ICR_ARRMCF                       0x00000002U            /*!< Autoreload match Clear Flag                    */
+#define  LPTIM_ICR_EXTTRIGCF                    0x00000004U            /*!< External trigger edge event Clear Flag         */
+#define  LPTIM_ICR_CMPOKCF                      0x00000008U            /*!< Compare register update OK Clear Flag          */
+#define  LPTIM_ICR_ARROKCF                      0x00000010U            /*!< Autoreload register update OK Clear Flag       */
+#define  LPTIM_ICR_UPCF                         0x00000020U            /*!< Counter direction change down to up Clear Flag */
+#define  LPTIM_ICR_DOWNCF                       0x00000040U            /*!< Counter direction change up to down Clear Flag */
+
+/******************  Bit definition for LPTIM_IER register *******************/
+#define  LPTIM_IER_CMPMIE                       0x00000001U            /*!< Compare match Interrupt Enable                       */
+#define  LPTIM_IER_ARRMIE                       0x00000002U            /*!< Autoreload match Interrupt Enable                    */
+#define  LPTIM_IER_EXTTRIGIE                    0x00000004U            /*!< External trigger edge event Interrupt Enable         */
+#define  LPTIM_IER_CMPOKIE                      0x00000008U            /*!< Compare register update OK Interrupt Enable          */
+#define  LPTIM_IER_ARROKIE                      0x00000010U            /*!< Autoreload register update OK Interrupt Enable       */
+#define  LPTIM_IER_UPIE                         0x00000020U            /*!< Counter direction change down to up Interrupt Enable */
+#define  LPTIM_IER_DOWNIE                       0x00000040U            /*!< Counter direction change up to down Interrupt Enable */
+
+/******************  Bit definition for LPTIM_CFGR register*******************/
+#define  LPTIM_CFGR_CKSEL                       0x00000001U             /*!< Clock selector */
+
+#define  LPTIM_CFGR_CKPOL                       0x00000006U             /*!< CKPOL[1:0] bits (Clock polarity) */
+#define  LPTIM_CFGR_CKPOL_0                     0x00000002U             /*!< Bit 0 */
+#define  LPTIM_CFGR_CKPOL_1                     0x00000004U             /*!< Bit 1 */
+
+#define  LPTIM_CFGR_CKFLT                       0x00000018U             /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define  LPTIM_CFGR_CKFLT_0                     0x00000008U             /*!< Bit 0 */
+#define  LPTIM_CFGR_CKFLT_1                     0x00000010U             /*!< Bit 1 */
+
+#define  LPTIM_CFGR_TRGFLT                      0x000000C0U             /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define  LPTIM_CFGR_TRGFLT_0                    0x00000040U             /*!< Bit 0 */
+#define  LPTIM_CFGR_TRGFLT_1                    0x00000080U             /*!< Bit 1 */
+
+#define  LPTIM_CFGR_PRESC                       0x00000E00U             /*!< PRESC[2:0] bits (Clock prescaler) */
+#define  LPTIM_CFGR_PRESC_0                     0x00000200U             /*!< Bit 0 */
+#define  LPTIM_CFGR_PRESC_1                     0x00000400U             /*!< Bit 1 */
+#define  LPTIM_CFGR_PRESC_2                     0x00000800U             /*!< Bit 2 */
+
+#define  LPTIM_CFGR_TRIGSEL                     0x0000E000U             /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define  LPTIM_CFGR_TRIGSEL_0                   0x00002000U             /*!< Bit 0 */
+#define  LPTIM_CFGR_TRIGSEL_1                   0x00004000U             /*!< Bit 1 */
+#define  LPTIM_CFGR_TRIGSEL_2                   0x00008000U             /*!< Bit 2 */
+
+#define  LPTIM_CFGR_TRIGEN                      0x00060000U             /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define  LPTIM_CFGR_TRIGEN_0                    0x00020000U             /*!< Bit 0 */
+#define  LPTIM_CFGR_TRIGEN_1                    0x00040000U             /*!< Bit 1 */
+
+#define  LPTIM_CFGR_TIMOUT                      0x00080000U             /*!< Timout enable           */
+#define  LPTIM_CFGR_WAVE                        0x00100000U             /*!< Waveform shape          */
+#define  LPTIM_CFGR_WAVPOL                      0x00200000U             /*!< Waveform shape polarity */
+#define  LPTIM_CFGR_PRELOAD                     0x00400000U             /*!< Reg update mode         */
+#define  LPTIM_CFGR_COUNTMODE                   0x00800000U             /*!< Counter mode enable     */     
+#define  LPTIM_CFGR_ENC                         0x01000000U             /*!< Encoder mode enable     */          
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define  LPTIM_CR_ENABLE                        0x00000001U             /*!< LPTIMer enable                 */
+#define  LPTIM_CR_SNGSTRT                       0x00000002U             /*!< Timer start in single mode     */
+#define  LPTIM_CR_CNTSTRT                       0x00000004U             /*!< Timer start in continuous mode */
+
+/******************  Bit definition for LPTIM_CMP register *******************/
+#define  LPTIM_CMP_CMP                          0x0000FFFFU             /*!< Compare register     */
+
+/******************  Bit definition for LPTIM_ARR register *******************/
+#define  LPTIM_ARR_ARR                          0x0000FFFFU             /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register *******************/
+#define  LPTIM_CNT_CNT                          0x0000FFFFU             /*!< Counter register     */
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_UE                        0x00000001U            /*!< USART Enable                                    */
+#define  USART_CR1_RE                        0x00000004U            /*!< Receiver Enable                                 */
+#define  USART_CR1_TE                        0x00000008U            /*!< Transmitter Enable                              */
+#define  USART_CR1_IDLEIE                    0x00000010U            /*!< IDLE Interrupt Enable                           */
+#define  USART_CR1_RXNEIE                    0x00000020U            /*!< RXNE Interrupt Enable                           */
+#define  USART_CR1_TCIE                      0x00000040U            /*!< Transmission Complete Interrupt Enable          */
+#define  USART_CR1_TXEIE                     0x00000080U            /*!< TXE Interrupt Enable                            */
+#define  USART_CR1_PEIE                      0x00000100U            /*!< PE Interrupt Enable                             */
+#define  USART_CR1_PS                        0x00000200U            /*!< Parity Selection                                */
+#define  USART_CR1_PCE                       0x00000400U            /*!< Parity Control Enable                           */
+#define  USART_CR1_WAKE                      0x00000800U            /*!< Receiver Wakeup method                          */
+#define  USART_CR1_M                         0x10001000U            /*!< Word length                                     */
+#define  USART_CR1_M_0                       0x00001000U            /*!< Word length - Bit 0                             */
+#define  USART_CR1_MME                       0x00002000U            /*!< Mute Mode Enable                                */
+#define  USART_CR1_CMIE                      0x00004000U            /*!< Character match interrupt enable                */
+#define  USART_CR1_OVER8                     0x00008000U            /*!< Oversampling by 8-bit or 16-bit mode            */
+#define  USART_CR1_DEDT                      0x001F0000U            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define  USART_CR1_DEDT_0                    0x00010000U            /*!< Bit 0 */
+#define  USART_CR1_DEDT_1                    0x00020000U            /*!< Bit 1 */
+#define  USART_CR1_DEDT_2                    0x00040000U            /*!< Bit 2 */
+#define  USART_CR1_DEDT_3                    0x00080000U            /*!< Bit 3 */
+#define  USART_CR1_DEDT_4                    0x00100000U            /*!< Bit 4 */
+#define  USART_CR1_DEAT                      0x03E00000U            /*!< DEAT[4:0] bits (Driver Enable Assertion Time)   */
+#define  USART_CR1_DEAT_0                    0x00200000U            /*!< Bit 0 */
+#define  USART_CR1_DEAT_1                    0x00400000U            /*!< Bit 1 */
+#define  USART_CR1_DEAT_2                    0x00800000U            /*!< Bit 2 */
+#define  USART_CR1_DEAT_3                    0x01000000U            /*!< Bit 3 */
+#define  USART_CR1_DEAT_4                    0x02000000U            /*!< Bit 4 */
+#define  USART_CR1_RTOIE                     0x04000000U            /*!< Receive Time Out interrupt enable */
+#define  USART_CR1_EOBIE                     0x08000000U            /*!< End of Block interrupt enable     */
+#define  USART_CR1_M_1                       0x10000000U            /*!< Word length - Bit 1               */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADDM7                     0x00000010U            /*!< 7-bit or 4-bit Address Detection       */
+#define  USART_CR2_LBDL                      0x00000020U            /*!< LIN Break Detection Length             */
+#define  USART_CR2_LBDIE                     0x00000040U            /*!< LIN Break Detection Interrupt Enable   */
+#define  USART_CR2_LBCL                      0x00000100U            /*!< Last Bit Clock pulse                   */
+#define  USART_CR2_CPHA                      0x00000200U            /*!< Clock Phase                            */
+#define  USART_CR2_CPOL                      0x00000400U            /*!< Clock Polarity                         */
+#define  USART_CR2_CLKEN                     0x00000800U            /*!< Clock Enable                           */
+#define  USART_CR2_STOP                      0x00003000U            /*!< STOP[1:0] bits (STOP bits)             */
+#define  USART_CR2_STOP_0                    0x00001000U            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    0x00002000U            /*!< Bit 1 */
+#define  USART_CR2_LINEN                     0x00004000U            /*!< LIN mode enable                        */
+#define  USART_CR2_SWAP                      0x00008000U            /*!< SWAP TX/RX pins                        */
+#define  USART_CR2_RXINV                     0x00010000U            /*!< RX pin active level inversion          */
+#define  USART_CR2_TXINV                     0x00020000U            /*!< TX pin active level inversion          */
+#define  USART_CR2_DATAINV                   0x00040000U            /*!< Binary data inversion                  */
+#define  USART_CR2_MSBFIRST                  0x00080000U            /*!< Most Significant Bit First             */
+#define  USART_CR2_ABREN                     0x00100000U            /*!< Auto Baud-Rate Enable                  */
+#define  USART_CR2_ABRMODE                   0x00600000U            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define  USART_CR2_ABRMODE_0                 0x00200000U            /*!< Bit 0 */
+#define  USART_CR2_ABRMODE_1                 0x00400000U            /*!< Bit 1 */
+#define  USART_CR2_RTOEN                     0x00800000U            /*!< Receiver Time-Out enable  */
+#define  USART_CR2_ADD                       0xFF000000U            /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       0x00000001U            /*!< Error Interrupt Enable                         */
+#define  USART_CR3_IREN                      0x00000002U            /*!< IrDA mode Enable                               */
+#define  USART_CR3_IRLP                      0x00000004U            /*!< IrDA Low-Power                                 */
+#define  USART_CR3_HDSEL                     0x00000008U            /*!< Half-Duplex Selection                          */
+#define  USART_CR3_NACK                      0x00000010U            /*!< SmartCard NACK enable                          */
+#define  USART_CR3_SCEN                      0x00000020U            /*!< SmartCard mode enable                          */
+#define  USART_CR3_DMAR                      0x00000040U            /*!< DMA Enable Receiver                            */
+#define  USART_CR3_DMAT                      0x00000080U            /*!< DMA Enable Transmitter                         */
+#define  USART_CR3_RTSE                      0x00000100U            /*!< RTS Enable                                     */
+#define  USART_CR3_CTSE                      0x00000200U            /*!< CTS Enable                                     */
+#define  USART_CR3_CTSIE                     0x00000400U            /*!< CTS Interrupt Enable                           */
+#define  USART_CR3_ONEBIT                    0x00000800U            /*!< One sample bit method enable                   */
+#define  USART_CR3_OVRDIS                    0x00001000U            /*!< Overrun Disable                                */
+#define  USART_CR3_DDRE                      0x00002000U            /*!< DMA Disable on Reception Error                 */
+#define  USART_CR3_DEM                       0x00004000U            /*!< Driver Enable Mode                             */
+#define  USART_CR3_DEP                       0x00008000U            /*!< Driver Enable Polarity Selection               */
+#define  USART_CR3_SCARCNT                   0x000E0000U            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define  USART_CR3_SCARCNT_0                 0x00020000U            /*!< Bit 0 */
+#define  USART_CR3_SCARCNT_1                 0x00040000U            /*!< Bit 1 */
+#define  USART_CR3_SCARCNT_2                 0x00080000U            /*!< Bit 2 */
+
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_FRACTION              0x000FU                /*!< Fraction of USARTDIV */
+#define  USART_BRR_DIV_MANTISSA              0xFFF0U                /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      0x00FFU                /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_GT                       0xFF00U                /*!< GT[7:0] bits (Guard time value) */
+
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define  USART_RTOR_RTO                      0x00FFFFFFU            /*!< Receiver Time Out Value */
+#define  USART_RTOR_BLEN                     0xFF000000U            /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define  USART_RQR_ABRRQ                     0x0001U                /*!< Auto-Baud Rate Request      */
+#define  USART_RQR_SBKRQ                     0x0002U                /*!< Send Break Request          */
+#define  USART_RQR_MMRQ                      0x0004U                /*!< Mute Mode Request           */
+#define  USART_RQR_RXFRQ                     0x0008U                /*!< Receive Data flush Request  */
+#define  USART_RQR_TXFRQ                     0x0010U                /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define  USART_ISR_PE                        0x00000001U            /*!< Parity Error                        */
+#define  USART_ISR_FE                        0x00000002U            /*!< Framing Error                       */
+#define  USART_ISR_NE                        0x00000004U            /*!< Noise detected Flag                 */
+#define  USART_ISR_ORE                       0x00000008U            /*!< OverRun Error                       */
+#define  USART_ISR_IDLE                      0x00000010U            /*!< IDLE line detected                  */
+#define  USART_ISR_RXNE                      0x00000020U            /*!< Read Data Register Not Empty        */
+#define  USART_ISR_TC                        0x00000040U            /*!< Transmission Complete               */
+#define  USART_ISR_TXE                       0x00000080U            /*!< Transmit Data Register Empty        */
+#define  USART_ISR_LBDF                      0x00000100U            /*!< LIN Break Detection Flag            */
+#define  USART_ISR_CTSIF                     0x00000200U            /*!< CTS interrupt flag                  */
+#define  USART_ISR_CTS                       0x00000400U            /*!< CTS flag                            */
+#define  USART_ISR_RTOF                      0x00000800U            /*!< Receiver Time Out                   */
+#define  USART_ISR_EOBF                      0x00001000U            /*!< End Of Block Flag                   */
+#define  USART_ISR_ABRE                      0x00004000U            /*!< Auto-Baud Rate Error                */
+#define  USART_ISR_ABRF                      0x00008000U            /*!< Auto-Baud Rate Flag                 */
+#define  USART_ISR_BUSY                      0x00010000U            /*!< Busy Flag                           */
+#define  USART_ISR_CMF                       0x00020000U            /*!< Character Match Flag                */
+#define  USART_ISR_SBKF                      0x00040000U            /*!< Send Break Flag                     */
+#define  USART_ISR_RWU                       0x00080000U            /*!< Receive Wake Up from mute mode Flag */
+#define  USART_ISR_WUF                       0x00100000U            /*!< Wake Up from stop mode Flag         */
+#define  USART_ISR_TEACK                     0x00200000U            /*!< Transmit Enable Acknowledge Flag    */
+#define  USART_ISR_REACK                     0x00400000U            /*!< Receive Enable Acknowledge Flag     */
+
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define  USART_ICR_PECF                      0x00000001U            /*!< Parity Error Clear Flag             */
+#define  USART_ICR_FECF                      0x00000002U            /*!< Framing Error Clear Flag            */
+#define  USART_ICR_NCF                       0x00000004U            /*!< Noise detected Clear Flag           */
+#define  USART_ICR_ORECF                     0x00000008U            /*!< OverRun Error Clear Flag            */
+#define  USART_ICR_IDLECF                    0x00000010U            /*!< IDLE line detected Clear Flag       */
+#define  USART_ICR_TCCF                      0x00000040U            /*!< Transmission Complete Clear Flag    */
+#define  USART_ICR_LBDCF                     0x00000100U            /*!< LIN Break Detection Clear Flag      */
+#define  USART_ICR_CTSCF                     0x00000200U            /*!< CTS Interrupt Clear Flag            */
+#define  USART_ICR_RTOCF                     0x00000800U            /*!< Receiver Time Out Clear Flag        */
+#define  USART_ICR_EOBCF                     0x00001000U            /*!< End Of Block Clear Flag             */
+#define  USART_ICR_CMCF                      0x00020000U            /*!< Character Match Clear Flag          */
+#define  USART_ICR_WUCF                      0x00100000U            /*!< Wake Up from stop mode Clear Flag   */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define  USART_RDR_RDR                       0x01FFU                /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define  USART_TDR_TDR                       0x01FFU                /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                            0x7FU                 /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T_0                          0x01U                 /*!<Bit 0 */
+#define  WWDG_CR_T_1                          0x02U                 /*!<Bit 1 */
+#define  WWDG_CR_T_2                          0x04U                 /*!<Bit 2 */
+#define  WWDG_CR_T_3                          0x08U                 /*!<Bit 3 */
+#define  WWDG_CR_T_4                          0x10U                 /*!<Bit 4 */
+#define  WWDG_CR_T_5                          0x20U                 /*!<Bit 5 */
+#define  WWDG_CR_T_6                          0x40U                 /*!<Bit 6 */
+
+
+#define  WWDG_CR_WDGA                        0x80U                  /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          0x007FU                /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W_0                        0x0001U                /*!<Bit 0 */
+#define  WWDG_CFR_W_1                        0x0002U                /*!<Bit 1 */
+#define  WWDG_CFR_W_2                        0x0004U                /*!<Bit 2 */
+#define  WWDG_CFR_W_3                        0x0008U                /*!<Bit 3 */
+#define  WWDG_CFR_W_4                        0x0010U                /*!<Bit 4 */
+#define  WWDG_CFR_W_5                        0x0020U                /*!<Bit 5 */
+#define  WWDG_CFR_W_6                        0x0040U                /*!<Bit 6 */
+
+
+#define  WWDG_CFR_WDGTB                      0x0180U                /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB_0                    0x0080U                /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB_1                    0x0100U                /*!<Bit 1 */
+
+
+#define  WWDG_CFR_EWI                        0x0200U               /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        0x01U                  /*!<Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                DBG                                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
+#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
+#define  DBGMCU_CR_DBG_STOP                  0x00000002U
+#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
+#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
+
+#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
+#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U /*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U /*!<Bit 1 */
+
+/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
+#define  DBGMCU_APB1_FZ_DBG_CAN3_STOP            0x00002000U
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
+
+/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP            0x00000001U
+#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP            0x00000002U
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP            0x00010000U
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP           0x00020000U
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP           0x00040000U
+
+/******************************************************************************/
+/*                                                                            */
+/*                Ethernet MAC Registers bits definitions                     */
+/*                                                                            */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD              0x00800000U  /* Watchdog disable */
+#define ETH_MACCR_JD              0x00400000U  /* Jabber disable */
+#define ETH_MACCR_IFG             0x000E0000U  /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit       0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
+#define ETH_MACCR_IFG_88Bit       0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
+#define ETH_MACCR_IFG_80Bit       0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
+#define ETH_MACCR_IFG_72Bit       0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
+#define ETH_MACCR_IFG_64Bit       0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */        
+#define ETH_MACCR_IFG_56Bit       0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
+#define ETH_MACCR_IFG_48Bit       0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
+#define ETH_MACCR_IFG_40Bit       0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */              
+#define ETH_MACCR_CSD             0x00010000U  /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES             0x00004000U  /* Fast ethernet speed */
+#define ETH_MACCR_ROD             0x00002000U  /* Receive own disable */
+#define ETH_MACCR_LM              0x00001000U  /* loopback mode */
+#define ETH_MACCR_DM              0x00000800U  /* Duplex mode */
+#define ETH_MACCR_IPCO            0x00000400U  /* IP Checksum offload */
+#define ETH_MACCR_RD              0x00000200U  /* Retry disable */
+#define ETH_MACCR_APCS            0x00000080U  /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL              0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
+#define ETH_MACCR_BL_10           0x00000000U  /* k = min (n, 10) */
+#define ETH_MACCR_BL_8            0x00000020U  /* k = min (n, 8) */
+#define ETH_MACCR_BL_4            0x00000040U  /* k = min (n, 4) */
+#define ETH_MACCR_BL_1            0x00000060U  /* k = min (n, 1) */ 
+#define ETH_MACCR_DC              0x00000010U  /* Defferal check */
+#define ETH_MACCR_TE              0x00000008U  /* Transmitter enable */
+#define ETH_MACCR_RE              0x00000004U  /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA             0x80000000U  /* Receive all */ 
+#define ETH_MACFFR_HPF            0x00000400U  /* Hash or perfect filter */ 
+#define ETH_MACFFR_SAF            0x00000200U  /* Source address filter enable */ 
+#define ETH_MACFFR_SAIF           0x00000100U  /* SA inverse filtering */ 
+#define ETH_MACFFR_PCF            0x000000C0U  /* Pass control frames: 3 cases */
+#define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
+#define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */ 
+#define ETH_MACFFR_BFD             0x00000020U  /* Broadcast frame disable */ 
+#define ETH_MACFFR_PAM             0x00000010U  /* Pass all mutlicast */ 
+#define ETH_MACFFR_DAIF            0x00000008U  /* DA Inverse filtering */ 
+#define ETH_MACFFR_HM              0x00000004U  /* Hash multicast */ 
+#define ETH_MACFFR_HU              0x00000002U  /* Hash unicast */
+#define ETH_MACFFR_PM              0x00000001U  /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH            0xFFFFFFFFU  /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL            0xFFFFFFFFU  /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA            0x0000F800U  /* Physical layer address */ 
+#define ETH_MACMIIAR_MR            0x000007C0U  /* MII register in the selected PHY */ 
+#define ETH_MACMIIAR_CR            0x0000001CU  /* CR clock range: 6 cases */ 
+#define ETH_MACMIIAR_CR_Div42      0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+#define ETH_MACMIIAR_CR_Div62      0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+#define ETH_MACMIIAR_CR_Div16      0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+#define ETH_MACMIIAR_CR_Div26      0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+#define ETH_MACMIIAR_CR_Div102     0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
+#define ETH_MACMIIAR_MW            0x00000002U  /* MII write */ 
+#define ETH_MACMIIAR_MB            0x00000001U  /* MII busy */ 
+  
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD            0x0000FFFFU  /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT              0xFFFF0000U  /* Pause time */
+#define ETH_MACFCR_ZQPD            0x00000080U  /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT             0x00000030U  /* Pause low threshold: 4 cases */
+#define ETH_MACFCR_PLT_Minus4      0x00000000U  /* Pause time minus 4 slot times */
+#define ETH_MACFCR_PLT_Minus28     0x00000010U  /* Pause time minus 28 slot times */
+#define ETH_MACFCR_PLT_Minus144    0x00000020U  /* Pause time minus 144 slot times */
+#define ETH_MACFCR_PLT_Minus256    0x00000030U  /* Pause time minus 256 slot times */      
+#define ETH_MACFCR_UPFD            0x00000008U  /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE            0x00000004U  /* Receive flow control enable */
+#define ETH_MACFCR_TFCE            0x00000002U  /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA          0x00000001U  /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC       0x00010000U  /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI       0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
+#define ETH_MACRWUFFR_D            0xFFFFFFFFU  /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
+                              RSVD - Filter1 Command - RSVD - Filter0 Command
+   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
+#define ETH_MACPMTCSR_WFFRPR       0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU           0x00000200U  /* Global Unicast */
+#define ETH_MACPMTCSR_WFR          0x00000040U  /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR          0x00000020U  /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE          0x00000004U  /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE          0x00000002U  /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD           0x00000001U  /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
+#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
+#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
+#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */ 
+#define ETH_MACA1HR_MACA1H            0x0000FFFFU  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
+  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
+  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
+
+/******************************************************************************/
+/*                Ethernet MMC Registers bits definition                      */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
+#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
+#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
+#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/*               Ethernet PTP Registers bits definition                       */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU       0x00000020U  /* Addend register update */
+#define ETH_PTPTSCR_TSITE       0x00000010U  /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU       0x00000008U  /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI       0x00000004U  /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU       0x00000002U  /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE         0x00000001U  /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI      0x000000FFU   /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS        0xFFFFFFFFU   /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS      0x80000000U  /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS       0x7FFFFFFFU  /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS      0xFFFFFFFFU  /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS    0x80000000U  /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS     0x7FFFFFFFU  /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA        0xFFFFFFFFU  /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH       0xFFFFFFFFU  /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL       0xFFFFFFFFU  /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR      0x00000020U  /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO       0x00000010U  /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/*                 Ethernet DMA Registers bits definition                     */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB        0x02000000U  /* Address-Aligned beats */
+#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
+#define ETH_DMABMR_USP        0x00800000U  /* Use separate PBL */
+#define ETH_DMABMR_RDP        0x007E0000U  /* RxDMA PBL */
+  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
+#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
+#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */  
+#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
+  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
+#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
+#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
+#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
+#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
+  /* combination with EBS[2:0] for GetFlagStatus function */
+  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
+  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
+  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
+  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
+  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
+  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
+  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
+  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
+  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
+  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
+  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
+  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
+  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
+  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
+  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
+#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
+#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
+#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
+#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
+#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
+#define ETH_DMASR_RS         0x00000040U  /* Receive status */
+#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
+#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
+#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
+#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
+#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
+#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
+  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
+#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
+  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
+#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U         /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ                     0x00000002U         /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN                0x00000004U         /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL               0x00000008U         /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN                 0x00000010U         /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL                0x00000020U         /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN                 0x00000040U         /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL                0x00000080U         /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U         /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U         /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U         /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U         /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN                    0x00001000U         /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U         /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT                    0x00020000U         /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U         /*!< A-session valid  */
+#define USB_OTG_GOTGCTL_BSESVLD                 0x00080000U         /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER                  0x00100000U         /*!< OTG version  */
+
+/********************  Bit definition for USB_OTG_HCFG register  ********************/
+#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
+
+/********************  Bit definition for USB_OTG_DCFG register  ********************/
+#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
+
+/********************  Bit definition for USB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
+
+/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
+#define USB_OTG_GOTGINT_IDCHNG                  0x00100000U            /*!< Change in ID pin input value           */
+
+/********************  Bit definition for USB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
+
+#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
+
+/********************  Bit definition for USB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
+
+/********************  Bit definition for USB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
+
+/********************  Bit definition for USB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
+
+#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
+
+/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
+#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
+
+/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
+
+/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
+
+/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
+#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
+
+/********************  Bit definition for USB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT                     0x0000FFFFU            /*!< Channel interrupts */
+
+/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM                0x00000020U            /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask       */
+#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
+
+/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation                      */
+#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt                        */
+#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                                  */
+#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                                 */
+#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                                */
+#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty                       */
+#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective            */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective                       */
+#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                                  */
+#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                                    */
+#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                      */
+#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                               */
+#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt       */
+#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt                */
+#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_RSTDET                  0x00800000U            /*!< Reset detected interrupt                       */
+#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_LPMINT                  0x08000000U            /*!< LPM interrupt                                  */
+#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
+
+/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_RSTDEM                  0x00800000U            /*!< Reset detected interrupt mask                       */
+#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_LPMINTM                 0x08000000U            /*!< LPM interrupt Mask                                  */
+#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
+
+/********************  Bit definition for USB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
+
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
+
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
+
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
+
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
+
+/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
+
+/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP                0x00000FFFU            /*!< Device VBUS pulsing time */
+
+/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
+
+/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
+
+/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM            0x0000FFFFU         /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT                0x00000002U           /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT                0x00020000U           /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition for USB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_PWRDWN                 0x00010000U              /*!< Power down */
+#define USB_OTG_GCCFG_VBDEN                  0x00200000U              /*!< USB VBUS Detection Enable */
+
+/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
+#define USB_OTG_GPWRDN_ADPMEN                 0x00000001U             /*!< ADP module enable */
+#define USB_OTG_GPWRDN_ADPIF                  0x00800000U             /*!< ADP Interrupt flag */
+
+/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM          0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM          0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
+ 
+/********************  Bit definition for USB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID               0xFFFFFFFFU            /*!< Product ID field */
+
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
+#define  USB_OTG_GLPMCFG_LPMEN               0x00000001U            /*!< LPM support enable                                     */
+#define  USB_OTG_GLPMCFG_LPMACK              0x00000002U            /*!< LPM Token acknowledge enable                           */
+#define  USB_OTG_GLPMCFG_BESL                0x0000003CU            /*!< BESL value received with last ACKed LPM Token          */
+#define  USB_OTG_GLPMCFG_REMWAKE             0x00000040U            /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define  USB_OTG_GLPMCFG_L1SSEN              0x00000080U            /*!< L1 shallow sleep enable                                */
+#define  USB_OTG_GLPMCFG_BESLTHRS            0x00000F00U            /*!< BESL threshold                                         */
+#define  USB_OTG_GLPMCFG_L1DSEN              0x00001000U            /*!< L1 deep sleep enable                                   */
+#define  USB_OTG_GLPMCFG_LPMRSP              0x00006000U            /*!< LPM response                                           */
+#define  USB_OTG_GLPMCFG_SLPSTS              0x00008000U            /*!< Port sleep status                                      */
+#define  USB_OTG_GLPMCFG_L1RSMOK             0x00010000U            /*!< Sleep State Resume OK                                  */
+#define  USB_OTG_GLPMCFG_LPMCHIDX            0x001E0000U            /*!< LPM Channel Index                                      */
+#define  USB_OTG_GLPMCFG_LPMRCNT             0x00E00000U            /*!< LPM retry count                                        */
+#define  USB_OTG_GLPMCFG_SNDLPM              0x01000000U            /*!< Send LPM transaction                                   */
+#define  USB_OTG_GLPMCFG_LPMRCNTSTS          0x0E000000U            /*!< LPM retry count status                                 */
+#define  USB_OTG_GLPMCFG_ENBESL              0x10000000U            /*!< Enable best effort service latency                     */
+
+/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM           0x00000001U            /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM            0x00000002U            /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM             0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK       0x00000010U            /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM         0x00000020U            /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM         0x00000040U            /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM          0x00000100U            /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPEACHMSK1_BIM             0x00000200U            /*!< BNA interrupt mask                                */
+#define USB_OTG_DIEPEACHMSK1_NAKM            0x00002000U            /*!< NAK interrupt mask                                */
+
+/********************  Bit definition for USB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume                */
+#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend               */
+#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset                 */
+
+#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status           */
+#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power                 */
+
+#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control          */
+#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed                 */
+#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
+
+/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM               0x00000001U            /*!< Transfer completed interrupt mask         */
+#define USB_OTG_DOEPEACHMSK1_EPDM                0x00000002U            /*!< Endpoint disabled interrupt mask          */
+#define USB_OTG_DOEPEACHMSK1_TOM                 0x00000008U            /*!< Timeout condition mask                    */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           0x00000010U            /*!< IN token received when TxFIFO empty mask  */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             0x00000020U            /*!< IN token received with EP mismatch mask   */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             0x00000040U            /*!< IN endpoint NAK effective mask            */
+#define USB_OTG_DOEPEACHMSK1_TXFURM              0x00000100U            /*!< OUT packet error mask                     */
+#define USB_OTG_DOEPEACHMSK1_BIM                 0x00000200U            /*!< BNA interrupt mask                        */
+#define USB_OTG_DOEPEACHMSK1_BERRM               0x00001000U            /*!< Bubble error interrupt mask               */
+#define USB_OTG_DOEPEACHMSK1_NAKM                0x00002000U            /*!< NAK interrupt mask                        */
+#define USB_OTG_DOEPEACHMSK1_NYETM               0x00004000U            /*!< NYET interrupt mask                       */
+
+/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address            */
+#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth                    */
+
+/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size              */
+#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint              */
+#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame                   */
+#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status                       */
+
+#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type                    */
+#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake                  */
+
+#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number                    */
+#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK                        */
+#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID                    */
+#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame                    */
+#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable                 */
+#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable                  */
+
+/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
+
+/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
+
+/********************  Bit definition for USB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
+
+/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
+
+/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
+/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
+
+/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
+#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR                 0x00000020U            /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
+
+/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        JPEG Encoder/Decoder                                */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for CONFR0 register  ********************/
+#define  JPEG_CONFR0_START                       0x00000001U        /*!<Start/Stop bit */  
+
+/********************  Bit definition for CONFR1 register  *******************/
+#define  JPEG_CONFR1_NF                          0x00000003U        /*!<Number of color components */  
+#define  JPEG_CONFR1_NF_0                        0x00000001U        /*!<Bit 0 */   
+#define  JPEG_CONFR1_NF_1                        0x00000002U        /*!<Bit 1 */
+#define  JPEG_CONFR1_RE                          0x00000004U        /*!<Restart maker Enable */  
+#define  JPEG_CONFR1_DE                          0x00000008U        /*!<Decoding Enable */  
+#define  JPEG_CONFR1_COLORSPACE                  0x00000030U        /*!<Color Space */  
+#define  JPEG_CONFR1_COLORSPACE_0                0x00000010U        /*!<Bit 0 */  
+#define  JPEG_CONFR1_COLORSPACE_1                0x00000020U        /*!<Bit 1 */  
+#define  JPEG_CONFR1_NS                          0x000000C0U        /*!<Number of components for Scan */  
+#define  JPEG_CONFR1_NS_0                        0x00000040U        /*!<Bit 0 */  
+#define  JPEG_CONFR1_NS_1                        0x00000080U        /*!<Bit 1 */
+#define  JPEG_CONFR1_HDR                         0x00000100U        /*!<Header Processing On/Off */
+#define  JPEG_CONFR1_YSIZE                       0xFFFF0000U        /*!<Number of lines in source image */
+
+/********************  Bit definition for CONFR2 register  *******************/
+#define  JPEG_CONFR2_NMCU                        0x03FFFFFFU        /*!<Number of MCU units minus 1 to encode */
+
+/********************  Bit definition for CONFR3 register  *******************/
+#define  JPEG_CONFR3_NRST                        0x0000FFFFU        /*!<Number of MCU between two restart makers minus 1 */
+#define  JPEG_CONFR3_XSIZE                       0xFFFF0000U        /*!<Number of pixels per line */
+
+/********************  Bit definition for CONFR4 register  *******************/
+#define  JPEG_CONFR4_HD                          0x00000001U        /*!<Selects the Huffman table for encoding the DC coefficients */  
+#define  JPEG_CONFR4_HA                          0x00000002U        /*!<Selects the Huffman table for encoding the AC coefficients */ 
+#define  JPEG_CONFR4_QT                          0x0000000CU        /*!<Selects quantization table associated with a color component */
+#define  JPEG_CONFR4_QT_0                        0x00000004U        /*!<Bit 0 */
+#define  JPEG_CONFR4_QT_1                        0x00000008U        /*!<Bit 1 */
+#define  JPEG_CONFR4_NB                          0x000000F0U        /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define  JPEG_CONFR4_NB_0                        0x00000010U        /*!<Bit 0 */
+#define  JPEG_CONFR4_NB_1                        0x00000020U        /*!<Bit 1 */
+#define  JPEG_CONFR4_NB_2                        0x00000040U        /*!<Bit 2 */
+#define  JPEG_CONFR4_NB_3                        0x00000080U        /*!<Bit 3 */
+#define  JPEG_CONFR4_VSF                         0x00000F00U        /*!<Vertical sampling factor for component 1 */
+#define  JPEG_CONFR4_VSF_0                       0x00000100U        /*!<Bit 0 */
+#define  JPEG_CONFR4_VSF_1                       0x00000200U        /*!<Bit 1 */
+#define  JPEG_CONFR4_VSF_2                       0x00000400U        /*!<Bit 2 */
+#define  JPEG_CONFR4_VSF_3                       0x00000800U        /*!<Bit 3 */
+#define  JPEG_CONFR4_HSF                         0x0000F000U        /*!<Horizontal sampling factor for component 1 */
+#define  JPEG_CONFR4_HSF_0                       0x00001000U        /*!<Bit 0 */
+#define  JPEG_CONFR4_HSF_1                       0x00002000U        /*!<Bit 1 */
+#define  JPEG_CONFR4_HSF_2                       0x00004000U        /*!<Bit 2 */
+#define  JPEG_CONFR4_HSF_3                       0x00008000U        /*!<Bit 3 */
+
+/********************  Bit definition for CONFR5 register  *******************/
+#define  JPEG_CONFR5_HD                          0x00000001U        /*!<Selects the Huffman table for encoding the DC coefficients */  
+#define  JPEG_CONFR5_HA                          0x00000002U        /*!<Selects the Huffman table for encoding the AC coefficients */ 
+#define  JPEG_CONFR5_QT                          0x0000000CU        /*!<Selects quantization table associated with a color component */
+#define  JPEG_CONFR5_QT_0                        0x00000004U        /*!<Bit 0 */
+#define  JPEG_CONFR5_QT_1                        0x00000008U        /*!<Bit 1 */
+#define  JPEG_CONFR5_NB                          0x000000F0U        /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define  JPEG_CONFR5_NB_0                        0x00000010U        /*!<Bit 0 */
+#define  JPEG_CONFR5_NB_1                        0x00000020U        /*!<Bit 1 */
+#define  JPEG_CONFR5_NB_2                        0x00000040U        /*!<Bit 2 */
+#define  JPEG_CONFR5_NB_3                        0x00000080U        /*!<Bit 3 */
+#define  JPEG_CONFR5_VSF                         0x00000F00U        /*!<Vertical sampling factor for component 2 */
+#define  JPEG_CONFR5_VSF_0                       0x00000100U        /*!<Bit 0 */
+#define  JPEG_CONFR5_VSF_1                       0x00000200U        /*!<Bit 1 */
+#define  JPEG_CONFR5_VSF_2                       0x00000400U        /*!<Bit 2 */
+#define  JPEG_CONFR5_VSF_3                       0x00000800U        /*!<Bit 3 */
+#define  JPEG_CONFR5_HSF                         0x0000F000U        /*!<Horizontal sampling factor for component 2 */
+#define  JPEG_CONFR5_HSF_0                       0x00001000U        /*!<Bit 0 */
+#define  JPEG_CONFR5_HSF_1                       0x00002000U        /*!<Bit 1 */
+#define  JPEG_CONFR5_HSF_2                       0x00004000U        /*!<Bit 2 */
+#define  JPEG_CONFR5_HSF_3                       0x00008000U        /*!<Bit 3 */
+
+/********************  Bit definition for CONFR6 register  *******************/
+#define  JPEG_CONFR6_HD                          0x00000001U        /*!<Selects the Huffman table for encoding the DC coefficients */  
+#define  JPEG_CONFR6_HA                          0x00000002U        /*!<Selects the Huffman table for encoding the AC coefficients */ 
+#define  JPEG_CONFR6_QT                          0x0000000CU        /*!<Selects quantization table associated with a color component */
+#define  JPEG_CONFR6_QT_0                        0x00000004U        /*!<Bit 0 */
+#define  JPEG_CONFR6_QT_1                        0x00000008U        /*!<Bit 1 */
+#define  JPEG_CONFR6_NB                          0x000000F0U        /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define  JPEG_CONFR6_NB_0                        0x00000010U        /*!<Bit 0 */
+#define  JPEG_CONFR6_NB_1                        0x00000020U        /*!<Bit 1 */
+#define  JPEG_CONFR6_NB_2                        0x00000040U        /*!<Bit 2 */
+#define  JPEG_CONFR6_NB_3                        0x00000080U        /*!<Bit 3 */
+#define  JPEG_CONFR6_VSF                         0x00000F00U        /*!<Vertical sampling factor for component 2 */
+#define  JPEG_CONFR6_VSF_0                       0x00000100U        /*!<Bit 0 */
+#define  JPEG_CONFR6_VSF_1                       0x00000200U        /*!<Bit 1 */
+#define  JPEG_CONFR6_VSF_2                       0x00000400U        /*!<Bit 2 */
+#define  JPEG_CONFR6_VSF_3                       0x00000800U        /*!<Bit 3 */
+#define  JPEG_CONFR6_HSF                         0x0000F000U        /*!<Horizontal sampling factor for component 2 */
+#define  JPEG_CONFR6_HSF_0                       0x00001000U        /*!<Bit 0 */
+#define  JPEG_CONFR6_HSF_1                       0x00002000U        /*!<Bit 1 */
+#define  JPEG_CONFR6_HSF_2                       0x00004000U        /*!<Bit 2 */
+#define  JPEG_CONFR6_HSF_3                       0x00008000U        /*!<Bit 3 */
+
+/********************  Bit definition for CONFR7 register  *******************/
+#define  JPEG_CONFR7_HD                          0x00000001U        /*!<Selects the Huffman table for encoding the DC coefficients */  
+#define  JPEG_CONFR7_HA                          0x00000002U        /*!<Selects the Huffman table for encoding the AC coefficients */ 
+#define  JPEG_CONFR7_QT                          0x0000000CU        /*!<Selects quantization table associated with a color component */
+#define  JPEG_CONFR7_QT_0                        0x00000004U        /*!<Bit 0 */
+#define  JPEG_CONFR7_QT_1                        0x00000008U        /*!<Bit 1 */
+#define  JPEG_CONFR7_NB                          0x000000F0U        /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define  JPEG_CONFR7_NB_0                        0x00000010U        /*!<Bit 0 */
+#define  JPEG_CONFR7_NB_1                        0x00000020U        /*!<Bit 1 */
+#define  JPEG_CONFR7_NB_2                        0x00000040U        /*!<Bit 2 */
+#define  JPEG_CONFR7_NB_3                        0x00000080U        /*!<Bit 3 */
+#define  JPEG_CONFR7_VSF                         0x00000F00U        /*!<Vertical sampling factor for component 2 */
+#define  JPEG_CONFR7_VSF_0                       0x00000100U        /*!<Bit 0 */
+#define  JPEG_CONFR7_VSF_1                       0x00000200U        /*!<Bit 1 */
+#define  JPEG_CONFR7_VSF_2                       0x00000400U        /*!<Bit 2 */
+#define  JPEG_CONFR7_VSF_3                       0x00000800U        /*!<Bit 3 */
+#define  JPEG_CONFR7_HSF                         0x0000F000U        /*!<Horizontal sampling factor for component 2 */
+#define  JPEG_CONFR7_HSF_0                       0x00001000U        /*!<Bit 0 */
+#define  JPEG_CONFR7_HSF_1                       0x00002000U        /*!<Bit 1 */
+#define  JPEG_CONFR7_HSF_2                       0x00004000U        /*!<Bit 2 */
+#define  JPEG_CONFR7_HSF_3                       0x00008000U        /*!<Bit 3 */
+
+/********************  Bit definition for CR register  *******************/
+#define  JPEG_CR_JCEN                            0x00000001U        /*!<Enable the JPEG Codec Core */
+#define  JPEG_CR_IFTIE                           0x00000002U        /*!<Input FIFO Threshold Interrupt Enable */
+#define  JPEG_CR_IFNFIE                          0x00000004U        /*!<Input FIFO Not Full Interrupt Enable */
+#define  JPEG_CR_OFTIE                           0x00000008U        /*!<Output FIFO Threshold Interrupt Enable */
+#define  JPEG_CR_OFNEIE                          0x00000010U        /*!<Output FIFO Not Empty Interrupt Enable */
+#define  JPEG_CR_EOCIE                           0x00000020U        /*!<End of Conversion Interrupt Enable */
+#define  JPEG_CR_HPDIE                           0x00000040U        /*!<Header Parsing Done Interrupt Enable */
+#define  JPEG_CR_IDMAEN                          0x00000800U        /*!<Enable the DMA request generation for the input FIFO */
+#define  JPEG_CR_ODMAEN                          0x00001000U        /*!<Enable the DMA request generation for the output FIFO */
+#define  JPEG_CR_IFF                             0x00002000U        /*!<Flush the input FIFO */
+#define  JPEG_CR_OFF                             0x00004000U        /*!<Flush the output FIFO */
+
+/********************  Bit definition for SR register  *******************/
+#define  JPEG_SR_IFTF                            0x00000002U        /*!<Input FIFO is not full and is bellow its threshold flag */
+#define  JPEG_SR_IFNFF                           0x00000004U        /*!<Input FIFO Not Full Flag, a data can be written */
+#define  JPEG_SR_OFTF                            0x00000008U        /*!<Output FIFO is not empty and has reach its threshold */
+#define  JPEG_SR_OFNEF                           0x000000010U       /*!<Output FIFO is not empty, a data is available */
+#define  JPEG_SR_EOCF                            0x000000020U       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
+#define  JPEG_SR_HPDF                            0x000000040U       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
+#define  JPEG_SR_COF                             0x000000080U       /*!<JPEG Codec operation on going  flag */
+
+/********************  Bit definition for CFR register  *******************/
+#define  JPEG_CFR_CEOCF                          0x00000020U       /*!<Clear End of Conversion Flag */
+#define  JPEG_CFR_CHPDF                          0x00000040U       /*!<Clear Header Parsing Done Flag */
+
+/********************  Bit definition for DIR register  ********************/
+#define  JPEG_DIR_DATAIN                         0xFFFFFFFFU        /*!<Data Input FIFO */
+
+/********************  Bit definition for DOR register  ********************/
+#define  JPEG_DOR_DATAOUT                        0xFFFFFFFFU        /*!<Data Output FIFO */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                MDIOS                                        */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for MDIOS_CR register  *******************/
+#define MDIOS_CR_EN               0x00000001U    /*!<Peripheral enable */
+#define MDIOS_CR_WRIE             0x00000002U    /*!<Register write interrupt enable */ 
+#define MDIOS_CR_RDIE             0x00000004U    /*!<Register Read Interrupt Enable */
+#define MDIOS_CR_EIE              0x00000008U    /*!<Error interrupt enable */
+#define MDIOS_CR_DPC              0x00000080U    /*!<Disable Preamble Check */
+#define MDIOS_CR_PORT_ADDRESS     0x00001F00U    /*!<PORT_ADDRESS[4:0] bits */
+#define MDIOS_CR_PORT_ADDRESS_0   0x00000100U    /*!<Bit 0 */
+#define MDIOS_CR_PORT_ADDRESS_1   0x00000200U    /*!<Bit 1 */
+#define MDIOS_CR_PORT_ADDRESS_2   0x00000400U    /*!<Bit 2 */
+#define MDIOS_CR_PORT_ADDRESS_3   0x00000800U    /*!<Bit 3 */
+#define MDIOS_CR_PORT_ADDRESS_4   0x00001000U    /*!<Bit 4 */
+
+/********************  Bit definition for MDIOS_WRFR register  *******************/
+#define MDIOS_WRFR_WRF            0xFFFFFFFFU    /*!<WRF[31:0] bits (Write flags for MDIO register 0 to 31) */
+
+/********************  Bit definition for MDIOS_CWRFR register  *******************/
+#define MDIOS_CWRFR_CWRF           0xFFFFFFFFU    /*!<CWRF[31:0] bits (Clear the write flag for MDIO register 0 to 31) */
+
+/********************  Bit definition for MDIOS_RDFR register  *******************/
+#define MDIOS_RDFR_RDF           0xFFFFFFFFU      /*!<RDF[31:0] bits (Read flags for MDIO registers 0 to 31) */
+
+/********************  Bit definition for MDIOS_CRDFR register  *******************/
+#define MDIOS_CRDFR_CRDF          0xFFFFFFFFU      /*!<CRDF[31:0] bits (Clear the read flag for MDIO registers 0 to 31) */
+
+/********************  Bit definition for MDIOS_SR register  *******************/
+#define MDIOS_SR_PERF             0x00000001U    /*!< Preamble error flag */
+#define MDIOS_SR_SERF             0x00000002U    /*!< Start error flag */
+#define MDIOS_SR_TERF             0x00000004U    /*!< Turnaround error flag */
+
+/********************  Bit definition for MDIOS_CLRFR register  *******************/
+#define MDIOS_CLRFR_CPERF             0x00000001U    /*!< Clear the preamble error flag */
+#define MDIOS_CLRFR_CSERF             0x00000002U    /*!< Clear the start error flag */
+#define MDIOS_CLRFR_CTERF             0x00000004U    /*!< Clear the turnaround error flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                     Display Serial Interface (DSI)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DSI_VR register  *****************/
+#define DSI_VR                         0x3133302AU               /*!< DSI Host Version */
+
+/*******************  Bit definition for DSI_CR register  *****************/
+#define DSI_CR_EN                      0x00000001U               /*!< DSI Host power up and reset */
+
+/*******************  Bit definition for DSI_CCR register  ****************/
+#define DSI_CCR_TXECKDIV               0x000000FFU               /*!< TX Escape Clock Division */
+#define DSI_CCR_TXECKDIV0              0x00000001U
+#define DSI_CCR_TXECKDIV1              0x00000002U
+#define DSI_CCR_TXECKDIV2              0x00000004U
+#define DSI_CCR_TXECKDIV3              0x00000008U
+#define DSI_CCR_TXECKDIV4              0x00000010U
+#define DSI_CCR_TXECKDIV5              0x00000020U
+#define DSI_CCR_TXECKDIV6              0x00000040U
+#define DSI_CCR_TXECKDIV7              0x00000080U
+
+#define DSI_CCR_TOCKDIV                0x0000FF00U               /*!< Timeout Clock Division */
+#define DSI_CCR_TOCKDIV0               0x00000100U
+#define DSI_CCR_TOCKDIV1               0x00000200U
+#define DSI_CCR_TOCKDIV2               0x00000400U
+#define DSI_CCR_TOCKDIV3               0x00000800U
+#define DSI_CCR_TOCKDIV4               0x00001000U
+#define DSI_CCR_TOCKDIV5               0x00002000U
+#define DSI_CCR_TOCKDIV6               0x00004000U
+#define DSI_CCR_TOCKDIV7               0x00008000U
+
+/*******************  Bit definition for DSI_LVCIDR register  *************/
+#define DSI_LVCIDR_VCID                0x00000003U               /*!< Virtual Channel ID */
+#define DSI_LVCIDR_VCID0               0x00000001U
+#define DSI_LVCIDR_VCID1               0x00000002U
+
+/*******************  Bit definition for DSI_LCOLCR register  *************/
+#define DSI_LCOLCR_COLC                0x0000000FU               /*!< Color Coding */
+#define DSI_LCOLCR_COLC0               0x00000001U
+#define DSI_LCOLCR_COLC1               0x00000020U
+#define DSI_LCOLCR_COLC2               0x00000040U
+#define DSI_LCOLCR_COLC3               0x00000080U
+
+#define DSI_LCOLCR_LPE                 0x00000100U               /*!< Loosly Packet Enable */
+
+/*******************  Bit definition for DSI_LPCR register  ***************/
+#define DSI_LPCR_DEP                   0x00000001U               /*!< Data Enable Polarity */
+#define DSI_LPCR_VSP                   0x00000002U               /*!< VSYNC Polarity */
+#define DSI_LPCR_HSP                   0x00000004U               /*!< HSYNC Polarity */
+
+/*******************  Bit definition for DSI_LPMCR register  **************/
+#define DSI_LPMCR_VLPSIZE              0x000000FFU               /*!< VACT Largest Packet Size */
+#define DSI_LPMCR_VLPSIZE0             0x00000001U
+#define DSI_LPMCR_VLPSIZE1             0x00000002U
+#define DSI_LPMCR_VLPSIZE2             0x00000004U
+#define DSI_LPMCR_VLPSIZE3             0x00000008U
+#define DSI_LPMCR_VLPSIZE4             0x00000010U
+#define DSI_LPMCR_VLPSIZE5             0x00000020U
+#define DSI_LPMCR_VLPSIZE6             0x00000040U
+#define DSI_LPMCR_VLPSIZE7             0x00000080U
+
+#define DSI_LPMCR_LPSIZE               0x00FF0000U               /*!< Largest Packet Size */
+#define DSI_LPMCR_LPSIZE0              0x00010000U
+#define DSI_LPMCR_LPSIZE1              0x00020000U
+#define DSI_LPMCR_LPSIZE2              0x00040000U
+#define DSI_LPMCR_LPSIZE3              0x00080000U
+#define DSI_LPMCR_LPSIZE4              0x00100000U
+#define DSI_LPMCR_LPSIZE5              0x00200000U
+#define DSI_LPMCR_LPSIZE6              0x00400000U
+#define DSI_LPMCR_LPSIZE7              0x00800000U
+
+/*******************  Bit definition for DSI_PCR register  ****************/
+#define DSI_PCR_ETTXE                  0x00000001U               /*!< EoTp Transmission Enable */
+#define DSI_PCR_ETRXE                  0x00000002U               /*!< EoTp Reception Enable */
+#define DSI_PCR_BTAE                   0x00000004U               /*!< Bus Turn Around Enable */
+#define DSI_PCR_ECCRXE                 0x00000008U               /*!< ECC Reception Enable */
+#define DSI_PCR_CRCRXE                 0x00000010U               /*!< CRC Reception Enable */
+
+/*******************  Bit definition for DSI_GVCIDR register  *************/
+#define DSI_GVCIDR_VCID                0x00000003U               /*!< Virtual Channel ID */
+#define DSI_GVCIDR_VCID0               0x00000001U
+#define DSI_GVCIDR_VCID1               0x00000002U
+
+/*******************  Bit definition for DSI_MCR register  ****************/
+#define DSI_MCR_CMDM                   0x00000001U               /*!< Command Mode */
+
+/*******************  Bit definition for DSI_VMCR register  ***************/
+#define DSI_VMCR_VMT                   0x00000003U               /*!< Video Mode Type */
+#define DSI_VMCR_VMT0                  0x00000001U
+#define DSI_VMCR_VMT1                  0x00000002U
+
+#define DSI_VMCR_LPVSAE                0x00000100U               /*!< Low-Power Vertical Sync Active Enable */
+#define DSI_VMCR_LPVBPE                0x00000200U               /*!< Low-power Vertical Back-Porch Enable */
+#define DSI_VMCR_LPVFPE                0x00000400U               /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCR_LPVAE                 0x00000800U               /*!< Low-Power Vertical Active Enable */
+#define DSI_VMCR_LPHBPE                0x00001000U               /*!< Low-Power Horizontal Back-Porch Enable */
+#define DSI_VMCR_LPHFPE                0x00002000U               /*!< Low-Power Horizontal Front-Porch Enable */
+#define DSI_VMCR_FBTAAE                0x00004000U               /*!< Frame Bus-Turn-Around Acknowledge Enable */
+#define DSI_VMCR_LPCE                  0x00008000U               /*!< Low-Power Command Enable */
+#define DSI_VMCR_PGE                   0x00010000U               /*!< Pattern Generator Enable */
+#define DSI_VMCR_PGM                   0x00100000U               /*!< Pattern Generator Mode */
+#define DSI_VMCR_PGO                   0x01000000U               /*!< Pattern Generator Orientation */
+
+/*******************  Bit definition for DSI_VPCR register  ***************/
+#define DSI_VPCR_VPSIZE                0x00003FFFU               /*!< Video Packet Size */
+#define DSI_VPCR_VPSIZE0               0x00000001U
+#define DSI_VPCR_VPSIZE1               0x00000002U
+#define DSI_VPCR_VPSIZE2               0x00000004U
+#define DSI_VPCR_VPSIZE3               0x00000008U
+#define DSI_VPCR_VPSIZE4               0x00000010U
+#define DSI_VPCR_VPSIZE5               0x00000020U
+#define DSI_VPCR_VPSIZE6               0x00000040U
+#define DSI_VPCR_VPSIZE7               0x00000080U
+#define DSI_VPCR_VPSIZE8               0x00000100U
+#define DSI_VPCR_VPSIZE9               0x00000200U
+#define DSI_VPCR_VPSIZE10              0x00000400U
+#define DSI_VPCR_VPSIZE11              0x00000800U
+#define DSI_VPCR_VPSIZE12              0x00001000U
+#define DSI_VPCR_VPSIZE13              0x00002000U
+
+/*******************  Bit definition for DSI_VCCR register  ***************/
+#define DSI_VCCR_NUMC                  0x00001FFFU               /*!< Number of Chunks */
+#define DSI_VCCR_NUMC0                 0x00000001U
+#define DSI_VCCR_NUMC1                 0x00000002U
+#define DSI_VCCR_NUMC2                 0x00000004U
+#define DSI_VCCR_NUMC3                 0x00000008U
+#define DSI_VCCR_NUMC4                 0x00000010U
+#define DSI_VCCR_NUMC5                 0x00000020U
+#define DSI_VCCR_NUMC6                 0x00000040U
+#define DSI_VCCR_NUMC7                 0x00000080U
+#define DSI_VCCR_NUMC8                 0x00000100U
+#define DSI_VCCR_NUMC9                 0x00000200U
+#define DSI_VCCR_NUMC10                0x00000400U
+#define DSI_VCCR_NUMC11                0x00000800U
+#define DSI_VCCR_NUMC12                0x00001000U
+
+/*******************  Bit definition for DSI_VNPCR register  **************/
+#define DSI_VNPCR_NPSIZE               0x00001FFFU               /*!< Null Packet Size */
+#define DSI_VNPCR_NPSIZE0              0x00000001U
+#define DSI_VNPCR_NPSIZE1              0x00000002U
+#define DSI_VNPCR_NPSIZE2              0x00000004U
+#define DSI_VNPCR_NPSIZE3              0x00000008U
+#define DSI_VNPCR_NPSIZE4              0x00000010U
+#define DSI_VNPCR_NPSIZE5              0x00000020U
+#define DSI_VNPCR_NPSIZE6              0x00000040U
+#define DSI_VNPCR_NPSIZE7              0x00000080U
+#define DSI_VNPCR_NPSIZE8              0x00000100U
+#define DSI_VNPCR_NPSIZE9              0x00000200U
+#define DSI_VNPCR_NPSIZE10             0x00000400U
+#define DSI_VNPCR_NPSIZE11             0x00000800U
+#define DSI_VNPCR_NPSIZE12             0x00001000U
+
+/*******************  Bit definition for DSI_VHSACR register  *************/
+#define DSI_VHSACR_HSA                 0x00000FFFU               /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACR_HSA0                0x00000001U
+#define DSI_VHSACR_HSA1                0x00000002U
+#define DSI_VHSACR_HSA2                0x00000004U
+#define DSI_VHSACR_HSA3                0x00000008U
+#define DSI_VHSACR_HSA4                0x00000010U
+#define DSI_VHSACR_HSA5                0x00000020U
+#define DSI_VHSACR_HSA6                0x00000040U
+#define DSI_VHSACR_HSA7                0x00000080U
+#define DSI_VHSACR_HSA8                0x00000100U
+#define DSI_VHSACR_HSA9                0x00000200U
+#define DSI_VHSACR_HSA10               0x00000400U
+#define DSI_VHSACR_HSA11               0x00000800U
+
+/*******************  Bit definition for DSI_VHBPCR register  *************/
+#define DSI_VHBPCR_HBP                 0x00000FFFU               /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCR_HBP0                0x00000001U
+#define DSI_VHBPCR_HBP1                0x00000002U
+#define DSI_VHBPCR_HBP2                0x00000004U
+#define DSI_VHBPCR_HBP3                0x00000008U
+#define DSI_VHBPCR_HBP4                0x00000010U
+#define DSI_VHBPCR_HBP5                0x00000020U
+#define DSI_VHBPCR_HBP6                0x00000040U
+#define DSI_VHBPCR_HBP7                0x00000080U
+#define DSI_VHBPCR_HBP8                0x00000100U
+#define DSI_VHBPCR_HBP9                0x00000200U
+#define DSI_VHBPCR_HBP10               0x00000400U
+#define DSI_VHBPCR_HBP11               0x00000800U
+
+/*******************  Bit definition for DSI_VLCR register  ***************/
+#define DSI_VLCR_HLINE                 0x00007FFFU               /*!< Horizontal Line duration */
+#define DSI_VLCR_HLINE0                0x00000001U
+#define DSI_VLCR_HLINE1                0x00000002U
+#define DSI_VLCR_HLINE2                0x00000004U
+#define DSI_VLCR_HLINE3                0x00000008U
+#define DSI_VLCR_HLINE4                0x00000010U
+#define DSI_VLCR_HLINE5                0x00000020U
+#define DSI_VLCR_HLINE6                0x00000040U
+#define DSI_VLCR_HLINE7                0x00000080U
+#define DSI_VLCR_HLINE8                0x00000100U
+#define DSI_VLCR_HLINE9                0x00000200U
+#define DSI_VLCR_HLINE10               0x00000400U
+#define DSI_VLCR_HLINE11               0x00000800U
+#define DSI_VLCR_HLINE12               0x00001000U
+#define DSI_VLCR_HLINE13               0x00002000U
+#define DSI_VLCR_HLINE14               0x00004000U
+
+/*******************  Bit definition for DSI_VVSACR register  *************/
+#define DSI_VVSACR_VSA                 0x000003FFU               /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACR_VSA0                0x00000001U
+#define DSI_VVSACR_VSA1                0x00000002U
+#define DSI_VVSACR_VSA2                0x00000004U
+#define DSI_VVSACR_VSA3                0x00000008U
+#define DSI_VVSACR_VSA4                0x00000010U
+#define DSI_VVSACR_VSA5                0x00000020U
+#define DSI_VVSACR_VSA6                0x00000040U
+#define DSI_VVSACR_VSA7                0x00000080U
+#define DSI_VVSACR_VSA8                0x00000100U
+#define DSI_VVSACR_VSA9                0x00000200U
+
+/*******************  Bit definition for DSI_VVBPCR register  *************/
+#define DSI_VVBPCR_VBP                 0x000003FFU               /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCR_VBP0                0x00000001U
+#define DSI_VVBPCR_VBP1                0x00000002U
+#define DSI_VVBPCR_VBP2                0x00000004U
+#define DSI_VVBPCR_VBP3                0x00000008U
+#define DSI_VVBPCR_VBP4                0x00000010U
+#define DSI_VVBPCR_VBP5                0x00000020U
+#define DSI_VVBPCR_VBP6                0x00000040U
+#define DSI_VVBPCR_VBP7                0x00000080U
+#define DSI_VVBPCR_VBP8                0x00000100U
+#define DSI_VVBPCR_VBP9                0x00000200U
+
+/*******************  Bit definition for DSI_VVFPCR register  *************/
+#define DSI_VVFPCR_VFP                 0x000003FFU               /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCR_VFP0                0x00000001U
+#define DSI_VVFPCR_VFP1                0x00000002U
+#define DSI_VVFPCR_VFP2                0x00000004U
+#define DSI_VVFPCR_VFP3                0x00000008U
+#define DSI_VVFPCR_VFP4                0x00000010U
+#define DSI_VVFPCR_VFP5                0x00000020U
+#define DSI_VVFPCR_VFP6                0x00000040U
+#define DSI_VVFPCR_VFP7                0x00000080U
+#define DSI_VVFPCR_VFP8                0x00000100U
+#define DSI_VVFPCR_VFP9                0x00000200U
+
+/*******************  Bit definition for DSI_VVACR register  **************/
+#define DSI_VVACR_VA                   0x00003FFFU               /*!< Vertical Active duration */
+#define DSI_VVACR_VA0                  0x00000001U
+#define DSI_VVACR_VA1                  0x00000002U
+#define DSI_VVACR_VA2                  0x00000004U
+#define DSI_VVACR_VA3                  0x00000008U
+#define DSI_VVACR_VA4                  0x00000010U
+#define DSI_VVACR_VA5                  0x00000020U
+#define DSI_VVACR_VA6                  0x00000040U
+#define DSI_VVACR_VA7                  0x00000080U
+#define DSI_VVACR_VA8                  0x00000100U
+#define DSI_VVACR_VA9                  0x00000200U
+#define DSI_VVACR_VA10                 0x00000400U
+#define DSI_VVACR_VA11                 0x00000800U
+#define DSI_VVACR_VA12                 0x00001000U
+#define DSI_VVACR_VA13                 0x00002000U
+
+/*******************  Bit definition for DSI_LCCR register  ***************/
+#define DSI_LCCR_CMDSIZE               0x0000FFFFU               /*!< Command Size */
+#define DSI_LCCR_CMDSIZE0              0x00000001U
+#define DSI_LCCR_CMDSIZE1              0x00000002U
+#define DSI_LCCR_CMDSIZE2              0x00000004U
+#define DSI_LCCR_CMDSIZE3              0x00000008U
+#define DSI_LCCR_CMDSIZE4              0x00000010U
+#define DSI_LCCR_CMDSIZE5              0x00000020U
+#define DSI_LCCR_CMDSIZE6              0x00000040U
+#define DSI_LCCR_CMDSIZE7              0x00000080U
+#define DSI_LCCR_CMDSIZE8              0x00000100U
+#define DSI_LCCR_CMDSIZE9              0x00000200U
+#define DSI_LCCR_CMDSIZE10             0x00000400U
+#define DSI_LCCR_CMDSIZE11             0x00000800U
+#define DSI_LCCR_CMDSIZE12             0x00001000U
+#define DSI_LCCR_CMDSIZE13             0x00002000U
+#define DSI_LCCR_CMDSIZE14             0x00004000U
+#define DSI_LCCR_CMDSIZE15             0x00008000U
+
+/*******************  Bit definition for DSI_CMCR register  ***************/
+#define DSI_CMCR_TEARE                 0x00000001U               /*!< Tearing Effect Acknowledge Request Enable */
+#define DSI_CMCR_ARE                   0x00000002U               /*!< Acknowledge Request Enable */
+#define DSI_CMCR_GSW0TX                0x00000100U               /*!< Generic Short Write Zero parameters Transmission */
+#define DSI_CMCR_GSW1TX                0x00000200U               /*!< Generic Short Write One parameters Transmission */
+#define DSI_CMCR_GSW2TX                0x00000400U               /*!< Generic Short Write Two parameters Transmission */
+#define DSI_CMCR_GSR0TX                0x00000800U               /*!< Generic Short Read Zero parameters Transmission */
+#define DSI_CMCR_GSR1TX                0x00001000U               /*!< Generic Short Read One parameters Transmission */
+#define DSI_CMCR_GSR2TX                0x00002000U               /*!< Generic Short Read Two parameters Transmission */
+#define DSI_CMCR_GLWTX                 0x00004000U               /*!< Generic Long Write Transmission */
+#define DSI_CMCR_DSW0TX                0x00010000U               /*!< DCS Short Write Zero parameter Transmission */
+#define DSI_CMCR_DSW1TX                0x00020000U               /*!< DCS Short Read One parameter Transmission */
+#define DSI_CMCR_DSR0TX                0x00040000U               /*!< DCS Short Read Zero parameter Transmission */
+#define DSI_CMCR_DLWTX                 0x00080000U               /*!< DCS Long Write Transmission */
+#define DSI_CMCR_MRDPS                 0x01000000U               /*!< Maximum Read Packet Size */
+
+/*******************  Bit definition for DSI_GHCR register  ***************/
+#define DSI_GHCR_DT                    0x0000003FU               /*!< Type */
+#define DSI_GHCR_DT0                   0x00000001U
+#define DSI_GHCR_DT1                   0x00000002U
+#define DSI_GHCR_DT2                   0x00000004U
+#define DSI_GHCR_DT3                   0x00000008U
+#define DSI_GHCR_DT4                   0x00000010U
+#define DSI_GHCR_DT5                   0x00000020U
+
+#define DSI_GHCR_VCID                  0x000000C0U               /*!< Channel */
+#define DSI_GHCR_VCID0                 0x00000040U
+#define DSI_GHCR_VCID1                 0x00000080U
+
+#define DSI_GHCR_WCLSB                 0x0000FF00U               /*!< WordCount LSB */
+#define DSI_GHCR_WCLSB0                0x00000100U
+#define DSI_GHCR_WCLSB1                0x00000200U
+#define DSI_GHCR_WCLSB2                0x00000400U
+#define DSI_GHCR_WCLSB3                0x00000800U
+#define DSI_GHCR_WCLSB4                0x00001000U
+#define DSI_GHCR_WCLSB5                0x00002000U
+#define DSI_GHCR_WCLSB6                0x00004000U
+#define DSI_GHCR_WCLSB7                0x00008000U
+
+#define DSI_GHCR_WCMSB                 0x00FF0000U               /*!< WordCount MSB */
+#define DSI_GHCR_WCMSB0                0x00010000U
+#define DSI_GHCR_WCMSB1                0x00020000U
+#define DSI_GHCR_WCMSB2                0x00040000U
+#define DSI_GHCR_WCMSB3                0x00080000U
+#define DSI_GHCR_WCMSB4                0x00100000U
+#define DSI_GHCR_WCMSB5                0x00200000U
+#define DSI_GHCR_WCMSB6                0x00400000U
+#define DSI_GHCR_WCMSB7                0x00800000U
+
+/*******************  Bit definition for DSI_GPDR register  ***************/
+#define DSI_GPDR_DATA1                 0x000000FFU               /*!< Payload Byte 1 */
+#define DSI_GPDR_DATA1_0               0x00000001U
+#define DSI_GPDR_DATA1_1               0x00000002U
+#define DSI_GPDR_DATA1_2               0x00000004U
+#define DSI_GPDR_DATA1_3               0x00000008U
+#define DSI_GPDR_DATA1_4               0x00000010U
+#define DSI_GPDR_DATA1_5               0x00000020U
+#define DSI_GPDR_DATA1_6               0x00000040U
+#define DSI_GPDR_DATA1_7               0x00000080U
+
+#define DSI_GPDR_DATA2                 0x0000FF00U               /*!< Payload Byte 2 */
+#define DSI_GPDR_DATA2_0               0x00000100U
+#define DSI_GPDR_DATA2_1               0x00000200U
+#define DSI_GPDR_DATA2_2               0x00000400U
+#define DSI_GPDR_DATA2_3               0x00000800U
+#define DSI_GPDR_DATA2_4               0x00001000U
+#define DSI_GPDR_DATA2_5               0x00002000U
+#define DSI_GPDR_DATA2_6               0x00004000U
+#define DSI_GPDR_DATA2_7               0x00008000U
+
+#define DSI_GPDR_DATA3                 0x00FF0000U               /*!< Payload Byte 3 */
+#define DSI_GPDR_DATA3_0               0x00010000U
+#define DSI_GPDR_DATA3_1               0x00020000U
+#define DSI_GPDR_DATA3_2               0x00040000U
+#define DSI_GPDR_DATA3_3               0x00080000U
+#define DSI_GPDR_DATA3_4               0x00100000U
+#define DSI_GPDR_DATA3_5               0x00200000U
+#define DSI_GPDR_DATA3_6               0x00400000U
+#define DSI_GPDR_DATA3_7               0x00800000U
+
+#define DSI_GPDR_DATA4                 0xFF000000U               /*!< Payload Byte 4 */
+#define DSI_GPDR_DATA4_0               0x01000000U
+#define DSI_GPDR_DATA4_1               0x02000000U
+#define DSI_GPDR_DATA4_2               0x04000000U
+#define DSI_GPDR_DATA4_3               0x08000000U
+#define DSI_GPDR_DATA4_4               0x10000000U
+#define DSI_GPDR_DATA4_5               0x20000000U
+#define DSI_GPDR_DATA4_6               0x40000000U
+#define DSI_GPDR_DATA4_7               0x80000000U
+
+/*******************  Bit definition for DSI_GPSR register  ***************/
+#define DSI_GPSR_CMDFE                 0x00000001U               /*!< Command FIFO Empty */
+#define DSI_GPSR_CMDFF                 0x00000002U               /*!< Command FIFO Full */
+#define DSI_GPSR_PWRFE                 0x00000004U               /*!< Payload Write FIFO Empty */
+#define DSI_GPSR_PWRFF                 0x00000008U               /*!< Payload Write FIFO Full */
+#define DSI_GPSR_PRDFE                 0x00000010U               /*!< Payload Read FIFO Empty */
+#define DSI_GPSR_PRDFF                 0x00000020U               /*!< Payload Read FIFO Full */
+#define DSI_GPSR_RCB                   0x00000040U               /*!< Read Command Busy */
+
+/*******************  Bit definition for DSI_TCCR0register  **************/
+#define DSI_TCCR0_LPRX_TOCNT           0x0000FFFFU               /*!< Low-power Reception Timeout Counter */
+#define DSI_TCCR0_LPRX_TOCNT0          0x00000001U
+#define DSI_TCCR0_LPRX_TOCNT1          0x00000002U
+#define DSI_TCCR0_LPRX_TOCNT2          0x00000004U
+#define DSI_TCCR0_LPRX_TOCNT3          0x00000008U
+#define DSI_TCCR0_LPRX_TOCNT4          0x00000010U
+#define DSI_TCCR0_LPRX_TOCNT5          0x00000020U
+#define DSI_TCCR0_LPRX_TOCNT6          0x00000040U
+#define DSI_TCCR0_LPRX_TOCNT7          0x00000080U
+#define DSI_TCCR0_LPRX_TOCNT8          0x00000100U
+#define DSI_TCCR0_LPRX_TOCNT9          0x00000200U
+#define DSI_TCCR0_LPRX_TOCNT10         0x00000400U
+#define DSI_TCCR0_LPRX_TOCNT11         0x00000800U
+#define DSI_TCCR0_LPRX_TOCNT12         0x00001000U
+#define DSI_TCCR0_LPRX_TOCNT13         0x00002000U
+#define DSI_TCCR0_LPRX_TOCNT14         0x00004000U
+#define DSI_TCCR0_LPRX_TOCNT15         0x00008000U
+
+#define DSI_TCCR0_HSTX_TOCNT           0xFFFF0000U               /*!< High-Speed Transmission Timeout Counter */
+#define DSI_TCCR0_HSTX_TOCNT0          0x00010000U
+#define DSI_TCCR0_HSTX_TOCNT1          0x00020000U
+#define DSI_TCCR0_HSTX_TOCNT2          0x00040000U
+#define DSI_TCCR0_HSTX_TOCNT3          0x00080000U
+#define DSI_TCCR0_HSTX_TOCNT4          0x00100000U
+#define DSI_TCCR0_HSTX_TOCNT5          0x00200000U
+#define DSI_TCCR0_HSTX_TOCNT6          0x00400000U
+#define DSI_TCCR0_HSTX_TOCNT7          0x00800000U
+#define DSI_TCCR0_HSTX_TOCNT8          0x01000000U
+#define DSI_TCCR0_HSTX_TOCNT9          0x02000000U
+#define DSI_TCCR0_HSTX_TOCNT10         0x04000000U
+#define DSI_TCCR0_HSTX_TOCNT11         0x08000000U
+#define DSI_TCCR0_HSTX_TOCNT12         0x10000000U
+#define DSI_TCCR0_HSTX_TOCNT13         0x20000000U
+#define DSI_TCCR0_HSTX_TOCNT14         0x40000000U
+#define DSI_TCCR0_HSTX_TOCNT15         0x80000000U
+
+/*******************  Bit definition for DSI_TCCR1register  **************/
+#define DSI_TCCR1_HSRD_TOCNT           0x0000FFFFU               /*!< High-Speed Read Timeout Counter */
+#define DSI_TCCR1_HSRD_TOCNT0          0x00000001U
+#define DSI_TCCR1_HSRD_TOCNT1          0x00000002U
+#define DSI_TCCR1_HSRD_TOCNT2          0x00000004U
+#define DSI_TCCR1_HSRD_TOCNT3          0x00000008U
+#define DSI_TCCR1_HSRD_TOCNT4          0x00000010U
+#define DSI_TCCR1_HSRD_TOCNT5          0x00000020U
+#define DSI_TCCR1_HSRD_TOCNT6          0x00000040U
+#define DSI_TCCR1_HSRD_TOCNT7          0x00000080U
+#define DSI_TCCR1_HSRD_TOCNT8          0x00000100U
+#define DSI_TCCR1_HSRD_TOCNT9          0x00000200U
+#define DSI_TCCR1_HSRD_TOCNT10         0x00000400U
+#define DSI_TCCR1_HSRD_TOCNT11         0x00000800U
+#define DSI_TCCR1_HSRD_TOCNT12         0x00001000U
+#define DSI_TCCR1_HSRD_TOCNT13         0x00002000U
+#define DSI_TCCR1_HSRD_TOCNT14         0x00004000U
+#define DSI_TCCR1_HSRD_TOCNT15         0x00008000U
+
+/*******************  Bit definition for DSI_TCCR2 register  **************/
+#define DSI_TCCR2_LPRD_TOCNT           0x0000FFFFU               /*!< Low-Power Read Timeout Counter */
+#define DSI_TCCR2_LPRD_TOCNT0          0x00000001U
+#define DSI_TCCR2_LPRD_TOCNT1          0x00000002U
+#define DSI_TCCR2_LPRD_TOCNT2          0x00000004U
+#define DSI_TCCR2_LPRD_TOCNT3          0x00000008U
+#define DSI_TCCR2_LPRD_TOCNT4          0x00000010U
+#define DSI_TCCR2_LPRD_TOCNT5          0x00000020U
+#define DSI_TCCR2_LPRD_TOCNT6          0x00000040U
+#define DSI_TCCR2_LPRD_TOCNT7          0x00000080U
+#define DSI_TCCR2_LPRD_TOCNT8          0x00000100U
+#define DSI_TCCR2_LPRD_TOCNT9          0x00000200U
+#define DSI_TCCR2_LPRD_TOCNT10         0x00000400U
+#define DSI_TCCR2_LPRD_TOCNT11         0x00000800U
+#define DSI_TCCR2_LPRD_TOCNT12         0x00001000U
+#define DSI_TCCR2_LPRD_TOCNT13         0x00002000U
+#define DSI_TCCR2_LPRD_TOCNT14         0x00004000U
+#define DSI_TCCR2_LPRD_TOCNT15         0x00008000U
+
+/*******************  Bit definition for DSI_TCCR3 register  **************/
+#define DSI_TCCR3_HSWR_TOCNT           0x0000FFFFU               /*!< High-Speed Write Timeout Counter */
+#define DSI_TCCR3_HSWR_TOCNT0          0x00000001U
+#define DSI_TCCR3_HSWR_TOCNT1          0x00000002U
+#define DSI_TCCR3_HSWR_TOCNT2          0x00000004U
+#define DSI_TCCR3_HSWR_TOCNT3          0x00000008U
+#define DSI_TCCR3_HSWR_TOCNT4          0x00000010U
+#define DSI_TCCR3_HSWR_TOCNT5          0x00000020U
+#define DSI_TCCR3_HSWR_TOCNT6          0x00000040U
+#define DSI_TCCR3_HSWR_TOCNT7          0x00000080U
+#define DSI_TCCR3_HSWR_TOCNT8          0x00000100U
+#define DSI_TCCR3_HSWR_TOCNT9          0x00000200U
+#define DSI_TCCR3_HSWR_TOCNT10         0x00000400U
+#define DSI_TCCR3_HSWR_TOCNT11         0x00000800U
+#define DSI_TCCR3_HSWR_TOCNT12         0x00001000U
+#define DSI_TCCR3_HSWR_TOCNT13         0x00002000U
+#define DSI_TCCR3_HSWR_TOCNT14         0x00004000U
+#define DSI_TCCR3_HSWR_TOCNT15         0x00008000U
+
+#define DSI_TCCR3_PM                   0x01000000U               /*!< Presp Mode */
+
+/*******************  Bit definition for DSI_TCCR4 register  **************/
+#define DSI_TCCR4_LPWR_TOCNT           0x0000FFFFU               /*!< Low-Power Write Timeout Counter */
+#define DSI_TCCR4_LPWR_TOCNT0          0x00000001U
+#define DSI_TCCR4_LPWR_TOCNT1          0x00000002U
+#define DSI_TCCR4_LPWR_TOCNT2          0x00000004U
+#define DSI_TCCR4_LPWR_TOCNT3          0x00000008U
+#define DSI_TCCR4_LPWR_TOCNT4          0x00000010U
+#define DSI_TCCR4_LPWR_TOCNT5          0x00000020U
+#define DSI_TCCR4_LPWR_TOCNT6          0x00000040U
+#define DSI_TCCR4_LPWR_TOCNT7          0x00000080U
+#define DSI_TCCR4_LPWR_TOCNT8          0x00000100U
+#define DSI_TCCR4_LPWR_TOCNT9          0x00000200U
+#define DSI_TCCR4_LPWR_TOCNT10         0x00000400U
+#define DSI_TCCR4_LPWR_TOCNT11         0x00000800U
+#define DSI_TCCR4_LPWR_TOCNT12         0x00001000U
+#define DSI_TCCR4_LPWR_TOCNT13         0x00002000U
+#define DSI_TCCR4_LPWR_TOCNT14         0x00004000U
+#define DSI_TCCR4_LPWR_TOCNT15         0x00008000U
+
+/*******************  Bit definition for DSI_TCCR5register  **************/
+#define DSI_TCCR5_BTA_TOCNT            0x0000FFFFU               /*!< Bus-Turn-Around Timeout Counter */
+#define DSI_TCCR5_BTA_TOCNT0           0x00000001U
+#define DSI_TCCR5_BTA_TOCNT1           0x00000002U
+#define DSI_TCCR5_BTA_TOCNT2           0x00000004U
+#define DSI_TCCR5_BTA_TOCNT3           0x00000008U
+#define DSI_TCCR5_BTA_TOCNT4           0x00000010U
+#define DSI_TCCR5_BTA_TOCNT5           0x00000020U
+#define DSI_TCCR5_BTA_TOCNT6           0x00000040U
+#define DSI_TCCR5_BTA_TOCNT7           0x00000080U
+#define DSI_TCCR5_BTA_TOCNT8           0x00000100U
+#define DSI_TCCR5_BTA_TOCNT9           0x00000200U
+#define DSI_TCCR5_BTA_TOCNT10          0x00000400U
+#define DSI_TCCR5_BTA_TOCNT11          0x00000800U
+#define DSI_TCCR5_BTA_TOCNT12          0x00001000U
+#define DSI_TCCR5_BTA_TOCNT13          0x00002000U
+#define DSI_TCCR5_BTA_TOCNT14          0x00004000U
+#define DSI_TCCR5_BTA_TOCNT15          0x00008000U
+
+/*******************  Bit definition for DSI_TDCR register  ***************/
+#define DSI_TDCR_3DM                   0x00000003U               /*!< 3D Mode */
+#define DSI_TDCR_3DM0                  0x00000001U
+#define DSI_TDCR_3DM1                  0x00000002U
+
+#define DSI_TDCR_3DF                   0x0000000CU               /*!< 3D Format */
+#define DSI_TDCR_3DF0                  0x00000004U
+#define DSI_TDCR_3DF1                  0x00000008U
+
+#define DSI_TDCR_SVS                   0x00000010U               /*!< Second VSYNC */
+#define DSI_TDCR_RF                    0x00000020U               /*!< Right First */
+#define DSI_TDCR_S3DC                  0x00010000U               /*!< Send 3D Control */
+
+/*******************  Bit definition for DSI_CLCR register  ***************/
+#define DSI_CLCR_DPCC                  0x00000001U               /*!< D-PHY Clock Control */
+#define DSI_CLCR_ACR                   0x00000002U               /*!< Automatic Clocklane Control */
+
+/*******************  Bit definition for DSI_CLTCR register  **************/
+#define DSI_CLTCR_LP2HS_TIME           0x000003FFU               /*!< Low-Power to High-Speed Time */
+#define DSI_CLTCR_LP2HS_TIME0          0x00000001U
+#define DSI_CLTCR_LP2HS_TIME1          0x00000002U
+#define DSI_CLTCR_LP2HS_TIME2          0x00000004U
+#define DSI_CLTCR_LP2HS_TIME3          0x00000008U
+#define DSI_CLTCR_LP2HS_TIME4          0x00000010U
+#define DSI_CLTCR_LP2HS_TIME5          0x00000020U
+#define DSI_CLTCR_LP2HS_TIME6          0x00000040U
+#define DSI_CLTCR_LP2HS_TIME7          0x00000080U
+#define DSI_CLTCR_LP2HS_TIME8          0x00000100U
+#define DSI_CLTCR_LP2HS_TIME9          0x00000200U
+
+#define DSI_CLTCR_HS2LP_TIME           0x03FF0000U               /*!< High-Speed to Low-Power Time */
+#define DSI_CLTCR_HS2LP_TIME0          0x00010000U
+#define DSI_CLTCR_HS2LP_TIME1          0x00020000U
+#define DSI_CLTCR_HS2LP_TIME2          0x00040000U
+#define DSI_CLTCR_HS2LP_TIME3          0x00080000U
+#define DSI_CLTCR_HS2LP_TIME4          0x00100000U
+#define DSI_CLTCR_HS2LP_TIME5          0x00200000U
+#define DSI_CLTCR_HS2LP_TIME6          0x00400000U
+#define DSI_CLTCR_HS2LP_TIME7          0x00800000U
+#define DSI_CLTCR_HS2LP_TIME8          0x01000000U
+#define DSI_CLTCR_HS2LP_TIME9          0x02000000U
+
+/*******************  Bit definition for DSI_DLTCR register  **************/
+#define DSI_DLTCR_MRD_TIME             0x00007FFFU               /*!< Maximum Read Time */
+#define DSI_DLTCR_MRD_TIME0            0x00000001U
+#define DSI_DLTCR_MRD_TIME1            0x00000002U
+#define DSI_DLTCR_MRD_TIME2            0x00000004U
+#define DSI_DLTCR_MRD_TIME3            0x00000008U
+#define DSI_DLTCR_MRD_TIME4            0x00000010U
+#define DSI_DLTCR_MRD_TIME5            0x00000020U
+#define DSI_DLTCR_MRD_TIME6            0x00000040U
+#define DSI_DLTCR_MRD_TIME7            0x00000080U
+#define DSI_DLTCR_MRD_TIME8            0x00000100U
+#define DSI_DLTCR_MRD_TIME9            0x00000200U
+#define DSI_DLTCR_MRD_TIME10           0x00000400U
+#define DSI_DLTCR_MRD_TIME11           0x00000800U
+#define DSI_DLTCR_MRD_TIME12           0x00001000U
+#define DSI_DLTCR_MRD_TIME13           0x00002000U
+#define DSI_DLTCR_MRD_TIME14           0x00004000U
+
+#define DSI_DLTCR_LP2HS_TIME           0x00FF0000U               /*!< Low-Power To High-Speed Time */
+#define DSI_DLTCR_LP2HS_TIME0          0x00010000U
+#define DSI_DLTCR_LP2HS_TIME1          0x00020000U
+#define DSI_DLTCR_LP2HS_TIME2          0x00040000U
+#define DSI_DLTCR_LP2HS_TIME3          0x00080000U
+#define DSI_DLTCR_LP2HS_TIME4          0x00100000U
+#define DSI_DLTCR_LP2HS_TIME5          0x00200000U
+#define DSI_DLTCR_LP2HS_TIME6          0x00400000U
+#define DSI_DLTCR_LP2HS_TIME7          0x00800000U
+
+#define DSI_DLTCR_HS2LP_TIME           0xFF000000U               /*!< High-Speed To Low-Power Time */
+#define DSI_DLTCR_HS2LP_TIME0          0x01000000U
+#define DSI_DLTCR_HS2LP_TIME1          0x02000000U
+#define DSI_DLTCR_HS2LP_TIME2          0x04000000U
+#define DSI_DLTCR_HS2LP_TIME3          0x08000000U
+#define DSI_DLTCR_HS2LP_TIME4          0x10000000U
+#define DSI_DLTCR_HS2LP_TIME5          0x20000000U
+#define DSI_DLTCR_HS2LP_TIME6          0x40000000U
+#define DSI_DLTCR_HS2LP_TIME7          0x80000000U
+
+/*******************  Bit definition for DSI_PCTLRregister  **************/
+#define DSI_PCTLR_DEN                  0x00000002U               /*!< Digital Enable */
+#define DSI_PCTLR_CKE                  0x00000004U               /*!< Clock Enable */
+
+/*******************  Bit definition for DSI_PCONFR register  *************/
+#define DSI_PCONFR_NL                  0x00000003U               /*!< Number of Lanes */
+#define DSI_PCONFR_NL0                 0x00000001U
+#define DSI_PCONFR_NL1                 0x00000002U
+
+#define DSI_PCONFR_SW_TIME             0x0000FF00U               /*!< Stop Wait Time */
+#define DSI_PCONFR_SW_TIME0            0x00000100U
+#define DSI_PCONFR_SW_TIME1            0x00000200U
+#define DSI_PCONFR_SW_TIME2            0x00000400U
+#define DSI_PCONFR_SW_TIME3            0x00000800U
+#define DSI_PCONFR_SW_TIME4            0x00001000U
+#define DSI_PCONFR_SW_TIME5            0x00002000U
+#define DSI_PCONFR_SW_TIME6            0x00004000U
+#define DSI_PCONFR_SW_TIME7            0x00008000U
+
+/*******************  Bit definition for DSI_PUCR register  ***************/
+#define DSI_PUCR_URCL                  0x00000001U               /*!< ULPS Request on Clock Lane */
+#define DSI_PUCR_UECL                  0x00000002U               /*!< ULPS Exit on Clock Lane */
+#define DSI_PUCR_URDL                  0x00000004U               /*!< ULPS Request on Data Lane */
+#define DSI_PUCR_UEDL                  0x00000008U               /*!< ULPS Exit on Data Lane */
+
+/*******************  Bit definition for DSI_PTTCRregister  **************/
+#define DSI_PTTCR_TX_TRIG              0x0000000FU               /*!< Transmission Trigger */
+#define DSI_PTTCR_TX_TRIG0             0x00000001U
+#define DSI_PTTCR_TX_TRIG1             0x00000002U
+#define DSI_PTTCR_TX_TRIG2             0x00000004U
+#define DSI_PTTCR_TX_TRIG3             0x00000008U
+
+/*******************  Bit definition for DSI_PSR register  ****************/
+#define DSI_PSR_PD                     0x00000002U               /*!< PHY Direction */
+#define DSI_PSR_PSSC                   0x00000004U               /*!< PHY Stop State Clock lane */
+#define DSI_PSR_UANC                   0x00000008U               /*!< ULPS Active Not Clock lane */
+#define DSI_PSR_PSS0                   0x00000010U               /*!< PHY Stop State lane 0 */
+#define DSI_PSR_UAN0                   0x00000020U               /*!< ULPS Active Not lane 0 */
+#define DSI_PSR_RUE0                   0x00000040U               /*!< RX ULPS Escape lane 0 */
+#define DSI_PSR_PSS1                   0x00000080U               /*!< PHY Stop State lane 1 */
+#define DSI_PSR_UAN1                   0x00000100U               /*!< ULPS Active Not lane 1 */
+
+/*******************  Bit definition for DSI_ISR0 register  ***************/
+#define DSI_ISR0_AE0                   0x00000001U               /*!< Acknowledge Error 0 */
+#define DSI_ISR0_AE1                   0x00000002U               /*!< Acknowledge Error 1 */
+#define DSI_ISR0_AE2                   0x00000004U               /*!< Acknowledge Error 2 */
+#define DSI_ISR0_AE3                   0x00000008U               /*!< Acknowledge Error 3 */
+#define DSI_ISR0_AE4                   0x00000010U               /*!< Acknowledge Error 4 */
+#define DSI_ISR0_AE5                   0x00000020U               /*!< Acknowledge Error 5 */
+#define DSI_ISR0_AE6                   0x00000040U               /*!< Acknowledge Error 6 */
+#define DSI_ISR0_AE7                   0x00000080U               /*!< Acknowledge Error 7 */
+#define DSI_ISR0_AE8                   0x00000100U               /*!< Acknowledge Error 8 */
+#define DSI_ISR0_AE9                   0x00000200U               /*!< Acknowledge Error 9 */
+#define DSI_ISR0_AE10                  0x00000400U               /*!< Acknowledge Error 10 */
+#define DSI_ISR0_AE11                  0x00000800U               /*!< Acknowledge Error 11 */
+#define DSI_ISR0_AE12                  0x00001000U               /*!< Acknowledge Error 12 */
+#define DSI_ISR0_AE13                  0x00002000U               /*!< Acknowledge Error 13 */
+#define DSI_ISR0_AE14                  0x00004000U               /*!< Acknowledge Error 14 */
+#define DSI_ISR0_AE15                  0x00008000U               /*!< Acknowledge Error 15 */
+#define DSI_ISR0_PE0                   0x00010000U               /*!< PHY Error 0 */
+#define DSI_ISR0_PE1                   0x00020000U               /*!< PHY Error 1 */
+#define DSI_ISR0_PE2                   0x00040000U               /*!< PHY Error 2 */
+#define DSI_ISR0_PE3                   0x00080000U               /*!< PHY Error 3 */
+#define DSI_ISR0_PE4                   0x00100000U               /*!< PHY Error 4 */
+
+/*******************  Bit definition for DSI_ISR1 register  ***************/
+#define DSI_ISR1_TOHSTX                0x00000001U               /*!< Timeout High-Speed Transmission */
+#define DSI_ISR1_TOLPRX                0x00000002U               /*!< Timeout Low-Power Reception */
+#define DSI_ISR1_ECCSE                 0x00000004U               /*!< ECC Single-bit Error */
+#define DSI_ISR1_ECCME                 0x00000008U               /*!< ECC Multi-bit Error */
+#define DSI_ISR1_CRCE                  0x00000010U               /*!< CRC Error */
+#define DSI_ISR1_PSE                   0x00000020U               /*!< Packet Size Error */
+#define DSI_ISR1_EOTPE                 0x00000040U               /*!< EoTp Error */
+#define DSI_ISR1_LPWRE                 0x00000080U               /*!< LTDC Payload Write Error */
+#define DSI_ISR1_GCWRE                 0x00000100U               /*!< Generic Command Write Error */
+#define DSI_ISR1_GPWRE                 0x00000200U               /*!< Generic Payload Write Error */
+#define DSI_ISR1_GPTXE                 0x00000400U               /*!< Generic Payload Transmit Error */
+#define DSI_ISR1_GPRDE                 0x00000800U               /*!< Generic Payload Read Error */
+#define DSI_ISR1_GPRXE                 0x00001000U               /*!< Generic Payload Receive Error */
+
+/*******************  Bit definition for DSI_IER0 register  ***************/
+#define DSI_IER0_AE0IE                 0x00000001U               /*!< Acknowledge Error 0 Interrupt Enable */
+#define DSI_IER0_AE1IE                 0x00000002U               /*!< Acknowledge Error 1 Interrupt Enable */
+#define DSI_IER0_AE2IE                 0x00000004U               /*!< Acknowledge Error 2 Interrupt Enable */
+#define DSI_IER0_AE3IE                 0x00000008U               /*!< Acknowledge Error 3 Interrupt Enable */
+#define DSI_IER0_AE4IE                 0x00000010U               /*!< Acknowledge Error 4 Interrupt Enable */
+#define DSI_IER0_AE5IE                 0x00000020U               /*!< Acknowledge Error 5 Interrupt Enable */
+#define DSI_IER0_AE6IE                 0x00000040U               /*!< Acknowledge Error 6 Interrupt Enable */
+#define DSI_IER0_AE7IE                 0x00000080U               /*!< Acknowledge Error 7 Interrupt Enable */
+#define DSI_IER0_AE8IE                 0x00000100U               /*!< Acknowledge Error 8 Interrupt Enable */
+#define DSI_IER0_AE9IE                 0x00000200U               /*!< Acknowledge Error 9 Interrupt Enable */
+#define DSI_IER0_AE10IE                0x00000400U               /*!< Acknowledge Error 10 Interrupt Enable */
+#define DSI_IER0_AE11IE                0x00000800U               /*!< Acknowledge Error 11 Interrupt Enable */
+#define DSI_IER0_AE12IE                0x00001000U               /*!< Acknowledge Error 12 Interrupt Enable */
+#define DSI_IER0_AE13IE                0x00002000U               /*!< Acknowledge Error 13 Interrupt Enable */
+#define DSI_IER0_AE14IE                0x00004000U               /*!< Acknowledge Error 14 Interrupt Enable */
+#define DSI_IER0_AE15IE                0x00008000U               /*!< Acknowledge Error 15 Interrupt Enable */
+#define DSI_IER0_PE0IE                 0x00010000U               /*!< PHY Error 0 Interrupt Enable */
+#define DSI_IER0_PE1IE                 0x00020000U               /*!< PHY Error 1 Interrupt Enable */
+#define DSI_IER0_PE2IE                 0x00040000U               /*!< PHY Error 2 Interrupt Enable */
+#define DSI_IER0_PE3IE                 0x00080000U               /*!< PHY Error 3 Interrupt Enable */
+#define DSI_IER0_PE4IE                 0x00100000U               /*!< PHY Error 4 Interrupt Enable */
+
+/*******************  Bit definition for DSI_IER1 register  ***************/
+#define DSI_IER1_TOHSTXIE              0x00000001U               /*!< Timeout High-Speed Transmission Interrupt Enable */
+#define DSI_IER1_TOLPRXIE              0x00000002U               /*!< Timeout Low-Power Reception Interrupt Enable */
+#define DSI_IER1_ECCSEIE               0x00000004U               /*!< ECC Single-bit Error Interrupt Enable */
+#define DSI_IER1_ECCMEIE               0x00000008U               /*!< ECC Multi-bit Error Interrupt Enable */
+#define DSI_IER1_CRCEIE                0x00000010U               /*!< CRC Error Interrupt Enable */
+#define DSI_IER1_PSEIE                 0x00000020U               /*!< Packet Size Error Interrupt Enable */
+#define DSI_IER1_EOTPEIE               0x00000040U               /*!< EoTp Error Interrupt Enable */
+#define DSI_IER1_LPWREIE               0x00000080U               /*!< LTDC Payload Write Error Interrupt Enable */
+#define DSI_IER1_GCWREIE               0x00000100U               /*!< Generic Command Write Error Interrupt Enable */
+#define DSI_IER1_GPWREIE               0x00000200U               /*!< Generic Payload Write Error Interrupt Enable */
+#define DSI_IER1_GPTXEIE               0x00000400U               /*!< Generic Payload Transmit Error Interrupt Enable */
+#define DSI_IER1_GPRDEIE               0x00000800U               /*!< Generic Payload Read Error Interrupt Enable */
+#define DSI_IER1_GPRXEIE               0x00001000U               /*!< Generic Payload Receive Error Interrupt Enable */
+
+/*******************  Bit definition for DSI_FIR0 register  ***************/
+#define DSI_FIR0_FAE0                  0x00000001U               /*!< Force Acknowledge Error 0 */
+#define DSI_FIR0_FAE1                  0x00000002U               /*!< Force Acknowledge Error 1 */
+#define DSI_FIR0_FAE2                  0x00000004U               /*!< Force Acknowledge Error 2 */
+#define DSI_FIR0_FAE3                  0x00000008U               /*!< Force Acknowledge Error 3 */
+#define DSI_FIR0_FAE4                  0x00000010U               /*!< Force Acknowledge Error 4 */
+#define DSI_FIR0_FAE5                  0x00000020U               /*!< Force Acknowledge Error 5 */
+#define DSI_FIR0_FAE6                  0x00000040U               /*!< Force Acknowledge Error 6 */
+#define DSI_FIR0_FAE7                  0x00000080U               /*!< Force Acknowledge Error 7 */
+#define DSI_FIR0_FAE8                  0x00000100U               /*!< Force Acknowledge Error 8 */
+#define DSI_FIR0_FAE9                  0x00000200U               /*!< Force Acknowledge Error 9 */
+#define DSI_FIR0_FAE10                 0x00000400U               /*!< Force Acknowledge Error 10 */
+#define DSI_FIR0_FAE11                 0x00000800U               /*!< Force Acknowledge Error 11 */
+#define DSI_FIR0_FAE12                 0x00001000U               /*!< Force Acknowledge Error 12 */
+#define DSI_FIR0_FAE13                 0x00002000U               /*!< Force Acknowledge Error 13 */
+#define DSI_FIR0_FAE14                 0x00004000U               /*!< Force Acknowledge Error 14 */
+#define DSI_FIR0_FAE15                 0x00008000U               /*!< Force Acknowledge Error 15 */
+#define DSI_FIR0_FPE0                  0x00010000U               /*!< Force PHY Error 0 */
+#define DSI_FIR0_FPE1                  0x00020000U               /*!< Force PHY Error 1 */
+#define DSI_FIR0_FPE2                  0x00040000U               /*!< Force PHY Error 2 */
+#define DSI_FIR0_FPE3                  0x00080000U               /*!< Force PHY Error 3 */
+#define DSI_FIR0_FPE4                  0x00100000U               /*!< Force PHY Error 4 */
+
+/*******************  Bit definition for DSI_FIR1 register  ***************/
+#define DSI_FIR1_FTOHSTX               0x00000001U               /*!< Force Timeout High-Speed Transmission */
+#define DSI_FIR1_FTOLPRX               0x00000002U               /*!< Force Timeout Low-Power Reception */
+#define DSI_FIR1_FECCSE                0x00000004U               /*!< Force ECC Single-bit Error */
+#define DSI_FIR1_FECCME                0x00000008U               /*!< Force ECC Multi-bit Error */
+#define DSI_FIR1_FCRCE                 0x00000010U               /*!< Force CRC Error */
+#define DSI_FIR1_FPSE                  0x00000020U               /*!< Force Packet Size Error */
+#define DSI_FIR1_FEOTPE                0x00000040U               /*!< Force EoTp Error */
+#define DSI_FIR1_FLPWRE                0x00000080U               /*!< Force LTDC Payload Write Error */
+#define DSI_FIR1_FGCWRE                0x00000100U               /*!< Force Generic Command Write Error */
+#define DSI_FIR1_FGPWRE                0x00000200U               /*!< Force Generic Payload Write Error */
+#define DSI_FIR1_FGPTXE                0x00000400U               /*!< Force Generic Payload Transmit Error */
+#define DSI_FIR1_FGPRDE                0x00000800U               /*!< Force Generic Payload Read Error */
+#define DSI_FIR1_FGPRXE                0x00001000U               /*!< Force Generic Payload Receive Error */
+
+/*******************  Bit definition for DSI_VSCR register  ***************/
+#define DSI_VSCR_EN                    0x00000001U               /*!< Enable */
+#define DSI_VSCR_UR                    0x00000100U               /*!< Update Register */
+
+/*******************  Bit definition for DSI_LCVCIDR register  ************/
+#define DSI_LCVCIDR_VCID               0x00000003U               /*!< Virtual Channel ID */
+#define DSI_LCVCIDR_VCID0              0x00000001U
+#define DSI_LCVCIDR_VCID1              0x00000002U
+
+/*******************  Bit definition for DSI_LCCCR register  **************/
+#define DSI_LCCCR_COLC                 0x0000000FU               /*!< Color Coding */
+#define DSI_LCCCR_COLC0                0x00000001U
+#define DSI_LCCCR_COLC1                0x00000002U
+#define DSI_LCCCR_COLC2                0x00000004U
+#define DSI_LCCCR_COLC3                0x00000008U
+
+#define DSI_LCCCR_LPE                  0x00000100U               /*!< Loosely Packed Enable */
+
+/*******************  Bit definition for DSI_LPMCCR register  *************/
+#define DSI_LPMCCR_VLPSIZE             0x000000FFU               /*!< VACT Largest Packet Size */
+#define DSI_LPMCCR_VLPSIZE0            0x00000001U
+#define DSI_LPMCCR_VLPSIZE1            0x00000002U
+#define DSI_LPMCCR_VLPSIZE2            0x00000004U
+#define DSI_LPMCCR_VLPSIZE3            0x00000008U
+#define DSI_LPMCCR_VLPSIZE4            0x00000010U
+#define DSI_LPMCCR_VLPSIZE5            0x00000020U
+#define DSI_LPMCCR_VLPSIZE6            0x00000040U
+#define DSI_LPMCCR_VLPSIZE7            0x00000080U
+
+#define DSI_LPMCCR_LPSIZE              0x00FF0000U               /*!< Largest Packet Size */
+#define DSI_LPMCCR_LPSIZE0             0x00010000U
+#define DSI_LPMCCR_LPSIZE1             0x00020000U
+#define DSI_LPMCCR_LPSIZE2             0x00040000U
+#define DSI_LPMCCR_LPSIZE3             0x00080000U
+#define DSI_LPMCCR_LPSIZE4             0x00100000U
+#define DSI_LPMCCR_LPSIZE5             0x00200000U
+#define DSI_LPMCCR_LPSIZE6             0x00400000U
+#define DSI_LPMCCR_LPSIZE7             0x00800000U
+
+/*******************  Bit definition for DSI_VMCCR register  **************/
+#define DSI_VMCCR_VMT                  0x00000003U               /*!< Video Mode Type */
+#define DSI_VMCCR_VMT0                 0x00000001U
+#define DSI_VMCCR_VMT1                 0x00000002U
+
+#define DSI_VMCCR_LPVSAE               0x00000100U               /*!< Low-power Vertical Sync time Enable */
+#define DSI_VMCCR_LPVBPE               0x00000200U               /*!< Low-power Vertical Back-porch Enable */
+#define DSI_VMCCR_LPVFPE               0x00000400U               /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCCR_LPVAE                0x00000800U               /*!< Low-power Vertical Active Enable */
+#define DSI_VMCCR_LPHBPE               0x00001000U               /*!< Low-power Horizontal Back-porch Enable */
+#define DSI_VMCCR_LPHFE                0x00002000U               /*!< Low-power Horizontal Front-porch Enable */
+#define DSI_VMCCR_FBTAAE               0x00004000U               /*!< Frame BTA Acknowledge Enable */
+#define DSI_VMCCR_LPCE                 0x00008000U               /*!< Low-power Command Enable */
+
+/*******************  Bit definition for DSI_VPCCR register  **************/
+#define DSI_VPCCR_VPSIZE               0x00003FFFU               /*!< Video Packet Size */
+#define DSI_VPCCR_VPSIZE0              0x00000001U
+#define DSI_VPCCR_VPSIZE1              0x00000002U
+#define DSI_VPCCR_VPSIZE2              0x00000004U
+#define DSI_VPCCR_VPSIZE3              0x00000008U
+#define DSI_VPCCR_VPSIZE4              0x00000010U
+#define DSI_VPCCR_VPSIZE5              0x00000020U
+#define DSI_VPCCR_VPSIZE6              0x00000040U
+#define DSI_VPCCR_VPSIZE7              0x00000080U
+#define DSI_VPCCR_VPSIZE8              0x00000100U
+#define DSI_VPCCR_VPSIZE9              0x00000200U
+#define DSI_VPCCR_VPSIZE10             0x00000400U
+#define DSI_VPCCR_VPSIZE11             0x00000800U
+#define DSI_VPCCR_VPSIZE12             0x00001000U
+#define DSI_VPCCR_VPSIZE13             0x00002000U
+
+/*******************  Bit definition for DSI_VCCCR register  **************/
+#define DSI_VCCCR_NUMC                 0x00001FFFU               /*!< Number of Chunks */
+#define DSI_VCCCR_NUMC0                0x00000001U
+#define DSI_VCCCR_NUMC1                0x00000002U
+#define DSI_VCCCR_NUMC2                0x00000004U
+#define DSI_VCCCR_NUMC3                0x00000008U
+#define DSI_VCCCR_NUMC4                0x00000010U
+#define DSI_VCCCR_NUMC5                0x00000020U
+#define DSI_VCCCR_NUMC6                0x00000040U
+#define DSI_VCCCR_NUMC7                0x00000080U
+#define DSI_VCCCR_NUMC8                0x00000100U
+#define DSI_VCCCR_NUMC9                0x00000200U
+#define DSI_VCCCR_NUMC10               0x00000400U
+#define DSI_VCCCR_NUMC11               0x00000800U
+#define DSI_VCCCR_NUMC12               0x00001000U
+
+/*******************  Bit definition for DSI_VNPCCR register  *************/
+#define DSI_VNPCCR_NPSIZE              0x00001FFFU               /*!< Number of Chunks */
+#define DSI_VNPCCR_NPSIZE0             0x00000001U
+#define DSI_VNPCCR_NPSIZE1             0x00000002U
+#define DSI_VNPCCR_NPSIZE2             0x00000004U
+#define DSI_VNPCCR_NPSIZE3             0x00000008U
+#define DSI_VNPCCR_NPSIZE4             0x00000010U
+#define DSI_VNPCCR_NPSIZE5             0x00000020U
+#define DSI_VNPCCR_NPSIZE6             0x00000040U
+#define DSI_VNPCCR_NPSIZE7             0x00000080U
+#define DSI_VNPCCR_NPSIZE8             0x00000100U
+#define DSI_VNPCCR_NPSIZE9             0x00000200U
+#define DSI_VNPCCR_NPSIZE10            0x00000400U
+#define DSI_VNPCCR_NPSIZE11            0x00000800U
+#define DSI_VNPCCR_NPSIZE12            0x00001000U
+
+/*******************  Bit definition for DSI_VHSACCR register  ************/
+#define DSI_VHSACCR_HSA                0x00000FFFU               /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACCR_HSA0               0x00000001U
+#define DSI_VHSACCR_HSA1               0x00000002U
+#define DSI_VHSACCR_HSA2               0x00000004U
+#define DSI_VHSACCR_HSA3               0x00000008U
+#define DSI_VHSACCR_HSA4               0x00000010U
+#define DSI_VHSACCR_HSA5               0x00000020U
+#define DSI_VHSACCR_HSA6               0x00000040U
+#define DSI_VHSACCR_HSA7               0x00000080U
+#define DSI_VHSACCR_HSA8               0x00000100U
+#define DSI_VHSACCR_HSA9               0x00000200U
+#define DSI_VHSACCR_HSA10              0x00000400U
+#define DSI_VHSACCR_HSA11              0x00000800U
+
+/*******************  Bit definition for DSI_VHBPCCR register  ************/
+#define DSI_VHBPCCR_HBP                0x00000FFFU               /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCCR_HBP0               0x00000001U
+#define DSI_VHBPCCR_HBP1               0x00000002U
+#define DSI_VHBPCCR_HBP2               0x00000004U
+#define DSI_VHBPCCR_HBP3               0x00000008U
+#define DSI_VHBPCCR_HBP4               0x00000010U
+#define DSI_VHBPCCR_HBP5               0x00000020U
+#define DSI_VHBPCCR_HBP6               0x00000040U
+#define DSI_VHBPCCR_HBP7               0x00000080U
+#define DSI_VHBPCCR_HBP8               0x00000100U
+#define DSI_VHBPCCR_HBP9               0x00000200U
+#define DSI_VHBPCCR_HBP10              0x00000400U
+#define DSI_VHBPCCR_HBP11              0x00000800U
+
+/*******************  Bit definition for DSI_VLCCR register  **************/
+#define DSI_VLCCR_HLINE                0x00007FFFU               /*!< Horizontal Line duration */
+#define DSI_VLCCR_HLINE0               0x00000001U
+#define DSI_VLCCR_HLINE1               0x00000002U
+#define DSI_VLCCR_HLINE2               0x00000004U
+#define DSI_VLCCR_HLINE3               0x00000008U
+#define DSI_VLCCR_HLINE4               0x00000010U
+#define DSI_VLCCR_HLINE5               0x00000020U
+#define DSI_VLCCR_HLINE6               0x00000040U
+#define DSI_VLCCR_HLINE7               0x00000080U
+#define DSI_VLCCR_HLINE8               0x00000100U
+#define DSI_VLCCR_HLINE9               0x00000200U
+#define DSI_VLCCR_HLINE10              0x00000400U
+#define DSI_VLCCR_HLINE11              0x00000800U
+#define DSI_VLCCR_HLINE12              0x00001000U
+#define DSI_VLCCR_HLINE13              0x00002000U
+#define DSI_VLCCR_HLINE14              0x00004000U
+
+/*******************  Bit definition for DSI_VVSACCR register  ***************/
+#define DSI_VVSACCR_VSA                0x000003FFU               /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACCR_VSA0               0x00000001U
+#define DSI_VVSACCR_VSA1               0x00000002U
+#define DSI_VVSACCR_VSA2               0x00000004U
+#define DSI_VVSACCR_VSA3               0x00000008U
+#define DSI_VVSACCR_VSA4               0x00000010U
+#define DSI_VVSACCR_VSA5               0x00000020U
+#define DSI_VVSACCR_VSA6               0x00000040U
+#define DSI_VVSACCR_VSA7               0x00000080U
+#define DSI_VVSACCR_VSA8               0x00000100U
+#define DSI_VVSACCR_VSA9               0x00000200U
+
+/*******************  Bit definition for DSI_VVBPCCR register  ************/
+#define DSI_VVBPCCR_VBP                0x000003FFU               /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCCR_VBP0               0x00000001U
+#define DSI_VVBPCCR_VBP1               0x00000002U
+#define DSI_VVBPCCR_VBP2               0x00000004U
+#define DSI_VVBPCCR_VBP3               0x00000008U
+#define DSI_VVBPCCR_VBP4               0x00000010U
+#define DSI_VVBPCCR_VBP5               0x00000020U
+#define DSI_VVBPCCR_VBP6               0x00000040U
+#define DSI_VVBPCCR_VBP7               0x00000080U
+#define DSI_VVBPCCR_VBP8               0x00000100U
+#define DSI_VVBPCCR_VBP9               0x00000200U
+
+/*******************  Bit definition for DSI_VVFPCCR register  ************/
+#define DSI_VVFPCCR_VFP                0x000003FFU               /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCCR_VFP0               0x00000001U
+#define DSI_VVFPCCR_VFP1               0x00000002U
+#define DSI_VVFPCCR_VFP2               0x00000004U
+#define DSI_VVFPCCR_VFP3               0x00000008U
+#define DSI_VVFPCCR_VFP4               0x00000010U
+#define DSI_VVFPCCR_VFP5               0x00000020U
+#define DSI_VVFPCCR_VFP6               0x00000040U
+#define DSI_VVFPCCR_VFP7               0x00000080U
+#define DSI_VVFPCCR_VFP8               0x00000100U
+#define DSI_VVFPCCR_VFP9               0x00000200U
+
+/*******************  Bit definition for DSI_VVACCR register  *************/
+#define DSI_VVACCR_VA                  0x00003FFFU               /*!< Vertical Active duration */
+#define DSI_VVACCR_VA0                 0x00000001U
+#define DSI_VVACCR_VA1                 0x00000002U
+#define DSI_VVACCR_VA2                 0x00000004U
+#define DSI_VVACCR_VA3                 0x00000008U
+#define DSI_VVACCR_VA4                 0x00000010U
+#define DSI_VVACCR_VA5                 0x00000020U
+#define DSI_VVACCR_VA6                 0x00000040U
+#define DSI_VVACCR_VA7                 0x00000080U
+#define DSI_VVACCR_VA8                 0x00000100U
+#define DSI_VVACCR_VA9                 0x00000200U
+#define DSI_VVACCR_VA10                0x00000400U
+#define DSI_VVACCR_VA11                0x00000800U
+#define DSI_VVACCR_VA12                0x00001000U
+#define DSI_VVACCR_VA13                0x00002000U
+
+/*******************  Bit definition for DSI_TDCCR register  **************/
+#define DSI_TDCCR_3DM                  0x00000003U               /*!< 3D Mode */
+#define DSI_TDCCR_3DM0                 0x00000001U
+#define DSI_TDCCR_3DM1                 0x00000002U
+
+#define DSI_TDCCR_3DF                  0x0000000CU               /*!< 3D Format */
+#define DSI_TDCCR_3DF0                 0x00000004U
+#define DSI_TDCCR_3DF1                 0x00000008U
+
+#define DSI_TDCCR_SVS                  0x00000010U               /*!< Second VSYNC */
+#define DSI_TDCCR_RF                   0x00000020U               /*!< Right First */
+#define DSI_TDCCR_S3DC                 0x00010000U               /*!< Send 3D Control */
+
+/*******************  Bit definition for DSI_WCFGR register  ***************/
+#define DSI_WCFGR_DSIM                   0x00000001U              /*!< DSI Mode */
+#define DSI_WCFGR_COLMUX                 0x0000000EU              /*!< Color Multiplexing */
+#define DSI_WCFGR_COLMUX0                0x00000002U
+#define DSI_WCFGR_COLMUX1                0x00000004U
+#define DSI_WCFGR_COLMUX2                0x00000008U
+
+#define DSI_WCFGR_TESRC                  0x00000010U              /*!< Tearing Effect Source */
+#define DSI_WCFGR_TEPOL                  0x00000020U              /*!< Tearing Effect Polarity */
+#define DSI_WCFGR_AR                     0x00000040U              /*!< Automatic Refresh */
+#define DSI_WCFGR_VSPOL                  0x00000080U              /*!< VSync Polarity */
+
+/*******************  Bit definition for DSI_WCR register  *****************/
+#define DSI_WCR_COLM                     0x00000001U              /*!< Color Mode */
+#define DSI_WCR_SHTDN                    0x00000002U              /*!< Shutdown */
+#define DSI_WCR_LTDCEN                   0x00000004U              /*!< LTDC Enable */
+#define DSI_WCR_DSIEN                    0x00000008U              /*!< DSI Enable */
+
+/*******************  Bit definition for DSI_WIER register  ****************/
+#define DSI_WIER_TEIE                    0x00000001U              /*!< Tearing Effect Interrupt Enable */
+#define DSI_WIER_ERIE                    0x00000002U              /*!< End of Refresh Interrupt Enable */
+#define DSI_WIER_PLLLIE                  0x00000200U              /*!< PLL Lock Interrupt Enable */
+#define DSI_WIER_PLLUIE                  0x00000400U              /*!< PLL Unlock Interrupt Enable */
+#define DSI_WIER_RRIE                    0x00002000U              /*!< Regulator Ready Interrupt Enable */
+
+/*******************  Bit definition for DSI_WISR register  ****************/
+#define DSI_WISR_TEIF                    0x00000001U              /*!< Tearing Effect Interrupt Flag */
+#define DSI_WISR_ERIF                    0x00000002U              /*!< End of Refresh Interrupt Flag */
+#define DSI_WISR_BUSY                    0x00000004U              /*!< Busy Flag */
+#define DSI_WISR_PLLLS                   0x00000100U              /*!< PLL Lock Status */
+#define DSI_WISR_PLLLIF                  0x00000200U              /*!< PLL Lock Interrupt Flag */
+#define DSI_WISR_PLLUIF                  0x00000400U              /*!< PLL Unlock Interrupt Flag */
+#define DSI_WISR_RRS                     0x00001000U              /*!< Regulator Ready Flag */
+#define DSI_WISR_RRIF                    0x00002000U              /*!< Regulator Ready Interrupt Flag */
+
+/*******************  Bit definition for DSI_WIFCR register  ***************/
+#define DSI_WIFCR_CTEIF                  0x00000001U              /*!< Clear Tearing Effect Interrupt Flag */
+#define DSI_WIFCR_CERIF                  0x00000002U              /*!< Clear End of Refresh Interrupt Flag */
+#define DSI_WIFCR_CPLLLIF                0x00000200U              /*!< Clear PLL Lock Interrupt Flag */
+#define DSI_WIFCR_CPLLUIF                0x00000400U              /*!< Clear PLL Unlock Interrupt Flag */
+#define DSI_WIFCR_CRRIF                  0x00002000U              /*!< Clear Regulator Ready Interrupt Flag */
+
+/*******************  Bit definition for DSI_WPCR0 register  ***************/
+#define DSI_WPCR0_UIX4                   0x0000003FU              /*!< Unit Interval multiplied by 4 */
+#define DSI_WPCR0_UIX4_0                 0x00000001U
+#define DSI_WPCR0_UIX4_1                 0x00000002U
+#define DSI_WPCR0_UIX4_2                 0x00000004U
+#define DSI_WPCR0_UIX4_3                 0x00000008U
+#define DSI_WPCR0_UIX4_4                 0x00000010U
+#define DSI_WPCR0_UIX4_5                 0x00000020U
+
+#define DSI_WPCR0_SWCL                   0x00000040U              /*!< Swap pins on clock lane */
+#define DSI_WPCR0_SWDL0                  0x00000080U              /*!< Swap pins on data lane 1 */
+#define DSI_WPCR0_SWDL1                  0x00000100U              /*!< Swap pins on data lane 2 */
+#define DSI_WPCR0_HSICL                  0x00000200U              /*!< Invert the high-speed data signal on clock lane */
+#define DSI_WPCR0_HSIDL0                 0x00000400U              /*!< Invert the high-speed data signal on lane 1 */
+#define DSI_WPCR0_HSIDL1                 0x00000800U              /*!< Invert the high-speed data signal on lane 2 */
+#define DSI_WPCR0_FTXSMCL                0x00001000U              /*!< Force clock lane in TX stop mode */
+#define DSI_WPCR0_FTXSMDL                0x00002000U              /*!< Force data lanes in TX stop mode */
+#define DSI_WPCR0_CDOFFDL                0x00004000U              /*!< Contention detection OFF */
+#define DSI_WPCR0_TDDL                   0x00010000U              /*!< Turn Disable Data Lanes */
+#define DSI_WPCR0_PDEN                   0x00040000U              /*!< Pull-Down Enable */
+#define DSI_WPCR0_TCLKPREPEN             0x00080000U              /*!< Timer for t-CLKPREP Enable */
+#define DSI_WPCR0_TCLKZEROEN             0x00100000U              /*!< Timer for t-CLKZERO Enable */
+#define DSI_WPCR0_THSPREPEN              0x00200000U              /*!< Timer for t-HSPREP Enable */
+#define DSI_WPCR0_THSTRAILEN             0x00400000U              /*!< Timer for t-HSTRAIL Enable */
+#define DSI_WPCR0_THSZEROEN              0x00800000U              /*!< Timer for t-HSZERO Enable */
+#define DSI_WPCR0_TLPXDEN                0x01000000U              /*!< Timer for t-LPXD Enable */
+#define DSI_WPCR0_THSEXITEN              0x02000000U              /*!< Timer for t-HSEXIT Enable */
+#define DSI_WPCR0_TLPXCEN                0x04000000U              /*!< Timer for t-LPXC Enable */
+#define DSI_WPCR0_TCLKPOSTEN             0x08000000U              /*!< Timer for t-CLKPOST Enable */
+
+/*******************  Bit definition for DSI_WPCR1 register  ***************/
+#define DSI_WPCR1_HSTXDCL                0x00000003U              /*!< High-Speed Transmission Delay on Clock Lane */
+#define DSI_WPCR1_HSTXDCL0               0x00000001U
+#define DSI_WPCR1_HSTXDCL1               0x00000002U
+
+#define DSI_WPCR1_HSTXDDL                0x0000000CU              /*!< High-Speed Transmission Delay on Data Lane */
+#define DSI_WPCR1_HSTXDDL0               0x00000004U
+#define DSI_WPCR1_HSTXDDL1               0x00000008U
+
+#define DSI_WPCR1_LPSRCCL                0x000000C0U              /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
+#define DSI_WPCR1_LPSRCCL0               0x00000040U
+#define DSI_WPCR1_LPSRCCL1               0x00000080U
+
+#define DSI_WPCR1_LPSRCDL                0x00000300U              /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
+#define DSI_WPCR1_LPSRCDL0               0x00000100U
+#define DSI_WPCR1_LPSRCDL1               0x00000200U
+
+#define DSI_WPCR1_SDDC                   0x00001000U              /*!< SDD Control */
+
+#define DSI_WPCR1_LPRXVCDL               0x0000C000U              /*!< Low-Power Reception V-IL Compensation on Data Lanes */
+#define DSI_WPCR1_LPRXVCDL0              0x00004000U
+#define DSI_WPCR1_LPRXVCDL1              0x00008000U
+
+#define DSI_WPCR1_HSTXSRCCL              0x00030000U              /*!< High-Speed Transmission Delay on Clock Lane */
+#define DSI_WPCR1_HSTXSRCCL0             0x00010000U
+#define DSI_WPCR1_HSTXSRCCL1             0x00020000U
+
+#define DSI_WPCR1_HSTXSRCDL              0x000C0000U              /*!< High-Speed Transmission Delay on Data Lane */
+#define DSI_WPCR1_HSTXSRCDL0             0x00040000U
+#define DSI_WPCR1_HSTXSRCDL1             0x00080000U
+
+#define DSI_WPCR1_FLPRXLPM               0x00400000U              /*!< Forces LP Receiver in Low-Power Mode */
+
+#define DSI_WPCR1_LPRXFT                 0x06000000U              /*!< Low-Power RX low-pass Filtering Tuning */
+#define DSI_WPCR1_LPRXFT0                0x02000000U
+#define DSI_WPCR1_LPRXFT1                0x04000000U
+
+/*******************  Bit definition for DSI_WPCR2 register  ***************/
+#define DSI_WPCR2_TCLKPREP               0x000000FFU              /*!< t-CLKPREP */
+#define DSI_WPCR2_TCLKPREP0              0x00000001U
+#define DSI_WPCR2_TCLKPREP1              0x00000002U
+#define DSI_WPCR2_TCLKPREP2              0x00000004U
+#define DSI_WPCR2_TCLKPREP3              0x00000008U
+#define DSI_WPCR2_TCLKPREP4              0x00000010U
+#define DSI_WPCR2_TCLKPREP5              0x00000020U
+#define DSI_WPCR2_TCLKPREP6              0x00000040U
+#define DSI_WPCR2_TCLKPREP7              0x00000080U
+
+#define DSI_WPCR2_TCLKZERO               0x0000FF00U              /*!< t-CLKZERO */
+#define DSI_WPCR2_TCLKZERO0              0x00000100U
+#define DSI_WPCR2_TCLKZERO1              0x00000200U
+#define DSI_WPCR2_TCLKZERO2              0x00000400U
+#define DSI_WPCR2_TCLKZERO3              0x00000800U
+#define DSI_WPCR2_TCLKZERO4              0x00001000U
+#define DSI_WPCR2_TCLKZERO5              0x00002000U
+#define DSI_WPCR2_TCLKZERO6              0x00004000U
+#define DSI_WPCR2_TCLKZERO7              0x00008000U
+
+#define DSI_WPCR2_THSPREP                0x00FF0000U              /*!< t-HSPREP */
+#define DSI_WPCR2_THSPREP0               0x00010000U
+#define DSI_WPCR2_THSPREP1               0x00020000U
+#define DSI_WPCR2_THSPREP2               0x00040000U
+#define DSI_WPCR2_THSPREP3               0x00080000U
+#define DSI_WPCR2_THSPREP4               0x00100000U
+#define DSI_WPCR2_THSPREP5               0x00200000U
+#define DSI_WPCR2_THSPREP6               0x00400000U
+#define DSI_WPCR2_THSPREP7               0x00800000U
+
+#define DSI_WPCR2_THSTRAIL               0xFF000000U              /*!< t-HSTRAIL */
+#define DSI_WPCR2_THSTRAIL0              0x01000000U
+#define DSI_WPCR2_THSTRAIL1              0x02000000U
+#define DSI_WPCR2_THSTRAIL2              0x04000000U
+#define DSI_WPCR2_THSTRAIL3              0x08000000U
+#define DSI_WPCR2_THSTRAIL4              0x10000000U
+#define DSI_WPCR2_THSTRAIL5              0x20000000U
+#define DSI_WPCR2_THSTRAIL6              0x40000000U
+#define DSI_WPCR2_THSTRAIL7              0x80000000U
+
+/*******************  Bit definition for DSI_WPCR3 register  ***************/
+#define DSI_WPCR3_THSZERO                0x000000FFU              /*!< t-HSZERO */
+#define DSI_WPCR3_THSZERO0               0x00000001U
+#define DSI_WPCR3_THSZERO1               0x00000002U
+#define DSI_WPCR3_THSZERO2               0x00000004U
+#define DSI_WPCR3_THSZERO3               0x00000008U
+#define DSI_WPCR3_THSZERO4               0x00000010U
+#define DSI_WPCR3_THSZERO5               0x00000020U
+#define DSI_WPCR3_THSZERO6               0x00000040U
+#define DSI_WPCR3_THSZERO7               0x00000080U
+
+#define DSI_WPCR3_TLPXD                  0x0000FF00U              /*!< t-LPXD */
+#define DSI_WPCR3_TLPXD0                 0x00000100U
+#define DSI_WPCR3_TLPXD1                 0x00000200U
+#define DSI_WPCR3_TLPXD2                 0x00000400U
+#define DSI_WPCR3_TLPXD3                 0x00000800U
+#define DSI_WPCR3_TLPXD4                 0x00001000U
+#define DSI_WPCR3_TLPXD5                 0x00002000U
+#define DSI_WPCR3_TLPXD6                 0x00004000U
+#define DSI_WPCR3_TLPXD7                 0x00008000U
+
+#define DSI_WPCR3_THSEXIT                0x00FF0000U              /*!< t-HSEXIT */
+#define DSI_WPCR3_THSEXIT0               0x00010000U
+#define DSI_WPCR3_THSEXIT1               0x00020000U
+#define DSI_WPCR3_THSEXIT2               0x00040000U
+#define DSI_WPCR3_THSEXIT3               0x00080000U
+#define DSI_WPCR3_THSEXIT4               0x00100000U
+#define DSI_WPCR3_THSEXIT5               0x00200000U
+#define DSI_WPCR3_THSEXIT6               0x00400000U
+#define DSI_WPCR3_THSEXIT7               0x00800000U
+
+#define DSI_WPCR3_TLPXC                  0xFF000000U              /*!< t-LPXC */
+#define DSI_WPCR3_TLPXC0                 0x01000000U
+#define DSI_WPCR3_TLPXC1                 0x02000000U
+#define DSI_WPCR3_TLPXC2                 0x04000000U
+#define DSI_WPCR3_TLPXC3                 0x08000000U
+#define DSI_WPCR3_TLPXC4                 0x10000000U
+#define DSI_WPCR3_TLPXC5                 0x20000000U
+#define DSI_WPCR3_TLPXC6                 0x40000000U
+#define DSI_WPCR3_TLPXC7                 0x80000000U
+
+/*******************  Bit definition for DSI_WPCR4 register  ***************/
+#define DSI_WPCR4_TCLKPOST               0x000000FFU              /*!< t-CLKPOST */
+#define DSI_WPCR4_TCLKPOST0              0x00000001U
+#define DSI_WPCR4_TCLKPOST1              0x00000002U
+#define DSI_WPCR4_TCLKPOST2              0x00000004U
+#define DSI_WPCR4_TCLKPOST3              0x00000008U
+#define DSI_WPCR4_TCLKPOST4              0x00000010U
+#define DSI_WPCR4_TCLKPOST5              0x00000020U
+#define DSI_WPCR4_TCLKPOST6              0x00000040U
+#define DSI_WPCR4_TCLKPOST7              0x00000080U
+
+/*******************  Bit definition for DSI_WRPCR register  ***************/
+#define DSI_WRPCR_PLLEN                  0x00000001U              /*!< PLL Enable */
+#define DSI_WRPCR_PLL_NDIV               0x000001FCU              /*!< PLL Loop Division Factor */
+#define DSI_WRPCR_PLL_NDIV0              0x00000004U
+#define DSI_WRPCR_PLL_NDIV1              0x00000008U
+#define DSI_WRPCR_PLL_NDIV2              0x00000010U
+#define DSI_WRPCR_PLL_NDIV3              0x00000020U
+#define DSI_WRPCR_PLL_NDIV4              0x00000040U
+#define DSI_WRPCR_PLL_NDIV5              0x00000080U
+#define DSI_WRPCR_PLL_NDIV6              0x00000100U
+
+#define DSI_WRPCR_PLL_IDF                0x00007800U              /*!< PLL Input Division Factor */
+#define DSI_WRPCR_PLL_IDF0               0x00000800U
+#define DSI_WRPCR_PLL_IDF1               0x00001000U
+#define DSI_WRPCR_PLL_IDF2               0x00002000U
+#define DSI_WRPCR_PLL_IDF3               0x00004000U
+
+#define DSI_WRPCR_PLL_ODF                0x00030000U              /*!< PLL Output Division Factor */
+#define DSI_WRPCR_PLL_ODF0               0x00010000U
+#define DSI_WRPCR_PLL_ODF1               0x00020000U
+
+#define DSI_WRPCR_REGEN                  0x01000000U              /*!< Regulator Enable */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
+                                       ((__INSTANCE__) == ADC2) || \
+                                       ((__INSTANCE__) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
+                                           ((__INSTANCE__) == CAN2) || \
+									       ((__INSTANCE__) == CAN3))
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
+
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+                                                ((INSTANCE) == DFSDM1_Filter1) || \
+                                                ((INSTANCE) == DFSDM1_Filter2) || \
+                                                ((INSTANCE) == DFSDM1_Filter3))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+                                                 ((INSTANCE) == DFSDM1_Channel1) || \
+                                                 ((INSTANCE) == DFSDM1_Channel2) || \
+                                                 ((INSTANCE) == DFSDM1_Channel3) || \
+                                                 ((INSTANCE) == DFSDM1_Channel4) || \
+                                                 ((INSTANCE) == DFSDM1_Channel5) || \
+                                                 ((INSTANCE) == DFSDM1_Channel6) || \
+                                                 ((INSTANCE) == DFSDM1_Channel7))
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
+                                              ((__INSTANCE__) == DMA1_Stream1) || \
+                                              ((__INSTANCE__) == DMA1_Stream2) || \
+                                              ((__INSTANCE__) == DMA1_Stream3) || \
+                                              ((__INSTANCE__) == DMA1_Stream4) || \
+                                              ((__INSTANCE__) == DMA1_Stream5) || \
+                                              ((__INSTANCE__) == DMA1_Stream6) || \
+                                              ((__INSTANCE__) == DMA1_Stream7) || \
+                                              ((__INSTANCE__) == DMA2_Stream0) || \
+                                              ((__INSTANCE__) == DMA2_Stream1) || \
+                                              ((__INSTANCE__) == DMA2_Stream2) || \
+                                              ((__INSTANCE__) == DMA2_Stream3) || \
+                                              ((__INSTANCE__) == DMA2_Stream4) || \
+                                              ((__INSTANCE__) == DMA2_Stream5) || \
+                                              ((__INSTANCE__) == DMA2_Stream6) || \
+                                              ((__INSTANCE__) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
+                                        ((__INSTANCE__) == GPIOB) || \
+                                        ((__INSTANCE__) == GPIOC) || \
+                                        ((__INSTANCE__) == GPIOD) || \
+                                        ((__INSTANCE__) == GPIOE) || \
+                                        ((__INSTANCE__) == GPIOF) || \
+                                        ((__INSTANCE__) == GPIOG) || \
+                                        ((__INSTANCE__) == GPIOH) || \
+                                        ((__INSTANCE__) == GPIOI) || \
+                                        ((__INSTANCE__) == GPIOJ) || \
+                                        ((__INSTANCE__) == GPIOK))
+										
+#define IS_GPIO_AF_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == GPIOA) || \
+                                        ((__INSTANCE__) == GPIOB) || \
+                                        ((__INSTANCE__) == GPIOC) || \
+                                        ((__INSTANCE__) == GPIOD) || \
+                                        ((__INSTANCE__) == GPIOE) || \
+                                        ((__INSTANCE__) == GPIOF) || \
+                                        ((__INSTANCE__) == GPIOG) || \
+                                        ((__INSTANCE__) == GPIOH) || \
+                                        ((__INSTANCE__) == GPIOI) || \
+                                        ((__INSTANCE__) == GPIOJ) || \
+                                        ((__INSTANCE__) == GPIOK))
+
+/****************************** CEC Instances *********************************/
+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
+
+/****************************** QSPI Instances *********************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+
+                                        
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
+                                       ((__INSTANCE__) == I2C2) || \
+                                       ((__INSTANCE__) == I2C3) || \
+                                       ((__INSTANCE__) == I2C4))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == SPI1) || \
+                                    ((__INSTANCE__) == SPI2) || \
+                                    ((__INSTANCE__) == SPI3))
+
+/******************************* LPTIM Instances ********************************/
+#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == LTDC)
+
+/****************************** MDIOS Instances ********************************/
+#define IS_MDIOS_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == MDIOS)
+
+/****************************** MDIOS Instances ********************************/
+#define IS_JPEG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == JPEG)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
+                                         ((__PERIPH__) == SAI1_Block_B) || \
+                                         ((__PERIPH__) == SAI2_Block_A) || \
+                                         ((__PERIPH__) == SAI2_Block_B))
+/* Legacy define */
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
+
+/******************************** SDMMC Instances *******************************/
+#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || \
+                                             ((__INSTANCE__) == SDMMC2))
+
+/****************************** SPDIFRX Instances *********************************/
+#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
+                                     
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
+                                       ((__INSTANCE__) == SPI2) || \
+                                       ((__INSTANCE__) == SPI3) || \
+                                       ((__INSTANCE__) == SPI4) || \
+                                       ((__INSTANCE__) == SPI5) || \
+                                       ((__INSTANCE__) == SPI6))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)   || \
+                                   ((__INSTANCE__) == TIM2)   || \
+                                   ((__INSTANCE__) == TIM3)   || \
+                                   ((__INSTANCE__) == TIM4)   || \
+                                   ((__INSTANCE__) == TIM5)   || \
+                                   ((__INSTANCE__) == TIM6)   || \
+                                   ((__INSTANCE__) == TIM7)   || \
+                                   ((__INSTANCE__) == TIM8)   || \
+                                   ((__INSTANCE__) == TIM9)   || \
+                                   ((__INSTANCE__) == TIM10)  || \
+                                   ((__INSTANCE__) == TIM11)  || \
+                                   ((__INSTANCE__) == TIM12)  || \
+                                   ((__INSTANCE__) == TIM13)  || \
+                                   ((__INSTANCE__) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \
+                                         ((__INSTANCE__) == TIM2)  || \
+                                         ((__INSTANCE__) == TIM3)  || \
+                                         ((__INSTANCE__) == TIM4)  || \
+                                         ((__INSTANCE__) == TIM5)  || \
+                                         ((__INSTANCE__) == TIM8)  || \
+                                         ((__INSTANCE__) == TIM9)  || \
+                                         ((__INSTANCE__) == TIM10) || \
+                                         ((__INSTANCE__) == TIM11) || \
+                                         ((__INSTANCE__) == TIM12) || \
+                                         ((__INSTANCE__) == TIM13) || \
+                                         ((__INSTANCE__) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \
+                                         ((__INSTANCE__) == TIM2)  || \
+                                         ((__INSTANCE__) == TIM3)  || \
+                                         ((__INSTANCE__) == TIM4)  || \
+                                         ((__INSTANCE__) == TIM5)  || \
+                                         ((__INSTANCE__) == TIM8)  || \
+                                         ((__INSTANCE__) == TIM9)  || \
+                                         ((__INSTANCE__) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \
+                                         ((__INSTANCE__) == TIM2) || \
+                                         ((__INSTANCE__) == TIM3) || \
+                                         ((__INSTANCE__) == TIM4) || \
+                                         ((__INSTANCE__) == TIM5) || \
+                                         ((__INSTANCE__) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                       ((__INSTANCE__) == TIM2) || \
+                                       ((__INSTANCE__) == TIM3) || \
+                                       ((__INSTANCE__) == TIM4) || \
+                                       ((__INSTANCE__) == TIM5) || \
+                                       ((__INSTANCE__) == TIM8))
+                                       
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
+                                       (((__INSTANCE__) == TIM1)    || \
+                                        ((__INSTANCE__) == TIM8))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
+                                  (((__INSTANCE__) == TIM1)    || \
+                                   ((__INSTANCE__) == TIM2)    || \
+                                   ((__INSTANCE__) == TIM3)    || \
+                                   ((__INSTANCE__) == TIM4)    || \
+                                   ((__INSTANCE__) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
+                                                 (((__INSTANCE__) == TIM1)    || \
+                                                  ((__INSTANCE__) == TIM2)    || \
+                                                  ((__INSTANCE__) == TIM3)    || \
+                                                  ((__INSTANCE__) == TIM4)    || \
+                                                  ((__INSTANCE__) == TIM5)    || \
+                                                  ((__INSTANCE__) == TIM8))
+ 
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
+                                                   (((__INSTANCE__) == TIM1)    || \
+                                                    ((__INSTANCE__) == TIM2)    || \
+                                                    ((__INSTANCE__) == TIM3)    || \
+                                                    ((__INSTANCE__) == TIM4)    || \
+                                                    ((__INSTANCE__) == TIM5)    || \
+                                                    ((__INSTANCE__) == TIM8))
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
+  (((__INSTANCE__) == TIM1)    || \
+   ((__INSTANCE__) == TIM8) )
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
+  (((__INSTANCE__) == TIM1)    || \
+   ((__INSTANCE__) == TIM8))
+
+                                       
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                            ((__INSTANCE__) == TIM8))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
+  (((__INSTANCE__) == TIM1)    || \
+   ((__INSTANCE__) == TIM8))
+   
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \
+                                         ((__INSTANCE__) == TIM2) || \
+                                         ((__INSTANCE__) == TIM3) || \
+                                         ((__INSTANCE__) == TIM4) || \
+                                         ((__INSTANCE__) == TIM5) || \
+                                         ((__INSTANCE__) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                       ((__INSTANCE__) == TIM2) || \
+                                       ((__INSTANCE__) == TIM3) || \
+                                       ((__INSTANCE__) == TIM4) || \
+                                       ((__INSTANCE__) == TIM5) || \
+                                       ((__INSTANCE__) == TIM6) || \
+                                       ((__INSTANCE__) == TIM7) || \
+                                       ((__INSTANCE__) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                          ((__INSTANCE__) == TIM2) || \
+                                          ((__INSTANCE__) == TIM3) || \
+                                          ((__INSTANCE__) == TIM4) || \
+                                          ((__INSTANCE__) == TIM5) || \
+                                          ((__INSTANCE__) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
+                                          ((__INSTANCE__) == TIM2) || \
+                                          ((__INSTANCE__) == TIM3) || \
+                                          ((__INSTANCE__) == TIM4) || \
+                                          ((__INSTANCE__) == TIM5) || \
+                                          ((__INSTANCE__) == TIM8)) 
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
+                                             ((__INSTANCE__) == TIM2) || \
+                                             ((__INSTANCE__) == TIM3) || \
+                                             ((__INSTANCE__) == TIM4) || \
+                                             ((__INSTANCE__) == TIM5) || \
+                                             ((__INSTANCE__) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                          ((__INSTANCE__) == TIM2) || \
+                                          ((__INSTANCE__) == TIM3) || \
+                                          ((__INSTANCE__) == TIM4) || \
+                                          ((__INSTANCE__) == TIM5) || \
+                                          ((__INSTANCE__) == TIM6) || \
+                                          ((__INSTANCE__) == TIM7) || \
+                                          ((__INSTANCE__) == TIM8) || \
+                                          ((__INSTANCE__) == TIM13) || \
+                                          ((__INSTANCE__) == TIM14))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                         ((__INSTANCE__) == TIM2) || \
+                                         ((__INSTANCE__) == TIM3) || \
+                                         ((__INSTANCE__) == TIM4) || \
+                                         ((__INSTANCE__) == TIM5) || \
+                                         ((__INSTANCE__) == TIM8) || \
+                                         ((__INSTANCE__) == TIM9) || \
+                                         ((__INSTANCE__) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
+                                              ((__INSTANCE__) == TIM5))
+
+/***************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
+                                        ((__INSTANCE__) == TIM2) || \
+                                        ((__INSTANCE__) == TIM3) || \
+                                        ((__INSTANCE__) == TIM4) || \
+                                        ((__INSTANCE__) == TIM5) || \
+                                        ((__INSTANCE__) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2)  || \
+                                         ((__INSTANCE__) == TIM5)  || \
+                                         ((__INSTANCE__) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
+    ((((__INSTANCE__) == TIM1) &&                  \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM2) &&                   \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM3) &&                   \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM4) &&                   \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM5) &&                   \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM8) &&                   \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM9) &&                   \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM10) &&                  \
+     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM11) &&                  \
+     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM12) &&                  \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM13) &&                  \
+     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM14) &&                  \
+     (((__CHANNEL__) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
+   ((((__INSTANCE__) == TIM1) &&                    \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \
+      ((__CHANNEL__) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((__INSTANCE__) == TIM8) &&                    \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \
+      ((__CHANNEL__) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
+  (((__INSTANCE__) == TIM1)    || \
+   ((__INSTANCE__) == TIM8) )
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
+    (((__INSTANCE__) == TIM1)    || \
+     ((__INSTANCE__) == TIM2)    || \
+     ((__INSTANCE__) == TIM3)    || \
+     ((__INSTANCE__) == TIM4)    || \
+     ((__INSTANCE__) == TIM5)    || \
+     ((__INSTANCE__) == TIM6)    || \
+     ((__INSTANCE__) == TIM7)    || \
+     ((__INSTANCE__) == TIM8))  
+      
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
+                                     ((__INSTANCE__) == USART2) || \
+                                     ((__INSTANCE__) == USART3) || \
+                                     ((__INSTANCE__) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
+                                    ((__INSTANCE__) == USART2) || \
+                                    ((__INSTANCE__) == USART3) || \
+                                    ((__INSTANCE__) == UART4)  || \
+                                    ((__INSTANCE__) == UART5)  || \
+                                    ((__INSTANCE__) == USART6) || \
+                                    ((__INSTANCE__) == UART7)  || \
+                                    ((__INSTANCE__) == UART8))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
+                                    ((__INSTANCE__) == USART2) || \
+                                    ((__INSTANCE__) == USART3) || \
+                                    ((__INSTANCE__) == UART4)  || \
+                                    ((__INSTANCE__) == UART5)  || \
+                                    ((__INSTANCE__) == USART6) || \
+                                    ((__INSTANCE__) == UART7)  || \
+                                    ((__INSTANCE__) == UART8))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
+                                    ((__INSTANCE__) == USART2) || \
+                                    ((__INSTANCE__) == USART3) || \
+                                    ((__INSTANCE__) == UART4)  || \
+                                    ((__INSTANCE__) == UART5)  || \
+                                    ((__INSTANCE__) == USART6) || \
+                                    ((__INSTANCE__) == UART7)  || \
+                                    ((__INSTANCE__) == UART8))
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
+                                         ((__INSTANCE__) == USART2) || \
+                                         ((__INSTANCE__) == USART3) || \
+                                         ((__INSTANCE__) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
+                                    ((__INSTANCE__) == USART2) || \
+                                    ((__INSTANCE__) == USART3) || \
+                                    ((__INSTANCE__) == UART4)  || \
+                                    ((__INSTANCE__) == UART5)  || \
+                                    ((__INSTANCE__) == USART6) || \
+                                    ((__INSTANCE__) == UART7)  || \
+                                    ((__INSTANCE__) == UART8))     
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == WWDG)
+
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32F7xx device product       */
+/*  lines, the aliases defined below are put in place to overcome the         */
+/*  differences in the interrupt handlers and IRQn definitions.               */
+/*  No need to update developed interrupt code when moving across             */
+/*  product lines within the same STM32F7 Family                              */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define HASH_RNG_IRQn              RNG_IRQn
+
+/* Aliases for __IRQHandler */
+#define HASH_RNG_IRQHandler        RNG_IRQHandler
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F769xx_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7xx.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,216 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx.h
+  * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    22-April-2016
+  * @brief   CMSIS STM32F7xx Device Peripheral Access Layer Header File.           
+  *            
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32F7xx device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral’s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_HAL_DRIVER"
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f7xx
+  * @{
+  */
+    
+#ifndef __STM32F7xx_H
+#define __STM32F7xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined  (STM32F7)
+#define STM32F7
+#endif /* STM32F7 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \
+    !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx)
+  /* #define STM32F756xx */   /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,
+                                   STM32F756NG Devices */
+  /* #define STM32F746xx */   /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,
+                                   STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */
+  /* #define STM32F745xx */   /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */
+  /* #define STM32F765xx */   /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,
+                                   STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */
+  /* #define STM32F767xx */   /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,
+                                   STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI, STM32F768AI Devices */
+#define STM32F769xx    /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,
+                                   STM32F769NG, STM32F769NI Devices */
+  /* #define STM32F777xx */   /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI, STM32F778AI Devices */
+  /* #define STM32F779xx */   /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI Devices */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V1.1.0
+  */
+#define __STM32F7_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32F7_CMSIS_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
+#define __STM32F7_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F7_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F7_CMSIS_VERSION        ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
+                                       |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
+                                       |(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\
+                                       |(__STM32F7_CMSIS_VERSION))
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+#if defined(STM32F756xx)
+  #include "stm32f756xx.h"
+#elif defined(STM32F746xx)
+  #include "stm32f746xx.h"
+#elif defined(STM32F745xx)
+  #include "stm32f745xx.h"
+#elif defined(STM32F765xx)
+  #include "stm32f765xx.h"
+#elif defined(STM32F767xx)
+  #include "stm32f767xx.h"
+#elif defined(STM32F769xx)
+  #include "stm32f769xx.h"
+#elif defined(STM32F777xx)
+  #include "stm32f777xx.h"
+#elif defined(STM32F779xx)
+  #include "stm32f779xx.h"  
+#else
+ #error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */ 
+typedef enum 
+{
+  RESET = 0, 
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum 
+{
+  DISABLE = 0, 
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum 
+{
+  ERROR = 0, 
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Exported_macro
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
+
+/**
+  * @}
+  */
+
+#ifdef USE_HAL_DRIVER
+  #include "stm32f7xx_hal_conf.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F7xx_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7xx_hal_conf.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,454 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_conf_template.h
+  * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    22-April-2016
+  * @brief   HAL configuration template file. 
+  *          This file should be copied to the application folder and renamed
+  *          to stm32f7xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_CONF_H
+#define __STM32F7xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+#define HAL_MODULE_ENABLED  
+#define HAL_ADC_MODULE_ENABLED  
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_CEC_MODULE_ENABLED  
+#define HAL_CRC_MODULE_ENABLED  
+#define HAL_CRYP_MODULE_ENABLED  
+#define HAL_DAC_MODULE_ENABLED  
+#define HAL_DCMI_MODULE_ENABLED 
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_DMA2D_MODULE_ENABLED 
+#define HAL_ETH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_SDRAM_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED  
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED   
+#define HAL_IWDG_MODULE_ENABLED 
+#define HAL_LPTIM_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED 
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_QSPI_MODULE_ENABLED   
+#define HAL_RCC_MODULE_ENABLED 
+#define HAL_RNG_MODULE_ENABLED   
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED   
+#define HAL_SD_MODULE_ENABLED  
+#define HAL_SPDIFRX_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED   
+#define HAL_TIM_MODULE_ENABLED   
+#define HAL_UART_MODULE_ENABLED 
+#define HAL_USART_MODULE_ENABLED 
+#define HAL_IRDA_MODULE_ENABLED 
+#define HAL_SMARTCARD_MODULE_ENABLED 
+#define HAL_WWDG_MODULE_ENABLED  
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+#define HAL_DFSDM_MODULE_ENABLED
+#define HAL_DSI_MODULE_ENABLED
+#define HAL_JPEG_MODULE_ENABLED
+#define HAL_MDIOS_MODULE_ENABLED
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    25000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    200U   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    16000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  32000U                  /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  32768U    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    5000U   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source 
+  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    3300U /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            0x0FU /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
+#define  ART_ACCLERATOR_ENABLE        1U /* To enable instruction cache and prefetch */
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2U
+#define MAC_ADDR1   0U
+#define MAC_ADDR2   0U
+#define MAC_ADDR3   0U
+#define MAC_ADDR4   0U
+#define MAC_ADDR5   0U
+
+/* Definition of the Ethernet driver buffers size and count */   
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    4U       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    4U       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/ 
+#define DP83848_PHY_ADDRESS             0x01U
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+#define PHY_RESET_DELAY                 0x000000FFU
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                0x00000FFFU
+
+#define PHY_READ_TO                     0x0000FFFFU
+#define PHY_WRITE_TO                    0x0000FFFFU
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x00U)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x01U)    /*!< Transceiver Basic Status Register    */
+ 
+#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */
+  
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR                          ((uint16_t)0x10U)    /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x11U)    /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x12U)    /*!< MII Interrupt Status and Misc. Control Register */
+ 
+#define PHY_LINK_STATUS                 ((uint16_t)0x0001U)  /*!< PHY Link mask                                   */
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002U)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004U)  /*!< PHY Duplex mask                                 */
+
+#define PHY_MICR_INT_EN                 ((uint16_t)0x0002U)  /*!< PHY Enable interrupts                           */
+#define PHY_MICR_INT_OE                 ((uint16_t)0x0001U)  /*!< PHY Enable output interrupt events              */
+
+#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020U)  /*!< Enable Interrupt on change of link status       */
+#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000U)  /*!< PHY link status interrupt mask                  */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                     1U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f7xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f7xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f7xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+   
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f7xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f7xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f7xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+  #include "stm32f7xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f7xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f7xx_hal_cryp.h" 
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f7xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f7xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f7xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f7xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f7xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+ 
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f7xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f7xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f7xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f7xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */      
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f7xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f7xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f7xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f7xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32f7xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f7xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f7xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32f7xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f7xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f7xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f7xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f7xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32f7xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f7xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f7xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f7xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f7xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f7xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f7xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f7xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f7xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f7xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32f7xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+ #include "stm32f7xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+ #include "stm32f7xx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_MDIOS_MODULE_ENABLED
+ #include "stm32f7xx_hal_mdios.h"
+#endif /* HAL_MDIOS_MODULE_ENABLED */
+   
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_HAL_CONF_H */
+ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/system_stm32f7xx.c	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,852 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f7xx.c
+  * @author  MCD Application Team
+  * @version V1.0.2
+  * @date    21-September-2015
+  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from 
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f7xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source       | [1] PLL_HSE_XTAL      | [2] PLL_HSI if [1] fails
+  *                           | (external 25MHz xtal) | (internal 16MHz clock)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)               | 216                   | 216
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)              | 216                   | 216
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)             |  54                   |  54
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)             | 108                   | 108
+  *-----------------------------------------------------------------------------
+  * USB capable               | YES                   |  NO
+  * with 48 MHz precise clock |                       |
+  *-----------------------------------------------------------------------------  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f7xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F7xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f7xx.h"
+#include "hal_tick.h"
+
+HAL_StatusTypeDef HAL_Init(void);
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
+     on STMicroelectronics EVAL/Discovery boards as data memory  */
+/*!< In case of EVAL/Discovery’s LCD use in application code, the DATA_IN_ExtSDRAM define
+     need to be added  in the project preprocessor to avoid SDRAM multiple configuration
+     (the LCD uses SDRAM as frame buffer, and its configuration is done by the BSP_SDRAM_Init()) */
+/* #define DATA_IN_ExtSRAM */ 
+/* #define DATA_IN_ExtSDRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Macros
+  * @{
+  */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */ 
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Variables
+  * @{
+  */
+
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+uint32_t SystemCoreClock = HSI_VALUE;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
+  * @{
+  */
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* Configure the Cube driver */
+  SystemCoreClock = HSI_VALUE; // At this stage the HSI is used as system clock
+  HAL_Init();
+
+  // Enable CPU L1-Cache
+  SCB_EnableICache();
+  SCB_EnableDCache();
+
+  /* Configure the System clock source, PLL Multiplier and Divider factors,
+     AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+  
+  /* Reset the timer to avoid issues after the RAM initialization */
+  TIM_MST_RESET_ON;
+  TIM_MST_RESET_OFF;  
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f7xx.s before jump to main.
+  *         This function configures the external memories (SRAM/SDRAM)
+  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+  __IO uint32_t tmp = 0;
+#if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
+  register uint32_t tmpreg = 0, timeout = 0xFFFF;
+  register uint32_t index;
+
+  /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
+      clock */
+  RCC->AHB1ENR |= 0x000001F8;
+
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
+
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CCC0CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A8A;
+
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0FCF;  
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x55550545;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00CC0CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA828A;
+  /* Configure PEx pins speed to 50 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC3CF;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x55554145;  
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCCC000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA800AAA;
+  /* Configure PFx pins speed to 50 MHz */ 
+  GPIOF->OSPEEDR = 0xFF800FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x55400555;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CC00CC;
+  GPIOG->AFR[1]  = 0xC00000CC;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x80220AAA;
+  /* Configure PGx pins speed to 50 MHz */ 
+  GPIOG->OSPEEDR = 0x80320FFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x40110555;
+
+  /* Connect PHx pins to FMC Alternate function */
+  GPIOH->AFR[0]  = 0x00C0CC00;
+  GPIOH->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PHx pins in Alternate function mode */ 
+  GPIOH->MODER   = 0xAAAA08A0;
+  /* Configure PHx pins speed to 50 MHz */ 
+  GPIOH->OSPEEDR = 0xAAAA08A0;
+  /* Configure PHx pins Output type to push-pull */  
+  GPIOH->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PHx pins */ 
+  GPIOH->PUPDR   = 0x55550450;
+
+  /* Connect PIx pins to FMC Alternate function */
+  GPIOI->AFR[0]  = 0xCCCCCCCC;
+  GPIOI->AFR[1]  = 0x00000CC0;
+  /* Configure PIx pins in Alternate function mode */ 
+  GPIOI->MODER   = 0x0028AAAA;
+  /* Configure PIx pins speed to 50 MHz */ 
+  GPIOI->OSPEEDR = 0x0028AAAA;
+  /* Configure PIx pins Output type to push-pull */  
+  GPIOI->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PIx pins */ 
+  GPIOI->PUPDR   = 0x00145555;
+
+/*-- FMC Configuration ------------------------------------------------------*/
+  /* Enable the FMC interface clock */
+  RCC->AHB3ENR |= 0x00000001;
+  
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[4]  = 0x00001091;
+  FMC_Bank1->BTCR[5]  = 0x00110212;
+  FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
+
+  /* Configure and enable SDRAM bank1 */
+  FMC_Bank5_6->SDCR[0] = 0x000019E5;
+  FMC_Bank5_6->SDTR[0] = 0x01116361;   
+
+  /* SDRAM initialization sequence */
+  /* Clock enable command */
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+
+  /* Delay */
+  for (index = 0; index<1000; index++);
+  
+  /* PALL command */
+  FMC_Bank5_6->SDCMR = 0x00000012;           
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+  
+  /* Auto refresh command */
+  FMC_Bank5_6->SDCMR = 0x000000F3;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+ 
+  /* MRD register program */
+  FMC_Bank5_6->SDCMR = 0x00046014;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
+  /* Set refresh count */
+  tmpreg = FMC_Bank5_6->SDRTR;
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
+  
+  /* Disable write protection */
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
+  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);  
+  
+#elif defined (DATA_IN_ExtSDRAM)
+  register uint32_t tmpreg = 0, timeout = 0xFFFF;
+  register uint32_t index;
+
+  /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
+      clock */
+  RCC->AHB1ENR |= 0x000001F8;
+  
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
+  
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x000000CC;
+  GPIOD->AFR[1]  = 0xCC000CCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xA02A000A;
+  /* Configure PDx pins speed to 50 MHz */  
+  GPIOD->OSPEEDR = 0xA02A000A;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x50150005;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 50 MHz */ 
+  GPIOE->OSPEEDR = 0xAAAA800A;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x55554005;
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCCC000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA800AAA;
+  /* Configure PFx pins speed to 50 MHz */ 
+  GPIOF->OSPEEDR = 0xAA800AAA;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x55400555;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CC00CC;
+  GPIOG->AFR[1]  = 0xC000000C;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x80020A0A;
+  /* Configure PGx pins speed to 50 MHz */ 
+  GPIOG->OSPEEDR = 0x80020A0A;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x40010505;
+  
+  /* Connect PHx pins to FMC Alternate function */
+  GPIOH->AFR[0]  = 0x00C0CC00;
+  GPIOH->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PHx pins in Alternate function mode */ 
+  GPIOH->MODER   = 0xAAAA08A0;
+  /* Configure PHx pins speed to 50 MHz */ 
+  GPIOH->OSPEEDR = 0xAAAA08A0;
+  /* Configure PHx pins Output type to push-pull */  
+  GPIOH->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PHx pins */ 
+  GPIOH->PUPDR   = 0x55550450;
+  
+  /* Connect PIx pins to FMC Alternate function */
+  GPIOI->AFR[0]  = 0xCCCCCCCC;
+  GPIOI->AFR[1]  = 0x00000CC0;
+  /* Configure PIx pins in Alternate function mode */ 
+  GPIOI->MODER   = 0x0028AAAA;
+  /* Configure PIx pins speed to 50 MHz */ 
+  GPIOI->OSPEEDR = 0x0028AAAA;
+  /* Configure PIx pins Output type to push-pull */  
+  GPIOI->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PIx pins */ 
+  GPIOI->PUPDR   = 0x00145555;
+  
+/*-- FMC Configuration ------------------------------------------------------*/
+  /* Enable the FMC interface clock */
+  RCC->AHB3ENR |= 0x00000001;
+  
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+  /* Configure and enable SDRAM bank1 */
+  FMC_Bank5_6->SDCR[0] = 0x000019E5;
+  FMC_Bank5_6->SDTR[0] = 0x01116361;      
+  
+  /* SDRAM initialization sequence */
+  /* Clock enable command */
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+
+  /* Delay */
+  for (index = 0; index<1000; index++);
+  
+  /* PALL command */
+  FMC_Bank5_6->SDCMR = 0x00000012;           
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+  
+  /* Auto refresh command */
+  FMC_Bank5_6->SDCMR = 0x000000F3;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+ 
+  /* MRD register program */
+  FMC_Bank5_6->SDCMR = 0x00046014;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
+  /* Set refresh count */
+  tmpreg = FMC_Bank5_6->SDRTR;
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
+  
+  /* Disable write protection */
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
+  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+  
+#elif defined(DATA_IN_ExtSRAM)
+/*-- GPIOs Configuration -----------------------------------------------------*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   |= 0x00000078;
+  
+    /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
+  
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CCC0CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A8A;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0FCF;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x55550545;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00CC0CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA828A;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC3CF;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x55554145;
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x55000555;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x000000C0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00200AAA;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x00300FFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00100555;
+  
+/*-- FMC/FSMC Configuration --------------------------------------------------*/                                                                               
+  /* Enable the FMC/FSMC interface clock */
+  RCC->AHB3ENR         |= 0x00000001;
+  
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[4]  = 0x00001091;
+  FMC_Bank1->BTCR[5]  = 0x00110212;
+  FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;  
+
+#endif /* DATA_IN_ExtSRAM */
+
+  (void)(tmp);
+}
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).             
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+  /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+  if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+  {
+    /* 2- If fail try to start with HSE and external xtal */
+    #if USE_PLL_HSE_XTAL != 0
+    if (SetSysClock_PLL_HSE(0) == 0)
+    #endif
+    {
+      /* 3- If fail start with HSI clock */
+      if (SetSysClock_PLL_HSI() == 0)
+      {
+        while(1)
+        {
+          // [TODO] Put something here to tell the user that a problem occured...
+        }
+      }
+    }
+  }
+  
+  // Output clock on MCO2 pin(PC9) for debugging purpose
+  // Can be visualized on CN8 connector pin 4
+  //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  // Enable power clock  
+  __PWR_CLK_ENABLE();
+  
+  // Enable HSE oscillator and activate PLL with HSE as source
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+  if (bypass == 0)
+  {
+    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
+  }
+  else
+  {
+    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External clock on OSC_IN */
+  }
+  // Warning: this configuration is for a 8 MHz xtal clock only
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM            = 25;             // VCO input clock = 1 MHz (25 MHz / 25)
+  RCC_OscInitStruct.PLL.PLLN            = 432;           // VCO output clock = 432 MHz (1 MHz * 432)
+  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
+  RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
+  
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+
+  // Activate the OverDrive to reach the 216 MHz Frequency
+  if (HAL_PWREx_EnableOverDrive() != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+  
+  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
+  
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+
+  return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  // Enable CPU L1-Cache
+  SCB_EnableICache();
+  SCB_EnableDCache();
+
+  // Enable power clock  
+  __PWR_CLK_ENABLE();
+ 
+  // Enable HSI oscillator and activate PLL with HSI as source
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+  RCC_OscInitStruct.HSICalibrationValue = 16;
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;   
+  RCC_OscInitStruct.PLL.PLLM            = 16;            // VCO input clock = 1 MHz (16 MHz / 16)
+  RCC_OscInitStruct.PLL.PLLN            = 432;           // VCO output clock = 432 MHz (1 MHz * 432)
+  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
+  RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
+  
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+ 
+  // Activate the OverDrive to reach the 216 MHz Frequency
+  if (HAL_PWREx_EnableOverDrive() != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+  
+  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+
+  return 1; // OK
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/system_stm32f7xx.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,126 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f7xx.h
+  * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    22-April-2016
+  * @brief   CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.       
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f7xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F7XX_H
+#define __SYSTEM_STM32F7XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F7xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F7xx_System_Exported_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+    */
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */
+extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F7XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.c	Fri Sep 16 16:24:25 2016 +0100
@@ -40,6 +40,12 @@
     kSAI_Error        /*!< Transfer error occured. */
 };
 
+/*! @brief Typedef for sai tx interrupt handler. */
+typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle);
+
+/*! @brief Typedef for sai rx interrupt handler. */
+typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle);
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -98,6 +104,10 @@
 static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS;
 /* Clock name array */
 static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS;
+/*! @brief Pointer to tx IRQ handler for each instance. */
+static sai_tx_isr_t s_saiTxIsr;
+/*! @brief Pointer to tx IRQ handler for each instance. */
+static sai_rx_isr_t s_saiRxIsr;
 
 /*******************************************************************************
  * Code
@@ -231,12 +241,13 @@
     CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]);
 
 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
-    /* Configure Master clock output enable */
-    base->MCR = I2S_MCR_MOE(config->mclkOutputEnable);
-
     /* Master clock source setting */
     val = (base->MCR & ~I2S_MCR_MICS_MASK);
     base->MCR = (val | I2S_MCR_MICS(config->mclkSource));
+
+    /* Configure Master clock output enable */
+    val = (base->MCR & ~I2S_MCR_MOE_MASK);
+    base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable));
 #endif /* FSL_FEATURE_SAI_HAS_MCR */
 
     /* Configure audio protocol */
@@ -332,12 +343,13 @@
     CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]);
 
 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
-    /* Configure Master clock output enable */
-    base->MCR = I2S_MCR_MOE(config->mclkOutputEnable);
-
     /* Master clock source setting */
     val = (base->MCR & ~I2S_MCR_MICS_MASK);
     base->MCR = (val | I2S_MCR_MICS(config->mclkSource));
+
+    /* Configure Master clock output enable */
+    val = (base->MCR & ~I2S_MCR_MOE_MASK);
+    base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable));
 #endif /* FSL_FEATURE_SAI_HAS_MCR */
 
     /* Configure audio protocol */
@@ -663,6 +675,9 @@
     handle->callback = callback;
     handle->userData = userData;
 
+    /* Set the isr pointer */
+    s_saiTxIsr = SAI_TransferTxHandleIRQ;
+
     /* Enable Tx irq */
     EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]);
 }
@@ -676,6 +691,9 @@
     handle->callback = callback;
     handle->userData = userData;
 
+    /* Set the isr pointer */
+    s_saiRxIsr = SAI_TransferRxHandleIRQ;
+
     /* Enable Rx irq */
     EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]);
 }
@@ -1011,24 +1029,24 @@
 {
     if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)))
     {
-        SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]);
+        s_saiRxIsr(I2S0, s_saiHandle[0][1]);
     }
     if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)))
     {
-        SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]);
+        s_saiTxIsr(I2S0, s_saiHandle[0][0]);
     }
 }
 #else
 void I2S0_Tx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[0][0]);
-    SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]);
+    s_saiTxIsr(I2S0, s_saiHandle[0][0]);
 }
 
 void I2S0_Rx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[0][1]);
-    SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]);
+    s_saiRxIsr(I2S0, s_saiHandle[0][1]);
 }
 #endif /* FSL_FEATURE_SAI_INT_SOURCE_NUM */
 #endif /* I2S0*/
@@ -1037,12 +1055,12 @@
 void I2S1_Tx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[1][0]);
-    SAI_TransferTxHandleIRQ(I2S1, s_saiHandle[1][0]);
+    s_saiTxIsr(I2S1, s_saiHandle[1][0]);
 }
 
 void I2S1_Rx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[1][1]);
-    SAI_TransferRxHandleIRQ(I2S1, s_saiHandle[1][1]);
+    s_saiRxIsr(I2S1, s_saiHandle[1][1]);
 }
 #endif

--- a/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.h	Fri Sep 16 16:24:25 2016 +0100
@@ -38,7 +38,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -46,7 +45,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */
+#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */
 /*@}*/
 
 /*! @brief SAI return status*/
@@ -168,7 +167,7 @@
 } sai_fifo_packing_t;
 #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */
 
-/*! @brief SAI user configure structure */
+/*! @brief SAI user configuration structure */
 typedef struct _sai_config
 {
     sai_protocol_t protocol;  /*!< Audio bus protocol in SAI */
@@ -276,7 +275,7 @@
  * because the clock is not enabled.
  *
  * @param base SAI base pointer
- * @param config SAI configure structure.
+ * @param config SAI configuration structure.
 */
 void SAI_TxInit(I2S_Type *base, const sai_config_t *config);
 
@@ -292,7 +291,7 @@
  * because the clock is not enabled.
  *
  * @param base SAI base pointer
- * @param config SAI configure structure.
+ * @param config SAI configuration structure.
  */
 void SAI_RxInit(I2S_Type *base, const sai_config_t *config);
 

--- a/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.c	Fri Sep 16 16:24:25 2016 +0100
@@ -73,6 +73,9 @@
     kFLEXCAN_TxMbNotUsed = 0xF,      /*!< Not used.*/
 };
 
+/* Typedef for interrupt handler. */
+typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle);
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -86,23 +89,24 @@
 uint32_t FLEXCAN_GetInstance(CAN_Type *base);
 
 /*!
- * @brief Enter FlexCAN Fraze Mode.
+ * @brief Enter FlexCAN Freeze Mode.
  *
- * This function makes the FlexCAN work under Fraze Mode.
+ * This function makes the FlexCAN work under Freeze Mode.
  *
  * @param base FlexCAN peripheral base address.
  */
-static void FLEXCAN_EnterFrazeMode(CAN_Type *base);
+static void FLEXCAN_EnterFreezeMode(CAN_Type *base);
 
 /*!
- * @brief Exit FlexCAN Fraze Mode.
+ * @brief Exit FlexCAN Freeze Mode.
  *
- * This function makes the FlexCAN leave Fraze Mode.
+ * This function makes the FlexCAN leave Freeze Mode.
  *
  * @param base FlexCAN peripheral base address.
  */
-static void FLEXCAN_ExitFrazeMode(CAN_Type *base);
+static void FLEXCAN_ExitFreezeMode(CAN_Type *base);
 
+#if !defined(NDEBUG)
 /*!
  * @brief Check if Message Buffer is occupied by Rx FIFO.
  *
@@ -112,6 +116,19 @@
  * @param mbIdx The FlexCAN Message Buffer index.
  */
 static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx);
+#endif
+
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+/*!
+ * @brief Get the first valid Message buffer ID of give FlexCAN instance.
+ *
+ * This function is a helper function for Errata 5641 workaround.
+ *
+ * @param base FlexCAN peripheral base address.
+ * @return The first valid Message Buffer Number.
+ */
+static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base);
+#endif
 
 /*!
  * @brief Check if Message Buffer interrupt is enabled.
@@ -165,6 +182,9 @@
 /* Array of FlexCAN clock name. */
 static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS;
 
+/* FlexCAN ISR for transactional APIs. */
+static flexcan_isr_t s_flexcanIsr;
+
 /*******************************************************************************
  * Code
  ******************************************************************************/
@@ -187,10 +207,10 @@
     return instance;
 }
 
-static void FLEXCAN_EnterFrazeMode(CAN_Type *base)
+static void FLEXCAN_EnterFreezeMode(CAN_Type *base)
 {
     /* Set Freeze, Halt bits. */
-    base->MCR |= CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK;
+    base->MCR |= CAN_MCR_HALT_MASK;
 
     /* Wait until the FlexCAN Module enter freeze mode. */
     while (!(base->MCR & CAN_MCR_FRZACK_MASK))
@@ -198,10 +218,10 @@
     }
 }
 
-static void FLEXCAN_ExitFrazeMode(CAN_Type *base)
+static void FLEXCAN_ExitFreezeMode(CAN_Type *base)
 {
     /* Clear Freeze, Halt bits. */
-    base->MCR &= ~(CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK);
+    base->MCR &= ~CAN_MCR_HALT_MASK;
 
     /* Wait until the FlexCAN Module exit freeze mode. */
     while (base->MCR & CAN_MCR_FRZACK_MASK)
@@ -209,6 +229,7 @@
     }
 }
 
+#if !defined(NDEBUG)
 static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx)
 {
     uint8_t lastOccupiedMb;
@@ -221,7 +242,11 @@
         /* Calculate the number of last Message Buffer occupied by Rx FIFO. */
         lastOccupiedMb = ((lastOccupiedMb + 1) * 2) + 5;
 
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+        if (mbIdx <= (lastOccupiedMb + 1))
+#else
         if (mbIdx <= lastOccupiedMb)
+#endif
         {
             return true;
         }
@@ -232,9 +257,40 @@
     }
     else
     {
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+        if (0 == mbIdx)
+        {
+            return true;
+        }
+        else
+        {
+            return false;
+        }
+#else
         return false;
+#endif
     }
 }
+#endif
+
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base)
+{
+    uint32_t firstValidMbNum;
+
+    if (base->MCR & CAN_MCR_RFEN_MASK)
+    {
+        firstValidMbNum = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT);
+        firstValidMbNum = ((firstValidMbNum + 1) * 2) + 6;
+    }
+    else
+    {
+        firstValidMbNum = 0;
+    }
+
+    return firstValidMbNum;
+}
+#endif
 
 static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx)
 {
@@ -296,7 +352,7 @@
     base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK |
                  CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1);
 #else
-        base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1);
+    base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1);
 #endif
 
     /* Reset CTRL1 and CTRL2 rigister. */
@@ -387,7 +443,7 @@
     /* Reset to known status. */
     FLEXCAN_Reset(base);
 
-    /* Save current MCR value. */
+    /* Save current MCR value and enable to enter Freeze mode(enabled by default). */
     mcrTemp = base->MCR;
 
     /* Set the maximum number of Message Buffers */
@@ -448,8 +504,8 @@
     /* Assertion. */
     assert(config);
 
-    /* Enter Fraze Mode. */
-    FLEXCAN_EnterFrazeMode(base);
+    /* Enter Freeze Mode. */
+    FLEXCAN_EnterFreezeMode(base);
 
     /* Cleaning previous Timing Setting. */
     base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK |
@@ -460,59 +516,55 @@
         (CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) |
          CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | CAN_CTRL1_PROPSEG(config->propSeg));
 
-    /* Exit Fraze Mode. */
-    FLEXCAN_ExitFrazeMode(base);
+    /* Exit Freeze Mode. */
+    FLEXCAN_ExitFreezeMode(base);
 }
 
-void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask)
+void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask)
 {
-    /* Enter Fraze Mode. */
-    FLEXCAN_EnterFrazeMode(base);
+    /* Enter Freeze Mode. */
+    FLEXCAN_EnterFreezeMode(base);
 
     /* Setting Rx Message Buffer Global Mask value. */
     base->RXMGMASK = mask;
     base->RX14MASK = mask;
     base->RX15MASK = mask;
 
-    /* Exit Fraze Mode. */
-    FLEXCAN_ExitFrazeMode(base);
+    /* Exit Freeze Mode. */
+    FLEXCAN_ExitFreezeMode(base);
 }
 
-void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask)
+void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask)
 {
-    /* Enter Fraze Mode. */
-    FLEXCAN_EnterFrazeMode(base);
+    /* Enter Freeze Mode. */
+    FLEXCAN_EnterFreezeMode(base);
 
     /* Setting Rx FIFO Global Mask value. */
     base->RXFGMASK = mask;
 
-    /* Exit Fraze Mode. */
-    FLEXCAN_ExitFrazeMode(base);
+    /* Exit Freeze Mode. */
+    FLEXCAN_ExitFreezeMode(base);
 }
 
-void FlEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask)
+void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask)
 {
     assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
 
-    /* Enter Fraze Mode. */
-    FLEXCAN_EnterFrazeMode(base);
+    /* Enter Freeze Mode. */
+    FLEXCAN_EnterFreezeMode(base);
 
     /* Setting Rx Individual Mask value. */
     base->RXIMR[maskIdx] = mask;
 
-    /* Exit Fraze Mode. */
-    FLEXCAN_ExitFrazeMode(base);
+    /* Exit Freeze Mode. */
+    FLEXCAN_ExitFreezeMode(base);
 }
 
 void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)
 {
     /* Assertion. */
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-
-    if (FLEXCAN_IsMbOccupied(base, mbIdx))
-    {
-        assert(false);
-    }
+    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
 
     /* Inactivate Message Buffer. */
     if (enable)
@@ -535,14 +587,10 @@
     /* Assertion. */
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
     assert(((config) || (false == enable)));
+    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
 
     uint32_t cs_temp = 0;
 
-    if (FLEXCAN_IsMbOccupied(base, mbIdx))
-    {
-        assert(false);
-    }
-
     /* Inactivate Message Buffer. */
     base->MB[mbIdx].CS = 0;
 
@@ -574,7 +622,7 @@
     }
 }
 
-void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable)
+void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable)
 {
     /* Assertion. */
     assert((config) || (false == enable));
@@ -582,8 +630,8 @@
     volatile uint32_t *idFilterRegion = (volatile uint32_t *)(&base->MB[6].CS);
     uint8_t setup_mb, i, rffn = 0;
 
-    /* Enter Fraze Mode. */
-    FLEXCAN_EnterFrazeMode(base);
+    /* Enter Freeze Mode. */
+    FLEXCAN_EnterFreezeMode(base);
 
     if (enable)
     {
@@ -675,8 +723,8 @@
         FLEXCAN_SetRxMbConfig(base, 5, NULL, false);
     }
 
-    /* Exit Fraze Mode. */
-    FLEXCAN_ExitFrazeMode(base);
+    /* Exit Freeze Mode. */
+    FLEXCAN_ExitFreezeMode(base);
 }
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA)
@@ -684,25 +732,25 @@
 {
     if (enable)
     {
-        /* Enter Fraze Mode. */
-        FLEXCAN_EnterFrazeMode(base);
+        /* Enter Freeze Mode. */
+        FLEXCAN_EnterFreezeMode(base);
 
         /* Enable FlexCAN DMA. */
         base->MCR |= CAN_MCR_DMA_MASK;
 
-        /* Exit Fraze Mode. */
-        FLEXCAN_ExitFrazeMode(base);
+        /* Exit Freeze Mode. */
+        FLEXCAN_ExitFreezeMode(base);
     }
     else
     {
-        /* Enter Fraze Mode. */
-        FLEXCAN_EnterFrazeMode(base);
+        /* Enter Freeze Mode. */
+        FLEXCAN_EnterFreezeMode(base);
 
         /* Disable FlexCAN DMA. */
         base->MCR &= ~CAN_MCR_DMA_MASK;
 
-        /* Exit Fraze Mode. */
-        FLEXCAN_ExitFrazeMode(base);
+        /* Exit Freeze Mode. */
+        FLEXCAN_ExitFreezeMode(base);
     }
 }
 #endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */
@@ -713,14 +761,10 @@
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
     assert(txFrame);
     assert(txFrame->length <= 8);
+    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
 
     uint32_t cs_temp = 0;
 
-    if (FLEXCAN_IsMbOccupied(base, mbIdx))
-    {
-        assert(false);
-    }
-
     /* Check if Message Buffer is available. */
     if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK))
     {
@@ -751,6 +795,11 @@
         /* Activate Tx Message Buffer. */
         base->MB[mbIdx].CS = cs_temp;
 
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+        base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
+        base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
+#endif
+
         return kStatus_Success;
     }
     else
@@ -765,15 +814,11 @@
     /* Assertion. */
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
     assert(rxFrame);
+    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
 
     uint32_t cs_temp;
     uint8_t rx_code;
 
-    if (FLEXCAN_IsMbOccupied(base, mbIdx))
-    {
-        assert(false);
-    }
-
     /* Read CS field of Rx Message Buffer to lock Message Buffer. */
     cs_temp = base->MB[mbIdx].CS;
     /* Get Rx Message Buffer Code field. */
@@ -819,7 +864,7 @@
     }
 }
 
-status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame)
+status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame)
 {
     /* Assertion. */
     assert(rxFrame);
@@ -863,7 +908,7 @@
     }
 }
 
-status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame)
+status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame)
 {
     /* Write Tx Message Buffer to initiate a data sending. */
     if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, txFrame))
@@ -884,7 +929,7 @@
     }
 }
 
-status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame)
+status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame)
 {
     /* Wait until Rx Message Buffer non-empty. */
     while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx))
@@ -898,7 +943,7 @@
     return FLEXCAN_ReadRxMb(base, mbIdx, rxFrame);
 }
 
-status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame)
+status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame)
 {
     status_t rxFifoStatus;
 
@@ -908,7 +953,7 @@
     }
 
     /*  */
-    rxFifoStatus = FlEXCAN_ReadRxFifo(base, rxFrame);
+    rxFifoStatus = FLEXCAN_ReadRxFifo(base, rxFrame);
 
     /* Clean Rx Fifo available flag. */
     FLEXCAN_ClearMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag);
@@ -938,6 +983,8 @@
     handle->callback = callback;
     handle->userData = userData;
 
+    s_flexcanIsr = FLEXCAN_TransferHandleIRQ;
+
     /* We Enable Error & Status interrupt here, because this interrupt just
      * report current status of FlexCAN module through Callback function.
      * It is insignificance without a available callback function.
@@ -970,11 +1017,7 @@
     assert(handle);
     assert(xfer);
     assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-
-    if (FLEXCAN_IsMbOccupied(base, xfer->mbIdx))
-    {
-        assert(false);
-    }
+    assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx));
 
     /* Check if Message Buffer is idle. */
     if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx])
@@ -1017,11 +1060,7 @@
     assert(handle);
     assert(xfer);
     assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-
-    if (FLEXCAN_IsMbOccupied(base, xfer->mbIdx))
-    {
-        assert(false);
-    }
+    assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx));
 
     /* Check if Message Buffer is idle. */
     if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx])
@@ -1073,11 +1112,7 @@
     /* Assertion. */
     assert(handle);
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-
-    if (FLEXCAN_IsMbOccupied(base, mbIdx))
-    {
-        assert(false);
-    }
+    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
 
     /* Disable Message Buffer Interrupt. */
     FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx);
@@ -1096,11 +1131,7 @@
     /* Assertion. */
     assert(handle);
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-
-    if (FLEXCAN_IsMbOccupied(base, mbIdx))
-    {
-        assert(false);
-    }
+    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
 
     /* Disable Message Buffer Interrupt. */
     FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx);
@@ -1185,7 +1216,7 @@
                         break;
 
                     case kFLEXCAN_RxFifoFrameAvlFlag:
-                        status = FlEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf);
+                        status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf);
                         if (kStatus_Success == status)
                         {
                             status = kStatus_FLEXCAN_RxFifoIdle;
@@ -1273,7 +1304,7 @@
 {
     assert(s_flexcanHandle[0]);
 
-    FLEXCAN_TransferHandleIRQ(CAN0, s_flexcanHandle[0]);
+    s_flexcanIsr(CAN0, s_flexcanHandle[0]);
 }
 #endif
 
@@ -1282,7 +1313,7 @@
 {
     assert(s_flexcanHandle[1]);
 
-    FLEXCAN_TransferHandleIRQ(CAN1, s_flexcanHandle[1]);
+    s_flexcanIsr(CAN1, s_flexcanHandle[1]);
 }
 #endif
 
@@ -1291,7 +1322,7 @@
 {
     assert(s_flexcanHandle[2]);
 
-    FLEXCAN_TransferHandleIRQ(CAN2, s_flexcanHandle[2]);
+    s_flexcanIsr(CAN2, s_flexcanHandle[2]);
 }
 #endif
 
@@ -1300,7 +1331,7 @@
 {
     assert(s_flexcanHandle[3]);
 
-    FLEXCAN_TransferHandleIRQ(CAN3, s_flexcanHandle[3]);
+    s_flexcanIsr(CAN3, s_flexcanHandle[3]);
 }
 #endif
 
@@ -1309,6 +1340,6 @@
 {
     assert(s_flexcanHandle[4]);
 
-    FLEXCAN_TransferHandleIRQ(CAN4, s_flexcanHandle[4]);
+    s_flexcanIsr(CAN4, s_flexcanHandle[4]);
 }
 #endif

--- a/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.h	Fri Sep 16 16:24:25 2016 +0100
@@ -37,7 +37,6 @@
  * @{
  */
 
-/*! @file*/
 
 /******************************************************************************
  * Definitions
@@ -87,10 +86,8 @@
     (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
      (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */
 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide)                        \
-    (                                                                             \
-        ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
-        ((FLEXCAN_ID_EXT(id) & 0x1FFF8000)                                        \
-         << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */
+    (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
+     ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */
 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide)                      \
     (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \
      ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >>                                     \
@@ -296,13 +293,13 @@
         uint32_t length : 4;     /*!< CAN frame payload length in bytes(Range: 0~8). */
         uint32_t type : 1;       /*!< CAN Frame Type(DATA or REMOTE). */
         uint32_t format : 1;     /*!< CAN Frame Identifier(STD or EXT format). */
-        uint32_t reserve1 : 1;   /*!< Reserved for placeholder. */
+        uint32_t : 1;            /*!< Reserved. */
         uint32_t idhit : 9;      /*!< CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode). */
     };
     struct
     {
         uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */
-        uint32_t reserve2 : 3; /*!< Reserved for place holder. */
+        uint32_t : 3;     /*!< Reserved. */
     };
     union
     {
@@ -366,7 +363,7 @@
     flexcan_frame_type_t type;     /*!< CAN Frame Type(Data or Remote). */
 } flexcan_rx_mb_config_t;
 
-/*! @brief FlexCAN Rx FIFO configure structure. */
+/*! @brief FlexCAN Rx FIFO configuration structure. */
 typedef struct _flexcan_rx_fifo_config
 {
     uint32_t *idFilterTable;                    /*!< Pointer to FlexCAN Rx FIFO identifier filter table. */
@@ -437,7 +434,7 @@
  * to call the FLEXCAN_Init function by passing in these parameters:
  *  @code
  *   flexcan_config_t flexcanConfig;
- *   flexcanConfig.clkSrc            = KFLEXCAN_ClkSrcOsc;
+ *   flexcanConfig.clkSrc            = kFLEXCAN_ClkSrcOsc;
  *   flexcanConfig.baudRate          = 125000U;
  *   flexcanConfig.maxMbNum          = 16;
  *   flexcanConfig.enableLoopBack    = false;
@@ -466,7 +463,7 @@
 /*!
  * @brief Get the default configuration structure.
  *
- * This function initializes the FlexCAN configure structure to default value. The default
+ * This function initializes the FlexCAN configuration structure to default value. The default
  * value are:
  *   flexcanConfig->clkSrc            = KFLEXCAN_ClkSrcOsc;
  *   flexcanConfig->baudRate          = 125000U;
@@ -512,7 +509,7 @@
  * @param base FlexCAN peripheral base address.
  * @param mask Rx Message Buffer Global Mask value.
  */
-void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask);
+void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask);
 
 /*!
  * @brief Sets the FlexCAN receive FIFO global mask.
@@ -522,7 +519,7 @@
  * @param base FlexCAN peripheral base address.
  * @param mask Rx Fifo Global Mask value.
  */
-void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask);
+void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask);
 
 /*!
  * @brief Sets the FlexCAN receive individual mask.
@@ -538,7 +535,7 @@
  * @param maskIdx The Index of individual Mask.
  * @param mask Rx Individual Mask value.
  */
-void FlEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask);
+void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask);
 
 /*!
  * @brief Configures a FlexCAN transmit message buffer.
@@ -580,7 +577,7 @@
  *               - true: Enable Rx FIFO.
  *               - false: Disable Rx FIFO.
  */
-void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable);
+void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable);
 
 /* @} */
 
@@ -629,7 +626,7 @@
  * @param txErrBuf Buffer to store Tx Error Counter value.
  * @param rxErrBuf Buffer to store Rx Error Counter value.
  */
-static inline void FlEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)
+static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)
 {
     if (txErrBuf)
     {
@@ -890,7 +887,7 @@
  * @retval kStatus_Success - Read Message from Rx FIFO successfully.
  * @retval kStatus_Fail    - Rx FIFO is not enabled.
  */
-status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame);
+status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame);
 
 /* @} */
 
@@ -910,7 +907,7 @@
  * @retval kStatus_Success - Write Tx Message Buffer Successfully.
  * @retval kStatus_Fail    - Tx Message Buffer is currently in use.
  */
-status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame);
+status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame);
 
 /*!
  * @brief Performs a polling receive transaction on the CAN bus.
@@ -924,7 +921,7 @@
  * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully.
  * @retval kStatus_Fail               - Rx Message Buffer is empty.
  */
-status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame);
+status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame);
 
 /*!
  * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus.
@@ -936,7 +933,7 @@
  * @retval kStatus_Success - Read Message from Rx FIFO successfully.
  * @retval kStatus_Fail    - Rx FIFO is not enabled.
  */
-status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame);
+status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame);
 
 /*!
  * @brief Initializes the FlexCAN handle.

--- a/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.c	Fri Sep 16 16:24:25 2016 +0100
@@ -40,6 +40,12 @@
     kSAI_Error        /*!< Transfer error occured. */
 };
 
+/*! @brief Typedef for sai tx interrupt handler. */
+typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle);
+
+/*! @brief Typedef for sai rx interrupt handler. */
+typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle);
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -98,6 +104,10 @@
 static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS;
 /* Clock name array */
 static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS;
+/*! @brief Pointer to tx IRQ handler for each instance. */
+static sai_tx_isr_t s_saiTxIsr;
+/*! @brief Pointer to tx IRQ handler for each instance. */
+static sai_rx_isr_t s_saiRxIsr;
 
 /*******************************************************************************
  * Code
@@ -231,12 +241,13 @@
     CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]);
 
 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
-    /* Configure Master clock output enable */
-    base->MCR = I2S_MCR_MOE(config->mclkOutputEnable);
-
     /* Master clock source setting */
     val = (base->MCR & ~I2S_MCR_MICS_MASK);
     base->MCR = (val | I2S_MCR_MICS(config->mclkSource));
+
+    /* Configure Master clock output enable */
+    val = (base->MCR & ~I2S_MCR_MOE_MASK);
+    base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable));
 #endif /* FSL_FEATURE_SAI_HAS_MCR */
 
     /* Configure audio protocol */
@@ -332,12 +343,13 @@
     CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]);
 
 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
-    /* Configure Master clock output enable */
-    base->MCR = I2S_MCR_MOE(config->mclkOutputEnable);
-
     /* Master clock source setting */
     val = (base->MCR & ~I2S_MCR_MICS_MASK);
     base->MCR = (val | I2S_MCR_MICS(config->mclkSource));
+
+    /* Configure Master clock output enable */
+    val = (base->MCR & ~I2S_MCR_MOE_MASK);
+    base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable));
 #endif /* FSL_FEATURE_SAI_HAS_MCR */
 
     /* Configure audio protocol */
@@ -663,6 +675,9 @@
     handle->callback = callback;
     handle->userData = userData;
 
+    /* Set the isr pointer */
+    s_saiTxIsr = SAI_TransferTxHandleIRQ;
+
     /* Enable Tx irq */
     EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]);
 }
@@ -676,6 +691,9 @@
     handle->callback = callback;
     handle->userData = userData;
 
+    /* Set the isr pointer */
+    s_saiRxIsr = SAI_TransferRxHandleIRQ;
+
     /* Enable Rx irq */
     EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]);
 }
@@ -1011,24 +1029,24 @@
 {
     if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)))
     {
-        SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]);
+        s_saiRxIsr(I2S0, s_saiHandle[0][1]);
     }
     if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)))
     {
-        SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]);
+        s_saiTxIsr(I2S0, s_saiHandle[0][0]);
     }
 }
 #else
 void I2S0_Tx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[0][0]);
-    SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]);
+    s_saiTxIsr(I2S0, s_saiHandle[0][0]);
 }
 
 void I2S0_Rx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[0][1]);
-    SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]);
+    s_saiRxIsr(I2S0, s_saiHandle[0][1]);
 }
 #endif /* FSL_FEATURE_SAI_INT_SOURCE_NUM */
 #endif /* I2S0*/
@@ -1037,12 +1055,12 @@
 void I2S1_Tx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[1][0]);
-    SAI_TransferTxHandleIRQ(I2S1, s_saiHandle[1][0]);
+    s_saiTxIsr(I2S1, s_saiHandle[1][0]);
 }
 
 void I2S1_Rx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[1][1]);
-    SAI_TransferRxHandleIRQ(I2S1, s_saiHandle[1][1]);
+    s_saiRxIsr(I2S1, s_saiHandle[1][1]);
 }
 #endif

--- a/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.h	Fri Sep 16 16:24:25 2016 +0100
@@ -38,7 +38,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -46,7 +45,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */
+#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */
 /*@}*/
 
 /*! @brief SAI return status*/
@@ -168,7 +167,7 @@
 } sai_fifo_packing_t;
 #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */
 
-/*! @brief SAI user configure structure */
+/*! @brief SAI user configuration structure */
 typedef struct _sai_config
 {
     sai_protocol_t protocol;  /*!< Audio bus protocol in SAI */
@@ -276,7 +275,7 @@
  * because the clock is not enabled.
  *
  * @param base SAI base pointer
- * @param config SAI configure structure.
+ * @param config SAI configuration structure.
 */
 void SAI_TxInit(I2S_Type *base, const sai_config_t *config);
 
@@ -292,7 +291,7 @@
  * because the clock is not enabled.
  *
  * @param base SAI base pointer
- * @param config SAI configure structure.
+ * @param config SAI configuration structure.
  */
 void SAI_RxInit(I2S_Type *base, const sai_config_t *config);
 

--- a/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.c	Fri Sep 16 16:24:25 2016 +0100
@@ -40,6 +40,12 @@
     kSAI_Error        /*!< Transfer error occured. */
 };
 
+/*! @brief Typedef for sai tx interrupt handler. */
+typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle);
+
+/*! @brief Typedef for sai rx interrupt handler. */
+typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle);
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -98,6 +104,10 @@
 static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS;
 /* Clock name array */
 static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS;
+/*! @brief Pointer to tx IRQ handler for each instance. */
+static sai_tx_isr_t s_saiTxIsr;
+/*! @brief Pointer to tx IRQ handler for each instance. */
+static sai_rx_isr_t s_saiRxIsr;
 
 /*******************************************************************************
  * Code
@@ -231,12 +241,13 @@
     CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]);
 
 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
-    /* Configure Master clock output enable */
-    base->MCR = I2S_MCR_MOE(config->mclkOutputEnable);
-
     /* Master clock source setting */
     val = (base->MCR & ~I2S_MCR_MICS_MASK);
     base->MCR = (val | I2S_MCR_MICS(config->mclkSource));
+
+    /* Configure Master clock output enable */
+    val = (base->MCR & ~I2S_MCR_MOE_MASK);
+    base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable));
 #endif /* FSL_FEATURE_SAI_HAS_MCR */
 
     /* Configure audio protocol */
@@ -332,12 +343,13 @@
     CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]);
 
 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
-    /* Configure Master clock output enable */
-    base->MCR = I2S_MCR_MOE(config->mclkOutputEnable);
-
     /* Master clock source setting */
     val = (base->MCR & ~I2S_MCR_MICS_MASK);
     base->MCR = (val | I2S_MCR_MICS(config->mclkSource));
+
+    /* Configure Master clock output enable */
+    val = (base->MCR & ~I2S_MCR_MOE_MASK);
+    base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable));
 #endif /* FSL_FEATURE_SAI_HAS_MCR */
 
     /* Configure audio protocol */
@@ -663,6 +675,9 @@
     handle->callback = callback;
     handle->userData = userData;
 
+    /* Set the isr pointer */
+    s_saiTxIsr = SAI_TransferTxHandleIRQ;
+
     /* Enable Tx irq */
     EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]);
 }
@@ -676,6 +691,9 @@
     handle->callback = callback;
     handle->userData = userData;
 
+    /* Set the isr pointer */
+    s_saiRxIsr = SAI_TransferRxHandleIRQ;
+
     /* Enable Rx irq */
     EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]);
 }
@@ -1011,24 +1029,24 @@
 {
     if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)))
     {
-        SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]);
+        s_saiRxIsr(I2S0, s_saiHandle[0][1]);
     }
     if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)))
     {
-        SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]);
+        s_saiTxIsr(I2S0, s_saiHandle[0][0]);
     }
 }
 #else
 void I2S0_Tx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[0][0]);
-    SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]);
+    s_saiTxIsr(I2S0, s_saiHandle[0][0]);
 }
 
 void I2S0_Rx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[0][1]);
-    SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]);
+    s_saiRxIsr(I2S0, s_saiHandle[0][1]);
 }
 #endif /* FSL_FEATURE_SAI_INT_SOURCE_NUM */
 #endif /* I2S0*/
@@ -1037,12 +1055,12 @@
 void I2S1_Tx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[1][0]);
-    SAI_TransferTxHandleIRQ(I2S1, s_saiHandle[1][0]);
+    s_saiTxIsr(I2S1, s_saiHandle[1][0]);
 }
 
 void I2S1_Rx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[1][1]);
-    SAI_TransferRxHandleIRQ(I2S1, s_saiHandle[1][1]);
+    s_saiRxIsr(I2S1, s_saiHandle[1][1]);
 }
 #endif

--- a/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.h	Fri Sep 16 16:24:25 2016 +0100
@@ -38,7 +38,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -46,7 +45,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */
+#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */
 /*@}*/
 
 /*! @brief SAI return status*/
@@ -168,7 +167,7 @@
 } sai_fifo_packing_t;
 #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */
 
-/*! @brief SAI user configure structure */
+/*! @brief SAI user configuration structure */
 typedef struct _sai_config
 {
     sai_protocol_t protocol;  /*!< Audio bus protocol in SAI */
@@ -276,7 +275,7 @@
  * because the clock is not enabled.
  *
  * @param base SAI base pointer
- * @param config SAI configure structure.
+ * @param config SAI configuration structure.
 */
 void SAI_TxInit(I2S_Type *base, const sai_config_t *config);
 
@@ -292,7 +291,7 @@
  * because the clock is not enabled.
  *
  * @param base SAI base pointer
- * @param config SAI configure structure.
+ * @param config SAI configuration structure.
  */
 void SAI_RxInit(I2S_Type *base, const sai_config_t *config);
 

--- a/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/TARGET_HEXIWEAR/PeripheralPins.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/TARGET_HEXIWEAR/PeripheralPins.c	Fri Sep 16 16:24:25 2016 +0100
@@ -99,6 +99,7 @@
 
 /************SPI***************/
 const PinMap PinMap_SPI_SCLK[] = {
+    {PTE2 , SPI_1, 2},
     {PTB21, SPI_2, 2},
     {PTC5 , SPI_0, 2},
     {PTD5 , SPI_1, 7},
@@ -106,6 +107,8 @@
 };
 
 const PinMap PinMap_SPI_MOSI[] = {
+    {PTE1 , SPI_1, 2},
+    {PTE3 , SPI_1, 7},
     {PTB22, SPI_2, 2},
     {PTC6 , SPI_0, 2},
     {PTD6 , SPI_1, 7},
@@ -113,6 +116,8 @@
 };
 
 const PinMap PinMap_SPI_MISO[] = {
+    {PTE1 , SPI_1, 7},
+    {PTE3 , SPI_1, 2},
     {PTB23, SPI_2, 2},
     {PTC7 , SPI_0, 2},
     {PTD7 , SPI_1, 7},
@@ -120,6 +125,7 @@
 };
 
 const PinMap PinMap_SPI_SSEL[] = {
+    {PTE4 , SPI_1, 2},
     {PTB20, SPI_2, 2},
     {PTC4 , SPI_0, 2},
     {PTD4 , SPI_1, 7},

--- a/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.c	Fri Sep 16 16:24:25 2016 +0100
@@ -73,6 +73,9 @@
     kFLEXCAN_TxMbNotUsed = 0xF,      /*!< Not used.*/
 };
 
+/* Typedef for interrupt handler. */
+typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle);
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -86,23 +89,24 @@
 uint32_t FLEXCAN_GetInstance(CAN_Type *base);
 
 /*!
- * @brief Enter FlexCAN Fraze Mode.
+ * @brief Enter FlexCAN Freeze Mode.
  *
- * This function makes the FlexCAN work under Fraze Mode.
+ * This function makes the FlexCAN work under Freeze Mode.
  *
  * @param base FlexCAN peripheral base address.
  */
-static void FLEXCAN_EnterFrazeMode(CAN_Type *base);
+static void FLEXCAN_EnterFreezeMode(CAN_Type *base);
 
 /*!
- * @brief Exit FlexCAN Fraze Mode.
+ * @brief Exit FlexCAN Freeze Mode.
  *
- * This function makes the FlexCAN leave Fraze Mode.
+ * This function makes the FlexCAN leave Freeze Mode.
  *
  * @param base FlexCAN peripheral base address.
  */
-static void FLEXCAN_ExitFrazeMode(CAN_Type *base);
+static void FLEXCAN_ExitFreezeMode(CAN_Type *base);
 
+#if !defined(NDEBUG)
 /*!
  * @brief Check if Message Buffer is occupied by Rx FIFO.
  *
@@ -112,6 +116,19 @@
  * @param mbIdx The FlexCAN Message Buffer index.
  */
 static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx);
+#endif
+
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+/*!
+ * @brief Get the first valid Message buffer ID of give FlexCAN instance.
+ *
+ * This function is a helper function for Errata 5641 workaround.
+ *
+ * @param base FlexCAN peripheral base address.
+ * @return The first valid Message Buffer Number.
+ */
+static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base);
+#endif
 
 /*!
  * @brief Check if Message Buffer interrupt is enabled.
@@ -165,6 +182,9 @@
 /* Array of FlexCAN clock name. */
 static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS;
 
+/* FlexCAN ISR for transactional APIs. */
+static flexcan_isr_t s_flexcanIsr;
+
 /*******************************************************************************
  * Code
  ******************************************************************************/
@@ -187,10 +207,10 @@
     return instance;
 }
 
-static void FLEXCAN_EnterFrazeMode(CAN_Type *base)
+static void FLEXCAN_EnterFreezeMode(CAN_Type *base)
 {
     /* Set Freeze, Halt bits. */
-    base->MCR |= CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK;
+    base->MCR |= CAN_MCR_HALT_MASK;
 
     /* Wait until the FlexCAN Module enter freeze mode. */
     while (!(base->MCR & CAN_MCR_FRZACK_MASK))
@@ -198,10 +218,10 @@
     }
 }
 
-static void FLEXCAN_ExitFrazeMode(CAN_Type *base)
+static void FLEXCAN_ExitFreezeMode(CAN_Type *base)
 {
     /* Clear Freeze, Halt bits. */
-    base->MCR &= ~(CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK);
+    base->MCR &= ~CAN_MCR_HALT_MASK;
 
     /* Wait until the FlexCAN Module exit freeze mode. */
     while (base->MCR & CAN_MCR_FRZACK_MASK)
@@ -209,6 +229,7 @@
     }
 }
 
+#if !defined(NDEBUG)
 static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx)
 {
     uint8_t lastOccupiedMb;
@@ -221,7 +242,11 @@
         /* Calculate the number of last Message Buffer occupied by Rx FIFO. */
         lastOccupiedMb = ((lastOccupiedMb + 1) * 2) + 5;
 
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+        if (mbIdx <= (lastOccupiedMb + 1))
+#else
         if (mbIdx <= lastOccupiedMb)
+#endif
         {
             return true;
         }
@@ -232,9 +257,40 @@
     }
     else
     {
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+        if (0 == mbIdx)
+        {
+            return true;
+        }
+        else
+        {
+            return false;
+        }
+#else
         return false;
+#endif
     }
 }
+#endif
+
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base)
+{
+    uint32_t firstValidMbNum;
+
+    if (base->MCR & CAN_MCR_RFEN_MASK)
+    {
+        firstValidMbNum = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT);
+        firstValidMbNum = ((firstValidMbNum + 1) * 2) + 6;
+    }
+    else
+    {
+        firstValidMbNum = 0;
+    }
+
+    return firstValidMbNum;
+}
+#endif
 
 static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx)
 {
@@ -296,7 +352,7 @@
     base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK |
                  CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1);
 #else
-        base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1);
+    base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1);
 #endif
 
     /* Reset CTRL1 and CTRL2 rigister. */
@@ -387,7 +443,7 @@
     /* Reset to known status. */
     FLEXCAN_Reset(base);
 
-    /* Save current MCR value. */
+    /* Save current MCR value and enable to enter Freeze mode(enabled by default). */
     mcrTemp = base->MCR;
 
     /* Set the maximum number of Message Buffers */
@@ -448,8 +504,8 @@
     /* Assertion. */
     assert(config);
 
-    /* Enter Fraze Mode. */
-    FLEXCAN_EnterFrazeMode(base);
+    /* Enter Freeze Mode. */
+    FLEXCAN_EnterFreezeMode(base);
 
     /* Cleaning previous Timing Setting. */
     base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK |
@@ -460,59 +516,55 @@
         (CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) |
          CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | CAN_CTRL1_PROPSEG(config->propSeg));
 
-    /* Exit Fraze Mode. */
-    FLEXCAN_ExitFrazeMode(base);
+    /* Exit Freeze Mode. */
+    FLEXCAN_ExitFreezeMode(base);
 }
 
-void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask)
+void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask)
 {
-    /* Enter Fraze Mode. */
-    FLEXCAN_EnterFrazeMode(base);
+    /* Enter Freeze Mode. */
+    FLEXCAN_EnterFreezeMode(base);
 
     /* Setting Rx Message Buffer Global Mask value. */
     base->RXMGMASK = mask;
     base->RX14MASK = mask;
     base->RX15MASK = mask;
 
-    /* Exit Fraze Mode. */
-    FLEXCAN_ExitFrazeMode(base);
+    /* Exit Freeze Mode. */
+    FLEXCAN_ExitFreezeMode(base);
 }
 
-void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask)
+void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask)
 {
-    /* Enter Fraze Mode. */
-    FLEXCAN_EnterFrazeMode(base);
+    /* Enter Freeze Mode. */
+    FLEXCAN_EnterFreezeMode(base);
 
     /* Setting Rx FIFO Global Mask value. */
     base->RXFGMASK = mask;
 
-    /* Exit Fraze Mode. */
-    FLEXCAN_ExitFrazeMode(base);
+    /* Exit Freeze Mode. */
+    FLEXCAN_ExitFreezeMode(base);
 }
 
-void FlEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask)
+void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask)
 {
     assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
 
-    /* Enter Fraze Mode. */
-    FLEXCAN_EnterFrazeMode(base);
+    /* Enter Freeze Mode. */
+    FLEXCAN_EnterFreezeMode(base);
 
     /* Setting Rx Individual Mask value. */
     base->RXIMR[maskIdx] = mask;
 
-    /* Exit Fraze Mode. */
-    FLEXCAN_ExitFrazeMode(base);
+    /* Exit Freeze Mode. */
+    FLEXCAN_ExitFreezeMode(base);
 }
 
 void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)
 {
     /* Assertion. */
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-
-    if (FLEXCAN_IsMbOccupied(base, mbIdx))
-    {
-        assert(false);
-    }
+    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
 
     /* Inactivate Message Buffer. */
     if (enable)
@@ -535,14 +587,10 @@
     /* Assertion. */
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
     assert(((config) || (false == enable)));
+    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
 
     uint32_t cs_temp = 0;
 
-    if (FLEXCAN_IsMbOccupied(base, mbIdx))
-    {
-        assert(false);
-    }
-
     /* Inactivate Message Buffer. */
     base->MB[mbIdx].CS = 0;
 
@@ -574,7 +622,7 @@
     }
 }
 
-void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable)
+void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable)
 {
     /* Assertion. */
     assert((config) || (false == enable));
@@ -582,8 +630,8 @@
     volatile uint32_t *idFilterRegion = (volatile uint32_t *)(&base->MB[6].CS);
     uint8_t setup_mb, i, rffn = 0;
 
-    /* Enter Fraze Mode. */
-    FLEXCAN_EnterFrazeMode(base);
+    /* Enter Freeze Mode. */
+    FLEXCAN_EnterFreezeMode(base);
 
     if (enable)
     {
@@ -675,8 +723,8 @@
         FLEXCAN_SetRxMbConfig(base, 5, NULL, false);
     }
 
-    /* Exit Fraze Mode. */
-    FLEXCAN_ExitFrazeMode(base);
+    /* Exit Freeze Mode. */
+    FLEXCAN_ExitFreezeMode(base);
 }
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA)
@@ -684,25 +732,25 @@
 {
     if (enable)
     {
-        /* Enter Fraze Mode. */
-        FLEXCAN_EnterFrazeMode(base);
+        /* Enter Freeze Mode. */
+        FLEXCAN_EnterFreezeMode(base);
 
         /* Enable FlexCAN DMA. */
         base->MCR |= CAN_MCR_DMA_MASK;
 
-        /* Exit Fraze Mode. */
-        FLEXCAN_ExitFrazeMode(base);
+        /* Exit Freeze Mode. */
+        FLEXCAN_ExitFreezeMode(base);
     }
     else
     {
-        /* Enter Fraze Mode. */
-        FLEXCAN_EnterFrazeMode(base);
+        /* Enter Freeze Mode. */
+        FLEXCAN_EnterFreezeMode(base);
 
         /* Disable FlexCAN DMA. */
         base->MCR &= ~CAN_MCR_DMA_MASK;
 
-        /* Exit Fraze Mode. */
-        FLEXCAN_ExitFrazeMode(base);
+        /* Exit Freeze Mode. */
+        FLEXCAN_ExitFreezeMode(base);
     }
 }
 #endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */
@@ -713,14 +761,10 @@
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
     assert(txFrame);
     assert(txFrame->length <= 8);
+    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
 
     uint32_t cs_temp = 0;
 
-    if (FLEXCAN_IsMbOccupied(base, mbIdx))
-    {
-        assert(false);
-    }
-
     /* Check if Message Buffer is available. */
     if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK))
     {
@@ -751,6 +795,11 @@
         /* Activate Tx Message Buffer. */
         base->MB[mbIdx].CS = cs_temp;
 
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+        base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
+        base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
+#endif
+
         return kStatus_Success;
     }
     else
@@ -765,15 +814,11 @@
     /* Assertion. */
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
     assert(rxFrame);
+    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
 
     uint32_t cs_temp;
     uint8_t rx_code;
 
-    if (FLEXCAN_IsMbOccupied(base, mbIdx))
-    {
-        assert(false);
-    }
-
     /* Read CS field of Rx Message Buffer to lock Message Buffer. */
     cs_temp = base->MB[mbIdx].CS;
     /* Get Rx Message Buffer Code field. */
@@ -819,7 +864,7 @@
     }
 }
 
-status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame)
+status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame)
 {
     /* Assertion. */
     assert(rxFrame);
@@ -863,7 +908,7 @@
     }
 }
 
-status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame)
+status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame)
 {
     /* Write Tx Message Buffer to initiate a data sending. */
     if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, txFrame))
@@ -884,7 +929,7 @@
     }
 }
 
-status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame)
+status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame)
 {
     /* Wait until Rx Message Buffer non-empty. */
     while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx))
@@ -898,7 +943,7 @@
     return FLEXCAN_ReadRxMb(base, mbIdx, rxFrame);
 }
 
-status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame)
+status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame)
 {
     status_t rxFifoStatus;
 
@@ -908,7 +953,7 @@
     }
 
     /*  */
-    rxFifoStatus = FlEXCAN_ReadRxFifo(base, rxFrame);
+    rxFifoStatus = FLEXCAN_ReadRxFifo(base, rxFrame);
 
     /* Clean Rx Fifo available flag. */
     FLEXCAN_ClearMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag);
@@ -938,6 +983,8 @@
     handle->callback = callback;
     handle->userData = userData;
 
+    s_flexcanIsr = FLEXCAN_TransferHandleIRQ;
+
     /* We Enable Error & Status interrupt here, because this interrupt just
      * report current status of FlexCAN module through Callback function.
      * It is insignificance without a available callback function.
@@ -970,11 +1017,7 @@
     assert(handle);
     assert(xfer);
     assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-
-    if (FLEXCAN_IsMbOccupied(base, xfer->mbIdx))
-    {
-        assert(false);
-    }
+    assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx));
 
     /* Check if Message Buffer is idle. */
     if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx])
@@ -1017,11 +1060,7 @@
     assert(handle);
     assert(xfer);
     assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-
-    if (FLEXCAN_IsMbOccupied(base, xfer->mbIdx))
-    {
-        assert(false);
-    }
+    assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx));
 
     /* Check if Message Buffer is idle. */
     if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx])
@@ -1073,11 +1112,7 @@
     /* Assertion. */
     assert(handle);
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-
-    if (FLEXCAN_IsMbOccupied(base, mbIdx))
-    {
-        assert(false);
-    }
+    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
 
     /* Disable Message Buffer Interrupt. */
     FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx);
@@ -1096,11 +1131,7 @@
     /* Assertion. */
     assert(handle);
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-
-    if (FLEXCAN_IsMbOccupied(base, mbIdx))
-    {
-        assert(false);
-    }
+    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
 
     /* Disable Message Buffer Interrupt. */
     FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx);
@@ -1185,7 +1216,7 @@
                         break;
 
                     case kFLEXCAN_RxFifoFrameAvlFlag:
-                        status = FlEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf);
+                        status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf);
                         if (kStatus_Success == status)
                         {
                             status = kStatus_FLEXCAN_RxFifoIdle;
@@ -1273,7 +1304,7 @@
 {
     assert(s_flexcanHandle[0]);
 
-    FLEXCAN_TransferHandleIRQ(CAN0, s_flexcanHandle[0]);
+    s_flexcanIsr(CAN0, s_flexcanHandle[0]);
 }
 #endif
 
@@ -1282,7 +1313,7 @@
 {
     assert(s_flexcanHandle[1]);
 
-    FLEXCAN_TransferHandleIRQ(CAN1, s_flexcanHandle[1]);
+    s_flexcanIsr(CAN1, s_flexcanHandle[1]);
 }
 #endif
 
@@ -1291,7 +1322,7 @@
 {
     assert(s_flexcanHandle[2]);
 
-    FLEXCAN_TransferHandleIRQ(CAN2, s_flexcanHandle[2]);
+    s_flexcanIsr(CAN2, s_flexcanHandle[2]);
 }
 #endif
 
@@ -1300,7 +1331,7 @@
 {
     assert(s_flexcanHandle[3]);
 
-    FLEXCAN_TransferHandleIRQ(CAN3, s_flexcanHandle[3]);
+    s_flexcanIsr(CAN3, s_flexcanHandle[3]);
 }
 #endif
 
@@ -1309,6 +1340,6 @@
 {
     assert(s_flexcanHandle[4]);
 
-    FLEXCAN_TransferHandleIRQ(CAN4, s_flexcanHandle[4]);
+    s_flexcanIsr(CAN4, s_flexcanHandle[4]);
 }
 #endif

--- a/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h	Fri Sep 16 16:24:25 2016 +0100
@@ -37,7 +37,6 @@
  * @{
  */
 
-/*! @file*/
 
 /******************************************************************************
  * Definitions
@@ -87,10 +86,8 @@
     (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
      (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */
 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide)                        \
-    (                                                                             \
-        ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
-        ((FLEXCAN_ID_EXT(id) & 0x1FFF8000)                                        \
-         << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */
+    (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
+     ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */
 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide)                      \
     (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \
      ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >>                                     \
@@ -296,13 +293,13 @@
         uint32_t length : 4;     /*!< CAN frame payload length in bytes(Range: 0~8). */
         uint32_t type : 1;       /*!< CAN Frame Type(DATA or REMOTE). */
         uint32_t format : 1;     /*!< CAN Frame Identifier(STD or EXT format). */
-        uint32_t reserve1 : 1;   /*!< Reserved for placeholder. */
+        uint32_t : 1;            /*!< Reserved. */
         uint32_t idhit : 9;      /*!< CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode). */
     };
     struct
     {
         uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */
-        uint32_t reserve2 : 3; /*!< Reserved for place holder. */
+        uint32_t : 3;     /*!< Reserved. */
     };
     union
     {
@@ -366,7 +363,7 @@
     flexcan_frame_type_t type;     /*!< CAN Frame Type(Data or Remote). */
 } flexcan_rx_mb_config_t;
 
-/*! @brief FlexCAN Rx FIFO configure structure. */
+/*! @brief FlexCAN Rx FIFO configuration structure. */
 typedef struct _flexcan_rx_fifo_config
 {
     uint32_t *idFilterTable;                    /*!< Pointer to FlexCAN Rx FIFO identifier filter table. */
@@ -437,7 +434,7 @@
  * to call the FLEXCAN_Init function by passing in these parameters:
  *  @code
  *   flexcan_config_t flexcanConfig;
- *   flexcanConfig.clkSrc            = KFLEXCAN_ClkSrcOsc;
+ *   flexcanConfig.clkSrc            = kFLEXCAN_ClkSrcOsc;
  *   flexcanConfig.baudRate          = 125000U;
  *   flexcanConfig.maxMbNum          = 16;
  *   flexcanConfig.enableLoopBack    = false;
@@ -466,7 +463,7 @@
 /*!
  * @brief Get the default configuration structure.
  *
- * This function initializes the FlexCAN configure structure to default value. The default
+ * This function initializes the FlexCAN configuration structure to default value. The default
  * value are:
  *   flexcanConfig->clkSrc            = KFLEXCAN_ClkSrcOsc;
  *   flexcanConfig->baudRate          = 125000U;
@@ -512,7 +509,7 @@
  * @param base FlexCAN peripheral base address.
  * @param mask Rx Message Buffer Global Mask value.
  */
-void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask);
+void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask);
 
 /*!
  * @brief Sets the FlexCAN receive FIFO global mask.
@@ -522,7 +519,7 @@
  * @param base FlexCAN peripheral base address.
  * @param mask Rx Fifo Global Mask value.
  */
-void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask);
+void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask);
 
 /*!
  * @brief Sets the FlexCAN receive individual mask.
@@ -538,7 +535,7 @@
  * @param maskIdx The Index of individual Mask.
  * @param mask Rx Individual Mask value.
  */
-void FlEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask);
+void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask);
 
 /*!
  * @brief Configures a FlexCAN transmit message buffer.
@@ -580,7 +577,7 @@
  *               - true: Enable Rx FIFO.
  *               - false: Disable Rx FIFO.
  */
-void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable);
+void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable);
 
 /* @} */
 
@@ -629,7 +626,7 @@
  * @param txErrBuf Buffer to store Tx Error Counter value.
  * @param rxErrBuf Buffer to store Rx Error Counter value.
  */
-static inline void FlEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)
+static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)
 {
     if (txErrBuf)
     {
@@ -890,7 +887,7 @@
  * @retval kStatus_Success - Read Message from Rx FIFO successfully.
  * @retval kStatus_Fail    - Rx FIFO is not enabled.
  */
-status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame);
+status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame);
 
 /* @} */
 
@@ -910,7 +907,7 @@
  * @retval kStatus_Success - Write Tx Message Buffer Successfully.
  * @retval kStatus_Fail    - Tx Message Buffer is currently in use.
  */
-status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame);
+status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame);
 
 /*!
  * @brief Performs a polling receive transaction on the CAN bus.
@@ -924,7 +921,7 @@
  * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully.
  * @retval kStatus_Fail               - Rx Message Buffer is empty.
  */
-status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame);
+status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame);
 
 /*!
  * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus.
@@ -936,7 +933,7 @@
  * @retval kStatus_Success - Read Message from Rx FIFO successfully.
  * @retval kStatus_Fail    - Rx FIFO is not enabled.
  */
-status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame);
+status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame);
 
 /*!
  * @brief Initializes the FlexCAN handle.

--- a/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.c	Fri Sep 16 16:24:25 2016 +0100
@@ -40,6 +40,12 @@
     kSAI_Error        /*!< Transfer error occured. */
 };
 
+/*! @brief Typedef for sai tx interrupt handler. */
+typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle);
+
+/*! @brief Typedef for sai rx interrupt handler. */
+typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle);
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -98,6 +104,10 @@
 static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS;
 /* Clock name array */
 static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS;
+/*! @brief Pointer to tx IRQ handler for each instance. */
+static sai_tx_isr_t s_saiTxIsr;
+/*! @brief Pointer to tx IRQ handler for each instance. */
+static sai_rx_isr_t s_saiRxIsr;
 
 /*******************************************************************************
  * Code
@@ -231,12 +241,13 @@
     CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]);
 
 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
-    /* Configure Master clock output enable */
-    base->MCR = I2S_MCR_MOE(config->mclkOutputEnable);
-
     /* Master clock source setting */
     val = (base->MCR & ~I2S_MCR_MICS_MASK);
     base->MCR = (val | I2S_MCR_MICS(config->mclkSource));
+
+    /* Configure Master clock output enable */
+    val = (base->MCR & ~I2S_MCR_MOE_MASK);
+    base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable));
 #endif /* FSL_FEATURE_SAI_HAS_MCR */
 
     /* Configure audio protocol */
@@ -332,12 +343,13 @@
     CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]);
 
 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
-    /* Configure Master clock output enable */
-    base->MCR = I2S_MCR_MOE(config->mclkOutputEnable);
-
     /* Master clock source setting */
     val = (base->MCR & ~I2S_MCR_MICS_MASK);
     base->MCR = (val | I2S_MCR_MICS(config->mclkSource));
+
+    /* Configure Master clock output enable */
+    val = (base->MCR & ~I2S_MCR_MOE_MASK);
+    base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable));
 #endif /* FSL_FEATURE_SAI_HAS_MCR */
 
     /* Configure audio protocol */
@@ -663,6 +675,9 @@
     handle->callback = callback;
     handle->userData = userData;
 
+    /* Set the isr pointer */
+    s_saiTxIsr = SAI_TransferTxHandleIRQ;
+
     /* Enable Tx irq */
     EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]);
 }
@@ -676,6 +691,9 @@
     handle->callback = callback;
     handle->userData = userData;
 
+    /* Set the isr pointer */
+    s_saiRxIsr = SAI_TransferRxHandleIRQ;
+
     /* Enable Rx irq */
     EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]);
 }
@@ -1011,24 +1029,24 @@
 {
     if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)))
     {
-        SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]);
+        s_saiRxIsr(I2S0, s_saiHandle[0][1]);
     }
     if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)))
     {
-        SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]);
+        s_saiTxIsr(I2S0, s_saiHandle[0][0]);
     }
 }
 #else
 void I2S0_Tx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[0][0]);
-    SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]);
+    s_saiTxIsr(I2S0, s_saiHandle[0][0]);
 }
 
 void I2S0_Rx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[0][1]);
-    SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]);
+    s_saiRxIsr(I2S0, s_saiHandle[0][1]);
 }
 #endif /* FSL_FEATURE_SAI_INT_SOURCE_NUM */
 #endif /* I2S0*/
@@ -1037,12 +1055,12 @@
 void I2S1_Tx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[1][0]);
-    SAI_TransferTxHandleIRQ(I2S1, s_saiHandle[1][0]);
+    s_saiTxIsr(I2S1, s_saiHandle[1][0]);
 }
 
 void I2S1_Rx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[1][1]);
-    SAI_TransferRxHandleIRQ(I2S1, s_saiHandle[1][1]);
+    s_saiRxIsr(I2S1, s_saiHandle[1][1]);
 }
 #endif

--- a/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.h	Fri Sep 16 16:24:25 2016 +0100
@@ -38,7 +38,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -46,7 +45,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */
+#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */
 /*@}*/
 
 /*! @brief SAI return status*/
@@ -168,7 +167,7 @@
 } sai_fifo_packing_t;
 #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */
 
-/*! @brief SAI user configure structure */
+/*! @brief SAI user configuration structure */
 typedef struct _sai_config
 {
     sai_protocol_t protocol;  /*!< Audio bus protocol in SAI */
@@ -276,7 +275,7 @@
  * because the clock is not enabled.
  *
  * @param base SAI base pointer
- * @param config SAI configure structure.
+ * @param config SAI configuration structure.
 */
 void SAI_TxInit(I2S_Type *base, const sai_config_t *config);
 
@@ -292,7 +291,7 @@
  * because the clock is not enabled.
  *
  * @param base SAI base pointer
- * @param config SAI configure structure.
+ * @param config SAI configuration structure.
  */
 void SAI_RxInit(I2S_Type *base, const sai_config_t *config);
 

--- a/targets/hal/TARGET_Maxim/TARGET_MAX32600/serial_api.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_Maxim/TARGET_MAX32600/serial_api.c	Fri Sep 16 16:24:25 2016 +0100
@@ -250,27 +250,15 @@
     while(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY) {}
     c = obj->uart->tx_rx_fifo & 0xFF;
 
-    // Echo characters for stdio
-    if (obj->uart == (mxc_uart_regs_t*)STDIO_UART) {
-        obj->uart->tx_rx_fifo = c;
-    }
-    
     return c;
 }
 
 //******************************************************************************
 void serial_putc(serial_t *obj, int c)
 {
-    // Append a carriage return for stdio
-    if ((c == (int)'\n') && (obj->uart == (mxc_uart_regs_t*)STDIO_UART)) {
-        while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {}
-        obj->uart->tx_rx_fifo = '\r';
-    }
-
     // Wait for TXFIFO to not be full
     while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {}
     obj->uart->tx_rx_fifo = c;
-
 }
 
 //******************************************************************************

--- a/targets/hal/TARGET_Maxim/TARGET_MAX32610/serial_api.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_Maxim/TARGET_MAX32610/serial_api.c	Fri Sep 16 16:24:25 2016 +0100
@@ -250,27 +250,15 @@
     while(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY) {}
     c = obj->uart->tx_rx_fifo & 0xFF;
 
-    // Echo characters for stdio
-    if (obj->uart == (mxc_uart_regs_t*)STDIO_UART) {
-        obj->uart->tx_rx_fifo = c;
-    }
-    
     return c;
 }
 
 //******************************************************************************
 void serial_putc(serial_t *obj, int c)
 {
-    // Append a carriage return for stdio
-    if ((c == (int)'\n') && (obj->uart == (mxc_uart_regs_t*)STDIO_UART)) {
-        while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {}
-        obj->uart->tx_rx_fifo = '\r';
-    }
-
     // Wait for TXFIFO to not be full
     while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {}
     obj->uart->tx_rx_fifo = c;
-
 }
 
 //******************************************************************************

--- a/targets/hal/TARGET_Maxim/TARGET_MAX32620/serial_api.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_Maxim/TARGET_MAX32620/serial_api.c	Fri Sep 16 16:24:25 2016 +0100
@@ -303,29 +303,12 @@
 
     c = *obj->fifo->rx_8;
 
-    // Echo characters for stdio
-    if (obj->uart == (mxc_uart_regs_t*)STDIO_UART) {
-        *obj->fifo->tx_8 = (uint8_t)c;
-    }
-
     return c;
 }
 
 //******************************************************************************
 void serial_putc(serial_t *obj, int c)
 {
-    // Append a carriage return for stdio
-    if ((c == (int)'\n') && (obj->uart == (mxc_uart_regs_t*)STDIO_UART)) {
-        while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
-                >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
-                >= MXC_UART_FIFO_DEPTH );
-
-        // Must clear before every write to the buffer to know that the fifo
-        // is empty when the TX DONE bit is set
-        obj->uart->intfl = MXC_F_UART_INTFL_TX_DONE;
-        *obj->fifo->tx_8 = (uint8_t)'\r';
-    }
-
     // Wait for TXFIFO to not be full
     while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
                 >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_MTM_MTCONNECT04S/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,137 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 Nordic Semiconductor
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  3
+
+typedef enum {
+    p0  = 0,
+    p1  = 1,
+    p2  = 2,
+    p3  = 3,
+    p4  = 4,
+    p5  = 5,
+    p6  = 6,
+    p7  = 7,
+    p8  = 8,
+    p9  = 9,
+    p10 = 10,
+    p11 = 11,
+    p12 = 12,
+    p13 = 13,
+    p14 = 14,
+    p15 = 15,
+    p16 = 16,
+    p17 = 17,
+    p18 = 18,
+    p19 = 19,
+    p20 = 20,
+    p21 = 21,
+    p22 = 22,
+    p23 = 23,
+    p24 = 24,
+    p25 = 25,
+    p26 = 26,
+    p27 = 27,
+    p28 = 28,
+    p29 = 29,
+    p30 = 30,      
+    p31 = 31,
+
+    P0_0  = p0,
+    P0_1  = p1,
+    P0_2  = p2,
+    P0_3  = p3,
+    P0_4  = p4,
+    P0_5  = p5,
+    P0_6  = p6,
+    P0_7  = p7,
+
+    P0_8  = p8,
+    P0_9  = p9,
+    P0_10 = p10,
+    P0_11 = p11,
+    P0_12 = p12,
+    P0_13 = p13,
+    P0_14 = p14,
+    P0_15 = p15,
+
+    P0_16 = p16,
+    P0_17 = p17,
+    P0_18 = p18,
+    P0_19 = p19,
+    P0_20 = p20,
+    P0_21 = p21,
+    P0_22 = p22,
+    P0_23 = p23,
+
+    P0_24 = p24,
+    P0_25 = p25,
+    P0_26 = p26,
+    P0_27 = p27,
+    P0_28 = p28,
+    P0_29 = p29,
+    P0_30 = p30,  
+    P0_31 = p31,
+                  
+    LEDR    = p16,
+    LEDG    = p15,
+    LEDB    = p6,
+    LED1    = LEDR,
+    LED2    = LEDG,
+    LED3    = LEDB,
+    LED4    = LEDB,
+
+    RX_PIN_NUMBER  = p4,
+    TX_PIN_NUMBER  = p5,
+    CTS_PIN_NUMBER = p2,
+    RTS_PIN_NUMBER = p3,
+
+    // mBed interface Pins
+    USBTX = TX_PIN_NUMBER,
+    USBRX = RX_PIN_NUMBER,
+
+    I2C_SDA0 = p14,
+    I2C_SCL0 = p13,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullNone = 0,
+    PullDown = 1,
+    PullUp = 3,
+    PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_MTM_MTCONNECT04S/device.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,38 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#include "objects.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_DELTA_DFBM_NQ620/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,202 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  3
+
+typedef enum {
+    p0  = 0,
+    p1  = 1,
+    p2  = 2,
+    p3  = 3,
+    p4  = 4,
+    p5  = 5,
+    p6  = 6,
+    p7  = 7,
+    p8  = 8,
+    p9  = 9,
+    p10 = 10,
+    p11 = 11,
+    p12 = 12,
+    p13 = 13,
+    p14 = 14,
+    p15 = 15,
+    p16 = 16,
+    p17 = 17,
+    p18 = 18,
+    p19 = 19,
+    p20 = 20,
+    p21 = 21,
+    p22 = 22,
+    p23 = 23,
+    p24 = 24,
+    p25 = 25,
+    p26 = 26,
+    p27 = 27,
+    p28 = 28,
+    p29 = 29,
+    p30 = 30,
+    p31 = 31,
+
+    P0_0  = p0,
+    P0_1  = p1,
+    P0_2  = p2,
+    P0_3  = p3,
+    P0_4  = p4,
+    P0_5  = p5,
+    P0_6  = p6,
+    P0_7  = p7,
+
+    P0_8  = p8,
+    P0_9  = p9,
+    P0_10 = p10,
+    P0_11 = p11,
+    P0_12 = p12,
+    P0_13 = p13,
+    P0_14 = p14,
+    P0_15 = p15,
+
+    P0_16 = p16,
+    P0_17 = p17,
+    P0_18 = p18,
+    P0_19 = p19,
+    P0_20 = p20,
+    P0_21 = p21,
+    P0_22 = p22,
+    P0_23 = p23,
+
+    P0_24 = p24,
+    P0_25 = p25,
+    P0_26 = p26,
+    P0_27 = p27,
+    P0_28 = p28,
+    P0_29 = p29,
+    P0_30 = p30,
+
+    LED1    = p17,
+    LED2    = p18,
+    LED3    = p19,
+    LED4    = p20,
+
+    BUTTON1 = p13,
+    BUTTON2 = p14,
+    BUTTON3 = p15,
+    BUTTON4 = p16,
+
+    RX_PIN_NUMBER  = p11,
+    TX_PIN_NUMBER  = p12,
+    CTS_PIN_NUMBER = p13,
+    RTS_PIN_NUMBER = p14,
+
+    // mBed interface Pins
+    USBTX = TX_PIN_NUMBER,
+    USBRX = RX_PIN_NUMBER,
+
+    SPI_PSELMOSI0 = p23,
+    SPI_PSELMISO0 = p24,
+    SPI_PSELSS0   = p22,
+    SPI_PSELSCK0  = p25,
+
+    SPI_PSELMOSI1 = p12,
+    SPI_PSELMISO1 = p13,
+    SPI_PSELSS1   = p11,
+    SPI_PSELSCK1  = p14,
+
+    SPIS_PSELMOSI = p12,
+    SPIS_PSELMISO = p13,
+    SPIS_PSELSS   = p11,
+    SPIS_PSELSCK  = p14,
+
+    I2C_SDA0 = p26,
+    I2C_SCL0 = p27,
+
+    D0 = p11,
+    D1 = p12,
+    D2 = p13,
+    D3 = p14,
+    D4 = p15,
+    D5 = p16,
+    D6 = p17,
+    D7 = p18,
+
+    D8 = p19,
+    D9 = p20,
+    D10 = p22,
+    D11 = p23,
+    D12 = p24,
+    D13 = p25,
+
+    D14 = p26,
+    D15 = p27,
+
+    A0 = p3,
+    A1 = p4,
+    A2 = p28,
+    A3 = p29,
+    A4 = p30,
+    A5 = p31,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullNone = 0,
+    PullDown = 1,
+    PullUp = 3,
+    PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_DELTA_DFBM_NQ620/device.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,38 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#include "objects.h"
+
+#endif

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/Pad.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/Pad.c	Fri Sep 16 16:24:25 2016 +0100
@@ -8,9 +8,15 @@
 * $Rev: 2848 $
 * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/PeripheralNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/PeripheralNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 0.1 $
  * $Date: 2015-11-07 $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 0.1 $
  * $Date: 2015-11-06 $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/adc_sar.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/adc_sar.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Date: 2015-06-15 16:46:35 +0530 (Mon, 15 Jun 2015) $
  * @brief Definitions and API for the SAR ADC driver.
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/adc_sar_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/adc_sar_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 3422 $
  * $Date: 2015-06-09 11:01:43 +0530 (Tue, 09 Jun 2015) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/aes_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/aes_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 2110 $
  * $Date: 2013-07-16 20:13:03 +0530 (Tue, 16 Jul 2013) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/analogin_api.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/analogin_api.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev:
  * $Date:
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/architecture.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/architecture.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: $
 * $Date:  $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/assert_onsemi.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/assert_onsemi.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 3823 $
  * $Date: 2015-10-23 16:21:37 +0530 (Fri, 23 Oct 2015) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 2607 $
  * $Date: 2013-12-06 18:02:43 +0530 (Fri, 06 Dec 2013) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/clock.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/clock.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 3414 $
 * $Date: 2015-06-05 13:27:04 +0530 (Fri, 05 Jun 2015) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 2848 $
 * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/crossbar.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/crossbar.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 2033 $
 * $Date: 2013-06-28 17:12:31 +0200 (Fri, 28 Jun 2013) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/crossbar_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/crossbar_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 3318 $
 * $Date: 2015-03-27 16:29:34 +0530 (Fri, 27 Mar 2015) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/device.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 0.1 $
  * $Date: 2015-11-06 $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 3415 $
 * $Date: 2015-06-05 13:29:52 +0530 (Fri, 05 Jun 2015) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/error.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/error.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 2074 $
  * $Date: 2013-07-10 18:06:15 +0530 (Wed, 10 Jul 2013) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/exceptions.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/exceptions.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 2074 $
 * $Date: 2013-07-10 14:36:15 +0200 (Wed, 10 Jul 2013) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/fib.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/fib.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 2074 $
 * $Date: 2013-07-10 14:36:15 +0200 (Wed, 10 Jul 2013) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/flash_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/flash_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 2686 $
  * $Date: 2014-01-23 13:31:54 +0530 (Thu, 23 Jan 2014) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 3724 $
  * $Date: 2015-09-14 14:35:42 +0530 (Mon, 14 Sep 2015) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_api.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_api.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev:
  * $Date: 2015-11-04 $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_irq_api.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_irq_api.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev:
  * $Date: 2015-11-04 $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 2115 $
  * $Date: 2013-07-17 18:08:17 +0530 (Wed, 17 Jul 2013) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev:  $
  * $Date: 2016-04-20 $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 3525 $
  * $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c_ipc7208_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c_ipc7208_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 3324 $
  * $Date: 2015-03-27 17:00:28 +0530 (Fri, 27 Mar 2015) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 3390 $
 * $Date: 2015-05-13 17:21:05 +0530 (Wed, 13 May 2015) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/macros.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/macros.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 2076 $
  * $Date: 2013-07-10 18:26:10 +0530 (Wed, 10 Jul 2013) $
  *******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 3525 $
 * $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/mib.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/mib.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 2284 $
  * $Date: 2013-09-12 15:08:22 +0530 (Thu, 12 Sep 2013) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev:
 * $Date: $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
@@ -28,7 +34,7 @@
 *  Header files                                                                                  *
 *                                                                                                *
 *************************************************************************************************/
-#include "NCS36510Init.h"
+#include "ncs36510Init.h"
 
 void fPmuInit(void);
 /**

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev:
 * $Date: $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev:  $
  * $Date: 2016-04-12 $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_lp_ticker_api.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_lp_ticker_api.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev:  $
  * $Date: $
  ******************************************************************************
- * @copyright (c) 2015 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_spi.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_spi.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * @version $Rev:  $
  * @date $Date: 2016-02-05 $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev:  $
  * $Date: 2015-11-15 $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/objects.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/objects.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 0.1 $
  * $Date: 2015-11-06 $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pad.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pad.h	Fri Sep 16 16:24:25 2016 +0100
@@ -8,9 +8,15 @@
 * $Rev: 2848 $
 * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pad_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pad_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 3166 $
 * $Date: 2015-01-19 11:28:08 +0530 (Mon, 19 Jan 2015) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 3372 $
 * $Date: 2015-04-22 12:18:18 +0530 (Wed, 22 Apr 2015) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/port_api.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/port_api.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev:
  * $Date:
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pwm_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pwm_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 3378 $
  * $Date: 2015-04-28 13:38:36 +0530 (Tue, 28 Apr 2015) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pwmout_api.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pwmout_api.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev:
  * $Date:
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/random_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/random_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 3283 $
 * $Date: 2015-02-26 18:52:22 +0530 (Thu, 26 Feb 2015) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/reset_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/reset_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 2848 $
 * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 3445 $
 * $Date: 2015-06-22 13:51:24 +0530 (Mon, 22 Jun 2015) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 2848 $
 * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 2953 $
 * $Date: 2014-09-15 18:13:01 +0530 (Mon, 15 Sep 2014) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 3525 $
  * $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 3485 $
  * $Date: 2015-07-14 15:20:11 +0530 (Tue, 14 Jul 2015) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc_api.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc_api.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 0.1 $
 * $Date: 2016-01-20 12:09:00 +0530 (Wed, 20 Jan 2016) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 3008 $
  * $Date: 2014-10-16 18:42:48 +0530 (Thu, 16 Oct 2014) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/serial_api.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/serial_api.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 0.1 $
 * $Date: 2015-11-04 05:30:00 +0530 (Wed, 04 Nov 2015) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev:  0.1 $
  * $Date: 01-21-2016 $
  ******************************************************************************
- * @copyright (c) 2015 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev:  $
  * $Date: $
  ******************************************************************************
- * @copyright (c) 2015 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep_api.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep_api.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,16 @@
  * $Rev:  $
  * $Date: $
  ******************************************************************************
- * @copyright (c) 2015 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
+
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * @version $Rev:  $
  * @date $Date: 2016-02-05 $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev:  0.1 $
  * $Date: 02-05-2016 $
  ******************************************************************************
- * @copyright (c) 2015 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi_ipc7207_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi_ipc7207_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 2110 $
  * $Date: 2013-07-16 20:13:03 +0530 (Tue, 16 Jul 2013) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/swversion.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/swversion.c	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 2199 $
 * $Date: 2013-08-07 12:17:27 +0200 (Wed, 07 Aug 2013) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sys.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sys.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 2074 $
 * $Date: 2013-07-10 14:36:15 +0200 (Wed, 10 Jul 2013) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/test_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/test_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 2848 $
 * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ticker.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ticker.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev:
  * $Date:
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/timer.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/timer.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 3725 $
  * $Date: 2015-09-14 14:36:27 +0530 (Mon, 14 Sep 2015) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/timer_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/timer_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 3423 $
  * $Date: 2015-06-09 11:16:49 +0530 (Tue, 09 Jun 2015) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
 * $Rev: 3727 $
 * $Date: 2015-09-14 14:38:34 +0530 (Mon, 14 Sep 2015) $
 ******************************************************************************
-* @copyright (c) 2012 ON Semiconductor. All rights reserved.
-* ON Semiconductor is supplying this software for use with ON Semiconductor
-* processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/types.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/types.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 2074 $
  * $Date: 2013-07-10 18:06:15 +0530 (Wed, 10 Jul 2013) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 2074 $
  * $Date: 2013-07-10 18:06:15 +0530 (Wed, 10 Jul 2013) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 2607 $
  * $Date: 2013-12-06 18:02:43 +0530 (Fri, 06 Dec 2013) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 2615 $
  * $Date: 2013-12-13 13:17:21 +0530 (Fri, 13 Dec 2013) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h	Fri Sep 16 16:24:25 2016 +0100
@@ -7,9 +7,15 @@
  * $Rev: 3283 $
  * $Date: 2015-02-26 18:52:22 +0530 (Thu, 26 Feb 2015) $
  ******************************************************************************
- * @copyright (c) 2012 ON Semiconductor. All rights reserved.
- * ON Semiconductor is supplying this software for use with ON Semiconductor
- * processor based microcontrollers only.
+ * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
+ * All rights reserved.  This software and/or documentation is licensed by ON Semiconductor
+ * under limited terms and conditions.  The terms and conditions pertaining to the software
+ * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
+ * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
+ * if applicable the software license agreement.  Do not use this software and/or
+ * documentation unless you have carefully read and you agree to the limited terms and
+ * conditions.  By using this software and/or documentation, you agree to the limited
+ * terms and conditions.
  *
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

--- a/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-//#define DEVICE_ERROR_RED      0
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/device.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,40 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+//=======================================
+#define DEVICE_ID_LENGTH       24
+
+#include "objects.h"
+
+#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h	Fri Sep 16 16:24:25 2016 +0100
@@ -60,17 +60,6 @@
     uint8_t channel;
 };
 
-struct serial_s {
-    UARTName uart;
-    int index; // Used by irq
-    uint32_t baudrate;
-    uint32_t databits;
-    uint32_t stopbits;
-    uint32_t parity;
-    PinName pin_tx;
-    PinName pin_rx;
-};
-
 struct spi_s {
     SPIName spi;
     uint32_t bits;

--- a/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h	Fri Sep 16 16:24:25 2016 +0100
@@ -60,17 +60,6 @@
     uint8_t channel;
 };
 
-struct serial_s {
-    UARTName uart;
-    int index; // Used by irq
-    uint32_t baudrate;
-    uint32_t databits;
-    uint32_t stopbits;
-    uint32_t parity; 
-    PinName pin_tx;
-    PinName pin_rx;
-};
-
 struct spi_s {
     SPIName spi;
     uint32_t bits;

--- a/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h	Fri Sep 16 16:24:25 2016 +0100
@@ -60,17 +60,6 @@
     uint8_t channel;
 };
 
-struct serial_s {
-    UARTName uart;
-    int index; // Used by irq
-    uint32_t baudrate;
-    uint32_t databits;
-    uint32_t stopbits;
-    uint32_t parity;
-    PinName pin_tx;
-    PinName pin_rx;
-};
-
 struct spi_s {
     SPIName spi;
     uint32_t bits;

--- a/targets/hal/TARGET_STM/TARGET_STM32F1/common_objects.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F1/common_objects.h	Fri Sep 16 16:24:25 2016 +0100
@@ -49,6 +49,25 @@
     uint8_t inverted;
 };
 
+struct serial_s {
+    UARTName uart;
+    int index; // Used by irq
+    uint32_t baudrate;
+    uint32_t databits;
+    uint32_t stopbits;
+    uint32_t parity;
+    PinName pin_tx;
+    PinName pin_rx;
+#if DEVICE_SERIAL_ASYNCH
+    uint32_t events;
+#endif
+#if DEVICE_SERIAL_FC
+    uint32_t hw_flow_ctl;
+    PinName pin_rts;
+    PinName pin_cts;
+#endif
+};
+
 #include "gpio_object.h"
 
 #ifdef __cplusplus

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F1/device.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,40 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+//=======================================
+#define DEVICE_ID_LENGTH       24
+
+#include "objects.h"
+
+#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F1/serial_api.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F1/serial_api.c	Fri Sep 16 16:24:25 2016 +0100
@@ -40,76 +40,93 @@
 
 #define UART_NUM (3)
 
-static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0};
+static uint32_t serial_irq_ids[UART_NUM] = {0};
+static UART_HandleTypeDef uart_handlers[UART_NUM];
 
 static uart_irq_handler irq_handler;
 
-UART_HandleTypeDef UartHandle;
-
 int stdio_uart_inited = 0;
 serial_t stdio_uart;
 
+#if DEVICE_SERIAL_ASYNCH
+    #define SERIAL_S(obj) (&((obj)->serial))
+#else
+    #define SERIAL_S(obj) (obj)
+#endif
+
 static void init_uart(serial_t *obj)
 {
-
-    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+    huart->Instance = (USART_TypeDef *)(obj_s->uart);
 
-    UartHandle.Init.BaudRate   = obj->baudrate;
-    UartHandle.Init.WordLength = obj->databits;
-    UartHandle.Init.StopBits   = obj->stopbits;
-    UartHandle.Init.Parity     = obj->parity;
-    UartHandle.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
+    huart->Init.BaudRate     = obj_s->baudrate;
+    huart->Init.WordLength   = obj_s->databits;
+    huart->Init.StopBits     = obj_s->stopbits;
+    huart->Init.Parity       = obj_s->parity;
+#if DEVICE_SERIAL_FC
+    huart->Init.HwFlowCtl    = obj_s->hw_flow_ctl;
+#else
+    huart->Init.HwFlowCtl    = UART_HWCONTROL_NONE;
+#endif
+    huart->TxXferCount       = 0;
+    huart->TxXferSize        = 0;
+    huart->RxXferCount       = 0;
+    huart->RxXferSize        = 0;
 
-    if (obj->pin_rx == NC) {
-        UartHandle.Init.Mode = UART_MODE_TX;
-    } else if (obj->pin_tx == NC) {
-        UartHandle.Init.Mode = UART_MODE_RX;
+    if (obj_s->pin_rx == NC) {
+        huart->Init.Mode = UART_MODE_TX;
+    } else if (obj_s->pin_tx == NC) {
+        huart->Init.Mode = UART_MODE_RX;
     } else {
-        UartHandle.Init.Mode = UART_MODE_TX_RX;
+        huart->Init.Mode = UART_MODE_TX_RX;
     }
 
-    // Fix because HAL_RCC_GetHCLKFreq() don't update anymore SystemCoreClock
+    /* uAMR & ARM: Call to UART init is done between reset of pre-initialized variables */
+    /* and before HAL Init. SystemCoreClock init required here */
     SystemCoreClockUpdate();
 
-    if (HAL_UART_Init(&UartHandle) != HAL_OK) {
+    if (HAL_UART_Init(huart) != HAL_OK) {
         error("Cannot initialize UART\n");
     }
-
 }
 
 void serial_init(serial_t *obj, PinName tx, PinName rx)
 {
+    struct serial_s *obj_s = SERIAL_S(obj);
+    
     // Determine the UART to use (UART_1, UART_2, ...)
     UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
     UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
 
     // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
-    obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
-    MBED_ASSERT(obj->uart != (UARTName)NC);
+    obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+    MBED_ASSERT(obj_s->uart != (UARTName)NC);
 
-    // Enable UART clock
-    if (obj->uart == UART_1) {
-    	__USART1_FORCE_RESET();
-    	__USART1_RELEASE_RESET();
+    // Enable USART clock
+    if (obj_s->uart == UART_1) {
+        __HAL_RCC_USART1_FORCE_RESET();
+        __HAL_RCC_USART1_RELEASE_RESET();
         __HAL_RCC_USART1_CLK_ENABLE();
-        obj->index = 0;
+        obj_s->index = 0;
     }
-    if (obj->uart == UART_2) {
-    	__USART2_FORCE_RESET();
-    	__USART2_RELEASE_RESET();
+    if (obj_s->uart == UART_2) {
+        __HAL_RCC_USART2_FORCE_RESET();
+        __HAL_RCC_USART2_RELEASE_RESET();
         __HAL_RCC_USART2_CLK_ENABLE();
-        obj->index = 1;
+        obj_s->index = 1;
     }
-    if (obj->uart == UART_3) {
-    	__USART3_FORCE_RESET();
-    	__USART3_RELEASE_RESET();
+    if (obj_s->uart == UART_3) {
+        __HAL_RCC_USART3_FORCE_RESET();
+        __HAL_RCC_USART3_RELEASE_RESET();
         __HAL_RCC_USART3_CLK_ENABLE();
-        obj->index = 2;
+        obj_s->index = 2;
     }
 
     // Configure UART pins
     pinmap_pinout(tx, PinMap_UART_TX);
     pinmap_pinout(rx, PinMap_UART_RX);
+    
     if (tx != NC) {
         pin_mode(tx, PullUp);
     }
@@ -118,18 +135,22 @@
     }
 
     // Configure UART
-    obj->baudrate = 9600;
-    obj->databits = UART_WORDLENGTH_8B;
-    obj->stopbits = UART_STOPBITS_1;
-    obj->parity   = UART_PARITY_NONE;
+    obj_s->baudrate = 9600;
+    obj_s->databits = UART_WORDLENGTH_8B;
+    obj_s->stopbits = UART_STOPBITS_1;
+    obj_s->parity   = UART_PARITY_NONE;
+    
+#if DEVICE_SERIAL_FC
+    obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
+#endif
 
-    obj->pin_tx = tx;
-    obj->pin_rx = rx;
+    obj_s->pin_tx = tx;
+    obj_s->pin_rx = rx;
 
     init_uart(obj);
 
     // For stdio management
-    if (obj->uart == STDIO_UART) {
+    if (obj_s->uart == STDIO_UART) {
         stdio_uart_inited = 1;
         memcpy(&stdio_uart, obj, sizeof(serial_t));
     }
@@ -137,62 +158,68 @@
 
 void serial_free(serial_t *obj)
 {
+    struct serial_s *obj_s = SERIAL_S(obj);
+      
     // Reset UART and disable clock
-    if (obj->uart == UART_1) {
+    if (obj_s->uart == UART_1) {
         __USART1_FORCE_RESET();
         __USART1_RELEASE_RESET();
         __USART1_CLK_DISABLE();
     }
-    if (obj->uart == UART_2) {
+    if (obj_s->uart == UART_2) {
         __USART2_FORCE_RESET();
         __USART2_RELEASE_RESET();
         __USART2_CLK_DISABLE();
     }
-    if (obj->uart == UART_3) {
+    if (obj_s->uart == UART_3) {
         __USART3_FORCE_RESET();
         __USART3_RELEASE_RESET();
         __USART3_CLK_DISABLE();
     }
 
     // Configure GPIOs
-    pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
 
-    serial_irq_ids[obj->index] = 0;
+    serial_irq_ids[obj_s->index] = 0;
 }
 
 void serial_baud(serial_t *obj, int baudrate)
 {
-    obj->baudrate = baudrate;
+    struct serial_s *obj_s = SERIAL_S(obj);
+
+    obj_s->baudrate = baudrate;
     init_uart(obj);
 }
 
 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
 {
+    struct serial_s *obj_s = SERIAL_S(obj);
+
     if (data_bits == 9) {
-        obj->databits = UART_WORDLENGTH_9B;
+        obj_s->databits = UART_WORDLENGTH_9B;
     } else {
-        obj->databits = UART_WORDLENGTH_8B;
+        obj_s->databits = UART_WORDLENGTH_8B;
     }
 
     switch (parity) {
         case ParityOdd:
-        case ParityForced0:
-            obj->parity = UART_PARITY_ODD;
+            obj_s->parity = UART_PARITY_ODD;
             break;
         case ParityEven:
-        case ParityForced1:
-            obj->parity = UART_PARITY_EVEN;
+            obj_s->parity = UART_PARITY_EVEN;
             break;
         default: // ParityNone
-            obj->parity = UART_PARITY_NONE;
+        case ParityForced0: // unsupported!
+        case ParityForced1: // unsupported!
+            obj_s->parity = UART_PARITY_NONE;
             break;
     }
 
     if (stop_bits == 2) {
-        obj->stopbits = UART_STOPBITS_2;
+        obj_s->stopbits = UART_STOPBITS_2;
     } else {
-        obj->stopbits = UART_STOPBITS_1;
+        obj_s->stopbits = UART_STOPBITS_1;
     }
 
     init_uart(obj);
@@ -202,91 +229,104 @@
  * INTERRUPTS HANDLING
  ******************************************************************************/
 
-static void uart_irq(UARTName name, int id)
+static void uart_irq(int id)
 {
-    UartHandle.Instance = (USART_TypeDef *)name;
+    UART_HandleTypeDef * huart = &uart_handlers[id];
+    
     if (serial_irq_ids[id] != 0) {
-        if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) {
-            irq_handler(serial_irq_ids[id], TxIrq);
-            __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_TC);
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
+            if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
+                irq_handler(serial_irq_ids[id], TxIrq);
+                __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
+            }
         }
-        if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) {
-            irq_handler(serial_irq_ids[id], RxIrq);
-            __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_RXNE);
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) {
+            if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET) {
+                irq_handler(serial_irq_ids[id], RxIrq);
+                __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
+            }
+        }
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
+            if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET) {
+                volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag
+            }
         }
     }
 }
 
 static void uart1_irq(void)
 {
-    uart_irq(UART_1, 0);
+    uart_irq(0);
 }
 
 static void uart2_irq(void)
 {
-    uart_irq(UART_2, 1);
+    uart_irq(1);
 }
 
 static void uart3_irq(void)
 {
-    uart_irq(UART_3, 2);
+    uart_irq(2);
 }
 
 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
 {
+    struct serial_s *obj_s = SERIAL_S(obj);
+  
     irq_handler = handler;
-    serial_irq_ids[obj->index] = id;
+    serial_irq_ids[obj_s->index] = id;
 }
 
 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
 {
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
     IRQn_Type irq_n = (IRQn_Type)0;
     uint32_t vector = 0;
 
-    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
-
-    if (obj->uart == UART_1) {
+    if (obj_s->uart == UART_1) {
         irq_n = USART1_IRQn;
         vector = (uint32_t)&uart1_irq;
     }
 
-    if (obj->uart == UART_2) {
+    if (obj_s->uart == UART_2) {
         irq_n = USART2_IRQn;
         vector = (uint32_t)&uart2_irq;
     }
 
-    if (obj->uart == UART_3) {
+    if (obj_s->uart == UART_3) {
         irq_n = USART3_IRQn;
         vector = (uint32_t)&uart3_irq;
     }
 
     if (enable) {
-
         if (irq == RxIrq) {
-            __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE);
+            __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
         } else { // TxIrq
-            __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC);
+            __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
         }
-
         NVIC_SetVector(irq_n, vector);
         NVIC_EnableIRQ(irq_n);
 
     } else { // disable
-
         int all_disabled = 0;
-
         if (irq == RxIrq) {
-            __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE);
+            __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
             // Check if TxIrq is disabled too
-            if ((UartHandle.Instance->CR1 & USART_CR1_TCIE) == 0) all_disabled = 1;
+            if ((huart->Instance->CR1 & USART_CR1_TXEIE) == 0) {
+                all_disabled = 1;
+            }
         } else { // TxIrq
-            __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TC);
+            __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
             // Check if RxIrq is disabled too
-            if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1;
+            if ((huart->Instance->CR1 & USART_CR1_RXNEIE) == 0) {
+                all_disabled = 1;
+            }
         }
 
-        if (all_disabled) NVIC_DisableIRQ(irq_n);
-
+        if (all_disabled) {
+            NVIC_DisableIRQ(irq_n);
+        }
     }
 }
 
@@ -296,49 +336,55 @@
 
 int serial_getc(serial_t *obj)
 {
-    USART_TypeDef *uart = (USART_TypeDef *)(obj->uart);
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
     while (!serial_readable(obj));
-    if (obj->databits == UART_WORDLENGTH_8B) {
-        return (int)(uart->DR & (uint8_t)0xFF);
+    if (obj_s->databits == UART_WORDLENGTH_8B) {
+        return (int)(huart->Instance->DR & (uint8_t)0xFF);
     } else {
-        return (int)(uart->DR & (uint16_t)0x1FF);
+        return (int)(huart->Instance->DR & (uint16_t)0x1FF);
     }
 }
 
 void serial_putc(serial_t *obj, int c)
 {
-    USART_TypeDef *uart = (USART_TypeDef *)(obj->uart);
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
     while (!serial_writable(obj));
-    if (obj->databits == UART_WORDLENGTH_8B) {
-        uart->DR = (uint8_t)(c & (uint8_t)0xFF);
+    if (obj_s->databits == UART_WORDLENGTH_8B) {
+        huart->Instance->DR = (uint8_t)(c & (uint8_t)0xFF);
     } else {
-        uart->DR = (uint16_t)(c & (uint16_t)0x1FF);
+        huart->Instance->DR = (uint16_t)(c & (uint16_t)0x1FF);
     }
 }
 
 int serial_readable(serial_t *obj)
 {
-    int status;
-    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+    
     // Check if data is received
-    status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0);
-    return status;
+    return (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) ? 1 : 0;
 }
 
 int serial_writable(serial_t *obj)
 {
-    int status;
-    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+    
     // Check if data is transmitted
-    status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0);
-    return status;
+    return (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) ? 1 : 0;
 }
 
 void serial_clear(serial_t *obj)
 {
-    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
-    __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_TXE);
-    __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_RXNE);
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+    
+    huart->TxXferCount = 0;
+    huart->RxXferCount = 0;
 }
 
 void serial_pinout_tx(PinName tx)
@@ -348,12 +394,462 @@
 
 void serial_break_set(serial_t *obj)
 {
-    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
-    HAL_LIN_SendBreak(&UartHandle);
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+    
+    HAL_LIN_SendBreak(huart);
 }
 
 void serial_break_clear(serial_t *obj)
 {
+    (void)obj;
+}
+
+#if DEVICE_SERIAL_ASYNCH
+
+/******************************************************************************
+ * LOCAL HELPER FUNCTIONS
+ ******************************************************************************/
+
+/** 
+ * Configure the TX buffer for an asynchronous write serial transaction
+ *
+ * @param obj       The serial object.
+ * @param tx        The buffer for sending.
+ * @param tx_length The number of words to transmit.
+ */
+static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t width)
+{
+    (void)width;
+
+    // Exit if a transmit is already on-going
+    if (serial_tx_active(obj)) {
+        return;
+    }
+
+    obj->tx_buff.buffer = tx;
+    obj->tx_buff.length = tx_length;
+    obj->tx_buff.pos = 0;
+}
+  
+/**
+ * Configure the RX buffer for an asynchronous write serial transaction
+ *
+ * @param obj       The serial object.
+ * @param tx        The buffer for sending.
+ * @param tx_length The number of words to transmit.
+ */
+static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t width)
+{
+    (void)width;
+
+    // Exit if a reception is already on-going
+    if (serial_rx_active(obj)) {
+        return;
+    }
+
+    obj->rx_buff.buffer = rx;
+    obj->rx_buff.length = rx_length;
+    obj->rx_buff.pos = 0;
+}
+
+/** 
+ * Configure events
+ *
+ * @param obj    The serial object
+ * @param event  The logical OR of the events to configure
+ * @param enable Set to non-zero to enable events, or zero to disable them
+ */
+static void serial_enable_event(serial_t *obj, int event, uint8_t enable)
+{  
+    struct serial_s *obj_s = SERIAL_S(obj);
+    
+    // Shouldn't have to enable interrupt here, just need to keep track of the requested events.
+    if (enable) {
+        obj_s->events |= event;
+    } else {
+        obj_s->events &= ~event;
+    }
+}
+
+
+/**
+* Get index of serial object TX IRQ, relating it to the physical peripheral.
+*
+* @param obj pointer to serial object
+* @return internal NVIC TX IRQ index of U(S)ART peripheral
+*/
+static IRQn_Type serial_get_irq_n(serial_t *obj)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+    IRQn_Type irq_n;
+
+    switch (obj_s->index) {
+        case 0:
+            irq_n = USART1_IRQn;
+            break;
+
+        case 1:
+            irq_n = USART2_IRQn;
+            break;
+
+        case 2:
+            irq_n = USART3_IRQn;
+            break;
+
+        default:
+            irq_n = (IRQn_Type)0;
+    }
+    
+    return irq_n;
+}
+
+/******************************************************************************
+ * MBED API FUNCTIONS
+ ******************************************************************************/
+
+/** 
+ * Begin asynchronous TX transfer. The used buffer is specified in the serial
+ * object, tx_buff
+ *
+ * @param obj       The serial object
+ * @param tx        The buffer for sending
+ * @param tx_length The number of words to transmit
+ * @param tx_width  The bit width of buffer word
+ * @param handler   The serial handler
+ * @param event     The logical OR of events to be registered
+ * @param hint      A suggestion for how to use DMA with this transfer
+ * @return Returns number of data transfered, or 0 otherwise
+ */
+int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{    
+    // TODO: DMA usage is currently ignored
+    (void) hint;
+    
+    // Check buffer is ok
+    MBED_ASSERT(tx != (void*)0);
+    MBED_ASSERT(tx_width == 8); // support only 8b width
+    
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef * huart = &uart_handlers[obj_s->index];
+
+    if (tx_length == 0) {
+        return 0;
+    }
+  
+    // Set up buffer
+    serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width);
+  
+    // Set up events
+    serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events
+    serial_enable_event(obj, event, 1); // Set only the wanted events
+    
+    // Enable interrupt
+    IRQn_Type irq_n = serial_get_irq_n(obj);
+    NVIC_ClearPendingIRQ(irq_n);
+    NVIC_DisableIRQ(irq_n);
+    NVIC_SetPriority(irq_n, 1);
+    NVIC_SetVector(irq_n, (uint32_t)handler);
+    NVIC_EnableIRQ(irq_n);
+
+    // the following function will enable UART_IT_TXE and error interrupts
+    if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) {
+        return 0;
+    }
+    
+    return tx_length;
+}
+
+/** 
+ * Begin asynchronous RX transfer (enable interrupt for data collecting)
+ * The used buffer is specified in the serial object, rx_buff
+ *
+ * @param obj        The serial object
+ * @param rx         The buffer for sending
+ * @param rx_length  The number of words to transmit
+ * @param rx_width   The bit width of buffer word
+ * @param handler    The serial handler
+ * @param event      The logical OR of events to be registered
+ * @param handler    The serial handler
+ * @param char_match A character in range 0-254 to be matched
+ * @param hint       A suggestion for how to use DMA with this transfer
+ */
+void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
+{
+    // TODO: DMA usage is currently ignored
+    (void) hint;
+
+    /* Sanity check arguments */
+    MBED_ASSERT(obj);
+    MBED_ASSERT(rx != (void*)0);
+    MBED_ASSERT(rx_width == 8); // support only 8b width
+    
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
+    serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0);
+    serial_enable_event(obj, event, 1);
+    
+    // set CharMatch
+    obj->char_match = char_match;
+    
+    serial_rx_buffer_set(obj, rx, rx_length, rx_width);
+
+    IRQn_Type irq_n = serial_get_irq_n(obj);
+    NVIC_ClearPendingIRQ(irq_n);
+    NVIC_DisableIRQ(irq_n);
+    NVIC_SetPriority(irq_n, 0);
+    NVIC_SetVector(irq_n, (uint32_t)handler);
+    NVIC_EnableIRQ(irq_n);
+
+    // following HAL function will enable the RXNE interrupt + error interrupts    
+    HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length);
+}
+
+/**
+ * Attempts to determine if the serial peripheral is already in use for TX
+ *
+ * @param obj The serial object
+ * @return Non-zero if the TX transaction is ongoing, 0 otherwise
+ */
+uint8_t serial_tx_active(serial_t *obj)
+{
+    MBED_ASSERT(obj);
+    
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+    
+    return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0);
+}
+
+/**
+ * Attempts to determine if the serial peripheral is already in use for RX
+ *
+ * @param obj The serial object
+ * @return Non-zero if the RX transaction is ongoing, 0 otherwise
+ */
+uint8_t serial_rx_active(serial_t *obj)
+{
+    MBED_ASSERT(obj);
+    
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+    
+    return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
+}
+
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
+    if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
+        __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
+    }
+}
+
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
+    if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
+        volatile uint32_t tmpval = huart->Instance->DR; // Clear PE flag
+    } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
+        volatile uint32_t tmpval = huart->Instance->DR; // Clear FE flag
+    } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_NE) != RESET) {
+        volatile uint32_t tmpval = huart->Instance->DR; // Clear NE flag
+    } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
+        volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag
+    }
+}
+
+/**
+ * The asynchronous TX and RX handler.
+ *
+ * @param obj The serial object
+ * @return Returns event flags if a TX/RX transfer termination condition was met or 0 otherwise
+ */
+int serial_irq_handler_asynch(serial_t *obj)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+    
+    volatile int return_event = 0;
+    uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer);
+    uint8_t i = 0;
+    
+    // TX PART:
+    if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
+        if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
+            // Return event SERIAL_EVENT_TX_COMPLETE if requested
+            if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) {
+                return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events);
+            }
+        }
+    }
+    
+    // Handle error events
+    if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
+        if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
+            return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events);
+        }
+}
+
+    if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
+        if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
+            return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events);
+        }
+    }
+    
+    if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
+        if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
+            return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events);
+        }
+    }
+    
+    HAL_UART_IRQHandler(huart);
+    
+    // Abort if an error occurs
+    if (return_event & SERIAL_EVENT_RX_PARITY_ERROR ||
+            return_event & SERIAL_EVENT_RX_FRAMING_ERROR ||
+            return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
+        return return_event;
+    }
+    
+    //RX PART
+    if (huart->RxXferSize != 0) {
+        obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount;
+    }
+    if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) {
+        return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events);
+    }
+    
+    // Check if char_match is present
+    if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) {
+        if (buf != NULL) {
+            for (i = 0; i < obj->rx_buff.pos; i++) {
+                if (buf[i] == obj->char_match) {
+                    obj->rx_buff.pos = i;
+                    return_event |= (SERIAL_EVENT_RX_CHARACTER_MATCH & obj_s->events);
+                    serial_rx_abort_asynch(obj);
+                    break;
+                }
+            }
+        }
+    }
+    
+    return return_event;  
+}
+
+/** 
+ * Abort the ongoing TX transaction. It disables the enabled interupt for TX and
+ * flush TX hardware buffer if TX FIFO is used
+ *
+ * @param obj The serial object
+ */
+void serial_tx_abort_asynch(serial_t *obj)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+    
+    __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+    __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+    
+    // clear flags
+    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
+    
+    // reset states
+    huart->TxXferCount = 0;
+    // update handle state
+    if(huart->State == HAL_UART_STATE_BUSY_TX_RX) {
+        huart->State = HAL_UART_STATE_BUSY_RX;
+    } else {
+        huart->State = HAL_UART_STATE_READY;
+    }
+}
+
+/**
+ * Abort the ongoing RX transaction It disables the enabled interrupt for RX and
+ * flush RX hardware buffer if RX FIFO is used
+ *
+ * @param obj The serial object
+ */
+void serial_rx_abort_asynch(serial_t *obj)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+    
+    // disable interrupts
+    __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+    __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+    __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+    
+    // clear flags
+    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
+    volatile uint32_t tmpval = huart->Instance->DR; // Clear errors flag
+    
+    // reset states
+    huart->RxXferCount = 0;
+    // update handle state
+    if(huart->State == HAL_UART_STATE_BUSY_TX_RX) {
+        huart->State = HAL_UART_STATE_BUSY_TX;
+    } else {
+        huart->State = HAL_UART_STATE_READY;
+    }
 }
 
 #endif
+
+#if DEVICE_SERIAL_FC
+
+/**
+ * Set HW Control Flow
+ * @param obj    The serial object
+ * @param type   The Control Flow type (FlowControlNone, FlowControlRTS, FlowControlCTS, FlowControlRTSCTS)
+ * @param rxflow Pin for the rxflow
+ * @param txflow Pin for the txflow
+ */
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+
+    // Determine the UART to use (UART_1, UART_2, ...)
+    UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
+    UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
+
+    // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
+    obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
+    MBED_ASSERT(obj_s->uart != (UARTName)NC);
+
+    if(type == FlowControlNone) {
+        // Disable hardware flow control
+      obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
+    }
+    if (type == FlowControlRTS) {
+        // Enable RTS
+        MBED_ASSERT(uart_rts != (UARTName)NC);
+        obj_s->hw_flow_ctl = UART_HWCONTROL_RTS;
+        obj_s->pin_rts = rxflow;
+        // Enable the pin for RTS function
+        pinmap_pinout(rxflow, PinMap_UART_RTS);
+    }
+    if (type == FlowControlCTS) {
+        // Enable CTS
+        MBED_ASSERT(uart_cts != (UARTName)NC);
+        obj_s->hw_flow_ctl = UART_HWCONTROL_CTS;
+        obj_s->pin_cts = txflow;
+        // Enable the pin for CTS function
+        pinmap_pinout(txflow, PinMap_UART_CTS);
+    }
+    if (type == FlowControlRTSCTS) {
+        // Enable CTS & RTS
+        MBED_ASSERT(uart_rts != (UARTName)NC);
+        MBED_ASSERT(uart_cts != (UARTName)NC);
+        obj_s->hw_flow_ctl = UART_HWCONTROL_RTS_CTS;
+        obj_s->pin_rts = rxflow;
+        obj_s->pin_cts = txflow;
+        // Enable the pin for CTS function
+        pinmap_pinout(txflow, PinMap_UART_CTS);
+        // Enable the pin for RTS function
+        pinmap_pinout(rxflow, PinMap_UART_RTS);
+    }
+    
+    init_uart(obj);
+}
+
+#endif
+
+#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-#define DEVICE_RTC_LSI 1
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PeripheralNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PeripheralNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -62,7 +62,8 @@
 typedef enum {
     SPI_1 = (int)SPI1_BASE,
     SPI_2 = (int)SPI2_BASE,
-    SPI_3 = (int)SPI3_BASE
+    SPI_3 = (int)SPI3_BASE,
+    SPI_4 = (int)SPI4_BASE
 } SPIName;
 
 typedef enum {
@@ -79,7 +80,8 @@
     PWM_8  = (int)TIM8_BASE,
     PWM_15 = (int)TIM15_BASE,
     PWM_16 = (int)TIM16_BASE,
-    PWM_17 = (int)TIM17_BASE
+    PWM_17 = (int)TIM17_BASE,
+    PWM_20 = (int)TIM20_BASE
 } PWMName;
 
 typedef enum {

--- a/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PortNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PortNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -40,7 +40,9 @@
     PortC = 2,
     PortD = 3,
     PortE = 4,
-    PortF = 5
+    PortF = 5,
+    PortG = 6,
+    PortH = 7
 } PortName;
 
 #ifdef __cplusplus

--- a/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PeripheralNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,97 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE,
+    ADC_2 = (int)ADC2_BASE,
+    ADC_3 = (int)ADC3_BASE,
+    ADC_4 = (int)ADC4_BASE
+} ADCName;
+
+typedef enum {
+    DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+    UART_1 = (int)USART1_BASE,
+    UART_2 = (int)USART2_BASE,
+    UART_3 = (int)USART3_BASE,
+    UART_4 = (int)UART4_BASE,
+    UART_5 = (int)UART5_BASE
+} UARTName;
+
+#define STDIO_UART_TX  SERIAL_TX
+#define STDIO_UART_RX  SERIAL_RX
+#define STDIO_UART     UART_3
+
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE,
+    SPI_3 = (int)SPI3_BASE,
+	SPI_4 = (int)SPI4_BASE
+
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_2 = (int)I2C2_BASE,
+    I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+    PWM_1  = (int)TIM1_BASE,
+    PWM_2  = (int)TIM2_BASE,
+    PWM_3  = (int)TIM3_BASE,
+    PWM_4  = (int)TIM4_BASE,
+    PWM_8  = (int)TIM8_BASE,
+    PWM_15 = (int)TIM15_BASE,
+    PWM_16 = (int)TIM16_BASE,
+    PWM_17 = (int)TIM17_BASE,
+	PWM_20 = (int)TIM20_BASE
+} PWMName;
+
+typedef enum {
+    CAN_1 = (int)CAN_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PeripheralPins.c	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,390 @@
+/* mbed Microcontroller Library
+ '*******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+//       If you change them, you will have also to modify the corresponding xxx_api.c file
+//       for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+    {PA_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 //- ARDUINO A0
+    {PA_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 
+    {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+    {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+    {PA_4,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1
+    {PA_5,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2
+    {PA_6,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3
+    {PA_7,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4
+    //{PB_0,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 //(pin used by LED1)
+    {PB_1,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1
+    {PB_2,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12
+    {PB_11,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+    //{PB_11,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14
+    {PB_12,  ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC4_IN3
+    {PB_13,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5
+    //{PB_14,  ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC4_IN4 //(pin used by LED3)
+    {PB_15,  ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC4_IN5
+    //{PC_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+    {PC_0,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6   //- ARDUINO A1
+    //{PC_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+    {PC_1,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7  //- ARDUINO A3
+    {PC_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+    //{PC_2,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8*/
+    {PC_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9   //- ARDUINO A2
+    //{PC_3,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9*/
+    {PC_4,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5   //- ARDUINO A4
+    {PC_5,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 //- ARDUINO A5
+    //{PD_8,  ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC4_IN12 //(pin used by UART console)
+    //{PD_9,  ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC4_IN13 //(pin used by UART console)
+    {PD_10,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7
+    //{PD_10,  ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC4_IN7*/
+    {PD_11,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8
+    //{PD_11,  ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC4_IN8
+    {PD_12,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9
+    //{PD_12,  ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC4_IN9
+    //{PD_13,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10
+    {PD_13,  ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC4_IN10
+    {PD_14,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11
+    //{PD_14,  ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC4_IN11
+    {PE_7,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13
+    //{PE_8,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6
+    {PE_8,  ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC4_IN6
+    {PE_9,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2
+    {PE_10,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14
+    {PE_11,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15
+    {PE_12,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC3_IN16
+    {PE_13,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3
+    {PE_14,  ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC4_IN1
+    {PE_15,  ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC4_IN2
+    //{PF_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+    {PF_2,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10
+    {PF_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+    {NC,   NC,    0}
+};
+
+//*** DAC ***
+
+const PinMap PinMap_DAC[] = {
+    {PA_4,  DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1
+    {PA_5,  DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2
+    {NC,   NC,    0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+    //{PA_10, I2C_2   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, //(pin used for usb)
+    //{PA_14, I2C_1   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},// (pin used for stmc)
+   // {PB_5,  I2C_3   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C3)},// I2C3 not useable with usb , no SCL available.
+    //{PB_7,  I2C_1   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},//(pin used by LED2)
+    {PB_9,  I2C_1   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, //- ARDUINO D14 
+    //{PC_9,  I2C_3   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C3)},
+    //{PF_0,  I2C_2   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},// PF_0 not useable on board , need resistors changes I2C2 not useable
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    //{PA_8,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C3)}, //(pin used for usb)
+    //{PA_9,  I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, //(pin used for usb)
+   // {PA_15, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+   // {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, //- ARDUINO D15
+    //{PF_1,  I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},// I2C2 not useable due to PF_0 not useable
+    //{PF_6,  I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},// I2C2 not useable due to PF_0 not useable
+    {NC,    NC,    0}
+};
+
+//*** PWM ***
+
+const PinMap PinMap_PWM[] = {
+    {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+    {PA_1,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 1)},  // TIM15_CH1N
+    //{PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2
+    //{PA_2,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 0)},  // TIM15_CH1
+    {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3
+    {PA_3,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 2, 0)},  // TIM15_CH2 
+	//{PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4
+    {PA_4,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+    {PA_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)},  // TIM16_CH1
+    //{PA_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+    //{PA_7,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)},  // TIM17_CH1
+    //{PA_7,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)},  // TIM1_CH1N
+    //{PA_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    {PA_7,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)},  // TIM8_CH1N
+    //{PA_8,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 0)},  // TIM1_CH1  //(pin used for usb)
+    //{PA_9,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 0)},  // TIM1_CH2  //(pin used for usb)
+    //{PA_9,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 3, 0)},  // TIM2_CH3 //(pin used for usb)
+    //{PA_10, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 0)},  // TIM1_CH3  //(pin used for usb)
+    //{PA_10, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 4, 0)},  // TIM2_CH4 //(pin used for usb)
+    //{PA_11, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)},  // TIM1_CH1N //(pin used for usb)
+    //{PA_11, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 4, 0)},  // TIM1_CH4 //(pin used for usb)
+    //{PA_11, PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 1, 0)},  // TIM4_CH1 //(pin used for usb)
+    //{PA_12, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)},  // TIM16_CH1 //(pin used for usb)
+    //{PA_12, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)},  // TIM1_CH2N //(pin used for usb)
+    //{PA_12, PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 2, 0)},  // TIM4_CH2 //(pin used for usb)
+    //{PA_13, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)},  // TIM16_CH1N
+    //{PA_13, PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 3, 0)},  // TIM4_CH3 //(pin used SWD signals connected to ST-LINK/V2-1)
+    {PA_14, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 2, 0)},  // TIM8_CH2
+    {PA_15, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+    {PA_15, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 1, 0)},  // TIM8_CH1
+    //{PB_0,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)},  // TIM1_CH2N
+    {PB_0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
+    //{PB_0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)},  // TIM8_CH2N
+    //{PB_1,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)},  // TIM1_CH3N
+    //{PB_1,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
+    {PB_1,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 1)},  // TIM8_CH3N
+    {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2
+    //{PB_3,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)},  // TIM8_CH1N
+    {PB_4,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)},  // TIM16_CH1
+    //{PB_4,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+    //{PB_4,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)},  // TIM8_CH2N
+    {PB_5,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)},  // TIM17_CH1
+    //{PB_5,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    //{PB_5,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)},  // TIM8_CH3N
+    {PB_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)},  // TIM16_CH1N
+    //{PB_6,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)},  // TIM4_CH1
+    //{PB_6,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 1, 0)},  // TIM8_CH1
+    //{PB_7,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)},  // TIM17_CH1N
+    //{PB_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3, 4, 0)},  // TIM3_CH4
+    {PB_7,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)},  // TIM4_CH2
+    {PB_8,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)},  // TIM16_CH1
+    //{PB_8,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)},  // TIM4_CH3
+    //{PB_8,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 2, 0)},  // TIM8_CH2
+    {PB_9,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)},  // TIM17_CH1
+    //{PB_9,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)},  // TIM4_CH4
+    //{PB_9,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 3, 0)},  // TIM8_CH3
+    {PB_10, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3
+    {PB_11, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4
+    {PB_13, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)},  // TIM1_CH1N
+    {PB_14, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15, 1, 0)},  // TIM15_CH1
+    //{PB_14, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)},  // TIM1_CH2N
+    //{PB_15, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 1)},  // TIM15_CH1N
+    {PB_15, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15, 2, 0)},  // TIM15_CH2
+    //{PB_15, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1, 3, 1)},  // TIM1_CH3N
+    {PC_0,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)},  // TIM1_CH1
+    {PC_1,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)},  // TIM1_CH2
+    {PC_2,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)},  // TIM1_CH3
+    {PC_3,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)},  // TIM1_CH4
+    {PC_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+    //{PC_6,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 0)},  // TIM8_CH1
+    //{PC_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    {PC_7,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 0)},  // TIM8_CH2
+    {PC_8,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
+    //{PC_8,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 0)},  // TIM8_CH3
+    //{PC_9,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
+    {PC_9,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 4, 0)},  // TIM8_CH4
+    {PC_10, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)},  // TIM8_CH1N
+    {PC_11, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)},  // TIM8_CH2N
+    {PC_12, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 1)},  // TIM8_CH3N
+	//{PC_13, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1, 1, 1)},  // TIM1_CH1N  //(pin used USER BUTTON)
+    {PD_1,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 4, 0)},  // TIM8_CH4
+    {PD_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)},  // TIM2_CH1
+    {PD_4,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2
+    {PD_6,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},  // TIM2_CH4
+    {PD_7,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},  // TIM2_CH3
+    {PD_12, PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)},  // TIM4_CH1
+    {PD_13, PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)},  // TIM4_CH2
+    {PD_14, PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)},  // TIM4_CH3
+    {PD_15, PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)},  // TIM4_CH4 - ARDUINO D9
+    {PE_0,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM16, 1, 0)},  // TIM16_CH1
+   // {PE_1,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM17, 1, 0)},  // TIM17_CH1
+    {PE_1,  PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM20, 4, 0)},  // TIM20_CH4
+    {PE_2,  PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM20, 1, 0)},  // TIM20_CH1
+    //{PE_2,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+    {PE_3,  PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM20, 2, 0)},  // TIM20_CH2
+    //{PE_3,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    //{PE_4,  PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM20, 1, 1)},  // TIM20_CH1N
+    {PE_4,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
+    //{PE_5,  PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM20, 2, 1)},  // TIM20_CH2N
+    {PE_5,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
+    {PE_6,  PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM20, 3, 1)},  // TIM20_CH3N
+    {PE_8,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)},  // TIM1_CH1N
+    {PE_9,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)},  // TIM1_CH1
+    {PE_10, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)},  // TIM1_CH2N
+    {PE_11, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)},  // TIM1_CH2
+    {PE_12, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)},  // TIM1_CH3N
+    {PE_13, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)},  // TIM1_CH3
+    {PE_14, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)},  // TIM1_CH4
+    //{PF_0,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)},  // TIM1_CH3N //PF_0 not useable , need resitor changes on board
+    {PF_2,  PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 3, 0)},  // TIM20_CH3
+    {PF_3,  PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 4, 0)},  // TIM20_CH4
+    {PF_4,  PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM20, 1, 1)},  // TIM20_CH1N
+    {PF_5,  PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 2, 1)},  // TIM20_CH2N
+    {PF_6,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)},  // TIM4_CH4
+    {PF_9,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM15, 1, 0)},  // TIM15_CH1
+    {PF_10, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM15, 2, 0)},  // TIM15_CH2
+    {PF_12, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 1, 0)},  // TIM20_CH1
+    {PF_13, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 2, 0)},  // TIM20_CH2
+    {PF_14, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 3, 0)},  // TIM20_CH3
+    {PF_15, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 4, 0)},  // TIM20_CH4
+    {PG_0,  PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 1, 1)},  // TIM20_CH1N
+    {PG_1,  PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 2, 1)},  // TIM20_CH2N
+    {PG_2,  PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 3, 1)},  // TIM20_CH3N
+    {PH_0,  PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 1, 0)},  // TIM20_CH1
+    {PH_1,  PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 2, 0)},  // TIM20_CH2
+    {NC,    NC,    0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+    {PA_2,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    //{PA_9,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, //(pin used for usb)
+    {PA_14, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PB_3,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PB_6,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_9,  UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_10, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_4,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PC_10, UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)},
+    //{PC_10, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_12, UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART5)},
+    {PD_5,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PD_8,  UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, //(pin used by  uart console)
+    {PE_0,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PA_3,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    //{PA_10, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, //(pin used for usb)
+    {PA_15, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PB_4,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    //{PB_7,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, //(pin used by LED2)
+    {PB_8,  UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_11, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_5,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PC_11, UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)},
+    //{PC_11, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PD_2,  UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART5)},
+    {PD_6,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PD_9,  UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},// (pin used by uart console)
+    {PE_1,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PE_15, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {PF_6,  UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PA_1,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    //{PB_14, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, //(pin used by LED3)
+    {PD_12, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    //{PA_12, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, //(pin used for usb)
+    {PD_4,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    {PA_0,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PB_13, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PD_11, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PA_11, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+   // {PA_13, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, //(pin used SWD signals connected to ST-LINK/V2-1)
+    {PD_3,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {NC,    NC,    0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, //- ARDUINO D11
+    //{PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, //(pin used for usb)
+    //{PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_5,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    //{PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},//SPI2 not useable with usb (no MISO pin)
+    {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PE_6,  SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+    {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+	{PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, //- ARDUINO D12
+	//{PA_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, //(pin used for usb)
+	//{PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+	{PB_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+	//{PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, //(pin used by LED3)
+	{PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+	{PE_5,  SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+	{PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+	{NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},//- ARDUINO D13
+    //{PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_3,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+   //{PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP,GPIO_AF5_SPI2)},//SPI2 not useable with usb
+    {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PE_2,  SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+    {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+    //{PF_1,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, //SPI2 not useable with usb (no MISO pin)
+    //{PF_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, //SPI2 not useable with usb  (no MISO pin)
+    //{PF_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, //SPI2 not useable with usb  (no MISO pin)
+
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+   // {PA_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+   // {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    //{PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},//SPI2 not useable with usb (no MISO pin)
+    //{PD_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)},//SPI2 not useable with usb (no MISO pin)
+    {PE_3,  SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+    {PE_4,  SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+    {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+   //{PF_0,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},//SPI2 not useable with usb (no MISO pin)
+
+    {NC,    NC,    0}
+};
+
+//*** CAN ***
+
+const PinMap PinMap_CAN_RD[] = {
+    //{PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_CAN)}, //(pin used for usb)
+    {PB_8,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_CAN)},
+    {PD_0,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_CAN)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_CAN_TD[] = {
+    //{PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_CAN)}, //(pin used for usb)
+    {PB_9,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_CAN)},
+    {PD_1,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_CAN)},
+    {NC,    NC,    0}
+};

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,255 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
+#define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
+#define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
+#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+#define STM_MODE_INPUT              (0)
+#define STM_MODE_OUTPUT_PP          (1)
+#define STM_MODE_OUTPUT_OD          (2)
+#define STM_MODE_AF_PP              (3)
+#define STM_MODE_AF_OD              (4)
+#define STM_MODE_ANALOG             (5)
+#define STM_MODE_IT_RISING          (6)
+#define STM_MODE_IT_FALLING         (7)
+#define STM_MODE_IT_RISING_FALLING  (8)
+#define STM_MODE_EVT_RISING         (9)
+#define STM_MODE_EVT_FALLING        (10)
+#define STM_MODE_EVT_RISING_FALLING (11)
+#define STM_MODE_IT_EVT_RESET       (12)
+
+// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
+// Low nibble  = pin number
+#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
+#define STM_PIN(X)  ((uint32_t)(X) & 0xF)
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+    PA_0  = 0x00,
+    PA_1  = 0x01,
+    PA_2  = 0x02,
+    PA_3  = 0x03,
+    PA_4  = 0x04,
+    PA_5  = 0x05,
+    PA_6  = 0x06,
+    PA_7  = 0x07,
+    PA_8  = 0x08,
+    PA_9  = 0x09,
+    PA_10 = 0x0A,
+    PA_11 = 0x0B,
+    PA_12 = 0x0C,
+    PA_13 = 0x0D,
+    PA_14 = 0x0E,
+    PA_15 = 0x0F,
+
+    PB_0  = 0x10,
+    PB_1  = 0x11,
+    PB_2  = 0x12,
+    PB_3  = 0x13,
+    PB_4  = 0x14,
+    PB_5  = 0x15,
+    PB_6  = 0x16,
+    PB_7  = 0x17,
+    PB_8  = 0x18,
+    PB_9  = 0x19,
+    PB_10 = 0x1A,
+    PB_11 = 0x1B,
+    PB_12 = 0x1C,
+    PB_13 = 0x1D,
+    PB_14 = 0x1E,
+    PB_15 = 0x1F,
+
+    PC_0  = 0x20,
+    PC_1  = 0x21,
+    PC_2  = 0x22,
+    PC_3  = 0x23,
+    PC_4  = 0x24,
+    PC_5  = 0x25,
+    PC_6  = 0x26,
+    PC_7  = 0x27,
+    PC_8  = 0x28,
+    PC_9  = 0x29,
+    PC_10 = 0x2A,
+    PC_11 = 0x2B,
+    PC_12 = 0x2C,
+    PC_13 = 0x2D,
+    PC_14 = 0x2E,
+    PC_15 = 0x2F,
+
+    PD_0  = 0x30,
+    PD_1  = 0x31,
+    PD_2  = 0x32,
+    PD_3  = 0x33,
+    PD_4  = 0x34,
+    PD_5  = 0x35,
+    PD_6  = 0x36,
+    PD_7  = 0x37,
+    PD_8  = 0x38,
+    PD_9  = 0x39,
+    PD_10 = 0x3A,
+    PD_11 = 0x3B,
+    PD_12 = 0x3C,
+    PD_13 = 0x3D,
+    PD_14 = 0x3E,
+    PD_15 = 0x3F,
+
+    PE_0  = 0x40,
+    PE_1  = 0x41,
+    PE_2  = 0x42,
+    PE_3  = 0x43,
+    PE_4  = 0x44,
+    PE_5  = 0x45,
+    PE_6  = 0x46,
+    PE_7  = 0x47,
+    PE_8  = 0x48,
+    PE_9  = 0x49,
+    PE_10 = 0x4A,
+    PE_11 = 0x4B,
+    PE_12 = 0x4C,
+    PE_13 = 0x4D,
+    PE_14 = 0x4E,
+    PE_15 = 0x4F,
+
+    PF_0  = 0x50,
+    PF_1  = 0x51,
+    PF_2  = 0x52,
+    PF_3  = 0x53,
+    PF_4  = 0x54,
+    PF_5  = 0x55,
+    PF_6  = 0x56,
+    PF_7  = 0x57,
+    PF_8  = 0x58,
+    PF_9  = 0x59,
+    PF_10 = 0x5A,
+    PF_11 = 0x5B,
+    PF_12 = 0x5C,
+    PF_13 = 0x5D,
+    PF_14 = 0x5E,
+    PF_15 = 0x5F,
+
+    PG_0  = 0x60,
+    PG_1  = 0x61,
+    PG_2  = 0x62,
+    PG_3  = 0x63,
+    PG_4  = 0x64,
+    PG_5  = 0x65,
+    PG_6  = 0x66,
+    PG_7  = 0x67,
+    PG_8  = 0x68,
+    PG_9  = 0x69,
+    PG_10 = 0x6A,
+    PG_11 = 0x6B,
+    PG_12 = 0x6C,
+    PG_13 = 0x6D,
+    PG_14 = 0x6E,
+    PG_15 = 0x6F,
+
+    PH_0  = 0x70,
+    PH_1  = 0x71,
+    PH_2  = 0x72,
+
+    // Arduino connector namings
+    A0          = PA_3,
+    A1          = PC_0,
+    A2          = PC_3,
+    A3          = PC_1,
+    A4          = PC_4,
+	A5          = PC_5,
+    D0          = PG_9,
+    D1          = PG_14,
+    D2          = PF_15,
+    D3          = PE_13,
+    D4          = PF_14,
+    D5          = PE_11,
+    D6          = PE_9,
+    D7          = PF_13,
+    D8          = PF_12,
+    D9          = PD_15,
+    D10         = PD_14,
+    D11         = PA_7,
+    D12         = PA_6,
+    D13         = PA_5,
+    D14         = PB_9,
+    D15         = PB_8,
+
+    // Generic signals namings
+    LED1        = PB_0,
+    LED2        = PB_7,
+    LED3        = PB_14,
+    LED4        = LED1,
+    USER_BUTTON = PC_13,
+    SERIAL_TX   = PD_8, // Virtual Com Port
+    SERIAL_RX   = PD_9, // Virtual Com Port
+    USBTX       = SERIAL_TX, // Virtual Com Port
+    USBRX       = SERIAL_RX, // Virtual Com Port
+    I2C_SCL     = D15,
+    I2C_SDA     = D14,
+    SPI_MOSI    = D11,
+    SPI_MISO    = D12,
+    SPI_SCK     = D13,
+    SPI_CS      = D10,
+    PWM_OUT     = D9,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullNone  = 0,
+    PullUp    = 1,
+    PullDown  = 2,
+    OpenDrain = 3,
+    PullDefault = PullNone
+} PinMode;
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PortNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PortA = 0,
+    PortB = 1,
+    PortC = 2,
+    PortD = 3,
+    PortE = 4,
+    PortF = 5,
+	PortG = 6,
+	PortH = 7
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,54 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+
+
+
+
+
+
+
+
+
+
+//=======================================
+
+#define DEVICE_ID_LENGTH       24
+
+
+
+
+#include "objects.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/objects.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,120 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    IRQn_Type irq_n;
+    uint32_t irq_index;
+    uint32_t event;
+    PinName pin;
+};
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+    PinDirection direction;
+    __IO uint32_t *reg_in;
+    __IO uint32_t *reg_out;
+};
+
+struct analogin_s {
+    ADCName adc;
+    PinName pin;
+    uint32_t channel;
+};
+
+struct dac_s {
+    DACName dac;
+    PinName pin;
+    uint32_t channel;
+};
+
+struct serial_s {
+    UARTName uart;
+    int index; // Used by irq
+    uint32_t baudrate;
+    uint32_t databits;
+    uint32_t stopbits;
+    uint32_t parity;
+    PinName pin_tx;
+    PinName pin_rx;
+};
+
+struct spi_s {
+    SPIName spi;
+    uint32_t bits;
+    uint32_t cpol;
+    uint32_t cpha;
+    uint32_t mode;
+    uint32_t nss;
+    uint32_t br_presc;
+    PinName pin_miso;
+    PinName pin_mosi;
+    PinName pin_sclk;
+    PinName pin_ssel;
+};
+
+struct i2c_s {
+    I2CName  i2c;
+    uint32_t slave;
+};
+
+struct pwmout_s {
+    PWMName pwm;
+    PinName pin;
+    uint32_t prescaler;
+    uint32_t period;
+    uint32_t pulse;
+    uint32_t channel;
+    uint32_t inverted;
+};
+
+struct can_s {
+    CANName can;
+    int index;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3/device.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,40 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+//=======================================
+#define DEVICE_ID_LENGTH       24
+
+#include "objects.h"
+
+#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F3/pinmap.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3/pinmap.c	Fri Sep 16 16:24:25 2016 +0100
@@ -71,16 +71,50 @@
             gpio_add = GPIOD_BASE;
             __GPIOD_CLK_ENABLE();
             break;
-#if defined(GPIOE_BASE)
+#if defined GPIOE_BASE
         case PortE:
             gpio_add = GPIOE_BASE;
             __GPIOE_CLK_ENABLE();
             break;
 #endif
+#if defined GPIOF_BASE
         case PortF:
             gpio_add = GPIOF_BASE;
             __GPIOF_CLK_ENABLE();
             break;
+#endif
+#if defined GPIOG_BASE
+        case PortG:
+            gpio_add = GPIOG_BASE;
+            __GPIOG_CLK_ENABLE();
+            break;
+#endif
+#if defined GPIOH_BASE
+        case PortH:
+            gpio_add = GPIOH_BASE;
+            __GPIOH_CLK_ENABLE();
+            break;
+#endif
+#if defined GPIOI_BASE
+        case PortI:
+            gpio_add = GPIOI_BASE;
+            __GPIOI_CLK_ENABLE();
+            break;
+#endif
+#if defined GPIOJ_BASE
+        case PortJ:
+            gpio_add = GPIOJ_BASE;
+            __GPIOJ_CLK_ENABLE();
+            break;
+#endif
+#if defined GPIOK_BASE
+        case PortK:
+            gpio_add = GPIOK_BASE;
+            __GPIOK_CLK_ENABLE();
+            break;
+#endif
+
+
         default:
             error("Pinmap error: wrong port number.");
             break;

--- a/targets/hal/TARGET_STM/TARGET_STM32F3/pwmout_api.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3/pwmout_api.c	Fri Sep 16 16:24:25 2016 +0100
@@ -50,18 +50,60 @@
     obj->channel = STM_PIN_CHANNEL(function);
     obj->inverted = STM_PIN_INVERTED(function);
 
-    // Enable TIM clock
-    if (obj->pwm == PWM_1) __TIM1_CLK_ENABLE();
-    if (obj->pwm == PWM_2) __TIM2_CLK_ENABLE();
-#if defined(TIM3)
-    if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE();
+#if defined(TIM1_BASE)
+    if (obj->pwm == PWM_1) __HAL_RCC_TIM1_CLK_ENABLE();
+#endif
+#if defined(TIM2_BASE)
+    if (obj->pwm == PWM_2) __HAL_RCC_TIM2_CLK_ENABLE();
+#endif
+#if defined(TIM3_BASE)
+    if (obj->pwm == PWM_3) __HAL_RCC_TIM3_CLK_ENABLE();
+#endif
+#if defined(TIM4_BASE)
+    if (obj->pwm == PWM_4) __HAL_RCC_TIM4_CLK_ENABLE();
+#endif
+#if defined(TIM5_BASE)
+    if (obj->pwm == PWM_5) __HAL_RCC_TIM5_CLK_ENABLE();
+#endif
+#if defined(TIM8_BASE)
+    if (obj->pwm == PWM_8) __HAL_RCC_TIM8_CLK_ENABLE();
+#endif
+#if defined(TIM9_BASE)
+    if (obj->pwm == PWM_9) __HAL_RCC_TIM9_CLK_ENABLE();
+#endif
+#if defined(TIM10_BASE)
+    if (obj->pwm == PWM_10) __HAL_RCC_TIM10_CLK_ENABLE();
+#endif
+#if defined(TIM11_BASE)
+    if (obj->pwm == PWM_11) __HAL_RCC_TIM11_CLK_ENABLE();
 #endif
-#if defined(TIM8)
-    if (obj->pwm == PWM_8) __TIM8_CLK_ENABLE();
+#if defined(TIM12_BASE)
+    if (obj->pwm == PWM_12) __HAL_RCC_TIM12_CLK_ENABLE();
+#endif
+#if defined(TIM13_BASE)
+    if (obj->pwm == PWM_13) __HAL_RCC_TIM13_CLK_ENABLE();
+#endif
+#if defined(TIM14_BASE)
+    if (obj->pwm == PWM_14) __HAL_RCC_TIM14_CLK_ENABLE();
+#endif
+#if defined(TIM15_BASE)
+    if (obj->pwm == PWM_15) __HAL_RCC_TIM15_CLK_ENABLE();
 #endif
-    if (obj->pwm == PWM_15) __TIM15_CLK_ENABLE();
-    if (obj->pwm == PWM_16) __TIM16_CLK_ENABLE();
-    if (obj->pwm == PWM_17) __TIM17_CLK_ENABLE();
+#if defined(TIM16_BASE)
+    if (obj->pwm == PWM_16) __HAL_RCC_TIM16_CLK_ENABLE();
+#endif
+#if defined(TIM17_BASE)
+    if (obj->pwm == PWM_17) __HAL_RCC_TIM17_CLK_ENABLE();
+#endif
+#if defined(TIM18_BASE)
+    if (obj->pwm == PWM_18) __HAL_RCC_TIM18_CLK_ENABLE();
+#endif
+#if defined(TIM19_BASE)
+    if (obj->pwm == PWM_19) __HAL_RCC_TIM19_CLK_ENABLE();
+#endif
+#if defined(TIM20_BASE)
+    if (obj->pwm == PWM_20) __HAL_RCC_TIM20_CLK_ENABLE();
+#endif
 
     // Configure GPIO
     pinmap_pinout(pin, PinMap_PWM);

--- a/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c	Fri Sep 16 16:24:25 2016 +0100
@@ -96,6 +96,12 @@
     }
 #endif
 
+#if defined(SPI4_BASE)
+    if (obj->spi == SPI_3) {
+        __SPI4_CLK_ENABLE();
+    }
+#endif
+
     // Configure the SPI pins
     pinmap_pinout(mosi, PinMap_SPI_MOSI);
     pinmap_pinout(miso, PinMap_SPI_MISO);
@@ -152,6 +158,14 @@
     }
 #endif
 
+#if defined(SPI4_BASE)
+    if (obj->spi == SPI_4) {
+        __SPI4_FORCE_RESET();
+        __SPI4_RELEASE_RESET();
+        __SPI4_CLK_DISABLE();
+    }
+#endif
+
     // Configure GPIOs
     pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
     pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
@@ -224,6 +238,9 @@
 #if defined SPI3_BASE
 		case SPI_3:
 #endif
+#if defined SPI4_BASE
+		case SPI_4:
+#endif
 			/* SPI_2 and SPI_3. Source CLK is PCKL1 */
 			spi_hz = HAL_RCC_GetPCLK1Freq();
 			break;

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PinNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -37,13 +37,13 @@
 #endif
 
 // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
 #define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
 #define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
 #define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x1F)
+#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
 #define STM_MODE_INPUT              (0)
 #define STM_MODE_OUTPUT_PP          (1)
 #define STM_MODE_OUTPUT_OD          (2)
@@ -222,6 +222,10 @@
     PI_14 = 0x8E,
     PI_15 = 0x8F,
 
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
 
     // Arduino connector namings
     A0          = PA_0,

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PeripheralPins.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PeripheralPins.c	Fri Sep 16 16:24:25 2016 +0100
@@ -55,6 +55,9 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT)
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP)
     {NC,   NC,    0}
 };
 

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PinNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -37,13 +37,13 @@
 #endif
 
 // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
 #define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
 #define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
 #define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x1F)
+#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
 #define STM_MODE_INPUT              (0)
 #define STM_MODE_OUTPUT_PP          (1)
 #define STM_MODE_OUTPUT_OD          (2)
@@ -156,6 +156,11 @@
     PH_0  = 0x70,
     PH_1  = 0x71,
 
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
     // Arduino connector namings
     A0          = PA_1,
     A1          = PA_2,
@@ -185,6 +190,7 @@
     LED2        = LED1,
     LED3        = PD_11,
     LED4        = PD_12,
+    LED_RED     = LED1,
     USER_BUTTON = PD_13,
     SERIAL_TX   = PC_10,
     SERIAL_RX   = PC_11,

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,55 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-#define LED_RED                 LED1
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PeripheralPins.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PeripheralPins.c	Fri Sep 16 16:24:25 2016 +0100
@@ -55,6 +55,9 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT)
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP)
     {NC,   NC,    0}
 };
 

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PinNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -37,13 +37,13 @@
 #endif
 
 // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
 #define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
 #define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
 #define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x1F)
+#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
 #define STM_MODE_INPUT              (0)
 #define STM_MODE_OUTPUT_PP          (1)
 #define STM_MODE_OUTPUT_OD          (2)
@@ -139,11 +139,17 @@
     PH_0  = 0x70,
     PH_1  = 0x71,
 
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
     // Generic signals namings
     LED1        = PD_12,
     LED2        = PD_13,
     LED3        = PD_14,
     LED4        = PD_15,
+    LED_RED     = LED1,
     USER_BUTTON = PA_0,
     SERIAL_TX   = PA_2,
     SERIAL_RX   = PA_3,

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-#define LED_RED                 LED1
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PeripheralPins.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PeripheralPins.c	Fri Sep 16 16:24:25 2016 +0100
@@ -55,6 +55,9 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18
     {NC,   NC,    0}
 };
 

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PinNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -37,13 +37,13 @@
 #endif
 
 // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_MODE(X)     (((X) >> 0)  & 0x0F)
-#define STM_PIN_PUPD(X)     (((X) >> 4)  & 0x07)
-#define STM_PIN_AFNUM(X)    (((X) >> 7)  & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
+#define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
+#define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x1F)
+#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
 #define STM_MODE_INPUT              (0)
 #define STM_MODE_OUTPUT_PP          (1)
 #define STM_MODE_OUTPUT_OD          (2)
@@ -222,6 +222,11 @@
     PI_14 = 0x8E,
     PI_15 = 0x8F,
 
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
     // Generic signals namings
     LED1        = PD_13,
     LED2        = PD_12,
@@ -229,6 +234,7 @@
     LED4        = PD_12,
     LED5        = PD_14,
     LED6        = PD_15,
+    LED_RED     = LED1,
     USER_BUTTON = PA_0,
     SERIAL_TX   = PA_2,	/* USART2 */
     SERIAL_RX   = PA_3,

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-#define LED_RED                 LED1
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralPins.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralPins.c	Fri Sep 16 16:24:25 2016 +0100
@@ -63,6 +63,9 @@
     {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6,  0)}, // ADC3_IN6
     {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7,  0)}, // ADC3_IN7
     {PF_10,ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8,  0)}, // ADC3_IN8
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT)
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP)
     {NC,   NC,    0}
 };
 

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PinNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -37,21 +37,13 @@
 #endif
 
 // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((MODE  & 0x0F) << 0) |\
-                                                ((PUPD  & 0x07) << 4) |\
-                                                ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((MODE     & 0x0F) <<  0) |\
-                                                                       ((PUPD     & 0x07) <<  4) |\
-                                                                       ((AFNUM    & 0x0F) <<  7) |\
-                                                                       ((CHANNEL  & 0x0F) << 11) |\
-                                                                       ((INVERTED & 0x01) << 15)))
-
-#define STM_PIN_MODE(X)     (((X) >>  0) & 0x0F)
-#define STM_PIN_PUPD(X)     (((X) >>  4) & 0x07)
-#define STM_PIN_AFNUM(X)    (((X) >>  7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
+#define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
+#define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x1F)
+#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
 #define STM_MODE_INPUT              (0)
 #define STM_MODE_OUTPUT_PP          (1)
 #define STM_MODE_OUTPUT_OD          (2)
@@ -162,7 +154,6 @@
     PE_14 = 0x4E,
     PE_15 = 0x4F,
 
-
     PF_0  = 0x50,
     PF_1  = 0x51,
     PF_2  = 0x52,
@@ -180,7 +171,6 @@
     PF_14 = 0x5E,
     PF_15 = 0x5F,
 
-
     PG_0  = 0x60,
     PG_1  = 0x61,
     PG_2  = 0x62,
@@ -198,15 +188,20 @@
     PG_14 = 0x6E,
     PG_15 = 0x6F,
 
-
     PH_0  = 0x70,
     PH_1  = 0x71,
 
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
     // Generic signals namings
     LED1        = PG_13, // Corresponds to LD3 on MB1075B
     LED2        = PG_14, // Corresponds to LD4 on MB1075B
     LED3        = PG_13,
     LED4        = PG_14,
+    LED_RED     = LED2,
     USER_BUTTON = PA_0,
     SERIAL_TX   = PA_9,
     SERIAL_RX   = PA_10,

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,55 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-#define LED_RED                 LED2
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PeripheralPins.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PeripheralPins.c	Fri Sep 16 16:24:25 2016 +0100
@@ -63,6 +63,9 @@
     {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6,  0)}, // ADC3_IN6
     {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7,  0)}, // ADC3_IN7
     {PF_10,ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8,  0)}, // ADC3_IN8
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT)
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP)
     {NC,   NC,    0}
 };
 

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PinNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -37,13 +37,13 @@
 #endif
 
 // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
 #define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
 #define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
 #define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x1F)
+#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
 #define STM_MODE_INPUT              (0)
 #define STM_MODE_OUTPUT_PP          (1)
 #define STM_MODE_OUTPUT_OD          (2)
@@ -154,7 +154,6 @@
     PE_14 = 0x4E,
     PE_15 = 0x4F,
 
-
     PF_0  = 0x50,
     PF_1  = 0x51,
     PF_2  = 0x52,
@@ -172,7 +171,6 @@
     PF_14 = 0x5E,
     PF_15 = 0x5F,
 
-
     PG_0  = 0x60,
     PG_1  = 0x61,
     PG_2  = 0x62,
@@ -190,7 +188,6 @@
     PG_14 = 0x6E,
     PG_15 = 0x6F,
 
-
     PH_0  = 0x70,
     PH_1  = 0x71,
     PH_2  = 0x72,
@@ -208,7 +205,6 @@
     PH_14 = 0x7E,
     PH_15 = 0x7F,
 
-
     PI_0  = 0x80,
     PI_1  = 0x81,
     PI_2  = 0x82,
@@ -226,7 +222,6 @@
     PI_14 = 0x8E,
     PI_15 = 0x8F,
 
-
     PJ_0  = 0x90,
     PJ_1  = 0x91,
     PJ_2  = 0x92,
@@ -244,6 +239,10 @@
     PK_6  = 0xA6,
     PK_7  = 0xA7,
 
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
 
     // Arduino connector namings
     A0          = PB_1,
@@ -276,6 +275,7 @@
     LED3        = PD_5,
     LED4        = PK_3,
     LED7        = PD_3,
+    LED_RED     = LED1,
     USER_BUTTON = PA_0,
     SERIAL_TX   = PB_10,
     SERIAL_RX   = PB_11,

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,55 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-#define LED_RED                 LED1
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PeripheralPins.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PeripheralPins.c	Fri Sep 16 16:24:25 2016 +0100
@@ -55,6 +55,9 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT)
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP)
     {NC,   NC,    0}
 };
 

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PinNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -37,13 +37,13 @@
 #endif
 
 // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
 #define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
 #define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
 #define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x1F)
+#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
 #define STM_MODE_INPUT              (0)
 #define STM_MODE_OUTPUT_PP          (1)
 #define STM_MODE_OUTPUT_OD          (2)
@@ -124,6 +124,11 @@
     PH_0  = 0x70,
     PH_1  = 0x71,
 
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
     // Not connected
     NC = (int)0xFFFFFFFF,
 

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PeripheralPins.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PeripheralPins.c	Fri Sep 16 16:24:25 2016 +0100
@@ -55,6 +55,9 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT)
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP)
     {NC,   NC,    0}
 };
 

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -37,13 +37,13 @@
 #endif
 
 // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
 #define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
 #define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
 #define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x1F)
+#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
 #define STM_MODE_INPUT              (0)
 #define STM_MODE_OUTPUT_PP          (1)
 #define STM_MODE_OUTPUT_OD          (2)
@@ -124,6 +124,11 @@
     PH_0  = 0x70,
     PH_1  = 0x71,
 
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
     // Arduino connector namings
     A0          = PC_2,
     A1          = PC_0,

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralPins.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralPins.c	Fri Sep 16 16:24:25 2016 +0100
@@ -55,6 +55,9 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18
     {NC,   NC,    0}
 };
 

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PinNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -37,13 +37,13 @@
 #endif
 
 // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
 #define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
 #define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
 #define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x1F)
+#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
 #define STM_MODE_INPUT              (0)
 #define STM_MODE_OUTPUT_PP          (1)
 #define STM_MODE_OUTPUT_OD          (2)
@@ -125,6 +125,11 @@
     PH_0  = 0x70,
     PH_1  = 0x71,
 
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
     // Generic signals namings
     LED1        = PA_9,
     LED2        = PA_9,

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralPins.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralPins.c	Fri Sep 16 16:24:25 2016 +0100
@@ -55,6 +55,9 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT)
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP)
     {NC,   NC,    0}
 };
 

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -37,13 +37,13 @@
 #endif
 
 // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
 #define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
 #define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
 #define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x1F)
+#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
 #define STM_MODE_INPUT              (0)
 #define STM_MODE_OUTPUT_PP          (1)
 #define STM_MODE_OUTPUT_OD          (2)
@@ -124,6 +124,11 @@
     PH_0  = 0x70,
     PH_1  = 0x71,
 
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
     // Generic signals namings
     XBEE_DOUT        = PA_2,
     XBEE_DIN         = PA_3,

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PeripheralPins.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PeripheralPins.c	Fri Sep 16 16:24:25 2016 +0100
@@ -55,6 +55,9 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18
     {NC,   NC,    0}
 };
 

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PinNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -37,14 +37,13 @@
 #endif
 
 // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
 #define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
 #define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
 #define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
-#define STM_PIN_AFNUM(X)    (((X) >> 7)  & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x1F)
+#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
 #define STM_MODE_INPUT              (0)
 #define STM_MODE_OUTPUT_PP          (1)
 #define STM_MODE_OUTPUT_OD          (2)
@@ -125,6 +124,11 @@
     PH_0  = 0x70,
     PH_1  = 0x71,
 
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
     // Arduino connector namings
     A0          = PA_0,
     A1          = PA_1,
@@ -154,6 +158,7 @@
     LED2        = PA_5,
     LED3        = PA_5,
     LED4        = PA_5,
+    LED_RED     = LED1,
     USER_BUTTON = PC_13,
     SERIAL_TX   = PA_2,
     SERIAL_RX   = PA_3,

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-#define LED_RED                 LED1
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/PeripheralPins.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/PeripheralPins.c	Fri Sep 16 16:24:25 2016 +0100
@@ -55,6 +55,9 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT)
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP)
     {NC,   NC,    0}
 };
 

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/PinNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -37,13 +37,13 @@
 #endif
 
 // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
 #define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
 #define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
 #define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x1F)
+#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
 #define STM_MODE_INPUT              (0)
 #define STM_MODE_OUTPUT_PP          (1)
 #define STM_MODE_OUTPUT_OD          (2)
@@ -124,6 +124,11 @@
     PH_0  = 0x70,
     PH_1  = 0x71,
 
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
     // Arduino connector namings
     A0          = PA_0,
     A1          = PA_1,
@@ -153,6 +158,7 @@
     LED2        = PA_5,
     LED3        = PA_5,
     LED4        = PA_5,
+    LED_RED     = LED1,
     USER_BUTTON = PC_13,
     SERIAL_TX   = PA_2,
     SERIAL_RX   = PA_3,

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-#define LED_RED                 LED1
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PeripheralPins.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PeripheralPins.c	Fri Sep 16 16:24:25 2016 +0100
@@ -55,6 +55,9 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT)
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP)
     {NC,   NC,    0}
 };
 

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PinNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -37,13 +37,13 @@
 #endif
 
 // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
 #define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
 #define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
 #define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x1F)
+#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
 #define STM_MODE_INPUT              (0)
 #define STM_MODE_OUTPUT_PP          (1)
 #define STM_MODE_OUTPUT_OD          (2)
@@ -124,6 +124,11 @@
     PH_0  = 0x70,
     PH_1  = 0x71,
 
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
     // Arduino connector namings
     A0          = PA_0,
     A1          = PA_1,
@@ -153,6 +158,7 @@
     LED2        = PA_5,
     LED3        = PA_5,
     LED4        = PA_5,
+    LED_RED     = LED1,
     USER_BUTTON = PC_13,
     SERIAL_TX   = PA_2,
     SERIAL_RX   = PA_3,

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-#define LED_RED                 LED1
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PeripheralPins.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PeripheralPins.c	Fri Sep 16 16:24:25 2016 +0100
@@ -87,6 +87,9 @@
     {PF_8,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6
     {PF_9,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7
     {PF_10,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - ARDUINO A5
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT)
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP)
     {NC,   NC,    0}
 };
 

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PinNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -37,22 +37,13 @@
 #endif
 
 // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((MODE  & 0x0F) << 0) |\
-                                                ((PUPD  & 0x07) << 4) |\
-                                                ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((MODE     & 0x0F) <<  0) |\
-                                                                       ((PUPD     & 0x07) <<  4) |\
-                                                                       ((AFNUM    & 0x0F) <<  7) |\
-                                                                       ((CHANNEL  & 0x0F) << 11) |\
-                                                                       ((INVERTED & 0x01) << 15)))
-
-#define STM_PIN_MODE(X)     (((X) >>  0) & 0x0F)
-#define STM_PIN_PUPD(X)     (((X) >>  4) & 0x07)
-#define STM_PIN_AFNUM(X)    (((X) >>  7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
-
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
+#define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
+#define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x1F)
+#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
 #define STM_MODE_INPUT              (0)
 #define STM_MODE_OUTPUT_PP          (1)
 #define STM_MODE_OUTPUT_OD          (2)
@@ -200,6 +191,11 @@
     PH_0  = 0x70,
     PH_1  = 0x71,
 
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
     // Arduino connector namings
     A0          = PA_3,
     A1          = PC_0,
@@ -229,6 +225,7 @@
     LED2        = PB_7,  // Blue
     LED3        = PB_14, // Red
     LED4        = PB_0,
+    LED_RED     = LED2,
     USER_BUTTON = PC_13,
     SERIAL_TX   = PD_8, // Virtual Com Port
     SERIAL_RX   = PD_9, // Virtual Com Port

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,55 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-#define LED_RED                 LED2
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PeripheralPins.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PeripheralPins.c	Fri Sep 16 16:24:25 2016 +0100
@@ -55,6 +55,9 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT)
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP)
     {NC,   NC,    0}
 };
 

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PinNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -37,13 +37,13 @@
 #endif
 
 // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
 #define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
 #define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
 #define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x1F)
+#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
 #define STM_MODE_INPUT              (0)
 #define STM_MODE_OUTPUT_PP          (1)
 #define STM_MODE_OUTPUT_OD          (2)
@@ -124,6 +124,11 @@
     PH_0  = 0x70,
     PH_1  = 0x71,
 
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
     // Arduino connector namings
     A0          = PA_0,
     A1          = PA_1,
@@ -153,6 +158,7 @@
     LED2        = PA_5,
     LED3        = PA_5,
     LED4        = PA_5,
+    LED_RED     = LED1,
     USER_BUTTON = PC_13,
     SERIAL_TX   = PA_2,
     SERIAL_RX   = PA_3,

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,55 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-#define LED_RED                 LED1
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/PeripheralPins.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/PeripheralPins.c	Fri Sep 16 16:24:25 2016 +0100
@@ -89,6 +89,9 @@
     {PF_8,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6
     {PF_9,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7
     //{PF_10,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - ARDUINO A5
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT)
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP)
     {NC,   NC,    0}
 };
 

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/PinNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -37,13 +37,13 @@
 #endif
 
 // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
 #define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
 #define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
 #define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x1F)
+#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
 #define STM_MODE_INPUT              (0)
 #define STM_MODE_OUTPUT_PP          (1)
 #define STM_MODE_OUTPUT_OD          (2)
@@ -192,6 +192,11 @@
     PH_1  = 0x71,
     PH_2  = 0x72,
 
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
     // Arduino connector namings
     A0          = PA_3,
     A1          = PC_0,
@@ -221,6 +226,7 @@
     LED2        = PB_7,
     LED3        = PB_14,
     LED4        = LED1,
+    LED_RED     = LED3,
     USER_BUTTON = PC_13,
     SERIAL_TX   = PD_8, // Virtual Com Port
     SERIAL_RX   = PD_9, // Virtual Com Port

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,41 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-#define LED_RED                 LED3
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -37,13 +37,13 @@
 #endif
 
 // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
 #define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
 #define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
 #define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x1F)
+#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
 #define STM_MODE_INPUT              (0)
 #define STM_MODE_OUTPUT_PP          (1)
 #define STM_MODE_OUTPUT_OD          (2)
@@ -109,6 +109,11 @@
     PH_8  = 0x78, PH_9  = 0x79, PH_10 = 0x7A, PH_11 = 0x7B,
     PH_12 = 0x7C, PH_13 = 0x7D, PH_14 = 0x7E, PH_15 = 0x7F,
 
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
     // Module Pins
     // A
     P_A5    = PC_2,   // UART-DTR

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F4/analogin_api.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/analogin_api.c	Fri Sep 16 16:24:25 2016 +0100
@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2015, STMicroelectronics
+ * Copyright (c) 2016, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -58,8 +58,10 @@
     MBED_ASSERT(function != (uint32_t)NC);
     obj->channel = STM_PIN_CHANNEL(function);
 
-    // Configure GPIO
-    pinmap_pinout(pin, PinMap_ADC);
+    // Configure GPIO excepted for internal channels (Temperature, Vref, Vbat)
+    if ((obj->channel != 16) && (obj->channel != 17) && (obj->channel != 18)) {
+        pinmap_pinout(pin, PinMap_ADC);
+    }
 
     // Save pin number for the read function
     obj->pin = pin;
@@ -101,6 +103,7 @@
     AdcHandle.Init.NbrOfConversion       = 1;
     AdcHandle.Init.DMAContinuousRequests = DISABLE;
     AdcHandle.Init.EOCSelection          = DISABLE;
+
     if (HAL_ADC_Init(&AdcHandle) != HAL_OK) {
         error("Cannot initialize ADC\n");
     }
@@ -114,7 +117,7 @@
 
     // Configure ADC channel
     sConfig.Rank         = 1;
-    sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
+    sConfig.SamplingTime = ADC_SAMPLETIME_15CYCLES;
     sConfig.Offset       = 0;
 
     switch (obj->channel) {
@@ -166,6 +169,15 @@
         case 15:
             sConfig.Channel = ADC_CHANNEL_15;
             break;
+        case 16:
+            sConfig.Channel = ADC_CHANNEL_16;
+            break;
+        case 17:
+            sConfig.Channel = ADC_CHANNEL_17;
+            break;
+        case 18:
+            sConfig.Channel = ADC_CHANNEL_18;
+            break;
         default:
             return 0;
     }

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/device.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,40 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+//=======================================
+#define DEVICE_ID_LENGTH       24
+
+#include "objects.h"
+
+#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PeripheralNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE,
+    ADC_2 = (int)ADC2_BASE,
+    ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+    DAC_1 = DAC_BASE
+} DACName;
+
+typedef enum {
+    UART_1 = (int)USART1_BASE,
+    UART_2 = (int)USART2_BASE,
+    UART_3 = (int)USART3_BASE,
+    UART_4 = (int)UART4_BASE,
+    UART_5 = (int)UART5_BASE,
+    UART_6 = (int)USART6_BASE,
+    UART_7 = (int)UART7_BASE,
+    UART_8 = (int)UART8_BASE
+} UARTName;
+
+#define STDIO_UART_TX  PA_9
+#define STDIO_UART_RX  PA_10
+#define STDIO_UART     UART_1
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE,
+    SPI_3 = (int)SPI3_BASE,
+    SPI_4 = (int)SPI4_BASE,
+    SPI_5 = (int)SPI5_BASE,
+    SPI_6 = (int)SPI6_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_2 = (int)I2C2_BASE,
+    I2C_3 = (int)I2C3_BASE,
+    I2C_4 = (int)I2C4_BASE
+} I2CName;
+
+typedef enum {
+    PWM_1  = (int)TIM1_BASE,
+    PWM_2  = (int)TIM2_BASE,
+    PWM_3  = (int)TIM3_BASE,
+    PWM_4  = (int)TIM4_BASE,
+    PWM_5  = (int)TIM5_BASE,
+    PWM_8  = (int)TIM8_BASE,
+    PWM_9  = (int)TIM9_BASE,
+    PWM_10 = (int)TIM10_BASE,
+    PWM_11 = (int)TIM11_BASE,
+    PWM_12 = (int)TIM12_BASE,
+    PWM_13 = (int)TIM13_BASE,
+    PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+    CAN_1 = (int)CAN1_BASE,
+    CAN_2 = (int)CAN2_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PeripheralPins.c	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,211 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =============================================================================
+// Notes:
+// * Commented lines are alternative possibilities which are not used per default.
+//   If you change them, you will have also to modify the corresponding xxx_api.c file
+//   for pwmout, analogin, analogout, ...
+// * Only the pins that are placed on the Arduino connector are described.
+// =============================================================================
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+ // {PA_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 - ARDUINO A1
+    {PA_4,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 - ARDUINO A1
+ // {PA_6,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 - ARDUINO A0
+    {PA_6,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 - ARDUINO A0
+    {PC_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,12, 0)}, // ADC1_IN12 - ARDUINO A2
+ // {PC_2,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,12, 0)}, // ADC2_IN12 - ARDUINO A2
+    {PF_6,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 - ARDUINO D3
+    {PF_7,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 - ARDUINO D6
+    {PF_8,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 - ARDUINO A4
+    {PF_9,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 - ARDUINO A5
+    {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - ARDUINO A3
+
+    {NC,    NC,    0}
+};
+
+//*** DAC ***
+
+const PinMap PinMap_DAC[] = {
+    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 1, 0)}, // DAC_OUT1 (ARDUINO A1)
+ // {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 2, 0)}, // DAC_OUT2 - used by USB3320C
+    {NC,   NC,    0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // used by Audio_SDA
+    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D14/SDA
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D14/SCL
+    {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, // used by Audio_SCL
+    {NC,    NC,    0}
+};
+
+//*** PWM ***
+
+const PinMap PinMap_PWM[] = {
+    {PA_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3,  1, 0)}, // TIM3_CH1  - ARDUINO A0
+ // {PA_6,  PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - ARDUINO A0
+    {PA_11, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  4, 0)}, // TIM1_CH4  - ARDUINO D10
+
+    {PB_8,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4,  3, 0)}, // TIM4_CH3  - ARDUINO D15
+ // {PB_8,  PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - ARDUINO D15
+    {PB_9,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4,  4, 0)}, // TIM4_CH4  - ARDUINO D14
+ // {PB_9,  PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - ARDUINO D14
+ // {PB_14, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  2, 1)}, // TIM1_CH2N - ARDUINO D12
+ // {PB_14, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8,  2, 1)}, // TIM8_CH2N - ARDUINO D12
+    {PB_14, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 - ARDUINO D12
+ // {PB_15, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1,  3, 1)}, // TIM1_CH3N - ARDUINO D11
+ // {PB_15, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8,  3, 1)}, // TIM8_CH3N - ARDUINO D11
+    {PB_15, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 - ARDUINO D11
+
+    {PC_6,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8,  1, 0)}, // TIM8_CH1  - ARDUINO D1
+ // {PC_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3,  1, 0)}, // TIM3_CH1  - ARDUINO D1
+    {PC_7,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8,  2, 0)}, // TIM8_CH2  - ARDUINO D0
+ // {PC_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3,  2, 0)}, // TIM3_CH2  - ARDUINO D0
+    {PC_8,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3,  3, 0)}, // TIM3_CH3  - ARDUINO D5
+ // {PC_8,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8,  3, 0)}, // TIM8_CH3  - ARDUINO D5
+
+    {PF_6,  PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - ARDUINO D3
+    {PF_7,  PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - ARDUINO D6
+    {PF_8,  PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - ARDUINO A4
+    {PF_9,  PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - ARDUINO A5
+
+    {PH_6,  PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 - ARDUINO D9
+    {NC,    NC,    0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+    {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by stlink usb)
+ // {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4 )}, // ARDUINO D13 - remove SB15 to use it
+    {PB_9,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)},  // ARDUINO D14
+    {PB_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // ARDUINO D12
+    {PC_6,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // ARDUINO D1
+    {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5 )}, // WIFI_RX
+    {PF_7,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7 )}, // ARDUINO D6
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by st-link usb)
+    {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4 )}, // ARDUINO D10
+    {PB_8,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5 )}, // ARDUINO D15
+    {PB_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // ARDUINO D11
+    {PC_7,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // ARDUINO D0
+    {PD_2,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5 )}, // WIFI_TX
+    {PF_6,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7 )}, // ARDUINO D3
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1  )}, // ARDUINO D13
+    {PB_14, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4   )}, // ARDUINO D12
+ // {PB_14, USART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3 )}, // ARDUINO D12
+    {PC_8,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5   )}, // ARDUINO D5
+    {PF_8,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7   )}, // ARDUINO A4
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // ARDUINO D10
+    {PB_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4 )}, // ARDUINO D11
+    {PF_9,  UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7 )}, // ARDUINO A5
+    {NC,    NC,     0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO D11
+    {PD_6,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, // SD card
+    {PD_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // SD card
+    {PF_9,  SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // ARDUINO A5
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // ARDUINO A0
+ // {PA_6,  SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, // ARDUINO A0
+    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // SD card
+ // {PB_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // SD card
+ // {PB_4,  SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, // SD card
+    {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO D12
+    {PC_2,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO A2
+    {PF_8,  SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // ARDUINO A4
+    {PG_9,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // SD card
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+    {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO D13
+    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // SD card
+ // {PB_3,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ // {PB_3,  SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)},
+    {PF_7,  SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // ARDUINO D6
+    {PH_6,  SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // ARDUINO D9
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // ARDUINO A1
+ // {PA_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+    {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO D10
+    {PB_4,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)}, // SD card
+    {PB_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO D14
+    {PF_6,  SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // ARDUINO D3
+    {PG_10, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // SD card
+    {NC,    NC,    0}
+};
+
+//*** CAN ***
+
+const PinMap PinMap_CAN_RD[] = {
+    {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PB_8,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_CAN_TD[] = {
+    {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PB_9,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {NC,    NC,    0}
+};
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PinNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,317 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((MODE  & 0x0F) << 0) |\
+                                                ((PUPD  & 0x07) << 4) |\
+                                                ((AFNUM & 0x0F) << 7)))
+
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((MODE     & 0x0F) <<  0) |\
+                                                                       ((PUPD     & 0x07) <<  4) |\
+                                                                       ((AFNUM    & 0x0F) <<  7) |\
+                                                                       ((CHANNEL  & 0x0F) << 11) |\
+                                                                       ((INVERTED & 0x01) << 15)))
+
+#define STM_PIN_MODE(X)     (((X) >>  0) & 0x0F)
+#define STM_PIN_PUPD(X)     (((X) >>  4) & 0x07)
+#define STM_PIN_AFNUM(X)    (((X) >>  7) & 0x0F)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
+#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+
+#define STM_MODE_INPUT              (0)
+#define STM_MODE_OUTPUT_PP          (1)
+#define STM_MODE_OUTPUT_OD          (2)
+#define STM_MODE_AF_PP              (3)
+#define STM_MODE_AF_OD              (4)
+#define STM_MODE_ANALOG             (5)
+#define STM_MODE_IT_RISING          (6)
+#define STM_MODE_IT_FALLING         (7)
+#define STM_MODE_IT_RISING_FALLING  (8)
+#define STM_MODE_EVT_RISING         (9)
+#define STM_MODE_EVT_FALLING        (10)
+#define STM_MODE_EVT_RISING_FALLING (11)
+#define STM_MODE_IT_EVT_RESET       (12)
+
+// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H, 8=I, 9=J, A=K)
+// Low nibble  = pin number
+#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
+#define STM_PIN(X)  ((uint32_t)(X) & 0xF)
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+    PA_0  = 0x00,
+    PA_1  = 0x01,
+    PA_2  = 0x02,
+    PA_3  = 0x03,
+    PA_4  = 0x04,
+    PA_5  = 0x05,
+    PA_6  = 0x06,
+    PA_7  = 0x07,
+    PA_8  = 0x08,
+    PA_9  = 0x09,
+    PA_10 = 0x0A,
+    PA_11 = 0x0B,
+    PA_12 = 0x0C,
+    PA_13 = 0x0D,
+    PA_14 = 0x0E,
+    PA_15 = 0x0F,
+
+    PB_0  = 0x10,
+    PB_1  = 0x11,
+    PB_2  = 0x12,
+    PB_3  = 0x13,
+    PB_4  = 0x14,
+    PB_5  = 0x15,
+    PB_6  = 0x16,
+    PB_7  = 0x17,
+    PB_8  = 0x18,
+    PB_9  = 0x19,
+    PB_10 = 0x1A,
+    PB_11 = 0x1B,
+    PB_12 = 0x1C,
+    PB_13 = 0x1D,
+    PB_14 = 0x1E,
+    PB_15 = 0x1F,
+
+    PC_0  = 0x20,
+    PC_1  = 0x21,
+    PC_2  = 0x22,
+    PC_3  = 0x23,
+    PC_4  = 0x24,
+    PC_5  = 0x25,
+    PC_6  = 0x26,
+    PC_7  = 0x27,
+    PC_8  = 0x28,
+    PC_9  = 0x29,
+    PC_10 = 0x2A,
+    PC_11 = 0x2B,
+    PC_12 = 0x2C,
+    PC_13 = 0x2D,
+    PC_14 = 0x2E,
+    PC_15 = 0x2F,
+
+    PD_0  = 0x30,
+    PD_1  = 0x31,
+    PD_2  = 0x32,
+    PD_3  = 0x33,
+    PD_4  = 0x34,
+    PD_5  = 0x35,
+    PD_6  = 0x36,
+    PD_7  = 0x37,
+    PD_8  = 0x38,
+    PD_9  = 0x39,
+    PD_10 = 0x3A,
+    PD_11 = 0x3B,
+    PD_12 = 0x3C,
+    PD_13 = 0x3D,
+    PD_14 = 0x3E,
+    PD_15 = 0x3F,
+
+    PE_0  = 0x40,
+    PE_1  = 0x41,
+    PE_2  = 0x42,
+    PE_3  = 0x43,
+    PE_4  = 0x44,
+    PE_5  = 0x45,
+    PE_6  = 0x46,
+    PE_7  = 0x47,
+    PE_8  = 0x48,
+    PE_9  = 0x49,
+    PE_10 = 0x4A,
+    PE_11 = 0x4B,
+    PE_12 = 0x4C,
+    PE_13 = 0x4D,
+    PE_14 = 0x4E,
+    PE_15 = 0x4F,
+
+    PF_0  = 0x50,
+    PF_1  = 0x51,
+    PF_2  = 0x52,
+    PF_3  = 0x53,
+    PF_4  = 0x54,
+    PF_5  = 0x55,
+    PF_6  = 0x56,
+    PF_7  = 0x57,
+    PF_8  = 0x58,
+    PF_9  = 0x59,
+    PF_10 = 0x5A,
+    PF_11 = 0x5B,
+    PF_12 = 0x5C,
+    PF_13 = 0x5D,
+    PF_14 = 0x5E,
+    PF_15 = 0x5F,
+
+    PG_0  = 0x60,
+    PG_1  = 0x61,
+    PG_2  = 0x62,
+    PG_3  = 0x63,
+    PG_4  = 0x64,
+    PG_5  = 0x65,
+    PG_6  = 0x66,
+    PG_7  = 0x67,
+    PG_8  = 0x68,
+    PG_9  = 0x69,
+    PG_10 = 0x6A,
+    PG_11 = 0x6B,
+    PG_12 = 0x6C,
+    PG_13 = 0x6D,
+    PG_14 = 0x6E,
+    PG_15 = 0x6F,
+
+    PH_0  = 0x70,
+    PH_1  = 0x71,
+    PH_2  = 0x72,
+    PH_3  = 0x73,
+    PH_4  = 0x74,
+    PH_5  = 0x75,
+    PH_6  = 0x76,
+    PH_7  = 0x77,
+    PH_8  = 0x78,
+    PH_9  = 0x79,
+    PH_10 = 0x7A,
+    PH_11 = 0x7B,
+    PH_12 = 0x7C,
+    PH_13 = 0x7D,
+    PH_14 = 0x7E,
+    PH_15 = 0x7F,
+
+    PI_0  = 0x80,
+    PI_1  = 0x81,
+    PI_2  = 0x82,
+    PI_3  = 0x83,
+    PI_4  = 0x84,
+    PI_5  = 0x85,
+    PI_6  = 0x86,
+    PI_7  = 0x87,
+    PI_8  = 0x88,
+    PI_9  = 0x89,
+    PI_10 = 0x8A,
+    PI_11 = 0x8B,
+    PI_12 = 0x8C,
+    PI_13 = 0x8D,
+    PI_14 = 0x8E,
+    PI_15 = 0x8F,
+
+    PJ_0  = 0x90,
+    PJ_1  = 0x91,
+    PJ_2  = 0x92,
+    PJ_3  = 0x93,
+    PJ_4  = 0x94,
+    PJ_5  = 0x95,
+    PJ_6  = 0x96,
+    PJ_7  = 0x97,
+    PJ_8  = 0x98,
+    PJ_9  = 0x99,
+    PJ_10 = 0x9A,
+    PJ_11 = 0x9B,
+    PJ_12 = 0x9C,
+    PJ_13 = 0x9D,
+    PJ_14 = 0x9E,
+    PJ_15 = 0x9F,
+
+    PK_0  = 0xA0,
+    PK_1  = 0xA1,
+    PK_2  = 0xA2,
+    PK_3  = 0xA3,
+    PK_4  = 0xA4,
+    PK_5  = 0xA5,
+    PK_6  = 0xA6,
+    PK_7  = 0xA7,
+
+    // Arduino connector namings
+    A0          = PA_6,
+    A1          = PA_4,
+    A2          = PC_2,
+    A3          = PF_10,
+    A4          = PF_8,
+    A5          = PF_9,
+    D0          = PC_7,
+    D1          = PC_6,
+    D2          = PJ_1,
+    D3          = PF_6,
+    D4          = PJ_0,
+    D5          = PC_8,
+    D6          = PF_7,
+    D7          = PJ_3,
+    D8          = PJ_4,
+    D9          = PH_6,
+    D10         = PA_11,
+    D11         = PB_15,
+    D12         = PB_14,
+    D13         = PA_12,
+    D14         = PB_9,
+    D15         = PB_8,
+
+    // Generic signals namings
+    LED1        = PJ_13, // LD1 = RED
+    LED2        = PJ_5,  // LD2 = GREEN
+    LED3        = PA_12, // LD3 = GREEN
+    LED4        = PJ_13,
+    USER_BUTTON = PA_0,
+    SERIAL_TX   = PA_9,  // Virtual Com Port
+    SERIAL_RX   = PA_10, // Virtual Com Port
+    USBTX       = PA_9,  // Virtual Com Port
+    USBRX       = PA_10, // Virtual Com Port
+    I2C_SCL     = D15,
+    I2C_SDA     = D14,
+    SPI_MOSI    = D11,
+    SPI_MISO    = D12,
+    SPI_SCK     = D13,
+    SPI_CS      = D10,
+    PWM_OUT     = D9,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullNone  = 0,
+    PullUp    = 1,
+    PullDown  = 2,
+    OpenDrain = 3,
+    PullDefault = PullNone
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PortNames.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PortA = 0,
+    PortB = 1,
+    PortC = 2,
+    PortD = 3,
+    PortE = 4,
+    PortF = 5,
+    PortG = 6,
+    PortH = 7,
+    PortI = 8, // kept for compilation
+    PortJ = 9, // kept for compilation
+    PortK = 10 // kept for compilation
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,54 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+
+
+
+
+
+
+
+
+
+
+//=======================================
+
+#define DEVICE_ID_LENGTH       24
+
+
+
+
+#include "objects.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/objects.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,116 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    IRQn_Type irq_n;
+    uint32_t irq_index;
+    uint32_t event;
+    PinName pin;
+};
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+    PinDirection direction;
+    __IO uint32_t *reg_in;
+    __IO uint32_t *reg_out;
+};
+
+struct analogin_s {
+    ADCName adc;
+    PinName pin;
+    uint8_t channel;
+};
+
+struct dac_s {
+    DACName dac;
+    PinName pin;
+    uint32_t channel;
+};
+
+struct serial_s {
+    UARTName uart;
+    int index; // Used by irq
+    uint32_t baudrate;
+    uint32_t databits;
+    uint32_t stopbits;
+    uint32_t parity;
+    PinName pin_tx;
+    PinName pin_rx;
+#if DEVICE_SERIAL_FC
+    uint32_t hw_flow_ctl;
+    PinName pin_rts;
+    PinName pin_cts;
+#endif
+};
+
+struct spi_s {
+    SPIName spi;
+    uint32_t bits;
+    uint32_t cpol;
+    uint32_t cpha;
+    uint32_t mode;
+    uint32_t nss;
+    uint32_t br_presc;
+    PinName pin_miso;
+    PinName pin_mosi;
+    PinName pin_sclk;
+    PinName pin_ssel;
+};
+
+struct i2c_s {
+    I2CName  i2c;
+    uint32_t slave;
+};
+
+struct can_s {
+    CANName can;
+    int index;
+};
+
+#include "gpio_object.h"
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,72 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-#define DEVICE_PORTIN           1
-#define DEVICE_PORTOUT          1
-#define DEVICE_PORTINOUT        1
-
-#define DEVICE_INTERRUPTIN      1
-
-#define DEVICE_ANALOGIN         1
-#define DEVICE_ANALOGOUT        1
-
-#define DEVICE_SERIAL           1
-#define DEVICE_SERIAL_FC        0
-
-#define DEVICE_I2C              1
-#define DEVICE_I2CSLAVE         1
-
-#define DEVICE_SPI              1
-#define DEVICE_SPISLAVE         1
-
-#define DEVICE_RTC              1
-#define DEVICE_RTC_LSI          0
-
-#define DEVICE_PWMOUT           1
-
-#define DEVICE_SLEEP            1
-
-//=======================================
-
-#define DEVICE_SEMIHOST         0
-#define DEVICE_LOCALFILESYSTEM  0
-#define DEVICE_ID_LENGTH       24
-
-#define DEVICE_DEBUG_AWARENESS  0
-
-#define DEVICE_STDIO_MESSAGES   1
-
-#define DEVICE_ERROR_RED        0
-
-#include "objects.h"
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F7/device.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,40 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+//=======================================
+#define DEVICE_ID_LENGTH       24
+
+#include "objects.h"
+
+#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32L0/device.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,40 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+//=======================================
+#define DEVICE_ID_LENGTH       24
+
+#include "objects.h"
+
+#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,62 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-//MODTRONIX BEGIN - mbed Defines //////////////////////////////////////////////
-//Provide place for adding mbed defines. Alternative to adding them in IDE project properties.
-//Add project defines here, or add them to your toolchain compiler preprocessor
-
-
-//MODTRONIX END ///////////////////////////////////////////////////////////////
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32L1/device.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,40 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+//=======================================
+#define DEVICE_ID_LENGTH       24
+
+#include "objects.h"
+
+#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/PeripheralPins.c	Thu Sep 08 15:05:30 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/PeripheralPins.c	Fri Sep 16 16:24:25 2016 +0100
@@ -192,6 +192,35 @@
     {NC,    NC,     0}
 };
 
+const PinMap PinMap_UART_RTS[] = {
+    {PA_1,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PB_1,  UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_14, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PD_12, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PA_12, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PA_15, UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PD_2,  UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PD_4,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PB_3,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_4,  UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {NC,    NC,       0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    {PA_0,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_6,  UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+//  {PB_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_13, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PD_11, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PA_11, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PD_3,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PB_4,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_5,  UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {PB_7,  UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {NC,    NC,       0}
+};
+
 //*** SPI ***
 
 const PinMap PinMap_SPI_MOSI[] = {

--- a/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device.h	Thu Sep 08 15:05:30 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32L4/device.h	Fri Sep 16 16:24:25 2016 +0100
@@ -0,0 +1,40 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+//=======================================
+#define DEVICE_ID_LENGTH       24
+
+#include "objects.h"
+
+#endif