Kenji Arai
Debug tools / show registers, memory and system clock data
Target mbed board
LPC1768
LPC1114FN28
ST Nucleo L152RE
ST NUcleo F401RE
ST Nucleo F411RE
Command structure
Top
1 - goto step1 -> no connection all pins
2 - goto step2 -> connects pin_x and pin_y (not impliment yet)
t - Check and set RTC
x - Goto HW monitor
q - Return to main
>1
l - Check LED
b - Check button
s - CPU system info & clock
o - CPU clock output (Bug fix, port_mco1_mco2_set() function. Thanks Topi Makinen on April 25th, 2015)
>x(Hardware level monitor)
m - Entry Memory Mode
m>? -> Aditinal functions can see by ?
r - Entry Register Mode
r>? -> Aditinal functions can see by ?
s - System Clock -> sf, System / CPU information -> sc
q - Quit (back to called routine)
p - Entry Port Mode
p>? -> Aditinal functions can see by ?
Usage
Please modify "mon_hw_config.h" file for your purpose.
Especially LPC114FN28 has small memory, you cannot run your own program together with this program.
You don't need any additional HW. Just connect with PC via terminal software.
CAUTION
Due to several CPU's and short development time, I cannot grantee the quality level and several functions are not available yet.
If you found the bug, please let me know. Thanks in advance.
Revision 4:02980a730cfb, committed 2015-04-26
- Comitter:
- kenjiArai
- Date:
- Sun Apr 26 09:31:58 2015 +0000
- Parent:
- 3:455df34f7285
- Commit message:
- Set output port PA8 & PC9 high speed mode
Changed in this revision
| debug_tools/mon_hw_STM32.cpp | Show annotated file Show diff for this revision Revisions of this file |
diff -r 455df34f7285 -r 02980a730cfb debug_tools/mon_hw_STM32.cpp
--- a/debug_tools/mon_hw_STM32.cpp Sat Apr 25 04:23:59 2015 +0000
+++ b/debug_tools/mon_hw_STM32.cpp Sun Apr 26 09:31:58 2015 +0000
@@ -11,6 +11,7 @@
* Spareted: June 25th, 2014 mon() & mon_hw()
* restart: July 12th, 2014
* Revised: April 25th, 2015 Bug fix ('o' command) pointed out by Topi Makinen
+ * Revised: April 26th, 2015 Change Port output speed (set High speed)
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
* INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
@@ -38,7 +39,7 @@
uint32_t SystemFrequency;
uint8_t quitflag;
-uint32_t reg_save0, reg_save1, reg_save2, reg_save3, reg_save4;
+uint32_t reg_save0, reg_save1, reg_save2, reg_save3, reg_save4, reg_save5, reg_save6;
// ROM / Constant data ---------------------------------------------------------------------------
#if defined(TARGET_NUCLEO_F401RE)
@@ -532,10 +533,12 @@
GPIOx = GPIOA;
reg_save0 = GPIOx->AFR[8 >> 3];
reg_save1 = GPIOx->MODER;
+ reg_save2 = GPIOx->OSPEEDR;
GPIOx = GPIOC;
- reg_save2 = GPIOx->AFR[9 >> 3];
- reg_save3 = GPIOx->MODER;
- reg_save4 = RCC->CFGR;
+ reg_save3 = GPIOx->AFR[9 >> 3];
+ reg_save4 = GPIOx->MODER;
+ reg_save5 = GPIOx->OSPEEDR;
+ reg_save6 = RCC->CFGR;
} else {
// PA8 -> MCO_1
GPIOx = GPIOA;
@@ -544,6 +547,7 @@
GPIOx->AFR[8 >> 3] |= temp;
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (8 * 2));
GPIOx->MODER |= (0x2 << (8 * 2));
+ GPIOx->OSPEEDR |= (0x03 << (8 * 2)); // High speed
// PC9 -> MCO_2
GPIOx = GPIOC;
temp = ((uint32_t)(GPIO_AF0_MCO) << (((uint32_t)9 & (uint32_t)0x07) * 4)) ;
@@ -551,6 +555,7 @@
GPIOx->AFR[9 >> 3] |= temp;
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (9 * 2));
GPIOx->MODER |= (0x2 << (9 * 2));
+ GPIOx->OSPEEDR |= (0x03 << (9 * 2)); // High speed
// Select output clock source
RCC->CFGR &= 0x009fffff;
if (n == 1){
@@ -573,12 +578,14 @@
GPIOx = GPIOA;
GPIOx->AFR[8 >> 3] = reg_save0;
GPIOx->MODER = reg_save1;
+ GPIOx->OSPEEDR = reg_save2;
// PC9 -> MCO_2
GPIOx = GPIOC;
- GPIOx->AFR[9 >> 3] = reg_save2;
- GPIOx->MODER = reg_save3;
+ GPIOx->AFR[9 >> 3] = reg_save3;
+ GPIOx->MODER = reg_save4;
+ GPIOx->OSPEEDR = reg_save5;
// MC0_1 & MCO_2
- RCC->CFGR = reg_save4;
+ RCC->CFGR = reg_save6;
}
#endif // defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE)