TYBLE16_mbedlized_os5_several_examples_1st

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Kenji Arai / TYBLE16_mbedlized_os5_several_examples_1st

Dependencies: nRF51_Vdd TextLCD BME280

TYBLE16_os5_BASE/cmsis/TARGET_CORTEX_M/core_cm23.h@6:6dd8c932bd56, 2019-12-19 (annotated)

Committer:: kenjiArai
Date:: Thu Dec 19 07:27:50 2019 +0000
Revision:: 6:6dd8c932bd56
Parent:: 4:e9dfb4ca4277

updated each main.cpp

Who changed what in which revision?

User	Revision	Line number	New contents of line
kenjiArai	4:e9dfb4ca4277	1	/************************************************************************//
kenjiArai	4:e9dfb4ca4277	2	* @file core_cm23.h
kenjiArai	4:e9dfb4ca4277	3	* @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
kenjiArai	4:e9dfb4ca4277	4	* @version V5.0.7
kenjiArai	4:e9dfb4ca4277	5	* @date 22. June 2018
kenjiArai	4:e9dfb4ca4277	6	******************************************************************************/
kenjiArai	4:e9dfb4ca4277	7	/*
kenjiArai	4:e9dfb4ca4277	8	* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
kenjiArai	4:e9dfb4ca4277	9	*
kenjiArai	4:e9dfb4ca4277	10	* SPDX-License-Identifier: Apache-2.0
kenjiArai	4:e9dfb4ca4277	11	*
kenjiArai	4:e9dfb4ca4277	12	* Licensed under the Apache License, Version 2.0 (the License); you may
kenjiArai	4:e9dfb4ca4277	13	* not use this file except in compliance with the License.
kenjiArai	4:e9dfb4ca4277	14	* You may obtain a copy of the License at
kenjiArai	4:e9dfb4ca4277	15	*
kenjiArai	4:e9dfb4ca4277	16	* www.apache.org/licenses/LICENSE-2.0
kenjiArai	4:e9dfb4ca4277	17	*
kenjiArai	4:e9dfb4ca4277	18	* Unless required by applicable law or agreed to in writing, software
kenjiArai	4:e9dfb4ca4277	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
kenjiArai	4:e9dfb4ca4277	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kenjiArai	4:e9dfb4ca4277	21	* See the License for the specific language governing permissions and
kenjiArai	4:e9dfb4ca4277	22	* limitations under the License.
kenjiArai	4:e9dfb4ca4277	23	*/
kenjiArai	4:e9dfb4ca4277	24
kenjiArai	4:e9dfb4ca4277	25	#if defined ( __ICCARM__ )
kenjiArai	4:e9dfb4ca4277	26	#pragma system_include /* treat file as system include file for MISRA check */
kenjiArai	4:e9dfb4ca4277	27	#elif defined (__clang__)
kenjiArai	4:e9dfb4ca4277	28	#pragma clang system_header /* treat file as system include file */
kenjiArai	4:e9dfb4ca4277	29	#endif
kenjiArai	4:e9dfb4ca4277	30
kenjiArai	4:e9dfb4ca4277	31	#ifndef __CORE_CM23_H_GENERIC
kenjiArai	4:e9dfb4ca4277	32	#define __CORE_CM23_H_GENERIC
kenjiArai	4:e9dfb4ca4277	33
kenjiArai	4:e9dfb4ca4277	34	#include <stdint.h>
kenjiArai	4:e9dfb4ca4277	35
kenjiArai	4:e9dfb4ca4277	36	#ifdef __cplusplus
kenjiArai	4:e9dfb4ca4277	37	extern "C" {
kenjiArai	4:e9dfb4ca4277	38	#endif
kenjiArai	4:e9dfb4ca4277	39
kenjiArai	4:e9dfb4ca4277	40	/**
kenjiArai	4:e9dfb4ca4277	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
kenjiArai	4:e9dfb4ca4277	42	CMSIS violates the following MISRA-C:2004 rules:
kenjiArai	4:e9dfb4ca4277	43
kenjiArai	4:e9dfb4ca4277	44	\li Required Rule 8.5, object/function definition in header file.<br>
kenjiArai	4:e9dfb4ca4277	45	Function definitions in header files are used to allow 'inlining'.
kenjiArai	4:e9dfb4ca4277	46
kenjiArai	4:e9dfb4ca4277	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
kenjiArai	4:e9dfb4ca4277	48	Unions are used for effective representation of core registers.
kenjiArai	4:e9dfb4ca4277	49
kenjiArai	4:e9dfb4ca4277	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
kenjiArai	4:e9dfb4ca4277	51	Function-like macros are used to allow more efficient code.
kenjiArai	4:e9dfb4ca4277	52	*/
kenjiArai	4:e9dfb4ca4277	53
kenjiArai	4:e9dfb4ca4277	54
kenjiArai	4:e9dfb4ca4277	55	/*******************************************************************************
kenjiArai	4:e9dfb4ca4277	56	* CMSIS definitions
kenjiArai	4:e9dfb4ca4277	57	******************************************************************************/
kenjiArai	4:e9dfb4ca4277	58	/**
kenjiArai	4:e9dfb4ca4277	59	\ingroup Cortex_M23
kenjiArai	4:e9dfb4ca4277	60	@{
kenjiArai	4:e9dfb4ca4277	61	*/
kenjiArai	4:e9dfb4ca4277	62
kenjiArai	4:e9dfb4ca4277	63	#include "cmsis_version.h"
kenjiArai	4:e9dfb4ca4277	64
kenjiArai	4:e9dfb4ca4277	65	/* CMSIS definitions */
kenjiArai	4:e9dfb4ca4277	66	#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
kenjiArai	4:e9dfb4ca4277	67	#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
kenjiArai	4:e9dfb4ca4277	68	#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) \| \
kenjiArai	4:e9dfb4ca4277	69	__CM23_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
kenjiArai	4:e9dfb4ca4277	70
kenjiArai	4:e9dfb4ca4277	71	#define __CORTEX_M (23U) /!< Cortex-M Core /
kenjiArai	4:e9dfb4ca4277	72
kenjiArai	4:e9dfb4ca4277	73	/** __FPU_USED indicates whether an FPU is used or not.
kenjiArai	4:e9dfb4ca4277	74	This core does not support an FPU at all
kenjiArai	4:e9dfb4ca4277	75	*/
kenjiArai	4:e9dfb4ca4277	76	#define __FPU_USED 0U
kenjiArai	4:e9dfb4ca4277	77
kenjiArai	4:e9dfb4ca4277	78	#if defined ( __CC_ARM )
kenjiArai	4:e9dfb4ca4277	79	#if defined __TARGET_FPU_VFP
kenjiArai	4:e9dfb4ca4277	80	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kenjiArai	4:e9dfb4ca4277	81	#endif
kenjiArai	4:e9dfb4ca4277	82
kenjiArai	4:e9dfb4ca4277	83	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
kenjiArai	4:e9dfb4ca4277	84	#if defined __ARM_PCS_VFP
kenjiArai	4:e9dfb4ca4277	85	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kenjiArai	4:e9dfb4ca4277	86	#endif
kenjiArai	4:e9dfb4ca4277	87
kenjiArai	4:e9dfb4ca4277	88	#elif defined ( __GNUC__ )
kenjiArai	4:e9dfb4ca4277	89	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
kenjiArai	4:e9dfb4ca4277	90	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kenjiArai	4:e9dfb4ca4277	91	#endif
kenjiArai	4:e9dfb4ca4277	92
kenjiArai	4:e9dfb4ca4277	93	#elif defined ( __ICCARM__ )
kenjiArai	4:e9dfb4ca4277	94	#if defined __ARMVFP__
kenjiArai	4:e9dfb4ca4277	95	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kenjiArai	4:e9dfb4ca4277	96	#endif
kenjiArai	4:e9dfb4ca4277	97
kenjiArai	4:e9dfb4ca4277	98	#elif defined ( __TI_ARM__ )
kenjiArai	4:e9dfb4ca4277	99	#if defined __TI_VFP_SUPPORT__
kenjiArai	4:e9dfb4ca4277	100	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kenjiArai	4:e9dfb4ca4277	101	#endif
kenjiArai	4:e9dfb4ca4277	102
kenjiArai	4:e9dfb4ca4277	103	#elif defined ( __TASKING__ )
kenjiArai	4:e9dfb4ca4277	104	#if defined __FPU_VFP__
kenjiArai	4:e9dfb4ca4277	105	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kenjiArai	4:e9dfb4ca4277	106	#endif
kenjiArai	4:e9dfb4ca4277	107
kenjiArai	4:e9dfb4ca4277	108	#elif defined ( __CSMC__ )
kenjiArai	4:e9dfb4ca4277	109	#if ( __CSMC__ & 0x400U)
kenjiArai	4:e9dfb4ca4277	110	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kenjiArai	4:e9dfb4ca4277	111	#endif
kenjiArai	4:e9dfb4ca4277	112
kenjiArai	4:e9dfb4ca4277	113	#endif
kenjiArai	4:e9dfb4ca4277	114
kenjiArai	4:e9dfb4ca4277	115	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
kenjiArai	4:e9dfb4ca4277	116
kenjiArai	4:e9dfb4ca4277	117
kenjiArai	4:e9dfb4ca4277	118	#ifdef __cplusplus
kenjiArai	4:e9dfb4ca4277	119	}
kenjiArai	4:e9dfb4ca4277	120	#endif
kenjiArai	4:e9dfb4ca4277	121
kenjiArai	4:e9dfb4ca4277	122	#endif /* __CORE_CM23_H_GENERIC */
kenjiArai	4:e9dfb4ca4277	123
kenjiArai	4:e9dfb4ca4277	124	#ifndef __CMSIS_GENERIC
kenjiArai	4:e9dfb4ca4277	125
kenjiArai	4:e9dfb4ca4277	126	#ifndef __CORE_CM23_H_DEPENDANT
kenjiArai	4:e9dfb4ca4277	127	#define __CORE_CM23_H_DEPENDANT
kenjiArai	4:e9dfb4ca4277	128
kenjiArai	4:e9dfb4ca4277	129	#ifdef __cplusplus
kenjiArai	4:e9dfb4ca4277	130	extern "C" {
kenjiArai	4:e9dfb4ca4277	131	#endif
kenjiArai	4:e9dfb4ca4277	132
kenjiArai	4:e9dfb4ca4277	133	/* check device defines and use defaults */
kenjiArai	4:e9dfb4ca4277	134	#if defined __CHECK_DEVICE_DEFINES
kenjiArai	4:e9dfb4ca4277	135	#ifndef __CM23_REV
kenjiArai	4:e9dfb4ca4277	136	#define __CM23_REV 0x0000U
kenjiArai	4:e9dfb4ca4277	137	#warning "__CM23_REV not defined in device header file; using default!"
kenjiArai	4:e9dfb4ca4277	138	#endif
kenjiArai	4:e9dfb4ca4277	139
kenjiArai	4:e9dfb4ca4277	140	#ifndef __FPU_PRESENT
kenjiArai	4:e9dfb4ca4277	141	#define __FPU_PRESENT 0U
kenjiArai	4:e9dfb4ca4277	142	#warning "__FPU_PRESENT not defined in device header file; using default!"
kenjiArai	4:e9dfb4ca4277	143	#endif
kenjiArai	4:e9dfb4ca4277	144
kenjiArai	4:e9dfb4ca4277	145	#ifndef __MPU_PRESENT
kenjiArai	4:e9dfb4ca4277	146	#define __MPU_PRESENT 0U
kenjiArai	4:e9dfb4ca4277	147	#warning "__MPU_PRESENT not defined in device header file; using default!"
kenjiArai	4:e9dfb4ca4277	148	#endif
kenjiArai	4:e9dfb4ca4277	149
kenjiArai	4:e9dfb4ca4277	150	#ifndef __SAUREGION_PRESENT
kenjiArai	4:e9dfb4ca4277	151	#define __SAUREGION_PRESENT 0U
kenjiArai	4:e9dfb4ca4277	152	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
kenjiArai	4:e9dfb4ca4277	153	#endif
kenjiArai	4:e9dfb4ca4277	154
kenjiArai	4:e9dfb4ca4277	155	#ifndef __VTOR_PRESENT
kenjiArai	4:e9dfb4ca4277	156	#define __VTOR_PRESENT 0U
kenjiArai	4:e9dfb4ca4277	157	#warning "__VTOR_PRESENT not defined in device header file; using default!"
kenjiArai	4:e9dfb4ca4277	158	#endif
kenjiArai	4:e9dfb4ca4277	159
kenjiArai	4:e9dfb4ca4277	160	#ifndef __NVIC_PRIO_BITS
kenjiArai	4:e9dfb4ca4277	161	#define __NVIC_PRIO_BITS 2U
kenjiArai	4:e9dfb4ca4277	162	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
kenjiArai	4:e9dfb4ca4277	163	#endif
kenjiArai	4:e9dfb4ca4277	164
kenjiArai	4:e9dfb4ca4277	165	#ifndef __Vendor_SysTickConfig
kenjiArai	4:e9dfb4ca4277	166	#define __Vendor_SysTickConfig 0U
kenjiArai	4:e9dfb4ca4277	167	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
kenjiArai	4:e9dfb4ca4277	168	#endif
kenjiArai	4:e9dfb4ca4277	169
kenjiArai	4:e9dfb4ca4277	170	#ifndef __ETM_PRESENT
kenjiArai	4:e9dfb4ca4277	171	#define __ETM_PRESENT 0U
kenjiArai	4:e9dfb4ca4277	172	#warning "__ETM_PRESENT not defined in device header file; using default!"
kenjiArai	4:e9dfb4ca4277	173	#endif
kenjiArai	4:e9dfb4ca4277	174
kenjiArai	4:e9dfb4ca4277	175	#ifndef __MTB_PRESENT
kenjiArai	4:e9dfb4ca4277	176	#define __MTB_PRESENT 0U
kenjiArai	4:e9dfb4ca4277	177	#warning "__MTB_PRESENT not defined in device header file; using default!"
kenjiArai	4:e9dfb4ca4277	178	#endif
kenjiArai	4:e9dfb4ca4277	179
kenjiArai	4:e9dfb4ca4277	180	#endif
kenjiArai	4:e9dfb4ca4277	181
kenjiArai	4:e9dfb4ca4277	182	/* IO definitions (access restrictions to peripheral registers) */
kenjiArai	4:e9dfb4ca4277	183	/**
kenjiArai	4:e9dfb4ca4277	184	\defgroup CMSIS_glob_defs CMSIS Global Defines
kenjiArai	4:e9dfb4ca4277	185
kenjiArai	4:e9dfb4ca4277	186	<strong>IO Type Qualifiers</strong> are used
kenjiArai	4:e9dfb4ca4277	187	\li to specify the access to peripheral variables.
kenjiArai	4:e9dfb4ca4277	188	\li for automatic generation of peripheral register debug information.
kenjiArai	4:e9dfb4ca4277	189	*/
kenjiArai	4:e9dfb4ca4277	190	#ifdef __cplusplus
kenjiArai	4:e9dfb4ca4277	191	#define __I volatile /!< Defines 'read only' permissions /
kenjiArai	4:e9dfb4ca4277	192	#else
kenjiArai	4:e9dfb4ca4277	193	#define __I volatile const /!< Defines 'read only' permissions /
kenjiArai	4:e9dfb4ca4277	194	#endif
kenjiArai	4:e9dfb4ca4277	195	#define __O volatile /!< Defines 'write only' permissions /
kenjiArai	4:e9dfb4ca4277	196	#define __IO volatile /!< Defines 'read / write' permissions /
kenjiArai	4:e9dfb4ca4277	197
kenjiArai	4:e9dfb4ca4277	198	/* following defines should be used for structure members */
kenjiArai	4:e9dfb4ca4277	199	#define __IM volatile const /! Defines 'read only' structure member permissions /
kenjiArai	4:e9dfb4ca4277	200	#define __OM volatile /! Defines 'write only' structure member permissions /
kenjiArai	4:e9dfb4ca4277	201	#define __IOM volatile /! Defines 'read / write' structure member permissions /
kenjiArai	4:e9dfb4ca4277	202
kenjiArai	4:e9dfb4ca4277	203	/@} end of group Cortex_M23 /
kenjiArai	4:e9dfb4ca4277	204
kenjiArai	4:e9dfb4ca4277	205
kenjiArai	4:e9dfb4ca4277	206
kenjiArai	4:e9dfb4ca4277	207	/*******************************************************************************
kenjiArai	4:e9dfb4ca4277	208	* Register Abstraction
kenjiArai	4:e9dfb4ca4277	209	Core Register contain:
kenjiArai	4:e9dfb4ca4277	210	- Core Register
kenjiArai	4:e9dfb4ca4277	211	- Core NVIC Register
kenjiArai	4:e9dfb4ca4277	212	- Core SCB Register
kenjiArai	4:e9dfb4ca4277	213	- Core SysTick Register
kenjiArai	4:e9dfb4ca4277	214	- Core Debug Register
kenjiArai	4:e9dfb4ca4277	215	- Core MPU Register
kenjiArai	4:e9dfb4ca4277	216	- Core SAU Register
kenjiArai	4:e9dfb4ca4277	217	******************************************************************************/
kenjiArai	4:e9dfb4ca4277	218	/**
kenjiArai	4:e9dfb4ca4277	219	\defgroup CMSIS_core_register Defines and Type Definitions
kenjiArai	4:e9dfb4ca4277	220	\brief Type definitions and defines for Cortex-M processor based devices.
kenjiArai	4:e9dfb4ca4277	221	*/
kenjiArai	4:e9dfb4ca4277	222
kenjiArai	4:e9dfb4ca4277	223	/**
kenjiArai	4:e9dfb4ca4277	224	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	225	\defgroup CMSIS_CORE Status and Control Registers
kenjiArai	4:e9dfb4ca4277	226	\brief Core Register type definitions.
kenjiArai	4:e9dfb4ca4277	227	@{
kenjiArai	4:e9dfb4ca4277	228	*/
kenjiArai	4:e9dfb4ca4277	229
kenjiArai	4:e9dfb4ca4277	230	/**
kenjiArai	4:e9dfb4ca4277	231	\brief Union type to access the Application Program Status Register (APSR).
kenjiArai	4:e9dfb4ca4277	232	*/
kenjiArai	4:e9dfb4ca4277	233	typedef union
kenjiArai	4:e9dfb4ca4277	234	{
kenjiArai	4:e9dfb4ca4277	235	struct
kenjiArai	4:e9dfb4ca4277	236	{
kenjiArai	4:e9dfb4ca4277	237	uint32_t _reserved0:28; /!< bit: 0..27 Reserved /
kenjiArai	4:e9dfb4ca4277	238	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
kenjiArai	4:e9dfb4ca4277	239	uint32_t C:1; /!< bit: 29 Carry condition code flag /
kenjiArai	4:e9dfb4ca4277	240	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
kenjiArai	4:e9dfb4ca4277	241	uint32_t N:1; /!< bit: 31 Negative condition code flag /
kenjiArai	4:e9dfb4ca4277	242	} b; /!< Structure used for bit access /
kenjiArai	4:e9dfb4ca4277	243	uint32_t w; /!< Type used for word access /
kenjiArai	4:e9dfb4ca4277	244	} APSR_Type;
kenjiArai	4:e9dfb4ca4277	245
kenjiArai	4:e9dfb4ca4277	246	/* APSR Register Definitions */
kenjiArai	4:e9dfb4ca4277	247	#define APSR_N_Pos 31U /!< APSR: N Position /
kenjiArai	4:e9dfb4ca4277	248	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
kenjiArai	4:e9dfb4ca4277	249
kenjiArai	4:e9dfb4ca4277	250	#define APSR_Z_Pos 30U /!< APSR: Z Position /
kenjiArai	4:e9dfb4ca4277	251	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
kenjiArai	4:e9dfb4ca4277	252
kenjiArai	4:e9dfb4ca4277	253	#define APSR_C_Pos 29U /!< APSR: C Position /
kenjiArai	4:e9dfb4ca4277	254	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
kenjiArai	4:e9dfb4ca4277	255
kenjiArai	4:e9dfb4ca4277	256	#define APSR_V_Pos 28U /!< APSR: V Position /
kenjiArai	4:e9dfb4ca4277	257	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
kenjiArai	4:e9dfb4ca4277	258
kenjiArai	4:e9dfb4ca4277	259
kenjiArai	4:e9dfb4ca4277	260	/**
kenjiArai	4:e9dfb4ca4277	261	\brief Union type to access the Interrupt Program Status Register (IPSR).
kenjiArai	4:e9dfb4ca4277	262	*/
kenjiArai	4:e9dfb4ca4277	263	typedef union
kenjiArai	4:e9dfb4ca4277	264	{
kenjiArai	4:e9dfb4ca4277	265	struct
kenjiArai	4:e9dfb4ca4277	266	{
kenjiArai	4:e9dfb4ca4277	267	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
kenjiArai	4:e9dfb4ca4277	268	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
kenjiArai	4:e9dfb4ca4277	269	} b; /!< Structure used for bit access /
kenjiArai	4:e9dfb4ca4277	270	uint32_t w; /!< Type used for word access /
kenjiArai	4:e9dfb4ca4277	271	} IPSR_Type;
kenjiArai	4:e9dfb4ca4277	272
kenjiArai	4:e9dfb4ca4277	273	/* IPSR Register Definitions */
kenjiArai	4:e9dfb4ca4277	274	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
kenjiArai	4:e9dfb4ca4277	275	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
kenjiArai	4:e9dfb4ca4277	276
kenjiArai	4:e9dfb4ca4277	277
kenjiArai	4:e9dfb4ca4277	278	/**
kenjiArai	4:e9dfb4ca4277	279	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
kenjiArai	4:e9dfb4ca4277	280	*/
kenjiArai	4:e9dfb4ca4277	281	typedef union
kenjiArai	4:e9dfb4ca4277	282	{
kenjiArai	4:e9dfb4ca4277	283	struct
kenjiArai	4:e9dfb4ca4277	284	{
kenjiArai	4:e9dfb4ca4277	285	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
kenjiArai	4:e9dfb4ca4277	286	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
kenjiArai	4:e9dfb4ca4277	287	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
kenjiArai	4:e9dfb4ca4277	288	uint32_t _reserved1:3; /!< bit: 25..27 Reserved /
kenjiArai	4:e9dfb4ca4277	289	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
kenjiArai	4:e9dfb4ca4277	290	uint32_t C:1; /!< bit: 29 Carry condition code flag /
kenjiArai	4:e9dfb4ca4277	291	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
kenjiArai	4:e9dfb4ca4277	292	uint32_t N:1; /!< bit: 31 Negative condition code flag /
kenjiArai	4:e9dfb4ca4277	293	} b; /!< Structure used for bit access /
kenjiArai	4:e9dfb4ca4277	294	uint32_t w; /!< Type used for word access /
kenjiArai	4:e9dfb4ca4277	295	} xPSR_Type;
kenjiArai	4:e9dfb4ca4277	296
kenjiArai	4:e9dfb4ca4277	297	/* xPSR Register Definitions */
kenjiArai	4:e9dfb4ca4277	298	#define xPSR_N_Pos 31U /!< xPSR: N Position /
kenjiArai	4:e9dfb4ca4277	299	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
kenjiArai	4:e9dfb4ca4277	300
kenjiArai	4:e9dfb4ca4277	301	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
kenjiArai	4:e9dfb4ca4277	302	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
kenjiArai	4:e9dfb4ca4277	303
kenjiArai	4:e9dfb4ca4277	304	#define xPSR_C_Pos 29U /!< xPSR: C Position /
kenjiArai	4:e9dfb4ca4277	305	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
kenjiArai	4:e9dfb4ca4277	306
kenjiArai	4:e9dfb4ca4277	307	#define xPSR_V_Pos 28U /!< xPSR: V Position /
kenjiArai	4:e9dfb4ca4277	308	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
kenjiArai	4:e9dfb4ca4277	309
kenjiArai	4:e9dfb4ca4277	310	#define xPSR_T_Pos 24U /!< xPSR: T Position /
kenjiArai	4:e9dfb4ca4277	311	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
kenjiArai	4:e9dfb4ca4277	312
kenjiArai	4:e9dfb4ca4277	313	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
kenjiArai	4:e9dfb4ca4277	314	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
kenjiArai	4:e9dfb4ca4277	315
kenjiArai	4:e9dfb4ca4277	316
kenjiArai	4:e9dfb4ca4277	317	/**
kenjiArai	4:e9dfb4ca4277	318	\brief Union type to access the Control Registers (CONTROL).
kenjiArai	4:e9dfb4ca4277	319	*/
kenjiArai	4:e9dfb4ca4277	320	typedef union
kenjiArai	4:e9dfb4ca4277	321	{
kenjiArai	4:e9dfb4ca4277	322	struct
kenjiArai	4:e9dfb4ca4277	323	{
kenjiArai	4:e9dfb4ca4277	324	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
kenjiArai	4:e9dfb4ca4277	325	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
kenjiArai	4:e9dfb4ca4277	326	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
kenjiArai	4:e9dfb4ca4277	327	} b; /!< Structure used for bit access /
kenjiArai	4:e9dfb4ca4277	328	uint32_t w; /!< Type used for word access /
kenjiArai	4:e9dfb4ca4277	329	} CONTROL_Type;
kenjiArai	4:e9dfb4ca4277	330
kenjiArai	4:e9dfb4ca4277	331	/* CONTROL Register Definitions */
kenjiArai	4:e9dfb4ca4277	332	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
kenjiArai	4:e9dfb4ca4277	333	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
kenjiArai	4:e9dfb4ca4277	334
kenjiArai	4:e9dfb4ca4277	335	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
kenjiArai	4:e9dfb4ca4277	336	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
kenjiArai	4:e9dfb4ca4277	337
kenjiArai	4:e9dfb4ca4277	338	/@} end of group CMSIS_CORE /
kenjiArai	4:e9dfb4ca4277	339
kenjiArai	4:e9dfb4ca4277	340
kenjiArai	4:e9dfb4ca4277	341	/**
kenjiArai	4:e9dfb4ca4277	342	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	343	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
kenjiArai	4:e9dfb4ca4277	344	\brief Type definitions for the NVIC Registers
kenjiArai	4:e9dfb4ca4277	345	@{
kenjiArai	4:e9dfb4ca4277	346	*/
kenjiArai	4:e9dfb4ca4277	347
kenjiArai	4:e9dfb4ca4277	348	/**
kenjiArai	4:e9dfb4ca4277	349	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
kenjiArai	4:e9dfb4ca4277	350	*/
kenjiArai	4:e9dfb4ca4277	351	typedef struct
kenjiArai	4:e9dfb4ca4277	352	{
kenjiArai	4:e9dfb4ca4277	353	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
kenjiArai	4:e9dfb4ca4277	354	uint32_t RESERVED0[16U];
kenjiArai	4:e9dfb4ca4277	355	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
kenjiArai	4:e9dfb4ca4277	356	uint32_t RSERVED1[16U];
kenjiArai	4:e9dfb4ca4277	357	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
kenjiArai	4:e9dfb4ca4277	358	uint32_t RESERVED2[16U];
kenjiArai	4:e9dfb4ca4277	359	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
kenjiArai	4:e9dfb4ca4277	360	uint32_t RESERVED3[16U];
kenjiArai	4:e9dfb4ca4277	361	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
kenjiArai	4:e9dfb4ca4277	362	uint32_t RESERVED4[16U];
kenjiArai	4:e9dfb4ca4277	363	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
kenjiArai	4:e9dfb4ca4277	364	uint32_t RESERVED5[16U];
kenjiArai	4:e9dfb4ca4277	365	__IOM uint32_t IPR[124U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register /
kenjiArai	4:e9dfb4ca4277	366	} NVIC_Type;
kenjiArai	4:e9dfb4ca4277	367
kenjiArai	4:e9dfb4ca4277	368	/@} end of group CMSIS_NVIC /
kenjiArai	4:e9dfb4ca4277	369
kenjiArai	4:e9dfb4ca4277	370
kenjiArai	4:e9dfb4ca4277	371	/**
kenjiArai	4:e9dfb4ca4277	372	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	373	\defgroup CMSIS_SCB System Control Block (SCB)
kenjiArai	4:e9dfb4ca4277	374	\brief Type definitions for the System Control Block Registers
kenjiArai	4:e9dfb4ca4277	375	@{
kenjiArai	4:e9dfb4ca4277	376	*/
kenjiArai	4:e9dfb4ca4277	377
kenjiArai	4:e9dfb4ca4277	378	/**
kenjiArai	4:e9dfb4ca4277	379	\brief Structure type to access the System Control Block (SCB).
kenjiArai	4:e9dfb4ca4277	380	*/
kenjiArai	4:e9dfb4ca4277	381	typedef struct
kenjiArai	4:e9dfb4ca4277	382	{
kenjiArai	4:e9dfb4ca4277	383	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
kenjiArai	4:e9dfb4ca4277	384	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
kenjiArai	4:e9dfb4ca4277	385	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	386	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
kenjiArai	4:e9dfb4ca4277	387	#else
kenjiArai	4:e9dfb4ca4277	388	uint32_t RESERVED0;
kenjiArai	4:e9dfb4ca4277	389	#endif
kenjiArai	4:e9dfb4ca4277	390	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
kenjiArai	4:e9dfb4ca4277	391	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
kenjiArai	4:e9dfb4ca4277	392	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
kenjiArai	4:e9dfb4ca4277	393	uint32_t RESERVED1;
kenjiArai	4:e9dfb4ca4277	394	__IOM uint32_t SHPR[2U]; /!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED /
kenjiArai	4:e9dfb4ca4277	395	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
kenjiArai	4:e9dfb4ca4277	396	} SCB_Type;
kenjiArai	4:e9dfb4ca4277	397
kenjiArai	4:e9dfb4ca4277	398	/* SCB CPUID Register Definitions */
kenjiArai	4:e9dfb4ca4277	399	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
kenjiArai	4:e9dfb4ca4277	400	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
kenjiArai	4:e9dfb4ca4277	401
kenjiArai	4:e9dfb4ca4277	402	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
kenjiArai	4:e9dfb4ca4277	403	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
kenjiArai	4:e9dfb4ca4277	404
kenjiArai	4:e9dfb4ca4277	405	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
kenjiArai	4:e9dfb4ca4277	406	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
kenjiArai	4:e9dfb4ca4277	407
kenjiArai	4:e9dfb4ca4277	408	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
kenjiArai	4:e9dfb4ca4277	409	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
kenjiArai	4:e9dfb4ca4277	410
kenjiArai	4:e9dfb4ca4277	411	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
kenjiArai	4:e9dfb4ca4277	412	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
kenjiArai	4:e9dfb4ca4277	413
kenjiArai	4:e9dfb4ca4277	414	/* SCB Interrupt Control State Register Definitions */
kenjiArai	4:e9dfb4ca4277	415	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
kenjiArai	4:e9dfb4ca4277	416	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
kenjiArai	4:e9dfb4ca4277	417
kenjiArai	4:e9dfb4ca4277	418	#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /!< SCB ICSR: NMIPENDSET Position, backward compatibility /
kenjiArai	4:e9dfb4ca4277	419	#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /!< SCB ICSR: NMIPENDSET Mask, backward compatibility /
kenjiArai	4:e9dfb4ca4277	420
kenjiArai	4:e9dfb4ca4277	421	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
kenjiArai	4:e9dfb4ca4277	422	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
kenjiArai	4:e9dfb4ca4277	423
kenjiArai	4:e9dfb4ca4277	424	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
kenjiArai	4:e9dfb4ca4277	425	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
kenjiArai	4:e9dfb4ca4277	426
kenjiArai	4:e9dfb4ca4277	427	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
kenjiArai	4:e9dfb4ca4277	428	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
kenjiArai	4:e9dfb4ca4277	429
kenjiArai	4:e9dfb4ca4277	430	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
kenjiArai	4:e9dfb4ca4277	431	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
kenjiArai	4:e9dfb4ca4277	432
kenjiArai	4:e9dfb4ca4277	433	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
kenjiArai	4:e9dfb4ca4277	434	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
kenjiArai	4:e9dfb4ca4277	435
kenjiArai	4:e9dfb4ca4277	436	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
kenjiArai	4:e9dfb4ca4277	437	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
kenjiArai	4:e9dfb4ca4277	438
kenjiArai	4:e9dfb4ca4277	439	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
kenjiArai	4:e9dfb4ca4277	440	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
kenjiArai	4:e9dfb4ca4277	441
kenjiArai	4:e9dfb4ca4277	442	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
kenjiArai	4:e9dfb4ca4277	443	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
kenjiArai	4:e9dfb4ca4277	444
kenjiArai	4:e9dfb4ca4277	445	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
kenjiArai	4:e9dfb4ca4277	446	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
kenjiArai	4:e9dfb4ca4277	447
kenjiArai	4:e9dfb4ca4277	448	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
kenjiArai	4:e9dfb4ca4277	449	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
kenjiArai	4:e9dfb4ca4277	450
kenjiArai	4:e9dfb4ca4277	451	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
kenjiArai	4:e9dfb4ca4277	452	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
kenjiArai	4:e9dfb4ca4277	453
kenjiArai	4:e9dfb4ca4277	454	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	455	/* SCB Vector Table Offset Register Definitions */
kenjiArai	4:e9dfb4ca4277	456	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
kenjiArai	4:e9dfb4ca4277	457	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
kenjiArai	4:e9dfb4ca4277	458	#endif
kenjiArai	4:e9dfb4ca4277	459
kenjiArai	4:e9dfb4ca4277	460	/* SCB Application Interrupt and Reset Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	461	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
kenjiArai	4:e9dfb4ca4277	462	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
kenjiArai	4:e9dfb4ca4277	463
kenjiArai	4:e9dfb4ca4277	464	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
kenjiArai	4:e9dfb4ca4277	465	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
kenjiArai	4:e9dfb4ca4277	466
kenjiArai	4:e9dfb4ca4277	467	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
kenjiArai	4:e9dfb4ca4277	468	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
kenjiArai	4:e9dfb4ca4277	469
kenjiArai	4:e9dfb4ca4277	470	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
kenjiArai	4:e9dfb4ca4277	471	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
kenjiArai	4:e9dfb4ca4277	472
kenjiArai	4:e9dfb4ca4277	473	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
kenjiArai	4:e9dfb4ca4277	474	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
kenjiArai	4:e9dfb4ca4277	475
kenjiArai	4:e9dfb4ca4277	476	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
kenjiArai	4:e9dfb4ca4277	477	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
kenjiArai	4:e9dfb4ca4277	478
kenjiArai	4:e9dfb4ca4277	479	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
kenjiArai	4:e9dfb4ca4277	480	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
kenjiArai	4:e9dfb4ca4277	481
kenjiArai	4:e9dfb4ca4277	482	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
kenjiArai	4:e9dfb4ca4277	483	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
kenjiArai	4:e9dfb4ca4277	484
kenjiArai	4:e9dfb4ca4277	485	/* SCB System Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	486	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
kenjiArai	4:e9dfb4ca4277	487	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
kenjiArai	4:e9dfb4ca4277	488
kenjiArai	4:e9dfb4ca4277	489	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
kenjiArai	4:e9dfb4ca4277	490	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
kenjiArai	4:e9dfb4ca4277	491
kenjiArai	4:e9dfb4ca4277	492	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
kenjiArai	4:e9dfb4ca4277	493	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
kenjiArai	4:e9dfb4ca4277	494
kenjiArai	4:e9dfb4ca4277	495	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
kenjiArai	4:e9dfb4ca4277	496	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
kenjiArai	4:e9dfb4ca4277	497
kenjiArai	4:e9dfb4ca4277	498	/* SCB Configuration Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	499	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
kenjiArai	4:e9dfb4ca4277	500	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
kenjiArai	4:e9dfb4ca4277	501
kenjiArai	4:e9dfb4ca4277	502	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
kenjiArai	4:e9dfb4ca4277	503	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
kenjiArai	4:e9dfb4ca4277	504
kenjiArai	4:e9dfb4ca4277	505	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
kenjiArai	4:e9dfb4ca4277	506	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
kenjiArai	4:e9dfb4ca4277	507
kenjiArai	4:e9dfb4ca4277	508	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
kenjiArai	4:e9dfb4ca4277	509	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
kenjiArai	4:e9dfb4ca4277	510
kenjiArai	4:e9dfb4ca4277	511	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
kenjiArai	4:e9dfb4ca4277	512	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
kenjiArai	4:e9dfb4ca4277	513
kenjiArai	4:e9dfb4ca4277	514	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
kenjiArai	4:e9dfb4ca4277	515	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
kenjiArai	4:e9dfb4ca4277	516
kenjiArai	4:e9dfb4ca4277	517	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
kenjiArai	4:e9dfb4ca4277	518	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
kenjiArai	4:e9dfb4ca4277	519
kenjiArai	4:e9dfb4ca4277	520	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
kenjiArai	4:e9dfb4ca4277	521	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
kenjiArai	4:e9dfb4ca4277	522
kenjiArai	4:e9dfb4ca4277	523	/* SCB System Handler Control and State Register Definitions */
kenjiArai	4:e9dfb4ca4277	524	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
kenjiArai	4:e9dfb4ca4277	525	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
kenjiArai	4:e9dfb4ca4277	526
kenjiArai	4:e9dfb4ca4277	527	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
kenjiArai	4:e9dfb4ca4277	528	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
kenjiArai	4:e9dfb4ca4277	529
kenjiArai	4:e9dfb4ca4277	530	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
kenjiArai	4:e9dfb4ca4277	531	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
kenjiArai	4:e9dfb4ca4277	532
kenjiArai	4:e9dfb4ca4277	533	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
kenjiArai	4:e9dfb4ca4277	534	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
kenjiArai	4:e9dfb4ca4277	535
kenjiArai	4:e9dfb4ca4277	536	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
kenjiArai	4:e9dfb4ca4277	537	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
kenjiArai	4:e9dfb4ca4277	538
kenjiArai	4:e9dfb4ca4277	539	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
kenjiArai	4:e9dfb4ca4277	540	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
kenjiArai	4:e9dfb4ca4277	541
kenjiArai	4:e9dfb4ca4277	542	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
kenjiArai	4:e9dfb4ca4277	543	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
kenjiArai	4:e9dfb4ca4277	544
kenjiArai	4:e9dfb4ca4277	545	/@} end of group CMSIS_SCB /
kenjiArai	4:e9dfb4ca4277	546
kenjiArai	4:e9dfb4ca4277	547
kenjiArai	4:e9dfb4ca4277	548	/**
kenjiArai	4:e9dfb4ca4277	549	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	550	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
kenjiArai	4:e9dfb4ca4277	551	\brief Type definitions for the System Timer Registers.
kenjiArai	4:e9dfb4ca4277	552	@{
kenjiArai	4:e9dfb4ca4277	553	*/
kenjiArai	4:e9dfb4ca4277	554
kenjiArai	4:e9dfb4ca4277	555	/**
kenjiArai	4:e9dfb4ca4277	556	\brief Structure type to access the System Timer (SysTick).
kenjiArai	4:e9dfb4ca4277	557	*/
kenjiArai	4:e9dfb4ca4277	558	typedef struct
kenjiArai	4:e9dfb4ca4277	559	{
kenjiArai	4:e9dfb4ca4277	560	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
kenjiArai	4:e9dfb4ca4277	561	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
kenjiArai	4:e9dfb4ca4277	562	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
kenjiArai	4:e9dfb4ca4277	563	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
kenjiArai	4:e9dfb4ca4277	564	} SysTick_Type;
kenjiArai	4:e9dfb4ca4277	565
kenjiArai	4:e9dfb4ca4277	566	/* SysTick Control / Status Register Definitions */
kenjiArai	4:e9dfb4ca4277	567	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
kenjiArai	4:e9dfb4ca4277	568	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
kenjiArai	4:e9dfb4ca4277	569
kenjiArai	4:e9dfb4ca4277	570	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
kenjiArai	4:e9dfb4ca4277	571	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
kenjiArai	4:e9dfb4ca4277	572
kenjiArai	4:e9dfb4ca4277	573	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
kenjiArai	4:e9dfb4ca4277	574	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
kenjiArai	4:e9dfb4ca4277	575
kenjiArai	4:e9dfb4ca4277	576	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
kenjiArai	4:e9dfb4ca4277	577	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
kenjiArai	4:e9dfb4ca4277	578
kenjiArai	4:e9dfb4ca4277	579	/* SysTick Reload Register Definitions */
kenjiArai	4:e9dfb4ca4277	580	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
kenjiArai	4:e9dfb4ca4277	581	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
kenjiArai	4:e9dfb4ca4277	582
kenjiArai	4:e9dfb4ca4277	583	/* SysTick Current Register Definitions */
kenjiArai	4:e9dfb4ca4277	584	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
kenjiArai	4:e9dfb4ca4277	585	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
kenjiArai	4:e9dfb4ca4277	586
kenjiArai	4:e9dfb4ca4277	587	/* SysTick Calibration Register Definitions */
kenjiArai	4:e9dfb4ca4277	588	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
kenjiArai	4:e9dfb4ca4277	589	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
kenjiArai	4:e9dfb4ca4277	590
kenjiArai	4:e9dfb4ca4277	591	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
kenjiArai	4:e9dfb4ca4277	592	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
kenjiArai	4:e9dfb4ca4277	593
kenjiArai	4:e9dfb4ca4277	594	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
kenjiArai	4:e9dfb4ca4277	595	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
kenjiArai	4:e9dfb4ca4277	596
kenjiArai	4:e9dfb4ca4277	597	/@} end of group CMSIS_SysTick /
kenjiArai	4:e9dfb4ca4277	598
kenjiArai	4:e9dfb4ca4277	599
kenjiArai	4:e9dfb4ca4277	600	/**
kenjiArai	4:e9dfb4ca4277	601	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	602	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
kenjiArai	4:e9dfb4ca4277	603	\brief Type definitions for the Data Watchpoint and Trace (DWT)
kenjiArai	4:e9dfb4ca4277	604	@{
kenjiArai	4:e9dfb4ca4277	605	*/
kenjiArai	4:e9dfb4ca4277	606
kenjiArai	4:e9dfb4ca4277	607	/**
kenjiArai	4:e9dfb4ca4277	608	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
kenjiArai	4:e9dfb4ca4277	609	*/
kenjiArai	4:e9dfb4ca4277	610	typedef struct
kenjiArai	4:e9dfb4ca4277	611	{
kenjiArai	4:e9dfb4ca4277	612	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
kenjiArai	4:e9dfb4ca4277	613	uint32_t RESERVED0[6U];
kenjiArai	4:e9dfb4ca4277	614	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
kenjiArai	4:e9dfb4ca4277	615	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
kenjiArai	4:e9dfb4ca4277	616	uint32_t RESERVED1[1U];
kenjiArai	4:e9dfb4ca4277	617	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
kenjiArai	4:e9dfb4ca4277	618	uint32_t RESERVED2[1U];
kenjiArai	4:e9dfb4ca4277	619	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
kenjiArai	4:e9dfb4ca4277	620	uint32_t RESERVED3[1U];
kenjiArai	4:e9dfb4ca4277	621	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
kenjiArai	4:e9dfb4ca4277	622	uint32_t RESERVED4[1U];
kenjiArai	4:e9dfb4ca4277	623	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
kenjiArai	4:e9dfb4ca4277	624	uint32_t RESERVED5[1U];
kenjiArai	4:e9dfb4ca4277	625	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
kenjiArai	4:e9dfb4ca4277	626	uint32_t RESERVED6[1U];
kenjiArai	4:e9dfb4ca4277	627	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
kenjiArai	4:e9dfb4ca4277	628	uint32_t RESERVED7[1U];
kenjiArai	4:e9dfb4ca4277	629	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
kenjiArai	4:e9dfb4ca4277	630	uint32_t RESERVED8[1U];
kenjiArai	4:e9dfb4ca4277	631	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
kenjiArai	4:e9dfb4ca4277	632	uint32_t RESERVED9[1U];
kenjiArai	4:e9dfb4ca4277	633	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
kenjiArai	4:e9dfb4ca4277	634	uint32_t RESERVED10[1U];
kenjiArai	4:e9dfb4ca4277	635	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
kenjiArai	4:e9dfb4ca4277	636	uint32_t RESERVED11[1U];
kenjiArai	4:e9dfb4ca4277	637	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
kenjiArai	4:e9dfb4ca4277	638	uint32_t RESERVED12[1U];
kenjiArai	4:e9dfb4ca4277	639	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
kenjiArai	4:e9dfb4ca4277	640	uint32_t RESERVED13[1U];
kenjiArai	4:e9dfb4ca4277	641	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
kenjiArai	4:e9dfb4ca4277	642	uint32_t RESERVED14[1U];
kenjiArai	4:e9dfb4ca4277	643	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
kenjiArai	4:e9dfb4ca4277	644	uint32_t RESERVED15[1U];
kenjiArai	4:e9dfb4ca4277	645	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
kenjiArai	4:e9dfb4ca4277	646	uint32_t RESERVED16[1U];
kenjiArai	4:e9dfb4ca4277	647	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
kenjiArai	4:e9dfb4ca4277	648	uint32_t RESERVED17[1U];
kenjiArai	4:e9dfb4ca4277	649	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
kenjiArai	4:e9dfb4ca4277	650	uint32_t RESERVED18[1U];
kenjiArai	4:e9dfb4ca4277	651	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
kenjiArai	4:e9dfb4ca4277	652	uint32_t RESERVED19[1U];
kenjiArai	4:e9dfb4ca4277	653	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
kenjiArai	4:e9dfb4ca4277	654	uint32_t RESERVED20[1U];
kenjiArai	4:e9dfb4ca4277	655	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
kenjiArai	4:e9dfb4ca4277	656	uint32_t RESERVED21[1U];
kenjiArai	4:e9dfb4ca4277	657	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
kenjiArai	4:e9dfb4ca4277	658	uint32_t RESERVED22[1U];
kenjiArai	4:e9dfb4ca4277	659	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
kenjiArai	4:e9dfb4ca4277	660	uint32_t RESERVED23[1U];
kenjiArai	4:e9dfb4ca4277	661	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
kenjiArai	4:e9dfb4ca4277	662	uint32_t RESERVED24[1U];
kenjiArai	4:e9dfb4ca4277	663	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
kenjiArai	4:e9dfb4ca4277	664	uint32_t RESERVED25[1U];
kenjiArai	4:e9dfb4ca4277	665	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
kenjiArai	4:e9dfb4ca4277	666	uint32_t RESERVED26[1U];
kenjiArai	4:e9dfb4ca4277	667	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
kenjiArai	4:e9dfb4ca4277	668	uint32_t RESERVED27[1U];
kenjiArai	4:e9dfb4ca4277	669	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
kenjiArai	4:e9dfb4ca4277	670	uint32_t RESERVED28[1U];
kenjiArai	4:e9dfb4ca4277	671	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
kenjiArai	4:e9dfb4ca4277	672	uint32_t RESERVED29[1U];
kenjiArai	4:e9dfb4ca4277	673	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
kenjiArai	4:e9dfb4ca4277	674	uint32_t RESERVED30[1U];
kenjiArai	4:e9dfb4ca4277	675	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
kenjiArai	4:e9dfb4ca4277	676	uint32_t RESERVED31[1U];
kenjiArai	4:e9dfb4ca4277	677	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
kenjiArai	4:e9dfb4ca4277	678	} DWT_Type;
kenjiArai	4:e9dfb4ca4277	679
kenjiArai	4:e9dfb4ca4277	680	/* DWT Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	681	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
kenjiArai	4:e9dfb4ca4277	682	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
kenjiArai	4:e9dfb4ca4277	683
kenjiArai	4:e9dfb4ca4277	684	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
kenjiArai	4:e9dfb4ca4277	685	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
kenjiArai	4:e9dfb4ca4277	686
kenjiArai	4:e9dfb4ca4277	687	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
kenjiArai	4:e9dfb4ca4277	688	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
kenjiArai	4:e9dfb4ca4277	689
kenjiArai	4:e9dfb4ca4277	690	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
kenjiArai	4:e9dfb4ca4277	691	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
kenjiArai	4:e9dfb4ca4277	692
kenjiArai	4:e9dfb4ca4277	693	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
kenjiArai	4:e9dfb4ca4277	694	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
kenjiArai	4:e9dfb4ca4277	695
kenjiArai	4:e9dfb4ca4277	696	/* DWT Comparator Function Register Definitions */
kenjiArai	4:e9dfb4ca4277	697	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
kenjiArai	4:e9dfb4ca4277	698	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
kenjiArai	4:e9dfb4ca4277	699
kenjiArai	4:e9dfb4ca4277	700	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
kenjiArai	4:e9dfb4ca4277	701	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
kenjiArai	4:e9dfb4ca4277	702
kenjiArai	4:e9dfb4ca4277	703	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
kenjiArai	4:e9dfb4ca4277	704	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
kenjiArai	4:e9dfb4ca4277	705
kenjiArai	4:e9dfb4ca4277	706	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
kenjiArai	4:e9dfb4ca4277	707	#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
kenjiArai	4:e9dfb4ca4277	708
kenjiArai	4:e9dfb4ca4277	709	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
kenjiArai	4:e9dfb4ca4277	710	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
kenjiArai	4:e9dfb4ca4277	711
kenjiArai	4:e9dfb4ca4277	712	/@}/ /* end of group CMSIS_DWT */
kenjiArai	4:e9dfb4ca4277	713
kenjiArai	4:e9dfb4ca4277	714
kenjiArai	4:e9dfb4ca4277	715	/**
kenjiArai	4:e9dfb4ca4277	716	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	717	\defgroup CMSIS_TPI Trace Port Interface (TPI)
kenjiArai	4:e9dfb4ca4277	718	\brief Type definitions for the Trace Port Interface (TPI)
kenjiArai	4:e9dfb4ca4277	719	@{
kenjiArai	4:e9dfb4ca4277	720	*/
kenjiArai	4:e9dfb4ca4277	721
kenjiArai	4:e9dfb4ca4277	722	/**
kenjiArai	4:e9dfb4ca4277	723	\brief Structure type to access the Trace Port Interface Register (TPI).
kenjiArai	4:e9dfb4ca4277	724	*/
kenjiArai	4:e9dfb4ca4277	725	typedef struct
kenjiArai	4:e9dfb4ca4277	726	{
kenjiArai	4:e9dfb4ca4277	727	__IM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
kenjiArai	4:e9dfb4ca4277	728	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
kenjiArai	4:e9dfb4ca4277	729	uint32_t RESERVED0[2U];
kenjiArai	4:e9dfb4ca4277	730	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
kenjiArai	4:e9dfb4ca4277	731	uint32_t RESERVED1[55U];
kenjiArai	4:e9dfb4ca4277	732	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
kenjiArai	4:e9dfb4ca4277	733	uint32_t RESERVED2[131U];
kenjiArai	4:e9dfb4ca4277	734	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
kenjiArai	4:e9dfb4ca4277	735	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
kenjiArai	4:e9dfb4ca4277	736	__IOM uint32_t PSCR; /!< Offset: 0x308 (R/W) Periodic Synchronization Control Register /
kenjiArai	4:e9dfb4ca4277	737	uint32_t RESERVED3[759U];
kenjiArai	4:e9dfb4ca4277	738	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER Register /
kenjiArai	4:e9dfb4ca4277	739	__IM uint32_t ITFTTD0; /!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register /
kenjiArai	4:e9dfb4ca4277	740	__IOM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 /
kenjiArai	4:e9dfb4ca4277	741	uint32_t RESERVED4[1U];
kenjiArai	4:e9dfb4ca4277	742	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 /
kenjiArai	4:e9dfb4ca4277	743	__IM uint32_t ITFTTD1; /!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register /
kenjiArai	4:e9dfb4ca4277	744	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
kenjiArai	4:e9dfb4ca4277	745	uint32_t RESERVED5[39U];
kenjiArai	4:e9dfb4ca4277	746	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
kenjiArai	4:e9dfb4ca4277	747	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
kenjiArai	4:e9dfb4ca4277	748	uint32_t RESERVED7[8U];
kenjiArai	4:e9dfb4ca4277	749	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) Device Configuration Register /
kenjiArai	4:e9dfb4ca4277	750	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) Device Type Identifier Register /
kenjiArai	4:e9dfb4ca4277	751	} TPI_Type;
kenjiArai	4:e9dfb4ca4277	752
kenjiArai	4:e9dfb4ca4277	753	/* TPI Asynchronous Clock Prescaler Register Definitions */
kenjiArai	4:e9dfb4ca4277	754	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
kenjiArai	4:e9dfb4ca4277	755	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
kenjiArai	4:e9dfb4ca4277	756
kenjiArai	4:e9dfb4ca4277	757	/* TPI Selected Pin Protocol Register Definitions */
kenjiArai	4:e9dfb4ca4277	758	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
kenjiArai	4:e9dfb4ca4277	759	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
kenjiArai	4:e9dfb4ca4277	760
kenjiArai	4:e9dfb4ca4277	761	/* TPI Formatter and Flush Status Register Definitions */
kenjiArai	4:e9dfb4ca4277	762	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
kenjiArai	4:e9dfb4ca4277	763	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
kenjiArai	4:e9dfb4ca4277	764
kenjiArai	4:e9dfb4ca4277	765	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
kenjiArai	4:e9dfb4ca4277	766	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
kenjiArai	4:e9dfb4ca4277	767
kenjiArai	4:e9dfb4ca4277	768	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
kenjiArai	4:e9dfb4ca4277	769	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
kenjiArai	4:e9dfb4ca4277	770
kenjiArai	4:e9dfb4ca4277	771	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
kenjiArai	4:e9dfb4ca4277	772	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
kenjiArai	4:e9dfb4ca4277	773
kenjiArai	4:e9dfb4ca4277	774	/* TPI Formatter and Flush Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	775	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
kenjiArai	4:e9dfb4ca4277	776	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
kenjiArai	4:e9dfb4ca4277	777
kenjiArai	4:e9dfb4ca4277	778	#define TPI_FFCR_FOnMan_Pos 6U /!< TPI FFCR: FOnMan Position /
kenjiArai	4:e9dfb4ca4277	779	#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /!< TPI FFCR: FOnMan Mask /
kenjiArai	4:e9dfb4ca4277	780
kenjiArai	4:e9dfb4ca4277	781	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
kenjiArai	4:e9dfb4ca4277	782	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
kenjiArai	4:e9dfb4ca4277	783
kenjiArai	4:e9dfb4ca4277	784	/* TPI TRIGGER Register Definitions */
kenjiArai	4:e9dfb4ca4277	785	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
kenjiArai	4:e9dfb4ca4277	786	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
kenjiArai	4:e9dfb4ca4277	787
kenjiArai	4:e9dfb4ca4277	788	/* TPI Integration Test FIFO Test Data 0 Register Definitions */
kenjiArai	4:e9dfb4ca4277	789	#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition /
kenjiArai	4:e9dfb4ca4277	790	#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask /
kenjiArai	4:e9dfb4ca4277	791
kenjiArai	4:e9dfb4ca4277	792	#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /!< TPI ITFTTD0: ATB Interface 2 byte count Position /
kenjiArai	4:e9dfb4ca4277	793	#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /!< TPI ITFTTD0: ATB Interface 2 byte count Mask /
kenjiArai	4:e9dfb4ca4277	794
kenjiArai	4:e9dfb4ca4277	795	#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /!< TPI ITFTTD0: ATB Interface 1 ATVALID Position /
kenjiArai	4:e9dfb4ca4277	796	#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask /
kenjiArai	4:e9dfb4ca4277	797
kenjiArai	4:e9dfb4ca4277	798	#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /!< TPI ITFTTD0: ATB Interface 1 byte count Position /
kenjiArai	4:e9dfb4ca4277	799	#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /!< TPI ITFTTD0: ATB Interface 1 byte countt Mask /
kenjiArai	4:e9dfb4ca4277	800
kenjiArai	4:e9dfb4ca4277	801	#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /!< TPI ITFTTD0: ATB Interface 1 data2 Position /
kenjiArai	4:e9dfb4ca4277	802	#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /!< TPI ITFTTD0: ATB Interface 1 data2 Mask /
kenjiArai	4:e9dfb4ca4277	803
kenjiArai	4:e9dfb4ca4277	804	#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /!< TPI ITFTTD0: ATB Interface 1 data1 Position /
kenjiArai	4:e9dfb4ca4277	805	#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /!< TPI ITFTTD0: ATB Interface 1 data1 Mask /
kenjiArai	4:e9dfb4ca4277	806
kenjiArai	4:e9dfb4ca4277	807	#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /!< TPI ITFTTD0: ATB Interface 1 data0 Position /
kenjiArai	4:e9dfb4ca4277	808	#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/) /!< TPI ITFTTD0: ATB Interface 1 data0 Mask /
kenjiArai	4:e9dfb4ca4277	809
kenjiArai	4:e9dfb4ca4277	810	/* TPI Integration Test ATB Control Register 2 Register Definitions */
kenjiArai	4:e9dfb4ca4277	811	#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /!< TPI ITATBCTR2: AFVALID2S Position /
kenjiArai	4:e9dfb4ca4277	812	#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /!< TPI ITATBCTR2: AFVALID2SS Mask /
kenjiArai	4:e9dfb4ca4277	813
kenjiArai	4:e9dfb4ca4277	814	#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /!< TPI ITATBCTR2: AFVALID1S Position /
kenjiArai	4:e9dfb4ca4277	815	#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /!< TPI ITATBCTR2: AFVALID1SS Mask /
kenjiArai	4:e9dfb4ca4277	816
kenjiArai	4:e9dfb4ca4277	817	#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /!< TPI ITATBCTR2: ATREADY2S Position /
kenjiArai	4:e9dfb4ca4277	818	#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/) /!< TPI ITATBCTR2: ATREADY2S Mask /
kenjiArai	4:e9dfb4ca4277	819
kenjiArai	4:e9dfb4ca4277	820	#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /!< TPI ITATBCTR2: ATREADY1S Position /
kenjiArai	4:e9dfb4ca4277	821	#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/) /!< TPI ITATBCTR2: ATREADY1S Mask /
kenjiArai	4:e9dfb4ca4277	822
kenjiArai	4:e9dfb4ca4277	823	/* TPI Integration Test FIFO Test Data 1 Register Definitions */
kenjiArai	4:e9dfb4ca4277	824	#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /!< TPI ITFTTD1: ATB Interface 2 ATVALID Position /
kenjiArai	4:e9dfb4ca4277	825	#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask /
kenjiArai	4:e9dfb4ca4277	826
kenjiArai	4:e9dfb4ca4277	827	#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /!< TPI ITFTTD1: ATB Interface 2 byte count Position /
kenjiArai	4:e9dfb4ca4277	828	#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /!< TPI ITFTTD1: ATB Interface 2 byte count Mask /
kenjiArai	4:e9dfb4ca4277	829
kenjiArai	4:e9dfb4ca4277	830	#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /!< TPI ITFTTD1: ATB Interface 1 ATVALID Position /
kenjiArai	4:e9dfb4ca4277	831	#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask /
kenjiArai	4:e9dfb4ca4277	832
kenjiArai	4:e9dfb4ca4277	833	#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /!< TPI ITFTTD1: ATB Interface 1 byte count Position /
kenjiArai	4:e9dfb4ca4277	834	#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /!< TPI ITFTTD1: ATB Interface 1 byte countt Mask /
kenjiArai	4:e9dfb4ca4277	835
kenjiArai	4:e9dfb4ca4277	836	#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /!< TPI ITFTTD1: ATB Interface 2 data2 Position /
kenjiArai	4:e9dfb4ca4277	837	#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /!< TPI ITFTTD1: ATB Interface 2 data2 Mask /
kenjiArai	4:e9dfb4ca4277	838
kenjiArai	4:e9dfb4ca4277	839	#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /!< TPI ITFTTD1: ATB Interface 2 data1 Position /
kenjiArai	4:e9dfb4ca4277	840	#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /!< TPI ITFTTD1: ATB Interface 2 data1 Mask /
kenjiArai	4:e9dfb4ca4277	841
kenjiArai	4:e9dfb4ca4277	842	#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /!< TPI ITFTTD1: ATB Interface 2 data0 Position /
kenjiArai	4:e9dfb4ca4277	843	#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/) /!< TPI ITFTTD1: ATB Interface 2 data0 Mask /
kenjiArai	4:e9dfb4ca4277	844
kenjiArai	4:e9dfb4ca4277	845	/* TPI Integration Test ATB Control Register 0 Definitions */
kenjiArai	4:e9dfb4ca4277	846	#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /!< TPI ITATBCTR0: AFVALID2S Position /
kenjiArai	4:e9dfb4ca4277	847	#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /!< TPI ITATBCTR0: AFVALID2SS Mask /
kenjiArai	4:e9dfb4ca4277	848
kenjiArai	4:e9dfb4ca4277	849	#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /!< TPI ITATBCTR0: AFVALID1S Position /
kenjiArai	4:e9dfb4ca4277	850	#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /!< TPI ITATBCTR0: AFVALID1SS Mask /
kenjiArai	4:e9dfb4ca4277	851
kenjiArai	4:e9dfb4ca4277	852	#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /!< TPI ITATBCTR0: ATREADY2S Position /
kenjiArai	4:e9dfb4ca4277	853	#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/) /!< TPI ITATBCTR0: ATREADY2S Mask /
kenjiArai	4:e9dfb4ca4277	854
kenjiArai	4:e9dfb4ca4277	855	#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /!< TPI ITATBCTR0: ATREADY1S Position /
kenjiArai	4:e9dfb4ca4277	856	#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/) /!< TPI ITATBCTR0: ATREADY1S Mask /
kenjiArai	4:e9dfb4ca4277	857
kenjiArai	4:e9dfb4ca4277	858	/* TPI Integration Mode Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	859	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
kenjiArai	4:e9dfb4ca4277	860	#define TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
kenjiArai	4:e9dfb4ca4277	861
kenjiArai	4:e9dfb4ca4277	862	/* TPI DEVID Register Definitions */
kenjiArai	4:e9dfb4ca4277	863	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
kenjiArai	4:e9dfb4ca4277	864	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
kenjiArai	4:e9dfb4ca4277	865
kenjiArai	4:e9dfb4ca4277	866	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
kenjiArai	4:e9dfb4ca4277	867	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
kenjiArai	4:e9dfb4ca4277	868
kenjiArai	4:e9dfb4ca4277	869	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
kenjiArai	4:e9dfb4ca4277	870	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
kenjiArai	4:e9dfb4ca4277	871
kenjiArai	4:e9dfb4ca4277	872	#define TPI_DEVID_FIFOSZ_Pos 6U /!< TPI DEVID: FIFOSZ Position /
kenjiArai	4:e9dfb4ca4277	873	#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /!< TPI DEVID: FIFOSZ Mask /
kenjiArai	4:e9dfb4ca4277	874
kenjiArai	4:e9dfb4ca4277	875	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
kenjiArai	4:e9dfb4ca4277	876	#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
kenjiArai	4:e9dfb4ca4277	877
kenjiArai	4:e9dfb4ca4277	878	/* TPI DEVTYPE Register Definitions */
kenjiArai	4:e9dfb4ca4277	879	#define TPI_DEVTYPE_SubType_Pos 4U /!< TPI DEVTYPE: SubType Position /
kenjiArai	4:e9dfb4ca4277	880	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
kenjiArai	4:e9dfb4ca4277	881
kenjiArai	4:e9dfb4ca4277	882	#define TPI_DEVTYPE_MajorType_Pos 0U /!< TPI DEVTYPE: MajorType Position /
kenjiArai	4:e9dfb4ca4277	883	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
kenjiArai	4:e9dfb4ca4277	884
kenjiArai	4:e9dfb4ca4277	885	/@}/ /* end of group CMSIS_TPI */
kenjiArai	4:e9dfb4ca4277	886
kenjiArai	4:e9dfb4ca4277	887
kenjiArai	4:e9dfb4ca4277	888	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	889	/**
kenjiArai	4:e9dfb4ca4277	890	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	891	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
kenjiArai	4:e9dfb4ca4277	892	\brief Type definitions for the Memory Protection Unit (MPU)
kenjiArai	4:e9dfb4ca4277	893	@{
kenjiArai	4:e9dfb4ca4277	894	*/
kenjiArai	4:e9dfb4ca4277	895
kenjiArai	4:e9dfb4ca4277	896	/**
kenjiArai	4:e9dfb4ca4277	897	\brief Structure type to access the Memory Protection Unit (MPU).
kenjiArai	4:e9dfb4ca4277	898	*/
kenjiArai	4:e9dfb4ca4277	899	typedef struct
kenjiArai	4:e9dfb4ca4277	900	{
kenjiArai	4:e9dfb4ca4277	901	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
kenjiArai	4:e9dfb4ca4277	902	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
kenjiArai	4:e9dfb4ca4277	903	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
kenjiArai	4:e9dfb4ca4277	904	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
kenjiArai	4:e9dfb4ca4277	905	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
kenjiArai	4:e9dfb4ca4277	906	uint32_t RESERVED0[7U];
kenjiArai	4:e9dfb4ca4277	907	union {
kenjiArai	4:e9dfb4ca4277	908	__IOM uint32_t MAIR[2];
kenjiArai	4:e9dfb4ca4277	909	struct {
kenjiArai	4:e9dfb4ca4277	910	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
kenjiArai	4:e9dfb4ca4277	911	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
kenjiArai	4:e9dfb4ca4277	912	};
kenjiArai	4:e9dfb4ca4277	913	};
kenjiArai	4:e9dfb4ca4277	914	} MPU_Type;
kenjiArai	4:e9dfb4ca4277	915
kenjiArai	4:e9dfb4ca4277	916	#define MPU_TYPE_RALIASES 1U
kenjiArai	4:e9dfb4ca4277	917
kenjiArai	4:e9dfb4ca4277	918	/* MPU Type Register Definitions */
kenjiArai	4:e9dfb4ca4277	919	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
kenjiArai	4:e9dfb4ca4277	920	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
kenjiArai	4:e9dfb4ca4277	921
kenjiArai	4:e9dfb4ca4277	922	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
kenjiArai	4:e9dfb4ca4277	923	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
kenjiArai	4:e9dfb4ca4277	924
kenjiArai	4:e9dfb4ca4277	925	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
kenjiArai	4:e9dfb4ca4277	926	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
kenjiArai	4:e9dfb4ca4277	927
kenjiArai	4:e9dfb4ca4277	928	/* MPU Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	929	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
kenjiArai	4:e9dfb4ca4277	930	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
kenjiArai	4:e9dfb4ca4277	931
kenjiArai	4:e9dfb4ca4277	932	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
kenjiArai	4:e9dfb4ca4277	933	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
kenjiArai	4:e9dfb4ca4277	934
kenjiArai	4:e9dfb4ca4277	935	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
kenjiArai	4:e9dfb4ca4277	936	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
kenjiArai	4:e9dfb4ca4277	937
kenjiArai	4:e9dfb4ca4277	938	/* MPU Region Number Register Definitions */
kenjiArai	4:e9dfb4ca4277	939	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
kenjiArai	4:e9dfb4ca4277	940	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
kenjiArai	4:e9dfb4ca4277	941
kenjiArai	4:e9dfb4ca4277	942	/* MPU Region Base Address Register Definitions */
kenjiArai	4:e9dfb4ca4277	943	#define MPU_RBAR_BASE_Pos 5U /!< MPU RBAR: BASE Position /
kenjiArai	4:e9dfb4ca4277	944	#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /!< MPU RBAR: BASE Mask /
kenjiArai	4:e9dfb4ca4277	945
kenjiArai	4:e9dfb4ca4277	946	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
kenjiArai	4:e9dfb4ca4277	947	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
kenjiArai	4:e9dfb4ca4277	948
kenjiArai	4:e9dfb4ca4277	949	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
kenjiArai	4:e9dfb4ca4277	950	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
kenjiArai	4:e9dfb4ca4277	951
kenjiArai	4:e9dfb4ca4277	952	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
kenjiArai	4:e9dfb4ca4277	953	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
kenjiArai	4:e9dfb4ca4277	954
kenjiArai	4:e9dfb4ca4277	955	/* MPU Region Limit Address Register Definitions */
kenjiArai	4:e9dfb4ca4277	956	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
kenjiArai	4:e9dfb4ca4277	957	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
kenjiArai	4:e9dfb4ca4277	958
kenjiArai	4:e9dfb4ca4277	959	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
kenjiArai	4:e9dfb4ca4277	960	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
kenjiArai	4:e9dfb4ca4277	961
kenjiArai	4:e9dfb4ca4277	962	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: EN Position /
kenjiArai	4:e9dfb4ca4277	963	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: EN Mask /
kenjiArai	4:e9dfb4ca4277	964
kenjiArai	4:e9dfb4ca4277	965	/* MPU Memory Attribute Indirection Register 0 Definitions */
kenjiArai	4:e9dfb4ca4277	966	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
kenjiArai	4:e9dfb4ca4277	967	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
kenjiArai	4:e9dfb4ca4277	968
kenjiArai	4:e9dfb4ca4277	969	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
kenjiArai	4:e9dfb4ca4277	970	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
kenjiArai	4:e9dfb4ca4277	971
kenjiArai	4:e9dfb4ca4277	972	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
kenjiArai	4:e9dfb4ca4277	973	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
kenjiArai	4:e9dfb4ca4277	974
kenjiArai	4:e9dfb4ca4277	975	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
kenjiArai	4:e9dfb4ca4277	976	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
kenjiArai	4:e9dfb4ca4277	977
kenjiArai	4:e9dfb4ca4277	978	/* MPU Memory Attribute Indirection Register 1 Definitions */
kenjiArai	4:e9dfb4ca4277	979	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
kenjiArai	4:e9dfb4ca4277	980	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
kenjiArai	4:e9dfb4ca4277	981
kenjiArai	4:e9dfb4ca4277	982	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
kenjiArai	4:e9dfb4ca4277	983	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
kenjiArai	4:e9dfb4ca4277	984
kenjiArai	4:e9dfb4ca4277	985	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
kenjiArai	4:e9dfb4ca4277	986	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
kenjiArai	4:e9dfb4ca4277	987
kenjiArai	4:e9dfb4ca4277	988	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
kenjiArai	4:e9dfb4ca4277	989	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
kenjiArai	4:e9dfb4ca4277	990
kenjiArai	4:e9dfb4ca4277	991	/@} end of group CMSIS_MPU /
kenjiArai	4:e9dfb4ca4277	992	#endif
kenjiArai	4:e9dfb4ca4277	993
kenjiArai	4:e9dfb4ca4277	994
kenjiArai	4:e9dfb4ca4277	995	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kenjiArai	4:e9dfb4ca4277	996	/**
kenjiArai	4:e9dfb4ca4277	997	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	998	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
kenjiArai	4:e9dfb4ca4277	999	\brief Type definitions for the Security Attribution Unit (SAU)
kenjiArai	4:e9dfb4ca4277	1000	@{
kenjiArai	4:e9dfb4ca4277	1001	*/
kenjiArai	4:e9dfb4ca4277	1002
kenjiArai	4:e9dfb4ca4277	1003	/**
kenjiArai	4:e9dfb4ca4277	1004	\brief Structure type to access the Security Attribution Unit (SAU).
kenjiArai	4:e9dfb4ca4277	1005	*/
kenjiArai	4:e9dfb4ca4277	1006	typedef struct
kenjiArai	4:e9dfb4ca4277	1007	{
kenjiArai	4:e9dfb4ca4277	1008	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
kenjiArai	4:e9dfb4ca4277	1009	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
kenjiArai	4:e9dfb4ca4277	1010	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	1011	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
kenjiArai	4:e9dfb4ca4277	1012	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
kenjiArai	4:e9dfb4ca4277	1013	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
kenjiArai	4:e9dfb4ca4277	1014	#endif
kenjiArai	4:e9dfb4ca4277	1015	} SAU_Type;
kenjiArai	4:e9dfb4ca4277	1016
kenjiArai	4:e9dfb4ca4277	1017	/* SAU Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	1018	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
kenjiArai	4:e9dfb4ca4277	1019	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
kenjiArai	4:e9dfb4ca4277	1020
kenjiArai	4:e9dfb4ca4277	1021	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
kenjiArai	4:e9dfb4ca4277	1022	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
kenjiArai	4:e9dfb4ca4277	1023
kenjiArai	4:e9dfb4ca4277	1024	/* SAU Type Register Definitions */
kenjiArai	4:e9dfb4ca4277	1025	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
kenjiArai	4:e9dfb4ca4277	1026	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
kenjiArai	4:e9dfb4ca4277	1027
kenjiArai	4:e9dfb4ca4277	1028	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	1029	/* SAU Region Number Register Definitions */
kenjiArai	4:e9dfb4ca4277	1030	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
kenjiArai	4:e9dfb4ca4277	1031	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
kenjiArai	4:e9dfb4ca4277	1032
kenjiArai	4:e9dfb4ca4277	1033	/* SAU Region Base Address Register Definitions */
kenjiArai	4:e9dfb4ca4277	1034	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
kenjiArai	4:e9dfb4ca4277	1035	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
kenjiArai	4:e9dfb4ca4277	1036
kenjiArai	4:e9dfb4ca4277	1037	/* SAU Region Limit Address Register Definitions */
kenjiArai	4:e9dfb4ca4277	1038	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
kenjiArai	4:e9dfb4ca4277	1039	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
kenjiArai	4:e9dfb4ca4277	1040
kenjiArai	4:e9dfb4ca4277	1041	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
kenjiArai	4:e9dfb4ca4277	1042	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
kenjiArai	4:e9dfb4ca4277	1043
kenjiArai	4:e9dfb4ca4277	1044	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
kenjiArai	4:e9dfb4ca4277	1045	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
kenjiArai	4:e9dfb4ca4277	1046
kenjiArai	4:e9dfb4ca4277	1047	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
kenjiArai	4:e9dfb4ca4277	1048
kenjiArai	4:e9dfb4ca4277	1049	/@} end of group CMSIS_SAU /
kenjiArai	4:e9dfb4ca4277	1050	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
kenjiArai	4:e9dfb4ca4277	1051
kenjiArai	4:e9dfb4ca4277	1052
kenjiArai	4:e9dfb4ca4277	1053	/**
kenjiArai	4:e9dfb4ca4277	1054	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	1055	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
kenjiArai	4:e9dfb4ca4277	1056	\brief Type definitions for the Core Debug Registers
kenjiArai	4:e9dfb4ca4277	1057	@{
kenjiArai	4:e9dfb4ca4277	1058	*/
kenjiArai	4:e9dfb4ca4277	1059
kenjiArai	4:e9dfb4ca4277	1060	/**
kenjiArai	4:e9dfb4ca4277	1061	\brief Structure type to access the Core Debug Register (CoreDebug).
kenjiArai	4:e9dfb4ca4277	1062	*/
kenjiArai	4:e9dfb4ca4277	1063	typedef struct
kenjiArai	4:e9dfb4ca4277	1064	{
kenjiArai	4:e9dfb4ca4277	1065	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
kenjiArai	4:e9dfb4ca4277	1066	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
kenjiArai	4:e9dfb4ca4277	1067	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
kenjiArai	4:e9dfb4ca4277	1068	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
kenjiArai	4:e9dfb4ca4277	1069	uint32_t RESERVED4[1U];
kenjiArai	4:e9dfb4ca4277	1070	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
kenjiArai	4:e9dfb4ca4277	1071	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
kenjiArai	4:e9dfb4ca4277	1072	} CoreDebug_Type;
kenjiArai	4:e9dfb4ca4277	1073
kenjiArai	4:e9dfb4ca4277	1074	/* Debug Halting Control and Status Register Definitions */
kenjiArai	4:e9dfb4ca4277	1075	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
kenjiArai	4:e9dfb4ca4277	1076	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
kenjiArai	4:e9dfb4ca4277	1077
kenjiArai	4:e9dfb4ca4277	1078	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
kenjiArai	4:e9dfb4ca4277	1079	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
kenjiArai	4:e9dfb4ca4277	1080
kenjiArai	4:e9dfb4ca4277	1081	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
kenjiArai	4:e9dfb4ca4277	1082	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
kenjiArai	4:e9dfb4ca4277	1083
kenjiArai	4:e9dfb4ca4277	1084	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
kenjiArai	4:e9dfb4ca4277	1085	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
kenjiArai	4:e9dfb4ca4277	1086
kenjiArai	4:e9dfb4ca4277	1087	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
kenjiArai	4:e9dfb4ca4277	1088	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
kenjiArai	4:e9dfb4ca4277	1089
kenjiArai	4:e9dfb4ca4277	1090	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
kenjiArai	4:e9dfb4ca4277	1091	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
kenjiArai	4:e9dfb4ca4277	1092
kenjiArai	4:e9dfb4ca4277	1093	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
kenjiArai	4:e9dfb4ca4277	1094	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
kenjiArai	4:e9dfb4ca4277	1095
kenjiArai	4:e9dfb4ca4277	1096	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
kenjiArai	4:e9dfb4ca4277	1097	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
kenjiArai	4:e9dfb4ca4277	1098
kenjiArai	4:e9dfb4ca4277	1099	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
kenjiArai	4:e9dfb4ca4277	1100	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
kenjiArai	4:e9dfb4ca4277	1101
kenjiArai	4:e9dfb4ca4277	1102	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
kenjiArai	4:e9dfb4ca4277	1103	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
kenjiArai	4:e9dfb4ca4277	1104
kenjiArai	4:e9dfb4ca4277	1105	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
kenjiArai	4:e9dfb4ca4277	1106	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
kenjiArai	4:e9dfb4ca4277	1107
kenjiArai	4:e9dfb4ca4277	1108	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
kenjiArai	4:e9dfb4ca4277	1109	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
kenjiArai	4:e9dfb4ca4277	1110
kenjiArai	4:e9dfb4ca4277	1111	/* Debug Core Register Selector Register Definitions */
kenjiArai	4:e9dfb4ca4277	1112	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
kenjiArai	4:e9dfb4ca4277	1113	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
kenjiArai	4:e9dfb4ca4277	1114
kenjiArai	4:e9dfb4ca4277	1115	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
kenjiArai	4:e9dfb4ca4277	1116	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
kenjiArai	4:e9dfb4ca4277	1117
kenjiArai	4:e9dfb4ca4277	1118	/* Debug Exception and Monitor Control Register */
kenjiArai	4:e9dfb4ca4277	1119	#define CoreDebug_DEMCR_DWTENA_Pos 24U /!< CoreDebug DEMCR: DWTENA Position /
kenjiArai	4:e9dfb4ca4277	1120	#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /!< CoreDebug DEMCR: DWTENA Mask /
kenjiArai	4:e9dfb4ca4277	1121
kenjiArai	4:e9dfb4ca4277	1122	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
kenjiArai	4:e9dfb4ca4277	1123	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
kenjiArai	4:e9dfb4ca4277	1124
kenjiArai	4:e9dfb4ca4277	1125	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
kenjiArai	4:e9dfb4ca4277	1126	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
kenjiArai	4:e9dfb4ca4277	1127
kenjiArai	4:e9dfb4ca4277	1128	/* Debug Authentication Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	1129	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
kenjiArai	4:e9dfb4ca4277	1130	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
kenjiArai	4:e9dfb4ca4277	1131
kenjiArai	4:e9dfb4ca4277	1132	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
kenjiArai	4:e9dfb4ca4277	1133	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
kenjiArai	4:e9dfb4ca4277	1134
kenjiArai	4:e9dfb4ca4277	1135	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
kenjiArai	4:e9dfb4ca4277	1136	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
kenjiArai	4:e9dfb4ca4277	1137
kenjiArai	4:e9dfb4ca4277	1138	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
kenjiArai	4:e9dfb4ca4277	1139	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
kenjiArai	4:e9dfb4ca4277	1140
kenjiArai	4:e9dfb4ca4277	1141	/* Debug Security Control and Status Register Definitions */
kenjiArai	4:e9dfb4ca4277	1142	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
kenjiArai	4:e9dfb4ca4277	1143	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
kenjiArai	4:e9dfb4ca4277	1144
kenjiArai	4:e9dfb4ca4277	1145	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
kenjiArai	4:e9dfb4ca4277	1146	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
kenjiArai	4:e9dfb4ca4277	1147
kenjiArai	4:e9dfb4ca4277	1148	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
kenjiArai	4:e9dfb4ca4277	1149	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
kenjiArai	4:e9dfb4ca4277	1150
kenjiArai	4:e9dfb4ca4277	1151	/@} end of group CMSIS_CoreDebug /
kenjiArai	4:e9dfb4ca4277	1152
kenjiArai	4:e9dfb4ca4277	1153
kenjiArai	4:e9dfb4ca4277	1154	/**
kenjiArai	4:e9dfb4ca4277	1155	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	1156	\defgroup CMSIS_core_bitfield Core register bit field macros
kenjiArai	4:e9dfb4ca4277	1157	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
kenjiArai	4:e9dfb4ca4277	1158	@{
kenjiArai	4:e9dfb4ca4277	1159	*/
kenjiArai	4:e9dfb4ca4277	1160
kenjiArai	4:e9dfb4ca4277	1161	/**
kenjiArai	4:e9dfb4ca4277	1162	\brief Mask and shift a bit field value for use in a register bit range.
kenjiArai	4:e9dfb4ca4277	1163	\param[in] field Name of the register bit field.
kenjiArai	4:e9dfb4ca4277	1164	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
kenjiArai	4:e9dfb4ca4277	1165	\return Masked and shifted value.
kenjiArai	4:e9dfb4ca4277	1166	*/
kenjiArai	4:e9dfb4ca4277	1167	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
kenjiArai	4:e9dfb4ca4277	1168
kenjiArai	4:e9dfb4ca4277	1169	/**
kenjiArai	4:e9dfb4ca4277	1170	\brief Mask and shift a register value to extract a bit filed value.
kenjiArai	4:e9dfb4ca4277	1171	\param[in] field Name of the register bit field.
kenjiArai	4:e9dfb4ca4277	1172	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
kenjiArai	4:e9dfb4ca4277	1173	\return Masked and shifted bit field value.
kenjiArai	4:e9dfb4ca4277	1174	*/
kenjiArai	4:e9dfb4ca4277	1175	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
kenjiArai	4:e9dfb4ca4277	1176
kenjiArai	4:e9dfb4ca4277	1177	/@} end of group CMSIS_core_bitfield /
kenjiArai	4:e9dfb4ca4277	1178
kenjiArai	4:e9dfb4ca4277	1179
kenjiArai	4:e9dfb4ca4277	1180	/**
kenjiArai	4:e9dfb4ca4277	1181	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	1182	\defgroup CMSIS_core_base Core Definitions
kenjiArai	4:e9dfb4ca4277	1183	\brief Definitions for base addresses, unions, and structures.
kenjiArai	4:e9dfb4ca4277	1184	@{
kenjiArai	4:e9dfb4ca4277	1185	*/
kenjiArai	4:e9dfb4ca4277	1186
kenjiArai	4:e9dfb4ca4277	1187	/* Memory mapping of Core Hardware */
kenjiArai	4:e9dfb4ca4277	1188	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
kenjiArai	4:e9dfb4ca4277	1189	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
kenjiArai	4:e9dfb4ca4277	1190	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
kenjiArai	4:e9dfb4ca4277	1191	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
kenjiArai	4:e9dfb4ca4277	1192	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
kenjiArai	4:e9dfb4ca4277	1193	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
kenjiArai	4:e9dfb4ca4277	1194	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
kenjiArai	4:e9dfb4ca4277	1195
kenjiArai	4:e9dfb4ca4277	1196
kenjiArai	4:e9dfb4ca4277	1197	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
kenjiArai	4:e9dfb4ca4277	1198	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
kenjiArai	4:e9dfb4ca4277	1199	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
kenjiArai	4:e9dfb4ca4277	1200	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
kenjiArai	4:e9dfb4ca4277	1201	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
kenjiArai	4:e9dfb4ca4277	1202	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
kenjiArai	4:e9dfb4ca4277	1203
kenjiArai	4:e9dfb4ca4277	1204	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	1205	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
kenjiArai	4:e9dfb4ca4277	1206	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
kenjiArai	4:e9dfb4ca4277	1207	#endif
kenjiArai	4:e9dfb4ca4277	1208
kenjiArai	4:e9dfb4ca4277	1209	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kenjiArai	4:e9dfb4ca4277	1210	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
kenjiArai	4:e9dfb4ca4277	1211	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
kenjiArai	4:e9dfb4ca4277	1212	#endif
kenjiArai	4:e9dfb4ca4277	1213
kenjiArai	4:e9dfb4ca4277	1214	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kenjiArai	4:e9dfb4ca4277	1215	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
kenjiArai	4:e9dfb4ca4277	1216	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
kenjiArai	4:e9dfb4ca4277	1217	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
kenjiArai	4:e9dfb4ca4277	1218	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
kenjiArai	4:e9dfb4ca4277	1219	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
kenjiArai	4:e9dfb4ca4277	1220
kenjiArai	4:e9dfb4ca4277	1221	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
kenjiArai	4:e9dfb4ca4277	1222	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
kenjiArai	4:e9dfb4ca4277	1223	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
kenjiArai	4:e9dfb4ca4277	1224	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
kenjiArai	4:e9dfb4ca4277	1225
kenjiArai	4:e9dfb4ca4277	1226	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	1227	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
kenjiArai	4:e9dfb4ca4277	1228	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
kenjiArai	4:e9dfb4ca4277	1229	#endif
kenjiArai	4:e9dfb4ca4277	1230
kenjiArai	4:e9dfb4ca4277	1231	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
kenjiArai	4:e9dfb4ca4277	1232	/@} /
kenjiArai	4:e9dfb4ca4277	1233
kenjiArai	4:e9dfb4ca4277	1234
kenjiArai	4:e9dfb4ca4277	1235
kenjiArai	4:e9dfb4ca4277	1236	/*******************************************************************************
kenjiArai	4:e9dfb4ca4277	1237	* Hardware Abstraction Layer
kenjiArai	4:e9dfb4ca4277	1238	Core Function Interface contains:
kenjiArai	4:e9dfb4ca4277	1239	- Core NVIC Functions
kenjiArai	4:e9dfb4ca4277	1240	- Core SysTick Functions
kenjiArai	4:e9dfb4ca4277	1241	- Core Register Access Functions
kenjiArai	4:e9dfb4ca4277	1242	******************************************************************************/
kenjiArai	4:e9dfb4ca4277	1243	/**
kenjiArai	4:e9dfb4ca4277	1244	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
kenjiArai	4:e9dfb4ca4277	1245	*/
kenjiArai	4:e9dfb4ca4277	1246
kenjiArai	4:e9dfb4ca4277	1247
kenjiArai	4:e9dfb4ca4277	1248
kenjiArai	4:e9dfb4ca4277	1249	/* ########################## NVIC functions #################################### */
kenjiArai	4:e9dfb4ca4277	1250	/**
kenjiArai	4:e9dfb4ca4277	1251	\ingroup CMSIS_Core_FunctionInterface
kenjiArai	4:e9dfb4ca4277	1252	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
kenjiArai	4:e9dfb4ca4277	1253	\brief Functions that manage interrupts and exceptions via the NVIC.
kenjiArai	4:e9dfb4ca4277	1254	@{
kenjiArai	4:e9dfb4ca4277	1255	*/
kenjiArai	4:e9dfb4ca4277	1256
kenjiArai	4:e9dfb4ca4277	1257	#ifdef CMSIS_NVIC_VIRTUAL
kenjiArai	4:e9dfb4ca4277	1258	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
kenjiArai	4:e9dfb4ca4277	1259	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
kenjiArai	4:e9dfb4ca4277	1260	#endif
kenjiArai	4:e9dfb4ca4277	1261	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
kenjiArai	4:e9dfb4ca4277	1262	#else
kenjiArai	4:e9dfb4ca4277	1263	/#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 /
kenjiArai	4:e9dfb4ca4277	1264	/#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 /
kenjiArai	4:e9dfb4ca4277	1265	#define NVIC_EnableIRQ __NVIC_EnableIRQ
kenjiArai	4:e9dfb4ca4277	1266	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
kenjiArai	4:e9dfb4ca4277	1267	#define NVIC_DisableIRQ __NVIC_DisableIRQ
kenjiArai	4:e9dfb4ca4277	1268	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
kenjiArai	4:e9dfb4ca4277	1269	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
kenjiArai	4:e9dfb4ca4277	1270	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
kenjiArai	4:e9dfb4ca4277	1271	#define NVIC_GetActive __NVIC_GetActive
kenjiArai	4:e9dfb4ca4277	1272	#define NVIC_SetPriority __NVIC_SetPriority
kenjiArai	4:e9dfb4ca4277	1273	#define NVIC_GetPriority __NVIC_GetPriority
kenjiArai	4:e9dfb4ca4277	1274	#define NVIC_SystemReset __NVIC_SystemReset
kenjiArai	4:e9dfb4ca4277	1275	#endif /* CMSIS_NVIC_VIRTUAL */
kenjiArai	4:e9dfb4ca4277	1276
kenjiArai	4:e9dfb4ca4277	1277	#ifdef CMSIS_VECTAB_VIRTUAL
kenjiArai	4:e9dfb4ca4277	1278	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
kenjiArai	4:e9dfb4ca4277	1279	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
kenjiArai	4:e9dfb4ca4277	1280	#endif
kenjiArai	4:e9dfb4ca4277	1281	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
kenjiArai	4:e9dfb4ca4277	1282	#else
kenjiArai	4:e9dfb4ca4277	1283	#define NVIC_SetVector __NVIC_SetVector
kenjiArai	4:e9dfb4ca4277	1284	#define NVIC_GetVector __NVIC_GetVector
kenjiArai	4:e9dfb4ca4277	1285	#endif /* (CMSIS_VECTAB_VIRTUAL) */
kenjiArai	4:e9dfb4ca4277	1286
kenjiArai	4:e9dfb4ca4277	1287	#define NVIC_USER_IRQ_OFFSET 16
kenjiArai	4:e9dfb4ca4277	1288
kenjiArai	4:e9dfb4ca4277	1289
kenjiArai	4:e9dfb4ca4277	1290	/* Special LR values for Secure/Non-Secure call handling and exception handling */
kenjiArai	4:e9dfb4ca4277	1291
kenjiArai	4:e9dfb4ca4277	1292	/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
kenjiArai	4:e9dfb4ca4277	1293	#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
kenjiArai	4:e9dfb4ca4277	1294
kenjiArai	4:e9dfb4ca4277	1295	/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
kenjiArai	4:e9dfb4ca4277	1296	#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
kenjiArai	4:e9dfb4ca4277	1297	#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
kenjiArai	4:e9dfb4ca4277	1298	#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
kenjiArai	4:e9dfb4ca4277	1299	#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
kenjiArai	4:e9dfb4ca4277	1300	#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
kenjiArai	4:e9dfb4ca4277	1301	#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
kenjiArai	4:e9dfb4ca4277	1302	#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
kenjiArai	4:e9dfb4ca4277	1303
kenjiArai	4:e9dfb4ca4277	1304	/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
kenjiArai	4:e9dfb4ca4277	1305	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
kenjiArai	4:e9dfb4ca4277	1306	#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
kenjiArai	4:e9dfb4ca4277	1307	#else
kenjiArai	4:e9dfb4ca4277	1308	#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
kenjiArai	4:e9dfb4ca4277	1309	#endif
kenjiArai	4:e9dfb4ca4277	1310
kenjiArai	4:e9dfb4ca4277	1311
kenjiArai	4:e9dfb4ca4277	1312	/* Interrupt Priorities are WORD accessible only under Armv6-M */
kenjiArai	4:e9dfb4ca4277	1313	/* The following MACROS handle generation of the register offset and byte masks */
kenjiArai	4:e9dfb4ca4277	1314	#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
kenjiArai	4:e9dfb4ca4277	1315	#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
kenjiArai	4:e9dfb4ca4277	1316	#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
kenjiArai	4:e9dfb4ca4277	1317
kenjiArai	4:e9dfb4ca4277	1318	#define __NVIC_SetPriorityGrouping(X) (void)(X)
kenjiArai	4:e9dfb4ca4277	1319	#define __NVIC_GetPriorityGrouping() (0U)
kenjiArai	4:e9dfb4ca4277	1320
kenjiArai	4:e9dfb4ca4277	1321	/**
kenjiArai	4:e9dfb4ca4277	1322	\brief Enable Interrupt
kenjiArai	4:e9dfb4ca4277	1323	\details Enables a device specific interrupt in the NVIC interrupt controller.
kenjiArai	4:e9dfb4ca4277	1324	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	1325	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	1326	*/
kenjiArai	4:e9dfb4ca4277	1327	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1328	{
kenjiArai	4:e9dfb4ca4277	1329	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1330	{
kenjiArai	4:e9dfb4ca4277	1331	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kenjiArai	4:e9dfb4ca4277	1332	}
kenjiArai	4:e9dfb4ca4277	1333	}
kenjiArai	4:e9dfb4ca4277	1334
kenjiArai	4:e9dfb4ca4277	1335
kenjiArai	4:e9dfb4ca4277	1336	/**
kenjiArai	4:e9dfb4ca4277	1337	\brief Get Interrupt Enable status
kenjiArai	4:e9dfb4ca4277	1338	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
kenjiArai	4:e9dfb4ca4277	1339	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	1340	\return 0 Interrupt is not enabled.
kenjiArai	4:e9dfb4ca4277	1341	\return 1 Interrupt is enabled.
kenjiArai	4:e9dfb4ca4277	1342	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	1343	*/
kenjiArai	4:e9dfb4ca4277	1344	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1345	{
kenjiArai	4:e9dfb4ca4277	1346	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1347	{
kenjiArai	4:e9dfb4ca4277	1348	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kenjiArai	4:e9dfb4ca4277	1349	}
kenjiArai	4:e9dfb4ca4277	1350	else
kenjiArai	4:e9dfb4ca4277	1351	{
kenjiArai	4:e9dfb4ca4277	1352	return(0U);
kenjiArai	4:e9dfb4ca4277	1353	}
kenjiArai	4:e9dfb4ca4277	1354	}
kenjiArai	4:e9dfb4ca4277	1355
kenjiArai	4:e9dfb4ca4277	1356
kenjiArai	4:e9dfb4ca4277	1357	/**
kenjiArai	4:e9dfb4ca4277	1358	\brief Disable Interrupt
kenjiArai	4:e9dfb4ca4277	1359	\details Disables a device specific interrupt in the NVIC interrupt controller.
kenjiArai	4:e9dfb4ca4277	1360	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	1361	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	1362	*/
kenjiArai	4:e9dfb4ca4277	1363	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1364	{
kenjiArai	4:e9dfb4ca4277	1365	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1366	{
kenjiArai	4:e9dfb4ca4277	1367	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kenjiArai	4:e9dfb4ca4277	1368	__DSB();
kenjiArai	4:e9dfb4ca4277	1369	__ISB();
kenjiArai	4:e9dfb4ca4277	1370	}
kenjiArai	4:e9dfb4ca4277	1371	}
kenjiArai	4:e9dfb4ca4277	1372
kenjiArai	4:e9dfb4ca4277	1373
kenjiArai	4:e9dfb4ca4277	1374	/**
kenjiArai	4:e9dfb4ca4277	1375	\brief Get Pending Interrupt
kenjiArai	4:e9dfb4ca4277	1376	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
kenjiArai	4:e9dfb4ca4277	1377	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	1378	\return 0 Interrupt status is not pending.
kenjiArai	4:e9dfb4ca4277	1379	\return 1 Interrupt status is pending.
kenjiArai	4:e9dfb4ca4277	1380	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	1381	*/
kenjiArai	4:e9dfb4ca4277	1382	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1383	{
kenjiArai	4:e9dfb4ca4277	1384	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1385	{
kenjiArai	4:e9dfb4ca4277	1386	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kenjiArai	4:e9dfb4ca4277	1387	}
kenjiArai	4:e9dfb4ca4277	1388	else
kenjiArai	4:e9dfb4ca4277	1389	{
kenjiArai	4:e9dfb4ca4277	1390	return(0U);
kenjiArai	4:e9dfb4ca4277	1391	}
kenjiArai	4:e9dfb4ca4277	1392	}
kenjiArai	4:e9dfb4ca4277	1393
kenjiArai	4:e9dfb4ca4277	1394
kenjiArai	4:e9dfb4ca4277	1395	/**
kenjiArai	4:e9dfb4ca4277	1396	\brief Set Pending Interrupt
kenjiArai	4:e9dfb4ca4277	1397	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
kenjiArai	4:e9dfb4ca4277	1398	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	1399	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	1400	*/
kenjiArai	4:e9dfb4ca4277	1401	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1402	{
kenjiArai	4:e9dfb4ca4277	1403	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1404	{
kenjiArai	4:e9dfb4ca4277	1405	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kenjiArai	4:e9dfb4ca4277	1406	}
kenjiArai	4:e9dfb4ca4277	1407	}
kenjiArai	4:e9dfb4ca4277	1408
kenjiArai	4:e9dfb4ca4277	1409
kenjiArai	4:e9dfb4ca4277	1410	/**
kenjiArai	4:e9dfb4ca4277	1411	\brief Clear Pending Interrupt
kenjiArai	4:e9dfb4ca4277	1412	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
kenjiArai	4:e9dfb4ca4277	1413	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	1414	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	1415	*/
kenjiArai	4:e9dfb4ca4277	1416	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1417	{
kenjiArai	4:e9dfb4ca4277	1418	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1419	{
kenjiArai	4:e9dfb4ca4277	1420	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kenjiArai	4:e9dfb4ca4277	1421	}
kenjiArai	4:e9dfb4ca4277	1422	}
kenjiArai	4:e9dfb4ca4277	1423
kenjiArai	4:e9dfb4ca4277	1424
kenjiArai	4:e9dfb4ca4277	1425	/**
kenjiArai	4:e9dfb4ca4277	1426	\brief Get Active Interrupt
kenjiArai	4:e9dfb4ca4277	1427	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
kenjiArai	4:e9dfb4ca4277	1428	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	1429	\return 0 Interrupt status is not active.
kenjiArai	4:e9dfb4ca4277	1430	\return 1 Interrupt status is active.
kenjiArai	4:e9dfb4ca4277	1431	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	1432	*/
kenjiArai	4:e9dfb4ca4277	1433	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1434	{
kenjiArai	4:e9dfb4ca4277	1435	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1436	{
kenjiArai	4:e9dfb4ca4277	1437	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kenjiArai	4:e9dfb4ca4277	1438	}
kenjiArai	4:e9dfb4ca4277	1439	else
kenjiArai	4:e9dfb4ca4277	1440	{
kenjiArai	4:e9dfb4ca4277	1441	return(0U);
kenjiArai	4:e9dfb4ca4277	1442	}
kenjiArai	4:e9dfb4ca4277	1443	}
kenjiArai	4:e9dfb4ca4277	1444
kenjiArai	4:e9dfb4ca4277	1445
kenjiArai	4:e9dfb4ca4277	1446	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kenjiArai	4:e9dfb4ca4277	1447	/**
kenjiArai	4:e9dfb4ca4277	1448	\brief Get Interrupt Target State
kenjiArai	4:e9dfb4ca4277	1449	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
kenjiArai	4:e9dfb4ca4277	1450	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	1451	\return 0 if interrupt is assigned to Secure
kenjiArai	4:e9dfb4ca4277	1452	\return 1 if interrupt is assigned to Non Secure
kenjiArai	4:e9dfb4ca4277	1453	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	1454	*/
kenjiArai	4:e9dfb4ca4277	1455	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1456	{
kenjiArai	4:e9dfb4ca4277	1457	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1458	{
kenjiArai	4:e9dfb4ca4277	1459	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kenjiArai	4:e9dfb4ca4277	1460	}
kenjiArai	4:e9dfb4ca4277	1461	else
kenjiArai	4:e9dfb4ca4277	1462	{
kenjiArai	4:e9dfb4ca4277	1463	return(0U);
kenjiArai	4:e9dfb4ca4277	1464	}
kenjiArai	4:e9dfb4ca4277	1465	}
kenjiArai	4:e9dfb4ca4277	1466
kenjiArai	4:e9dfb4ca4277	1467
kenjiArai	4:e9dfb4ca4277	1468	/**
kenjiArai	4:e9dfb4ca4277	1469	\brief Set Interrupt Target State
kenjiArai	4:e9dfb4ca4277	1470	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
kenjiArai	4:e9dfb4ca4277	1471	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	1472	\return 0 if interrupt is assigned to Secure
kenjiArai	4:e9dfb4ca4277	1473	1 if interrupt is assigned to Non Secure
kenjiArai	4:e9dfb4ca4277	1474	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	1475	*/
kenjiArai	4:e9dfb4ca4277	1476	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1477	{
kenjiArai	4:e9dfb4ca4277	1478	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1479	{
kenjiArai	4:e9dfb4ca4277	1480	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
kenjiArai	4:e9dfb4ca4277	1481	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kenjiArai	4:e9dfb4ca4277	1482	}
kenjiArai	4:e9dfb4ca4277	1483	else
kenjiArai	4:e9dfb4ca4277	1484	{
kenjiArai	4:e9dfb4ca4277	1485	return(0U);
kenjiArai	4:e9dfb4ca4277	1486	}
kenjiArai	4:e9dfb4ca4277	1487	}
kenjiArai	4:e9dfb4ca4277	1488
kenjiArai	4:e9dfb4ca4277	1489
kenjiArai	4:e9dfb4ca4277	1490	/**
kenjiArai	4:e9dfb4ca4277	1491	\brief Clear Interrupt Target State
kenjiArai	4:e9dfb4ca4277	1492	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
kenjiArai	4:e9dfb4ca4277	1493	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	1494	\return 0 if interrupt is assigned to Secure
kenjiArai	4:e9dfb4ca4277	1495	1 if interrupt is assigned to Non Secure
kenjiArai	4:e9dfb4ca4277	1496	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	1497	*/
kenjiArai	4:e9dfb4ca4277	1498	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1499	{
kenjiArai	4:e9dfb4ca4277	1500	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1501	{
kenjiArai	4:e9dfb4ca4277	1502	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
kenjiArai	4:e9dfb4ca4277	1503	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kenjiArai	4:e9dfb4ca4277	1504	}
kenjiArai	4:e9dfb4ca4277	1505	else
kenjiArai	4:e9dfb4ca4277	1506	{
kenjiArai	4:e9dfb4ca4277	1507	return(0U);
kenjiArai	4:e9dfb4ca4277	1508	}
kenjiArai	4:e9dfb4ca4277	1509	}
kenjiArai	4:e9dfb4ca4277	1510	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
kenjiArai	4:e9dfb4ca4277	1511
kenjiArai	4:e9dfb4ca4277	1512
kenjiArai	4:e9dfb4ca4277	1513	/**
kenjiArai	4:e9dfb4ca4277	1514	\brief Set Interrupt Priority
kenjiArai	4:e9dfb4ca4277	1515	\details Sets the priority of a device specific interrupt or a processor exception.
kenjiArai	4:e9dfb4ca4277	1516	The interrupt number can be positive to specify a device specific interrupt,
kenjiArai	4:e9dfb4ca4277	1517	or negative to specify a processor exception.
kenjiArai	4:e9dfb4ca4277	1518	\param [in] IRQn Interrupt number.
kenjiArai	4:e9dfb4ca4277	1519	\param [in] priority Priority to set.
kenjiArai	4:e9dfb4ca4277	1520	\note The priority cannot be set for every processor exception.
kenjiArai	4:e9dfb4ca4277	1521	*/
kenjiArai	4:e9dfb4ca4277	1522	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
kenjiArai	4:e9dfb4ca4277	1523	{
kenjiArai	4:e9dfb4ca4277	1524	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1525	{
kenjiArai	4:e9dfb4ca4277	1526	NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
kenjiArai	4:e9dfb4ca4277	1527	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
kenjiArai	4:e9dfb4ca4277	1528	}
kenjiArai	4:e9dfb4ca4277	1529	else
kenjiArai	4:e9dfb4ca4277	1530	{
kenjiArai	4:e9dfb4ca4277	1531	SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
kenjiArai	4:e9dfb4ca4277	1532	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
kenjiArai	4:e9dfb4ca4277	1533	}
kenjiArai	4:e9dfb4ca4277	1534	}
kenjiArai	4:e9dfb4ca4277	1535
kenjiArai	4:e9dfb4ca4277	1536
kenjiArai	4:e9dfb4ca4277	1537	/**
kenjiArai	4:e9dfb4ca4277	1538	\brief Get Interrupt Priority
kenjiArai	4:e9dfb4ca4277	1539	\details Reads the priority of a device specific interrupt or a processor exception.
kenjiArai	4:e9dfb4ca4277	1540	The interrupt number can be positive to specify a device specific interrupt,
kenjiArai	4:e9dfb4ca4277	1541	or negative to specify a processor exception.
kenjiArai	4:e9dfb4ca4277	1542	\param [in] IRQn Interrupt number.
kenjiArai	4:e9dfb4ca4277	1543	\return Interrupt Priority.
kenjiArai	4:e9dfb4ca4277	1544	Value is aligned automatically to the implemented priority bits of the microcontroller.
kenjiArai	4:e9dfb4ca4277	1545	*/
kenjiArai	4:e9dfb4ca4277	1546	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1547	{
kenjiArai	4:e9dfb4ca4277	1548
kenjiArai	4:e9dfb4ca4277	1549	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1550	{
kenjiArai	4:e9dfb4ca4277	1551	return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
kenjiArai	4:e9dfb4ca4277	1552	}
kenjiArai	4:e9dfb4ca4277	1553	else
kenjiArai	4:e9dfb4ca4277	1554	{
kenjiArai	4:e9dfb4ca4277	1555	return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
kenjiArai	4:e9dfb4ca4277	1556	}
kenjiArai	4:e9dfb4ca4277	1557	}
kenjiArai	4:e9dfb4ca4277	1558
kenjiArai	4:e9dfb4ca4277	1559
kenjiArai	4:e9dfb4ca4277	1560	/**
kenjiArai	4:e9dfb4ca4277	1561	\brief Encode Priority
kenjiArai	4:e9dfb4ca4277	1562	\details Encodes the priority for an interrupt with the given priority group,
kenjiArai	4:e9dfb4ca4277	1563	preemptive priority value, and subpriority value.
kenjiArai	4:e9dfb4ca4277	1564	In case of a conflict between priority grouping and available
kenjiArai	4:e9dfb4ca4277	1565	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
kenjiArai	4:e9dfb4ca4277	1566	\param [in] PriorityGroup Used priority group.
kenjiArai	4:e9dfb4ca4277	1567	\param [in] PreemptPriority Preemptive priority value (starting from 0).
kenjiArai	4:e9dfb4ca4277	1568	\param [in] SubPriority Subpriority value (starting from 0).
kenjiArai	4:e9dfb4ca4277	1569	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
kenjiArai	4:e9dfb4ca4277	1570	*/
kenjiArai	4:e9dfb4ca4277	1571	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
kenjiArai	4:e9dfb4ca4277	1572	{
kenjiArai	4:e9dfb4ca4277	1573	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
kenjiArai	4:e9dfb4ca4277	1574	uint32_t PreemptPriorityBits;
kenjiArai	4:e9dfb4ca4277	1575	uint32_t SubPriorityBits;
kenjiArai	4:e9dfb4ca4277	1576
kenjiArai	4:e9dfb4ca4277	1577	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
kenjiArai	4:e9dfb4ca4277	1578	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
kenjiArai	4:e9dfb4ca4277	1579
kenjiArai	4:e9dfb4ca4277	1580	return (
kenjiArai	4:e9dfb4ca4277	1581	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
kenjiArai	4:e9dfb4ca4277	1582	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
kenjiArai	4:e9dfb4ca4277	1583	);
kenjiArai	4:e9dfb4ca4277	1584	}
kenjiArai	4:e9dfb4ca4277	1585
kenjiArai	4:e9dfb4ca4277	1586
kenjiArai	4:e9dfb4ca4277	1587	/**
kenjiArai	4:e9dfb4ca4277	1588	\brief Decode Priority
kenjiArai	4:e9dfb4ca4277	1589	\details Decodes an interrupt priority value with a given priority group to
kenjiArai	4:e9dfb4ca4277	1590	preemptive priority value and subpriority value.
kenjiArai	4:e9dfb4ca4277	1591	In case of a conflict between priority grouping and available
kenjiArai	4:e9dfb4ca4277	1592	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
kenjiArai	4:e9dfb4ca4277	1593	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
kenjiArai	4:e9dfb4ca4277	1594	\param [in] PriorityGroup Used priority group.
kenjiArai	4:e9dfb4ca4277	1595	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
kenjiArai	4:e9dfb4ca4277	1596	\param [out] pSubPriority Subpriority value (starting from 0).
kenjiArai	4:e9dfb4ca4277	1597	*/
kenjiArai	4:e9dfb4ca4277	1598	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
kenjiArai	4:e9dfb4ca4277	1599	{
kenjiArai	4:e9dfb4ca4277	1600	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
kenjiArai	4:e9dfb4ca4277	1601	uint32_t PreemptPriorityBits;
kenjiArai	4:e9dfb4ca4277	1602	uint32_t SubPriorityBits;
kenjiArai	4:e9dfb4ca4277	1603
kenjiArai	4:e9dfb4ca4277	1604	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
kenjiArai	4:e9dfb4ca4277	1605	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
kenjiArai	4:e9dfb4ca4277	1606
kenjiArai	4:e9dfb4ca4277	1607	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
kenjiArai	4:e9dfb4ca4277	1608	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
kenjiArai	4:e9dfb4ca4277	1609	}
kenjiArai	4:e9dfb4ca4277	1610
kenjiArai	4:e9dfb4ca4277	1611
kenjiArai	4:e9dfb4ca4277	1612	/**
kenjiArai	4:e9dfb4ca4277	1613	\brief Set Interrupt Vector
kenjiArai	4:e9dfb4ca4277	1614	\details Sets an interrupt vector in SRAM based interrupt vector table.
kenjiArai	4:e9dfb4ca4277	1615	The interrupt number can be positive to specify a device specific interrupt,
kenjiArai	4:e9dfb4ca4277	1616	or negative to specify a processor exception.
kenjiArai	4:e9dfb4ca4277	1617	VTOR must been relocated to SRAM before.
kenjiArai	4:e9dfb4ca4277	1618	If VTOR is not present address 0 must be mapped to SRAM.
kenjiArai	4:e9dfb4ca4277	1619	\param [in] IRQn Interrupt number
kenjiArai	4:e9dfb4ca4277	1620	\param [in] vector Address of interrupt handler function
kenjiArai	4:e9dfb4ca4277	1621	*/
kenjiArai	4:e9dfb4ca4277	1622	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
kenjiArai	4:e9dfb4ca4277	1623	{
kenjiArai	4:e9dfb4ca4277	1624	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	1625	uint32_t vectors = (uint32_t )SCB->VTOR;
kenjiArai	4:e9dfb4ca4277	1626	#else
kenjiArai	4:e9dfb4ca4277	1627	uint32_t vectors = (uint32_t )0x0U;
kenjiArai	4:e9dfb4ca4277	1628	#endif
kenjiArai	4:e9dfb4ca4277	1629	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
kenjiArai	4:e9dfb4ca4277	1630	}
kenjiArai	4:e9dfb4ca4277	1631
kenjiArai	4:e9dfb4ca4277	1632
kenjiArai	4:e9dfb4ca4277	1633	/**
kenjiArai	4:e9dfb4ca4277	1634	\brief Get Interrupt Vector
kenjiArai	4:e9dfb4ca4277	1635	\details Reads an interrupt vector from interrupt vector table.
kenjiArai	4:e9dfb4ca4277	1636	The interrupt number can be positive to specify a device specific interrupt,
kenjiArai	4:e9dfb4ca4277	1637	or negative to specify a processor exception.
kenjiArai	4:e9dfb4ca4277	1638	\param [in] IRQn Interrupt number.
kenjiArai	4:e9dfb4ca4277	1639	\return Address of interrupt handler function
kenjiArai	4:e9dfb4ca4277	1640	*/
kenjiArai	4:e9dfb4ca4277	1641	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1642	{
kenjiArai	4:e9dfb4ca4277	1643	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	1644	uint32_t vectors = (uint32_t )SCB->VTOR;
kenjiArai	4:e9dfb4ca4277	1645	#else
kenjiArai	4:e9dfb4ca4277	1646	uint32_t vectors = (uint32_t )0x0U;
kenjiArai	4:e9dfb4ca4277	1647	#endif
kenjiArai	4:e9dfb4ca4277	1648	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
kenjiArai	4:e9dfb4ca4277	1649	}
kenjiArai	4:e9dfb4ca4277	1650
kenjiArai	4:e9dfb4ca4277	1651
kenjiArai	4:e9dfb4ca4277	1652	/**
kenjiArai	4:e9dfb4ca4277	1653	\brief System Reset
kenjiArai	4:e9dfb4ca4277	1654	\details Initiates a system reset request to reset the MCU.
kenjiArai	4:e9dfb4ca4277	1655	*/
kenjiArai	4:e9dfb4ca4277	1656	__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
kenjiArai	4:e9dfb4ca4277	1657	{
kenjiArai	4:e9dfb4ca4277	1658	__DSB(); /* Ensure all outstanding memory accesses included
kenjiArai	4:e9dfb4ca4277	1659	buffered write are completed before reset */
kenjiArai	4:e9dfb4ca4277	1660	SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
kenjiArai	4:e9dfb4ca4277	1661	SCB_AIRCR_SYSRESETREQ_Msk);
kenjiArai	4:e9dfb4ca4277	1662	__DSB(); /* Ensure completion of memory access */
kenjiArai	4:e9dfb4ca4277	1663
kenjiArai	4:e9dfb4ca4277	1664	for(;;) /* wait until reset */
kenjiArai	4:e9dfb4ca4277	1665	{
kenjiArai	4:e9dfb4ca4277	1666	__NOP();
kenjiArai	4:e9dfb4ca4277	1667	}
kenjiArai	4:e9dfb4ca4277	1668	}
kenjiArai	4:e9dfb4ca4277	1669
kenjiArai	4:e9dfb4ca4277	1670	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kenjiArai	4:e9dfb4ca4277	1671	/**
kenjiArai	4:e9dfb4ca4277	1672	\brief Enable Interrupt (non-secure)
kenjiArai	4:e9dfb4ca4277	1673	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
kenjiArai	4:e9dfb4ca4277	1674	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	1675	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	1676	*/
kenjiArai	4:e9dfb4ca4277	1677	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1678	{
kenjiArai	4:e9dfb4ca4277	1679	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1680	{
kenjiArai	4:e9dfb4ca4277	1681	NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kenjiArai	4:e9dfb4ca4277	1682	}
kenjiArai	4:e9dfb4ca4277	1683	}
kenjiArai	4:e9dfb4ca4277	1684
kenjiArai	4:e9dfb4ca4277	1685
kenjiArai	4:e9dfb4ca4277	1686	/**
kenjiArai	4:e9dfb4ca4277	1687	\brief Get Interrupt Enable status (non-secure)
kenjiArai	4:e9dfb4ca4277	1688	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
kenjiArai	4:e9dfb4ca4277	1689	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	1690	\return 0 Interrupt is not enabled.
kenjiArai	4:e9dfb4ca4277	1691	\return 1 Interrupt is enabled.
kenjiArai	4:e9dfb4ca4277	1692	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	1693	*/
kenjiArai	4:e9dfb4ca4277	1694	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1695	{
kenjiArai	4:e9dfb4ca4277	1696	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1697	{
kenjiArai	4:e9dfb4ca4277	1698	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kenjiArai	4:e9dfb4ca4277	1699	}
kenjiArai	4:e9dfb4ca4277	1700	else
kenjiArai	4:e9dfb4ca4277	1701	{
kenjiArai	4:e9dfb4ca4277	1702	return(0U);
kenjiArai	4:e9dfb4ca4277	1703	}
kenjiArai	4:e9dfb4ca4277	1704	}
kenjiArai	4:e9dfb4ca4277	1705
kenjiArai	4:e9dfb4ca4277	1706
kenjiArai	4:e9dfb4ca4277	1707	/**
kenjiArai	4:e9dfb4ca4277	1708	\brief Disable Interrupt (non-secure)
kenjiArai	4:e9dfb4ca4277	1709	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
kenjiArai	4:e9dfb4ca4277	1710	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	1711	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	1712	*/
kenjiArai	4:e9dfb4ca4277	1713	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1714	{
kenjiArai	4:e9dfb4ca4277	1715	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1716	{
kenjiArai	4:e9dfb4ca4277	1717	NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kenjiArai	4:e9dfb4ca4277	1718	}
kenjiArai	4:e9dfb4ca4277	1719	}
kenjiArai	4:e9dfb4ca4277	1720
kenjiArai	4:e9dfb4ca4277	1721
kenjiArai	4:e9dfb4ca4277	1722	/**
kenjiArai	4:e9dfb4ca4277	1723	\brief Get Pending Interrupt (non-secure)
kenjiArai	4:e9dfb4ca4277	1724	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
kenjiArai	4:e9dfb4ca4277	1725	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	1726	\return 0 Interrupt status is not pending.
kenjiArai	4:e9dfb4ca4277	1727	\return 1 Interrupt status is pending.
kenjiArai	4:e9dfb4ca4277	1728	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	1729	*/
kenjiArai	4:e9dfb4ca4277	1730	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1731	{
kenjiArai	4:e9dfb4ca4277	1732	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1733	{
kenjiArai	4:e9dfb4ca4277	1734	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kenjiArai	4:e9dfb4ca4277	1735	}
kenjiArai	4:e9dfb4ca4277	1736	else
kenjiArai	4:e9dfb4ca4277	1737	{
kenjiArai	4:e9dfb4ca4277	1738	return(0U);
kenjiArai	4:e9dfb4ca4277	1739	}
kenjiArai	4:e9dfb4ca4277	1740	}
kenjiArai	4:e9dfb4ca4277	1741
kenjiArai	4:e9dfb4ca4277	1742
kenjiArai	4:e9dfb4ca4277	1743	/**
kenjiArai	4:e9dfb4ca4277	1744	\brief Set Pending Interrupt (non-secure)
kenjiArai	4:e9dfb4ca4277	1745	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
kenjiArai	4:e9dfb4ca4277	1746	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	1747	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	1748	*/
kenjiArai	4:e9dfb4ca4277	1749	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1750	{
kenjiArai	4:e9dfb4ca4277	1751	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1752	{
kenjiArai	4:e9dfb4ca4277	1753	NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kenjiArai	4:e9dfb4ca4277	1754	}
kenjiArai	4:e9dfb4ca4277	1755	}
kenjiArai	4:e9dfb4ca4277	1756
kenjiArai	4:e9dfb4ca4277	1757
kenjiArai	4:e9dfb4ca4277	1758	/**
kenjiArai	4:e9dfb4ca4277	1759	\brief Clear Pending Interrupt (non-secure)
kenjiArai	4:e9dfb4ca4277	1760	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
kenjiArai	4:e9dfb4ca4277	1761	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	1762	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	1763	*/
kenjiArai	4:e9dfb4ca4277	1764	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1765	{
kenjiArai	4:e9dfb4ca4277	1766	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1767	{
kenjiArai	4:e9dfb4ca4277	1768	NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kenjiArai	4:e9dfb4ca4277	1769	}
kenjiArai	4:e9dfb4ca4277	1770	}
kenjiArai	4:e9dfb4ca4277	1771
kenjiArai	4:e9dfb4ca4277	1772
kenjiArai	4:e9dfb4ca4277	1773	/**
kenjiArai	4:e9dfb4ca4277	1774	\brief Get Active Interrupt (non-secure)
kenjiArai	4:e9dfb4ca4277	1775	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
kenjiArai	4:e9dfb4ca4277	1776	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	1777	\return 0 Interrupt status is not active.
kenjiArai	4:e9dfb4ca4277	1778	\return 1 Interrupt status is active.
kenjiArai	4:e9dfb4ca4277	1779	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	1780	*/
kenjiArai	4:e9dfb4ca4277	1781	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1782	{
kenjiArai	4:e9dfb4ca4277	1783	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1784	{
kenjiArai	4:e9dfb4ca4277	1785	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kenjiArai	4:e9dfb4ca4277	1786	}
kenjiArai	4:e9dfb4ca4277	1787	else
kenjiArai	4:e9dfb4ca4277	1788	{
kenjiArai	4:e9dfb4ca4277	1789	return(0U);
kenjiArai	4:e9dfb4ca4277	1790	}
kenjiArai	4:e9dfb4ca4277	1791	}
kenjiArai	4:e9dfb4ca4277	1792
kenjiArai	4:e9dfb4ca4277	1793
kenjiArai	4:e9dfb4ca4277	1794	/**
kenjiArai	4:e9dfb4ca4277	1795	\brief Set Interrupt Priority (non-secure)
kenjiArai	4:e9dfb4ca4277	1796	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
kenjiArai	4:e9dfb4ca4277	1797	The interrupt number can be positive to specify a device specific interrupt,
kenjiArai	4:e9dfb4ca4277	1798	or negative to specify a processor exception.
kenjiArai	4:e9dfb4ca4277	1799	\param [in] IRQn Interrupt number.
kenjiArai	4:e9dfb4ca4277	1800	\param [in] priority Priority to set.
kenjiArai	4:e9dfb4ca4277	1801	\note The priority cannot be set for every non-secure processor exception.
kenjiArai	4:e9dfb4ca4277	1802	*/
kenjiArai	4:e9dfb4ca4277	1803	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
kenjiArai	4:e9dfb4ca4277	1804	{
kenjiArai	4:e9dfb4ca4277	1805	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1806	{
kenjiArai	4:e9dfb4ca4277	1807	NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
kenjiArai	4:e9dfb4ca4277	1808	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
kenjiArai	4:e9dfb4ca4277	1809	}
kenjiArai	4:e9dfb4ca4277	1810	else
kenjiArai	4:e9dfb4ca4277	1811	{
kenjiArai	4:e9dfb4ca4277	1812	SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
kenjiArai	4:e9dfb4ca4277	1813	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
kenjiArai	4:e9dfb4ca4277	1814	}
kenjiArai	4:e9dfb4ca4277	1815	}
kenjiArai	4:e9dfb4ca4277	1816
kenjiArai	4:e9dfb4ca4277	1817
kenjiArai	4:e9dfb4ca4277	1818	/**
kenjiArai	4:e9dfb4ca4277	1819	\brief Get Interrupt Priority (non-secure)
kenjiArai	4:e9dfb4ca4277	1820	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
kenjiArai	4:e9dfb4ca4277	1821	The interrupt number can be positive to specify a device specific interrupt,
kenjiArai	4:e9dfb4ca4277	1822	or negative to specify a processor exception.
kenjiArai	4:e9dfb4ca4277	1823	\param [in] IRQn Interrupt number.
kenjiArai	4:e9dfb4ca4277	1824	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
kenjiArai	4:e9dfb4ca4277	1825	*/
kenjiArai	4:e9dfb4ca4277	1826	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	1827	{
kenjiArai	4:e9dfb4ca4277	1828
kenjiArai	4:e9dfb4ca4277	1829	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	1830	{
kenjiArai	4:e9dfb4ca4277	1831	return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
kenjiArai	4:e9dfb4ca4277	1832	}
kenjiArai	4:e9dfb4ca4277	1833	else
kenjiArai	4:e9dfb4ca4277	1834	{
kenjiArai	4:e9dfb4ca4277	1835	return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
kenjiArai	4:e9dfb4ca4277	1836	}
kenjiArai	4:e9dfb4ca4277	1837	}
kenjiArai	4:e9dfb4ca4277	1838	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
kenjiArai	4:e9dfb4ca4277	1839
kenjiArai	4:e9dfb4ca4277	1840	/@} end of CMSIS_Core_NVICFunctions /
kenjiArai	4:e9dfb4ca4277	1841
kenjiArai	4:e9dfb4ca4277	1842	/* ########################## MPU functions #################################### */
kenjiArai	4:e9dfb4ca4277	1843
kenjiArai	4:e9dfb4ca4277	1844	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	1845
kenjiArai	4:e9dfb4ca4277	1846	#include "mpu_armv8.h"
kenjiArai	4:e9dfb4ca4277	1847
kenjiArai	4:e9dfb4ca4277	1848	#endif
kenjiArai	4:e9dfb4ca4277	1849
kenjiArai	4:e9dfb4ca4277	1850	/* ########################## FPU functions #################################### */
kenjiArai	4:e9dfb4ca4277	1851	/**
kenjiArai	4:e9dfb4ca4277	1852	\ingroup CMSIS_Core_FunctionInterface
kenjiArai	4:e9dfb4ca4277	1853	\defgroup CMSIS_Core_FpuFunctions FPU Functions
kenjiArai	4:e9dfb4ca4277	1854	\brief Function that provides FPU type.
kenjiArai	4:e9dfb4ca4277	1855	@{
kenjiArai	4:e9dfb4ca4277	1856	*/
kenjiArai	4:e9dfb4ca4277	1857
kenjiArai	4:e9dfb4ca4277	1858	/**
kenjiArai	4:e9dfb4ca4277	1859	\brief get FPU type
kenjiArai	4:e9dfb4ca4277	1860	\details returns the FPU type
kenjiArai	4:e9dfb4ca4277	1861	\returns
kenjiArai	4:e9dfb4ca4277	1862	- \b 0: No FPU
kenjiArai	4:e9dfb4ca4277	1863	- \b 1: Single precision FPU
kenjiArai	4:e9dfb4ca4277	1864	- \b 2: Double + Single precision FPU
kenjiArai	4:e9dfb4ca4277	1865	*/
kenjiArai	4:e9dfb4ca4277	1866	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
kenjiArai	4:e9dfb4ca4277	1867	{
kenjiArai	4:e9dfb4ca4277	1868	return 0U; /* No FPU */
kenjiArai	4:e9dfb4ca4277	1869	}
kenjiArai	4:e9dfb4ca4277	1870
kenjiArai	4:e9dfb4ca4277	1871
kenjiArai	4:e9dfb4ca4277	1872	/@} end of CMSIS_Core_FpuFunctions /
kenjiArai	4:e9dfb4ca4277	1873
kenjiArai	4:e9dfb4ca4277	1874
kenjiArai	4:e9dfb4ca4277	1875
kenjiArai	4:e9dfb4ca4277	1876	/* ########################## SAU functions #################################### */
kenjiArai	4:e9dfb4ca4277	1877	/**
kenjiArai	4:e9dfb4ca4277	1878	\ingroup CMSIS_Core_FunctionInterface
kenjiArai	4:e9dfb4ca4277	1879	\defgroup CMSIS_Core_SAUFunctions SAU Functions
kenjiArai	4:e9dfb4ca4277	1880	\brief Functions that configure the SAU.
kenjiArai	4:e9dfb4ca4277	1881	@{
kenjiArai	4:e9dfb4ca4277	1882	*/
kenjiArai	4:e9dfb4ca4277	1883
kenjiArai	4:e9dfb4ca4277	1884	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kenjiArai	4:e9dfb4ca4277	1885
kenjiArai	4:e9dfb4ca4277	1886	/**
kenjiArai	4:e9dfb4ca4277	1887	\brief Enable SAU
kenjiArai	4:e9dfb4ca4277	1888	\details Enables the Security Attribution Unit (SAU).
kenjiArai	4:e9dfb4ca4277	1889	*/
kenjiArai	4:e9dfb4ca4277	1890	__STATIC_INLINE void TZ_SAU_Enable(void)
kenjiArai	4:e9dfb4ca4277	1891	{
kenjiArai	4:e9dfb4ca4277	1892	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
kenjiArai	4:e9dfb4ca4277	1893	}
kenjiArai	4:e9dfb4ca4277	1894
kenjiArai	4:e9dfb4ca4277	1895
kenjiArai	4:e9dfb4ca4277	1896
kenjiArai	4:e9dfb4ca4277	1897	/**
kenjiArai	4:e9dfb4ca4277	1898	\brief Disable SAU
kenjiArai	4:e9dfb4ca4277	1899	\details Disables the Security Attribution Unit (SAU).
kenjiArai	4:e9dfb4ca4277	1900	*/
kenjiArai	4:e9dfb4ca4277	1901	__STATIC_INLINE void TZ_SAU_Disable(void)
kenjiArai	4:e9dfb4ca4277	1902	{
kenjiArai	4:e9dfb4ca4277	1903	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
kenjiArai	4:e9dfb4ca4277	1904	}
kenjiArai	4:e9dfb4ca4277	1905
kenjiArai	4:e9dfb4ca4277	1906	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
kenjiArai	4:e9dfb4ca4277	1907
kenjiArai	4:e9dfb4ca4277	1908	/@} end of CMSIS_Core_SAUFunctions /
kenjiArai	4:e9dfb4ca4277	1909
kenjiArai	4:e9dfb4ca4277	1910
kenjiArai	4:e9dfb4ca4277	1911
kenjiArai	4:e9dfb4ca4277	1912
kenjiArai	4:e9dfb4ca4277	1913	/* ################################## SysTick function ############################################ */
kenjiArai	4:e9dfb4ca4277	1914	/**
kenjiArai	4:e9dfb4ca4277	1915	\ingroup CMSIS_Core_FunctionInterface
kenjiArai	4:e9dfb4ca4277	1916	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
kenjiArai	4:e9dfb4ca4277	1917	\brief Functions that configure the System.
kenjiArai	4:e9dfb4ca4277	1918	@{
kenjiArai	4:e9dfb4ca4277	1919	*/
kenjiArai	4:e9dfb4ca4277	1920
kenjiArai	4:e9dfb4ca4277	1921	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
kenjiArai	4:e9dfb4ca4277	1922
kenjiArai	4:e9dfb4ca4277	1923	/**
kenjiArai	4:e9dfb4ca4277	1924	\brief System Tick Configuration
kenjiArai	4:e9dfb4ca4277	1925	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
kenjiArai	4:e9dfb4ca4277	1926	Counter is in free running mode to generate periodic interrupts.
kenjiArai	4:e9dfb4ca4277	1927	\param [in] ticks Number of ticks between two interrupts.
kenjiArai	4:e9dfb4ca4277	1928	\return 0 Function succeeded.
kenjiArai	4:e9dfb4ca4277	1929	\return 1 Function failed.
kenjiArai	4:e9dfb4ca4277	1930	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
kenjiArai	4:e9dfb4ca4277	1931	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
kenjiArai	4:e9dfb4ca4277	1932	must contain a vendor-specific implementation of this function.
kenjiArai	4:e9dfb4ca4277	1933	*/
kenjiArai	4:e9dfb4ca4277	1934	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
kenjiArai	4:e9dfb4ca4277	1935	{
kenjiArai	4:e9dfb4ca4277	1936	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
kenjiArai	4:e9dfb4ca4277	1937	{
kenjiArai	4:e9dfb4ca4277	1938	return (1UL); /* Reload value impossible */
kenjiArai	4:e9dfb4ca4277	1939	}
kenjiArai	4:e9dfb4ca4277	1940
kenjiArai	4:e9dfb4ca4277	1941	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
kenjiArai	4:e9dfb4ca4277	1942	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
kenjiArai	4:e9dfb4ca4277	1943	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
kenjiArai	4:e9dfb4ca4277	1944	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
kenjiArai	4:e9dfb4ca4277	1945	SysTick_CTRL_TICKINT_Msk \|
kenjiArai	4:e9dfb4ca4277	1946	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
kenjiArai	4:e9dfb4ca4277	1947	return (0UL); /* Function successful */
kenjiArai	4:e9dfb4ca4277	1948	}
kenjiArai	4:e9dfb4ca4277	1949
kenjiArai	4:e9dfb4ca4277	1950	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kenjiArai	4:e9dfb4ca4277	1951	/**
kenjiArai	4:e9dfb4ca4277	1952	\brief System Tick Configuration (non-secure)
kenjiArai	4:e9dfb4ca4277	1953	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
kenjiArai	4:e9dfb4ca4277	1954	Counter is in free running mode to generate periodic interrupts.
kenjiArai	4:e9dfb4ca4277	1955	\param [in] ticks Number of ticks between two interrupts.
kenjiArai	4:e9dfb4ca4277	1956	\return 0 Function succeeded.
kenjiArai	4:e9dfb4ca4277	1957	\return 1 Function failed.
kenjiArai	4:e9dfb4ca4277	1958	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
kenjiArai	4:e9dfb4ca4277	1959	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
kenjiArai	4:e9dfb4ca4277	1960	must contain a vendor-specific implementation of this function.
kenjiArai	4:e9dfb4ca4277	1961
kenjiArai	4:e9dfb4ca4277	1962	*/
kenjiArai	4:e9dfb4ca4277	1963	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
kenjiArai	4:e9dfb4ca4277	1964	{
kenjiArai	4:e9dfb4ca4277	1965	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
kenjiArai	4:e9dfb4ca4277	1966	{
kenjiArai	4:e9dfb4ca4277	1967	return (1UL); /* Reload value impossible */
kenjiArai	4:e9dfb4ca4277	1968	}
kenjiArai	4:e9dfb4ca4277	1969
kenjiArai	4:e9dfb4ca4277	1970	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
kenjiArai	4:e9dfb4ca4277	1971	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
kenjiArai	4:e9dfb4ca4277	1972	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
kenjiArai	4:e9dfb4ca4277	1973	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
kenjiArai	4:e9dfb4ca4277	1974	SysTick_CTRL_TICKINT_Msk \|
kenjiArai	4:e9dfb4ca4277	1975	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
kenjiArai	4:e9dfb4ca4277	1976	return (0UL); /* Function successful */
kenjiArai	4:e9dfb4ca4277	1977	}
kenjiArai	4:e9dfb4ca4277	1978	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
kenjiArai	4:e9dfb4ca4277	1979
kenjiArai	4:e9dfb4ca4277	1980	#endif
kenjiArai	4:e9dfb4ca4277	1981
kenjiArai	4:e9dfb4ca4277	1982	/@} end of CMSIS_Core_SysTickFunctions /
kenjiArai	4:e9dfb4ca4277	1983
kenjiArai	4:e9dfb4ca4277	1984
kenjiArai	4:e9dfb4ca4277	1985
kenjiArai	4:e9dfb4ca4277	1986
kenjiArai	4:e9dfb4ca4277	1987	#ifdef __cplusplus
kenjiArai	4:e9dfb4ca4277	1988	}
kenjiArai	4:e9dfb4ca4277	1989	#endif
kenjiArai	4:e9dfb4ca4277	1990
kenjiArai	4:e9dfb4ca4277	1991	#endif /* __CORE_CM23_H_DEPENDANT */
kenjiArai	4:e9dfb4ca4277	1992
kenjiArai	4:e9dfb4ca4277	1993	#endif /* __CMSIS_GENERIC */

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Type:	Program
Created:	12 Feb 2019
Imports:	15
Forks:	0
Commits:	7
Dependents:	0
Dependencies:	3
Followers:	1

The code in this repository is Apache licensed.

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TYBLE16_os5_BASE/cmsis/TARGET_CORTEX_M/core_cm23.h@6:6dd8c932bd56, 2019-12-19 (annotated)

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