TYBLE16_mbedlized_os5_several_examples_1st

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Kenji Arai / TYBLE16_mbedlized_os5_several_examples_1st

Dependencies: nRF51_Vdd TextLCD BME280

TYBLE16_os5_BASE/cmsis/TARGET_CORTEX_M/core_armv8mml.h@4:e9dfb4ca4277, 2018-12-08 (annotated)

Committer:: kenjiArai
Date:: Sat Dec 08 02:13:04 2018 +0000
Revision:: 4:e9dfb4ca4277

test

Who changed what in which revision?

User	Revision	Line number	New contents of line
kenjiArai	4:e9dfb4ca4277	1	/************************************************************************//
kenjiArai	4:e9dfb4ca4277	2	* @file core_armv8mml.h
kenjiArai	4:e9dfb4ca4277	3	* @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
kenjiArai	4:e9dfb4ca4277	4	* @version V5.0.7
kenjiArai	4:e9dfb4ca4277	5	* @date 06. July 2018
kenjiArai	4:e9dfb4ca4277	6	******************************************************************************/
kenjiArai	4:e9dfb4ca4277	7	/*
kenjiArai	4:e9dfb4ca4277	8	* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
kenjiArai	4:e9dfb4ca4277	9	*
kenjiArai	4:e9dfb4ca4277	10	* SPDX-License-Identifier: Apache-2.0
kenjiArai	4:e9dfb4ca4277	11	*
kenjiArai	4:e9dfb4ca4277	12	* Licensed under the Apache License, Version 2.0 (the License); you may
kenjiArai	4:e9dfb4ca4277	13	* not use this file except in compliance with the License.
kenjiArai	4:e9dfb4ca4277	14	* You may obtain a copy of the License at
kenjiArai	4:e9dfb4ca4277	15	*
kenjiArai	4:e9dfb4ca4277	16	* www.apache.org/licenses/LICENSE-2.0
kenjiArai	4:e9dfb4ca4277	17	*
kenjiArai	4:e9dfb4ca4277	18	* Unless required by applicable law or agreed to in writing, software
kenjiArai	4:e9dfb4ca4277	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
kenjiArai	4:e9dfb4ca4277	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kenjiArai	4:e9dfb4ca4277	21	* See the License for the specific language governing permissions and
kenjiArai	4:e9dfb4ca4277	22	* limitations under the License.
kenjiArai	4:e9dfb4ca4277	23	*/
kenjiArai	4:e9dfb4ca4277	24
kenjiArai	4:e9dfb4ca4277	25	#if defined ( __ICCARM__ )
kenjiArai	4:e9dfb4ca4277	26	#pragma system_include /* treat file as system include file for MISRA check */
kenjiArai	4:e9dfb4ca4277	27	#elif defined (__clang__)
kenjiArai	4:e9dfb4ca4277	28	#pragma clang system_header /* treat file as system include file */
kenjiArai	4:e9dfb4ca4277	29	#endif
kenjiArai	4:e9dfb4ca4277	30
kenjiArai	4:e9dfb4ca4277	31	#ifndef __CORE_ARMV8MML_H_GENERIC
kenjiArai	4:e9dfb4ca4277	32	#define __CORE_ARMV8MML_H_GENERIC
kenjiArai	4:e9dfb4ca4277	33
kenjiArai	4:e9dfb4ca4277	34	#include <stdint.h>
kenjiArai	4:e9dfb4ca4277	35
kenjiArai	4:e9dfb4ca4277	36	#ifdef __cplusplus
kenjiArai	4:e9dfb4ca4277	37	extern "C" {
kenjiArai	4:e9dfb4ca4277	38	#endif
kenjiArai	4:e9dfb4ca4277	39
kenjiArai	4:e9dfb4ca4277	40	/**
kenjiArai	4:e9dfb4ca4277	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
kenjiArai	4:e9dfb4ca4277	42	CMSIS violates the following MISRA-C:2004 rules:
kenjiArai	4:e9dfb4ca4277	43
kenjiArai	4:e9dfb4ca4277	44	\li Required Rule 8.5, object/function definition in header file.<br>
kenjiArai	4:e9dfb4ca4277	45	Function definitions in header files are used to allow 'inlining'.
kenjiArai	4:e9dfb4ca4277	46
kenjiArai	4:e9dfb4ca4277	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
kenjiArai	4:e9dfb4ca4277	48	Unions are used for effective representation of core registers.
kenjiArai	4:e9dfb4ca4277	49
kenjiArai	4:e9dfb4ca4277	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
kenjiArai	4:e9dfb4ca4277	51	Function-like macros are used to allow more efficient code.
kenjiArai	4:e9dfb4ca4277	52	*/
kenjiArai	4:e9dfb4ca4277	53
kenjiArai	4:e9dfb4ca4277	54
kenjiArai	4:e9dfb4ca4277	55	/*******************************************************************************
kenjiArai	4:e9dfb4ca4277	56	* CMSIS definitions
kenjiArai	4:e9dfb4ca4277	57	******************************************************************************/
kenjiArai	4:e9dfb4ca4277	58	/**
kenjiArai	4:e9dfb4ca4277	59	\ingroup Cortex_ARMv8MML
kenjiArai	4:e9dfb4ca4277	60	@{
kenjiArai	4:e9dfb4ca4277	61	*/
kenjiArai	4:e9dfb4ca4277	62
kenjiArai	4:e9dfb4ca4277	63	#include "cmsis_version.h"
kenjiArai	4:e9dfb4ca4277	64
kenjiArai	4:e9dfb4ca4277	65	/* CMSIS Armv8MML definitions */
kenjiArai	4:e9dfb4ca4277	66	#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
kenjiArai	4:e9dfb4ca4277	67	#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
kenjiArai	4:e9dfb4ca4277	68	#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) \| \
kenjiArai	4:e9dfb4ca4277	69	__ARMv8MML_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
kenjiArai	4:e9dfb4ca4277	70
kenjiArai	4:e9dfb4ca4277	71	#define __CORTEX_M (81U) /!< Cortex-M Core /
kenjiArai	4:e9dfb4ca4277	72
kenjiArai	4:e9dfb4ca4277	73	/** __FPU_USED indicates whether an FPU is used or not.
kenjiArai	4:e9dfb4ca4277	74	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
kenjiArai	4:e9dfb4ca4277	75	*/
kenjiArai	4:e9dfb4ca4277	76	#if defined ( __CC_ARM )
kenjiArai	4:e9dfb4ca4277	77	#if defined __TARGET_FPU_VFP
kenjiArai	4:e9dfb4ca4277	78	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	79	#define __FPU_USED 1U
kenjiArai	4:e9dfb4ca4277	80	#else
kenjiArai	4:e9dfb4ca4277	81	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kenjiArai	4:e9dfb4ca4277	82	#define __FPU_USED 0U
kenjiArai	4:e9dfb4ca4277	83	#endif
kenjiArai	4:e9dfb4ca4277	84	#else
kenjiArai	4:e9dfb4ca4277	85	#define __FPU_USED 0U
kenjiArai	4:e9dfb4ca4277	86	#endif
kenjiArai	4:e9dfb4ca4277	87
kenjiArai	4:e9dfb4ca4277	88	#if defined(__ARM_FEATURE_DSP)
kenjiArai	4:e9dfb4ca4277	89	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	90	#define __DSP_USED 1U
kenjiArai	4:e9dfb4ca4277	91	#else
kenjiArai	4:e9dfb4ca4277	92	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
kenjiArai	4:e9dfb4ca4277	93	#define __DSP_USED 0U
kenjiArai	4:e9dfb4ca4277	94	#endif
kenjiArai	4:e9dfb4ca4277	95	#else
kenjiArai	4:e9dfb4ca4277	96	#define __DSP_USED 0U
kenjiArai	4:e9dfb4ca4277	97	#endif
kenjiArai	4:e9dfb4ca4277	98
kenjiArai	4:e9dfb4ca4277	99	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
kenjiArai	4:e9dfb4ca4277	100	#if defined __ARM_PCS_VFP
kenjiArai	4:e9dfb4ca4277	101	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	102	#define __FPU_USED 1U
kenjiArai	4:e9dfb4ca4277	103	#else
kenjiArai	4:e9dfb4ca4277	104	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kenjiArai	4:e9dfb4ca4277	105	#define __FPU_USED 0U
kenjiArai	4:e9dfb4ca4277	106	#endif
kenjiArai	4:e9dfb4ca4277	107	#else
kenjiArai	4:e9dfb4ca4277	108	#define __FPU_USED 0U
kenjiArai	4:e9dfb4ca4277	109	#endif
kenjiArai	4:e9dfb4ca4277	110
kenjiArai	4:e9dfb4ca4277	111	#if defined(__ARM_FEATURE_DSP)
kenjiArai	4:e9dfb4ca4277	112	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	113	#define __DSP_USED 1U
kenjiArai	4:e9dfb4ca4277	114	#else
kenjiArai	4:e9dfb4ca4277	115	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
kenjiArai	4:e9dfb4ca4277	116	#define __DSP_USED 0U
kenjiArai	4:e9dfb4ca4277	117	#endif
kenjiArai	4:e9dfb4ca4277	118	#else
kenjiArai	4:e9dfb4ca4277	119	#define __DSP_USED 0U
kenjiArai	4:e9dfb4ca4277	120	#endif
kenjiArai	4:e9dfb4ca4277	121
kenjiArai	4:e9dfb4ca4277	122	#elif defined ( __GNUC__ )
kenjiArai	4:e9dfb4ca4277	123	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
kenjiArai	4:e9dfb4ca4277	124	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	125	#define __FPU_USED 1U
kenjiArai	4:e9dfb4ca4277	126	#else
kenjiArai	4:e9dfb4ca4277	127	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kenjiArai	4:e9dfb4ca4277	128	#define __FPU_USED 0U
kenjiArai	4:e9dfb4ca4277	129	#endif
kenjiArai	4:e9dfb4ca4277	130	#else
kenjiArai	4:e9dfb4ca4277	131	#define __FPU_USED 0U
kenjiArai	4:e9dfb4ca4277	132	#endif
kenjiArai	4:e9dfb4ca4277	133
kenjiArai	4:e9dfb4ca4277	134	#if defined(__ARM_FEATURE_DSP)
kenjiArai	4:e9dfb4ca4277	135	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	136	#define __DSP_USED 1U
kenjiArai	4:e9dfb4ca4277	137	#else
kenjiArai	4:e9dfb4ca4277	138	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
kenjiArai	4:e9dfb4ca4277	139	#define __DSP_USED 0U
kenjiArai	4:e9dfb4ca4277	140	#endif
kenjiArai	4:e9dfb4ca4277	141	#else
kenjiArai	4:e9dfb4ca4277	142	#define __DSP_USED 0U
kenjiArai	4:e9dfb4ca4277	143	#endif
kenjiArai	4:e9dfb4ca4277	144
kenjiArai	4:e9dfb4ca4277	145	#elif defined ( __ICCARM__ )
kenjiArai	4:e9dfb4ca4277	146	#if defined __ARMVFP__
kenjiArai	4:e9dfb4ca4277	147	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	148	#define __FPU_USED 1U
kenjiArai	4:e9dfb4ca4277	149	#else
kenjiArai	4:e9dfb4ca4277	150	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kenjiArai	4:e9dfb4ca4277	151	#define __FPU_USED 0U
kenjiArai	4:e9dfb4ca4277	152	#endif
kenjiArai	4:e9dfb4ca4277	153	#else
kenjiArai	4:e9dfb4ca4277	154	#define __FPU_USED 0U
kenjiArai	4:e9dfb4ca4277	155	#endif
kenjiArai	4:e9dfb4ca4277	156
kenjiArai	4:e9dfb4ca4277	157	#if defined(__ARM_FEATURE_DSP)
kenjiArai	4:e9dfb4ca4277	158	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	159	#define __DSP_USED 1U
kenjiArai	4:e9dfb4ca4277	160	#else
kenjiArai	4:e9dfb4ca4277	161	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
kenjiArai	4:e9dfb4ca4277	162	#define __DSP_USED 0U
kenjiArai	4:e9dfb4ca4277	163	#endif
kenjiArai	4:e9dfb4ca4277	164	#else
kenjiArai	4:e9dfb4ca4277	165	#define __DSP_USED 0U
kenjiArai	4:e9dfb4ca4277	166	#endif
kenjiArai	4:e9dfb4ca4277	167
kenjiArai	4:e9dfb4ca4277	168	#elif defined ( __TI_ARM__ )
kenjiArai	4:e9dfb4ca4277	169	#if defined __TI_VFP_SUPPORT__
kenjiArai	4:e9dfb4ca4277	170	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	171	#define __FPU_USED 1U
kenjiArai	4:e9dfb4ca4277	172	#else
kenjiArai	4:e9dfb4ca4277	173	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kenjiArai	4:e9dfb4ca4277	174	#define __FPU_USED 0U
kenjiArai	4:e9dfb4ca4277	175	#endif
kenjiArai	4:e9dfb4ca4277	176	#else
kenjiArai	4:e9dfb4ca4277	177	#define __FPU_USED 0U
kenjiArai	4:e9dfb4ca4277	178	#endif
kenjiArai	4:e9dfb4ca4277	179
kenjiArai	4:e9dfb4ca4277	180	#elif defined ( __TASKING__ )
kenjiArai	4:e9dfb4ca4277	181	#if defined __FPU_VFP__
kenjiArai	4:e9dfb4ca4277	182	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	183	#define __FPU_USED 1U
kenjiArai	4:e9dfb4ca4277	184	#else
kenjiArai	4:e9dfb4ca4277	185	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kenjiArai	4:e9dfb4ca4277	186	#define __FPU_USED 0U
kenjiArai	4:e9dfb4ca4277	187	#endif
kenjiArai	4:e9dfb4ca4277	188	#else
kenjiArai	4:e9dfb4ca4277	189	#define __FPU_USED 0U
kenjiArai	4:e9dfb4ca4277	190	#endif
kenjiArai	4:e9dfb4ca4277	191
kenjiArai	4:e9dfb4ca4277	192	#elif defined ( __CSMC__ )
kenjiArai	4:e9dfb4ca4277	193	#if ( __CSMC__ & 0x400U)
kenjiArai	4:e9dfb4ca4277	194	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	195	#define __FPU_USED 1U
kenjiArai	4:e9dfb4ca4277	196	#else
kenjiArai	4:e9dfb4ca4277	197	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kenjiArai	4:e9dfb4ca4277	198	#define __FPU_USED 0U
kenjiArai	4:e9dfb4ca4277	199	#endif
kenjiArai	4:e9dfb4ca4277	200	#else
kenjiArai	4:e9dfb4ca4277	201	#define __FPU_USED 0U
kenjiArai	4:e9dfb4ca4277	202	#endif
kenjiArai	4:e9dfb4ca4277	203
kenjiArai	4:e9dfb4ca4277	204	#endif
kenjiArai	4:e9dfb4ca4277	205
kenjiArai	4:e9dfb4ca4277	206	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
kenjiArai	4:e9dfb4ca4277	207
kenjiArai	4:e9dfb4ca4277	208
kenjiArai	4:e9dfb4ca4277	209	#ifdef __cplusplus
kenjiArai	4:e9dfb4ca4277	210	}
kenjiArai	4:e9dfb4ca4277	211	#endif
kenjiArai	4:e9dfb4ca4277	212
kenjiArai	4:e9dfb4ca4277	213	#endif /* __CORE_ARMV8MML_H_GENERIC */
kenjiArai	4:e9dfb4ca4277	214
kenjiArai	4:e9dfb4ca4277	215	#ifndef __CMSIS_GENERIC
kenjiArai	4:e9dfb4ca4277	216
kenjiArai	4:e9dfb4ca4277	217	#ifndef __CORE_ARMV8MML_H_DEPENDANT
kenjiArai	4:e9dfb4ca4277	218	#define __CORE_ARMV8MML_H_DEPENDANT
kenjiArai	4:e9dfb4ca4277	219
kenjiArai	4:e9dfb4ca4277	220	#ifdef __cplusplus
kenjiArai	4:e9dfb4ca4277	221	extern "C" {
kenjiArai	4:e9dfb4ca4277	222	#endif
kenjiArai	4:e9dfb4ca4277	223
kenjiArai	4:e9dfb4ca4277	224	/* check device defines and use defaults */
kenjiArai	4:e9dfb4ca4277	225	#if defined __CHECK_DEVICE_DEFINES
kenjiArai	4:e9dfb4ca4277	226	#ifndef __ARMv8MML_REV
kenjiArai	4:e9dfb4ca4277	227	#define __ARMv8MML_REV 0x0000U
kenjiArai	4:e9dfb4ca4277	228	#warning "__ARMv8MML_REV not defined in device header file; using default!"
kenjiArai	4:e9dfb4ca4277	229	#endif
kenjiArai	4:e9dfb4ca4277	230
kenjiArai	4:e9dfb4ca4277	231	#ifndef __FPU_PRESENT
kenjiArai	4:e9dfb4ca4277	232	#define __FPU_PRESENT 0U
kenjiArai	4:e9dfb4ca4277	233	#warning "__FPU_PRESENT not defined in device header file; using default!"
kenjiArai	4:e9dfb4ca4277	234	#endif
kenjiArai	4:e9dfb4ca4277	235
kenjiArai	4:e9dfb4ca4277	236	#ifndef __MPU_PRESENT
kenjiArai	4:e9dfb4ca4277	237	#define __MPU_PRESENT 0U
kenjiArai	4:e9dfb4ca4277	238	#warning "__MPU_PRESENT not defined in device header file; using default!"
kenjiArai	4:e9dfb4ca4277	239	#endif
kenjiArai	4:e9dfb4ca4277	240
kenjiArai	4:e9dfb4ca4277	241	#ifndef __SAUREGION_PRESENT
kenjiArai	4:e9dfb4ca4277	242	#define __SAUREGION_PRESENT 0U
kenjiArai	4:e9dfb4ca4277	243	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
kenjiArai	4:e9dfb4ca4277	244	#endif
kenjiArai	4:e9dfb4ca4277	245
kenjiArai	4:e9dfb4ca4277	246	#ifndef __DSP_PRESENT
kenjiArai	4:e9dfb4ca4277	247	#define __DSP_PRESENT 0U
kenjiArai	4:e9dfb4ca4277	248	#warning "__DSP_PRESENT not defined in device header file; using default!"
kenjiArai	4:e9dfb4ca4277	249	#endif
kenjiArai	4:e9dfb4ca4277	250
kenjiArai	4:e9dfb4ca4277	251	#ifndef __NVIC_PRIO_BITS
kenjiArai	4:e9dfb4ca4277	252	#define __NVIC_PRIO_BITS 3U
kenjiArai	4:e9dfb4ca4277	253	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
kenjiArai	4:e9dfb4ca4277	254	#endif
kenjiArai	4:e9dfb4ca4277	255
kenjiArai	4:e9dfb4ca4277	256	#ifndef __Vendor_SysTickConfig
kenjiArai	4:e9dfb4ca4277	257	#define __Vendor_SysTickConfig 0U
kenjiArai	4:e9dfb4ca4277	258	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
kenjiArai	4:e9dfb4ca4277	259	#endif
kenjiArai	4:e9dfb4ca4277	260	#endif
kenjiArai	4:e9dfb4ca4277	261
kenjiArai	4:e9dfb4ca4277	262	/* IO definitions (access restrictions to peripheral registers) */
kenjiArai	4:e9dfb4ca4277	263	/**
kenjiArai	4:e9dfb4ca4277	264	\defgroup CMSIS_glob_defs CMSIS Global Defines
kenjiArai	4:e9dfb4ca4277	265
kenjiArai	4:e9dfb4ca4277	266	<strong>IO Type Qualifiers</strong> are used
kenjiArai	4:e9dfb4ca4277	267	\li to specify the access to peripheral variables.
kenjiArai	4:e9dfb4ca4277	268	\li for automatic generation of peripheral register debug information.
kenjiArai	4:e9dfb4ca4277	269	*/
kenjiArai	4:e9dfb4ca4277	270	#ifdef __cplusplus
kenjiArai	4:e9dfb4ca4277	271	#define __I volatile /!< Defines 'read only' permissions /
kenjiArai	4:e9dfb4ca4277	272	#else
kenjiArai	4:e9dfb4ca4277	273	#define __I volatile const /!< Defines 'read only' permissions /
kenjiArai	4:e9dfb4ca4277	274	#endif
kenjiArai	4:e9dfb4ca4277	275	#define __O volatile /!< Defines 'write only' permissions /
kenjiArai	4:e9dfb4ca4277	276	#define __IO volatile /!< Defines 'read / write' permissions /
kenjiArai	4:e9dfb4ca4277	277
kenjiArai	4:e9dfb4ca4277	278	/* following defines should be used for structure members */
kenjiArai	4:e9dfb4ca4277	279	#define __IM volatile const /! Defines 'read only' structure member permissions /
kenjiArai	4:e9dfb4ca4277	280	#define __OM volatile /! Defines 'write only' structure member permissions /
kenjiArai	4:e9dfb4ca4277	281	#define __IOM volatile /! Defines 'read / write' structure member permissions /
kenjiArai	4:e9dfb4ca4277	282
kenjiArai	4:e9dfb4ca4277	283	/@} end of group ARMv8MML /
kenjiArai	4:e9dfb4ca4277	284
kenjiArai	4:e9dfb4ca4277	285
kenjiArai	4:e9dfb4ca4277	286
kenjiArai	4:e9dfb4ca4277	287	/*******************************************************************************
kenjiArai	4:e9dfb4ca4277	288	* Register Abstraction
kenjiArai	4:e9dfb4ca4277	289	Core Register contain:
kenjiArai	4:e9dfb4ca4277	290	- Core Register
kenjiArai	4:e9dfb4ca4277	291	- Core NVIC Register
kenjiArai	4:e9dfb4ca4277	292	- Core SCB Register
kenjiArai	4:e9dfb4ca4277	293	- Core SysTick Register
kenjiArai	4:e9dfb4ca4277	294	- Core Debug Register
kenjiArai	4:e9dfb4ca4277	295	- Core MPU Register
kenjiArai	4:e9dfb4ca4277	296	- Core SAU Register
kenjiArai	4:e9dfb4ca4277	297	- Core FPU Register
kenjiArai	4:e9dfb4ca4277	298	******************************************************************************/
kenjiArai	4:e9dfb4ca4277	299	/**
kenjiArai	4:e9dfb4ca4277	300	\defgroup CMSIS_core_register Defines and Type Definitions
kenjiArai	4:e9dfb4ca4277	301	\brief Type definitions and defines for Cortex-M processor based devices.
kenjiArai	4:e9dfb4ca4277	302	*/
kenjiArai	4:e9dfb4ca4277	303
kenjiArai	4:e9dfb4ca4277	304	/**
kenjiArai	4:e9dfb4ca4277	305	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	306	\defgroup CMSIS_CORE Status and Control Registers
kenjiArai	4:e9dfb4ca4277	307	\brief Core Register type definitions.
kenjiArai	4:e9dfb4ca4277	308	@{
kenjiArai	4:e9dfb4ca4277	309	*/
kenjiArai	4:e9dfb4ca4277	310
kenjiArai	4:e9dfb4ca4277	311	/**
kenjiArai	4:e9dfb4ca4277	312	\brief Union type to access the Application Program Status Register (APSR).
kenjiArai	4:e9dfb4ca4277	313	*/
kenjiArai	4:e9dfb4ca4277	314	typedef union
kenjiArai	4:e9dfb4ca4277	315	{
kenjiArai	4:e9dfb4ca4277	316	struct
kenjiArai	4:e9dfb4ca4277	317	{
kenjiArai	4:e9dfb4ca4277	318	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
kenjiArai	4:e9dfb4ca4277	319	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
kenjiArai	4:e9dfb4ca4277	320	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
kenjiArai	4:e9dfb4ca4277	321	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
kenjiArai	4:e9dfb4ca4277	322	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
kenjiArai	4:e9dfb4ca4277	323	uint32_t C:1; /!< bit: 29 Carry condition code flag /
kenjiArai	4:e9dfb4ca4277	324	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
kenjiArai	4:e9dfb4ca4277	325	uint32_t N:1; /!< bit: 31 Negative condition code flag /
kenjiArai	4:e9dfb4ca4277	326	} b; /!< Structure used for bit access /
kenjiArai	4:e9dfb4ca4277	327	uint32_t w; /!< Type used for word access /
kenjiArai	4:e9dfb4ca4277	328	} APSR_Type;
kenjiArai	4:e9dfb4ca4277	329
kenjiArai	4:e9dfb4ca4277	330	/* APSR Register Definitions */
kenjiArai	4:e9dfb4ca4277	331	#define APSR_N_Pos 31U /!< APSR: N Position /
kenjiArai	4:e9dfb4ca4277	332	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
kenjiArai	4:e9dfb4ca4277	333
kenjiArai	4:e9dfb4ca4277	334	#define APSR_Z_Pos 30U /!< APSR: Z Position /
kenjiArai	4:e9dfb4ca4277	335	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
kenjiArai	4:e9dfb4ca4277	336
kenjiArai	4:e9dfb4ca4277	337	#define APSR_C_Pos 29U /!< APSR: C Position /
kenjiArai	4:e9dfb4ca4277	338	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
kenjiArai	4:e9dfb4ca4277	339
kenjiArai	4:e9dfb4ca4277	340	#define APSR_V_Pos 28U /!< APSR: V Position /
kenjiArai	4:e9dfb4ca4277	341	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
kenjiArai	4:e9dfb4ca4277	342
kenjiArai	4:e9dfb4ca4277	343	#define APSR_Q_Pos 27U /!< APSR: Q Position /
kenjiArai	4:e9dfb4ca4277	344	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
kenjiArai	4:e9dfb4ca4277	345
kenjiArai	4:e9dfb4ca4277	346	#define APSR_GE_Pos 16U /!< APSR: GE Position /
kenjiArai	4:e9dfb4ca4277	347	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
kenjiArai	4:e9dfb4ca4277	348
kenjiArai	4:e9dfb4ca4277	349
kenjiArai	4:e9dfb4ca4277	350	/**
kenjiArai	4:e9dfb4ca4277	351	\brief Union type to access the Interrupt Program Status Register (IPSR).
kenjiArai	4:e9dfb4ca4277	352	*/
kenjiArai	4:e9dfb4ca4277	353	typedef union
kenjiArai	4:e9dfb4ca4277	354	{
kenjiArai	4:e9dfb4ca4277	355	struct
kenjiArai	4:e9dfb4ca4277	356	{
kenjiArai	4:e9dfb4ca4277	357	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
kenjiArai	4:e9dfb4ca4277	358	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
kenjiArai	4:e9dfb4ca4277	359	} b; /!< Structure used for bit access /
kenjiArai	4:e9dfb4ca4277	360	uint32_t w; /!< Type used for word access /
kenjiArai	4:e9dfb4ca4277	361	} IPSR_Type;
kenjiArai	4:e9dfb4ca4277	362
kenjiArai	4:e9dfb4ca4277	363	/* IPSR Register Definitions */
kenjiArai	4:e9dfb4ca4277	364	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
kenjiArai	4:e9dfb4ca4277	365	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
kenjiArai	4:e9dfb4ca4277	366
kenjiArai	4:e9dfb4ca4277	367
kenjiArai	4:e9dfb4ca4277	368	/**
kenjiArai	4:e9dfb4ca4277	369	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
kenjiArai	4:e9dfb4ca4277	370	*/
kenjiArai	4:e9dfb4ca4277	371	typedef union
kenjiArai	4:e9dfb4ca4277	372	{
kenjiArai	4:e9dfb4ca4277	373	struct
kenjiArai	4:e9dfb4ca4277	374	{
kenjiArai	4:e9dfb4ca4277	375	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
kenjiArai	4:e9dfb4ca4277	376	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
kenjiArai	4:e9dfb4ca4277	377	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
kenjiArai	4:e9dfb4ca4277	378	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
kenjiArai	4:e9dfb4ca4277	379	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
kenjiArai	4:e9dfb4ca4277	380	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
kenjiArai	4:e9dfb4ca4277	381	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
kenjiArai	4:e9dfb4ca4277	382	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
kenjiArai	4:e9dfb4ca4277	383	uint32_t C:1; /!< bit: 29 Carry condition code flag /
kenjiArai	4:e9dfb4ca4277	384	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
kenjiArai	4:e9dfb4ca4277	385	uint32_t N:1; /!< bit: 31 Negative condition code flag /
kenjiArai	4:e9dfb4ca4277	386	} b; /!< Structure used for bit access /
kenjiArai	4:e9dfb4ca4277	387	uint32_t w; /!< Type used for word access /
kenjiArai	4:e9dfb4ca4277	388	} xPSR_Type;
kenjiArai	4:e9dfb4ca4277	389
kenjiArai	4:e9dfb4ca4277	390	/* xPSR Register Definitions */
kenjiArai	4:e9dfb4ca4277	391	#define xPSR_N_Pos 31U /!< xPSR: N Position /
kenjiArai	4:e9dfb4ca4277	392	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
kenjiArai	4:e9dfb4ca4277	393
kenjiArai	4:e9dfb4ca4277	394	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
kenjiArai	4:e9dfb4ca4277	395	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
kenjiArai	4:e9dfb4ca4277	396
kenjiArai	4:e9dfb4ca4277	397	#define xPSR_C_Pos 29U /!< xPSR: C Position /
kenjiArai	4:e9dfb4ca4277	398	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
kenjiArai	4:e9dfb4ca4277	399
kenjiArai	4:e9dfb4ca4277	400	#define xPSR_V_Pos 28U /!< xPSR: V Position /
kenjiArai	4:e9dfb4ca4277	401	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
kenjiArai	4:e9dfb4ca4277	402
kenjiArai	4:e9dfb4ca4277	403	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
kenjiArai	4:e9dfb4ca4277	404	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
kenjiArai	4:e9dfb4ca4277	405
kenjiArai	4:e9dfb4ca4277	406	#define xPSR_IT_Pos 25U /!< xPSR: IT Position /
kenjiArai	4:e9dfb4ca4277	407	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
kenjiArai	4:e9dfb4ca4277	408
kenjiArai	4:e9dfb4ca4277	409	#define xPSR_T_Pos 24U /!< xPSR: T Position /
kenjiArai	4:e9dfb4ca4277	410	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
kenjiArai	4:e9dfb4ca4277	411
kenjiArai	4:e9dfb4ca4277	412	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
kenjiArai	4:e9dfb4ca4277	413	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
kenjiArai	4:e9dfb4ca4277	414
kenjiArai	4:e9dfb4ca4277	415	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
kenjiArai	4:e9dfb4ca4277	416	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
kenjiArai	4:e9dfb4ca4277	417
kenjiArai	4:e9dfb4ca4277	418
kenjiArai	4:e9dfb4ca4277	419	/**
kenjiArai	4:e9dfb4ca4277	420	\brief Union type to access the Control Registers (CONTROL).
kenjiArai	4:e9dfb4ca4277	421	*/
kenjiArai	4:e9dfb4ca4277	422	typedef union
kenjiArai	4:e9dfb4ca4277	423	{
kenjiArai	4:e9dfb4ca4277	424	struct
kenjiArai	4:e9dfb4ca4277	425	{
kenjiArai	4:e9dfb4ca4277	426	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
kenjiArai	4:e9dfb4ca4277	427	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
kenjiArai	4:e9dfb4ca4277	428	uint32_t FPCA:1; /!< bit: 2 Floating-point context active /
kenjiArai	4:e9dfb4ca4277	429	uint32_t SFPA:1; /!< bit: 3 Secure floating-point active /
kenjiArai	4:e9dfb4ca4277	430	uint32_t _reserved1:28; /!< bit: 4..31 Reserved /
kenjiArai	4:e9dfb4ca4277	431	} b; /!< Structure used for bit access /
kenjiArai	4:e9dfb4ca4277	432	uint32_t w; /!< Type used for word access /
kenjiArai	4:e9dfb4ca4277	433	} CONTROL_Type;
kenjiArai	4:e9dfb4ca4277	434
kenjiArai	4:e9dfb4ca4277	435	/* CONTROL Register Definitions */
kenjiArai	4:e9dfb4ca4277	436	#define CONTROL_SFPA_Pos 3U /!< CONTROL: SFPA Position /
kenjiArai	4:e9dfb4ca4277	437	#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /!< CONTROL: SFPA Mask /
kenjiArai	4:e9dfb4ca4277	438
kenjiArai	4:e9dfb4ca4277	439	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
kenjiArai	4:e9dfb4ca4277	440	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
kenjiArai	4:e9dfb4ca4277	441
kenjiArai	4:e9dfb4ca4277	442	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
kenjiArai	4:e9dfb4ca4277	443	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
kenjiArai	4:e9dfb4ca4277	444
kenjiArai	4:e9dfb4ca4277	445	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
kenjiArai	4:e9dfb4ca4277	446	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
kenjiArai	4:e9dfb4ca4277	447
kenjiArai	4:e9dfb4ca4277	448	/@} end of group CMSIS_CORE /
kenjiArai	4:e9dfb4ca4277	449
kenjiArai	4:e9dfb4ca4277	450
kenjiArai	4:e9dfb4ca4277	451	/**
kenjiArai	4:e9dfb4ca4277	452	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	453	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
kenjiArai	4:e9dfb4ca4277	454	\brief Type definitions for the NVIC Registers
kenjiArai	4:e9dfb4ca4277	455	@{
kenjiArai	4:e9dfb4ca4277	456	*/
kenjiArai	4:e9dfb4ca4277	457
kenjiArai	4:e9dfb4ca4277	458	/**
kenjiArai	4:e9dfb4ca4277	459	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
kenjiArai	4:e9dfb4ca4277	460	*/
kenjiArai	4:e9dfb4ca4277	461	typedef struct
kenjiArai	4:e9dfb4ca4277	462	{
kenjiArai	4:e9dfb4ca4277	463	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
kenjiArai	4:e9dfb4ca4277	464	uint32_t RESERVED0[16U];
kenjiArai	4:e9dfb4ca4277	465	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
kenjiArai	4:e9dfb4ca4277	466	uint32_t RSERVED1[16U];
kenjiArai	4:e9dfb4ca4277	467	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
kenjiArai	4:e9dfb4ca4277	468	uint32_t RESERVED2[16U];
kenjiArai	4:e9dfb4ca4277	469	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
kenjiArai	4:e9dfb4ca4277	470	uint32_t RESERVED3[16U];
kenjiArai	4:e9dfb4ca4277	471	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
kenjiArai	4:e9dfb4ca4277	472	uint32_t RESERVED4[16U];
kenjiArai	4:e9dfb4ca4277	473	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
kenjiArai	4:e9dfb4ca4277	474	uint32_t RESERVED5[16U];
kenjiArai	4:e9dfb4ca4277	475	__IOM uint8_t IPR[496U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
kenjiArai	4:e9dfb4ca4277	476	uint32_t RESERVED6[580U];
kenjiArai	4:e9dfb4ca4277	477	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
kenjiArai	4:e9dfb4ca4277	478	} NVIC_Type;
kenjiArai	4:e9dfb4ca4277	479
kenjiArai	4:e9dfb4ca4277	480	/* Software Triggered Interrupt Register Definitions */
kenjiArai	4:e9dfb4ca4277	481	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
kenjiArai	4:e9dfb4ca4277	482	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
kenjiArai	4:e9dfb4ca4277	483
kenjiArai	4:e9dfb4ca4277	484	/@} end of group CMSIS_NVIC /
kenjiArai	4:e9dfb4ca4277	485
kenjiArai	4:e9dfb4ca4277	486
kenjiArai	4:e9dfb4ca4277	487	/**
kenjiArai	4:e9dfb4ca4277	488	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	489	\defgroup CMSIS_SCB System Control Block (SCB)
kenjiArai	4:e9dfb4ca4277	490	\brief Type definitions for the System Control Block Registers
kenjiArai	4:e9dfb4ca4277	491	@{
kenjiArai	4:e9dfb4ca4277	492	*/
kenjiArai	4:e9dfb4ca4277	493
kenjiArai	4:e9dfb4ca4277	494	/**
kenjiArai	4:e9dfb4ca4277	495	\brief Structure type to access the System Control Block (SCB).
kenjiArai	4:e9dfb4ca4277	496	*/
kenjiArai	4:e9dfb4ca4277	497	typedef struct
kenjiArai	4:e9dfb4ca4277	498	{
kenjiArai	4:e9dfb4ca4277	499	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
kenjiArai	4:e9dfb4ca4277	500	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
kenjiArai	4:e9dfb4ca4277	501	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
kenjiArai	4:e9dfb4ca4277	502	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
kenjiArai	4:e9dfb4ca4277	503	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
kenjiArai	4:e9dfb4ca4277	504	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
kenjiArai	4:e9dfb4ca4277	505	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
kenjiArai	4:e9dfb4ca4277	506	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
kenjiArai	4:e9dfb4ca4277	507	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
kenjiArai	4:e9dfb4ca4277	508	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
kenjiArai	4:e9dfb4ca4277	509	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
kenjiArai	4:e9dfb4ca4277	510	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
kenjiArai	4:e9dfb4ca4277	511	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
kenjiArai	4:e9dfb4ca4277	512	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
kenjiArai	4:e9dfb4ca4277	513	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
kenjiArai	4:e9dfb4ca4277	514	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
kenjiArai	4:e9dfb4ca4277	515	__IM uint32_t ID_ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
kenjiArai	4:e9dfb4ca4277	516	__IM uint32_t ID_MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
kenjiArai	4:e9dfb4ca4277	517	__IM uint32_t ID_ISAR[6U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
kenjiArai	4:e9dfb4ca4277	518	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
kenjiArai	4:e9dfb4ca4277	519	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
kenjiArai	4:e9dfb4ca4277	520	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
kenjiArai	4:e9dfb4ca4277	521	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
kenjiArai	4:e9dfb4ca4277	522	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
kenjiArai	4:e9dfb4ca4277	523	__IOM uint32_t NSACR; /!< Offset: 0x08C (R/W) Non-Secure Access Control Register /
kenjiArai	4:e9dfb4ca4277	524	uint32_t RESERVED3[92U];
kenjiArai	4:e9dfb4ca4277	525	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
kenjiArai	4:e9dfb4ca4277	526	uint32_t RESERVED4[15U];
kenjiArai	4:e9dfb4ca4277	527	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
kenjiArai	4:e9dfb4ca4277	528	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
kenjiArai	4:e9dfb4ca4277	529	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 /
kenjiArai	4:e9dfb4ca4277	530	uint32_t RESERVED5[1U];
kenjiArai	4:e9dfb4ca4277	531	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
kenjiArai	4:e9dfb4ca4277	532	uint32_t RESERVED6[1U];
kenjiArai	4:e9dfb4ca4277	533	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
kenjiArai	4:e9dfb4ca4277	534	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
kenjiArai	4:e9dfb4ca4277	535	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
kenjiArai	4:e9dfb4ca4277	536	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
kenjiArai	4:e9dfb4ca4277	537	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
kenjiArai	4:e9dfb4ca4277	538	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
kenjiArai	4:e9dfb4ca4277	539	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
kenjiArai	4:e9dfb4ca4277	540	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
kenjiArai	4:e9dfb4ca4277	541	uint32_t RESERVED7[6U];
kenjiArai	4:e9dfb4ca4277	542	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
kenjiArai	4:e9dfb4ca4277	543	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
kenjiArai	4:e9dfb4ca4277	544	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
kenjiArai	4:e9dfb4ca4277	545	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
kenjiArai	4:e9dfb4ca4277	546	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
kenjiArai	4:e9dfb4ca4277	547	uint32_t RESERVED8[1U];
kenjiArai	4:e9dfb4ca4277	548	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
kenjiArai	4:e9dfb4ca4277	549	} SCB_Type;
kenjiArai	4:e9dfb4ca4277	550
kenjiArai	4:e9dfb4ca4277	551	/* SCB CPUID Register Definitions */
kenjiArai	4:e9dfb4ca4277	552	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
kenjiArai	4:e9dfb4ca4277	553	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
kenjiArai	4:e9dfb4ca4277	554
kenjiArai	4:e9dfb4ca4277	555	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
kenjiArai	4:e9dfb4ca4277	556	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
kenjiArai	4:e9dfb4ca4277	557
kenjiArai	4:e9dfb4ca4277	558	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
kenjiArai	4:e9dfb4ca4277	559	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
kenjiArai	4:e9dfb4ca4277	560
kenjiArai	4:e9dfb4ca4277	561	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
kenjiArai	4:e9dfb4ca4277	562	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
kenjiArai	4:e9dfb4ca4277	563
kenjiArai	4:e9dfb4ca4277	564	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
kenjiArai	4:e9dfb4ca4277	565	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
kenjiArai	4:e9dfb4ca4277	566
kenjiArai	4:e9dfb4ca4277	567	/* SCB Interrupt Control State Register Definitions */
kenjiArai	4:e9dfb4ca4277	568	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
kenjiArai	4:e9dfb4ca4277	569	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
kenjiArai	4:e9dfb4ca4277	570
kenjiArai	4:e9dfb4ca4277	571	#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /!< SCB ICSR: NMIPENDSET Position, backward compatibility /
kenjiArai	4:e9dfb4ca4277	572	#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /!< SCB ICSR: NMIPENDSET Mask, backward compatibility /
kenjiArai	4:e9dfb4ca4277	573
kenjiArai	4:e9dfb4ca4277	574	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
kenjiArai	4:e9dfb4ca4277	575	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
kenjiArai	4:e9dfb4ca4277	576
kenjiArai	4:e9dfb4ca4277	577	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
kenjiArai	4:e9dfb4ca4277	578	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
kenjiArai	4:e9dfb4ca4277	579
kenjiArai	4:e9dfb4ca4277	580	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
kenjiArai	4:e9dfb4ca4277	581	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
kenjiArai	4:e9dfb4ca4277	582
kenjiArai	4:e9dfb4ca4277	583	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
kenjiArai	4:e9dfb4ca4277	584	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
kenjiArai	4:e9dfb4ca4277	585
kenjiArai	4:e9dfb4ca4277	586	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
kenjiArai	4:e9dfb4ca4277	587	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
kenjiArai	4:e9dfb4ca4277	588
kenjiArai	4:e9dfb4ca4277	589	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
kenjiArai	4:e9dfb4ca4277	590	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
kenjiArai	4:e9dfb4ca4277	591
kenjiArai	4:e9dfb4ca4277	592	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
kenjiArai	4:e9dfb4ca4277	593	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
kenjiArai	4:e9dfb4ca4277	594
kenjiArai	4:e9dfb4ca4277	595	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
kenjiArai	4:e9dfb4ca4277	596	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
kenjiArai	4:e9dfb4ca4277	597
kenjiArai	4:e9dfb4ca4277	598	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
kenjiArai	4:e9dfb4ca4277	599	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
kenjiArai	4:e9dfb4ca4277	600
kenjiArai	4:e9dfb4ca4277	601	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
kenjiArai	4:e9dfb4ca4277	602	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
kenjiArai	4:e9dfb4ca4277	603
kenjiArai	4:e9dfb4ca4277	604	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
kenjiArai	4:e9dfb4ca4277	605	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
kenjiArai	4:e9dfb4ca4277	606
kenjiArai	4:e9dfb4ca4277	607	/* SCB Vector Table Offset Register Definitions */
kenjiArai	4:e9dfb4ca4277	608	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
kenjiArai	4:e9dfb4ca4277	609	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
kenjiArai	4:e9dfb4ca4277	610
kenjiArai	4:e9dfb4ca4277	611	/* SCB Application Interrupt and Reset Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	612	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
kenjiArai	4:e9dfb4ca4277	613	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
kenjiArai	4:e9dfb4ca4277	614
kenjiArai	4:e9dfb4ca4277	615	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
kenjiArai	4:e9dfb4ca4277	616	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
kenjiArai	4:e9dfb4ca4277	617
kenjiArai	4:e9dfb4ca4277	618	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
kenjiArai	4:e9dfb4ca4277	619	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
kenjiArai	4:e9dfb4ca4277	620
kenjiArai	4:e9dfb4ca4277	621	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
kenjiArai	4:e9dfb4ca4277	622	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
kenjiArai	4:e9dfb4ca4277	623
kenjiArai	4:e9dfb4ca4277	624	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
kenjiArai	4:e9dfb4ca4277	625	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
kenjiArai	4:e9dfb4ca4277	626
kenjiArai	4:e9dfb4ca4277	627	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
kenjiArai	4:e9dfb4ca4277	628	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
kenjiArai	4:e9dfb4ca4277	629
kenjiArai	4:e9dfb4ca4277	630	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
kenjiArai	4:e9dfb4ca4277	631	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
kenjiArai	4:e9dfb4ca4277	632
kenjiArai	4:e9dfb4ca4277	633	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
kenjiArai	4:e9dfb4ca4277	634	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
kenjiArai	4:e9dfb4ca4277	635
kenjiArai	4:e9dfb4ca4277	636	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
kenjiArai	4:e9dfb4ca4277	637	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
kenjiArai	4:e9dfb4ca4277	638
kenjiArai	4:e9dfb4ca4277	639	/* SCB System Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	640	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
kenjiArai	4:e9dfb4ca4277	641	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
kenjiArai	4:e9dfb4ca4277	642
kenjiArai	4:e9dfb4ca4277	643	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
kenjiArai	4:e9dfb4ca4277	644	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
kenjiArai	4:e9dfb4ca4277	645
kenjiArai	4:e9dfb4ca4277	646	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
kenjiArai	4:e9dfb4ca4277	647	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
kenjiArai	4:e9dfb4ca4277	648
kenjiArai	4:e9dfb4ca4277	649	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
kenjiArai	4:e9dfb4ca4277	650	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
kenjiArai	4:e9dfb4ca4277	651
kenjiArai	4:e9dfb4ca4277	652	/* SCB Configuration Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	653	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
kenjiArai	4:e9dfb4ca4277	654	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
kenjiArai	4:e9dfb4ca4277	655
kenjiArai	4:e9dfb4ca4277	656	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
kenjiArai	4:e9dfb4ca4277	657	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
kenjiArai	4:e9dfb4ca4277	658
kenjiArai	4:e9dfb4ca4277	659	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
kenjiArai	4:e9dfb4ca4277	660	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
kenjiArai	4:e9dfb4ca4277	661
kenjiArai	4:e9dfb4ca4277	662	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
kenjiArai	4:e9dfb4ca4277	663	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
kenjiArai	4:e9dfb4ca4277	664
kenjiArai	4:e9dfb4ca4277	665	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
kenjiArai	4:e9dfb4ca4277	666	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
kenjiArai	4:e9dfb4ca4277	667
kenjiArai	4:e9dfb4ca4277	668	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
kenjiArai	4:e9dfb4ca4277	669	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
kenjiArai	4:e9dfb4ca4277	670
kenjiArai	4:e9dfb4ca4277	671	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
kenjiArai	4:e9dfb4ca4277	672	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
kenjiArai	4:e9dfb4ca4277	673
kenjiArai	4:e9dfb4ca4277	674	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
kenjiArai	4:e9dfb4ca4277	675	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
kenjiArai	4:e9dfb4ca4277	676
kenjiArai	4:e9dfb4ca4277	677	/* SCB System Handler Control and State Register Definitions */
kenjiArai	4:e9dfb4ca4277	678	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
kenjiArai	4:e9dfb4ca4277	679	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
kenjiArai	4:e9dfb4ca4277	680
kenjiArai	4:e9dfb4ca4277	681	#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /!< SCB SHCSR: SECUREFAULTPENDED Position /
kenjiArai	4:e9dfb4ca4277	682	#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /!< SCB SHCSR: SECUREFAULTPENDED Mask /
kenjiArai	4:e9dfb4ca4277	683
kenjiArai	4:e9dfb4ca4277	684	#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /!< SCB SHCSR: SECUREFAULTENA Position /
kenjiArai	4:e9dfb4ca4277	685	#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /!< SCB SHCSR: SECUREFAULTENA Mask /
kenjiArai	4:e9dfb4ca4277	686
kenjiArai	4:e9dfb4ca4277	687	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
kenjiArai	4:e9dfb4ca4277	688	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
kenjiArai	4:e9dfb4ca4277	689
kenjiArai	4:e9dfb4ca4277	690	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
kenjiArai	4:e9dfb4ca4277	691	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
kenjiArai	4:e9dfb4ca4277	692
kenjiArai	4:e9dfb4ca4277	693	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
kenjiArai	4:e9dfb4ca4277	694	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
kenjiArai	4:e9dfb4ca4277	695
kenjiArai	4:e9dfb4ca4277	696	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
kenjiArai	4:e9dfb4ca4277	697	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
kenjiArai	4:e9dfb4ca4277	698
kenjiArai	4:e9dfb4ca4277	699	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
kenjiArai	4:e9dfb4ca4277	700	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
kenjiArai	4:e9dfb4ca4277	701
kenjiArai	4:e9dfb4ca4277	702	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
kenjiArai	4:e9dfb4ca4277	703	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
kenjiArai	4:e9dfb4ca4277	704
kenjiArai	4:e9dfb4ca4277	705	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
kenjiArai	4:e9dfb4ca4277	706	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
kenjiArai	4:e9dfb4ca4277	707
kenjiArai	4:e9dfb4ca4277	708	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
kenjiArai	4:e9dfb4ca4277	709	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
kenjiArai	4:e9dfb4ca4277	710
kenjiArai	4:e9dfb4ca4277	711	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
kenjiArai	4:e9dfb4ca4277	712	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
kenjiArai	4:e9dfb4ca4277	713
kenjiArai	4:e9dfb4ca4277	714	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
kenjiArai	4:e9dfb4ca4277	715	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
kenjiArai	4:e9dfb4ca4277	716
kenjiArai	4:e9dfb4ca4277	717	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
kenjiArai	4:e9dfb4ca4277	718	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
kenjiArai	4:e9dfb4ca4277	719
kenjiArai	4:e9dfb4ca4277	720	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
kenjiArai	4:e9dfb4ca4277	721	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
kenjiArai	4:e9dfb4ca4277	722
kenjiArai	4:e9dfb4ca4277	723	#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /!< SCB SHCSR: SECUREFAULTACT Position /
kenjiArai	4:e9dfb4ca4277	724	#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /!< SCB SHCSR: SECUREFAULTACT Mask /
kenjiArai	4:e9dfb4ca4277	725
kenjiArai	4:e9dfb4ca4277	726	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
kenjiArai	4:e9dfb4ca4277	727	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
kenjiArai	4:e9dfb4ca4277	728
kenjiArai	4:e9dfb4ca4277	729	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
kenjiArai	4:e9dfb4ca4277	730	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
kenjiArai	4:e9dfb4ca4277	731
kenjiArai	4:e9dfb4ca4277	732	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
kenjiArai	4:e9dfb4ca4277	733	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
kenjiArai	4:e9dfb4ca4277	734
kenjiArai	4:e9dfb4ca4277	735	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
kenjiArai	4:e9dfb4ca4277	736	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
kenjiArai	4:e9dfb4ca4277	737
kenjiArai	4:e9dfb4ca4277	738	/* SCB Configurable Fault Status Register Definitions */
kenjiArai	4:e9dfb4ca4277	739	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
kenjiArai	4:e9dfb4ca4277	740	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
kenjiArai	4:e9dfb4ca4277	741
kenjiArai	4:e9dfb4ca4277	742	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
kenjiArai	4:e9dfb4ca4277	743	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
kenjiArai	4:e9dfb4ca4277	744
kenjiArai	4:e9dfb4ca4277	745	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
kenjiArai	4:e9dfb4ca4277	746	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
kenjiArai	4:e9dfb4ca4277	747
kenjiArai	4:e9dfb4ca4277	748	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
kenjiArai	4:e9dfb4ca4277	749	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
kenjiArai	4:e9dfb4ca4277	750	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
kenjiArai	4:e9dfb4ca4277	751
kenjiArai	4:e9dfb4ca4277	752	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
kenjiArai	4:e9dfb4ca4277	753	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
kenjiArai	4:e9dfb4ca4277	754
kenjiArai	4:e9dfb4ca4277	755	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
kenjiArai	4:e9dfb4ca4277	756	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
kenjiArai	4:e9dfb4ca4277	757
kenjiArai	4:e9dfb4ca4277	758	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
kenjiArai	4:e9dfb4ca4277	759	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
kenjiArai	4:e9dfb4ca4277	760
kenjiArai	4:e9dfb4ca4277	761	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
kenjiArai	4:e9dfb4ca4277	762	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
kenjiArai	4:e9dfb4ca4277	763
kenjiArai	4:e9dfb4ca4277	764	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
kenjiArai	4:e9dfb4ca4277	765	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
kenjiArai	4:e9dfb4ca4277	766
kenjiArai	4:e9dfb4ca4277	767	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
kenjiArai	4:e9dfb4ca4277	768	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
kenjiArai	4:e9dfb4ca4277	769	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
kenjiArai	4:e9dfb4ca4277	770
kenjiArai	4:e9dfb4ca4277	771	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
kenjiArai	4:e9dfb4ca4277	772	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
kenjiArai	4:e9dfb4ca4277	773
kenjiArai	4:e9dfb4ca4277	774	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
kenjiArai	4:e9dfb4ca4277	775	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
kenjiArai	4:e9dfb4ca4277	776
kenjiArai	4:e9dfb4ca4277	777	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
kenjiArai	4:e9dfb4ca4277	778	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
kenjiArai	4:e9dfb4ca4277	779
kenjiArai	4:e9dfb4ca4277	780	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
kenjiArai	4:e9dfb4ca4277	781	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
kenjiArai	4:e9dfb4ca4277	782
kenjiArai	4:e9dfb4ca4277	783	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
kenjiArai	4:e9dfb4ca4277	784	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
kenjiArai	4:e9dfb4ca4277	785
kenjiArai	4:e9dfb4ca4277	786	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
kenjiArai	4:e9dfb4ca4277	787	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
kenjiArai	4:e9dfb4ca4277	788
kenjiArai	4:e9dfb4ca4277	789	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
kenjiArai	4:e9dfb4ca4277	790	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
kenjiArai	4:e9dfb4ca4277	791	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
kenjiArai	4:e9dfb4ca4277	792
kenjiArai	4:e9dfb4ca4277	793	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
kenjiArai	4:e9dfb4ca4277	794	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
kenjiArai	4:e9dfb4ca4277	795
kenjiArai	4:e9dfb4ca4277	796	#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /!< SCB CFSR (UFSR): STKOF Position /
kenjiArai	4:e9dfb4ca4277	797	#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /!< SCB CFSR (UFSR): STKOF Mask /
kenjiArai	4:e9dfb4ca4277	798
kenjiArai	4:e9dfb4ca4277	799	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
kenjiArai	4:e9dfb4ca4277	800	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
kenjiArai	4:e9dfb4ca4277	801
kenjiArai	4:e9dfb4ca4277	802	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
kenjiArai	4:e9dfb4ca4277	803	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
kenjiArai	4:e9dfb4ca4277	804
kenjiArai	4:e9dfb4ca4277	805	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
kenjiArai	4:e9dfb4ca4277	806	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
kenjiArai	4:e9dfb4ca4277	807
kenjiArai	4:e9dfb4ca4277	808	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
kenjiArai	4:e9dfb4ca4277	809	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
kenjiArai	4:e9dfb4ca4277	810
kenjiArai	4:e9dfb4ca4277	811	/* SCB Hard Fault Status Register Definitions */
kenjiArai	4:e9dfb4ca4277	812	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
kenjiArai	4:e9dfb4ca4277	813	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
kenjiArai	4:e9dfb4ca4277	814
kenjiArai	4:e9dfb4ca4277	815	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
kenjiArai	4:e9dfb4ca4277	816	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
kenjiArai	4:e9dfb4ca4277	817
kenjiArai	4:e9dfb4ca4277	818	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
kenjiArai	4:e9dfb4ca4277	819	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
kenjiArai	4:e9dfb4ca4277	820
kenjiArai	4:e9dfb4ca4277	821	/* SCB Debug Fault Status Register Definitions */
kenjiArai	4:e9dfb4ca4277	822	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
kenjiArai	4:e9dfb4ca4277	823	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
kenjiArai	4:e9dfb4ca4277	824
kenjiArai	4:e9dfb4ca4277	825	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
kenjiArai	4:e9dfb4ca4277	826	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
kenjiArai	4:e9dfb4ca4277	827
kenjiArai	4:e9dfb4ca4277	828	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
kenjiArai	4:e9dfb4ca4277	829	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
kenjiArai	4:e9dfb4ca4277	830
kenjiArai	4:e9dfb4ca4277	831	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
kenjiArai	4:e9dfb4ca4277	832	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
kenjiArai	4:e9dfb4ca4277	833
kenjiArai	4:e9dfb4ca4277	834	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
kenjiArai	4:e9dfb4ca4277	835	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
kenjiArai	4:e9dfb4ca4277	836
kenjiArai	4:e9dfb4ca4277	837	/* SCB Non-Secure Access Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	838	#define SCB_NSACR_CP11_Pos 11U /!< SCB NSACR: CP11 Position /
kenjiArai	4:e9dfb4ca4277	839	#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /!< SCB NSACR: CP11 Mask /
kenjiArai	4:e9dfb4ca4277	840
kenjiArai	4:e9dfb4ca4277	841	#define SCB_NSACR_CP10_Pos 10U /!< SCB NSACR: CP10 Position /
kenjiArai	4:e9dfb4ca4277	842	#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /!< SCB NSACR: CP10 Mask /
kenjiArai	4:e9dfb4ca4277	843
kenjiArai	4:e9dfb4ca4277	844	#define SCB_NSACR_CPn_Pos 0U /!< SCB NSACR: CPn Position /
kenjiArai	4:e9dfb4ca4277	845	#define SCB_NSACR_CPn_Msk (1UL /<< SCB_NSACR_CPn_Pos/) /!< SCB NSACR: CPn Mask /
kenjiArai	4:e9dfb4ca4277	846
kenjiArai	4:e9dfb4ca4277	847	/* SCB Cache Level ID Register Definitions */
kenjiArai	4:e9dfb4ca4277	848	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
kenjiArai	4:e9dfb4ca4277	849	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
kenjiArai	4:e9dfb4ca4277	850
kenjiArai	4:e9dfb4ca4277	851	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
kenjiArai	4:e9dfb4ca4277	852	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
kenjiArai	4:e9dfb4ca4277	853
kenjiArai	4:e9dfb4ca4277	854	/* SCB Cache Type Register Definitions */
kenjiArai	4:e9dfb4ca4277	855	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
kenjiArai	4:e9dfb4ca4277	856	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
kenjiArai	4:e9dfb4ca4277	857
kenjiArai	4:e9dfb4ca4277	858	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
kenjiArai	4:e9dfb4ca4277	859	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
kenjiArai	4:e9dfb4ca4277	860
kenjiArai	4:e9dfb4ca4277	861	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
kenjiArai	4:e9dfb4ca4277	862	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
kenjiArai	4:e9dfb4ca4277	863
kenjiArai	4:e9dfb4ca4277	864	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
kenjiArai	4:e9dfb4ca4277	865	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
kenjiArai	4:e9dfb4ca4277	866
kenjiArai	4:e9dfb4ca4277	867	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
kenjiArai	4:e9dfb4ca4277	868	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
kenjiArai	4:e9dfb4ca4277	869
kenjiArai	4:e9dfb4ca4277	870	/* SCB Cache Size ID Register Definitions */
kenjiArai	4:e9dfb4ca4277	871	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
kenjiArai	4:e9dfb4ca4277	872	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
kenjiArai	4:e9dfb4ca4277	873
kenjiArai	4:e9dfb4ca4277	874	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
kenjiArai	4:e9dfb4ca4277	875	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
kenjiArai	4:e9dfb4ca4277	876
kenjiArai	4:e9dfb4ca4277	877	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
kenjiArai	4:e9dfb4ca4277	878	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
kenjiArai	4:e9dfb4ca4277	879
kenjiArai	4:e9dfb4ca4277	880	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
kenjiArai	4:e9dfb4ca4277	881	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
kenjiArai	4:e9dfb4ca4277	882
kenjiArai	4:e9dfb4ca4277	883	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
kenjiArai	4:e9dfb4ca4277	884	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
kenjiArai	4:e9dfb4ca4277	885
kenjiArai	4:e9dfb4ca4277	886	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
kenjiArai	4:e9dfb4ca4277	887	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
kenjiArai	4:e9dfb4ca4277	888
kenjiArai	4:e9dfb4ca4277	889	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
kenjiArai	4:e9dfb4ca4277	890	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
kenjiArai	4:e9dfb4ca4277	891
kenjiArai	4:e9dfb4ca4277	892	/* SCB Cache Size Selection Register Definitions */
kenjiArai	4:e9dfb4ca4277	893	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
kenjiArai	4:e9dfb4ca4277	894	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
kenjiArai	4:e9dfb4ca4277	895
kenjiArai	4:e9dfb4ca4277	896	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
kenjiArai	4:e9dfb4ca4277	897	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
kenjiArai	4:e9dfb4ca4277	898
kenjiArai	4:e9dfb4ca4277	899	/* SCB Software Triggered Interrupt Register Definitions */
kenjiArai	4:e9dfb4ca4277	900	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
kenjiArai	4:e9dfb4ca4277	901	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
kenjiArai	4:e9dfb4ca4277	902
kenjiArai	4:e9dfb4ca4277	903	/* SCB D-Cache Invalidate by Set-way Register Definitions */
kenjiArai	4:e9dfb4ca4277	904	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
kenjiArai	4:e9dfb4ca4277	905	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
kenjiArai	4:e9dfb4ca4277	906
kenjiArai	4:e9dfb4ca4277	907	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
kenjiArai	4:e9dfb4ca4277	908	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
kenjiArai	4:e9dfb4ca4277	909
kenjiArai	4:e9dfb4ca4277	910	/* SCB D-Cache Clean by Set-way Register Definitions */
kenjiArai	4:e9dfb4ca4277	911	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
kenjiArai	4:e9dfb4ca4277	912	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
kenjiArai	4:e9dfb4ca4277	913
kenjiArai	4:e9dfb4ca4277	914	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
kenjiArai	4:e9dfb4ca4277	915	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
kenjiArai	4:e9dfb4ca4277	916
kenjiArai	4:e9dfb4ca4277	917	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
kenjiArai	4:e9dfb4ca4277	918	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
kenjiArai	4:e9dfb4ca4277	919	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
kenjiArai	4:e9dfb4ca4277	920
kenjiArai	4:e9dfb4ca4277	921	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
kenjiArai	4:e9dfb4ca4277	922	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
kenjiArai	4:e9dfb4ca4277	923
kenjiArai	4:e9dfb4ca4277	924	/* Instruction Tightly-Coupled Memory Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	925	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
kenjiArai	4:e9dfb4ca4277	926	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
kenjiArai	4:e9dfb4ca4277	927
kenjiArai	4:e9dfb4ca4277	928	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
kenjiArai	4:e9dfb4ca4277	929	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
kenjiArai	4:e9dfb4ca4277	930
kenjiArai	4:e9dfb4ca4277	931	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
kenjiArai	4:e9dfb4ca4277	932	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
kenjiArai	4:e9dfb4ca4277	933
kenjiArai	4:e9dfb4ca4277	934	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
kenjiArai	4:e9dfb4ca4277	935	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
kenjiArai	4:e9dfb4ca4277	936
kenjiArai	4:e9dfb4ca4277	937	/* Data Tightly-Coupled Memory Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	938	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
kenjiArai	4:e9dfb4ca4277	939	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
kenjiArai	4:e9dfb4ca4277	940
kenjiArai	4:e9dfb4ca4277	941	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
kenjiArai	4:e9dfb4ca4277	942	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
kenjiArai	4:e9dfb4ca4277	943
kenjiArai	4:e9dfb4ca4277	944	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
kenjiArai	4:e9dfb4ca4277	945	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
kenjiArai	4:e9dfb4ca4277	946
kenjiArai	4:e9dfb4ca4277	947	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
kenjiArai	4:e9dfb4ca4277	948	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
kenjiArai	4:e9dfb4ca4277	949
kenjiArai	4:e9dfb4ca4277	950	/* AHBP Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	951	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
kenjiArai	4:e9dfb4ca4277	952	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
kenjiArai	4:e9dfb4ca4277	953
kenjiArai	4:e9dfb4ca4277	954	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
kenjiArai	4:e9dfb4ca4277	955	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
kenjiArai	4:e9dfb4ca4277	956
kenjiArai	4:e9dfb4ca4277	957	/* L1 Cache Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	958	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
kenjiArai	4:e9dfb4ca4277	959	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
kenjiArai	4:e9dfb4ca4277	960
kenjiArai	4:e9dfb4ca4277	961	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
kenjiArai	4:e9dfb4ca4277	962	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
kenjiArai	4:e9dfb4ca4277	963
kenjiArai	4:e9dfb4ca4277	964	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
kenjiArai	4:e9dfb4ca4277	965	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
kenjiArai	4:e9dfb4ca4277	966
kenjiArai	4:e9dfb4ca4277	967	/* AHBS Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	968	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
kenjiArai	4:e9dfb4ca4277	969	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
kenjiArai	4:e9dfb4ca4277	970
kenjiArai	4:e9dfb4ca4277	971	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
kenjiArai	4:e9dfb4ca4277	972	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
kenjiArai	4:e9dfb4ca4277	973
kenjiArai	4:e9dfb4ca4277	974	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
kenjiArai	4:e9dfb4ca4277	975	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
kenjiArai	4:e9dfb4ca4277	976
kenjiArai	4:e9dfb4ca4277	977	/* Auxiliary Bus Fault Status Register Definitions */
kenjiArai	4:e9dfb4ca4277	978	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
kenjiArai	4:e9dfb4ca4277	979	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
kenjiArai	4:e9dfb4ca4277	980
kenjiArai	4:e9dfb4ca4277	981	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
kenjiArai	4:e9dfb4ca4277	982	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
kenjiArai	4:e9dfb4ca4277	983
kenjiArai	4:e9dfb4ca4277	984	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
kenjiArai	4:e9dfb4ca4277	985	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
kenjiArai	4:e9dfb4ca4277	986
kenjiArai	4:e9dfb4ca4277	987	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
kenjiArai	4:e9dfb4ca4277	988	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
kenjiArai	4:e9dfb4ca4277	989
kenjiArai	4:e9dfb4ca4277	990	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
kenjiArai	4:e9dfb4ca4277	991	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
kenjiArai	4:e9dfb4ca4277	992
kenjiArai	4:e9dfb4ca4277	993	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
kenjiArai	4:e9dfb4ca4277	994	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
kenjiArai	4:e9dfb4ca4277	995
kenjiArai	4:e9dfb4ca4277	996	/@} end of group CMSIS_SCB /
kenjiArai	4:e9dfb4ca4277	997
kenjiArai	4:e9dfb4ca4277	998
kenjiArai	4:e9dfb4ca4277	999	/**
kenjiArai	4:e9dfb4ca4277	1000	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	1001	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
kenjiArai	4:e9dfb4ca4277	1002	\brief Type definitions for the System Control and ID Register not in the SCB
kenjiArai	4:e9dfb4ca4277	1003	@{
kenjiArai	4:e9dfb4ca4277	1004	*/
kenjiArai	4:e9dfb4ca4277	1005
kenjiArai	4:e9dfb4ca4277	1006	/**
kenjiArai	4:e9dfb4ca4277	1007	\brief Structure type to access the System Control and ID Register not in the SCB.
kenjiArai	4:e9dfb4ca4277	1008	*/
kenjiArai	4:e9dfb4ca4277	1009	typedef struct
kenjiArai	4:e9dfb4ca4277	1010	{
kenjiArai	4:e9dfb4ca4277	1011	uint32_t RESERVED0[1U];
kenjiArai	4:e9dfb4ca4277	1012	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
kenjiArai	4:e9dfb4ca4277	1013	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
kenjiArai	4:e9dfb4ca4277	1014	__IOM uint32_t CPPWR; /!< Offset: 0x00C (R/W) Coprocessor Power Control Register /
kenjiArai	4:e9dfb4ca4277	1015	} SCnSCB_Type;
kenjiArai	4:e9dfb4ca4277	1016
kenjiArai	4:e9dfb4ca4277	1017	/* Interrupt Controller Type Register Definitions */
kenjiArai	4:e9dfb4ca4277	1018	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
kenjiArai	4:e9dfb4ca4277	1019	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
kenjiArai	4:e9dfb4ca4277	1020
kenjiArai	4:e9dfb4ca4277	1021	/@} end of group CMSIS_SCnotSCB /
kenjiArai	4:e9dfb4ca4277	1022
kenjiArai	4:e9dfb4ca4277	1023
kenjiArai	4:e9dfb4ca4277	1024	/**
kenjiArai	4:e9dfb4ca4277	1025	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	1026	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
kenjiArai	4:e9dfb4ca4277	1027	\brief Type definitions for the System Timer Registers.
kenjiArai	4:e9dfb4ca4277	1028	@{
kenjiArai	4:e9dfb4ca4277	1029	*/
kenjiArai	4:e9dfb4ca4277	1030
kenjiArai	4:e9dfb4ca4277	1031	/**
kenjiArai	4:e9dfb4ca4277	1032	\brief Structure type to access the System Timer (SysTick).
kenjiArai	4:e9dfb4ca4277	1033	*/
kenjiArai	4:e9dfb4ca4277	1034	typedef struct
kenjiArai	4:e9dfb4ca4277	1035	{
kenjiArai	4:e9dfb4ca4277	1036	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
kenjiArai	4:e9dfb4ca4277	1037	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
kenjiArai	4:e9dfb4ca4277	1038	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
kenjiArai	4:e9dfb4ca4277	1039	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
kenjiArai	4:e9dfb4ca4277	1040	} SysTick_Type;
kenjiArai	4:e9dfb4ca4277	1041
kenjiArai	4:e9dfb4ca4277	1042	/* SysTick Control / Status Register Definitions */
kenjiArai	4:e9dfb4ca4277	1043	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
kenjiArai	4:e9dfb4ca4277	1044	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
kenjiArai	4:e9dfb4ca4277	1045
kenjiArai	4:e9dfb4ca4277	1046	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
kenjiArai	4:e9dfb4ca4277	1047	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
kenjiArai	4:e9dfb4ca4277	1048
kenjiArai	4:e9dfb4ca4277	1049	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
kenjiArai	4:e9dfb4ca4277	1050	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
kenjiArai	4:e9dfb4ca4277	1051
kenjiArai	4:e9dfb4ca4277	1052	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
kenjiArai	4:e9dfb4ca4277	1053	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
kenjiArai	4:e9dfb4ca4277	1054
kenjiArai	4:e9dfb4ca4277	1055	/* SysTick Reload Register Definitions */
kenjiArai	4:e9dfb4ca4277	1056	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
kenjiArai	4:e9dfb4ca4277	1057	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
kenjiArai	4:e9dfb4ca4277	1058
kenjiArai	4:e9dfb4ca4277	1059	/* SysTick Current Register Definitions */
kenjiArai	4:e9dfb4ca4277	1060	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
kenjiArai	4:e9dfb4ca4277	1061	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
kenjiArai	4:e9dfb4ca4277	1062
kenjiArai	4:e9dfb4ca4277	1063	/* SysTick Calibration Register Definitions */
kenjiArai	4:e9dfb4ca4277	1064	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
kenjiArai	4:e9dfb4ca4277	1065	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
kenjiArai	4:e9dfb4ca4277	1066
kenjiArai	4:e9dfb4ca4277	1067	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
kenjiArai	4:e9dfb4ca4277	1068	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
kenjiArai	4:e9dfb4ca4277	1069
kenjiArai	4:e9dfb4ca4277	1070	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
kenjiArai	4:e9dfb4ca4277	1071	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
kenjiArai	4:e9dfb4ca4277	1072
kenjiArai	4:e9dfb4ca4277	1073	/@} end of group CMSIS_SysTick /
kenjiArai	4:e9dfb4ca4277	1074
kenjiArai	4:e9dfb4ca4277	1075
kenjiArai	4:e9dfb4ca4277	1076	/**
kenjiArai	4:e9dfb4ca4277	1077	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	1078	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
kenjiArai	4:e9dfb4ca4277	1079	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
kenjiArai	4:e9dfb4ca4277	1080	@{
kenjiArai	4:e9dfb4ca4277	1081	*/
kenjiArai	4:e9dfb4ca4277	1082
kenjiArai	4:e9dfb4ca4277	1083	/**
kenjiArai	4:e9dfb4ca4277	1084	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
kenjiArai	4:e9dfb4ca4277	1085	*/
kenjiArai	4:e9dfb4ca4277	1086	typedef struct
kenjiArai	4:e9dfb4ca4277	1087	{
kenjiArai	4:e9dfb4ca4277	1088	__OM union
kenjiArai	4:e9dfb4ca4277	1089	{
kenjiArai	4:e9dfb4ca4277	1090	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
kenjiArai	4:e9dfb4ca4277	1091	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
kenjiArai	4:e9dfb4ca4277	1092	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
kenjiArai	4:e9dfb4ca4277	1093	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
kenjiArai	4:e9dfb4ca4277	1094	uint32_t RESERVED0[864U];
kenjiArai	4:e9dfb4ca4277	1095	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
kenjiArai	4:e9dfb4ca4277	1096	uint32_t RESERVED1[15U];
kenjiArai	4:e9dfb4ca4277	1097	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
kenjiArai	4:e9dfb4ca4277	1098	uint32_t RESERVED2[15U];
kenjiArai	4:e9dfb4ca4277	1099	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
kenjiArai	4:e9dfb4ca4277	1100	uint32_t RESERVED3[29U];
kenjiArai	4:e9dfb4ca4277	1101	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
kenjiArai	4:e9dfb4ca4277	1102	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
kenjiArai	4:e9dfb4ca4277	1103	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
kenjiArai	4:e9dfb4ca4277	1104	uint32_t RESERVED4[43U];
kenjiArai	4:e9dfb4ca4277	1105	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
kenjiArai	4:e9dfb4ca4277	1106	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
kenjiArai	4:e9dfb4ca4277	1107	uint32_t RESERVED5[1U];
kenjiArai	4:e9dfb4ca4277	1108	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) ITM Device Architecture Register /
kenjiArai	4:e9dfb4ca4277	1109	uint32_t RESERVED6[4U];
kenjiArai	4:e9dfb4ca4277	1110	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
kenjiArai	4:e9dfb4ca4277	1111	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
kenjiArai	4:e9dfb4ca4277	1112	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
kenjiArai	4:e9dfb4ca4277	1113	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
kenjiArai	4:e9dfb4ca4277	1114	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
kenjiArai	4:e9dfb4ca4277	1115	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
kenjiArai	4:e9dfb4ca4277	1116	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
kenjiArai	4:e9dfb4ca4277	1117	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
kenjiArai	4:e9dfb4ca4277	1118	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
kenjiArai	4:e9dfb4ca4277	1119	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
kenjiArai	4:e9dfb4ca4277	1120	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
kenjiArai	4:e9dfb4ca4277	1121	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
kenjiArai	4:e9dfb4ca4277	1122	} ITM_Type;
kenjiArai	4:e9dfb4ca4277	1123
kenjiArai	4:e9dfb4ca4277	1124	/* ITM Stimulus Port Register Definitions */
kenjiArai	4:e9dfb4ca4277	1125	#define ITM_STIM_DISABLED_Pos 1U /!< ITM STIM: DISABLED Position /
kenjiArai	4:e9dfb4ca4277	1126	#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /!< ITM STIM: DISABLED Mask /
kenjiArai	4:e9dfb4ca4277	1127
kenjiArai	4:e9dfb4ca4277	1128	#define ITM_STIM_FIFOREADY_Pos 0U /!< ITM STIM: FIFOREADY Position /
kenjiArai	4:e9dfb4ca4277	1129	#define ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/) /!< ITM STIM: FIFOREADY Mask /
kenjiArai	4:e9dfb4ca4277	1130
kenjiArai	4:e9dfb4ca4277	1131	/* ITM Trace Privilege Register Definitions */
kenjiArai	4:e9dfb4ca4277	1132	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
kenjiArai	4:e9dfb4ca4277	1133	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
kenjiArai	4:e9dfb4ca4277	1134
kenjiArai	4:e9dfb4ca4277	1135	/* ITM Trace Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	1136	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
kenjiArai	4:e9dfb4ca4277	1137	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
kenjiArai	4:e9dfb4ca4277	1138
kenjiArai	4:e9dfb4ca4277	1139	#define ITM_TCR_TRACEBUSID_Pos 16U /!< ITM TCR: ATBID Position /
kenjiArai	4:e9dfb4ca4277	1140	#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /!< ITM TCR: ATBID Mask /
kenjiArai	4:e9dfb4ca4277	1141
kenjiArai	4:e9dfb4ca4277	1142	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
kenjiArai	4:e9dfb4ca4277	1143	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
kenjiArai	4:e9dfb4ca4277	1144
kenjiArai	4:e9dfb4ca4277	1145	#define ITM_TCR_TSPRESCALE_Pos 8U /!< ITM TCR: TSPRESCALE Position /
kenjiArai	4:e9dfb4ca4277	1146	#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /!< ITM TCR: TSPRESCALE Mask /
kenjiArai	4:e9dfb4ca4277	1147
kenjiArai	4:e9dfb4ca4277	1148	#define ITM_TCR_STALLENA_Pos 5U /!< ITM TCR: STALLENA Position /
kenjiArai	4:e9dfb4ca4277	1149	#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /!< ITM TCR: STALLENA Mask /
kenjiArai	4:e9dfb4ca4277	1150
kenjiArai	4:e9dfb4ca4277	1151	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
kenjiArai	4:e9dfb4ca4277	1152	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
kenjiArai	4:e9dfb4ca4277	1153
kenjiArai	4:e9dfb4ca4277	1154	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
kenjiArai	4:e9dfb4ca4277	1155	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
kenjiArai	4:e9dfb4ca4277	1156
kenjiArai	4:e9dfb4ca4277	1157	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
kenjiArai	4:e9dfb4ca4277	1158	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
kenjiArai	4:e9dfb4ca4277	1159
kenjiArai	4:e9dfb4ca4277	1160	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
kenjiArai	4:e9dfb4ca4277	1161	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
kenjiArai	4:e9dfb4ca4277	1162
kenjiArai	4:e9dfb4ca4277	1163	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
kenjiArai	4:e9dfb4ca4277	1164	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
kenjiArai	4:e9dfb4ca4277	1165
kenjiArai	4:e9dfb4ca4277	1166	/* ITM Integration Write Register Definitions */
kenjiArai	4:e9dfb4ca4277	1167	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
kenjiArai	4:e9dfb4ca4277	1168	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
kenjiArai	4:e9dfb4ca4277	1169
kenjiArai	4:e9dfb4ca4277	1170	/* ITM Integration Read Register Definitions */
kenjiArai	4:e9dfb4ca4277	1171	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
kenjiArai	4:e9dfb4ca4277	1172	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
kenjiArai	4:e9dfb4ca4277	1173
kenjiArai	4:e9dfb4ca4277	1174	/* ITM Integration Mode Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	1175	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
kenjiArai	4:e9dfb4ca4277	1176	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
kenjiArai	4:e9dfb4ca4277	1177
kenjiArai	4:e9dfb4ca4277	1178	/* ITM Lock Status Register Definitions */
kenjiArai	4:e9dfb4ca4277	1179	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
kenjiArai	4:e9dfb4ca4277	1180	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
kenjiArai	4:e9dfb4ca4277	1181
kenjiArai	4:e9dfb4ca4277	1182	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
kenjiArai	4:e9dfb4ca4277	1183	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
kenjiArai	4:e9dfb4ca4277	1184
kenjiArai	4:e9dfb4ca4277	1185	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
kenjiArai	4:e9dfb4ca4277	1186	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
kenjiArai	4:e9dfb4ca4277	1187
kenjiArai	4:e9dfb4ca4277	1188	/@}/ /* end of group CMSIS_ITM */
kenjiArai	4:e9dfb4ca4277	1189
kenjiArai	4:e9dfb4ca4277	1190
kenjiArai	4:e9dfb4ca4277	1191	/**
kenjiArai	4:e9dfb4ca4277	1192	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	1193	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
kenjiArai	4:e9dfb4ca4277	1194	\brief Type definitions for the Data Watchpoint and Trace (DWT)
kenjiArai	4:e9dfb4ca4277	1195	@{
kenjiArai	4:e9dfb4ca4277	1196	*/
kenjiArai	4:e9dfb4ca4277	1197
kenjiArai	4:e9dfb4ca4277	1198	/**
kenjiArai	4:e9dfb4ca4277	1199	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
kenjiArai	4:e9dfb4ca4277	1200	*/
kenjiArai	4:e9dfb4ca4277	1201	typedef struct
kenjiArai	4:e9dfb4ca4277	1202	{
kenjiArai	4:e9dfb4ca4277	1203	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
kenjiArai	4:e9dfb4ca4277	1204	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
kenjiArai	4:e9dfb4ca4277	1205	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
kenjiArai	4:e9dfb4ca4277	1206	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
kenjiArai	4:e9dfb4ca4277	1207	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
kenjiArai	4:e9dfb4ca4277	1208	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
kenjiArai	4:e9dfb4ca4277	1209	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
kenjiArai	4:e9dfb4ca4277	1210	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
kenjiArai	4:e9dfb4ca4277	1211	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
kenjiArai	4:e9dfb4ca4277	1212	uint32_t RESERVED1[1U];
kenjiArai	4:e9dfb4ca4277	1213	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
kenjiArai	4:e9dfb4ca4277	1214	uint32_t RESERVED2[1U];
kenjiArai	4:e9dfb4ca4277	1215	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
kenjiArai	4:e9dfb4ca4277	1216	uint32_t RESERVED3[1U];
kenjiArai	4:e9dfb4ca4277	1217	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
kenjiArai	4:e9dfb4ca4277	1218	uint32_t RESERVED4[1U];
kenjiArai	4:e9dfb4ca4277	1219	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
kenjiArai	4:e9dfb4ca4277	1220	uint32_t RESERVED5[1U];
kenjiArai	4:e9dfb4ca4277	1221	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
kenjiArai	4:e9dfb4ca4277	1222	uint32_t RESERVED6[1U];
kenjiArai	4:e9dfb4ca4277	1223	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
kenjiArai	4:e9dfb4ca4277	1224	uint32_t RESERVED7[1U];
kenjiArai	4:e9dfb4ca4277	1225	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
kenjiArai	4:e9dfb4ca4277	1226	uint32_t RESERVED8[1U];
kenjiArai	4:e9dfb4ca4277	1227	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
kenjiArai	4:e9dfb4ca4277	1228	uint32_t RESERVED9[1U];
kenjiArai	4:e9dfb4ca4277	1229	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
kenjiArai	4:e9dfb4ca4277	1230	uint32_t RESERVED10[1U];
kenjiArai	4:e9dfb4ca4277	1231	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
kenjiArai	4:e9dfb4ca4277	1232	uint32_t RESERVED11[1U];
kenjiArai	4:e9dfb4ca4277	1233	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
kenjiArai	4:e9dfb4ca4277	1234	uint32_t RESERVED12[1U];
kenjiArai	4:e9dfb4ca4277	1235	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
kenjiArai	4:e9dfb4ca4277	1236	uint32_t RESERVED13[1U];
kenjiArai	4:e9dfb4ca4277	1237	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
kenjiArai	4:e9dfb4ca4277	1238	uint32_t RESERVED14[1U];
kenjiArai	4:e9dfb4ca4277	1239	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
kenjiArai	4:e9dfb4ca4277	1240	uint32_t RESERVED15[1U];
kenjiArai	4:e9dfb4ca4277	1241	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
kenjiArai	4:e9dfb4ca4277	1242	uint32_t RESERVED16[1U];
kenjiArai	4:e9dfb4ca4277	1243	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
kenjiArai	4:e9dfb4ca4277	1244	uint32_t RESERVED17[1U];
kenjiArai	4:e9dfb4ca4277	1245	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
kenjiArai	4:e9dfb4ca4277	1246	uint32_t RESERVED18[1U];
kenjiArai	4:e9dfb4ca4277	1247	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
kenjiArai	4:e9dfb4ca4277	1248	uint32_t RESERVED19[1U];
kenjiArai	4:e9dfb4ca4277	1249	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
kenjiArai	4:e9dfb4ca4277	1250	uint32_t RESERVED20[1U];
kenjiArai	4:e9dfb4ca4277	1251	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
kenjiArai	4:e9dfb4ca4277	1252	uint32_t RESERVED21[1U];
kenjiArai	4:e9dfb4ca4277	1253	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
kenjiArai	4:e9dfb4ca4277	1254	uint32_t RESERVED22[1U];
kenjiArai	4:e9dfb4ca4277	1255	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
kenjiArai	4:e9dfb4ca4277	1256	uint32_t RESERVED23[1U];
kenjiArai	4:e9dfb4ca4277	1257	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
kenjiArai	4:e9dfb4ca4277	1258	uint32_t RESERVED24[1U];
kenjiArai	4:e9dfb4ca4277	1259	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
kenjiArai	4:e9dfb4ca4277	1260	uint32_t RESERVED25[1U];
kenjiArai	4:e9dfb4ca4277	1261	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
kenjiArai	4:e9dfb4ca4277	1262	uint32_t RESERVED26[1U];
kenjiArai	4:e9dfb4ca4277	1263	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
kenjiArai	4:e9dfb4ca4277	1264	uint32_t RESERVED27[1U];
kenjiArai	4:e9dfb4ca4277	1265	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
kenjiArai	4:e9dfb4ca4277	1266	uint32_t RESERVED28[1U];
kenjiArai	4:e9dfb4ca4277	1267	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
kenjiArai	4:e9dfb4ca4277	1268	uint32_t RESERVED29[1U];
kenjiArai	4:e9dfb4ca4277	1269	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
kenjiArai	4:e9dfb4ca4277	1270	uint32_t RESERVED30[1U];
kenjiArai	4:e9dfb4ca4277	1271	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
kenjiArai	4:e9dfb4ca4277	1272	uint32_t RESERVED31[1U];
kenjiArai	4:e9dfb4ca4277	1273	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
kenjiArai	4:e9dfb4ca4277	1274	uint32_t RESERVED32[934U];
kenjiArai	4:e9dfb4ca4277	1275	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
kenjiArai	4:e9dfb4ca4277	1276	uint32_t RESERVED33[1U];
kenjiArai	4:e9dfb4ca4277	1277	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) Device Architecture Register /
kenjiArai	4:e9dfb4ca4277	1278	} DWT_Type;
kenjiArai	4:e9dfb4ca4277	1279
kenjiArai	4:e9dfb4ca4277	1280	/* DWT Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	1281	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
kenjiArai	4:e9dfb4ca4277	1282	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
kenjiArai	4:e9dfb4ca4277	1283
kenjiArai	4:e9dfb4ca4277	1284	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
kenjiArai	4:e9dfb4ca4277	1285	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
kenjiArai	4:e9dfb4ca4277	1286
kenjiArai	4:e9dfb4ca4277	1287	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
kenjiArai	4:e9dfb4ca4277	1288	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
kenjiArai	4:e9dfb4ca4277	1289
kenjiArai	4:e9dfb4ca4277	1290	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
kenjiArai	4:e9dfb4ca4277	1291	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
kenjiArai	4:e9dfb4ca4277	1292
kenjiArai	4:e9dfb4ca4277	1293	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
kenjiArai	4:e9dfb4ca4277	1294	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
kenjiArai	4:e9dfb4ca4277	1295
kenjiArai	4:e9dfb4ca4277	1296	#define DWT_CTRL_CYCDISS_Pos 23U /!< DWT CTRL: CYCDISS Position /
kenjiArai	4:e9dfb4ca4277	1297	#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /!< DWT CTRL: CYCDISS Mask /
kenjiArai	4:e9dfb4ca4277	1298
kenjiArai	4:e9dfb4ca4277	1299	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
kenjiArai	4:e9dfb4ca4277	1300	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
kenjiArai	4:e9dfb4ca4277	1301
kenjiArai	4:e9dfb4ca4277	1302	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
kenjiArai	4:e9dfb4ca4277	1303	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
kenjiArai	4:e9dfb4ca4277	1304
kenjiArai	4:e9dfb4ca4277	1305	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
kenjiArai	4:e9dfb4ca4277	1306	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
kenjiArai	4:e9dfb4ca4277	1307
kenjiArai	4:e9dfb4ca4277	1308	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
kenjiArai	4:e9dfb4ca4277	1309	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
kenjiArai	4:e9dfb4ca4277	1310
kenjiArai	4:e9dfb4ca4277	1311	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
kenjiArai	4:e9dfb4ca4277	1312	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
kenjiArai	4:e9dfb4ca4277	1313
kenjiArai	4:e9dfb4ca4277	1314	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
kenjiArai	4:e9dfb4ca4277	1315	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
kenjiArai	4:e9dfb4ca4277	1316
kenjiArai	4:e9dfb4ca4277	1317	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
kenjiArai	4:e9dfb4ca4277	1318	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
kenjiArai	4:e9dfb4ca4277	1319
kenjiArai	4:e9dfb4ca4277	1320	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
kenjiArai	4:e9dfb4ca4277	1321	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
kenjiArai	4:e9dfb4ca4277	1322
kenjiArai	4:e9dfb4ca4277	1323	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
kenjiArai	4:e9dfb4ca4277	1324	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
kenjiArai	4:e9dfb4ca4277	1325
kenjiArai	4:e9dfb4ca4277	1326	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
kenjiArai	4:e9dfb4ca4277	1327	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
kenjiArai	4:e9dfb4ca4277	1328
kenjiArai	4:e9dfb4ca4277	1329	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
kenjiArai	4:e9dfb4ca4277	1330	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
kenjiArai	4:e9dfb4ca4277	1331
kenjiArai	4:e9dfb4ca4277	1332	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
kenjiArai	4:e9dfb4ca4277	1333	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
kenjiArai	4:e9dfb4ca4277	1334
kenjiArai	4:e9dfb4ca4277	1335	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
kenjiArai	4:e9dfb4ca4277	1336	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
kenjiArai	4:e9dfb4ca4277	1337
kenjiArai	4:e9dfb4ca4277	1338	/* DWT CPI Count Register Definitions */
kenjiArai	4:e9dfb4ca4277	1339	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
kenjiArai	4:e9dfb4ca4277	1340	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
kenjiArai	4:e9dfb4ca4277	1341
kenjiArai	4:e9dfb4ca4277	1342	/* DWT Exception Overhead Count Register Definitions */
kenjiArai	4:e9dfb4ca4277	1343	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
kenjiArai	4:e9dfb4ca4277	1344	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
kenjiArai	4:e9dfb4ca4277	1345
kenjiArai	4:e9dfb4ca4277	1346	/* DWT Sleep Count Register Definitions */
kenjiArai	4:e9dfb4ca4277	1347	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
kenjiArai	4:e9dfb4ca4277	1348	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
kenjiArai	4:e9dfb4ca4277	1349
kenjiArai	4:e9dfb4ca4277	1350	/* DWT LSU Count Register Definitions */
kenjiArai	4:e9dfb4ca4277	1351	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
kenjiArai	4:e9dfb4ca4277	1352	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
kenjiArai	4:e9dfb4ca4277	1353
kenjiArai	4:e9dfb4ca4277	1354	/* DWT Folded-instruction Count Register Definitions */
kenjiArai	4:e9dfb4ca4277	1355	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
kenjiArai	4:e9dfb4ca4277	1356	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
kenjiArai	4:e9dfb4ca4277	1357
kenjiArai	4:e9dfb4ca4277	1358	/* DWT Comparator Function Register Definitions */
kenjiArai	4:e9dfb4ca4277	1359	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
kenjiArai	4:e9dfb4ca4277	1360	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
kenjiArai	4:e9dfb4ca4277	1361
kenjiArai	4:e9dfb4ca4277	1362	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
kenjiArai	4:e9dfb4ca4277	1363	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
kenjiArai	4:e9dfb4ca4277	1364
kenjiArai	4:e9dfb4ca4277	1365	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
kenjiArai	4:e9dfb4ca4277	1366	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
kenjiArai	4:e9dfb4ca4277	1367
kenjiArai	4:e9dfb4ca4277	1368	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
kenjiArai	4:e9dfb4ca4277	1369	#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
kenjiArai	4:e9dfb4ca4277	1370
kenjiArai	4:e9dfb4ca4277	1371	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
kenjiArai	4:e9dfb4ca4277	1372	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
kenjiArai	4:e9dfb4ca4277	1373
kenjiArai	4:e9dfb4ca4277	1374	/@}/ /* end of group CMSIS_DWT */
kenjiArai	4:e9dfb4ca4277	1375
kenjiArai	4:e9dfb4ca4277	1376
kenjiArai	4:e9dfb4ca4277	1377	/**
kenjiArai	4:e9dfb4ca4277	1378	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	1379	\defgroup CMSIS_TPI Trace Port Interface (TPI)
kenjiArai	4:e9dfb4ca4277	1380	\brief Type definitions for the Trace Port Interface (TPI)
kenjiArai	4:e9dfb4ca4277	1381	@{
kenjiArai	4:e9dfb4ca4277	1382	*/
kenjiArai	4:e9dfb4ca4277	1383
kenjiArai	4:e9dfb4ca4277	1384	/**
kenjiArai	4:e9dfb4ca4277	1385	\brief Structure type to access the Trace Port Interface Register (TPI).
kenjiArai	4:e9dfb4ca4277	1386	*/
kenjiArai	4:e9dfb4ca4277	1387	typedef struct
kenjiArai	4:e9dfb4ca4277	1388	{
kenjiArai	4:e9dfb4ca4277	1389	__IM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register /
kenjiArai	4:e9dfb4ca4277	1390	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register /
kenjiArai	4:e9dfb4ca4277	1391	uint32_t RESERVED0[2U];
kenjiArai	4:e9dfb4ca4277	1392	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
kenjiArai	4:e9dfb4ca4277	1393	uint32_t RESERVED1[55U];
kenjiArai	4:e9dfb4ca4277	1394	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
kenjiArai	4:e9dfb4ca4277	1395	uint32_t RESERVED2[131U];
kenjiArai	4:e9dfb4ca4277	1396	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
kenjiArai	4:e9dfb4ca4277	1397	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
kenjiArai	4:e9dfb4ca4277	1398	__IOM uint32_t PSCR; /!< Offset: 0x308 (R/W) Periodic Synchronization Control Register /
kenjiArai	4:e9dfb4ca4277	1399	uint32_t RESERVED3[809U];
kenjiArai	4:e9dfb4ca4277	1400	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) Software Lock Access Register /
kenjiArai	4:e9dfb4ca4277	1401	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) Software Lock Status Register /
kenjiArai	4:e9dfb4ca4277	1402	uint32_t RESERVED4[4U];
kenjiArai	4:e9dfb4ca4277	1403	__IM uint32_t TYPE; /!< Offset: 0xFC8 (R/ ) Device Identifier Register /
kenjiArai	4:e9dfb4ca4277	1404	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) Device Type Register /
kenjiArai	4:e9dfb4ca4277	1405	} TPI_Type;
kenjiArai	4:e9dfb4ca4277	1406
kenjiArai	4:e9dfb4ca4277	1407	/* TPI Asynchronous Clock Prescaler Register Definitions */
kenjiArai	4:e9dfb4ca4277	1408	#define TPI_ACPR_SWOSCALER_Pos 0U /!< TPI ACPR: SWOSCALER Position /
kenjiArai	4:e9dfb4ca4277	1409	#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/) /!< TPI ACPR: SWOSCALER Mask /
kenjiArai	4:e9dfb4ca4277	1410
kenjiArai	4:e9dfb4ca4277	1411	/* TPI Selected Pin Protocol Register Definitions */
kenjiArai	4:e9dfb4ca4277	1412	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
kenjiArai	4:e9dfb4ca4277	1413	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
kenjiArai	4:e9dfb4ca4277	1414
kenjiArai	4:e9dfb4ca4277	1415	/* TPI Formatter and Flush Status Register Definitions */
kenjiArai	4:e9dfb4ca4277	1416	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
kenjiArai	4:e9dfb4ca4277	1417	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
kenjiArai	4:e9dfb4ca4277	1418
kenjiArai	4:e9dfb4ca4277	1419	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
kenjiArai	4:e9dfb4ca4277	1420	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
kenjiArai	4:e9dfb4ca4277	1421
kenjiArai	4:e9dfb4ca4277	1422	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
kenjiArai	4:e9dfb4ca4277	1423	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
kenjiArai	4:e9dfb4ca4277	1424
kenjiArai	4:e9dfb4ca4277	1425	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
kenjiArai	4:e9dfb4ca4277	1426	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
kenjiArai	4:e9dfb4ca4277	1427
kenjiArai	4:e9dfb4ca4277	1428	/* TPI Formatter and Flush Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	1429	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
kenjiArai	4:e9dfb4ca4277	1430	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
kenjiArai	4:e9dfb4ca4277	1431
kenjiArai	4:e9dfb4ca4277	1432	#define TPI_FFCR_FOnMan_Pos 6U /!< TPI FFCR: FOnMan Position /
kenjiArai	4:e9dfb4ca4277	1433	#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /!< TPI FFCR: FOnMan Mask /
kenjiArai	4:e9dfb4ca4277	1434
kenjiArai	4:e9dfb4ca4277	1435	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
kenjiArai	4:e9dfb4ca4277	1436	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
kenjiArai	4:e9dfb4ca4277	1437
kenjiArai	4:e9dfb4ca4277	1438	/* TPI Periodic Synchronization Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	1439	#define TPI_PSCR_PSCount_Pos 0U /!< TPI PSCR: PSCount Position /
kenjiArai	4:e9dfb4ca4277	1440	#define TPI_PSCR_PSCount_Msk (0x1FUL /<< TPI_PSCR_PSCount_Pos/) /!< TPI PSCR: TPSCount Mask /
kenjiArai	4:e9dfb4ca4277	1441
kenjiArai	4:e9dfb4ca4277	1442	/* TPI Software Lock Status Register Definitions */
kenjiArai	4:e9dfb4ca4277	1443	#define TPI_LSR_nTT_Pos 1U /!< TPI LSR: Not thirty-two bit. Position /
kenjiArai	4:e9dfb4ca4277	1444	#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /!< TPI LSR: Not thirty-two bit. Mask /
kenjiArai	4:e9dfb4ca4277	1445
kenjiArai	4:e9dfb4ca4277	1446	#define TPI_LSR_SLK_Pos 1U /!< TPI LSR: Software Lock status Position /
kenjiArai	4:e9dfb4ca4277	1447	#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /!< TPI LSR: Software Lock status Mask /
kenjiArai	4:e9dfb4ca4277	1448
kenjiArai	4:e9dfb4ca4277	1449	#define TPI_LSR_SLI_Pos 0U /!< TPI LSR: Software Lock implemented Position /
kenjiArai	4:e9dfb4ca4277	1450	#define TPI_LSR_SLI_Msk (0x1UL /<< TPI_LSR_SLI_Pos/) /!< TPI LSR: Software Lock implemented Mask /
kenjiArai	4:e9dfb4ca4277	1451
kenjiArai	4:e9dfb4ca4277	1452	/* TPI DEVID Register Definitions */
kenjiArai	4:e9dfb4ca4277	1453	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
kenjiArai	4:e9dfb4ca4277	1454	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
kenjiArai	4:e9dfb4ca4277	1455
kenjiArai	4:e9dfb4ca4277	1456	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
kenjiArai	4:e9dfb4ca4277	1457	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
kenjiArai	4:e9dfb4ca4277	1458
kenjiArai	4:e9dfb4ca4277	1459	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
kenjiArai	4:e9dfb4ca4277	1460	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
kenjiArai	4:e9dfb4ca4277	1461
kenjiArai	4:e9dfb4ca4277	1462	#define TPI_DEVID_FIFOSZ_Pos 6U /!< TPI DEVID: FIFO depth Position /
kenjiArai	4:e9dfb4ca4277	1463	#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /!< TPI DEVID: FIFO depth Mask /
kenjiArai	4:e9dfb4ca4277	1464
kenjiArai	4:e9dfb4ca4277	1465	/* TPI DEVTYPE Register Definitions */
kenjiArai	4:e9dfb4ca4277	1466	#define TPI_DEVTYPE_SubType_Pos 4U /!< TPI DEVTYPE: SubType Position /
kenjiArai	4:e9dfb4ca4277	1467	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
kenjiArai	4:e9dfb4ca4277	1468
kenjiArai	4:e9dfb4ca4277	1469	#define TPI_DEVTYPE_MajorType_Pos 0U /!< TPI DEVTYPE: MajorType Position /
kenjiArai	4:e9dfb4ca4277	1470	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
kenjiArai	4:e9dfb4ca4277	1471
kenjiArai	4:e9dfb4ca4277	1472	/@}/ /* end of group CMSIS_TPI */
kenjiArai	4:e9dfb4ca4277	1473
kenjiArai	4:e9dfb4ca4277	1474
kenjiArai	4:e9dfb4ca4277	1475	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	1476	/**
kenjiArai	4:e9dfb4ca4277	1477	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	1478	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
kenjiArai	4:e9dfb4ca4277	1479	\brief Type definitions for the Memory Protection Unit (MPU)
kenjiArai	4:e9dfb4ca4277	1480	@{
kenjiArai	4:e9dfb4ca4277	1481	*/
kenjiArai	4:e9dfb4ca4277	1482
kenjiArai	4:e9dfb4ca4277	1483	/**
kenjiArai	4:e9dfb4ca4277	1484	\brief Structure type to access the Memory Protection Unit (MPU).
kenjiArai	4:e9dfb4ca4277	1485	*/
kenjiArai	4:e9dfb4ca4277	1486	typedef struct
kenjiArai	4:e9dfb4ca4277	1487	{
kenjiArai	4:e9dfb4ca4277	1488	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
kenjiArai	4:e9dfb4ca4277	1489	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
kenjiArai	4:e9dfb4ca4277	1490	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
kenjiArai	4:e9dfb4ca4277	1491	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
kenjiArai	4:e9dfb4ca4277	1492	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
kenjiArai	4:e9dfb4ca4277	1493	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 /
kenjiArai	4:e9dfb4ca4277	1494	__IOM uint32_t RLAR_A1; /!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 /
kenjiArai	4:e9dfb4ca4277	1495	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 /
kenjiArai	4:e9dfb4ca4277	1496	__IOM uint32_t RLAR_A2; /!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 /
kenjiArai	4:e9dfb4ca4277	1497	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 /
kenjiArai	4:e9dfb4ca4277	1498	__IOM uint32_t RLAR_A3; /!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 /
kenjiArai	4:e9dfb4ca4277	1499	uint32_t RESERVED0[1];
kenjiArai	4:e9dfb4ca4277	1500	union {
kenjiArai	4:e9dfb4ca4277	1501	__IOM uint32_t MAIR[2];
kenjiArai	4:e9dfb4ca4277	1502	struct {
kenjiArai	4:e9dfb4ca4277	1503	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
kenjiArai	4:e9dfb4ca4277	1504	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
kenjiArai	4:e9dfb4ca4277	1505	};
kenjiArai	4:e9dfb4ca4277	1506	};
kenjiArai	4:e9dfb4ca4277	1507	} MPU_Type;
kenjiArai	4:e9dfb4ca4277	1508
kenjiArai	4:e9dfb4ca4277	1509	#define MPU_TYPE_RALIASES 4U
kenjiArai	4:e9dfb4ca4277	1510
kenjiArai	4:e9dfb4ca4277	1511	/* MPU Type Register Definitions */
kenjiArai	4:e9dfb4ca4277	1512	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
kenjiArai	4:e9dfb4ca4277	1513	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
kenjiArai	4:e9dfb4ca4277	1514
kenjiArai	4:e9dfb4ca4277	1515	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
kenjiArai	4:e9dfb4ca4277	1516	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
kenjiArai	4:e9dfb4ca4277	1517
kenjiArai	4:e9dfb4ca4277	1518	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
kenjiArai	4:e9dfb4ca4277	1519	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
kenjiArai	4:e9dfb4ca4277	1520
kenjiArai	4:e9dfb4ca4277	1521	/* MPU Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	1522	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
kenjiArai	4:e9dfb4ca4277	1523	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
kenjiArai	4:e9dfb4ca4277	1524
kenjiArai	4:e9dfb4ca4277	1525	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
kenjiArai	4:e9dfb4ca4277	1526	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
kenjiArai	4:e9dfb4ca4277	1527
kenjiArai	4:e9dfb4ca4277	1528	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
kenjiArai	4:e9dfb4ca4277	1529	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
kenjiArai	4:e9dfb4ca4277	1530
kenjiArai	4:e9dfb4ca4277	1531	/* MPU Region Number Register Definitions */
kenjiArai	4:e9dfb4ca4277	1532	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
kenjiArai	4:e9dfb4ca4277	1533	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
kenjiArai	4:e9dfb4ca4277	1534
kenjiArai	4:e9dfb4ca4277	1535	/* MPU Region Base Address Register Definitions */
kenjiArai	4:e9dfb4ca4277	1536	#define MPU_RBAR_BASE_Pos 5U /!< MPU RBAR: BASE Position /
kenjiArai	4:e9dfb4ca4277	1537	#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /!< MPU RBAR: BASE Mask /
kenjiArai	4:e9dfb4ca4277	1538
kenjiArai	4:e9dfb4ca4277	1539	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
kenjiArai	4:e9dfb4ca4277	1540	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
kenjiArai	4:e9dfb4ca4277	1541
kenjiArai	4:e9dfb4ca4277	1542	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
kenjiArai	4:e9dfb4ca4277	1543	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
kenjiArai	4:e9dfb4ca4277	1544
kenjiArai	4:e9dfb4ca4277	1545	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
kenjiArai	4:e9dfb4ca4277	1546	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
kenjiArai	4:e9dfb4ca4277	1547
kenjiArai	4:e9dfb4ca4277	1548	/* MPU Region Limit Address Register Definitions */
kenjiArai	4:e9dfb4ca4277	1549	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
kenjiArai	4:e9dfb4ca4277	1550	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
kenjiArai	4:e9dfb4ca4277	1551
kenjiArai	4:e9dfb4ca4277	1552	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
kenjiArai	4:e9dfb4ca4277	1553	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
kenjiArai	4:e9dfb4ca4277	1554
kenjiArai	4:e9dfb4ca4277	1555	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: Region enable bit Position /
kenjiArai	4:e9dfb4ca4277	1556	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: Region enable bit Disable Mask /
kenjiArai	4:e9dfb4ca4277	1557
kenjiArai	4:e9dfb4ca4277	1558	/* MPU Memory Attribute Indirection Register 0 Definitions */
kenjiArai	4:e9dfb4ca4277	1559	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
kenjiArai	4:e9dfb4ca4277	1560	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
kenjiArai	4:e9dfb4ca4277	1561
kenjiArai	4:e9dfb4ca4277	1562	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
kenjiArai	4:e9dfb4ca4277	1563	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
kenjiArai	4:e9dfb4ca4277	1564
kenjiArai	4:e9dfb4ca4277	1565	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
kenjiArai	4:e9dfb4ca4277	1566	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
kenjiArai	4:e9dfb4ca4277	1567
kenjiArai	4:e9dfb4ca4277	1568	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
kenjiArai	4:e9dfb4ca4277	1569	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
kenjiArai	4:e9dfb4ca4277	1570
kenjiArai	4:e9dfb4ca4277	1571	/* MPU Memory Attribute Indirection Register 1 Definitions */
kenjiArai	4:e9dfb4ca4277	1572	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
kenjiArai	4:e9dfb4ca4277	1573	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
kenjiArai	4:e9dfb4ca4277	1574
kenjiArai	4:e9dfb4ca4277	1575	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
kenjiArai	4:e9dfb4ca4277	1576	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
kenjiArai	4:e9dfb4ca4277	1577
kenjiArai	4:e9dfb4ca4277	1578	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
kenjiArai	4:e9dfb4ca4277	1579	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
kenjiArai	4:e9dfb4ca4277	1580
kenjiArai	4:e9dfb4ca4277	1581	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
kenjiArai	4:e9dfb4ca4277	1582	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
kenjiArai	4:e9dfb4ca4277	1583
kenjiArai	4:e9dfb4ca4277	1584	/@} end of group CMSIS_MPU /
kenjiArai	4:e9dfb4ca4277	1585	#endif
kenjiArai	4:e9dfb4ca4277	1586
kenjiArai	4:e9dfb4ca4277	1587
kenjiArai	4:e9dfb4ca4277	1588	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kenjiArai	4:e9dfb4ca4277	1589	/**
kenjiArai	4:e9dfb4ca4277	1590	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	1591	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
kenjiArai	4:e9dfb4ca4277	1592	\brief Type definitions for the Security Attribution Unit (SAU)
kenjiArai	4:e9dfb4ca4277	1593	@{
kenjiArai	4:e9dfb4ca4277	1594	*/
kenjiArai	4:e9dfb4ca4277	1595
kenjiArai	4:e9dfb4ca4277	1596	/**
kenjiArai	4:e9dfb4ca4277	1597	\brief Structure type to access the Security Attribution Unit (SAU).
kenjiArai	4:e9dfb4ca4277	1598	*/
kenjiArai	4:e9dfb4ca4277	1599	typedef struct
kenjiArai	4:e9dfb4ca4277	1600	{
kenjiArai	4:e9dfb4ca4277	1601	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
kenjiArai	4:e9dfb4ca4277	1602	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
kenjiArai	4:e9dfb4ca4277	1603	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	1604	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
kenjiArai	4:e9dfb4ca4277	1605	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
kenjiArai	4:e9dfb4ca4277	1606	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
kenjiArai	4:e9dfb4ca4277	1607	#else
kenjiArai	4:e9dfb4ca4277	1608	uint32_t RESERVED0[3];
kenjiArai	4:e9dfb4ca4277	1609	#endif
kenjiArai	4:e9dfb4ca4277	1610	__IOM uint32_t SFSR; /!< Offset: 0x014 (R/W) Secure Fault Status Register /
kenjiArai	4:e9dfb4ca4277	1611	__IOM uint32_t SFAR; /!< Offset: 0x018 (R/W) Secure Fault Address Register /
kenjiArai	4:e9dfb4ca4277	1612	} SAU_Type;
kenjiArai	4:e9dfb4ca4277	1613
kenjiArai	4:e9dfb4ca4277	1614	/* SAU Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	1615	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
kenjiArai	4:e9dfb4ca4277	1616	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
kenjiArai	4:e9dfb4ca4277	1617
kenjiArai	4:e9dfb4ca4277	1618	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
kenjiArai	4:e9dfb4ca4277	1619	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
kenjiArai	4:e9dfb4ca4277	1620
kenjiArai	4:e9dfb4ca4277	1621	/* SAU Type Register Definitions */
kenjiArai	4:e9dfb4ca4277	1622	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
kenjiArai	4:e9dfb4ca4277	1623	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
kenjiArai	4:e9dfb4ca4277	1624
kenjiArai	4:e9dfb4ca4277	1625	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	1626	/* SAU Region Number Register Definitions */
kenjiArai	4:e9dfb4ca4277	1627	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
kenjiArai	4:e9dfb4ca4277	1628	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
kenjiArai	4:e9dfb4ca4277	1629
kenjiArai	4:e9dfb4ca4277	1630	/* SAU Region Base Address Register Definitions */
kenjiArai	4:e9dfb4ca4277	1631	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
kenjiArai	4:e9dfb4ca4277	1632	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
kenjiArai	4:e9dfb4ca4277	1633
kenjiArai	4:e9dfb4ca4277	1634	/* SAU Region Limit Address Register Definitions */
kenjiArai	4:e9dfb4ca4277	1635	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
kenjiArai	4:e9dfb4ca4277	1636	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
kenjiArai	4:e9dfb4ca4277	1637
kenjiArai	4:e9dfb4ca4277	1638	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
kenjiArai	4:e9dfb4ca4277	1639	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
kenjiArai	4:e9dfb4ca4277	1640
kenjiArai	4:e9dfb4ca4277	1641	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
kenjiArai	4:e9dfb4ca4277	1642	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
kenjiArai	4:e9dfb4ca4277	1643
kenjiArai	4:e9dfb4ca4277	1644	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
kenjiArai	4:e9dfb4ca4277	1645
kenjiArai	4:e9dfb4ca4277	1646	/* Secure Fault Status Register Definitions */
kenjiArai	4:e9dfb4ca4277	1647	#define SAU_SFSR_LSERR_Pos 7U /!< SAU SFSR: LSERR Position /
kenjiArai	4:e9dfb4ca4277	1648	#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /!< SAU SFSR: LSERR Mask /
kenjiArai	4:e9dfb4ca4277	1649
kenjiArai	4:e9dfb4ca4277	1650	#define SAU_SFSR_SFARVALID_Pos 6U /!< SAU SFSR: SFARVALID Position /
kenjiArai	4:e9dfb4ca4277	1651	#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /!< SAU SFSR: SFARVALID Mask /
kenjiArai	4:e9dfb4ca4277	1652
kenjiArai	4:e9dfb4ca4277	1653	#define SAU_SFSR_LSPERR_Pos 5U /!< SAU SFSR: LSPERR Position /
kenjiArai	4:e9dfb4ca4277	1654	#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /!< SAU SFSR: LSPERR Mask /
kenjiArai	4:e9dfb4ca4277	1655
kenjiArai	4:e9dfb4ca4277	1656	#define SAU_SFSR_INVTRAN_Pos 4U /!< SAU SFSR: INVTRAN Position /
kenjiArai	4:e9dfb4ca4277	1657	#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /!< SAU SFSR: INVTRAN Mask /
kenjiArai	4:e9dfb4ca4277	1658
kenjiArai	4:e9dfb4ca4277	1659	#define SAU_SFSR_AUVIOL_Pos 3U /!< SAU SFSR: AUVIOL Position /
kenjiArai	4:e9dfb4ca4277	1660	#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /!< SAU SFSR: AUVIOL Mask /
kenjiArai	4:e9dfb4ca4277	1661
kenjiArai	4:e9dfb4ca4277	1662	#define SAU_SFSR_INVER_Pos 2U /!< SAU SFSR: INVER Position /
kenjiArai	4:e9dfb4ca4277	1663	#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /!< SAU SFSR: INVER Mask /
kenjiArai	4:e9dfb4ca4277	1664
kenjiArai	4:e9dfb4ca4277	1665	#define SAU_SFSR_INVIS_Pos 1U /!< SAU SFSR: INVIS Position /
kenjiArai	4:e9dfb4ca4277	1666	#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /!< SAU SFSR: INVIS Mask /
kenjiArai	4:e9dfb4ca4277	1667
kenjiArai	4:e9dfb4ca4277	1668	#define SAU_SFSR_INVEP_Pos 0U /!< SAU SFSR: INVEP Position /
kenjiArai	4:e9dfb4ca4277	1669	#define SAU_SFSR_INVEP_Msk (1UL /<< SAU_SFSR_INVEP_Pos/) /!< SAU SFSR: INVEP Mask /
kenjiArai	4:e9dfb4ca4277	1670
kenjiArai	4:e9dfb4ca4277	1671	/@} end of group CMSIS_SAU /
kenjiArai	4:e9dfb4ca4277	1672	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
kenjiArai	4:e9dfb4ca4277	1673
kenjiArai	4:e9dfb4ca4277	1674
kenjiArai	4:e9dfb4ca4277	1675	/**
kenjiArai	4:e9dfb4ca4277	1676	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	1677	\defgroup CMSIS_FPU Floating Point Unit (FPU)
kenjiArai	4:e9dfb4ca4277	1678	\brief Type definitions for the Floating Point Unit (FPU)
kenjiArai	4:e9dfb4ca4277	1679	@{
kenjiArai	4:e9dfb4ca4277	1680	*/
kenjiArai	4:e9dfb4ca4277	1681
kenjiArai	4:e9dfb4ca4277	1682	/**
kenjiArai	4:e9dfb4ca4277	1683	\brief Structure type to access the Floating Point Unit (FPU).
kenjiArai	4:e9dfb4ca4277	1684	*/
kenjiArai	4:e9dfb4ca4277	1685	typedef struct
kenjiArai	4:e9dfb4ca4277	1686	{
kenjiArai	4:e9dfb4ca4277	1687	uint32_t RESERVED0[1U];
kenjiArai	4:e9dfb4ca4277	1688	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
kenjiArai	4:e9dfb4ca4277	1689	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
kenjiArai	4:e9dfb4ca4277	1690	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
kenjiArai	4:e9dfb4ca4277	1691	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
kenjiArai	4:e9dfb4ca4277	1692	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
kenjiArai	4:e9dfb4ca4277	1693	} FPU_Type;
kenjiArai	4:e9dfb4ca4277	1694
kenjiArai	4:e9dfb4ca4277	1695	/* Floating-Point Context Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	1696	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
kenjiArai	4:e9dfb4ca4277	1697	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
kenjiArai	4:e9dfb4ca4277	1698
kenjiArai	4:e9dfb4ca4277	1699	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
kenjiArai	4:e9dfb4ca4277	1700	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
kenjiArai	4:e9dfb4ca4277	1701
kenjiArai	4:e9dfb4ca4277	1702	#define FPU_FPCCR_LSPENS_Pos 29U /!< FPCCR: LSPENS Position /
kenjiArai	4:e9dfb4ca4277	1703	#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /!< FPCCR: LSPENS bit Mask /
kenjiArai	4:e9dfb4ca4277	1704
kenjiArai	4:e9dfb4ca4277	1705	#define FPU_FPCCR_CLRONRET_Pos 28U /!< FPCCR: CLRONRET Position /
kenjiArai	4:e9dfb4ca4277	1706	#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /!< FPCCR: CLRONRET bit Mask /
kenjiArai	4:e9dfb4ca4277	1707
kenjiArai	4:e9dfb4ca4277	1708	#define FPU_FPCCR_CLRONRETS_Pos 27U /!< FPCCR: CLRONRETS Position /
kenjiArai	4:e9dfb4ca4277	1709	#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /!< FPCCR: CLRONRETS bit Mask /
kenjiArai	4:e9dfb4ca4277	1710
kenjiArai	4:e9dfb4ca4277	1711	#define FPU_FPCCR_TS_Pos 26U /!< FPCCR: TS Position /
kenjiArai	4:e9dfb4ca4277	1712	#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /!< FPCCR: TS bit Mask /
kenjiArai	4:e9dfb4ca4277	1713
kenjiArai	4:e9dfb4ca4277	1714	#define FPU_FPCCR_UFRDY_Pos 10U /!< FPCCR: UFRDY Position /
kenjiArai	4:e9dfb4ca4277	1715	#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /!< FPCCR: UFRDY bit Mask /
kenjiArai	4:e9dfb4ca4277	1716
kenjiArai	4:e9dfb4ca4277	1717	#define FPU_FPCCR_SPLIMVIOL_Pos 9U /!< FPCCR: SPLIMVIOL Position /
kenjiArai	4:e9dfb4ca4277	1718	#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /!< FPCCR: SPLIMVIOL bit Mask /
kenjiArai	4:e9dfb4ca4277	1719
kenjiArai	4:e9dfb4ca4277	1720	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
kenjiArai	4:e9dfb4ca4277	1721	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
kenjiArai	4:e9dfb4ca4277	1722
kenjiArai	4:e9dfb4ca4277	1723	#define FPU_FPCCR_SFRDY_Pos 7U /!< FPCCR: SFRDY Position /
kenjiArai	4:e9dfb4ca4277	1724	#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /!< FPCCR: SFRDY bit Mask /
kenjiArai	4:e9dfb4ca4277	1725
kenjiArai	4:e9dfb4ca4277	1726	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
kenjiArai	4:e9dfb4ca4277	1727	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
kenjiArai	4:e9dfb4ca4277	1728
kenjiArai	4:e9dfb4ca4277	1729	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
kenjiArai	4:e9dfb4ca4277	1730	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
kenjiArai	4:e9dfb4ca4277	1731
kenjiArai	4:e9dfb4ca4277	1732	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
kenjiArai	4:e9dfb4ca4277	1733	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
kenjiArai	4:e9dfb4ca4277	1734
kenjiArai	4:e9dfb4ca4277	1735	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
kenjiArai	4:e9dfb4ca4277	1736	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
kenjiArai	4:e9dfb4ca4277	1737
kenjiArai	4:e9dfb4ca4277	1738	#define FPU_FPCCR_S_Pos 2U /!< FPCCR: Security status of the FP context bit Position /
kenjiArai	4:e9dfb4ca4277	1739	#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /!< FPCCR: Security status of the FP context bit Mask /
kenjiArai	4:e9dfb4ca4277	1740
kenjiArai	4:e9dfb4ca4277	1741	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
kenjiArai	4:e9dfb4ca4277	1742	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
kenjiArai	4:e9dfb4ca4277	1743
kenjiArai	4:e9dfb4ca4277	1744	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
kenjiArai	4:e9dfb4ca4277	1745	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
kenjiArai	4:e9dfb4ca4277	1746
kenjiArai	4:e9dfb4ca4277	1747	/* Floating-Point Context Address Register Definitions */
kenjiArai	4:e9dfb4ca4277	1748	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
kenjiArai	4:e9dfb4ca4277	1749	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
kenjiArai	4:e9dfb4ca4277	1750
kenjiArai	4:e9dfb4ca4277	1751	/* Floating-Point Default Status Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	1752	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
kenjiArai	4:e9dfb4ca4277	1753	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
kenjiArai	4:e9dfb4ca4277	1754
kenjiArai	4:e9dfb4ca4277	1755	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
kenjiArai	4:e9dfb4ca4277	1756	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
kenjiArai	4:e9dfb4ca4277	1757
kenjiArai	4:e9dfb4ca4277	1758	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
kenjiArai	4:e9dfb4ca4277	1759	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
kenjiArai	4:e9dfb4ca4277	1760
kenjiArai	4:e9dfb4ca4277	1761	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
kenjiArai	4:e9dfb4ca4277	1762	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
kenjiArai	4:e9dfb4ca4277	1763
kenjiArai	4:e9dfb4ca4277	1764	/* Media and FP Feature Register 0 Definitions */
kenjiArai	4:e9dfb4ca4277	1765	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
kenjiArai	4:e9dfb4ca4277	1766	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
kenjiArai	4:e9dfb4ca4277	1767
kenjiArai	4:e9dfb4ca4277	1768	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
kenjiArai	4:e9dfb4ca4277	1769	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
kenjiArai	4:e9dfb4ca4277	1770
kenjiArai	4:e9dfb4ca4277	1771	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
kenjiArai	4:e9dfb4ca4277	1772	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
kenjiArai	4:e9dfb4ca4277	1773
kenjiArai	4:e9dfb4ca4277	1774	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
kenjiArai	4:e9dfb4ca4277	1775	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
kenjiArai	4:e9dfb4ca4277	1776
kenjiArai	4:e9dfb4ca4277	1777	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
kenjiArai	4:e9dfb4ca4277	1778	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
kenjiArai	4:e9dfb4ca4277	1779
kenjiArai	4:e9dfb4ca4277	1780	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
kenjiArai	4:e9dfb4ca4277	1781	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
kenjiArai	4:e9dfb4ca4277	1782
kenjiArai	4:e9dfb4ca4277	1783	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
kenjiArai	4:e9dfb4ca4277	1784	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
kenjiArai	4:e9dfb4ca4277	1785
kenjiArai	4:e9dfb4ca4277	1786	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
kenjiArai	4:e9dfb4ca4277	1787	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
kenjiArai	4:e9dfb4ca4277	1788
kenjiArai	4:e9dfb4ca4277	1789	/* Media and FP Feature Register 1 Definitions */
kenjiArai	4:e9dfb4ca4277	1790	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
kenjiArai	4:e9dfb4ca4277	1791	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
kenjiArai	4:e9dfb4ca4277	1792
kenjiArai	4:e9dfb4ca4277	1793	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
kenjiArai	4:e9dfb4ca4277	1794	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
kenjiArai	4:e9dfb4ca4277	1795
kenjiArai	4:e9dfb4ca4277	1796	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
kenjiArai	4:e9dfb4ca4277	1797	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
kenjiArai	4:e9dfb4ca4277	1798
kenjiArai	4:e9dfb4ca4277	1799	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
kenjiArai	4:e9dfb4ca4277	1800	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
kenjiArai	4:e9dfb4ca4277	1801
kenjiArai	4:e9dfb4ca4277	1802	/@} end of group CMSIS_FPU /
kenjiArai	4:e9dfb4ca4277	1803
kenjiArai	4:e9dfb4ca4277	1804
kenjiArai	4:e9dfb4ca4277	1805	/**
kenjiArai	4:e9dfb4ca4277	1806	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	1807	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
kenjiArai	4:e9dfb4ca4277	1808	\brief Type definitions for the Core Debug Registers
kenjiArai	4:e9dfb4ca4277	1809	@{
kenjiArai	4:e9dfb4ca4277	1810	*/
kenjiArai	4:e9dfb4ca4277	1811
kenjiArai	4:e9dfb4ca4277	1812	/**
kenjiArai	4:e9dfb4ca4277	1813	\brief Structure type to access the Core Debug Register (CoreDebug).
kenjiArai	4:e9dfb4ca4277	1814	*/
kenjiArai	4:e9dfb4ca4277	1815	typedef struct
kenjiArai	4:e9dfb4ca4277	1816	{
kenjiArai	4:e9dfb4ca4277	1817	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
kenjiArai	4:e9dfb4ca4277	1818	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
kenjiArai	4:e9dfb4ca4277	1819	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
kenjiArai	4:e9dfb4ca4277	1820	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
kenjiArai	4:e9dfb4ca4277	1821	uint32_t RESERVED4[1U];
kenjiArai	4:e9dfb4ca4277	1822	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
kenjiArai	4:e9dfb4ca4277	1823	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
kenjiArai	4:e9dfb4ca4277	1824	} CoreDebug_Type;
kenjiArai	4:e9dfb4ca4277	1825
kenjiArai	4:e9dfb4ca4277	1826	/* Debug Halting Control and Status Register Definitions */
kenjiArai	4:e9dfb4ca4277	1827	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
kenjiArai	4:e9dfb4ca4277	1828	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
kenjiArai	4:e9dfb4ca4277	1829
kenjiArai	4:e9dfb4ca4277	1830	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
kenjiArai	4:e9dfb4ca4277	1831	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
kenjiArai	4:e9dfb4ca4277	1832
kenjiArai	4:e9dfb4ca4277	1833	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
kenjiArai	4:e9dfb4ca4277	1834	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
kenjiArai	4:e9dfb4ca4277	1835
kenjiArai	4:e9dfb4ca4277	1836	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
kenjiArai	4:e9dfb4ca4277	1837	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
kenjiArai	4:e9dfb4ca4277	1838
kenjiArai	4:e9dfb4ca4277	1839	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
kenjiArai	4:e9dfb4ca4277	1840	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
kenjiArai	4:e9dfb4ca4277	1841
kenjiArai	4:e9dfb4ca4277	1842	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
kenjiArai	4:e9dfb4ca4277	1843	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
kenjiArai	4:e9dfb4ca4277	1844
kenjiArai	4:e9dfb4ca4277	1845	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
kenjiArai	4:e9dfb4ca4277	1846	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
kenjiArai	4:e9dfb4ca4277	1847
kenjiArai	4:e9dfb4ca4277	1848	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
kenjiArai	4:e9dfb4ca4277	1849	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
kenjiArai	4:e9dfb4ca4277	1850
kenjiArai	4:e9dfb4ca4277	1851	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
kenjiArai	4:e9dfb4ca4277	1852	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
kenjiArai	4:e9dfb4ca4277	1853
kenjiArai	4:e9dfb4ca4277	1854	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
kenjiArai	4:e9dfb4ca4277	1855	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
kenjiArai	4:e9dfb4ca4277	1856
kenjiArai	4:e9dfb4ca4277	1857	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
kenjiArai	4:e9dfb4ca4277	1858	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
kenjiArai	4:e9dfb4ca4277	1859
kenjiArai	4:e9dfb4ca4277	1860	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
kenjiArai	4:e9dfb4ca4277	1861	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
kenjiArai	4:e9dfb4ca4277	1862
kenjiArai	4:e9dfb4ca4277	1863	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
kenjiArai	4:e9dfb4ca4277	1864	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
kenjiArai	4:e9dfb4ca4277	1865
kenjiArai	4:e9dfb4ca4277	1866	/* Debug Core Register Selector Register Definitions */
kenjiArai	4:e9dfb4ca4277	1867	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
kenjiArai	4:e9dfb4ca4277	1868	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
kenjiArai	4:e9dfb4ca4277	1869
kenjiArai	4:e9dfb4ca4277	1870	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
kenjiArai	4:e9dfb4ca4277	1871	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
kenjiArai	4:e9dfb4ca4277	1872
kenjiArai	4:e9dfb4ca4277	1873	/* Debug Exception and Monitor Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	1874	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
kenjiArai	4:e9dfb4ca4277	1875	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
kenjiArai	4:e9dfb4ca4277	1876
kenjiArai	4:e9dfb4ca4277	1877	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
kenjiArai	4:e9dfb4ca4277	1878	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
kenjiArai	4:e9dfb4ca4277	1879
kenjiArai	4:e9dfb4ca4277	1880	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
kenjiArai	4:e9dfb4ca4277	1881	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
kenjiArai	4:e9dfb4ca4277	1882
kenjiArai	4:e9dfb4ca4277	1883	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
kenjiArai	4:e9dfb4ca4277	1884	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
kenjiArai	4:e9dfb4ca4277	1885
kenjiArai	4:e9dfb4ca4277	1886	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
kenjiArai	4:e9dfb4ca4277	1887	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
kenjiArai	4:e9dfb4ca4277	1888
kenjiArai	4:e9dfb4ca4277	1889	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
kenjiArai	4:e9dfb4ca4277	1890	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
kenjiArai	4:e9dfb4ca4277	1891
kenjiArai	4:e9dfb4ca4277	1892	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
kenjiArai	4:e9dfb4ca4277	1893	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
kenjiArai	4:e9dfb4ca4277	1894
kenjiArai	4:e9dfb4ca4277	1895	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
kenjiArai	4:e9dfb4ca4277	1896	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
kenjiArai	4:e9dfb4ca4277	1897
kenjiArai	4:e9dfb4ca4277	1898	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
kenjiArai	4:e9dfb4ca4277	1899	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
kenjiArai	4:e9dfb4ca4277	1900
kenjiArai	4:e9dfb4ca4277	1901	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
kenjiArai	4:e9dfb4ca4277	1902	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
kenjiArai	4:e9dfb4ca4277	1903
kenjiArai	4:e9dfb4ca4277	1904	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
kenjiArai	4:e9dfb4ca4277	1905	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
kenjiArai	4:e9dfb4ca4277	1906
kenjiArai	4:e9dfb4ca4277	1907	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
kenjiArai	4:e9dfb4ca4277	1908	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
kenjiArai	4:e9dfb4ca4277	1909
kenjiArai	4:e9dfb4ca4277	1910	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
kenjiArai	4:e9dfb4ca4277	1911	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
kenjiArai	4:e9dfb4ca4277	1912
kenjiArai	4:e9dfb4ca4277	1913	/* Debug Authentication Control Register Definitions */
kenjiArai	4:e9dfb4ca4277	1914	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
kenjiArai	4:e9dfb4ca4277	1915	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
kenjiArai	4:e9dfb4ca4277	1916
kenjiArai	4:e9dfb4ca4277	1917	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
kenjiArai	4:e9dfb4ca4277	1918	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
kenjiArai	4:e9dfb4ca4277	1919
kenjiArai	4:e9dfb4ca4277	1920	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
kenjiArai	4:e9dfb4ca4277	1921	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
kenjiArai	4:e9dfb4ca4277	1922
kenjiArai	4:e9dfb4ca4277	1923	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
kenjiArai	4:e9dfb4ca4277	1924	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
kenjiArai	4:e9dfb4ca4277	1925
kenjiArai	4:e9dfb4ca4277	1926	/* Debug Security Control and Status Register Definitions */
kenjiArai	4:e9dfb4ca4277	1927	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
kenjiArai	4:e9dfb4ca4277	1928	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
kenjiArai	4:e9dfb4ca4277	1929
kenjiArai	4:e9dfb4ca4277	1930	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
kenjiArai	4:e9dfb4ca4277	1931	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
kenjiArai	4:e9dfb4ca4277	1932
kenjiArai	4:e9dfb4ca4277	1933	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
kenjiArai	4:e9dfb4ca4277	1934	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
kenjiArai	4:e9dfb4ca4277	1935
kenjiArai	4:e9dfb4ca4277	1936	/@} end of group CMSIS_CoreDebug /
kenjiArai	4:e9dfb4ca4277	1937
kenjiArai	4:e9dfb4ca4277	1938
kenjiArai	4:e9dfb4ca4277	1939	/**
kenjiArai	4:e9dfb4ca4277	1940	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	1941	\defgroup CMSIS_core_bitfield Core register bit field macros
kenjiArai	4:e9dfb4ca4277	1942	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
kenjiArai	4:e9dfb4ca4277	1943	@{
kenjiArai	4:e9dfb4ca4277	1944	*/
kenjiArai	4:e9dfb4ca4277	1945
kenjiArai	4:e9dfb4ca4277	1946	/**
kenjiArai	4:e9dfb4ca4277	1947	\brief Mask and shift a bit field value for use in a register bit range.
kenjiArai	4:e9dfb4ca4277	1948	\param[in] field Name of the register bit field.
kenjiArai	4:e9dfb4ca4277	1949	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
kenjiArai	4:e9dfb4ca4277	1950	\return Masked and shifted value.
kenjiArai	4:e9dfb4ca4277	1951	*/
kenjiArai	4:e9dfb4ca4277	1952	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
kenjiArai	4:e9dfb4ca4277	1953
kenjiArai	4:e9dfb4ca4277	1954	/**
kenjiArai	4:e9dfb4ca4277	1955	\brief Mask and shift a register value to extract a bit filed value.
kenjiArai	4:e9dfb4ca4277	1956	\param[in] field Name of the register bit field.
kenjiArai	4:e9dfb4ca4277	1957	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
kenjiArai	4:e9dfb4ca4277	1958	\return Masked and shifted bit field value.
kenjiArai	4:e9dfb4ca4277	1959	*/
kenjiArai	4:e9dfb4ca4277	1960	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
kenjiArai	4:e9dfb4ca4277	1961
kenjiArai	4:e9dfb4ca4277	1962	/@} end of group CMSIS_core_bitfield /
kenjiArai	4:e9dfb4ca4277	1963
kenjiArai	4:e9dfb4ca4277	1964
kenjiArai	4:e9dfb4ca4277	1965	/**
kenjiArai	4:e9dfb4ca4277	1966	\ingroup CMSIS_core_register
kenjiArai	4:e9dfb4ca4277	1967	\defgroup CMSIS_core_base Core Definitions
kenjiArai	4:e9dfb4ca4277	1968	\brief Definitions for base addresses, unions, and structures.
kenjiArai	4:e9dfb4ca4277	1969	@{
kenjiArai	4:e9dfb4ca4277	1970	*/
kenjiArai	4:e9dfb4ca4277	1971
kenjiArai	4:e9dfb4ca4277	1972	/* Memory mapping of Core Hardware */
kenjiArai	4:e9dfb4ca4277	1973	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
kenjiArai	4:e9dfb4ca4277	1974	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
kenjiArai	4:e9dfb4ca4277	1975	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
kenjiArai	4:e9dfb4ca4277	1976	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
kenjiArai	4:e9dfb4ca4277	1977	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
kenjiArai	4:e9dfb4ca4277	1978	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
kenjiArai	4:e9dfb4ca4277	1979	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
kenjiArai	4:e9dfb4ca4277	1980	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
kenjiArai	4:e9dfb4ca4277	1981
kenjiArai	4:e9dfb4ca4277	1982	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
kenjiArai	4:e9dfb4ca4277	1983	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
kenjiArai	4:e9dfb4ca4277	1984	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
kenjiArai	4:e9dfb4ca4277	1985	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
kenjiArai	4:e9dfb4ca4277	1986	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
kenjiArai	4:e9dfb4ca4277	1987	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
kenjiArai	4:e9dfb4ca4277	1988	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
kenjiArai	4:e9dfb4ca4277	1989	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
kenjiArai	4:e9dfb4ca4277	1990
kenjiArai	4:e9dfb4ca4277	1991	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	1992	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
kenjiArai	4:e9dfb4ca4277	1993	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
kenjiArai	4:e9dfb4ca4277	1994	#endif
kenjiArai	4:e9dfb4ca4277	1995
kenjiArai	4:e9dfb4ca4277	1996	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kenjiArai	4:e9dfb4ca4277	1997	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
kenjiArai	4:e9dfb4ca4277	1998	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
kenjiArai	4:e9dfb4ca4277	1999	#endif
kenjiArai	4:e9dfb4ca4277	2000
kenjiArai	4:e9dfb4ca4277	2001	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
kenjiArai	4:e9dfb4ca4277	2002	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
kenjiArai	4:e9dfb4ca4277	2003
kenjiArai	4:e9dfb4ca4277	2004	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kenjiArai	4:e9dfb4ca4277	2005	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
kenjiArai	4:e9dfb4ca4277	2006	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
kenjiArai	4:e9dfb4ca4277	2007	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
kenjiArai	4:e9dfb4ca4277	2008	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
kenjiArai	4:e9dfb4ca4277	2009	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
kenjiArai	4:e9dfb4ca4277	2010
kenjiArai	4:e9dfb4ca4277	2011	#define SCnSCB_NS ((SCnSCB_Type ) SCS_BASE_NS ) /!< System control Register not in SCB(non-secure address space) */
kenjiArai	4:e9dfb4ca4277	2012	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
kenjiArai	4:e9dfb4ca4277	2013	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
kenjiArai	4:e9dfb4ca4277	2014	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
kenjiArai	4:e9dfb4ca4277	2015	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
kenjiArai	4:e9dfb4ca4277	2016
kenjiArai	4:e9dfb4ca4277	2017	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	2018	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
kenjiArai	4:e9dfb4ca4277	2019	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
kenjiArai	4:e9dfb4ca4277	2020	#endif
kenjiArai	4:e9dfb4ca4277	2021
kenjiArai	4:e9dfb4ca4277	2022	#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /!< Floating Point Unit (non-secure address space) /
kenjiArai	4:e9dfb4ca4277	2023	#define FPU_NS ((FPU_Type ) FPU_BASE_NS ) /!< Floating Point Unit (non-secure address space) */
kenjiArai	4:e9dfb4ca4277	2024
kenjiArai	4:e9dfb4ca4277	2025	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
kenjiArai	4:e9dfb4ca4277	2026	/@} /
kenjiArai	4:e9dfb4ca4277	2027
kenjiArai	4:e9dfb4ca4277	2028
kenjiArai	4:e9dfb4ca4277	2029
kenjiArai	4:e9dfb4ca4277	2030	/*******************************************************************************
kenjiArai	4:e9dfb4ca4277	2031	* Hardware Abstraction Layer
kenjiArai	4:e9dfb4ca4277	2032	Core Function Interface contains:
kenjiArai	4:e9dfb4ca4277	2033	- Core NVIC Functions
kenjiArai	4:e9dfb4ca4277	2034	- Core SysTick Functions
kenjiArai	4:e9dfb4ca4277	2035	- Core Debug Functions
kenjiArai	4:e9dfb4ca4277	2036	- Core Register Access Functions
kenjiArai	4:e9dfb4ca4277	2037	******************************************************************************/
kenjiArai	4:e9dfb4ca4277	2038	/**
kenjiArai	4:e9dfb4ca4277	2039	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
kenjiArai	4:e9dfb4ca4277	2040	*/
kenjiArai	4:e9dfb4ca4277	2041
kenjiArai	4:e9dfb4ca4277	2042
kenjiArai	4:e9dfb4ca4277	2043
kenjiArai	4:e9dfb4ca4277	2044	/* ########################## NVIC functions #################################### */
kenjiArai	4:e9dfb4ca4277	2045	/**
kenjiArai	4:e9dfb4ca4277	2046	\ingroup CMSIS_Core_FunctionInterface
kenjiArai	4:e9dfb4ca4277	2047	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
kenjiArai	4:e9dfb4ca4277	2048	\brief Functions that manage interrupts and exceptions via the NVIC.
kenjiArai	4:e9dfb4ca4277	2049	@{
kenjiArai	4:e9dfb4ca4277	2050	*/
kenjiArai	4:e9dfb4ca4277	2051
kenjiArai	4:e9dfb4ca4277	2052	#ifdef CMSIS_NVIC_VIRTUAL
kenjiArai	4:e9dfb4ca4277	2053	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
kenjiArai	4:e9dfb4ca4277	2054	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
kenjiArai	4:e9dfb4ca4277	2055	#endif
kenjiArai	4:e9dfb4ca4277	2056	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
kenjiArai	4:e9dfb4ca4277	2057	#else
kenjiArai	4:e9dfb4ca4277	2058	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
kenjiArai	4:e9dfb4ca4277	2059	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
kenjiArai	4:e9dfb4ca4277	2060	#define NVIC_EnableIRQ __NVIC_EnableIRQ
kenjiArai	4:e9dfb4ca4277	2061	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
kenjiArai	4:e9dfb4ca4277	2062	#define NVIC_DisableIRQ __NVIC_DisableIRQ
kenjiArai	4:e9dfb4ca4277	2063	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
kenjiArai	4:e9dfb4ca4277	2064	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
kenjiArai	4:e9dfb4ca4277	2065	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
kenjiArai	4:e9dfb4ca4277	2066	#define NVIC_GetActive __NVIC_GetActive
kenjiArai	4:e9dfb4ca4277	2067	#define NVIC_SetPriority __NVIC_SetPriority
kenjiArai	4:e9dfb4ca4277	2068	#define NVIC_GetPriority __NVIC_GetPriority
kenjiArai	4:e9dfb4ca4277	2069	#define NVIC_SystemReset __NVIC_SystemReset
kenjiArai	4:e9dfb4ca4277	2070	#endif /* CMSIS_NVIC_VIRTUAL */
kenjiArai	4:e9dfb4ca4277	2071
kenjiArai	4:e9dfb4ca4277	2072	#ifdef CMSIS_VECTAB_VIRTUAL
kenjiArai	4:e9dfb4ca4277	2073	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
kenjiArai	4:e9dfb4ca4277	2074	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
kenjiArai	4:e9dfb4ca4277	2075	#endif
kenjiArai	4:e9dfb4ca4277	2076	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
kenjiArai	4:e9dfb4ca4277	2077	#else
kenjiArai	4:e9dfb4ca4277	2078	#define NVIC_SetVector __NVIC_SetVector
kenjiArai	4:e9dfb4ca4277	2079	#define NVIC_GetVector __NVIC_GetVector
kenjiArai	4:e9dfb4ca4277	2080	#endif /* (CMSIS_VECTAB_VIRTUAL) */
kenjiArai	4:e9dfb4ca4277	2081
kenjiArai	4:e9dfb4ca4277	2082	#define NVIC_USER_IRQ_OFFSET 16
kenjiArai	4:e9dfb4ca4277	2083
kenjiArai	4:e9dfb4ca4277	2084
kenjiArai	4:e9dfb4ca4277	2085	/* Special LR values for Secure/Non-Secure call handling and exception handling */
kenjiArai	4:e9dfb4ca4277	2086
kenjiArai	4:e9dfb4ca4277	2087	/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
kenjiArai	4:e9dfb4ca4277	2088	#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
kenjiArai	4:e9dfb4ca4277	2089
kenjiArai	4:e9dfb4ca4277	2090	/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
kenjiArai	4:e9dfb4ca4277	2091	#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
kenjiArai	4:e9dfb4ca4277	2092	#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
kenjiArai	4:e9dfb4ca4277	2093	#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
kenjiArai	4:e9dfb4ca4277	2094	#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
kenjiArai	4:e9dfb4ca4277	2095	#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
kenjiArai	4:e9dfb4ca4277	2096	#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
kenjiArai	4:e9dfb4ca4277	2097	#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
kenjiArai	4:e9dfb4ca4277	2098
kenjiArai	4:e9dfb4ca4277	2099	/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
kenjiArai	4:e9dfb4ca4277	2100	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
kenjiArai	4:e9dfb4ca4277	2101	#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
kenjiArai	4:e9dfb4ca4277	2102	#else
kenjiArai	4:e9dfb4ca4277	2103	#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
kenjiArai	4:e9dfb4ca4277	2104	#endif
kenjiArai	4:e9dfb4ca4277	2105
kenjiArai	4:e9dfb4ca4277	2106
kenjiArai	4:e9dfb4ca4277	2107	/**
kenjiArai	4:e9dfb4ca4277	2108	\brief Set Priority Grouping
kenjiArai	4:e9dfb4ca4277	2109	\details Sets the priority grouping field using the required unlock sequence.
kenjiArai	4:e9dfb4ca4277	2110	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
kenjiArai	4:e9dfb4ca4277	2111	Only values from 0..7 are used.
kenjiArai	4:e9dfb4ca4277	2112	In case of a conflict between priority grouping and available
kenjiArai	4:e9dfb4ca4277	2113	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
kenjiArai	4:e9dfb4ca4277	2114	\param [in] PriorityGroup Priority grouping field.
kenjiArai	4:e9dfb4ca4277	2115	*/
kenjiArai	4:e9dfb4ca4277	2116	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
kenjiArai	4:e9dfb4ca4277	2117	{
kenjiArai	4:e9dfb4ca4277	2118	uint32_t reg_value;
kenjiArai	4:e9dfb4ca4277	2119	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
kenjiArai	4:e9dfb4ca4277	2120
kenjiArai	4:e9dfb4ca4277	2121	reg_value = SCB->AIRCR; /* read old register configuration */
kenjiArai	4:e9dfb4ca4277	2122	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
kenjiArai	4:e9dfb4ca4277	2123	reg_value = (reg_value \|
kenjiArai	4:e9dfb4ca4277	2124	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
kenjiArai	4:e9dfb4ca4277	2125	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
kenjiArai	4:e9dfb4ca4277	2126	SCB->AIRCR = reg_value;
kenjiArai	4:e9dfb4ca4277	2127	}
kenjiArai	4:e9dfb4ca4277	2128
kenjiArai	4:e9dfb4ca4277	2129
kenjiArai	4:e9dfb4ca4277	2130	/**
kenjiArai	4:e9dfb4ca4277	2131	\brief Get Priority Grouping
kenjiArai	4:e9dfb4ca4277	2132	\details Reads the priority grouping field from the NVIC Interrupt Controller.
kenjiArai	4:e9dfb4ca4277	2133	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
kenjiArai	4:e9dfb4ca4277	2134	*/
kenjiArai	4:e9dfb4ca4277	2135	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
kenjiArai	4:e9dfb4ca4277	2136	{
kenjiArai	4:e9dfb4ca4277	2137	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
kenjiArai	4:e9dfb4ca4277	2138	}
kenjiArai	4:e9dfb4ca4277	2139
kenjiArai	4:e9dfb4ca4277	2140
kenjiArai	4:e9dfb4ca4277	2141	/**
kenjiArai	4:e9dfb4ca4277	2142	\brief Enable Interrupt
kenjiArai	4:e9dfb4ca4277	2143	\details Enables a device specific interrupt in the NVIC interrupt controller.
kenjiArai	4:e9dfb4ca4277	2144	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	2145	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	2146	*/
kenjiArai	4:e9dfb4ca4277	2147	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2148	{
kenjiArai	4:e9dfb4ca4277	2149	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2150	{
kenjiArai	4:e9dfb4ca4277	2151	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kenjiArai	4:e9dfb4ca4277	2152	}
kenjiArai	4:e9dfb4ca4277	2153	}
kenjiArai	4:e9dfb4ca4277	2154
kenjiArai	4:e9dfb4ca4277	2155
kenjiArai	4:e9dfb4ca4277	2156	/**
kenjiArai	4:e9dfb4ca4277	2157	\brief Get Interrupt Enable status
kenjiArai	4:e9dfb4ca4277	2158	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
kenjiArai	4:e9dfb4ca4277	2159	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	2160	\return 0 Interrupt is not enabled.
kenjiArai	4:e9dfb4ca4277	2161	\return 1 Interrupt is enabled.
kenjiArai	4:e9dfb4ca4277	2162	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	2163	*/
kenjiArai	4:e9dfb4ca4277	2164	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2165	{
kenjiArai	4:e9dfb4ca4277	2166	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2167	{
kenjiArai	4:e9dfb4ca4277	2168	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kenjiArai	4:e9dfb4ca4277	2169	}
kenjiArai	4:e9dfb4ca4277	2170	else
kenjiArai	4:e9dfb4ca4277	2171	{
kenjiArai	4:e9dfb4ca4277	2172	return(0U);
kenjiArai	4:e9dfb4ca4277	2173	}
kenjiArai	4:e9dfb4ca4277	2174	}
kenjiArai	4:e9dfb4ca4277	2175
kenjiArai	4:e9dfb4ca4277	2176
kenjiArai	4:e9dfb4ca4277	2177	/**
kenjiArai	4:e9dfb4ca4277	2178	\brief Disable Interrupt
kenjiArai	4:e9dfb4ca4277	2179	\details Disables a device specific interrupt in the NVIC interrupt controller.
kenjiArai	4:e9dfb4ca4277	2180	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	2181	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	2182	*/
kenjiArai	4:e9dfb4ca4277	2183	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2184	{
kenjiArai	4:e9dfb4ca4277	2185	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2186	{
kenjiArai	4:e9dfb4ca4277	2187	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kenjiArai	4:e9dfb4ca4277	2188	__DSB();
kenjiArai	4:e9dfb4ca4277	2189	__ISB();
kenjiArai	4:e9dfb4ca4277	2190	}
kenjiArai	4:e9dfb4ca4277	2191	}
kenjiArai	4:e9dfb4ca4277	2192
kenjiArai	4:e9dfb4ca4277	2193
kenjiArai	4:e9dfb4ca4277	2194	/**
kenjiArai	4:e9dfb4ca4277	2195	\brief Get Pending Interrupt
kenjiArai	4:e9dfb4ca4277	2196	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
kenjiArai	4:e9dfb4ca4277	2197	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	2198	\return 0 Interrupt status is not pending.
kenjiArai	4:e9dfb4ca4277	2199	\return 1 Interrupt status is pending.
kenjiArai	4:e9dfb4ca4277	2200	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	2201	*/
kenjiArai	4:e9dfb4ca4277	2202	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2203	{
kenjiArai	4:e9dfb4ca4277	2204	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2205	{
kenjiArai	4:e9dfb4ca4277	2206	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kenjiArai	4:e9dfb4ca4277	2207	}
kenjiArai	4:e9dfb4ca4277	2208	else
kenjiArai	4:e9dfb4ca4277	2209	{
kenjiArai	4:e9dfb4ca4277	2210	return(0U);
kenjiArai	4:e9dfb4ca4277	2211	}
kenjiArai	4:e9dfb4ca4277	2212	}
kenjiArai	4:e9dfb4ca4277	2213
kenjiArai	4:e9dfb4ca4277	2214
kenjiArai	4:e9dfb4ca4277	2215	/**
kenjiArai	4:e9dfb4ca4277	2216	\brief Set Pending Interrupt
kenjiArai	4:e9dfb4ca4277	2217	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
kenjiArai	4:e9dfb4ca4277	2218	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	2219	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	2220	*/
kenjiArai	4:e9dfb4ca4277	2221	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2222	{
kenjiArai	4:e9dfb4ca4277	2223	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2224	{
kenjiArai	4:e9dfb4ca4277	2225	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kenjiArai	4:e9dfb4ca4277	2226	}
kenjiArai	4:e9dfb4ca4277	2227	}
kenjiArai	4:e9dfb4ca4277	2228
kenjiArai	4:e9dfb4ca4277	2229
kenjiArai	4:e9dfb4ca4277	2230	/**
kenjiArai	4:e9dfb4ca4277	2231	\brief Clear Pending Interrupt
kenjiArai	4:e9dfb4ca4277	2232	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
kenjiArai	4:e9dfb4ca4277	2233	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	2234	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	2235	*/
kenjiArai	4:e9dfb4ca4277	2236	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2237	{
kenjiArai	4:e9dfb4ca4277	2238	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2239	{
kenjiArai	4:e9dfb4ca4277	2240	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kenjiArai	4:e9dfb4ca4277	2241	}
kenjiArai	4:e9dfb4ca4277	2242	}
kenjiArai	4:e9dfb4ca4277	2243
kenjiArai	4:e9dfb4ca4277	2244
kenjiArai	4:e9dfb4ca4277	2245	/**
kenjiArai	4:e9dfb4ca4277	2246	\brief Get Active Interrupt
kenjiArai	4:e9dfb4ca4277	2247	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
kenjiArai	4:e9dfb4ca4277	2248	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	2249	\return 0 Interrupt status is not active.
kenjiArai	4:e9dfb4ca4277	2250	\return 1 Interrupt status is active.
kenjiArai	4:e9dfb4ca4277	2251	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	2252	*/
kenjiArai	4:e9dfb4ca4277	2253	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2254	{
kenjiArai	4:e9dfb4ca4277	2255	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2256	{
kenjiArai	4:e9dfb4ca4277	2257	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kenjiArai	4:e9dfb4ca4277	2258	}
kenjiArai	4:e9dfb4ca4277	2259	else
kenjiArai	4:e9dfb4ca4277	2260	{
kenjiArai	4:e9dfb4ca4277	2261	return(0U);
kenjiArai	4:e9dfb4ca4277	2262	}
kenjiArai	4:e9dfb4ca4277	2263	}
kenjiArai	4:e9dfb4ca4277	2264
kenjiArai	4:e9dfb4ca4277	2265
kenjiArai	4:e9dfb4ca4277	2266	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kenjiArai	4:e9dfb4ca4277	2267	/**
kenjiArai	4:e9dfb4ca4277	2268	\brief Get Interrupt Target State
kenjiArai	4:e9dfb4ca4277	2269	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
kenjiArai	4:e9dfb4ca4277	2270	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	2271	\return 0 if interrupt is assigned to Secure
kenjiArai	4:e9dfb4ca4277	2272	\return 1 if interrupt is assigned to Non Secure
kenjiArai	4:e9dfb4ca4277	2273	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	2274	*/
kenjiArai	4:e9dfb4ca4277	2275	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2276	{
kenjiArai	4:e9dfb4ca4277	2277	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2278	{
kenjiArai	4:e9dfb4ca4277	2279	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kenjiArai	4:e9dfb4ca4277	2280	}
kenjiArai	4:e9dfb4ca4277	2281	else
kenjiArai	4:e9dfb4ca4277	2282	{
kenjiArai	4:e9dfb4ca4277	2283	return(0U);
kenjiArai	4:e9dfb4ca4277	2284	}
kenjiArai	4:e9dfb4ca4277	2285	}
kenjiArai	4:e9dfb4ca4277	2286
kenjiArai	4:e9dfb4ca4277	2287
kenjiArai	4:e9dfb4ca4277	2288	/**
kenjiArai	4:e9dfb4ca4277	2289	\brief Set Interrupt Target State
kenjiArai	4:e9dfb4ca4277	2290	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
kenjiArai	4:e9dfb4ca4277	2291	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	2292	\return 0 if interrupt is assigned to Secure
kenjiArai	4:e9dfb4ca4277	2293	1 if interrupt is assigned to Non Secure
kenjiArai	4:e9dfb4ca4277	2294	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	2295	*/
kenjiArai	4:e9dfb4ca4277	2296	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2297	{
kenjiArai	4:e9dfb4ca4277	2298	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2299	{
kenjiArai	4:e9dfb4ca4277	2300	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
kenjiArai	4:e9dfb4ca4277	2301	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kenjiArai	4:e9dfb4ca4277	2302	}
kenjiArai	4:e9dfb4ca4277	2303	else
kenjiArai	4:e9dfb4ca4277	2304	{
kenjiArai	4:e9dfb4ca4277	2305	return(0U);
kenjiArai	4:e9dfb4ca4277	2306	}
kenjiArai	4:e9dfb4ca4277	2307	}
kenjiArai	4:e9dfb4ca4277	2308
kenjiArai	4:e9dfb4ca4277	2309
kenjiArai	4:e9dfb4ca4277	2310	/**
kenjiArai	4:e9dfb4ca4277	2311	\brief Clear Interrupt Target State
kenjiArai	4:e9dfb4ca4277	2312	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
kenjiArai	4:e9dfb4ca4277	2313	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	2314	\return 0 if interrupt is assigned to Secure
kenjiArai	4:e9dfb4ca4277	2315	1 if interrupt is assigned to Non Secure
kenjiArai	4:e9dfb4ca4277	2316	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	2317	*/
kenjiArai	4:e9dfb4ca4277	2318	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2319	{
kenjiArai	4:e9dfb4ca4277	2320	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2321	{
kenjiArai	4:e9dfb4ca4277	2322	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
kenjiArai	4:e9dfb4ca4277	2323	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kenjiArai	4:e9dfb4ca4277	2324	}
kenjiArai	4:e9dfb4ca4277	2325	else
kenjiArai	4:e9dfb4ca4277	2326	{
kenjiArai	4:e9dfb4ca4277	2327	return(0U);
kenjiArai	4:e9dfb4ca4277	2328	}
kenjiArai	4:e9dfb4ca4277	2329	}
kenjiArai	4:e9dfb4ca4277	2330	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
kenjiArai	4:e9dfb4ca4277	2331
kenjiArai	4:e9dfb4ca4277	2332
kenjiArai	4:e9dfb4ca4277	2333	/**
kenjiArai	4:e9dfb4ca4277	2334	\brief Set Interrupt Priority
kenjiArai	4:e9dfb4ca4277	2335	\details Sets the priority of a device specific interrupt or a processor exception.
kenjiArai	4:e9dfb4ca4277	2336	The interrupt number can be positive to specify a device specific interrupt,
kenjiArai	4:e9dfb4ca4277	2337	or negative to specify a processor exception.
kenjiArai	4:e9dfb4ca4277	2338	\param [in] IRQn Interrupt number.
kenjiArai	4:e9dfb4ca4277	2339	\param [in] priority Priority to set.
kenjiArai	4:e9dfb4ca4277	2340	\note The priority cannot be set for every processor exception.
kenjiArai	4:e9dfb4ca4277	2341	*/
kenjiArai	4:e9dfb4ca4277	2342	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
kenjiArai	4:e9dfb4ca4277	2343	{
kenjiArai	4:e9dfb4ca4277	2344	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2345	{
kenjiArai	4:e9dfb4ca4277	2346	NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
kenjiArai	4:e9dfb4ca4277	2347	}
kenjiArai	4:e9dfb4ca4277	2348	else
kenjiArai	4:e9dfb4ca4277	2349	{
kenjiArai	4:e9dfb4ca4277	2350	SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
kenjiArai	4:e9dfb4ca4277	2351	}
kenjiArai	4:e9dfb4ca4277	2352	}
kenjiArai	4:e9dfb4ca4277	2353
kenjiArai	4:e9dfb4ca4277	2354
kenjiArai	4:e9dfb4ca4277	2355	/**
kenjiArai	4:e9dfb4ca4277	2356	\brief Get Interrupt Priority
kenjiArai	4:e9dfb4ca4277	2357	\details Reads the priority of a device specific interrupt or a processor exception.
kenjiArai	4:e9dfb4ca4277	2358	The interrupt number can be positive to specify a device specific interrupt,
kenjiArai	4:e9dfb4ca4277	2359	or negative to specify a processor exception.
kenjiArai	4:e9dfb4ca4277	2360	\param [in] IRQn Interrupt number.
kenjiArai	4:e9dfb4ca4277	2361	\return Interrupt Priority.
kenjiArai	4:e9dfb4ca4277	2362	Value is aligned automatically to the implemented priority bits of the microcontroller.
kenjiArai	4:e9dfb4ca4277	2363	*/
kenjiArai	4:e9dfb4ca4277	2364	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2365	{
kenjiArai	4:e9dfb4ca4277	2366
kenjiArai	4:e9dfb4ca4277	2367	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2368	{
kenjiArai	4:e9dfb4ca4277	2369	return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
kenjiArai	4:e9dfb4ca4277	2370	}
kenjiArai	4:e9dfb4ca4277	2371	else
kenjiArai	4:e9dfb4ca4277	2372	{
kenjiArai	4:e9dfb4ca4277	2373	return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
kenjiArai	4:e9dfb4ca4277	2374	}
kenjiArai	4:e9dfb4ca4277	2375	}
kenjiArai	4:e9dfb4ca4277	2376
kenjiArai	4:e9dfb4ca4277	2377
kenjiArai	4:e9dfb4ca4277	2378	/**
kenjiArai	4:e9dfb4ca4277	2379	\brief Encode Priority
kenjiArai	4:e9dfb4ca4277	2380	\details Encodes the priority for an interrupt with the given priority group,
kenjiArai	4:e9dfb4ca4277	2381	preemptive priority value, and subpriority value.
kenjiArai	4:e9dfb4ca4277	2382	In case of a conflict between priority grouping and available
kenjiArai	4:e9dfb4ca4277	2383	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
kenjiArai	4:e9dfb4ca4277	2384	\param [in] PriorityGroup Used priority group.
kenjiArai	4:e9dfb4ca4277	2385	\param [in] PreemptPriority Preemptive priority value (starting from 0).
kenjiArai	4:e9dfb4ca4277	2386	\param [in] SubPriority Subpriority value (starting from 0).
kenjiArai	4:e9dfb4ca4277	2387	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
kenjiArai	4:e9dfb4ca4277	2388	*/
kenjiArai	4:e9dfb4ca4277	2389	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
kenjiArai	4:e9dfb4ca4277	2390	{
kenjiArai	4:e9dfb4ca4277	2391	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
kenjiArai	4:e9dfb4ca4277	2392	uint32_t PreemptPriorityBits;
kenjiArai	4:e9dfb4ca4277	2393	uint32_t SubPriorityBits;
kenjiArai	4:e9dfb4ca4277	2394
kenjiArai	4:e9dfb4ca4277	2395	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
kenjiArai	4:e9dfb4ca4277	2396	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
kenjiArai	4:e9dfb4ca4277	2397
kenjiArai	4:e9dfb4ca4277	2398	return (
kenjiArai	4:e9dfb4ca4277	2399	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
kenjiArai	4:e9dfb4ca4277	2400	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
kenjiArai	4:e9dfb4ca4277	2401	);
kenjiArai	4:e9dfb4ca4277	2402	}
kenjiArai	4:e9dfb4ca4277	2403
kenjiArai	4:e9dfb4ca4277	2404
kenjiArai	4:e9dfb4ca4277	2405	/**
kenjiArai	4:e9dfb4ca4277	2406	\brief Decode Priority
kenjiArai	4:e9dfb4ca4277	2407	\details Decodes an interrupt priority value with a given priority group to
kenjiArai	4:e9dfb4ca4277	2408	preemptive priority value and subpriority value.
kenjiArai	4:e9dfb4ca4277	2409	In case of a conflict between priority grouping and available
kenjiArai	4:e9dfb4ca4277	2410	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
kenjiArai	4:e9dfb4ca4277	2411	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
kenjiArai	4:e9dfb4ca4277	2412	\param [in] PriorityGroup Used priority group.
kenjiArai	4:e9dfb4ca4277	2413	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
kenjiArai	4:e9dfb4ca4277	2414	\param [out] pSubPriority Subpriority value (starting from 0).
kenjiArai	4:e9dfb4ca4277	2415	*/
kenjiArai	4:e9dfb4ca4277	2416	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
kenjiArai	4:e9dfb4ca4277	2417	{
kenjiArai	4:e9dfb4ca4277	2418	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
kenjiArai	4:e9dfb4ca4277	2419	uint32_t PreemptPriorityBits;
kenjiArai	4:e9dfb4ca4277	2420	uint32_t SubPriorityBits;
kenjiArai	4:e9dfb4ca4277	2421
kenjiArai	4:e9dfb4ca4277	2422	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
kenjiArai	4:e9dfb4ca4277	2423	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
kenjiArai	4:e9dfb4ca4277	2424
kenjiArai	4:e9dfb4ca4277	2425	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
kenjiArai	4:e9dfb4ca4277	2426	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
kenjiArai	4:e9dfb4ca4277	2427	}
kenjiArai	4:e9dfb4ca4277	2428
kenjiArai	4:e9dfb4ca4277	2429
kenjiArai	4:e9dfb4ca4277	2430	/**
kenjiArai	4:e9dfb4ca4277	2431	\brief Set Interrupt Vector
kenjiArai	4:e9dfb4ca4277	2432	\details Sets an interrupt vector in SRAM based interrupt vector table.
kenjiArai	4:e9dfb4ca4277	2433	The interrupt number can be positive to specify a device specific interrupt,
kenjiArai	4:e9dfb4ca4277	2434	or negative to specify a processor exception.
kenjiArai	4:e9dfb4ca4277	2435	VTOR must been relocated to SRAM before.
kenjiArai	4:e9dfb4ca4277	2436	\param [in] IRQn Interrupt number
kenjiArai	4:e9dfb4ca4277	2437	\param [in] vector Address of interrupt handler function
kenjiArai	4:e9dfb4ca4277	2438	*/
kenjiArai	4:e9dfb4ca4277	2439	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
kenjiArai	4:e9dfb4ca4277	2440	{
kenjiArai	4:e9dfb4ca4277	2441	uint32_t vectors = (uint32_t )SCB->VTOR;
kenjiArai	4:e9dfb4ca4277	2442	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
kenjiArai	4:e9dfb4ca4277	2443	}
kenjiArai	4:e9dfb4ca4277	2444
kenjiArai	4:e9dfb4ca4277	2445
kenjiArai	4:e9dfb4ca4277	2446	/**
kenjiArai	4:e9dfb4ca4277	2447	\brief Get Interrupt Vector
kenjiArai	4:e9dfb4ca4277	2448	\details Reads an interrupt vector from interrupt vector table.
kenjiArai	4:e9dfb4ca4277	2449	The interrupt number can be positive to specify a device specific interrupt,
kenjiArai	4:e9dfb4ca4277	2450	or negative to specify a processor exception.
kenjiArai	4:e9dfb4ca4277	2451	\param [in] IRQn Interrupt number.
kenjiArai	4:e9dfb4ca4277	2452	\return Address of interrupt handler function
kenjiArai	4:e9dfb4ca4277	2453	*/
kenjiArai	4:e9dfb4ca4277	2454	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2455	{
kenjiArai	4:e9dfb4ca4277	2456	uint32_t vectors = (uint32_t )SCB->VTOR;
kenjiArai	4:e9dfb4ca4277	2457	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
kenjiArai	4:e9dfb4ca4277	2458	}
kenjiArai	4:e9dfb4ca4277	2459
kenjiArai	4:e9dfb4ca4277	2460
kenjiArai	4:e9dfb4ca4277	2461	/**
kenjiArai	4:e9dfb4ca4277	2462	\brief System Reset
kenjiArai	4:e9dfb4ca4277	2463	\details Initiates a system reset request to reset the MCU.
kenjiArai	4:e9dfb4ca4277	2464	*/
kenjiArai	4:e9dfb4ca4277	2465	__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
kenjiArai	4:e9dfb4ca4277	2466	{
kenjiArai	4:e9dfb4ca4277	2467	__DSB(); /* Ensure all outstanding memory accesses included
kenjiArai	4:e9dfb4ca4277	2468	buffered write are completed before reset */
kenjiArai	4:e9dfb4ca4277	2469	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
kenjiArai	4:e9dfb4ca4277	2470	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
kenjiArai	4:e9dfb4ca4277	2471	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
kenjiArai	4:e9dfb4ca4277	2472	__DSB(); /* Ensure completion of memory access */
kenjiArai	4:e9dfb4ca4277	2473
kenjiArai	4:e9dfb4ca4277	2474	for(;;) /* wait until reset */
kenjiArai	4:e9dfb4ca4277	2475	{
kenjiArai	4:e9dfb4ca4277	2476	__NOP();
kenjiArai	4:e9dfb4ca4277	2477	}
kenjiArai	4:e9dfb4ca4277	2478	}
kenjiArai	4:e9dfb4ca4277	2479
kenjiArai	4:e9dfb4ca4277	2480	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kenjiArai	4:e9dfb4ca4277	2481	/**
kenjiArai	4:e9dfb4ca4277	2482	\brief Set Priority Grouping (non-secure)
kenjiArai	4:e9dfb4ca4277	2483	\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
kenjiArai	4:e9dfb4ca4277	2484	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
kenjiArai	4:e9dfb4ca4277	2485	Only values from 0..7 are used.
kenjiArai	4:e9dfb4ca4277	2486	In case of a conflict between priority grouping and available
kenjiArai	4:e9dfb4ca4277	2487	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
kenjiArai	4:e9dfb4ca4277	2488	\param [in] PriorityGroup Priority grouping field.
kenjiArai	4:e9dfb4ca4277	2489	*/
kenjiArai	4:e9dfb4ca4277	2490	__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
kenjiArai	4:e9dfb4ca4277	2491	{
kenjiArai	4:e9dfb4ca4277	2492	uint32_t reg_value;
kenjiArai	4:e9dfb4ca4277	2493	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
kenjiArai	4:e9dfb4ca4277	2494
kenjiArai	4:e9dfb4ca4277	2495	reg_value = SCB_NS->AIRCR; /* read old register configuration */
kenjiArai	4:e9dfb4ca4277	2496	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
kenjiArai	4:e9dfb4ca4277	2497	reg_value = (reg_value \|
kenjiArai	4:e9dfb4ca4277	2498	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
kenjiArai	4:e9dfb4ca4277	2499	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
kenjiArai	4:e9dfb4ca4277	2500	SCB_NS->AIRCR = reg_value;
kenjiArai	4:e9dfb4ca4277	2501	}
kenjiArai	4:e9dfb4ca4277	2502
kenjiArai	4:e9dfb4ca4277	2503
kenjiArai	4:e9dfb4ca4277	2504	/**
kenjiArai	4:e9dfb4ca4277	2505	\brief Get Priority Grouping (non-secure)
kenjiArai	4:e9dfb4ca4277	2506	\details Reads the priority grouping field from the non-secure NVIC when in secure state.
kenjiArai	4:e9dfb4ca4277	2507	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
kenjiArai	4:e9dfb4ca4277	2508	*/
kenjiArai	4:e9dfb4ca4277	2509	__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
kenjiArai	4:e9dfb4ca4277	2510	{
kenjiArai	4:e9dfb4ca4277	2511	return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
kenjiArai	4:e9dfb4ca4277	2512	}
kenjiArai	4:e9dfb4ca4277	2513
kenjiArai	4:e9dfb4ca4277	2514
kenjiArai	4:e9dfb4ca4277	2515	/**
kenjiArai	4:e9dfb4ca4277	2516	\brief Enable Interrupt (non-secure)
kenjiArai	4:e9dfb4ca4277	2517	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
kenjiArai	4:e9dfb4ca4277	2518	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	2519	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	2520	*/
kenjiArai	4:e9dfb4ca4277	2521	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2522	{
kenjiArai	4:e9dfb4ca4277	2523	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2524	{
kenjiArai	4:e9dfb4ca4277	2525	NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kenjiArai	4:e9dfb4ca4277	2526	}
kenjiArai	4:e9dfb4ca4277	2527	}
kenjiArai	4:e9dfb4ca4277	2528
kenjiArai	4:e9dfb4ca4277	2529
kenjiArai	4:e9dfb4ca4277	2530	/**
kenjiArai	4:e9dfb4ca4277	2531	\brief Get Interrupt Enable status (non-secure)
kenjiArai	4:e9dfb4ca4277	2532	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
kenjiArai	4:e9dfb4ca4277	2533	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	2534	\return 0 Interrupt is not enabled.
kenjiArai	4:e9dfb4ca4277	2535	\return 1 Interrupt is enabled.
kenjiArai	4:e9dfb4ca4277	2536	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	2537	*/
kenjiArai	4:e9dfb4ca4277	2538	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2539	{
kenjiArai	4:e9dfb4ca4277	2540	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2541	{
kenjiArai	4:e9dfb4ca4277	2542	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kenjiArai	4:e9dfb4ca4277	2543	}
kenjiArai	4:e9dfb4ca4277	2544	else
kenjiArai	4:e9dfb4ca4277	2545	{
kenjiArai	4:e9dfb4ca4277	2546	return(0U);
kenjiArai	4:e9dfb4ca4277	2547	}
kenjiArai	4:e9dfb4ca4277	2548	}
kenjiArai	4:e9dfb4ca4277	2549
kenjiArai	4:e9dfb4ca4277	2550
kenjiArai	4:e9dfb4ca4277	2551	/**
kenjiArai	4:e9dfb4ca4277	2552	\brief Disable Interrupt (non-secure)
kenjiArai	4:e9dfb4ca4277	2553	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
kenjiArai	4:e9dfb4ca4277	2554	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	2555	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	2556	*/
kenjiArai	4:e9dfb4ca4277	2557	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2558	{
kenjiArai	4:e9dfb4ca4277	2559	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2560	{
kenjiArai	4:e9dfb4ca4277	2561	NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kenjiArai	4:e9dfb4ca4277	2562	}
kenjiArai	4:e9dfb4ca4277	2563	}
kenjiArai	4:e9dfb4ca4277	2564
kenjiArai	4:e9dfb4ca4277	2565
kenjiArai	4:e9dfb4ca4277	2566	/**
kenjiArai	4:e9dfb4ca4277	2567	\brief Get Pending Interrupt (non-secure)
kenjiArai	4:e9dfb4ca4277	2568	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
kenjiArai	4:e9dfb4ca4277	2569	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	2570	\return 0 Interrupt status is not pending.
kenjiArai	4:e9dfb4ca4277	2571	\return 1 Interrupt status is pending.
kenjiArai	4:e9dfb4ca4277	2572	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	2573	*/
kenjiArai	4:e9dfb4ca4277	2574	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2575	{
kenjiArai	4:e9dfb4ca4277	2576	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2577	{
kenjiArai	4:e9dfb4ca4277	2578	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kenjiArai	4:e9dfb4ca4277	2579	}
kenjiArai	4:e9dfb4ca4277	2580	else
kenjiArai	4:e9dfb4ca4277	2581	{
kenjiArai	4:e9dfb4ca4277	2582	return(0U);
kenjiArai	4:e9dfb4ca4277	2583	}
kenjiArai	4:e9dfb4ca4277	2584	}
kenjiArai	4:e9dfb4ca4277	2585
kenjiArai	4:e9dfb4ca4277	2586
kenjiArai	4:e9dfb4ca4277	2587	/**
kenjiArai	4:e9dfb4ca4277	2588	\brief Set Pending Interrupt (non-secure)
kenjiArai	4:e9dfb4ca4277	2589	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
kenjiArai	4:e9dfb4ca4277	2590	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	2591	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	2592	*/
kenjiArai	4:e9dfb4ca4277	2593	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2594	{
kenjiArai	4:e9dfb4ca4277	2595	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2596	{
kenjiArai	4:e9dfb4ca4277	2597	NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kenjiArai	4:e9dfb4ca4277	2598	}
kenjiArai	4:e9dfb4ca4277	2599	}
kenjiArai	4:e9dfb4ca4277	2600
kenjiArai	4:e9dfb4ca4277	2601
kenjiArai	4:e9dfb4ca4277	2602	/**
kenjiArai	4:e9dfb4ca4277	2603	\brief Clear Pending Interrupt (non-secure)
kenjiArai	4:e9dfb4ca4277	2604	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
kenjiArai	4:e9dfb4ca4277	2605	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	2606	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	2607	*/
kenjiArai	4:e9dfb4ca4277	2608	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2609	{
kenjiArai	4:e9dfb4ca4277	2610	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2611	{
kenjiArai	4:e9dfb4ca4277	2612	NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kenjiArai	4:e9dfb4ca4277	2613	}
kenjiArai	4:e9dfb4ca4277	2614	}
kenjiArai	4:e9dfb4ca4277	2615
kenjiArai	4:e9dfb4ca4277	2616
kenjiArai	4:e9dfb4ca4277	2617	/**
kenjiArai	4:e9dfb4ca4277	2618	\brief Get Active Interrupt (non-secure)
kenjiArai	4:e9dfb4ca4277	2619	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
kenjiArai	4:e9dfb4ca4277	2620	\param [in] IRQn Device specific interrupt number.
kenjiArai	4:e9dfb4ca4277	2621	\return 0 Interrupt status is not active.
kenjiArai	4:e9dfb4ca4277	2622	\return 1 Interrupt status is active.
kenjiArai	4:e9dfb4ca4277	2623	\note IRQn must not be negative.
kenjiArai	4:e9dfb4ca4277	2624	*/
kenjiArai	4:e9dfb4ca4277	2625	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2626	{
kenjiArai	4:e9dfb4ca4277	2627	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2628	{
kenjiArai	4:e9dfb4ca4277	2629	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kenjiArai	4:e9dfb4ca4277	2630	}
kenjiArai	4:e9dfb4ca4277	2631	else
kenjiArai	4:e9dfb4ca4277	2632	{
kenjiArai	4:e9dfb4ca4277	2633	return(0U);
kenjiArai	4:e9dfb4ca4277	2634	}
kenjiArai	4:e9dfb4ca4277	2635	}
kenjiArai	4:e9dfb4ca4277	2636
kenjiArai	4:e9dfb4ca4277	2637
kenjiArai	4:e9dfb4ca4277	2638	/**
kenjiArai	4:e9dfb4ca4277	2639	\brief Set Interrupt Priority (non-secure)
kenjiArai	4:e9dfb4ca4277	2640	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
kenjiArai	4:e9dfb4ca4277	2641	The interrupt number can be positive to specify a device specific interrupt,
kenjiArai	4:e9dfb4ca4277	2642	or negative to specify a processor exception.
kenjiArai	4:e9dfb4ca4277	2643	\param [in] IRQn Interrupt number.
kenjiArai	4:e9dfb4ca4277	2644	\param [in] priority Priority to set.
kenjiArai	4:e9dfb4ca4277	2645	\note The priority cannot be set for every non-secure processor exception.
kenjiArai	4:e9dfb4ca4277	2646	*/
kenjiArai	4:e9dfb4ca4277	2647	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
kenjiArai	4:e9dfb4ca4277	2648	{
kenjiArai	4:e9dfb4ca4277	2649	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2650	{
kenjiArai	4:e9dfb4ca4277	2651	NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
kenjiArai	4:e9dfb4ca4277	2652	}
kenjiArai	4:e9dfb4ca4277	2653	else
kenjiArai	4:e9dfb4ca4277	2654	{
kenjiArai	4:e9dfb4ca4277	2655	SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
kenjiArai	4:e9dfb4ca4277	2656	}
kenjiArai	4:e9dfb4ca4277	2657	}
kenjiArai	4:e9dfb4ca4277	2658
kenjiArai	4:e9dfb4ca4277	2659
kenjiArai	4:e9dfb4ca4277	2660	/**
kenjiArai	4:e9dfb4ca4277	2661	\brief Get Interrupt Priority (non-secure)
kenjiArai	4:e9dfb4ca4277	2662	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
kenjiArai	4:e9dfb4ca4277	2663	The interrupt number can be positive to specify a device specific interrupt,
kenjiArai	4:e9dfb4ca4277	2664	or negative to specify a processor exception.
kenjiArai	4:e9dfb4ca4277	2665	\param [in] IRQn Interrupt number.
kenjiArai	4:e9dfb4ca4277	2666	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
kenjiArai	4:e9dfb4ca4277	2667	*/
kenjiArai	4:e9dfb4ca4277	2668	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
kenjiArai	4:e9dfb4ca4277	2669	{
kenjiArai	4:e9dfb4ca4277	2670
kenjiArai	4:e9dfb4ca4277	2671	if ((int32_t)(IRQn) >= 0)
kenjiArai	4:e9dfb4ca4277	2672	{
kenjiArai	4:e9dfb4ca4277	2673	return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
kenjiArai	4:e9dfb4ca4277	2674	}
kenjiArai	4:e9dfb4ca4277	2675	else
kenjiArai	4:e9dfb4ca4277	2676	{
kenjiArai	4:e9dfb4ca4277	2677	return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
kenjiArai	4:e9dfb4ca4277	2678	}
kenjiArai	4:e9dfb4ca4277	2679	}
kenjiArai	4:e9dfb4ca4277	2680	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
kenjiArai	4:e9dfb4ca4277	2681
kenjiArai	4:e9dfb4ca4277	2682	/@} end of CMSIS_Core_NVICFunctions /
kenjiArai	4:e9dfb4ca4277	2683
kenjiArai	4:e9dfb4ca4277	2684	/* ########################## MPU functions #################################### */
kenjiArai	4:e9dfb4ca4277	2685
kenjiArai	4:e9dfb4ca4277	2686	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kenjiArai	4:e9dfb4ca4277	2687
kenjiArai	4:e9dfb4ca4277	2688	#include "mpu_armv8.h"
kenjiArai	4:e9dfb4ca4277	2689
kenjiArai	4:e9dfb4ca4277	2690	#endif
kenjiArai	4:e9dfb4ca4277	2691
kenjiArai	4:e9dfb4ca4277	2692	/* ########################## FPU functions #################################### */
kenjiArai	4:e9dfb4ca4277	2693	/**
kenjiArai	4:e9dfb4ca4277	2694	\ingroup CMSIS_Core_FunctionInterface
kenjiArai	4:e9dfb4ca4277	2695	\defgroup CMSIS_Core_FpuFunctions FPU Functions
kenjiArai	4:e9dfb4ca4277	2696	\brief Function that provides FPU type.
kenjiArai	4:e9dfb4ca4277	2697	@{
kenjiArai	4:e9dfb4ca4277	2698	*/
kenjiArai	4:e9dfb4ca4277	2699
kenjiArai	4:e9dfb4ca4277	2700	/**
kenjiArai	4:e9dfb4ca4277	2701	\brief get FPU type
kenjiArai	4:e9dfb4ca4277	2702	\details returns the FPU type
kenjiArai	4:e9dfb4ca4277	2703	\returns
kenjiArai	4:e9dfb4ca4277	2704	- \b 0: No FPU
kenjiArai	4:e9dfb4ca4277	2705	- \b 1: Single precision FPU
kenjiArai	4:e9dfb4ca4277	2706	- \b 2: Double + Single precision FPU
kenjiArai	4:e9dfb4ca4277	2707	*/
kenjiArai	4:e9dfb4ca4277	2708	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
kenjiArai	4:e9dfb4ca4277	2709	{
kenjiArai	4:e9dfb4ca4277	2710	uint32_t mvfr0;
kenjiArai	4:e9dfb4ca4277	2711
kenjiArai	4:e9dfb4ca4277	2712	mvfr0 = FPU->MVFR0;
kenjiArai	4:e9dfb4ca4277	2713	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
kenjiArai	4:e9dfb4ca4277	2714	{
kenjiArai	4:e9dfb4ca4277	2715	return 2U; /* Double + Single precision FPU */
kenjiArai	4:e9dfb4ca4277	2716	}
kenjiArai	4:e9dfb4ca4277	2717	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
kenjiArai	4:e9dfb4ca4277	2718	{
kenjiArai	4:e9dfb4ca4277	2719	return 1U; /* Single precision FPU */
kenjiArai	4:e9dfb4ca4277	2720	}
kenjiArai	4:e9dfb4ca4277	2721	else
kenjiArai	4:e9dfb4ca4277	2722	{
kenjiArai	4:e9dfb4ca4277	2723	return 0U; /* No FPU */
kenjiArai	4:e9dfb4ca4277	2724	}
kenjiArai	4:e9dfb4ca4277	2725	}
kenjiArai	4:e9dfb4ca4277	2726
kenjiArai	4:e9dfb4ca4277	2727
kenjiArai	4:e9dfb4ca4277	2728	/@} end of CMSIS_Core_FpuFunctions /
kenjiArai	4:e9dfb4ca4277	2729
kenjiArai	4:e9dfb4ca4277	2730
kenjiArai	4:e9dfb4ca4277	2731
kenjiArai	4:e9dfb4ca4277	2732	/* ########################## SAU functions #################################### */
kenjiArai	4:e9dfb4ca4277	2733	/**
kenjiArai	4:e9dfb4ca4277	2734	\ingroup CMSIS_Core_FunctionInterface
kenjiArai	4:e9dfb4ca4277	2735	\defgroup CMSIS_Core_SAUFunctions SAU Functions
kenjiArai	4:e9dfb4ca4277	2736	\brief Functions that configure the SAU.
kenjiArai	4:e9dfb4ca4277	2737	@{
kenjiArai	4:e9dfb4ca4277	2738	*/
kenjiArai	4:e9dfb4ca4277	2739
kenjiArai	4:e9dfb4ca4277	2740	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kenjiArai	4:e9dfb4ca4277	2741
kenjiArai	4:e9dfb4ca4277	2742	/**
kenjiArai	4:e9dfb4ca4277	2743	\brief Enable SAU
kenjiArai	4:e9dfb4ca4277	2744	\details Enables the Security Attribution Unit (SAU).
kenjiArai	4:e9dfb4ca4277	2745	*/
kenjiArai	4:e9dfb4ca4277	2746	__STATIC_INLINE void TZ_SAU_Enable(void)
kenjiArai	4:e9dfb4ca4277	2747	{
kenjiArai	4:e9dfb4ca4277	2748	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
kenjiArai	4:e9dfb4ca4277	2749	}
kenjiArai	4:e9dfb4ca4277	2750
kenjiArai	4:e9dfb4ca4277	2751
kenjiArai	4:e9dfb4ca4277	2752
kenjiArai	4:e9dfb4ca4277	2753	/**
kenjiArai	4:e9dfb4ca4277	2754	\brief Disable SAU
kenjiArai	4:e9dfb4ca4277	2755	\details Disables the Security Attribution Unit (SAU).
kenjiArai	4:e9dfb4ca4277	2756	*/
kenjiArai	4:e9dfb4ca4277	2757	__STATIC_INLINE void TZ_SAU_Disable(void)
kenjiArai	4:e9dfb4ca4277	2758	{
kenjiArai	4:e9dfb4ca4277	2759	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
kenjiArai	4:e9dfb4ca4277	2760	}
kenjiArai	4:e9dfb4ca4277	2761
kenjiArai	4:e9dfb4ca4277	2762	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
kenjiArai	4:e9dfb4ca4277	2763
kenjiArai	4:e9dfb4ca4277	2764	/@} end of CMSIS_Core_SAUFunctions /
kenjiArai	4:e9dfb4ca4277	2765
kenjiArai	4:e9dfb4ca4277	2766
kenjiArai	4:e9dfb4ca4277	2767
kenjiArai	4:e9dfb4ca4277	2768
kenjiArai	4:e9dfb4ca4277	2769	/* ################################## SysTick function ############################################ */
kenjiArai	4:e9dfb4ca4277	2770	/**
kenjiArai	4:e9dfb4ca4277	2771	\ingroup CMSIS_Core_FunctionInterface
kenjiArai	4:e9dfb4ca4277	2772	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
kenjiArai	4:e9dfb4ca4277	2773	\brief Functions that configure the System.
kenjiArai	4:e9dfb4ca4277	2774	@{
kenjiArai	4:e9dfb4ca4277	2775	*/
kenjiArai	4:e9dfb4ca4277	2776
kenjiArai	4:e9dfb4ca4277	2777	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
kenjiArai	4:e9dfb4ca4277	2778
kenjiArai	4:e9dfb4ca4277	2779	/**
kenjiArai	4:e9dfb4ca4277	2780	\brief System Tick Configuration
kenjiArai	4:e9dfb4ca4277	2781	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
kenjiArai	4:e9dfb4ca4277	2782	Counter is in free running mode to generate periodic interrupts.
kenjiArai	4:e9dfb4ca4277	2783	\param [in] ticks Number of ticks between two interrupts.
kenjiArai	4:e9dfb4ca4277	2784	\return 0 Function succeeded.
kenjiArai	4:e9dfb4ca4277	2785	\return 1 Function failed.
kenjiArai	4:e9dfb4ca4277	2786	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
kenjiArai	4:e9dfb4ca4277	2787	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
kenjiArai	4:e9dfb4ca4277	2788	must contain a vendor-specific implementation of this function.
kenjiArai	4:e9dfb4ca4277	2789	*/
kenjiArai	4:e9dfb4ca4277	2790	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
kenjiArai	4:e9dfb4ca4277	2791	{
kenjiArai	4:e9dfb4ca4277	2792	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
kenjiArai	4:e9dfb4ca4277	2793	{
kenjiArai	4:e9dfb4ca4277	2794	return (1UL); /* Reload value impossible */
kenjiArai	4:e9dfb4ca4277	2795	}
kenjiArai	4:e9dfb4ca4277	2796
kenjiArai	4:e9dfb4ca4277	2797	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
kenjiArai	4:e9dfb4ca4277	2798	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
kenjiArai	4:e9dfb4ca4277	2799	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
kenjiArai	4:e9dfb4ca4277	2800	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
kenjiArai	4:e9dfb4ca4277	2801	SysTick_CTRL_TICKINT_Msk \|
kenjiArai	4:e9dfb4ca4277	2802	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
kenjiArai	4:e9dfb4ca4277	2803	return (0UL); /* Function successful */
kenjiArai	4:e9dfb4ca4277	2804	}
kenjiArai	4:e9dfb4ca4277	2805
kenjiArai	4:e9dfb4ca4277	2806	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kenjiArai	4:e9dfb4ca4277	2807	/**
kenjiArai	4:e9dfb4ca4277	2808	\brief System Tick Configuration (non-secure)
kenjiArai	4:e9dfb4ca4277	2809	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
kenjiArai	4:e9dfb4ca4277	2810	Counter is in free running mode to generate periodic interrupts.
kenjiArai	4:e9dfb4ca4277	2811	\param [in] ticks Number of ticks between two interrupts.
kenjiArai	4:e9dfb4ca4277	2812	\return 0 Function succeeded.
kenjiArai	4:e9dfb4ca4277	2813	\return 1 Function failed.
kenjiArai	4:e9dfb4ca4277	2814	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
kenjiArai	4:e9dfb4ca4277	2815	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
kenjiArai	4:e9dfb4ca4277	2816	must contain a vendor-specific implementation of this function.
kenjiArai	4:e9dfb4ca4277	2817
kenjiArai	4:e9dfb4ca4277	2818	*/
kenjiArai	4:e9dfb4ca4277	2819	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
kenjiArai	4:e9dfb4ca4277	2820	{
kenjiArai	4:e9dfb4ca4277	2821	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
kenjiArai	4:e9dfb4ca4277	2822	{
kenjiArai	4:e9dfb4ca4277	2823	return (1UL); /* Reload value impossible */
kenjiArai	4:e9dfb4ca4277	2824	}
kenjiArai	4:e9dfb4ca4277	2825
kenjiArai	4:e9dfb4ca4277	2826	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
kenjiArai	4:e9dfb4ca4277	2827	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
kenjiArai	4:e9dfb4ca4277	2828	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
kenjiArai	4:e9dfb4ca4277	2829	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
kenjiArai	4:e9dfb4ca4277	2830	SysTick_CTRL_TICKINT_Msk \|
kenjiArai	4:e9dfb4ca4277	2831	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
kenjiArai	4:e9dfb4ca4277	2832	return (0UL); /* Function successful */
kenjiArai	4:e9dfb4ca4277	2833	}
kenjiArai	4:e9dfb4ca4277	2834	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
kenjiArai	4:e9dfb4ca4277	2835
kenjiArai	4:e9dfb4ca4277	2836	#endif
kenjiArai	4:e9dfb4ca4277	2837
kenjiArai	4:e9dfb4ca4277	2838	/@} end of CMSIS_Core_SysTickFunctions /
kenjiArai	4:e9dfb4ca4277	2839
kenjiArai	4:e9dfb4ca4277	2840
kenjiArai	4:e9dfb4ca4277	2841
kenjiArai	4:e9dfb4ca4277	2842	/* ##################################### Debug In/Output function ########################################### */
kenjiArai	4:e9dfb4ca4277	2843	/**
kenjiArai	4:e9dfb4ca4277	2844	\ingroup CMSIS_Core_FunctionInterface
kenjiArai	4:e9dfb4ca4277	2845	\defgroup CMSIS_core_DebugFunctions ITM Functions
kenjiArai	4:e9dfb4ca4277	2846	\brief Functions that access the ITM debug interface.
kenjiArai	4:e9dfb4ca4277	2847	@{
kenjiArai	4:e9dfb4ca4277	2848	*/
kenjiArai	4:e9dfb4ca4277	2849
kenjiArai	4:e9dfb4ca4277	2850	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
kenjiArai	4:e9dfb4ca4277	2851	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
kenjiArai	4:e9dfb4ca4277	2852
kenjiArai	4:e9dfb4ca4277	2853
kenjiArai	4:e9dfb4ca4277	2854	/**
kenjiArai	4:e9dfb4ca4277	2855	\brief ITM Send Character
kenjiArai	4:e9dfb4ca4277	2856	\details Transmits a character via the ITM channel 0, and
kenjiArai	4:e9dfb4ca4277	2857	\li Just returns when no debugger is connected that has booked the output.
kenjiArai	4:e9dfb4ca4277	2858	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
kenjiArai	4:e9dfb4ca4277	2859	\param [in] ch Character to transmit.
kenjiArai	4:e9dfb4ca4277	2860	\returns Character to transmit.
kenjiArai	4:e9dfb4ca4277	2861	*/
kenjiArai	4:e9dfb4ca4277	2862	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
kenjiArai	4:e9dfb4ca4277	2863	{
kenjiArai	4:e9dfb4ca4277	2864	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
kenjiArai	4:e9dfb4ca4277	2865	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
kenjiArai	4:e9dfb4ca4277	2866	{
kenjiArai	4:e9dfb4ca4277	2867	while (ITM->PORT[0U].u32 == 0UL)
kenjiArai	4:e9dfb4ca4277	2868	{
kenjiArai	4:e9dfb4ca4277	2869	__NOP();
kenjiArai	4:e9dfb4ca4277	2870	}
kenjiArai	4:e9dfb4ca4277	2871	ITM->PORT[0U].u8 = (uint8_t)ch;
kenjiArai	4:e9dfb4ca4277	2872	}
kenjiArai	4:e9dfb4ca4277	2873	return (ch);
kenjiArai	4:e9dfb4ca4277	2874	}
kenjiArai	4:e9dfb4ca4277	2875
kenjiArai	4:e9dfb4ca4277	2876
kenjiArai	4:e9dfb4ca4277	2877	/**
kenjiArai	4:e9dfb4ca4277	2878	\brief ITM Receive Character
kenjiArai	4:e9dfb4ca4277	2879	\details Inputs a character via the external variable \ref ITM_RxBuffer.
kenjiArai	4:e9dfb4ca4277	2880	\return Received character.
kenjiArai	4:e9dfb4ca4277	2881	\return -1 No character pending.
kenjiArai	4:e9dfb4ca4277	2882	*/
kenjiArai	4:e9dfb4ca4277	2883	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
kenjiArai	4:e9dfb4ca4277	2884	{
kenjiArai	4:e9dfb4ca4277	2885	int32_t ch = -1; /* no character available */
kenjiArai	4:e9dfb4ca4277	2886
kenjiArai	4:e9dfb4ca4277	2887	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
kenjiArai	4:e9dfb4ca4277	2888	{
kenjiArai	4:e9dfb4ca4277	2889	ch = ITM_RxBuffer;
kenjiArai	4:e9dfb4ca4277	2890	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
kenjiArai	4:e9dfb4ca4277	2891	}
kenjiArai	4:e9dfb4ca4277	2892
kenjiArai	4:e9dfb4ca4277	2893	return (ch);
kenjiArai	4:e9dfb4ca4277	2894	}
kenjiArai	4:e9dfb4ca4277	2895
kenjiArai	4:e9dfb4ca4277	2896
kenjiArai	4:e9dfb4ca4277	2897	/**
kenjiArai	4:e9dfb4ca4277	2898	\brief ITM Check Character
kenjiArai	4:e9dfb4ca4277	2899	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
kenjiArai	4:e9dfb4ca4277	2900	\return 0 No character available.
kenjiArai	4:e9dfb4ca4277	2901	\return 1 Character available.
kenjiArai	4:e9dfb4ca4277	2902	*/
kenjiArai	4:e9dfb4ca4277	2903	__STATIC_INLINE int32_t ITM_CheckChar (void)
kenjiArai	4:e9dfb4ca4277	2904	{
kenjiArai	4:e9dfb4ca4277	2905
kenjiArai	4:e9dfb4ca4277	2906	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
kenjiArai	4:e9dfb4ca4277	2907	{
kenjiArai	4:e9dfb4ca4277	2908	return (0); /* no character available */
kenjiArai	4:e9dfb4ca4277	2909	}
kenjiArai	4:e9dfb4ca4277	2910	else
kenjiArai	4:e9dfb4ca4277	2911	{
kenjiArai	4:e9dfb4ca4277	2912	return (1); /* character available */
kenjiArai	4:e9dfb4ca4277	2913	}
kenjiArai	4:e9dfb4ca4277	2914	}
kenjiArai	4:e9dfb4ca4277	2915
kenjiArai	4:e9dfb4ca4277	2916	/@} end of CMSIS_core_DebugFunctions /
kenjiArai	4:e9dfb4ca4277	2917
kenjiArai	4:e9dfb4ca4277	2918
kenjiArai	4:e9dfb4ca4277	2919
kenjiArai	4:e9dfb4ca4277	2920
kenjiArai	4:e9dfb4ca4277	2921	#ifdef __cplusplus
kenjiArai	4:e9dfb4ca4277	2922	}
kenjiArai	4:e9dfb4ca4277	2923	#endif
kenjiArai	4:e9dfb4ca4277	2924
kenjiArai	4:e9dfb4ca4277	2925	#endif /* __CORE_ARMV8MML_H_DEPENDANT */
kenjiArai	4:e9dfb4ca4277	2926
kenjiArai	4:e9dfb4ca4277	2927	#endif /* __CMSIS_GENERIC */

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Type:	Program
Created:	12 Feb 2019
Imports:	15
Forks:	0
Commits:	7
Dependents:	0
Dependencies:	3
Followers:	1

The code in this repository is Apache licensed.

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TYBLE16_os5_BASE/cmsis/TARGET_CORTEX_M/core_armv8mml.h@4:e9dfb4ca4277, 2018-12-08 (annotated)

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