frq_cuntr_full.cpp

00001 /*
00002  * mbed Library / Frequency Counter with GPS 1PPS Compensation
00003  *      Frequency Counter Hardware relataed program
00004  *      Only for ST Nucleo F411RE
00005  *
00006  * Copyright (c) 2014 Kenji Arai / JH1PJL
00007  *  http://www.page.sannet.ne.jp/kenjia/index.html
00008  *  http://mbed.org/users/kenjiArai/
00009  *      Additional functions and modification
00010  *      started: October   18th, 2014
00011  *      Revised: January    1st, 2015
00012  *
00013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
00014  * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
00015  * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
00016  * DAMAGES OR OTHER  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
00017  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
00018  */
00019 
00020 #if defined(TARGET_NUCLEO_F411RE)
00021 
00022 #include "frq_cuntr_full.h"
00023 
00024 #ifdef DEBUG
00025 Serial pcm(USBTX, USBRX);
00026 DigitalOut debug_led(LED1);
00027 #endif
00028 
00029 #ifdef DEBUG
00030 #define BAUD(x)         pcm.baud(x)
00031 #define PRINTF(...)     pcm.printf(__VA_ARGS__)
00032 #else
00033 #define BAUD(x)         {;}
00034 #define PRINTF(...)     {;}
00035 #endif
00036 
00037 namespace Frequency_counter
00038 {
00039 // TIM2 OC
00040 static uint32_t oc_set_time0;
00041 static uint32_t oc_set_time1;
00042 static uint8_t  new_gt_value;
00043 static uint32_t oc_hi_time;
00044 static uint32_t oc_lo_time;
00045 // TIM2 IC
00046 static uint8_t  tim2_ready_flg;
00047 static uint32_t tim2_cnt_data;
00048 static uint32_t tim2_old_cnt_data;
00049 // TIM3+4 IC
00050 static uint8_t  tim3p4_ready_flg;
00051 static uint32_t tim3p4_cnt_data;
00052 
00053 //-------------------------------------------------------------------------------------------------
00054 //  Interrupt Handlers
00055 //-------------------------------------------------------------------------------------------------
00056 // TIM2 IC2 Interrupt control
00057 void irq_ic2_TIM2(void)
00058 {
00059     uint16_t reg;
00060     reg = TIM2->SR;
00061     if (reg & TIM_SR_CC2IF) {
00062         TIM2->SR &= ~TIM_SR_CC2IF;      // clear IC flag
00063         tim2_old_cnt_data = tim2_cnt_data;
00064         tim2_cnt_data = TIM2->CCR2;
00065         tim2_ready_flg = 1;
00066 #if defined(DEBUG)
00067         debug_led = !debug_led;
00068 #endif // defined(DEBUG)
00069     } else if (reg & TIM_SR_CC3IF) {    // Output Compare
00070         TIM2->SR &= ~TIM_SR_CC3IF;      // clear IC flag
00071         if (GPIOB->IDR & 0x0400) {      // Check PB10 status
00072             TIM2->CCR3 = TIM2->CCR3 + oc_hi_time;
00073         } else {
00074             TIM2->CCR3 = TIM2->CCR3 + oc_lo_time;
00075             if (new_gt_value) {
00076                 new_gt_value = 0;
00077                 oc_hi_time = oc_set_time0;
00078                 oc_lo_time = oc_set_time1;
00079             }
00080         }
00081 #if defined(DEBUG)
00082         debug_led = !debug_led;
00083 #endif // defined(DEBUG)
00084     }
00085 }
00086 
00087 // TIM3 IC2 Interrupt control (same signal connected to TIM4 IC1)
00088 void irq_ic2_TIM3P4(void)
00089 {
00090     TIM3->SR &= ~TIM_SR_CC2IF;      // clear IC flag
00091     TIM4->SR &= ~TIM_SR_CC1IF;
00092     tim3p4_cnt_data = (TIM4->CCR1 << 16) + TIM3->CCR2;
00093     tim3p4_ready_flg = 1;
00094 #if defined(DEBUG)
00095     debug_led = !debug_led;
00096 #endif // defined(DEBUG)
00097 }
00098 
00099 //---------------------------------------------------------------------------------------
00100 //  Frequency Counter
00101 //---------------------------------------------------------------------------------------
00102 FRQ_CUNTR::FRQ_CUNTR(PinName f_in, double gt, double ex_clock): _pin(f_in)
00103 {
00104     // Don't change calling sequence!!
00105     set_external_clock(ex_clock);   // 1st
00106     set_gate_time(gt);              // 2nd
00107     initialize_Freq_counter();      // 3rd
00108 }
00109 
00110 // Set gate time
00111 double FRQ_CUNTR::set_gate_time(double gt)
00112 {
00113     if (gt < 0.05) {
00114         gate_time = 0.05;
00115     } else if (gt > 60.0) {
00116         gate_time = 60.0;
00117     } else {
00118         gate_time = gt;
00119     }
00120     oc_set_time0 = clk_hi_const;
00121     double gt_tmp0 = ex_clk_base * gate_time;
00122     uint32_t gt_tmp1 = (uint32_t)gt_tmp0;
00123     if ((gt_tmp0 - (double)gt_tmp1) >= 0.5) {
00124         ++gt_tmp1;
00125     }
00126     oc_set_time1 = gt_tmp1 - clk_hi_const;
00127     new_gt_value = 1;
00128     return gate_time;
00129 }
00130 
00131 // Read gate time
00132 double FRQ_CUNTR::read_gate_time(void)
00133 {
00134     return gate_time;
00135 }
00136 
00137 // Set External Clock Frequency
00138 void FRQ_CUNTR::set_external_clock(double ex_clock)
00139 {
00140 #if defined(BASE_EXTERNAL_CLOCK)
00141     ex_clock_freq = ex_clock;
00142     ex_clk_base = (uint32_t)(ex_clock_freq * 1000000); // MHz->Hz
00143     clk_hi_const = (uint32_t)(ex_clock_freq * 1000000 * 0.04);  // 40mS
00144     uint32_t err = (uint32_t)(ex_clock_freq * 1000000 * 0.00001);  // 10ppm error range
00145     clk_upper_limit = ex_clk_base + err;
00146     clk_lower_limit = ex_clk_base - err;
00147     PRINTF("EXTERNAL Clock mode\r\n");
00148 #else // defined(BASE_EXTERNAL_CLOCK)
00149     ex_clock_freq = 100;     // Internal 100MHz
00150     ex_clk_base = 100000000; // MHz->Hz
00151     clk_hi_const = 4000000;  // 40mS
00152     uint32_t err = 10000;    // error range
00153     clk_upper_limit = ex_clk_base + err;
00154     clk_lower_limit = ex_clk_base - err;
00155     PRINTF("INTERNAL Clock mode\r\n");
00156 #endif // defined(BASE_EXTERNAL_CLOCK)
00157 }
00158 
00159 // Read new frequency data
00160 double FRQ_CUNTR::read_freq_data(void)
00161 {
00162     old_cntr_tim3p4 = counter_tim3p4;
00163     counter_tim3p4 = read_ic2_counter_TIM3P4();
00164     double freq0 = (double)(counter_tim3p4 - old_cntr_tim3p4);
00165     newest_frequency = freq0 / gate_time;
00166     return newest_frequency;
00167 }
00168 
00169 // Read status (new frequency data is available or not)
00170 uint32_t FRQ_CUNTR::status_freq_update(void)
00171 {
00172     return check_ic2_status_TIM3P4();
00173 }
00174 
00175 // Read status (new 1PPS data is available or not)
00176 uint32_t FRQ_CUNTR::status_1pps(void)
00177 {
00178     return check_ic2_status_TIM2();
00179 }
00180 
00181 // Read GPS 1PPS counter value
00182 uint32_t FRQ_CUNTR::set_1PPS_data(void)
00183 {
00184     uint32_t diff = tim2_cnt_data - tim2_old_cnt_data;
00185     if ((diff > clk_upper_limit) || (diff < clk_lower_limit)) {
00186         PRINTF("IC0 %d %d %d \r\n", diff, clk_upper_limit, clk_lower_limit);
00187         gps_ready = 0;
00188         return 0;
00189     } else {
00190         gps_ready = 1;
00191         onepps_cnt[onepps_num] = diff;
00192         if (++onepps_num >= CNT_BF_SIZE) {
00193             onepps_num = 0;
00194             onepps_buf_full = 1;
00195         }
00196         onepps_newest = diff;
00197         return diff;
00198     }
00199 }
00200 
00201 // Avarage measued data GPS 1PPS by 25MHz External Clock
00202 uint32_t FRQ_CUNTR::read_avarage_1pps(void)
00203 {
00204     uint64_t total = 0;
00205     if (onepps_buf_full == 1) {
00206         for (uint32_t i = 0; i < CNT_BF_SIZE; i++) {
00207             total += (uint64_t)onepps_cnt[i];
00208         }
00209         onepps_cnt_avarage = total / CNT_BF_SIZE;
00210         PRINTF("buf");
00211     } else {
00212         for (uint32_t i = 0; i < onepps_num; i++) {
00213             total += (uint64_t)onepps_cnt[i];
00214         }
00215         onepps_cnt_avarage = total / onepps_num;
00216         PRINTF("not");
00217     }
00218     PRINTF(" full, num= %3d , 1PPS/new= %9d\r\n", onepps_num, onepps_newest);
00219     return onepps_cnt_avarage;
00220 }
00221 
00222 // Newest measued data GPS 1PPS
00223 uint32_t FRQ_CUNTR::read_newest_1pps(void)
00224 {
00225     return onepps_newest;
00226 }
00227 
00228 // Check GPS condition
00229 uint8_t FRQ_CUNTR::status_gps(void)
00230 {
00231     return gps_ready;
00232 }
00233 
00234 //---------------------------------------------------------------------------------------
00235 //  TIM2 (32bit Counter + IC + OC)
00236 //---------------------------------------------------------------------------------------
00237 // Read TIM2 captured counter value
00238 uint32_t FRQ_CUNTR::read_ic2_counter_TIM2(void)
00239 {
00240     return tim2_cnt_data;   // return TIM2->CCR2;
00241 }
00242 
00243 // Check TIM2 IC2 status
00244 uint32_t FRQ_CUNTR::check_ic2_status_TIM2(void)
00245 {
00246     if (tim2_ready_flg == 0) {
00247         return 0;
00248     } else {
00249         tim2_ready_flg = 0;
00250         set_1PPS_data();
00251         return 1;
00252     }
00253 }
00254 
00255 // Check OC port status
00256 uint8_t FRQ_CUNTR::read_oc_port_status(void)
00257 {
00258     uint32_t p = GPIOB->IDR;
00259     if (p & 0x0400) {   // Check PB10 status
00260         return 1;
00261     } else {
00262         return 0;
00263     }
00264 }
00265 
00266 //---------------------------------------------------------------------------------------
00267 //  TIM3+TIM4 (32bit Counter + IC)
00268 //---------------------------------------------------------------------------------------
00269 // Read TIM3+4(as 32bit) captured counter value
00270 uint32_t FRQ_CUNTR::read_ic2_counter_TIM3P4(void)
00271 {
00272     return tim3p4_cnt_data;
00273 }
00274 
00275 // Check TIM3 IC2 & TIM4 IC1 status
00276 uint32_t FRQ_CUNTR::check_ic2_status_TIM3P4(void)
00277 {
00278     if (tim3p4_ready_flg == 0) {
00279         return 0;
00280     } else {
00281         tim3p4_ready_flg = 0;
00282         return 1;
00283     }
00284 }
00285 
00286 //---------------------------------------------------------------------------------------
00287 //  Frequency check for test purpose
00288 //---------------------------------------------------------------------------------------
00289 // Read TIM2 Clock frequency
00290 uint32_t FRQ_CUNTR::read_frequency_TIM2(float gate_time)
00291 {
00292     uint32_t freq = 0;
00293     TIM2->CNT = 0;
00294     wait(gate_time);                // Gate time for count
00295     freq = TIM2->CNT;               // read counter
00296     PRINTF("Clock freq.=%10d [Hz], gate= %4.2f [Sec]\r\n", freq, gate_time);
00297     return freq;                    // return counter data
00298 }
00299 
00300 // Read TIM3(+TIM4) Input frequency
00301 uint32_t FRQ_CUNTR::read_frequency_TIM3P4(float gate_time)
00302 {
00303     uint32_t freq0 = 0;
00304     uint32_t freq1 = 0;
00305     TIM3->CNT = 0;
00306     TIM4->CNT = 0;
00307     TIM3->CNT = 0;
00308     wait(gate_time);                // Gate time for count
00309     freq0 = TIM3->CNT;
00310     freq1 = TIM4->CNT;
00311     freq0 = (freq1 << 16) + freq0;
00312     PRINTF("Input freq.=%10d [Hz], gate= %4.2f [Sec]\r\n", freq0, gate_time);
00313     return freq0;                   // read counter
00314 }
00315 
00316 //---------------------------------------------------------------------------------------
00317 //  Clock output for test purpose
00318 //---------------------------------------------------------------------------------------
00319 // Output internal clock
00320 void FRQ_CUNTR::port_mco1_mco2_set(uint8_t select)
00321 {
00322     // PA8 -> MCO_1
00323     GPIOA->AFR[1] &= 0xfffffff0;
00324     GPIOA->AFR[1] |= GPIO_AF0_MCO << 0;
00325     GPIOA->MODER &= ~(GPIO_MODER_MODER8);   // AF
00326     GPIOA->MODER |= GPIO_MODER_MODER8_1;
00327     GPIOA->OTYPER &= ~(GPIO_OTYPER_OT_8);   // Output Push-Pull=0
00328     GPIOA->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR8;// Speed full=11
00329     GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPDR8);   // Pull-up=01
00330     GPIOA->PUPDR |= GPIO_PUPDR_PUPDR8_0;
00331     // PC9 -> MCO_2
00332     GPIOC->AFR[1] &= 0xffffff0f;
00333     GPIOC->AFR[1] |= GPIO_AF0_MCO << 4;
00334     GPIOC->MODER &= ~(GPIO_MODER_MODER9);   // AF
00335     GPIOC->MODER |= GPIO_MODER_MODER9_1;
00336     GPIOC->OTYPER &= ~(GPIO_OTYPER_OT_9);   // Output Push-Pull=0
00337     GPIOC->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR9;// Speed full=11
00338     GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPDR9);   // Pull-up=01
00339     GPIOC->PUPDR |= GPIO_PUPDR_PUPDR9_0;
00340     // Select output clock source
00341     RCC->CFGR &= 0x009fffff;
00342     if (select == 1) {
00343         // MC01 output HSE 1/1, MCO2 output SYSCLK 1/1
00344         //             MCO2          MCO2PRE       MCO1PRE       MCO1
00345         RCC->CFGR |= (0x0 << 30) + (0x0 << 27) + (0x0 << 24) + (0x2 << 21);
00346         PRINTF("Set MCO1(PA8):HSE/1, MCO2(PC9):SYSCLK/1\r\n");
00347     } else if (select == 2) {
00348         // MC01 output HSE 1/2, MCO2 output SYSCLK 1/2
00349         //             MCO2          MCO2PRE       MCO1PRE       MCO1
00350         RCC->CFGR |= (0x0 << 30) + (0x4 << 27) + (0x4 << 24) + (0x2 << 21);
00351         PRINTF("Set MCO1(PA8):HSE/2, MCO2(PC9):SYSCLK/2\r\n");
00352     } else { // select = 4 and other wrong order
00353         // MC01 output HSE 1/4, MCO2 output SYSCLK 1/4
00354         //             MCO2          MCO2PRE       MCO1PRE       MCO1
00355         RCC->CFGR |= (0x0 << 30) + (0x6 << 27) + (0x6 << 24) + (0x2 << 21);
00356         PRINTF("Set MCO1(PA8):HSE/4, MCO2(PC9):SYSCLK/4\r\n");
00357     }
00358 }
00359 
00360 //---------------------------------------------------------------------------------------
00361 //  Initialize TIM2 and TIM3+4
00362 //---------------------------------------------------------------------------------------
00363 void FRQ_CUNTR::initialize_Freq_counter(void)
00364 {
00365     initialize_TIM2();
00366     initialize_TIM3P4();
00367 }
00368 
00369 // Initialize TIM2
00370 // Internal clock (100MHz) or External clock(?MHz) and IC2 for GPS 1pps signal measurement
00371 void FRQ_CUNTR::initialize_TIM2(void)
00372 {
00373 #if defined(BASE_EXTERNAL_CLOCK)
00374     // PA0 -> Counter frequency input pin as Timer2 CH1/ETR
00375     RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOAEN);
00376     GPIOA->AFR[0] &= 0xfffffff0;
00377     GPIOA->AFR[0] |= GPIO_AF1_TIM2;
00378     GPIOA->MODER &= ~(GPIO_MODER_MODER0);   // AF
00379     GPIOA->MODER |= GPIO_MODER_MODER0_1;
00380     GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPDR0);   // PU
00381     GPIOA->PUPDR |= GPIO_PUPDR_PUPDR0_0;
00382     // Initialize Timer2(32bit) for an external up counter mode
00383     RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
00384     TIM2->CR1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD));// count_up + div by 1
00385     TIM2->CR1 |= TIM_CR1_URS;
00386     TIM2->ARR = 0xffffffff;
00387     TIM2->PSC = 0x0000;
00388     TIM2->CCER &= (uint16_t)~TIM_CCER_CC1E;      // Disable the CC1
00389     TIM2->CCMR1 &= (uint16_t)~(TIM_CCMR1_IC1F | TIM_CCMR1_CC1S);    // input filter + input select
00390     TIM2->CCMR1 |= (uint16_t)TIM_CCMR1_CC1S_0;
00391     TIM2->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NE | TIM_CCER_CC1NP); // positive edge
00392     TIM2->SMCR  = (uint16_t)(TIM_SMCR_ECE| TIM_SMCR_ETPS_0 | TIM_SMCR_TS);  // clock/2 !!
00393     TIM2->CR1 |= (uint16_t)TIM_CR1_CEN;          // Enable the TIM Counter
00394 #else // defined(BASE_EXTERNAL_CLOCK)
00395     // Initialize Timer2(32bit) for an internal up counter mode
00396     RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
00397     TIM2->CR1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD));  // count_up + div by 1
00398     TIM2->CR1 |= TIM_CR1_URS;
00399     TIM2->ARR = 0xffffffff;
00400     TIM2->PSC = 0x0000;
00401     TIM2->CCER &= (uint16_t)~TIM_CCER_CC1E;      // Disable the CC1
00402     TIM2->SMCR &= (uint16_t)~(TIM_SMCR_ECE | TIM_SMCR_TS | TIM_SMCR_SMS);
00403     TIM2->SMCR |= (uint16_t)0;     // Internal clock = 100MHz
00404     TIM2->CR1 |= (uint16_t)TIM_CR1_CEN;          // Enable the TIM Counter
00405 #endif // defined(BASE_EXTERNAL_CLOCK)
00406     // PA1 -> Input Capture pin as Timer2 IC2
00407     GPIOA->AFR[0] &= 0xffffff0f;
00408     GPIOA->AFR[0] |= GPIO_AF1_TIM2 << 4;
00409     GPIOA->MODER &= ~(GPIO_MODER_MODER1);  // AF
00410     GPIOA->MODER |= GPIO_MODER_MODER1_1;
00411     GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPDR1);
00412     GPIOA->PUPDR |= GPIO_PUPDR_PUPDR1_0;   // PU
00413     // Initialize Timer2 I.C.2
00414     TIM2->CCER  &= (uint16_t)~TIM_CCER_CC2E;    // Disable the CC2
00415     TIM2->CCMR1 &= (uint16_t)~(TIM_CCMR1_IC2F | TIM_CCMR1_CC2S);// input filter + input select
00416     TIM2->CCMR1 |= (uint16_t)TIM_CCMR1_CC2S_0;
00417     TIM2->CCER  &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); // positive edge
00418     TIM2->CCER  |= (uint16_t)TIM_CCER_CC2E;     // enable capture
00419     // PB10 -> Output Compare pin as Timer2 CH3/OC3
00420     GPIOB->AFR[1] &= 0xfffff0ff;
00421     GPIOB->AFR[1] |= GPIO_AF1_TIM2 << 8;
00422     GPIOB->MODER &= ~(GPIO_MODER_MODER10);  // AF
00423     GPIOB->MODER |= GPIO_MODER_MODER10_1;
00424     GPIOB->OTYPER &= ~(GPIO_OTYPER_OT_10);// Output Push-Pull=0
00425     GPIOB->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR10;// Speed full=11
00426     GPIOB->PUPDR &= ~(GPIO_PUPDR_PUPDR10);   // Pull-up=01
00427     GPIOB->PUPDR |= GPIO_PUPDR_PUPDR10_0;
00428     // Initialize Timer2 O.C.3
00429     TIM2->CCER &= (uint16_t)~TIM_CCER_CC3E; // Reset the CC3E Bit
00430     TIM2->CCMR2 &= (uint16_t)~(TIM_CCMR2_OC3M | TIM_CCMR2_CC3S |
00431                                TIM_CCMR2_OC3PE | TIM_CCMR2_OC3CE | TIM_CCMR2_OC3FE);
00432     TIM2->CCMR2 |= (TIM_CCMR2_OC3M_0 | TIM_CCMR2_OC3M_1);
00433     TIM2->CCER &= (uint16_t)~TIM_CCER_CC3P;// Reset the Output Polarity level
00434     TIM2->CCER |= (uint16_t)TIM_CCER_CC3E; // Set the CC3E Bit
00435     new_gt_value = 0;
00436     oc_hi_time = oc_set_time0;
00437     oc_lo_time = oc_set_time1;
00438     TIM2->CCR3 = TIM2->CNT + oc_hi_time;// Set the Capture Compare Register value
00439     // Only for Debug purpose
00440     BAUD(9600);
00441     //  PA
00442     PRINTF("\r\n// Timer2(32bit) for an internal up counter mode\r\n");
00443     PRINTF("// PA1  -> Input Capture pin as Timer2 CH2/TI2\r\n");
00444     PRINTF("GPIOA->AFR[0]0x%08x:0x%08x\r\n",&GPIOA->AFR[0], GPIOA->AFR[0]);
00445     PRINTF("GPIOA->AFR[1]0x%08x:0x%08x\r\n",&GPIOA->AFR[1], GPIOA->AFR[1]);
00446     PRINTF("GPIOA->MODER 0x%08x:0x%08x\r\n",&GPIOA->MODER, GPIOA->MODER);
00447     PRINTF("GPIOA->PUPDR 0x%08x:0x%08x\r\n",&GPIOA->PUPDR, GPIOA->PUPDR);
00448     //  PB
00449     PRINTF("// PB10 -> Output Compare pin as Timer2 CH3/TI3\r\n");
00450     PRINTF("GPIOB->AFR[0]0x%08x:0x%08x\r\n",&GPIOB->AFR[0], GPIOB->AFR[0]);
00451     PRINTF("GPIOB->AFR[1]0x%08x:0x%08x\r\n",&GPIOB->AFR[1], GPIOB->AFR[1]);
00452     PRINTF("GPIOB->MODER 0x%08x:0x%08x\r\n",&GPIOB->MODER, GPIOB->MODER);
00453     PRINTF("GPIOB->PUPDR 0x%08x:0x%08x\r\n",&GPIOB->PUPDR, GPIOB->PUPDR);
00454     //  TIM2
00455     PRINTF("// PA1 -> Timer2 IC2\r\n");
00456     PRINTF("// PB10-> Timer2 OC3\r\n");
00457     PRINTF("TIM2->CR1    0x%08x:0x%08x\r\n",&TIM2->CR1, TIM2->CR1);
00458     PRINTF("TIM2->ARR    0x%08x:0x%08x\r\n",&TIM2->ARR, TIM2->ARR);
00459     PRINTF("TIM2->PSC    0x%08x:0x%08x\r\n",&TIM2->PSC, TIM2->PSC);
00460     PRINTF("TIM2->CCMR1  0x%08x:0x%08x\r\n",&TIM2->CCMR1, TIM2->CCMR1);
00461     PRINTF("TIM2->CCMR2  0x%08x:0x%08x\r\n",&TIM2->CCMR2, TIM2->CCMR2);
00462     PRINTF("TIM2->CCER   0x%08x:0x%08x\r\n",&TIM2->CCER, TIM2->CCER);
00463     PRINTF("TIM2->SMCR   0x%08x:0x%08x\r\n",&TIM2->SMCR, TIM2->SMCR);
00464     PRINTF("TIM2->CCR3   0x%08x:0x%08x\r\n\r\n",&TIM2->CCR3, TIM2->CCR3);
00465     // Interrupt Timer2 IC2
00466     for (uint32_t i = 0; i < CNT_BF_SIZE; i++) {
00467         onepps_cnt[i] = 0;
00468     }
00469     onepps_num = 0;
00470     onepps_ready_flg = 0;
00471     onepps_buf_full = 0;
00472     onepps_cnt_avarage = 0;
00473     tim2_ready_flg = 0;
00474     tim2_cnt_data = 0;
00475     tim2_old_cnt_data = 0;
00476     TIM2->SR &= ~(TIM_SR_CC2IF + TIM_SR_CC3IF); // clear IC flag
00477     TIM2->DIER |= TIM_DIER_CC2IE + TIM_DIER_CC3IE;
00478     NVIC_SetVector(TIM2_IRQn, (uint32_t)irq_ic2_TIM2);
00479     NVIC_ClearPendingIRQ(TIM2_IRQn);
00480     NVIC_EnableIRQ(TIM2_IRQn);
00481 }
00482 
00483 // Initialize TIM3 and TIM4 as 32bit counter (TIM3(16bit) + TIM4(16bit))
00484 //      TIM3 clock input is unkown freq.(measuring freq.) and TIM4 is slave counter
00485 //      1sec gate signal connected both TIM3 IC2 and TIM4 IC1
00486 void FRQ_CUNTR::initialize_TIM3P4(void)
00487 {
00488     // PC6 -> Unkown frequency input pin as Timer3 CH1/TI1
00489     RCC->AHB1ENR  |= (RCC_AHB1ENR_GPIOCEN);
00490     GPIOC->AFR[0] &= 0xf0ffffff;
00491     GPIOC->AFR[0] |= GPIO_AF2_TIM3 << 24;
00492     GPIOC->MODER  &= ~(GPIO_MODER_MODER6);   // AF
00493     GPIOC->MODER  |= GPIO_MODER_MODER6_1;
00494     GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPDR6);
00495     GPIOC->PUPDR |= GPIO_PUPDR_PUPDR6_0;   // PU
00496     // Initialize Timer3(16bit) for an external up counter mode
00497     RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
00498     TIM3->CR1   &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD));// count_up + div by 1
00499     TIM3->CR1   |= (uint16_t)TIM_CR1_URS;
00500     TIM3->ARR    = 0xffff;
00501     TIM3->CCER  &= (uint16_t)~TIM_CCER_CC1E;    // Disable the CC1
00502     TIM3->CCMR1 &= (uint16_t)~(TIM_CCMR1_IC1F | TIM_CCMR1_CC1S);    // input filter + input select
00503     TIM3->CCMR1 |= (uint16_t)TIM_CCMR1_CC1S_0;
00504     TIM3->CCER  &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NE | TIM_CCER_CC1NP);// positive edge
00505     TIM3->SMCR  &= (uint16_t)~(TIM_SMCR_ECE | TIM_SMCR_TS | TIM_SMCR_SMS);// external mode 1
00506     TIM3->SMCR  |= (uint16_t)( TIM_TS_TI1FP1 | TIM_SLAVEMODE_EXTERNAL1);  // ECE must be ZERO!!!!
00507     TIM3->CR2   &= (uint16_t)~(TIM_CR2_TI1S | TIM_CR2_MMS);
00508     TIM3->CR2   |= (uint16_t)TIM_CR2_MMS_1;       // TRGO update
00509     TIM3->CR1   |= (uint16_t)TIM_CR1_CEN;         // Enable the TIM Counter
00510     // Initialize Timer4(16bit) for an slave up counter of TIM3
00511     RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;
00512     TIM4->CR1  &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD));// count_up + div by 1
00513     TIM4->CR1  |= (uint16_t)TIM_CR1_URS;
00514     TIM4->ARR   = 0xffff;
00515     TIM4->CCER &= (uint16_t)TIM_CCER_CC1E; // Capture enable
00516     TIM4->SMCR &= (uint16_t)~(TIM_SMCR_ECE | TIM_SMCR_TS | TIM_SMCR_SMS);// external mode 1
00517     TIM4->SMCR |= (uint16_t)( TIM_TS_ITR2 | TIM_SLAVEMODE_EXTERNAL1);// ECE must be ZERO!!!!
00518     TIM4->CR2  &= (uint16_t)~(TIM_CR2_TI1S | TIM_CR2_MMS);
00519     TIM4->CR1  |= (uint16_t)TIM_CR1_CEN;         // Enable the TIM Counter
00520     // PC7 -> Input Capture pin as Timer3 IC2
00521     GPIOC->AFR[0] &= 0x0fffffff;
00522     GPIOC->AFR[0] |= GPIO_AF2_TIM3 << 28;
00523     GPIOC->MODER  &= ~(GPIO_MODER_MODER7);  // AF
00524     GPIOC->MODER  |= GPIO_MODER_MODER7_1;
00525     GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPDR7);
00526     GPIOC->PUPDR |= GPIO_PUPDR_PUPDR7_0;   // PU
00527     // Initialize Timer3 IC2
00528     TIM3->CCER  &= (uint16_t)~TIM_CCER_CC2E;    // Disable the CC2
00529     TIM3->CCMR1 &= (uint16_t)~(TIM_CCMR1_IC2F | TIM_CCMR1_CC2S);// input filter + input select
00530     TIM3->CCMR1 |= (uint16_t)TIM_CCMR1_CC2S_0;
00531     TIM3->CCER  &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); // positive edge
00532     TIM3->CCER  |= (uint16_t)TIM_CCER_CC2E;     // enable capture
00533     // PB6 -> Input Capture pin as Timer4 IC1
00534     GPIOB->AFR[0] &= 0xf0ffffff;
00535     GPIOB->AFR[0] |= GPIO_AF2_TIM4 << 24;
00536     GPIOB->MODER  &= ~(GPIO_MODER_MODER6);  // AF
00537     GPIOB->MODER  |= GPIO_MODER_MODER6_1;
00538     GPIOB->PUPDR &= ~(GPIO_PUPDR_PUPDR6);
00539     GPIOB->PUPDR |= GPIO_PUPDR_PUPDR6_0;   // Pull-up=01
00540     // Initialize Timer4 IC1
00541     TIM4->CCER  &= (uint16_t)~TIM_CCER_CC1E;
00542     TIM4->CCMR1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F);
00543     TIM4->CCMR1 |= (uint16_t)TIM_CCMR1_CC1S_0;
00544     TIM4->CCER  &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); // positive edge
00545     TIM4->CCER  |= (uint16_t)TIM_CCER_CC1E;     // enable capture
00546     // Only for Debug purpose
00547     //  PB
00548     PRINTF("// PB6 -> Input Capture pin as Timer4 CH1/TI1\r\n");
00549     PRINTF("GPIOB->AFR[0]0x%08x:0x%08x\r\n",&GPIOB->AFR[0], GPIOB->AFR[0]);
00550     PRINTF("GPIOB->AFR[1]0x%08x:0x%08x\r\n",&GPIOB->AFR[1], GPIOB->AFR[1]);
00551     PRINTF("GPIOB->MODER 0x%08x:0x%08x\r\n",&GPIOB->MODER, GPIOB->MODER);
00552     PRINTF("GPIOB->PUPDR 0x%08x:0x%08x\r\n",&GPIOB->PUPDR, GPIOB->PUPDR);
00553     PRINTF("GPIOB->OTYPER  0x%08x:0x%08x\r\n",&GPIOB->OTYPER, GPIOB->OTYPER);
00554     PRINTF("GPIOB->OSPEEDR 0x%08x:0x%08x\r\n",&GPIOB->OSPEEDR, GPIOB->OSPEEDR);
00555     //  PC
00556     PRINTF("// PC6 -> unkown frequency input pin as Timer3 CH1/TI1\r\n");
00557     PRINTF("// PC7 -> Input Capture pin as Timer3 CH2/TI2\r\n");
00558     PRINTF("GPIOC->AFR[0]0x%08x:0x%08x\r\n",&GPIOC->AFR[0], GPIOC->AFR[0]);
00559     PRINTF("GPIOC->AFR[1]0x%08x:0x%08x\r\n",&GPIOC->AFR[1], GPIOC->AFR[1]);
00560     PRINTF("GPIOC->MODER 0x%08x:0x%08x\r\n",&GPIOC->MODER, GPIOC->MODER);
00561     PRINTF("GPIOC->PUPDR 0x%08x:0x%08x\r\n",&GPIOC->PUPDR, GPIOC->PUPDR);
00562     PRINTF("GPIOC->OTYPER  0x%08x:0x%08x\r\n",&GPIOC->OTYPER, GPIOC->OTYPER);
00563     PRINTF("GPIOC->OSPEEDR 0x%08x:0x%08x\r\n",&GPIOC->OSPEEDR, GPIOC->OSPEEDR);
00564     //  TIM3
00565     PRINTF("// PC6 -> Timer3(16bit) for an external up counter mode\r\n");
00566     PRINTF("// PC7 -> Timer3 IC2\r\n");
00567     PRINTF("TIM3->CR1    0x%08x:0x%08x\r\n",&TIM3->CR1, TIM3->CR1);
00568     PRINTF("TIM3->ARR    0x%08x:0x%08x\r\n",&TIM3->ARR, TIM3->ARR);
00569     PRINTF("TIM3->PSC    0x%08x:0x%08x\r\n",&TIM3->PSC, TIM3->PSC);
00570     PRINTF("TIM3->CCMR1  0x%08x:0x%08x\r\n",&TIM3->CCMR1, TIM3->CCMR1);
00571     PRINTF("TIM3->CCMR2  0x%08x:0x%08x\r\n",&TIM3->CCMR2, TIM3->CCMR2);
00572     PRINTF("TIM3->CCER   0x%08x:0x%08x\r\n",&TIM3->CCER, TIM3->CCER);
00573     PRINTF("TIM3->SMCR   0x%08x:0x%08x\r\n",&TIM3->SMCR, TIM3->SMCR);
00574     //  TIM4
00575     PRINTF("// none-> Timer4(16bit) for an slave counter\r\n");
00576     PRINTF("// PB6 -> Timer4 IC1\r\n");
00577     PRINTF("TIM4->CR1    0x%08x:0x%08x\r\n",&TIM4->CR1, TIM4->CR1);
00578     PRINTF("TIM4->ARR    0x%08x:0x%08x\r\n",&TIM4->ARR, TIM4->ARR);
00579     PRINTF("TIM4->PSC    0x%08x:0x%08x\r\n",&TIM4->PSC, TIM4->PSC);
00580     PRINTF("TIM4->CCMR1  0x%08x:0x%08x\r\n",&TIM4->CCMR1, TIM4->CCMR1);
00581     PRINTF("TIM4->CCMR2  0x%08x:0x%08x\r\n",&TIM4->CCMR2, TIM4->CCMR2);
00582     PRINTF("TIM4->CCER   0x%08x:0x%08x\r\n",&TIM4->CCER, TIM4->CCER);
00583     PRINTF("TIM4->SMCR   0x%08x:0x%08x\r\n\r\n",&TIM4->SMCR, TIM4->SMCR);
00584     PRINTF("RCC->APB1ENR 0x%08x:0x%08x\r\n\r\n",&RCC->APB1ENR, RCC->APB1ENR);
00585     // Interrupt Timer3 IC2
00586     tim3p4_ready_flg = 0;
00587     tim3p4_cnt_data = 0;
00588     TIM3->SR &= ~TIM_SR_CC2IF;          // clear IC flag
00589     TIM4->SR &= ~TIM_SR_CC1IF;
00590     TIM3->DIER |= TIM_DIER_CC2IE;
00591     NVIC_SetVector(TIM3_IRQn, (uint32_t)irq_ic2_TIM3P4);
00592     NVIC_ClearPendingIRQ(TIM3_IRQn);
00593     NVIC_EnableIRQ(TIM3_IRQn);
00594 }
00595 
00596 //---------------------------------------------------------------------------------------
00597 //  Only for Debug purpose
00598 //---------------------------------------------------------------------------------------
00599 void FRQ_CUNTR::debug_printf_internal_data(void)
00600 {
00601     PRINTF("Debug information\r\n");
00602     PRINTF("gate_time       %f\r\n", gate_time);
00603     PRINTF("ex_clock_freq   %f\r\n", ex_clock_freq);
00604     PRINTF("ex_clk_base     %9d\r\n", ex_clk_base);
00605     PRINTF("clk_hi_const    %9d\r\n", clk_hi_const);
00606     PRINTF("clk_upper_limit %9d\r\n", clk_upper_limit);
00607     PRINTF("clk_lower_limit %9d\r\n", clk_lower_limit);
00608     PRINTF("\r\n");
00609 }
00610 
00611 }   // Frequency_counter
00612 
00613 #endif      // #if defined(TARGET_NUCLEO_F411RE)