FreeRTOS_on_mbed_v1 - Please see my note book http://mbed.org/users/ken…

Users » kenjiArai » Code » FreeRTOS_on_mbed_v1

Please see my note book http://mbed.org/users/kenjiArai/notebook/freertos-on-mbed-board-with-mbed-cloud-ide--never-/

This is too old.
Below is another FreeRTOS on mbed.
http://developer.mbed.org/users/rgrover1/code/FreeRTOS/
I don't know it works well or not.
I have not evaluated it.

LPC17xx.h@0:d4960fcea8ff, 2011-01-01 (annotated)

Committer:: kenjiArai
Date:: Sat Jan 01 11:17:45 2011 +0000
Revision:: 0:d4960fcea8ff

Who changed what in which revision?

User	Revision	Line number	New contents of line
kenjiArai	0:d4960fcea8ff	1	/******************************************************************************
kenjiArai	0:d4960fcea8ff	2	* @file: LPC17xx.h
kenjiArai	0:d4960fcea8ff	3	* @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
kenjiArai	0:d4960fcea8ff	4	* NXP LPC17xx Device Series
kenjiArai	0:d4960fcea8ff	5	* @version: V1.04
kenjiArai	0:d4960fcea8ff	6	* @date: 2. July 2009
kenjiArai	0:d4960fcea8ff	7	*----------------------------------------------------------------------------
kenjiArai	0:d4960fcea8ff	8	*
kenjiArai	0:d4960fcea8ff	9	* Copyright (C) 2008 ARM Limited. All rights reserved.
kenjiArai	0:d4960fcea8ff	10	*
kenjiArai	0:d4960fcea8ff	11	* ARM Limited (ARM) is supplying this software for use with Cortex-M3
kenjiArai	0:d4960fcea8ff	12	* processor based microcontrollers. This file can be freely distributed
kenjiArai	0:d4960fcea8ff	13	* within development tools that are supporting such ARM based processors.
kenjiArai	0:d4960fcea8ff	14	*
kenjiArai	0:d4960fcea8ff	15	* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
kenjiArai	0:d4960fcea8ff	16	* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
kenjiArai	0:d4960fcea8ff	17	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
kenjiArai	0:d4960fcea8ff	18	* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
kenjiArai	0:d4960fcea8ff	19	* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
kenjiArai	0:d4960fcea8ff	20	*
kenjiArai	0:d4960fcea8ff	21	******************************************************************************/
kenjiArai	0:d4960fcea8ff	22
kenjiArai	0:d4960fcea8ff	23	#ifndef __LPC17xx_H__
kenjiArai	0:d4960fcea8ff	24	#define __LPC17xx_H__
kenjiArai	0:d4960fcea8ff	25	/////////////////////////////////////////////////////////////////////////////
kenjiArai	0:d4960fcea8ff	26	/* System Control Block (SCB) includes:
kenjiArai	0:d4960fcea8ff	27	Flash Accelerator Module, Clocking and Power Control, External Interrupts,
kenjiArai	0:d4960fcea8ff	28	Reset, System Control and Status
kenjiArai	0:d4960fcea8ff	29	*/
kenjiArai	0:d4960fcea8ff	30	/*
kenjiArai	0:d4960fcea8ff	31	* Modified by following information
kenjiArai	0:d4960fcea8ff	32	* http://www.onarm.com/download/download395.asp
kenjiArai	0:d4960fcea8ff	33	*
kenjiArai	0:d4960fcea8ff	34	* By Kenji Arai / JH1PJL on April 11th,2010
kenjiArai	0:d4960fcea8ff	35	* April 11th,2010
kenjiArai	0:d4960fcea8ff	36	*/
kenjiArai	0:d4960fcea8ff	37
kenjiArai	0:d4960fcea8ff	38	#define SCB_BASE_ADDR 0x400FC000
kenjiArai	0:d4960fcea8ff	39	#define PCONP_PCTIM0 0x00000002
kenjiArai	0:d4960fcea8ff	40	#define PCONP_PCTIM1 0x00000004
kenjiArai	0:d4960fcea8ff	41	#define PCONP_PCUART0 0x00000008
kenjiArai	0:d4960fcea8ff	42	#define PCONP_PCUART1 0x00000010
kenjiArai	0:d4960fcea8ff	43	#define PCONP_PCPWM1 0x00000040
kenjiArai	0:d4960fcea8ff	44	#define PCONP_PCI2C0 0x00000080
kenjiArai	0:d4960fcea8ff	45	#define PCONP_PCSPI 0x00000100
kenjiArai	0:d4960fcea8ff	46	#define PCONP_PCRTC 0x00000200
kenjiArai	0:d4960fcea8ff	47	#define PCONP_PCSSP1 0x00000400
kenjiArai	0:d4960fcea8ff	48	#define PCONP_PCAD 0x00001000
kenjiArai	0:d4960fcea8ff	49	#define PCONP_PCCAN1 0x00002000
kenjiArai	0:d4960fcea8ff	50	#define PCONP_PCCAN2 0x00004000
kenjiArai	0:d4960fcea8ff	51	#define PCONP_PCGPIO 0x00008000
kenjiArai	0:d4960fcea8ff	52	#define PCONP_PCRIT 0x00010000
kenjiArai	0:d4960fcea8ff	53	#define PCONP_PCMCPWM 0x00020000
kenjiArai	0:d4960fcea8ff	54	#define PCONP_PCQEI 0x00040000
kenjiArai	0:d4960fcea8ff	55	#define PCONP_PCI2C1 0x00080000
kenjiArai	0:d4960fcea8ff	56	#define PCONP_PCSSP0 0x00200000
kenjiArai	0:d4960fcea8ff	57	#define PCONP_PCTIM2 0x00400000
kenjiArai	0:d4960fcea8ff	58	#define PCONP_PCTIM3 0x00800000
kenjiArai	0:d4960fcea8ff	59	#define PCONP_PCUART2 0x01000000
kenjiArai	0:d4960fcea8ff	60	#define PCONP_PCUART3 0x02000000
kenjiArai	0:d4960fcea8ff	61	#define PCONP_PCI2C2 0x04000000
kenjiArai	0:d4960fcea8ff	62	#define PCONP_PCI2S 0x08000000
kenjiArai	0:d4960fcea8ff	63	#define PCONP_PCGPDMA 0x20000000
kenjiArai	0:d4960fcea8ff	64	#define PCONP_PCENET 0x40000000
kenjiArai	0:d4960fcea8ff	65	#define PCONP_PCUSB 0x80000000
kenjiArai	0:d4960fcea8ff	66
kenjiArai	0:d4960fcea8ff	67	#define PLLCON_PLLE 0x00000001
kenjiArai	0:d4960fcea8ff	68	#define PLLCON_PLLC 0x00000002
kenjiArai	0:d4960fcea8ff	69	#define PLLCON_MASK 0x00000003
kenjiArai	0:d4960fcea8ff	70
kenjiArai	0:d4960fcea8ff	71	#define PLLCFG_MUL1 0x00000000
kenjiArai	0:d4960fcea8ff	72	#define PLLCFG_MUL2 0x00000001
kenjiArai	0:d4960fcea8ff	73	#define PLLCFG_MUL3 0x00000002
kenjiArai	0:d4960fcea8ff	74	#define PLLCFG_MUL4 0x00000003
kenjiArai	0:d4960fcea8ff	75	#define PLLCFG_MUL5 0x00000004
kenjiArai	0:d4960fcea8ff	76	#define PLLCFG_MUL6 0x00000005
kenjiArai	0:d4960fcea8ff	77	#define PLLCFG_MUL7 0x00000006
kenjiArai	0:d4960fcea8ff	78	#define PLLCFG_MUL8 0x00000007
kenjiArai	0:d4960fcea8ff	79	#define PLLCFG_MUL9 0x00000008
kenjiArai	0:d4960fcea8ff	80	#define PLLCFG_MUL10 0x00000009
kenjiArai	0:d4960fcea8ff	81	#define PLLCFG_MUL11 0x0000000A
kenjiArai	0:d4960fcea8ff	82	#define PLLCFG_MUL12 0x0000000B
kenjiArai	0:d4960fcea8ff	83	#define PLLCFG_MUL13 0x0000000C
kenjiArai	0:d4960fcea8ff	84	#define PLLCFG_MUL14 0x0000000D
kenjiArai	0:d4960fcea8ff	85	#define PLLCFG_MUL15 0x0000000E
kenjiArai	0:d4960fcea8ff	86	#define PLLCFG_MUL16 0x0000000F
kenjiArai	0:d4960fcea8ff	87	#define PLLCFG_MUL17 0x00000010
kenjiArai	0:d4960fcea8ff	88	#define PLLCFG_MUL18 0x00000011
kenjiArai	0:d4960fcea8ff	89	#define PLLCFG_MUL19 0x00000012
kenjiArai	0:d4960fcea8ff	90	#define PLLCFG_MUL20 0x00000013
kenjiArai	0:d4960fcea8ff	91	#define PLLCFG_MUL21 0x00000014
kenjiArai	0:d4960fcea8ff	92	#define PLLCFG_MUL22 0x00000015
kenjiArai	0:d4960fcea8ff	93	#define PLLCFG_MUL23 0x00000016
kenjiArai	0:d4960fcea8ff	94	#define PLLCFG_MUL24 0x00000017
kenjiArai	0:d4960fcea8ff	95	#define PLLCFG_MUL25 0x00000018
kenjiArai	0:d4960fcea8ff	96	#define PLLCFG_MUL26 0x00000019
kenjiArai	0:d4960fcea8ff	97	#define PLLCFG_MUL27 0x0000001A
kenjiArai	0:d4960fcea8ff	98	#define PLLCFG_MUL28 0x0000001B
kenjiArai	0:d4960fcea8ff	99	#define PLLCFG_MUL29 0x0000001C
kenjiArai	0:d4960fcea8ff	100	#define PLLCFG_MUL30 0x0000001D
kenjiArai	0:d4960fcea8ff	101	#define PLLCFG_MUL31 0x0000001E
kenjiArai	0:d4960fcea8ff	102	#define PLLCFG_MUL32 0x0000001F
kenjiArai	0:d4960fcea8ff	103	#define PLLCFG_MUL33 0x00000020
kenjiArai	0:d4960fcea8ff	104	#define PLLCFG_MUL34 0x00000021
kenjiArai	0:d4960fcea8ff	105	#define PLLCFG_MUL35 0x00000022
kenjiArai	0:d4960fcea8ff	106	#define PLLCFG_MUL36 0x00000023
kenjiArai	0:d4960fcea8ff	107
kenjiArai	0:d4960fcea8ff	108	#define PLLCFG_DIV1 0x00000000
kenjiArai	0:d4960fcea8ff	109	#define PLLCFG_DIV2 0x00010000
kenjiArai	0:d4960fcea8ff	110	#define PLLCFG_DIV3 0x00020000
kenjiArai	0:d4960fcea8ff	111	#define PLLCFG_DIV4 0x00030000
kenjiArai	0:d4960fcea8ff	112	#define PLLCFG_DIV5 0x00040000
kenjiArai	0:d4960fcea8ff	113	#define PLLCFG_DIV6 0x00050000
kenjiArai	0:d4960fcea8ff	114	#define PLLCFG_DIV7 0x00060000
kenjiArai	0:d4960fcea8ff	115	#define PLLCFG_DIV8 0x00070000
kenjiArai	0:d4960fcea8ff	116	#define PLLCFG_DIV9 0x00080000
kenjiArai	0:d4960fcea8ff	117	#define PLLCFG_DIV10 0x00090000
kenjiArai	0:d4960fcea8ff	118	#define PLLCFG_MASK 0x00FF7FFF
kenjiArai	0:d4960fcea8ff	119
kenjiArai	0:d4960fcea8ff	120	#define PLLSTAT_MSEL_MASK 0x00007FFF
kenjiArai	0:d4960fcea8ff	121	#define PLLSTAT_NSEL_MASK 0x00FF0000
kenjiArai	0:d4960fcea8ff	122
kenjiArai	0:d4960fcea8ff	123	#define PLLSTAT_PLLE (1 << 24)
kenjiArai	0:d4960fcea8ff	124	#define PLLSTAT_PLLC (1 << 25)
kenjiArai	0:d4960fcea8ff	125	#define PLLSTAT_PLOCK (1 << 26)
kenjiArai	0:d4960fcea8ff	126
kenjiArai	0:d4960fcea8ff	127	#define PLLFEED_FEED1 0x000000AA
kenjiArai	0:d4960fcea8ff	128	#define PLLFEED_FEED2 0x00000055
kenjiArai	0:d4960fcea8ff	129
kenjiArai	0:d4960fcea8ff	130	#define NVIC_IRQ_WDT 0u // IRQ0, exception number 16
kenjiArai	0:d4960fcea8ff	131	#define NVIC_IRQ_TIMER0 1u // IRQ1, exception number 17
kenjiArai	0:d4960fcea8ff	132	#define NVIC_IRQ_TIMER1 2u // IRQ2, exception number 18
kenjiArai	0:d4960fcea8ff	133	#define NVIC_IRQ_TIMER2 3u // IRQ3, exception number 19
kenjiArai	0:d4960fcea8ff	134	#define NVIC_IRQ_TIMER3 4u // IRQ4, exception number 20
kenjiArai	0:d4960fcea8ff	135	#define NVIC_IRQ_UART0 5u // IRQ5, exception number 21
kenjiArai	0:d4960fcea8ff	136	#define NVIC_IRQ_UART1 6u // IRQ6, exception number 22
kenjiArai	0:d4960fcea8ff	137	#define NVIC_IRQ_UART2 7u // IRQ7, exception number 23
kenjiArai	0:d4960fcea8ff	138	#define NVIC_IRQ_UART3 8u // IRQ8, exception number 24
kenjiArai	0:d4960fcea8ff	139	#define NVIC_IRQ_PWM1 9u // IRQ9, exception number 25
kenjiArai	0:d4960fcea8ff	140	#define NVIC_IRQ_I2C0 10u // IRQ10, exception number 26
kenjiArai	0:d4960fcea8ff	141	#define NVIC_IRQ_I2C1 11u // IRQ11, exception number 27
kenjiArai	0:d4960fcea8ff	142	#define NVIC_IRQ_I2C2 12u // IRQ12, exception number 28
kenjiArai	0:d4960fcea8ff	143	#define NVIC_IRQ_SPI 13u // IRQ13, exception number 29
kenjiArai	0:d4960fcea8ff	144	#define NVIC_IRQ_SSP0 14u // IRQ14, exception number 30
kenjiArai	0:d4960fcea8ff	145	#define NVIC_IRQ_SSP1 15u // IRQ15, exception number 31
kenjiArai	0:d4960fcea8ff	146	#define NVIC_IRQ_PLL0 16u // IRQ16, exception number 32
kenjiArai	0:d4960fcea8ff	147	#define NVIC_IRQ_RTC 17u // IRQ17, exception number 33
kenjiArai	0:d4960fcea8ff	148	#define NVIC_IRQ_EINT0 18u // IRQ18, exception number 34
kenjiArai	0:d4960fcea8ff	149	#define NVIC_IRQ_EINT1 19u // IRQ19, exception number 35
kenjiArai	0:d4960fcea8ff	150	#define NVIC_IRQ_EINT2 20u // IRQ20, exception number 36
kenjiArai	0:d4960fcea8ff	151	#define NVIC_IRQ_EINT3 21u // IRQ21, exception number 37
kenjiArai	0:d4960fcea8ff	152	#define NVIC_IRQ_ADC 22u // IRQ22, exception number 38
kenjiArai	0:d4960fcea8ff	153	#define NVIC_IRQ_BOD 23u // IRQ23, exception number 39
kenjiArai	0:d4960fcea8ff	154	#define NVIC_IRQ_USB 24u // IRQ24, exception number 40
kenjiArai	0:d4960fcea8ff	155	#define NVIC_IRQ_CAN 25u // IRQ25, exception number 41
kenjiArai	0:d4960fcea8ff	156	#define NVIC_IRQ_GPDMA 26u // IRQ26, exception number 42
kenjiArai	0:d4960fcea8ff	157	#define NVIC_IRQ_I2S 27u // IRQ27, exception number 43
kenjiArai	0:d4960fcea8ff	158	#define NVIC_IRQ_ETHERNET 28u // IRQ28, exception number 44
kenjiArai	0:d4960fcea8ff	159	#define NVIC_IRQ_RIT 29u // IRQ29, exception number 45
kenjiArai	0:d4960fcea8ff	160	#define NVIC_IRQ_MCPWM 30u // IRQ30, exception number 46
kenjiArai	0:d4960fcea8ff	161	#define NVIC_IRQ_QE 31u // IRQ31, exception number 47
kenjiArai	0:d4960fcea8ff	162	#define NVIC_IRQ_PLL1 32u // IRQ32, exception number 48
kenjiArai	0:d4960fcea8ff	163	#define NVIC_IRQ_USB_ACT 33u // IRQ33, exception number 49
kenjiArai	0:d4960fcea8ff	164	#define NVIC_IRQ_CAN_ACT 34u // IRQ34, exception number 50
kenjiArai	0:d4960fcea8ff	165	/////////////////////////////////////////////////////////////////////////////
kenjiArai	0:d4960fcea8ff	166
kenjiArai	0:d4960fcea8ff	167	/*
kenjiArai	0:d4960fcea8ff	168	* ==========================================================================
kenjiArai	0:d4960fcea8ff	169	* ---------- Interrupt Number Definition -----------------------------------
kenjiArai	0:d4960fcea8ff	170	* ==========================================================================
kenjiArai	0:d4960fcea8ff	171	*/
kenjiArai	0:d4960fcea8ff	172
kenjiArai	0:d4960fcea8ff	173	typedef enum IRQn
kenjiArai	0:d4960fcea8ff	174	{
kenjiArai	0:d4960fcea8ff	175	/**** Cortex-M3 Processor Exceptions Numbers *************************************************/
kenjiArai	0:d4960fcea8ff	176	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
kenjiArai	0:d4960fcea8ff	177	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
kenjiArai	0:d4960fcea8ff	178	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
kenjiArai	0:d4960fcea8ff	179	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
kenjiArai	0:d4960fcea8ff	180	SVCall_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
kenjiArai	0:d4960fcea8ff	181	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
kenjiArai	0:d4960fcea8ff	182	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
kenjiArai	0:d4960fcea8ff	183	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
kenjiArai	0:d4960fcea8ff	184
kenjiArai	0:d4960fcea8ff	185	/**** LPC17xx Specific Interrupt Numbers *****************************************************/
kenjiArai	0:d4960fcea8ff	186	WDT_IRQn = 0, /!< Watchdog Timer Interrupt /
kenjiArai	0:d4960fcea8ff	187	TIMER0_IRQn = 1, /!< Timer0 Interrupt /
kenjiArai	0:d4960fcea8ff	188	TIMER1_IRQn = 2, /!< Timer1 Interrupt /
kenjiArai	0:d4960fcea8ff	189	TIMER2_IRQn = 3, /!< Timer2 Interrupt /
kenjiArai	0:d4960fcea8ff	190	TIMER3_IRQn = 4, /!< Timer3 Interrupt /
kenjiArai	0:d4960fcea8ff	191	UART0_IRQn = 5, /!< UART0 Interrupt /
kenjiArai	0:d4960fcea8ff	192	UART1_IRQn = 6, /!< UART1 Interrupt /
kenjiArai	0:d4960fcea8ff	193	UART2_IRQn = 7, /!< UART2 Interrupt /
kenjiArai	0:d4960fcea8ff	194	UART3_IRQn = 8, /!< UART3 Interrupt /
kenjiArai	0:d4960fcea8ff	195	PWM1_IRQn = 9, /!< PWM1 Interrupt /
kenjiArai	0:d4960fcea8ff	196	I2C0_IRQn = 10, /!< I2C0 Interrupt /
kenjiArai	0:d4960fcea8ff	197	I2C1_IRQn = 11, /!< I2C1 Interrupt /
kenjiArai	0:d4960fcea8ff	198	I2C2_IRQn = 12, /!< I2C2 Interrupt /
kenjiArai	0:d4960fcea8ff	199	SPI_IRQn = 13, /!< SPI Interrupt /
kenjiArai	0:d4960fcea8ff	200	SSP0_IRQn = 14, /!< SSP0 Interrupt /
kenjiArai	0:d4960fcea8ff	201	SSP1_IRQn = 15, /!< SSP1 Interrupt /
kenjiArai	0:d4960fcea8ff	202	PLL0_IRQn = 16, /!< PLL0 Lock (Main PLL) Interrupt /
kenjiArai	0:d4960fcea8ff	203	RTC_IRQn = 17, /!< Real Time Clock Interrupt /
kenjiArai	0:d4960fcea8ff	204	EINT0_IRQn = 18, /!< External Interrupt 0 Interrupt /
kenjiArai	0:d4960fcea8ff	205	EINT1_IRQn = 19, /!< External Interrupt 1 Interrupt /
kenjiArai	0:d4960fcea8ff	206	EINT2_IRQn = 20, /!< External Interrupt 2 Interrupt /
kenjiArai	0:d4960fcea8ff	207	EINT3_IRQn = 21, /!< External Interrupt 3 Interrupt /
kenjiArai	0:d4960fcea8ff	208	ADC_IRQn = 22, /!< A/D Converter Interrupt /
kenjiArai	0:d4960fcea8ff	209	BOD_IRQn = 23, /!< Brown-Out Detect Interrupt /
kenjiArai	0:d4960fcea8ff	210	USB_IRQn = 24, /!< USB Interrupt /
kenjiArai	0:d4960fcea8ff	211	CAN_IRQn = 25, /!< CAN Interrupt /
kenjiArai	0:d4960fcea8ff	212	DMA_IRQn = 26, /!< General Purpose DMA Interrupt /
kenjiArai	0:d4960fcea8ff	213	I2S_IRQn = 27, /!< I2S Interrupt /
kenjiArai	0:d4960fcea8ff	214	ENET_IRQn = 28, /!< Ethernet Interrupt /
kenjiArai	0:d4960fcea8ff	215	RIT_IRQn = 29, /!< Repetitive Interrupt Timer Interrupt /
kenjiArai	0:d4960fcea8ff	216	MCPWM_IRQn = 30, /!< Motor Control PWM Interrupt /
kenjiArai	0:d4960fcea8ff	217	QEI_IRQn = 31, /!< Quadrature Encoder Interface Interrupt /
kenjiArai	0:d4960fcea8ff	218	PLL1_IRQn = 32, /!< PLL1 Lock (USB PLL) Interrupt /
kenjiArai	0:d4960fcea8ff	219	} IRQn_Type;
kenjiArai	0:d4960fcea8ff	220
kenjiArai	0:d4960fcea8ff	221
kenjiArai	0:d4960fcea8ff	222	/*
kenjiArai	0:d4960fcea8ff	223	* ==========================================================================
kenjiArai	0:d4960fcea8ff	224	* ----------- Processor and Core Peripheral Section ------------------------
kenjiArai	0:d4960fcea8ff	225	* ==========================================================================
kenjiArai	0:d4960fcea8ff	226	*/
kenjiArai	0:d4960fcea8ff	227
kenjiArai	0:d4960fcea8ff	228	/* Configuration of the Cortex-M3 Processor and Core Peripherals */
kenjiArai	0:d4960fcea8ff	229	#define __MPU_PRESENT 1 /!< MPU present or not /
kenjiArai	0:d4960fcea8ff	230	#define __NVIC_PRIO_BITS 5 /!< Number of Bits used for Priority Levels /
kenjiArai	0:d4960fcea8ff	231	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
kenjiArai	0:d4960fcea8ff	232
kenjiArai	0:d4960fcea8ff	233
kenjiArai	0:d4960fcea8ff	234	//#include <core_cm3.h> /* Cortex-M3 processor and core peripherals */
kenjiArai	0:d4960fcea8ff	235	#include "core_cm3.h" // by roger
kenjiArai	0:d4960fcea8ff	236
kenjiArai	0:d4960fcea8ff	237	/******************************************************************************/
kenjiArai	0:d4960fcea8ff	238	/* Device Specific Peripheral registers structures */
kenjiArai	0:d4960fcea8ff	239	/******************************************************************************/
kenjiArai	0:d4960fcea8ff	240
kenjiArai	0:d4960fcea8ff	241	#pragma anon_unions
kenjiArai	0:d4960fcea8ff	242
kenjiArai	0:d4960fcea8ff	243	/------------- System Control (SC) ------------------------------------------/
kenjiArai	0:d4960fcea8ff	244	typedef struct
kenjiArai	0:d4960fcea8ff	245	{
kenjiArai	0:d4960fcea8ff	246	__IO uint32_t FLASHCFG; /* Flash Accelerator Module */
kenjiArai	0:d4960fcea8ff	247	uint32_t RESERVED0[31];
kenjiArai	0:d4960fcea8ff	248	__IO uint32_t PLL0CON; /* Clocking and Power Control */
kenjiArai	0:d4960fcea8ff	249	__IO uint32_t PLL0CFG;
kenjiArai	0:d4960fcea8ff	250	__I uint32_t PLL0STAT;
kenjiArai	0:d4960fcea8ff	251	__O uint32_t PLL0FEED;
kenjiArai	0:d4960fcea8ff	252	uint32_t RESERVED1[4];
kenjiArai	0:d4960fcea8ff	253	__IO uint32_t PLL1CON;
kenjiArai	0:d4960fcea8ff	254	__IO uint32_t PLL1CFG;
kenjiArai	0:d4960fcea8ff	255	__I uint32_t PLL1STAT;
kenjiArai	0:d4960fcea8ff	256	__O uint32_t PLL1FEED;
kenjiArai	0:d4960fcea8ff	257	uint32_t RESERVED2[4];
kenjiArai	0:d4960fcea8ff	258	__IO uint32_t PCON;
kenjiArai	0:d4960fcea8ff	259	__IO uint32_t PCONP;
kenjiArai	0:d4960fcea8ff	260	uint32_t RESERVED3[15];
kenjiArai	0:d4960fcea8ff	261	__IO uint32_t CCLKCFG;
kenjiArai	0:d4960fcea8ff	262	__IO uint32_t USBCLKCFG;
kenjiArai	0:d4960fcea8ff	263	__IO uint32_t CLKSRCSEL;
kenjiArai	0:d4960fcea8ff	264	uint32_t RESERVED4[12];
kenjiArai	0:d4960fcea8ff	265	__IO uint32_t EXTINT; /* External Interrupts */
kenjiArai	0:d4960fcea8ff	266	uint32_t RESERVED5;
kenjiArai	0:d4960fcea8ff	267	__IO uint32_t EXTMODE;
kenjiArai	0:d4960fcea8ff	268	__IO uint32_t EXTPOLAR;
kenjiArai	0:d4960fcea8ff	269	uint32_t RESERVED6[12];
kenjiArai	0:d4960fcea8ff	270	__IO uint32_t RSID; /* Reset */
kenjiArai	0:d4960fcea8ff	271	uint32_t RESERVED7[7];
kenjiArai	0:d4960fcea8ff	272	__IO uint32_t SCS; /* Syscon Miscellaneous Registers */
kenjiArai	0:d4960fcea8ff	273	__IO uint32_t IRCTRIM; /* Clock Dividers */
kenjiArai	0:d4960fcea8ff	274	__IO uint32_t PCLKSEL0;
kenjiArai	0:d4960fcea8ff	275	__IO uint32_t PCLKSEL1;
kenjiArai	0:d4960fcea8ff	276	uint32_t RESERVED8[4];
kenjiArai	0:d4960fcea8ff	277	__IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
kenjiArai	0:d4960fcea8ff	278	uint32_t RESERVED9;
kenjiArai	0:d4960fcea8ff	279	__IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
kenjiArai	0:d4960fcea8ff	280	} LPC_SC_TypeDef;
kenjiArai	0:d4960fcea8ff	281
kenjiArai	0:d4960fcea8ff	282	/------------- Pin Connect Block (PINCON) -----------------------------------/
kenjiArai	0:d4960fcea8ff	283	typedef struct
kenjiArai	0:d4960fcea8ff	284	{
kenjiArai	0:d4960fcea8ff	285	__IO uint32_t PINSEL0;
kenjiArai	0:d4960fcea8ff	286	__IO uint32_t PINSEL1;
kenjiArai	0:d4960fcea8ff	287	__IO uint32_t PINSEL2;
kenjiArai	0:d4960fcea8ff	288	__IO uint32_t PINSEL3;
kenjiArai	0:d4960fcea8ff	289	__IO uint32_t PINSEL4;
kenjiArai	0:d4960fcea8ff	290	__IO uint32_t PINSEL5;
kenjiArai	0:d4960fcea8ff	291	__IO uint32_t PINSEL6;
kenjiArai	0:d4960fcea8ff	292	__IO uint32_t PINSEL7;
kenjiArai	0:d4960fcea8ff	293	__IO uint32_t PINSEL8;
kenjiArai	0:d4960fcea8ff	294	__IO uint32_t PINSEL9;
kenjiArai	0:d4960fcea8ff	295	__IO uint32_t PINSEL10;
kenjiArai	0:d4960fcea8ff	296	uint32_t RESERVED0[5];
kenjiArai	0:d4960fcea8ff	297	__IO uint32_t PINMODE0;
kenjiArai	0:d4960fcea8ff	298	__IO uint32_t PINMODE1;
kenjiArai	0:d4960fcea8ff	299	__IO uint32_t PINMODE2;
kenjiArai	0:d4960fcea8ff	300	__IO uint32_t PINMODE3;
kenjiArai	0:d4960fcea8ff	301	__IO uint32_t PINMODE4;
kenjiArai	0:d4960fcea8ff	302	__IO uint32_t PINMODE5;
kenjiArai	0:d4960fcea8ff	303	__IO uint32_t PINMODE6;
kenjiArai	0:d4960fcea8ff	304	__IO uint32_t PINMODE7;
kenjiArai	0:d4960fcea8ff	305	__IO uint32_t PINMODE8;
kenjiArai	0:d4960fcea8ff	306	__IO uint32_t PINMODE9;
kenjiArai	0:d4960fcea8ff	307	__IO uint32_t PINMODE_OD0;
kenjiArai	0:d4960fcea8ff	308	__IO uint32_t PINMODE_OD1;
kenjiArai	0:d4960fcea8ff	309	__IO uint32_t PINMODE_OD2;
kenjiArai	0:d4960fcea8ff	310	__IO uint32_t PINMODE_OD3;
kenjiArai	0:d4960fcea8ff	311	__IO uint32_t PINMODE_OD4;
kenjiArai	0:d4960fcea8ff	312	__IO uint32_t I2CPADCFG;
kenjiArai	0:d4960fcea8ff	313	} LPC_PINCON_TypeDef;
kenjiArai	0:d4960fcea8ff	314
kenjiArai	0:d4960fcea8ff	315	/------------- General Purpose Input/Output (GPIO) --------------------------/
kenjiArai	0:d4960fcea8ff	316	typedef struct
kenjiArai	0:d4960fcea8ff	317	{
kenjiArai	0:d4960fcea8ff	318	__IO uint32_t FIODIR;
kenjiArai	0:d4960fcea8ff	319	uint32_t RESERVED0[3];
kenjiArai	0:d4960fcea8ff	320	__IO uint32_t FIOMASK;
kenjiArai	0:d4960fcea8ff	321	__IO uint32_t FIOPIN;
kenjiArai	0:d4960fcea8ff	322	__IO uint32_t FIOSET;
kenjiArai	0:d4960fcea8ff	323	__O uint32_t FIOCLR;
kenjiArai	0:d4960fcea8ff	324	} LPC_GPIO_TypeDef;
kenjiArai	0:d4960fcea8ff	325
kenjiArai	0:d4960fcea8ff	326	typedef struct
kenjiArai	0:d4960fcea8ff	327	{
kenjiArai	0:d4960fcea8ff	328	__I uint32_t IntStatus;
kenjiArai	0:d4960fcea8ff	329	__I uint32_t IO0IntStatR;
kenjiArai	0:d4960fcea8ff	330	__I uint32_t IO0IntStatF;
kenjiArai	0:d4960fcea8ff	331	__O uint32_t IO0IntClr;
kenjiArai	0:d4960fcea8ff	332	__IO uint32_t IO0IntEnR;
kenjiArai	0:d4960fcea8ff	333	__IO uint32_t IO0IntEnF;
kenjiArai	0:d4960fcea8ff	334	uint32_t RESERVED0[3];
kenjiArai	0:d4960fcea8ff	335	__I uint32_t IO2IntStatR;
kenjiArai	0:d4960fcea8ff	336	__I uint32_t IO2IntStatF;
kenjiArai	0:d4960fcea8ff	337	__O uint32_t IO2IntClr;
kenjiArai	0:d4960fcea8ff	338	__IO uint32_t IO2IntEnR;
kenjiArai	0:d4960fcea8ff	339	__IO uint32_t IO2IntEnF;
kenjiArai	0:d4960fcea8ff	340	} LPC_GPIOINT_TypeDef;
kenjiArai	0:d4960fcea8ff	341
kenjiArai	0:d4960fcea8ff	342	/------------- Timer (TIM) --------------------------------------------------/
kenjiArai	0:d4960fcea8ff	343	typedef struct
kenjiArai	0:d4960fcea8ff	344	{
kenjiArai	0:d4960fcea8ff	345	__IO uint32_t IR;
kenjiArai	0:d4960fcea8ff	346	__IO uint32_t TCR;
kenjiArai	0:d4960fcea8ff	347	__IO uint32_t TC;
kenjiArai	0:d4960fcea8ff	348	__IO uint32_t PR;
kenjiArai	0:d4960fcea8ff	349	__IO uint32_t PC;
kenjiArai	0:d4960fcea8ff	350	__IO uint32_t MCR;
kenjiArai	0:d4960fcea8ff	351	__IO uint32_t MR0;
kenjiArai	0:d4960fcea8ff	352	__IO uint32_t MR1;
kenjiArai	0:d4960fcea8ff	353	__IO uint32_t MR2;
kenjiArai	0:d4960fcea8ff	354	__IO uint32_t MR3;
kenjiArai	0:d4960fcea8ff	355	__IO uint32_t CCR;
kenjiArai	0:d4960fcea8ff	356	__I uint32_t CR0;
kenjiArai	0:d4960fcea8ff	357	__I uint32_t CR1;
kenjiArai	0:d4960fcea8ff	358	uint32_t RESERVED0[2];
kenjiArai	0:d4960fcea8ff	359	__IO uint32_t EMR;
kenjiArai	0:d4960fcea8ff	360	uint32_t RESERVED1[12];
kenjiArai	0:d4960fcea8ff	361	__IO uint32_t CTCR;
kenjiArai	0:d4960fcea8ff	362	} LPC_TIM_TypeDef;
kenjiArai	0:d4960fcea8ff	363
kenjiArai	0:d4960fcea8ff	364	/------------- Pulse-Width Modulation (PWM) ---------------------------------/
kenjiArai	0:d4960fcea8ff	365	typedef struct
kenjiArai	0:d4960fcea8ff	366	{
kenjiArai	0:d4960fcea8ff	367	__IO uint32_t IR;
kenjiArai	0:d4960fcea8ff	368	__IO uint32_t TCR;
kenjiArai	0:d4960fcea8ff	369	__IO uint32_t TC;
kenjiArai	0:d4960fcea8ff	370	__IO uint32_t PR;
kenjiArai	0:d4960fcea8ff	371	__IO uint32_t PC;
kenjiArai	0:d4960fcea8ff	372	__IO uint32_t MCR;
kenjiArai	0:d4960fcea8ff	373	__IO uint32_t MR0;
kenjiArai	0:d4960fcea8ff	374	__IO uint32_t MR1;
kenjiArai	0:d4960fcea8ff	375	__IO uint32_t MR2;
kenjiArai	0:d4960fcea8ff	376	__IO uint32_t MR3;
kenjiArai	0:d4960fcea8ff	377	__IO uint32_t CCR;
kenjiArai	0:d4960fcea8ff	378	__I uint32_t CR0;
kenjiArai	0:d4960fcea8ff	379	__I uint32_t CR1;
kenjiArai	0:d4960fcea8ff	380	__I uint32_t CR2;
kenjiArai	0:d4960fcea8ff	381	__I uint32_t CR3;
kenjiArai	0:d4960fcea8ff	382	uint32_t RESERVED0;
kenjiArai	0:d4960fcea8ff	383	__IO uint32_t MR4;
kenjiArai	0:d4960fcea8ff	384	__IO uint32_t MR5;
kenjiArai	0:d4960fcea8ff	385	__IO uint32_t MR6;
kenjiArai	0:d4960fcea8ff	386	__IO uint32_t PCR;
kenjiArai	0:d4960fcea8ff	387	__IO uint32_t LER;
kenjiArai	0:d4960fcea8ff	388	uint32_t RESERVED1[7];
kenjiArai	0:d4960fcea8ff	389	__IO uint32_t CTCR;
kenjiArai	0:d4960fcea8ff	390	} LPC_PWM_TypeDef;
kenjiArai	0:d4960fcea8ff	391
kenjiArai	0:d4960fcea8ff	392	/------------- Universal Asynchronous Receiver Transmitter (UART) -----------/
kenjiArai	0:d4960fcea8ff	393	typedef struct
kenjiArai	0:d4960fcea8ff	394	{
kenjiArai	0:d4960fcea8ff	395	union {
kenjiArai	0:d4960fcea8ff	396	__I uint8_t RBR;
kenjiArai	0:d4960fcea8ff	397	__O uint8_t THR;
kenjiArai	0:d4960fcea8ff	398	__IO uint8_t DLL;
kenjiArai	0:d4960fcea8ff	399	uint32_t RESERVED0;
kenjiArai	0:d4960fcea8ff	400	};
kenjiArai	0:d4960fcea8ff	401	union {
kenjiArai	0:d4960fcea8ff	402	__IO uint8_t DLM;
kenjiArai	0:d4960fcea8ff	403	__IO uint32_t IER;
kenjiArai	0:d4960fcea8ff	404	};
kenjiArai	0:d4960fcea8ff	405	union {
kenjiArai	0:d4960fcea8ff	406	__I uint32_t IIR;
kenjiArai	0:d4960fcea8ff	407	__O uint8_t FCR;
kenjiArai	0:d4960fcea8ff	408	};
kenjiArai	0:d4960fcea8ff	409	__IO uint8_t LCR;
kenjiArai	0:d4960fcea8ff	410	uint8_t RESERVED1[7];
kenjiArai	0:d4960fcea8ff	411	__I uint8_t LSR;
kenjiArai	0:d4960fcea8ff	412	uint8_t RESERVED2[7];
kenjiArai	0:d4960fcea8ff	413	__IO uint8_t SCR;
kenjiArai	0:d4960fcea8ff	414	uint8_t RESERVED3[3];
kenjiArai	0:d4960fcea8ff	415	__IO uint32_t ACR;
kenjiArai	0:d4960fcea8ff	416	__IO uint8_t ICR;
kenjiArai	0:d4960fcea8ff	417	uint8_t RESERVED4[3];
kenjiArai	0:d4960fcea8ff	418	__IO uint8_t FDR;
kenjiArai	0:d4960fcea8ff	419	uint8_t RESERVED5[7];
kenjiArai	0:d4960fcea8ff	420	__IO uint8_t TER;
kenjiArai	0:d4960fcea8ff	421	uint8_t RESERVED6[39];
kenjiArai	0:d4960fcea8ff	422	__I uint8_t FIFOLVL;
kenjiArai	0:d4960fcea8ff	423	} LPC_UART_TypeDef;
kenjiArai	0:d4960fcea8ff	424
kenjiArai	0:d4960fcea8ff	425	typedef struct
kenjiArai	0:d4960fcea8ff	426	{
kenjiArai	0:d4960fcea8ff	427	union {
kenjiArai	0:d4960fcea8ff	428	__I uint8_t RBR;
kenjiArai	0:d4960fcea8ff	429	__O uint8_t THR;
kenjiArai	0:d4960fcea8ff	430	__IO uint8_t DLL;
kenjiArai	0:d4960fcea8ff	431	uint32_t RESERVED0;
kenjiArai	0:d4960fcea8ff	432	};
kenjiArai	0:d4960fcea8ff	433	union {
kenjiArai	0:d4960fcea8ff	434	__IO uint8_t DLM;
kenjiArai	0:d4960fcea8ff	435	__IO uint32_t IER;
kenjiArai	0:d4960fcea8ff	436	};
kenjiArai	0:d4960fcea8ff	437	union {
kenjiArai	0:d4960fcea8ff	438	__I uint32_t IIR;
kenjiArai	0:d4960fcea8ff	439	__O uint8_t FCR;
kenjiArai	0:d4960fcea8ff	440	};
kenjiArai	0:d4960fcea8ff	441	__IO uint8_t LCR;
kenjiArai	0:d4960fcea8ff	442	uint8_t RESERVED1[7];
kenjiArai	0:d4960fcea8ff	443	__I uint8_t LSR;
kenjiArai	0:d4960fcea8ff	444	uint8_t RESERVED2[7];
kenjiArai	0:d4960fcea8ff	445	__IO uint8_t SCR;
kenjiArai	0:d4960fcea8ff	446	uint8_t RESERVED3[3];
kenjiArai	0:d4960fcea8ff	447	__IO uint32_t ACR;
kenjiArai	0:d4960fcea8ff	448	__IO uint8_t ICR;
kenjiArai	0:d4960fcea8ff	449	uint8_t RESERVED4[3];
kenjiArai	0:d4960fcea8ff	450	__IO uint8_t FDR;
kenjiArai	0:d4960fcea8ff	451	uint8_t RESERVED5[7];
kenjiArai	0:d4960fcea8ff	452	__IO uint8_t TER;
kenjiArai	0:d4960fcea8ff	453	uint8_t RESERVED6[39];
kenjiArai	0:d4960fcea8ff	454	__I uint8_t FIFOLVL;
kenjiArai	0:d4960fcea8ff	455	uint8_t RESERVED7[363];
kenjiArai	0:d4960fcea8ff	456	__IO uint32_t DMAREQSEL;
kenjiArai	0:d4960fcea8ff	457	} LPC_UART0_TypeDef;
kenjiArai	0:d4960fcea8ff	458
kenjiArai	0:d4960fcea8ff	459	typedef struct
kenjiArai	0:d4960fcea8ff	460	{
kenjiArai	0:d4960fcea8ff	461	union {
kenjiArai	0:d4960fcea8ff	462	__I uint8_t RBR;
kenjiArai	0:d4960fcea8ff	463	__O uint8_t THR;
kenjiArai	0:d4960fcea8ff	464	__IO uint8_t DLL;
kenjiArai	0:d4960fcea8ff	465	uint32_t RESERVED0;
kenjiArai	0:d4960fcea8ff	466	};
kenjiArai	0:d4960fcea8ff	467	union {
kenjiArai	0:d4960fcea8ff	468	__IO uint8_t DLM;
kenjiArai	0:d4960fcea8ff	469	__IO uint32_t IER;
kenjiArai	0:d4960fcea8ff	470	};
kenjiArai	0:d4960fcea8ff	471	union {
kenjiArai	0:d4960fcea8ff	472	__I uint32_t IIR;
kenjiArai	0:d4960fcea8ff	473	__O uint8_t FCR;
kenjiArai	0:d4960fcea8ff	474	};
kenjiArai	0:d4960fcea8ff	475	__IO uint8_t LCR;
kenjiArai	0:d4960fcea8ff	476	uint8_t RESERVED1[3];
kenjiArai	0:d4960fcea8ff	477	__IO uint8_t MCR;
kenjiArai	0:d4960fcea8ff	478	uint8_t RESERVED2[3];
kenjiArai	0:d4960fcea8ff	479	__I uint8_t LSR;
kenjiArai	0:d4960fcea8ff	480	uint8_t RESERVED3[3];
kenjiArai	0:d4960fcea8ff	481	__I uint8_t MSR;
kenjiArai	0:d4960fcea8ff	482	uint8_t RESERVED4[3];
kenjiArai	0:d4960fcea8ff	483	__IO uint8_t SCR;
kenjiArai	0:d4960fcea8ff	484	uint8_t RESERVED5[3];
kenjiArai	0:d4960fcea8ff	485	__IO uint32_t ACR;
kenjiArai	0:d4960fcea8ff	486	uint32_t RESERVED6;
kenjiArai	0:d4960fcea8ff	487	__IO uint32_t FDR;
kenjiArai	0:d4960fcea8ff	488	uint32_t RESERVED7;
kenjiArai	0:d4960fcea8ff	489	__IO uint8_t TER;
kenjiArai	0:d4960fcea8ff	490	uint8_t RESERVED8[27];
kenjiArai	0:d4960fcea8ff	491	__IO uint8_t RS485CTRL;
kenjiArai	0:d4960fcea8ff	492	uint8_t RESERVED9[3];
kenjiArai	0:d4960fcea8ff	493	__IO uint8_t ADRMATCH;
kenjiArai	0:d4960fcea8ff	494	uint8_t RESERVED10[3];
kenjiArai	0:d4960fcea8ff	495	__IO uint8_t RS485DLY;
kenjiArai	0:d4960fcea8ff	496	uint8_t RESERVED11[3];
kenjiArai	0:d4960fcea8ff	497	__I uint8_t FIFOLVL;
kenjiArai	0:d4960fcea8ff	498	} LPC_UART1_TypeDef;
kenjiArai	0:d4960fcea8ff	499
kenjiArai	0:d4960fcea8ff	500	/------------- Serial Peripheral Interface (SPI) ----------------------------/
kenjiArai	0:d4960fcea8ff	501	typedef struct
kenjiArai	0:d4960fcea8ff	502	{
kenjiArai	0:d4960fcea8ff	503	__IO uint32_t SPCR;
kenjiArai	0:d4960fcea8ff	504	__I uint32_t SPSR;
kenjiArai	0:d4960fcea8ff	505	__IO uint32_t SPDR;
kenjiArai	0:d4960fcea8ff	506	__IO uint32_t SPCCR;
kenjiArai	0:d4960fcea8ff	507	uint32_t RESERVED0[3];
kenjiArai	0:d4960fcea8ff	508	__IO uint32_t SPINT;
kenjiArai	0:d4960fcea8ff	509	} LPC_SPI_TypeDef;
kenjiArai	0:d4960fcea8ff	510
kenjiArai	0:d4960fcea8ff	511	/------------- Synchronous Serial Communication (SSP) -----------------------/
kenjiArai	0:d4960fcea8ff	512	typedef struct
kenjiArai	0:d4960fcea8ff	513	{
kenjiArai	0:d4960fcea8ff	514	__IO uint32_t CR0;
kenjiArai	0:d4960fcea8ff	515	__IO uint32_t CR1;
kenjiArai	0:d4960fcea8ff	516	__IO uint32_t DR;
kenjiArai	0:d4960fcea8ff	517	__I uint32_t SR;
kenjiArai	0:d4960fcea8ff	518	__IO uint32_t CPSR;
kenjiArai	0:d4960fcea8ff	519	__IO uint32_t IMSC;
kenjiArai	0:d4960fcea8ff	520	__IO uint32_t RIS;
kenjiArai	0:d4960fcea8ff	521	__IO uint32_t MIS;
kenjiArai	0:d4960fcea8ff	522	__IO uint32_t ICR;
kenjiArai	0:d4960fcea8ff	523	__IO uint32_t DMACR;
kenjiArai	0:d4960fcea8ff	524	} LPC_SSP_TypeDef;
kenjiArai	0:d4960fcea8ff	525
kenjiArai	0:d4960fcea8ff	526	/------------- Inter-Integrated Circuit (I2C) -------------------------------/
kenjiArai	0:d4960fcea8ff	527	typedef struct
kenjiArai	0:d4960fcea8ff	528	{
kenjiArai	0:d4960fcea8ff	529	__IO uint32_t I2CONSET;
kenjiArai	0:d4960fcea8ff	530	__I uint32_t I2STAT;
kenjiArai	0:d4960fcea8ff	531	__IO uint32_t I2DAT;
kenjiArai	0:d4960fcea8ff	532	__IO uint32_t I2ADR0;
kenjiArai	0:d4960fcea8ff	533	__IO uint32_t I2SCLH;
kenjiArai	0:d4960fcea8ff	534	__IO uint32_t I2SCLL;
kenjiArai	0:d4960fcea8ff	535	__O uint32_t I2CONCLR;
kenjiArai	0:d4960fcea8ff	536	__IO uint32_t MMCTRL;
kenjiArai	0:d4960fcea8ff	537	__IO uint32_t I2ADR1;
kenjiArai	0:d4960fcea8ff	538	__IO uint32_t I2ADR2;
kenjiArai	0:d4960fcea8ff	539	__IO uint32_t I2ADR3;
kenjiArai	0:d4960fcea8ff	540	__I uint32_t I2DATA_BUFFER;
kenjiArai	0:d4960fcea8ff	541	__IO uint32_t I2MASK0;
kenjiArai	0:d4960fcea8ff	542	__IO uint32_t I2MASK1;
kenjiArai	0:d4960fcea8ff	543	__IO uint32_t I2MASK2;
kenjiArai	0:d4960fcea8ff	544	__IO uint32_t I2MASK3;
kenjiArai	0:d4960fcea8ff	545	} LPC_I2C_TypeDef;
kenjiArai	0:d4960fcea8ff	546
kenjiArai	0:d4960fcea8ff	547	/------------- Inter IC Sound (I2S) -----------------------------------------/
kenjiArai	0:d4960fcea8ff	548	typedef struct
kenjiArai	0:d4960fcea8ff	549	{
kenjiArai	0:d4960fcea8ff	550	__IO uint32_t I2SDAO;
kenjiArai	0:d4960fcea8ff	551	__IO uint32_t I2SDAI;
kenjiArai	0:d4960fcea8ff	552	__O uint32_t I2STXFIFO;
kenjiArai	0:d4960fcea8ff	553	__I uint32_t I2SRXFIFO;
kenjiArai	0:d4960fcea8ff	554	__I uint32_t I2SSTATE;
kenjiArai	0:d4960fcea8ff	555	__IO uint32_t I2SDMA1;
kenjiArai	0:d4960fcea8ff	556	__IO uint32_t I2SDMA2;
kenjiArai	0:d4960fcea8ff	557	__IO uint32_t I2SIRQ;
kenjiArai	0:d4960fcea8ff	558	__IO uint32_t I2STXRATE;
kenjiArai	0:d4960fcea8ff	559	__IO uint32_t I2SRXRATE;
kenjiArai	0:d4960fcea8ff	560	__IO uint32_t I2STXBITRATE;
kenjiArai	0:d4960fcea8ff	561	__IO uint32_t I2SRXBITRATE;
kenjiArai	0:d4960fcea8ff	562	__IO uint32_t I2STXMODE;
kenjiArai	0:d4960fcea8ff	563	__IO uint32_t I2SRXMODE;
kenjiArai	0:d4960fcea8ff	564	} LPC_I2S_TypeDef;
kenjiArai	0:d4960fcea8ff	565
kenjiArai	0:d4960fcea8ff	566	/------------- Repetitive Interrupt Timer (RIT) -----------------------------/
kenjiArai	0:d4960fcea8ff	567	typedef struct
kenjiArai	0:d4960fcea8ff	568	{
kenjiArai	0:d4960fcea8ff	569	__IO uint32_t RICOMPVAL;
kenjiArai	0:d4960fcea8ff	570	__IO uint32_t RIMASK;
kenjiArai	0:d4960fcea8ff	571	__IO uint8_t RICTRL;
kenjiArai	0:d4960fcea8ff	572	uint8_t RESERVED0[3];
kenjiArai	0:d4960fcea8ff	573	__IO uint32_t RICOUNTER;
kenjiArai	0:d4960fcea8ff	574	} LPC_RIT_TypeDef;
kenjiArai	0:d4960fcea8ff	575
kenjiArai	0:d4960fcea8ff	576	/------------- Real-Time Clock (RTC) ----------------------------------------/
kenjiArai	0:d4960fcea8ff	577	typedef struct
kenjiArai	0:d4960fcea8ff	578	{
kenjiArai	0:d4960fcea8ff	579	__IO uint8_t ILR;
kenjiArai	0:d4960fcea8ff	580	uint8_t RESERVED0[7];
kenjiArai	0:d4960fcea8ff	581	__IO uint8_t CCR;
kenjiArai	0:d4960fcea8ff	582	uint8_t RESERVED1[3];
kenjiArai	0:d4960fcea8ff	583	__IO uint8_t CIIR;
kenjiArai	0:d4960fcea8ff	584	uint8_t RESERVED2[3];
kenjiArai	0:d4960fcea8ff	585	__IO uint8_t AMR;
kenjiArai	0:d4960fcea8ff	586	uint8_t RESERVED3[3];
kenjiArai	0:d4960fcea8ff	587	__I uint32_t CTIME0;
kenjiArai	0:d4960fcea8ff	588	__I uint32_t CTIME1;
kenjiArai	0:d4960fcea8ff	589	__I uint32_t CTIME2;
kenjiArai	0:d4960fcea8ff	590	__IO uint8_t SEC;
kenjiArai	0:d4960fcea8ff	591	uint8_t RESERVED4[3];
kenjiArai	0:d4960fcea8ff	592	__IO uint8_t MIN;
kenjiArai	0:d4960fcea8ff	593	uint8_t RESERVED5[3];
kenjiArai	0:d4960fcea8ff	594	__IO uint8_t HOUR;
kenjiArai	0:d4960fcea8ff	595	uint8_t RESERVED6[3];
kenjiArai	0:d4960fcea8ff	596	__IO uint8_t DOM;
kenjiArai	0:d4960fcea8ff	597	uint8_t RESERVED7[3];
kenjiArai	0:d4960fcea8ff	598	__IO uint8_t DOW;
kenjiArai	0:d4960fcea8ff	599	uint8_t RESERVED8[3];
kenjiArai	0:d4960fcea8ff	600	__IO uint16_t DOY;
kenjiArai	0:d4960fcea8ff	601	uint16_t RESERVED9;
kenjiArai	0:d4960fcea8ff	602	__IO uint8_t MONTH;
kenjiArai	0:d4960fcea8ff	603	uint8_t RESERVED10[3];
kenjiArai	0:d4960fcea8ff	604	__IO uint16_t YEAR;
kenjiArai	0:d4960fcea8ff	605	uint16_t RESERVED11;
kenjiArai	0:d4960fcea8ff	606	__IO uint32_t CALIBRATION;
kenjiArai	0:d4960fcea8ff	607	__IO uint32_t GPREG0;
kenjiArai	0:d4960fcea8ff	608	__IO uint32_t GPREG1;
kenjiArai	0:d4960fcea8ff	609	__IO uint32_t GPREG2;
kenjiArai	0:d4960fcea8ff	610	__IO uint32_t GPREG3;
kenjiArai	0:d4960fcea8ff	611	__IO uint32_t GPREG4;
kenjiArai	0:d4960fcea8ff	612	__IO uint8_t RTC_AUXEN;
kenjiArai	0:d4960fcea8ff	613	uint8_t RESERVED12[3];
kenjiArai	0:d4960fcea8ff	614	__IO uint8_t RTC_AUX;
kenjiArai	0:d4960fcea8ff	615	uint8_t RESERVED13[3];
kenjiArai	0:d4960fcea8ff	616	__IO uint8_t ALSEC;
kenjiArai	0:d4960fcea8ff	617	uint8_t RESERVED14[3];
kenjiArai	0:d4960fcea8ff	618	__IO uint8_t ALMIN;
kenjiArai	0:d4960fcea8ff	619	uint8_t RESERVED15[3];
kenjiArai	0:d4960fcea8ff	620	__IO uint8_t ALHOUR;
kenjiArai	0:d4960fcea8ff	621	uint8_t RESERVED16[3];
kenjiArai	0:d4960fcea8ff	622	__IO uint8_t ALDOM;
kenjiArai	0:d4960fcea8ff	623	uint8_t RESERVED17[3];
kenjiArai	0:d4960fcea8ff	624	__IO uint8_t ALDOW;
kenjiArai	0:d4960fcea8ff	625	uint8_t RESERVED18[3];
kenjiArai	0:d4960fcea8ff	626	__IO uint16_t ALDOY;
kenjiArai	0:d4960fcea8ff	627	uint16_t RESERVED19;
kenjiArai	0:d4960fcea8ff	628	__IO uint8_t ALMON;
kenjiArai	0:d4960fcea8ff	629	uint8_t RESERVED20[3];
kenjiArai	0:d4960fcea8ff	630	__IO uint16_t ALYEAR;
kenjiArai	0:d4960fcea8ff	631	uint16_t RESERVED21;
kenjiArai	0:d4960fcea8ff	632	} LPC_RTC_TypeDef;
kenjiArai	0:d4960fcea8ff	633
kenjiArai	0:d4960fcea8ff	634	/------------- Watchdog Timer (WDT) -----------------------------------------/
kenjiArai	0:d4960fcea8ff	635	typedef struct
kenjiArai	0:d4960fcea8ff	636	{
kenjiArai	0:d4960fcea8ff	637	__IO uint8_t WDMOD;
kenjiArai	0:d4960fcea8ff	638	uint8_t RESERVED0[3];
kenjiArai	0:d4960fcea8ff	639	__IO uint32_t WDTC;
kenjiArai	0:d4960fcea8ff	640	__O uint8_t WDFEED;
kenjiArai	0:d4960fcea8ff	641	uint8_t RESERVED1[3];
kenjiArai	0:d4960fcea8ff	642	__I uint32_t WDTV;
kenjiArai	0:d4960fcea8ff	643	__IO uint32_t WDCLKSEL;
kenjiArai	0:d4960fcea8ff	644	} LPC_WDT_TypeDef;
kenjiArai	0:d4960fcea8ff	645
kenjiArai	0:d4960fcea8ff	646	/------------- Analog-to-Digital Converter (ADC) ----------------------------/
kenjiArai	0:d4960fcea8ff	647	typedef struct
kenjiArai	0:d4960fcea8ff	648	{
kenjiArai	0:d4960fcea8ff	649	__IO uint32_t ADCR;
kenjiArai	0:d4960fcea8ff	650	__IO uint32_t ADGDR;
kenjiArai	0:d4960fcea8ff	651	uint32_t RESERVED0;
kenjiArai	0:d4960fcea8ff	652	__IO uint32_t ADINTEN;
kenjiArai	0:d4960fcea8ff	653	__I uint32_t ADDR0;
kenjiArai	0:d4960fcea8ff	654	__I uint32_t ADDR1;
kenjiArai	0:d4960fcea8ff	655	__I uint32_t ADDR2;
kenjiArai	0:d4960fcea8ff	656	__I uint32_t ADDR3;
kenjiArai	0:d4960fcea8ff	657	__I uint32_t ADDR4;
kenjiArai	0:d4960fcea8ff	658	__I uint32_t ADDR5;
kenjiArai	0:d4960fcea8ff	659	__I uint32_t ADDR6;
kenjiArai	0:d4960fcea8ff	660	__I uint32_t ADDR7;
kenjiArai	0:d4960fcea8ff	661	__I uint32_t ADSTAT;
kenjiArai	0:d4960fcea8ff	662	__IO uint32_t ADTRM;
kenjiArai	0:d4960fcea8ff	663	} LPC_ADC_TypeDef;
kenjiArai	0:d4960fcea8ff	664
kenjiArai	0:d4960fcea8ff	665	/------------- Digital-to-Analog Converter (DAC) ----------------------------/
kenjiArai	0:d4960fcea8ff	666	typedef struct
kenjiArai	0:d4960fcea8ff	667	{
kenjiArai	0:d4960fcea8ff	668	__IO uint32_t DACR;
kenjiArai	0:d4960fcea8ff	669	__IO uint32_t DACCTRL;
kenjiArai	0:d4960fcea8ff	670	__IO uint16_t DACCNTVAL;
kenjiArai	0:d4960fcea8ff	671	} LPC_DAC_TypeDef;
kenjiArai	0:d4960fcea8ff	672
kenjiArai	0:d4960fcea8ff	673	/------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------/
kenjiArai	0:d4960fcea8ff	674	typedef struct
kenjiArai	0:d4960fcea8ff	675	{
kenjiArai	0:d4960fcea8ff	676	__I uint32_t MCCON;
kenjiArai	0:d4960fcea8ff	677	__O uint32_t MCCON_SET;
kenjiArai	0:d4960fcea8ff	678	__O uint32_t MCCON_CLR;
kenjiArai	0:d4960fcea8ff	679	__I uint32_t MCCAPCON;
kenjiArai	0:d4960fcea8ff	680	__O uint32_t MCCAPCON_SET;
kenjiArai	0:d4960fcea8ff	681	__O uint32_t MCCAPCON_CLR;
kenjiArai	0:d4960fcea8ff	682	__IO uint32_t MCTIM0;
kenjiArai	0:d4960fcea8ff	683	__IO uint32_t MCTIM1;
kenjiArai	0:d4960fcea8ff	684	__IO uint32_t MCTIM2;
kenjiArai	0:d4960fcea8ff	685	__IO uint32_t MCPER0;
kenjiArai	0:d4960fcea8ff	686	__IO uint32_t MCPER1;
kenjiArai	0:d4960fcea8ff	687	__IO uint32_t MCPER2;
kenjiArai	0:d4960fcea8ff	688	__IO uint32_t MCPW0;
kenjiArai	0:d4960fcea8ff	689	__IO uint32_t MCPW1;
kenjiArai	0:d4960fcea8ff	690	__IO uint32_t MCPW2;
kenjiArai	0:d4960fcea8ff	691	__IO uint32_t MCDEADTIME;
kenjiArai	0:d4960fcea8ff	692	__IO uint32_t MCCCP;
kenjiArai	0:d4960fcea8ff	693	__IO uint32_t MCCR0;
kenjiArai	0:d4960fcea8ff	694	__IO uint32_t MCCR1;
kenjiArai	0:d4960fcea8ff	695	__IO uint32_t MCCR2;
kenjiArai	0:d4960fcea8ff	696	__I uint32_t MCINTEN;
kenjiArai	0:d4960fcea8ff	697	__O uint32_t MCINTEN_SET;
kenjiArai	0:d4960fcea8ff	698	__O uint32_t MCINTEN_CLR;
kenjiArai	0:d4960fcea8ff	699	__I uint32_t MCCNTCON;
kenjiArai	0:d4960fcea8ff	700	__O uint32_t MCCNTCON_SET;
kenjiArai	0:d4960fcea8ff	701	__O uint32_t MCCNTCON_CLR;
kenjiArai	0:d4960fcea8ff	702	__I uint32_t MCINTFLAG;
kenjiArai	0:d4960fcea8ff	703	__O uint32_t MCINTFLAG_SET;
kenjiArai	0:d4960fcea8ff	704	__O uint32_t MCINTFLAG_CLR;
kenjiArai	0:d4960fcea8ff	705	__O uint32_t MCCAP_CLR;
kenjiArai	0:d4960fcea8ff	706	} LPC_MCPWM_TypeDef;
kenjiArai	0:d4960fcea8ff	707
kenjiArai	0:d4960fcea8ff	708	/------------- Quadrature Encoder Interface (QEI) ---------------------------/
kenjiArai	0:d4960fcea8ff	709	typedef struct
kenjiArai	0:d4960fcea8ff	710	{
kenjiArai	0:d4960fcea8ff	711	__O uint32_t QEICON;
kenjiArai	0:d4960fcea8ff	712	__I uint32_t QEISTAT;
kenjiArai	0:d4960fcea8ff	713	__IO uint32_t QEICONF;
kenjiArai	0:d4960fcea8ff	714	__I uint32_t QEIPOS;
kenjiArai	0:d4960fcea8ff	715	__IO uint32_t QEIMAXPOS;
kenjiArai	0:d4960fcea8ff	716	__IO uint32_t CMPOS0;
kenjiArai	0:d4960fcea8ff	717	__IO uint32_t CMPOS1;
kenjiArai	0:d4960fcea8ff	718	__IO uint32_t CMPOS2;
kenjiArai	0:d4960fcea8ff	719	__I uint32_t INXCNT;
kenjiArai	0:d4960fcea8ff	720	__IO uint32_t INXCMP;
kenjiArai	0:d4960fcea8ff	721	__IO uint32_t QEILOAD;
kenjiArai	0:d4960fcea8ff	722	__I uint32_t QEITIME;
kenjiArai	0:d4960fcea8ff	723	__I uint32_t QEIVEL;
kenjiArai	0:d4960fcea8ff	724	__I uint32_t QEICAP;
kenjiArai	0:d4960fcea8ff	725	__IO uint32_t VELCOMP;
kenjiArai	0:d4960fcea8ff	726	__IO uint32_t FILTER;
kenjiArai	0:d4960fcea8ff	727	uint32_t RESERVED0[998];
kenjiArai	0:d4960fcea8ff	728	__O uint32_t QEIIEC;
kenjiArai	0:d4960fcea8ff	729	__O uint32_t QEIIES;
kenjiArai	0:d4960fcea8ff	730	__I uint32_t QEIINTSTAT;
kenjiArai	0:d4960fcea8ff	731	__I uint32_t QEIIE;
kenjiArai	0:d4960fcea8ff	732	__O uint32_t QEICLR;
kenjiArai	0:d4960fcea8ff	733	__O uint32_t QEISET;
kenjiArai	0:d4960fcea8ff	734	} LPC_QEI_TypeDef;
kenjiArai	0:d4960fcea8ff	735
kenjiArai	0:d4960fcea8ff	736	/------------- Controller Area Network (CAN) --------------------------------/
kenjiArai	0:d4960fcea8ff	737	typedef struct
kenjiArai	0:d4960fcea8ff	738	{
kenjiArai	0:d4960fcea8ff	739	__IO uint32_t mask[512]; /* ID Masks */
kenjiArai	0:d4960fcea8ff	740	} LPC_CANAF_RAM_TypeDef;
kenjiArai	0:d4960fcea8ff	741
kenjiArai	0:d4960fcea8ff	742	typedef struct /* Acceptance Filter Registers */
kenjiArai	0:d4960fcea8ff	743	{
kenjiArai	0:d4960fcea8ff	744	__IO uint32_t AFMR;
kenjiArai	0:d4960fcea8ff	745	__IO uint32_t SFF_sa;
kenjiArai	0:d4960fcea8ff	746	__IO uint32_t SFF_GRP_sa;
kenjiArai	0:d4960fcea8ff	747	__IO uint32_t EFF_sa;
kenjiArai	0:d4960fcea8ff	748	__IO uint32_t EFF_GRP_sa;
kenjiArai	0:d4960fcea8ff	749	__IO uint32_t ENDofTable;
kenjiArai	0:d4960fcea8ff	750	__I uint32_t LUTerrAd;
kenjiArai	0:d4960fcea8ff	751	__I uint32_t LUTerr;
kenjiArai	0:d4960fcea8ff	752	__IO uint32_t FCANIE;
kenjiArai	0:d4960fcea8ff	753	__IO uint32_t FCANIC0;
kenjiArai	0:d4960fcea8ff	754	__IO uint32_t FCANIC1;
kenjiArai	0:d4960fcea8ff	755	} LPC_CANAF_TypeDef;
kenjiArai	0:d4960fcea8ff	756
kenjiArai	0:d4960fcea8ff	757	typedef struct /* Central Registers */
kenjiArai	0:d4960fcea8ff	758	{
kenjiArai	0:d4960fcea8ff	759	__I uint32_t CANTxSR;
kenjiArai	0:d4960fcea8ff	760	__I uint32_t CANRxSR;
kenjiArai	0:d4960fcea8ff	761	__I uint32_t CANMSR;
kenjiArai	0:d4960fcea8ff	762	} LPC_CANCR_TypeDef;
kenjiArai	0:d4960fcea8ff	763
kenjiArai	0:d4960fcea8ff	764	typedef struct /* Controller Registers */
kenjiArai	0:d4960fcea8ff	765	{
kenjiArai	0:d4960fcea8ff	766	__IO uint32_t MOD;
kenjiArai	0:d4960fcea8ff	767	__O uint32_t CMR;
kenjiArai	0:d4960fcea8ff	768	__IO uint32_t GSR;
kenjiArai	0:d4960fcea8ff	769	__I uint32_t ICR;
kenjiArai	0:d4960fcea8ff	770	__IO uint32_t IER;
kenjiArai	0:d4960fcea8ff	771	__IO uint32_t BTR;
kenjiArai	0:d4960fcea8ff	772	__IO uint32_t EWL;
kenjiArai	0:d4960fcea8ff	773	__I uint32_t SR;
kenjiArai	0:d4960fcea8ff	774	__IO uint32_t RFS;
kenjiArai	0:d4960fcea8ff	775	__IO uint32_t RID;
kenjiArai	0:d4960fcea8ff	776	__IO uint32_t RDA;
kenjiArai	0:d4960fcea8ff	777	__IO uint32_t RDB;
kenjiArai	0:d4960fcea8ff	778	__IO uint32_t TFI1;
kenjiArai	0:d4960fcea8ff	779	__IO uint32_t TID1;
kenjiArai	0:d4960fcea8ff	780	__IO uint32_t TDA1;
kenjiArai	0:d4960fcea8ff	781	__IO uint32_t TDB1;
kenjiArai	0:d4960fcea8ff	782	__IO uint32_t TFI2;
kenjiArai	0:d4960fcea8ff	783	__IO uint32_t TID2;
kenjiArai	0:d4960fcea8ff	784	__IO uint32_t TDA2;
kenjiArai	0:d4960fcea8ff	785	__IO uint32_t TDB2;
kenjiArai	0:d4960fcea8ff	786	__IO uint32_t TFI3;
kenjiArai	0:d4960fcea8ff	787	__IO uint32_t TID3;
kenjiArai	0:d4960fcea8ff	788	__IO uint32_t TDA3;
kenjiArai	0:d4960fcea8ff	789	__IO uint32_t TDB3;
kenjiArai	0:d4960fcea8ff	790	} LPC_CAN_TypeDef;
kenjiArai	0:d4960fcea8ff	791
kenjiArai	0:d4960fcea8ff	792	/------------- General Purpose Direct Memory Access (GPDMA) -----------------/
kenjiArai	0:d4960fcea8ff	793	typedef struct /* Common Registers */
kenjiArai	0:d4960fcea8ff	794	{
kenjiArai	0:d4960fcea8ff	795	__I uint32_t DMACIntStat;
kenjiArai	0:d4960fcea8ff	796	__I uint32_t DMACIntTCStat;
kenjiArai	0:d4960fcea8ff	797	__O uint32_t DMACIntTCClear;
kenjiArai	0:d4960fcea8ff	798	__I uint32_t DMACIntErrStat;
kenjiArai	0:d4960fcea8ff	799	__O uint32_t DMACIntErrClr;
kenjiArai	0:d4960fcea8ff	800	__I uint32_t DMACRawIntTCStat;
kenjiArai	0:d4960fcea8ff	801	__I uint32_t DMACRawIntErrStat;
kenjiArai	0:d4960fcea8ff	802	__I uint32_t DMACEnbldChns;
kenjiArai	0:d4960fcea8ff	803	__IO uint32_t DMACSoftBReq;
kenjiArai	0:d4960fcea8ff	804	__IO uint32_t DMACSoftSReq;
kenjiArai	0:d4960fcea8ff	805	__IO uint32_t DMACSoftLBReq;
kenjiArai	0:d4960fcea8ff	806	__IO uint32_t DMACSoftLSReq;
kenjiArai	0:d4960fcea8ff	807	__IO uint32_t DMACConfig;
kenjiArai	0:d4960fcea8ff	808	__IO uint32_t DMACSync;
kenjiArai	0:d4960fcea8ff	809	} LPC_GPDMA_TypeDef;
kenjiArai	0:d4960fcea8ff	810
kenjiArai	0:d4960fcea8ff	811	typedef struct /* Channel Registers */
kenjiArai	0:d4960fcea8ff	812	{
kenjiArai	0:d4960fcea8ff	813	__IO uint32_t DMACCSrcAddr;
kenjiArai	0:d4960fcea8ff	814	__IO uint32_t DMACCDestAddr;
kenjiArai	0:d4960fcea8ff	815	__IO uint32_t DMACCLLI;
kenjiArai	0:d4960fcea8ff	816	__IO uint32_t DMACCControl;
kenjiArai	0:d4960fcea8ff	817	__IO uint32_t DMACCConfig;
kenjiArai	0:d4960fcea8ff	818	} LPC_GPDMACH_TypeDef;
kenjiArai	0:d4960fcea8ff	819
kenjiArai	0:d4960fcea8ff	820	/------------- Universal Serial Bus (USB) -----------------------------------/
kenjiArai	0:d4960fcea8ff	821	typedef struct
kenjiArai	0:d4960fcea8ff	822	{
kenjiArai	0:d4960fcea8ff	823	__I uint32_t HcRevision; /* USB Host Registers */
kenjiArai	0:d4960fcea8ff	824	__IO uint32_t HcControl;
kenjiArai	0:d4960fcea8ff	825	__IO uint32_t HcCommandStatus;
kenjiArai	0:d4960fcea8ff	826	__IO uint32_t HcInterruptStatus;
kenjiArai	0:d4960fcea8ff	827	__IO uint32_t HcInterruptEnable;
kenjiArai	0:d4960fcea8ff	828	__IO uint32_t HcInterruptDisable;
kenjiArai	0:d4960fcea8ff	829	__IO uint32_t HcHCCA;
kenjiArai	0:d4960fcea8ff	830	__I uint32_t HcPeriodCurrentED;
kenjiArai	0:d4960fcea8ff	831	__IO uint32_t HcControlHeadED;
kenjiArai	0:d4960fcea8ff	832	__IO uint32_t HcControlCurrentED;
kenjiArai	0:d4960fcea8ff	833	__IO uint32_t HcBulkHeadED;
kenjiArai	0:d4960fcea8ff	834	__IO uint32_t HcBulkCurrentED;
kenjiArai	0:d4960fcea8ff	835	__I uint32_t HcDoneHead;
kenjiArai	0:d4960fcea8ff	836	__IO uint32_t HcFmInterval;
kenjiArai	0:d4960fcea8ff	837	__I uint32_t HcFmRemaining;
kenjiArai	0:d4960fcea8ff	838	__I uint32_t HcFmNumber;
kenjiArai	0:d4960fcea8ff	839	__IO uint32_t HcPeriodicStart;
kenjiArai	0:d4960fcea8ff	840	__IO uint32_t HcLSTreshold;
kenjiArai	0:d4960fcea8ff	841	__IO uint32_t HcRhDescriptorA;
kenjiArai	0:d4960fcea8ff	842	__IO uint32_t HcRhDescriptorB;
kenjiArai	0:d4960fcea8ff	843	__IO uint32_t HcRhStatus;
kenjiArai	0:d4960fcea8ff	844	__IO uint32_t HcRhPortStatus1;
kenjiArai	0:d4960fcea8ff	845	__IO uint32_t HcRhPortStatus2;
kenjiArai	0:d4960fcea8ff	846	uint32_t RESERVED0[40];
kenjiArai	0:d4960fcea8ff	847	__I uint32_t Module_ID;
kenjiArai	0:d4960fcea8ff	848
kenjiArai	0:d4960fcea8ff	849	__I uint32_t OTGIntSt; /* USB On-The-Go Registers */
kenjiArai	0:d4960fcea8ff	850	__IO uint32_t OTGIntEn;
kenjiArai	0:d4960fcea8ff	851	__O uint32_t OTGIntSet;
kenjiArai	0:d4960fcea8ff	852	__O uint32_t OTGIntClr;
kenjiArai	0:d4960fcea8ff	853	__IO uint32_t OTGStCtrl;
kenjiArai	0:d4960fcea8ff	854	__IO uint32_t OTGTmr;
kenjiArai	0:d4960fcea8ff	855	uint32_t RESERVED1[58];
kenjiArai	0:d4960fcea8ff	856
kenjiArai	0:d4960fcea8ff	857	__I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
kenjiArai	0:d4960fcea8ff	858	__IO uint32_t USBDevIntEn;
kenjiArai	0:d4960fcea8ff	859	__O uint32_t USBDevIntClr;
kenjiArai	0:d4960fcea8ff	860	__O uint32_t USBDevIntSet;
kenjiArai	0:d4960fcea8ff	861
kenjiArai	0:d4960fcea8ff	862	__O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
kenjiArai	0:d4960fcea8ff	863	__I uint32_t USBCmdData;
kenjiArai	0:d4960fcea8ff	864
kenjiArai	0:d4960fcea8ff	865	__I uint32_t USBRxData; /* USB Device Transfer Registers */
kenjiArai	0:d4960fcea8ff	866	__O uint32_t USBTxData;
kenjiArai	0:d4960fcea8ff	867	__I uint32_t USBRxPLen;
kenjiArai	0:d4960fcea8ff	868	__O uint32_t USBTxPLen;
kenjiArai	0:d4960fcea8ff	869	__IO uint32_t USBCtrl;
kenjiArai	0:d4960fcea8ff	870	__O uint32_t USBDevIntPri;
kenjiArai	0:d4960fcea8ff	871
kenjiArai	0:d4960fcea8ff	872	__I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
kenjiArai	0:d4960fcea8ff	873	__IO uint32_t USBEpIntEn;
kenjiArai	0:d4960fcea8ff	874	__O uint32_t USBEpIntClr;
kenjiArai	0:d4960fcea8ff	875	__O uint32_t USBEpIntSet;
kenjiArai	0:d4960fcea8ff	876	__O uint32_t USBEpIntPri;
kenjiArai	0:d4960fcea8ff	877
kenjiArai	0:d4960fcea8ff	878	__IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
kenjiArai	0:d4960fcea8ff	879	__O uint32_t USBEpInd;
kenjiArai	0:d4960fcea8ff	880	__IO uint32_t USBMaxPSize;
kenjiArai	0:d4960fcea8ff	881
kenjiArai	0:d4960fcea8ff	882	__I uint32_t USBDMARSt; /* USB Device DMA Registers */
kenjiArai	0:d4960fcea8ff	883	__O uint32_t USBDMARClr;
kenjiArai	0:d4960fcea8ff	884	__O uint32_t USBDMARSet;
kenjiArai	0:d4960fcea8ff	885	uint32_t RESERVED2[9];
kenjiArai	0:d4960fcea8ff	886	__IO uint32_t USBUDCAH;
kenjiArai	0:d4960fcea8ff	887	__I uint32_t USBEpDMASt;
kenjiArai	0:d4960fcea8ff	888	__O uint32_t USBEpDMAEn;
kenjiArai	0:d4960fcea8ff	889	__O uint32_t USBEpDMADis;
kenjiArai	0:d4960fcea8ff	890	__I uint32_t USBDMAIntSt;
kenjiArai	0:d4960fcea8ff	891	__IO uint32_t USBDMAIntEn;
kenjiArai	0:d4960fcea8ff	892	uint32_t RESERVED3[2];
kenjiArai	0:d4960fcea8ff	893	__I uint32_t USBEoTIntSt;
kenjiArai	0:d4960fcea8ff	894	__O uint32_t USBEoTIntClr;
kenjiArai	0:d4960fcea8ff	895	__O uint32_t USBEoTIntSet;
kenjiArai	0:d4960fcea8ff	896	__I uint32_t USBNDDRIntSt;
kenjiArai	0:d4960fcea8ff	897	__O uint32_t USBNDDRIntClr;
kenjiArai	0:d4960fcea8ff	898	__O uint32_t USBNDDRIntSet;
kenjiArai	0:d4960fcea8ff	899	__I uint32_t USBSysErrIntSt;
kenjiArai	0:d4960fcea8ff	900	__O uint32_t USBSysErrIntClr;
kenjiArai	0:d4960fcea8ff	901	__O uint32_t USBSysErrIntSet;
kenjiArai	0:d4960fcea8ff	902	uint32_t RESERVED4[15];
kenjiArai	0:d4960fcea8ff	903
kenjiArai	0:d4960fcea8ff	904	__I uint32_t I2C_RX; /* USB OTG I2C Registers */
kenjiArai	0:d4960fcea8ff	905	__O uint32_t I2C_WO;
kenjiArai	0:d4960fcea8ff	906	__I uint32_t I2C_STS;
kenjiArai	0:d4960fcea8ff	907	__IO uint32_t I2C_CTL;
kenjiArai	0:d4960fcea8ff	908	__IO uint32_t I2C_CLKHI;
kenjiArai	0:d4960fcea8ff	909	__O uint32_t I2C_CLKLO;
kenjiArai	0:d4960fcea8ff	910	uint32_t RESERVED5[823];
kenjiArai	0:d4960fcea8ff	911
kenjiArai	0:d4960fcea8ff	912	union {
kenjiArai	0:d4960fcea8ff	913	__IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
kenjiArai	0:d4960fcea8ff	914	__IO uint32_t OTGClkCtrl;
kenjiArai	0:d4960fcea8ff	915	};
kenjiArai	0:d4960fcea8ff	916	union {
kenjiArai	0:d4960fcea8ff	917	__I uint32_t USBClkSt;
kenjiArai	0:d4960fcea8ff	918	__I uint32_t OTGClkSt;
kenjiArai	0:d4960fcea8ff	919	};
kenjiArai	0:d4960fcea8ff	920	} LPC_USB_TypeDef;
kenjiArai	0:d4960fcea8ff	921
kenjiArai	0:d4960fcea8ff	922	/------------- Ethernet Media Access Controller (EMAC) ----------------------/
kenjiArai	0:d4960fcea8ff	923	typedef struct
kenjiArai	0:d4960fcea8ff	924	{
kenjiArai	0:d4960fcea8ff	925	__IO uint32_t MAC1; /* MAC Registers */
kenjiArai	0:d4960fcea8ff	926	__IO uint32_t MAC2;
kenjiArai	0:d4960fcea8ff	927	__IO uint32_t IPGT;
kenjiArai	0:d4960fcea8ff	928	__IO uint32_t IPGR;
kenjiArai	0:d4960fcea8ff	929	__IO uint32_t CLRT;
kenjiArai	0:d4960fcea8ff	930	__IO uint32_t MAXF;
kenjiArai	0:d4960fcea8ff	931	__IO uint32_t SUPP;
kenjiArai	0:d4960fcea8ff	932	__IO uint32_t TEST;
kenjiArai	0:d4960fcea8ff	933	__IO uint32_t MCFG;
kenjiArai	0:d4960fcea8ff	934	__IO uint32_t MCMD;
kenjiArai	0:d4960fcea8ff	935	__IO uint32_t MADR;
kenjiArai	0:d4960fcea8ff	936	__O uint32_t MWTD;
kenjiArai	0:d4960fcea8ff	937	__I uint32_t MRDD;
kenjiArai	0:d4960fcea8ff	938	__I uint32_t MIND;
kenjiArai	0:d4960fcea8ff	939	uint32_t RESERVED0[2];
kenjiArai	0:d4960fcea8ff	940	__IO uint32_t SA0;
kenjiArai	0:d4960fcea8ff	941	__IO uint32_t SA1;
kenjiArai	0:d4960fcea8ff	942	__IO uint32_t SA2;
kenjiArai	0:d4960fcea8ff	943	uint32_t RESERVED1[45];
kenjiArai	0:d4960fcea8ff	944	__IO uint32_t Command; /* Control Registers */
kenjiArai	0:d4960fcea8ff	945	__I uint32_t Status;
kenjiArai	0:d4960fcea8ff	946	__IO uint32_t RxDescriptor;
kenjiArai	0:d4960fcea8ff	947	__IO uint32_t RxStatus;
kenjiArai	0:d4960fcea8ff	948	__IO uint32_t RxDescriptorNumber;
kenjiArai	0:d4960fcea8ff	949	__I uint32_t RxProduceIndex;
kenjiArai	0:d4960fcea8ff	950	__IO uint32_t RxConsumeIndex;
kenjiArai	0:d4960fcea8ff	951	__IO uint32_t TxDescriptor;
kenjiArai	0:d4960fcea8ff	952	__IO uint32_t TxStatus;
kenjiArai	0:d4960fcea8ff	953	__IO uint32_t TxDescriptorNumber;
kenjiArai	0:d4960fcea8ff	954	__IO uint32_t TxProduceIndex;
kenjiArai	0:d4960fcea8ff	955	__I uint32_t TxConsumeIndex;
kenjiArai	0:d4960fcea8ff	956	uint32_t RESERVED2[10];
kenjiArai	0:d4960fcea8ff	957	__I uint32_t TSV0;
kenjiArai	0:d4960fcea8ff	958	__I uint32_t TSV1;
kenjiArai	0:d4960fcea8ff	959	__I uint32_t RSV;
kenjiArai	0:d4960fcea8ff	960	uint32_t RESERVED3[3];
kenjiArai	0:d4960fcea8ff	961	__IO uint32_t FlowControlCounter;
kenjiArai	0:d4960fcea8ff	962	__I uint32_t FlowControlStatus;
kenjiArai	0:d4960fcea8ff	963	uint32_t RESERVED4[34];
kenjiArai	0:d4960fcea8ff	964	__IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
kenjiArai	0:d4960fcea8ff	965	__IO uint32_t RxFilterWoLStatus;
kenjiArai	0:d4960fcea8ff	966	__IO uint32_t RxFilterWoLClear;
kenjiArai	0:d4960fcea8ff	967	uint32_t RESERVED5;
kenjiArai	0:d4960fcea8ff	968	__IO uint32_t HashFilterL;
kenjiArai	0:d4960fcea8ff	969	__IO uint32_t HashFilterH;
kenjiArai	0:d4960fcea8ff	970	uint32_t RESERVED6[882];
kenjiArai	0:d4960fcea8ff	971	__I uint32_t IntStatus; /* Module Control Registers */
kenjiArai	0:d4960fcea8ff	972	__IO uint32_t IntEnable;
kenjiArai	0:d4960fcea8ff	973	__O uint32_t IntClear;
kenjiArai	0:d4960fcea8ff	974	__O uint32_t IntSet;
kenjiArai	0:d4960fcea8ff	975	uint32_t RESERVED7;
kenjiArai	0:d4960fcea8ff	976	__IO uint32_t PowerDown;
kenjiArai	0:d4960fcea8ff	977	uint32_t RESERVED8;
kenjiArai	0:d4960fcea8ff	978	__IO uint32_t Module_ID;
kenjiArai	0:d4960fcea8ff	979	} LPC_EMAC_TypeDef;
kenjiArai	0:d4960fcea8ff	980
kenjiArai	0:d4960fcea8ff	981	#pragma no_anon_unions
kenjiArai	0:d4960fcea8ff	982
kenjiArai	0:d4960fcea8ff	983
kenjiArai	0:d4960fcea8ff	984	/******************************************************************************/
kenjiArai	0:d4960fcea8ff	985	/* Peripheral memory map */
kenjiArai	0:d4960fcea8ff	986	/******************************************************************************/
kenjiArai	0:d4960fcea8ff	987	/* Base addresses */
kenjiArai	0:d4960fcea8ff	988	#define LPC_FLASH_BASE (0x00000000UL)
kenjiArai	0:d4960fcea8ff	989	#define LPC_RAM_BASE (0x10000000UL)
kenjiArai	0:d4960fcea8ff	990	#define LPC_GPIO_BASE (0x2009C000UL)
kenjiArai	0:d4960fcea8ff	991	#define LPC_APB0_BASE (0x40000000UL)
kenjiArai	0:d4960fcea8ff	992	#define LPC_APB1_BASE (0x40080000UL)
kenjiArai	0:d4960fcea8ff	993	#define LPC_AHB_BASE (0x50000000UL)
kenjiArai	0:d4960fcea8ff	994	#define LPC_CM3_BASE (0xE0000000UL)
kenjiArai	0:d4960fcea8ff	995
kenjiArai	0:d4960fcea8ff	996	/* APB0 peripherals */
kenjiArai	0:d4960fcea8ff	997	#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
kenjiArai	0:d4960fcea8ff	998	#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
kenjiArai	0:d4960fcea8ff	999	#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
kenjiArai	0:d4960fcea8ff	1000	#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
kenjiArai	0:d4960fcea8ff	1001	#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
kenjiArai	0:d4960fcea8ff	1002	#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
kenjiArai	0:d4960fcea8ff	1003	#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
kenjiArai	0:d4960fcea8ff	1004	#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
kenjiArai	0:d4960fcea8ff	1005	#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
kenjiArai	0:d4960fcea8ff	1006	#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
kenjiArai	0:d4960fcea8ff	1007	#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
kenjiArai	0:d4960fcea8ff	1008	#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
kenjiArai	0:d4960fcea8ff	1009	#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
kenjiArai	0:d4960fcea8ff	1010	#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
kenjiArai	0:d4960fcea8ff	1011	#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
kenjiArai	0:d4960fcea8ff	1012	#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
kenjiArai	0:d4960fcea8ff	1013	#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
kenjiArai	0:d4960fcea8ff	1014	#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
kenjiArai	0:d4960fcea8ff	1015	#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
kenjiArai	0:d4960fcea8ff	1016
kenjiArai	0:d4960fcea8ff	1017	/* APB1 peripherals */
kenjiArai	0:d4960fcea8ff	1018	#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
kenjiArai	0:d4960fcea8ff	1019	#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
kenjiArai	0:d4960fcea8ff	1020	#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
kenjiArai	0:d4960fcea8ff	1021	#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
kenjiArai	0:d4960fcea8ff	1022	#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
kenjiArai	0:d4960fcea8ff	1023	#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
kenjiArai	0:d4960fcea8ff	1024	#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
kenjiArai	0:d4960fcea8ff	1025	#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
kenjiArai	0:d4960fcea8ff	1026	#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
kenjiArai	0:d4960fcea8ff	1027	#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
kenjiArai	0:d4960fcea8ff	1028	#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
kenjiArai	0:d4960fcea8ff	1029	#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
kenjiArai	0:d4960fcea8ff	1030
kenjiArai	0:d4960fcea8ff	1031	/* AHB peripherals */
kenjiArai	0:d4960fcea8ff	1032	#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
kenjiArai	0:d4960fcea8ff	1033	#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
kenjiArai	0:d4960fcea8ff	1034	#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
kenjiArai	0:d4960fcea8ff	1035	#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
kenjiArai	0:d4960fcea8ff	1036	#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
kenjiArai	0:d4960fcea8ff	1037	#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
kenjiArai	0:d4960fcea8ff	1038	#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
kenjiArai	0:d4960fcea8ff	1039	#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
kenjiArai	0:d4960fcea8ff	1040	#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
kenjiArai	0:d4960fcea8ff	1041	#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
kenjiArai	0:d4960fcea8ff	1042	#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
kenjiArai	0:d4960fcea8ff	1043
kenjiArai	0:d4960fcea8ff	1044	/* GPIOs */
kenjiArai	0:d4960fcea8ff	1045	#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
kenjiArai	0:d4960fcea8ff	1046	#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
kenjiArai	0:d4960fcea8ff	1047	#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
kenjiArai	0:d4960fcea8ff	1048	#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
kenjiArai	0:d4960fcea8ff	1049	#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
kenjiArai	0:d4960fcea8ff	1050
kenjiArai	0:d4960fcea8ff	1051
kenjiArai	0:d4960fcea8ff	1052	/******************************************************************************/
kenjiArai	0:d4960fcea8ff	1053	/* Peripheral declaration */
kenjiArai	0:d4960fcea8ff	1054	/******************************************************************************/
kenjiArai	0:d4960fcea8ff	1055	#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
kenjiArai	0:d4960fcea8ff	1056	#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
kenjiArai	0:d4960fcea8ff	1057	#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
kenjiArai	0:d4960fcea8ff	1058	#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
kenjiArai	0:d4960fcea8ff	1059	#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
kenjiArai	0:d4960fcea8ff	1060	#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
kenjiArai	0:d4960fcea8ff	1061	#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
kenjiArai	0:d4960fcea8ff	1062	#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
kenjiArai	0:d4960fcea8ff	1063	#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
kenjiArai	0:d4960fcea8ff	1064	#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
kenjiArai	0:d4960fcea8ff	1065	#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
kenjiArai	0:d4960fcea8ff	1066	#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
kenjiArai	0:d4960fcea8ff	1067	#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
kenjiArai	0:d4960fcea8ff	1068	#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
kenjiArai	0:d4960fcea8ff	1069	#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
kenjiArai	0:d4960fcea8ff	1070	#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
kenjiArai	0:d4960fcea8ff	1071	#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
kenjiArai	0:d4960fcea8ff	1072	#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
kenjiArai	0:d4960fcea8ff	1073	#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
kenjiArai	0:d4960fcea8ff	1074	#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
kenjiArai	0:d4960fcea8ff	1075	#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
kenjiArai	0:d4960fcea8ff	1076	#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
kenjiArai	0:d4960fcea8ff	1077	#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
kenjiArai	0:d4960fcea8ff	1078	#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
kenjiArai	0:d4960fcea8ff	1079	#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
kenjiArai	0:d4960fcea8ff	1080	#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
kenjiArai	0:d4960fcea8ff	1081	#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
kenjiArai	0:d4960fcea8ff	1082	#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
kenjiArai	0:d4960fcea8ff	1083	#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
kenjiArai	0:d4960fcea8ff	1084	#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
kenjiArai	0:d4960fcea8ff	1085	#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
kenjiArai	0:d4960fcea8ff	1086	#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
kenjiArai	0:d4960fcea8ff	1087	#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
kenjiArai	0:d4960fcea8ff	1088	#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
kenjiArai	0:d4960fcea8ff	1089	#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
kenjiArai	0:d4960fcea8ff	1090	#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
kenjiArai	0:d4960fcea8ff	1091	#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
kenjiArai	0:d4960fcea8ff	1092	#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
kenjiArai	0:d4960fcea8ff	1093	#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
kenjiArai	0:d4960fcea8ff	1094	#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
kenjiArai	0:d4960fcea8ff	1095	#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
kenjiArai	0:d4960fcea8ff	1096	#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
kenjiArai	0:d4960fcea8ff	1097	#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
kenjiArai	0:d4960fcea8ff	1098	#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
kenjiArai	0:d4960fcea8ff	1099	#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
kenjiArai	0:d4960fcea8ff	1100	#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
kenjiArai	0:d4960fcea8ff	1101	#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
kenjiArai	0:d4960fcea8ff	1102
kenjiArai	0:d4960fcea8ff	1103	#endif // __LPC17xx_H__

Repository toolbox

Export to desktop IDE

Build repository

Repository details

Type:	Program
Created:	01 Jan 2011
Imports:	289
Forks:	1
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	14

LPC17xx.h@0:d4960fcea8ff, 2011-01-01 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning