karthick B / GR-PEACH_video

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Fork of GR-PEACH_video by Renesas

drivers/vdc5/src/r_vdc5_shared_param.h@4:aeefe5171463, 2016-06-30 (annotated)

Committer:
dkato
Date:
Thu Jun 30 11:00:37 2016 +0000
Revision:
4:aeefe5171463
Parent:
0:853f5b7408a7 
Add ARGB4444 to graphics layer read format.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:853f5b7408a7 1 /*******************************************************************************
dkato 0:853f5b7408a7 2 * DISCLAIMER
dkato 0:853f5b7408a7 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:853f5b7408a7 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:853f5b7408a7 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:853f5b7408a7 6 * all applicable laws, including copyright laws.
dkato 0:853f5b7408a7 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:853f5b7408a7 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:853f5b7408a7 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:853f5b7408a7 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:853f5b7408a7 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:853f5b7408a7 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:853f5b7408a7 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:853f5b7408a7 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:853f5b7408a7 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:853f5b7408a7 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:853f5b7408a7 17 * and to discontinue the availability of this software. By using this software,
dkato 0:853f5b7408a7 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:853f5b7408a7 19 * following link:
dkato 0:853f5b7408a7 20 * http://www.renesas.com/disclaimer
dkato 0:853f5b7408a7 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
dkato 0:853f5b7408a7 22 *******************************************************************************/
dkato 0:853f5b7408a7 23 /**************************************************************************//**
dkato 0:853f5b7408a7 24 * @file r_vdc5_shared_param.h
dkato 0:853f5b7408a7 25 * @version 1.00
dkato 0:853f5b7408a7 26 * $Rev: 199 $
dkato 0:853f5b7408a7 27 * $Date:: 2014-05-23 16:33:52 +0900#$
dkato 0:853f5b7408a7 28 * @brief VDC5 driver shared parameter definitions
dkato 0:853f5b7408a7 29 ******************************************************************************/
dkato 0:853f5b7408a7 30
dkato 0:853f5b7408a7 31 #ifndef R_VDC5_SHARED_PARAM_H
dkato 0:853f5b7408a7 32 #define R_VDC5_SHARED_PARAM_H
dkato 0:853f5b7408a7 33
dkato 0:853f5b7408a7 34 /******************************************************************************
dkato 0:853f5b7408a7 35 Includes <System Includes> , "Project Includes"
dkato 0:853f5b7408a7 36 ******************************************************************************/
dkato 0:853f5b7408a7 37 #include "r_vdc5.h"
dkato 0:853f5b7408a7 38 #include "r_vdc5_user.h"
dkato 0:853f5b7408a7 39
dkato 0:853f5b7408a7 40
dkato 0:853f5b7408a7 41 /******************************************************************************
dkato 0:853f5b7408a7 42 Macro definitions
dkato 0:853f5b7408a7 43 ******************************************************************************/
dkato 0:853f5b7408a7 44
dkato 0:853f5b7408a7 45 /******************************************************************************
dkato 0:853f5b7408a7 46 Typedef definitions
dkato 0:853f5b7408a7 47 ******************************************************************************/
dkato 0:853f5b7408a7 48 /*! Color space */
dkato 0:853f5b7408a7 49 typedef enum {
dkato 0:853f5b7408a7 50 VDC5_COLOR_SPACE_GBR = 0, /*!< GBR */
dkato 0:853f5b7408a7 51 VDC5_COLOR_SPACE_YCBCR = 1 /*!< YCbCr */
dkato 0:853f5b7408a7 52 } vdc5_color_space_t;
dkato 0:853f5b7408a7 53
dkato 0:853f5b7408a7 54 /*! Resource state */
dkato 0:853f5b7408a7 55 typedef enum {
dkato 0:853f5b7408a7 56 VDC5_RESOURCE_ST_INVALID = 0, /*!< Invalid */
dkato 0:853f5b7408a7 57 VDC5_RESOURCE_ST_VALID = 1 /*!< Valid */
dkato 0:853f5b7408a7 58 } vdc5_resource_state_t;
dkato 0:853f5b7408a7 59
dkato 0:853f5b7408a7 60 /*! Resource type */
dkato 0:853f5b7408a7 61 typedef enum {
dkato 0:853f5b7408a7 62 VDC5_RESOURCE_PANEL_CLK = 0, /*!< Panel clock */
dkato 0:853f5b7408a7 63 VDC5_RESOURCE_VIDEO_IN, /*!< Input video */
dkato 0:853f5b7408a7 64 VDC5_RESOURCE_VSYNC, /*!< Vsync signal */
dkato 0:853f5b7408a7 65 VDC5_RESOURCE_LCD_PANEL, /*!< LCD panel (output video) */
dkato 0:853f5b7408a7 66 VDC5_RESOURCE_LVDS_CLK, /*!< LVDS PLL clock */
dkato 0:853f5b7408a7 67 VDC5_RESOURCE_NUM
dkato 0:853f5b7408a7 68 } vdc5_resource_type_t;
dkato 0:853f5b7408a7 69
dkato 0:853f5b7408a7 70
dkato 0:853f5b7408a7 71 /******************************************************************************
dkato 0:853f5b7408a7 72 Functions Prototypes
dkato 0:853f5b7408a7 73 ******************************************************************************/
dkato 0:853f5b7408a7 74 void VDC5_ShrdPrmInit(const vdc5_channel_t ch);
dkato 0:853f5b7408a7 75
dkato 0:853f5b7408a7 76 void VDC5_ShrdPrmSetInitParam(const vdc5_channel_t ch, const vdc5_init_t * const param);
dkato 0:853f5b7408a7 77 void VDC5_ShrdPrmSetTerminate(const vdc5_channel_t ch);
dkato 0:853f5b7408a7 78 void VDC5_ShrdPrmSetInputParam(const vdc5_channel_t ch, const vdc5_input_t * const param);
dkato 0:853f5b7408a7 79 void VDC5_ShrdPrmSetSyncParam(const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param);
dkato 0:853f5b7408a7 80 void VDC5_ShrdPrmSetOutputParam(const vdc5_channel_t ch, const vdc5_output_t * const param);
dkato 0:853f5b7408a7 81 void VDC5_ShrdPrmSetWriteParam(
dkato 0:853f5b7408a7 82 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 83 const vdc5_scaling_type_t scaling_id,
dkato 0:853f5b7408a7 84 const vdc5_write_t * const param);
dkato 0:853f5b7408a7 85 void VDC5_ShrdPrmSetChgWriteParam(
dkato 0:853f5b7408a7 86 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 87 const vdc5_scaling_type_t scaling_id,
dkato 0:853f5b7408a7 88 const vdc5_write_chg_t * const param);
dkato 0:853f5b7408a7 89 void VDC5_ShrdPrmSetReadParam(
dkato 0:853f5b7408a7 90 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 91 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 92 const vdc5_read_t * const param);
dkato 0:853f5b7408a7 93 void VDC5_ShrdPrmSetChgReadParam(
dkato 0:853f5b7408a7 94 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 95 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 96 const vdc5_read_chg_t * const param);
dkato 0:853f5b7408a7 97 void VDC5_ShrdPrmSetCascade(const vdc5_channel_t ch, const vdc5_onoff_t cascade);
dkato 0:853f5b7408a7 98 void VDC5_ShrdPrmSetUndSel(const vdc5_channel_t ch, const vdc5_onoff_t und_sel);
dkato 0:853f5b7408a7 99
dkato 0:853f5b7408a7 100 vdc5_panel_clksel_t VDC5_ShrdPrmGetPanelClkSel(const vdc5_channel_t ch);
dkato 0:853f5b7408a7 101 vdc5_onoff_t VDC5_ShrdPrmGetLvdsClkRef(void);
dkato 0:853f5b7408a7 102 vdc5_color_space_t VDC5_ShrdPrmGetColorSpace(const vdc5_channel_t ch);
dkato 0:853f5b7408a7 103 vdc5_input_sel_t VDC5_ShrdPrmGetInputSelect(const vdc5_channel_t ch);
dkato 0:853f5b7408a7 104 vdc5_res_vs_in_sel_t VDC5_ShrdPrmGetVsInSel(const vdc5_channel_t ch);
dkato 0:853f5b7408a7 105 vdc5_onoff_t VDC5_ShrdPrmGetCascade(const vdc5_channel_t ch);
dkato 0:853f5b7408a7 106 vdc5_onoff_t VDC5_ShrdPrmGetUndSel(const vdc5_channel_t ch);
dkato 0:853f5b7408a7 107 uint32_t VDC5_ShrdPrmGetBgColor(const vdc5_channel_t ch, const vdc5_color_space_t color_space);
dkato 0:853f5b7408a7 108 vdc5_wr_md_t VDC5_ShrdPrmGetWritingMode(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
dkato 0:853f5b7408a7 109 vdc5_res_inter_t VDC5_ShrdPrmGetInterlace(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
dkato 0:853f5b7408a7 110 vdc5_color_space_t VDC5_ShrdPrmGetColorSpaceFbWr(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
dkato 0:853f5b7408a7 111 void * VDC5_ShrdPrmGetFrBuffBtm(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
dkato 0:853f5b7408a7 112
dkato 0:853f5b7408a7 113 vdc5_gr_ln_off_dir_t VDC5_ShrdPrmGetLineOfsAddrDir(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
dkato 0:853f5b7408a7 114 vdc5_gr_flm_sel_t VDC5_ShrdPrmGetSelFbAddrSig(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
dkato 0:853f5b7408a7 115 vdc5_gr_format_t VDC5_ShrdPrmGetGraphicsFormat(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
dkato 0:853f5b7408a7 116 vdc5_color_space_t VDC5_ShrdPrmGetColorSpaceFbRd(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
dkato 0:853f5b7408a7 117 vdc5_onoff_t VDC5_ShrdPrmGetMeasureFolding(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
dkato 0:853f5b7408a7 118 vdc5_period_rect_t * VDC5_ShrdPrmGetDisplayArea(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
dkato 0:853f5b7408a7 119 vdc5_width_read_fb_t * VDC5_ShrdPrmGetFrBuffWidth_Rd(
dkato 0:853f5b7408a7 120 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 121 const vdc5_graphics_type_t graphics_id);
dkato 0:853f5b7408a7 122 vdc5_channel_t VDC5_ShrdPrmGetLvdsCh(void);
dkato 0:853f5b7408a7 123
dkato 0:853f5b7408a7 124 void VDC5_ShrdPrmSetResource(
dkato 0:853f5b7408a7 125 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 126 const vdc5_resource_type_t rsrc_type,
dkato 0:853f5b7408a7 127 const vdc5_resource_state_t rsrc_state);
dkato 0:853f5b7408a7 128 void VDC5_ShrdPrmSetLayerResource(
dkato 0:853f5b7408a7 129 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 130 const vdc5_layer_id_t layer_id,
dkato 0:853f5b7408a7 131 const vdc5_resource_state_t rsrc_state);
dkato 0:853f5b7408a7 132 vdc5_resource_state_t VDC5_ShrdPrmGetResource(const vdc5_channel_t ch, const vdc5_resource_type_t rsrc_type);
dkato 0:853f5b7408a7 133 vdc5_resource_state_t VDC5_ShrdPrmGetLayerResource(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
dkato 0:853f5b7408a7 134
dkato 0:853f5b7408a7 135 void VDC5_ShrdPrmSetRwProcEnable(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
dkato 0:853f5b7408a7 136 void VDC5_ShrdPrmSetRwProcDisable(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
dkato 0:853f5b7408a7 137 vdc5_resource_state_t VDC5_ShrdPrmGetRwProcReady(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
dkato 0:853f5b7408a7 138 vdc5_resource_state_t VDC5_ShrdPrmGetRwProcEnabled(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
dkato 0:853f5b7408a7 139 vdc5_resource_state_t VDC5_ShrdPrmGetOirRwProcEnabled(const vdc5_channel_t ch);
dkato 0:853f5b7408a7 140
dkato 0:853f5b7408a7 141
dkato 0:853f5b7408a7 142 #endif /* R_VDC5_SHARED_PARAM_H */
dkato 0:853f5b7408a7 143