cc y / mbed

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of mbed by mbed official

TARGET_KW41Z/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/drivers/fsl_edma.h@135:fce8a9387ed1, 2017-01-17 (annotated)

Committer:
kaoshen
Date:
Tue Jan 17 23:27:32 2017 +0000
Revision:
135:fce8a9387ed1
Parent:
133:99b5ccf27215 
333 ADS1115 ADC1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /*
<> 128:9bcdf88f62b0 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 128:9bcdf88f62b0 3 * All rights reserved.
<> 128:9bcdf88f62b0 4 *
<> 128:9bcdf88f62b0 5 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 6 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 7 *
<> 128:9bcdf88f62b0 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 128:9bcdf88f62b0 9 * of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 128:9bcdf88f62b0 12 * list of conditions and the following disclaimer in the documentation and/or
<> 128:9bcdf88f62b0 13 * other materials provided with the distribution.
<> 128:9bcdf88f62b0 14 *
<> 128:9bcdf88f62b0 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 128:9bcdf88f62b0 16 * contributors may be used to endorse or promote products derived from this
<> 128:9bcdf88f62b0 17 * software without specific prior written permission.
<> 128:9bcdf88f62b0 18 *
<> 128:9bcdf88f62b0 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 128:9bcdf88f62b0 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 128:9bcdf88f62b0 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 128:9bcdf88f62b0 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 128:9bcdf88f62b0 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 128:9bcdf88f62b0 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 128:9bcdf88f62b0 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 128:9bcdf88f62b0 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 128:9bcdf88f62b0 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 29 */
<> 128:9bcdf88f62b0 30
<> 128:9bcdf88f62b0 31 #ifndef _FSL_EDMA_H_
<> 128:9bcdf88f62b0 32 #define _FSL_EDMA_H_
<> 128:9bcdf88f62b0 33
<> 128:9bcdf88f62b0 34 #include "fsl_common.h"
<> 128:9bcdf88f62b0 35
<> 128:9bcdf88f62b0 36 /*!
<> 128:9bcdf88f62b0 37 * @addtogroup edma
<> 128:9bcdf88f62b0 38 * @{
<> 128:9bcdf88f62b0 39 */
<> 128:9bcdf88f62b0 40
<> 128:9bcdf88f62b0 41 /*******************************************************************************
<> 128:9bcdf88f62b0 42 * Definitions
<> 128:9bcdf88f62b0 43 ******************************************************************************/
<> 128:9bcdf88f62b0 44
<> 128:9bcdf88f62b0 45 /*! @name Driver version */
<> 128:9bcdf88f62b0 46 /*@{*/
<> 128:9bcdf88f62b0 47 /*! @brief eDMA driver version */
<> 128:9bcdf88f62b0 48 #define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */
<> 128:9bcdf88f62b0 49 /*@}*/
<> 128:9bcdf88f62b0 50
<> 128:9bcdf88f62b0 51 /*! @brief Compute the offset unit from DCHPRI3 */
<> 128:9bcdf88f62b0 52 #define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U)))
<> 128:9bcdf88f62b0 53
<> 128:9bcdf88f62b0 54 /*! @brief Get the pointer of DCHPRIn */
<> 128:9bcdf88f62b0 55 #define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&(base->DCHPRI3))[DMA_DCHPRI_INDEX(channel)]
<> 128:9bcdf88f62b0 56
<> 128:9bcdf88f62b0 57 /*! @brief eDMA transfer configuration */
<> 128:9bcdf88f62b0 58 typedef enum _edma_transfer_size
<> 128:9bcdf88f62b0 59 {
<> 128:9bcdf88f62b0 60 kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */
<> 128:9bcdf88f62b0 61 kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */
<> 128:9bcdf88f62b0 62 kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */
<> 128:9bcdf88f62b0 63 kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */
<> 128:9bcdf88f62b0 64 kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */
<> 128:9bcdf88f62b0 65 } edma_transfer_size_t;
<> 128:9bcdf88f62b0 66
<> 128:9bcdf88f62b0 67 /*! @brief eDMA modulo configuration */
<> 128:9bcdf88f62b0 68 typedef enum _edma_modulo
<> 128:9bcdf88f62b0 69 {
<> 128:9bcdf88f62b0 70 kEDMA_ModuloDisable = 0x0U, /*!< Disable modulo */
<> 128:9bcdf88f62b0 71 kEDMA_Modulo2bytes, /*!< Circular buffer size is 2 bytes. */
<> 128:9bcdf88f62b0 72 kEDMA_Modulo4bytes, /*!< Circular buffer size is 4 bytes. */
<> 128:9bcdf88f62b0 73 kEDMA_Modulo8bytes, /*!< Circular buffer size is 8 bytes. */
<> 128:9bcdf88f62b0 74 kEDMA_Modulo16bytes, /*!< Circular buffer size is 16 bytes. */
<> 128:9bcdf88f62b0 75 kEDMA_Modulo32bytes, /*!< Circular buffer size is 32 bytes. */
<> 128:9bcdf88f62b0 76 kEDMA_Modulo64bytes, /*!< Circular buffer size is 64 bytes. */
<> 128:9bcdf88f62b0 77 kEDMA_Modulo128bytes, /*!< Circular buffer size is 128 bytes. */
<> 128:9bcdf88f62b0 78 kEDMA_Modulo256bytes, /*!< Circular buffer size is 256 bytes. */
<> 128:9bcdf88f62b0 79 kEDMA_Modulo512bytes, /*!< Circular buffer size is 512 bytes. */
<> 128:9bcdf88f62b0 80 kEDMA_Modulo1Kbytes, /*!< Circular buffer size is 1K bytes. */
<> 128:9bcdf88f62b0 81 kEDMA_Modulo2Kbytes, /*!< Circular buffer size is 2K bytes. */
<> 128:9bcdf88f62b0 82 kEDMA_Modulo4Kbytes, /*!< Circular buffer size is 4K bytes. */
<> 128:9bcdf88f62b0 83 kEDMA_Modulo8Kbytes, /*!< Circular buffer size is 8K bytes. */
<> 128:9bcdf88f62b0 84 kEDMA_Modulo16Kbytes, /*!< Circular buffer size is 16K bytes. */
<> 128:9bcdf88f62b0 85 kEDMA_Modulo32Kbytes, /*!< Circular buffer size is 32K bytes. */
<> 128:9bcdf88f62b0 86 kEDMA_Modulo64Kbytes, /*!< Circular buffer size is 64K bytes. */
<> 128:9bcdf88f62b0 87 kEDMA_Modulo128Kbytes, /*!< Circular buffer size is 128K bytes. */
<> 128:9bcdf88f62b0 88 kEDMA_Modulo256Kbytes, /*!< Circular buffer size is 256K bytes. */
<> 128:9bcdf88f62b0 89 kEDMA_Modulo512Kbytes, /*!< Circular buffer size is 512K bytes. */
<> 128:9bcdf88f62b0 90 kEDMA_Modulo1Mbytes, /*!< Circular buffer size is 1M bytes. */
<> 128:9bcdf88f62b0 91 kEDMA_Modulo2Mbytes, /*!< Circular buffer size is 2M bytes. */
<> 128:9bcdf88f62b0 92 kEDMA_Modulo4Mbytes, /*!< Circular buffer size is 4M bytes. */
<> 128:9bcdf88f62b0 93 kEDMA_Modulo8Mbytes, /*!< Circular buffer size is 8M bytes. */
<> 128:9bcdf88f62b0 94 kEDMA_Modulo16Mbytes, /*!< Circular buffer size is 16M bytes. */
<> 128:9bcdf88f62b0 95 kEDMA_Modulo32Mbytes, /*!< Circular buffer size is 32M bytes. */
<> 128:9bcdf88f62b0 96 kEDMA_Modulo64Mbytes, /*!< Circular buffer size is 64M bytes. */
<> 128:9bcdf88f62b0 97 kEDMA_Modulo128Mbytes, /*!< Circular buffer size is 128M bytes. */
<> 128:9bcdf88f62b0 98 kEDMA_Modulo256Mbytes, /*!< Circular buffer size is 256M bytes. */
<> 128:9bcdf88f62b0 99 kEDMA_Modulo512Mbytes, /*!< Circular buffer size is 512M bytes. */
<> 128:9bcdf88f62b0 100 kEDMA_Modulo1Gbytes, /*!< Circular buffer size is 1G bytes. */
<> 128:9bcdf88f62b0 101 kEDMA_Modulo2Gbytes, /*!< Circular buffer size is 2G bytes. */
<> 128:9bcdf88f62b0 102 } edma_modulo_t;
<> 128:9bcdf88f62b0 103
<> 128:9bcdf88f62b0 104 /*! @brief Bandwidth control */
<> 128:9bcdf88f62b0 105 typedef enum _edma_bandwidth
<> 128:9bcdf88f62b0 106 {
<> 128:9bcdf88f62b0 107 kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */
<> 128:9bcdf88f62b0 108 kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */
<> 128:9bcdf88f62b0 109 kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */
<> 128:9bcdf88f62b0 110 } edma_bandwidth_t;
<> 128:9bcdf88f62b0 111
<> 128:9bcdf88f62b0 112 /*! @brief Channel link type */
<> 128:9bcdf88f62b0 113 typedef enum _edma_channel_link_type
<> 128:9bcdf88f62b0 114 {
<> 128:9bcdf88f62b0 115 kEDMA_LinkNone = 0x0U, /*!< No channel link */
<> 128:9bcdf88f62b0 116 kEDMA_MinorLink, /*!< Channel link after each minor loop */
<> 128:9bcdf88f62b0 117 kEDMA_MajorLink, /*!< Channel link while major loop count exhausted */
<> 128:9bcdf88f62b0 118 } edma_channel_link_type_t;
<> 128:9bcdf88f62b0 119
<> 128:9bcdf88f62b0 120 /*!@brief eDMA channel status flags. */
<> 128:9bcdf88f62b0 121 enum _edma_channel_status_flags
<> 128:9bcdf88f62b0 122 {
<> 128:9bcdf88f62b0 123 kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/
<> 128:9bcdf88f62b0 124 kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */
<> 128:9bcdf88f62b0 125 kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */
<> 128:9bcdf88f62b0 126 };
<> 128:9bcdf88f62b0 127
<> 128:9bcdf88f62b0 128 /*! @brief eDMA channel error status flags. */
<> 128:9bcdf88f62b0 129 enum _edma_error_status_flags
<> 128:9bcdf88f62b0 130 {
<> 128:9bcdf88f62b0 131 kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK, /*!< Bus error on destination address */
<> 128:9bcdf88f62b0 132 kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK, /*!< Bus error on the source address */
<> 128:9bcdf88f62b0 133 kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK, /*!< Error on the Scatter/Gather address, not 32byte aligned. */
<> 128:9bcdf88f62b0 134 kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK, /*!< NBYTES/CITER configuration error */
<> 128:9bcdf88f62b0 135 kEDMA_DestinationOffsetErrorFlag = DMA_ES_DOE_MASK, /*!< Destination offset not aligned with destination size */
<> 128:9bcdf88f62b0 136 kEDMA_DestinationAddressErrorFlag = DMA_ES_DAE_MASK, /*!< Destination address not aligned with destination size */
<> 128:9bcdf88f62b0 137 kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK, /*!< Source offset not aligned with source size */
<> 128:9bcdf88f62b0 138 kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK, /*!< Source address not aligned with source size*/
<> 128:9bcdf88f62b0 139 kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK, /*!< Error channel number of the cancelled channel number */
<> 128:9bcdf88f62b0 140 kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK, /*!< Channel priority is not unique. */
<> 128:9bcdf88f62b0 141 kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK, /*!< Transfer cancelled */
<> 128:9bcdf88f62b0 142 #if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1
<> 128:9bcdf88f62b0 143 kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */
<> 128:9bcdf88f62b0 144 #endif
<> 128:9bcdf88f62b0 145 kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */
<> 128:9bcdf88f62b0 146 };
<> 128:9bcdf88f62b0 147
<> 128:9bcdf88f62b0 148 /*! @brief eDMA interrupt source */
<> 128:9bcdf88f62b0 149 typedef enum _edma_interrupt_enable
<> 128:9bcdf88f62b0 150 {
<> 128:9bcdf88f62b0 151 kEDMA_ErrorInterruptEnable = 0x1U, /*!< Enable interrupt while channel error occurs. */
<> 128:9bcdf88f62b0 152 kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */
<> 128:9bcdf88f62b0 153 kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */
<> 128:9bcdf88f62b0 154 } edma_interrupt_enable_t;
<> 128:9bcdf88f62b0 155
<> 128:9bcdf88f62b0 156 /*! @brief eDMA transfer type */
<> 128:9bcdf88f62b0 157 typedef enum _edma_transfer_type
<> 128:9bcdf88f62b0 158 {
<> 128:9bcdf88f62b0 159 kEDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory */
<> 128:9bcdf88f62b0 160 kEDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory */
<> 128:9bcdf88f62b0 161 kEDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral */
<> 128:9bcdf88f62b0 162 } edma_transfer_type_t;
<> 128:9bcdf88f62b0 163
<> 128:9bcdf88f62b0 164 /*! @brief eDMA transfer status */
<> 128:9bcdf88f62b0 165 enum _edma_transfer_status
<> 128:9bcdf88f62b0 166 {
<> 128:9bcdf88f62b0 167 kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */
<> 128:9bcdf88f62b0 168 kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the
<> 128:9bcdf88f62b0 169 transfer request. */
<> 128:9bcdf88f62b0 170 };
<> 128:9bcdf88f62b0 171
<> 128:9bcdf88f62b0 172 /*! @brief eDMA global configuration structure.*/
<> 128:9bcdf88f62b0 173 typedef struct _edma_config
<> 128:9bcdf88f62b0 174 {
<> 128:9bcdf88f62b0 175 bool enableContinuousLinkMode; /*!< Enable (true) continuous link mode. Upon minor loop completion, the channel
<> 128:9bcdf88f62b0 176 activates again if that channel has a minor loop channel link enabled and
<> 128:9bcdf88f62b0 177 the link channel is itself. */
<> 128:9bcdf88f62b0 178 bool enableHaltOnError; /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set.
<> 128:9bcdf88f62b0 179 Subsequently, all service requests are ignored until the HALT bit is cleared.*/
<> 128:9bcdf88f62b0 180 bool enableRoundRobinArbitration; /*!< Enable (true) round robin channel arbitration method, or fixed priority
<> 128:9bcdf88f62b0 181 arbitration is used for channel selection */
<> 128:9bcdf88f62b0 182 bool enableDebugMode; /*!< Enable(true) eDMA debug mode. When in debug mode, the eDMA stalls the start of
<> 128:9bcdf88f62b0 183 a new channel. Executing channels are allowed to complete. */
<> 128:9bcdf88f62b0 184 } edma_config_t;
<> 128:9bcdf88f62b0 185
<> 128:9bcdf88f62b0 186 /*!
<> 128:9bcdf88f62b0 187 * @brief eDMA transfer configuration
<> 128:9bcdf88f62b0 188 *
<> 128:9bcdf88f62b0 189 * This structure configures the source/destination transfer attribute.
<> 128:9bcdf88f62b0 190 * This figure shows the eDMA's transfer model:
<> 128:9bcdf88f62b0 191 * _________________________________________________
<> 128:9bcdf88f62b0 192 * | Transfer Size | |
<> 128:9bcdf88f62b0 193 * Minor Loop |_______________| Major loop Count 1 |
<> 128:9bcdf88f62b0 194 * Bytes | Transfer Size | |
<> 128:9bcdf88f62b0 195 * ____________|_______________|____________________|--> Minor loop complete
<> 128:9bcdf88f62b0 196 * ____________________________________
<> 128:9bcdf88f62b0 197 * | | |
<> 128:9bcdf88f62b0 198 * |_______________| Major Loop Count 2 |
<> 128:9bcdf88f62b0 199 * | | |
<> 128:9bcdf88f62b0 200 * |_______________|____________________|--> Minor loop Complete
<> 128:9bcdf88f62b0 201 *
<> 128:9bcdf88f62b0 202 * ---------------------------------------------------------> Transfer complete
<> 128:9bcdf88f62b0 203 */
<> 128:9bcdf88f62b0 204 typedef struct _edma_transfer_config
<> 128:9bcdf88f62b0 205 {
<> 128:9bcdf88f62b0 206 uint32_t srcAddr; /*!< Source data address. */
<> 128:9bcdf88f62b0 207 uint32_t destAddr; /*!< Destination data address. */
<> 128:9bcdf88f62b0 208 edma_transfer_size_t srcTransferSize; /*!< Source data transfer size. */
<> 128:9bcdf88f62b0 209 edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */
<> 128:9bcdf88f62b0 210 int16_t srcOffset; /*!< Sign-extended offset applied to the current source address to
<> 128:9bcdf88f62b0 211 form the next-state value as each source read is completed. */
<> 128:9bcdf88f62b0 212 int16_t destOffset; /*!< Sign-extended offset applied to the current destination address to
<> 128:9bcdf88f62b0 213 form the next-state value as each destination write is completed. */
<> 128:9bcdf88f62b0 214 uint16_t minorLoopBytes; /*!< Bytes to transfer in a minor loop*/
<> 128:9bcdf88f62b0 215 uint32_t majorLoopCounts; /*!< Major loop iteration count. */
<> 128:9bcdf88f62b0 216 } edma_transfer_config_t;
<> 128:9bcdf88f62b0 217
<> 128:9bcdf88f62b0 218 /*! @brief eDMA channel priority configuration */
<> 128:9bcdf88f62b0 219 typedef struct _edma_channel_Preemption_config
<> 128:9bcdf88f62b0 220 {
<> 128:9bcdf88f62b0 221 bool enableChannelPreemption; /*!< If true: channel can be suspended by other channel with higher priority */
<> 128:9bcdf88f62b0 222 bool enablePreemptAbility; /*!< If true: channel can suspend other channel with low priority */
<> 128:9bcdf88f62b0 223 uint8_t channelPriority; /*!< Channel priority */
<> 128:9bcdf88f62b0 224 } edma_channel_Preemption_config_t;
<> 128:9bcdf88f62b0 225
<> 128:9bcdf88f62b0 226 /*! @brief eDMA minor offset configuration */
<> 128:9bcdf88f62b0 227 typedef struct _edma_minor_offset_config
<> 128:9bcdf88f62b0 228 {
<> 128:9bcdf88f62b0 229 bool enableSrcMinorOffset; /*!< Enable(true) or Disable(false) source minor loop offset. */
<> 128:9bcdf88f62b0 230 bool enableDestMinorOffset; /*!< Enable(true) or Disable(false) destination minor loop offset. */
<> 128:9bcdf88f62b0 231 uint32_t minorOffset; /*!< Offset for minor loop mapping. */
<> 128:9bcdf88f62b0 232 } edma_minor_offset_config_t;
<> 128:9bcdf88f62b0 233
<> 128:9bcdf88f62b0 234 /*!
<> 128:9bcdf88f62b0 235 * @brief eDMA TCD.
<> 128:9bcdf88f62b0 236 *
<> 128:9bcdf88f62b0 237 * This structure is same as TCD register which is described in reference manual,
<> 128:9bcdf88f62b0 238 * and is used to configure the scatter/gather feature as a next hardware TCD.
<> 128:9bcdf88f62b0 239 */
<> 128:9bcdf88f62b0 240 typedef struct _edma_tcd
<> 128:9bcdf88f62b0 241 {
<> 128:9bcdf88f62b0 242 __IO uint32_t SADDR; /*!< SADDR register, used to save source address */
<> 128:9bcdf88f62b0 243 __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */
<> 128:9bcdf88f62b0 244 __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */
<> 128:9bcdf88f62b0 245 __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */
<> 128:9bcdf88f62b0 246 __IO uint32_t SLAST; /*!< SLAST register */
<> 128:9bcdf88f62b0 247 __IO uint32_t DADDR; /*!< DADDR register, used for destination address */
<> 128:9bcdf88f62b0 248 __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */
<> 128:9bcdf88f62b0 249 __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/
<> 128:9bcdf88f62b0 250 __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next stcd address used in scatter-gather mode */
<> 128:9bcdf88f62b0 251 __IO uint16_t CSR; /*!< CSR register, for TCD control status */
<> 128:9bcdf88f62b0 252 __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */
<> 128:9bcdf88f62b0 253 } edma_tcd_t;
<> 128:9bcdf88f62b0 254
<> 128:9bcdf88f62b0 255 /*! @brief Callback for eDMA */
<> 128:9bcdf88f62b0 256 struct _edma_handle;
<> 128:9bcdf88f62b0 257
<> 128:9bcdf88f62b0 258 /*! @brief Define Callback function for eDMA. */
<> 128:9bcdf88f62b0 259 typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds);
<> 128:9bcdf88f62b0 260
<> 128:9bcdf88f62b0 261 /*! @brief eDMA transfer handle structure */
<> 128:9bcdf88f62b0 262 typedef struct _edma_handle
<> 128:9bcdf88f62b0 263 {
<> 128:9bcdf88f62b0 264 edma_callback callback; /*!< Callback function for major count exhausted. */
<> 128:9bcdf88f62b0 265 void *userData; /*!< Callback function parameter. */
<> 128:9bcdf88f62b0 266 DMA_Type *base; /*!< eDMA peripheral base address. */
<> 128:9bcdf88f62b0 267 edma_tcd_t *tcdPool; /*!< Pointer to memory stored TCDs. */
<> 128:9bcdf88f62b0 268 uint8_t channel; /*!< eDMA channel number. */
<> 128:9bcdf88f62b0 269 volatile int8_t header; /*!< The first TCD index. */
<> 128:9bcdf88f62b0 270 volatile int8_t tail; /*!< The last TCD index. */
<> 128:9bcdf88f62b0 271 volatile int8_t tcdUsed; /*!< The number of used TCD slots. */
<> 128:9bcdf88f62b0 272 volatile int8_t tcdSize; /*!< The total number of TCD slots in the queue. */
<> 128:9bcdf88f62b0 273 uint8_t flags; /*!< The status of the current channel. */
<> 128:9bcdf88f62b0 274 } edma_handle_t;
<> 128:9bcdf88f62b0 275
<> 128:9bcdf88f62b0 276 /*******************************************************************************
<> 128:9bcdf88f62b0 277 * APIs
<> 128:9bcdf88f62b0 278 ******************************************************************************/
<> 128:9bcdf88f62b0 279 #if defined(__cplusplus)
<> 128:9bcdf88f62b0 280 extern "C" {
<> 128:9bcdf88f62b0 281 #endif /* __cplusplus */
<> 128:9bcdf88f62b0 282
<> 128:9bcdf88f62b0 283 /*!
<> 128:9bcdf88f62b0 284 * @name eDMA initialization and De-initialization
<> 128:9bcdf88f62b0 285 * @{
<> 128:9bcdf88f62b0 286 */
<> 128:9bcdf88f62b0 287
<> 128:9bcdf88f62b0 288 /*!
<> 128:9bcdf88f62b0 289 * @brief Initializes eDMA peripheral.
<> 128:9bcdf88f62b0 290 *
<> 128:9bcdf88f62b0 291 * This function ungates the eDMA clock and configures the eDMA peripheral according
<> 128:9bcdf88f62b0 292 * to the configuration structure.
<> 128:9bcdf88f62b0 293 *
<> 128:9bcdf88f62b0 294 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 295 * @param config Pointer to configuration structure, see "edma_config_t".
<> 128:9bcdf88f62b0 296 * @note This function enable the minor loop map feature.
<> 128:9bcdf88f62b0 297 */
<> 128:9bcdf88f62b0 298 void EDMA_Init(DMA_Type *base, const edma_config_t *config);
<> 128:9bcdf88f62b0 299
<> 128:9bcdf88f62b0 300 /*!
<> 128:9bcdf88f62b0 301 * @brief Deinitializes eDMA peripheral.
<> 128:9bcdf88f62b0 302 *
<> 128:9bcdf88f62b0 303 * This function gates the eDMA clock.
<> 128:9bcdf88f62b0 304 *
<> 128:9bcdf88f62b0 305 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 306 */
<> 128:9bcdf88f62b0 307 void EDMA_Deinit(DMA_Type *base);
<> 128:9bcdf88f62b0 308
<> 128:9bcdf88f62b0 309 /*!
<> 128:9bcdf88f62b0 310 * @brief Gets the eDMA default configuration structure.
<> 128:9bcdf88f62b0 311 *
<> 128:9bcdf88f62b0 312 * This function sets the configuration structure to a default value.
<> 128:9bcdf88f62b0 313 * The default configuration is set to the following value:
<> 128:9bcdf88f62b0 314 * @code
<> 128:9bcdf88f62b0 315 * config.enableContinuousLinkMode = false;
<> 128:9bcdf88f62b0 316 * config.enableHaltOnError = true;
<> 128:9bcdf88f62b0 317 * config.enableRoundRobinArbitration = false;
<> 128:9bcdf88f62b0 318 * config.enableDebugMode = false;
<> 128:9bcdf88f62b0 319 * @endcode
<> 128:9bcdf88f62b0 320 *
<> 128:9bcdf88f62b0 321 * @param config Pointer to eDMA configuration structure.
<> 128:9bcdf88f62b0 322 */
<> 128:9bcdf88f62b0 323 void EDMA_GetDefaultConfig(edma_config_t *config);
<> 128:9bcdf88f62b0 324
<> 128:9bcdf88f62b0 325 /* @} */
<> 128:9bcdf88f62b0 326 /*!
<> 128:9bcdf88f62b0 327 * @name eDMA Channel Operation
<> 128:9bcdf88f62b0 328 * @{
<> 128:9bcdf88f62b0 329 */
<> 128:9bcdf88f62b0 330
<> 128:9bcdf88f62b0 331 /*!
<> 128:9bcdf88f62b0 332 * @brief Sets all TCD registers to a default value.
<> 128:9bcdf88f62b0 333 *
<> 128:9bcdf88f62b0 334 * This function sets TCD registers for this channel to default value.
<> 128:9bcdf88f62b0 335 *
<> 128:9bcdf88f62b0 336 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 337 * @param channel eDMA channel number.
<> 128:9bcdf88f62b0 338 * @note This function must not be called while the channel transfer is on-going,
<> 128:9bcdf88f62b0 339 * or it causes unpredictable results.
<> 128:9bcdf88f62b0 340 * @note This function enables the auto stop request feature.
<> 128:9bcdf88f62b0 341 */
<> 128:9bcdf88f62b0 342 void EDMA_ResetChannel(DMA_Type *base, uint32_t channel);
<> 128:9bcdf88f62b0 343
<> 128:9bcdf88f62b0 344 /*!
<> 128:9bcdf88f62b0 345 * @brief Configures the eDMA transfer attribute.
<> 128:9bcdf88f62b0 346 *
<> 128:9bcdf88f62b0 347 * This function configures the transfer attribute, including source address, destination address,
<> 128:9bcdf88f62b0 348 * transfer size, address offset, and so on. It also configures the scatter gather feature if the
<> 128:9bcdf88f62b0 349 * user supplies the TCD address.
<> 128:9bcdf88f62b0 350 * Example:
<> 128:9bcdf88f62b0 351 * @code
<> 128:9bcdf88f62b0 352 * edma_transfer_t config;
<> 128:9bcdf88f62b0 353 * edma_tcd_t tcd;
<> 128:9bcdf88f62b0 354 * config.srcAddr = ..;
<> 128:9bcdf88f62b0 355 * config.destAddr = ..;
<> 128:9bcdf88f62b0 356 * ...
<> 128:9bcdf88f62b0 357 * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);
<> 128:9bcdf88f62b0 358 * @endcode
<> 128:9bcdf88f62b0 359 *
<> 128:9bcdf88f62b0 360 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 361 * @param channel eDMA channel number.
<> 128:9bcdf88f62b0 362 * @param config Pointer to eDMA transfer configuration structure.
<> 128:9bcdf88f62b0 363 * @param nextTcd Point to TCD structure. It can be NULL if users
<> 128:9bcdf88f62b0 364 * do not want to enable scatter/gather feature.
<> 128:9bcdf88f62b0 365 * @note If nextTcd is not NULL, it means scatter gather feature is enabled
<> 128:9bcdf88f62b0 366 * and DREQ bit is cleared in the previous transfer configuration, which
<> 128:9bcdf88f62b0 367 * is set in eDMA_ResetChannel.
<> 128:9bcdf88f62b0 368 */
<> 128:9bcdf88f62b0 369 void EDMA_SetTransferConfig(DMA_Type *base,
<> 128:9bcdf88f62b0 370 uint32_t channel,
<> 128:9bcdf88f62b0 371 const edma_transfer_config_t *config,
<> 128:9bcdf88f62b0 372 edma_tcd_t *nextTcd);
<> 128:9bcdf88f62b0 373
<> 128:9bcdf88f62b0 374 /*!
<> 128:9bcdf88f62b0 375 * @brief Configures the eDMA minor offset feature.
<> 128:9bcdf88f62b0 376 *
<> 128:9bcdf88f62b0 377 * Minor offset means signed-extended value added to source address or destination
<> 128:9bcdf88f62b0 378 * address after each minor loop.
<> 128:9bcdf88f62b0 379 *
<> 128:9bcdf88f62b0 380 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 381 * @param channel eDMA channel number.
<> 128:9bcdf88f62b0 382 * @param config Pointer to Minor offset configuration structure.
<> 128:9bcdf88f62b0 383 */
<> 128:9bcdf88f62b0 384 void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config);
<> 128:9bcdf88f62b0 385
<> 128:9bcdf88f62b0 386 /*!
<> 128:9bcdf88f62b0 387 * @brief Configures the eDMA channel preemption feature.
<> 128:9bcdf88f62b0 388 *
<> 128:9bcdf88f62b0 389 * This function configures the channel preemption attribute and the priority of the channel.
<> 128:9bcdf88f62b0 390 *
<> 128:9bcdf88f62b0 391 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 392 * @param channel eDMA channel number
<> 128:9bcdf88f62b0 393 * @param config Pointer to channel preemption configuration structure.
<> 128:9bcdf88f62b0 394 */
<> 128:9bcdf88f62b0 395 static inline void EDMA_SetChannelPreemptionConfig(DMA_Type *base,
<> 128:9bcdf88f62b0 396 uint32_t channel,
<> 128:9bcdf88f62b0 397 const edma_channel_Preemption_config_t *config)
<> 128:9bcdf88f62b0 398 {
<> 128:9bcdf88f62b0 399 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
<> 128:9bcdf88f62b0 400 assert(config != NULL);
<> 128:9bcdf88f62b0 401
<> 128:9bcdf88f62b0 402 DMA_DCHPRIn(base, channel) =
<> 128:9bcdf88f62b0 403 (DMA_DCHPRI0_DPA(!config->enablePreemptAbility) | DMA_DCHPRI0_ECP(config->enableChannelPreemption) |
<> 128:9bcdf88f62b0 404 DMA_DCHPRI0_CHPRI(config->channelPriority));
<> 128:9bcdf88f62b0 405 }
<> 128:9bcdf88f62b0 406
<> 128:9bcdf88f62b0 407 /*!
<> 128:9bcdf88f62b0 408 * @brief Sets the channel link for the eDMA transfer.
<> 128:9bcdf88f62b0 409 *
<> 128:9bcdf88f62b0 410 * This function configures minor link or major link mode. The minor link means that the channel link is
<> 128:9bcdf88f62b0 411 * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is
<> 128:9bcdf88f62b0 412 * exhausted.
<> 128:9bcdf88f62b0 413 *
<> 128:9bcdf88f62b0 414 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 415 * @param channel eDMA channel number.
<> 128:9bcdf88f62b0 416 * @param type Channel link type, it can be one of:
<> 128:9bcdf88f62b0 417 * @arg kEDMA_LinkNone
<> 128:9bcdf88f62b0 418 * @arg kEDMA_MinorLink
<> 128:9bcdf88f62b0 419 * @arg kEDMA_MajorLink
<> 128:9bcdf88f62b0 420 * @param linkedChannel The linked channel number.
<> 128:9bcdf88f62b0 421 * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
<> 128:9bcdf88f62b0 422 */
<> 128:9bcdf88f62b0 423 void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel);
<> 128:9bcdf88f62b0 424
<> 128:9bcdf88f62b0 425 /*!
<> 128:9bcdf88f62b0 426 * @brief Sets the bandwidth for the eDMA transfer.
<> 128:9bcdf88f62b0 427 *
<> 128:9bcdf88f62b0 428 * In general, because the eDMA processes the minor loop, it continuously generates read/write sequences
<> 128:9bcdf88f62b0 429 * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of
<> 128:9bcdf88f62b0 430 * each read/write access to control the bus request bandwidth seen by the crossbar switch.
<> 128:9bcdf88f62b0 431 *
<> 128:9bcdf88f62b0 432 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 433 * @param channel eDMA channel number.
<> 128:9bcdf88f62b0 434 * @param bandWidth Bandwidth setting, it can be one of:
<> 128:9bcdf88f62b0 435 * @arg kEDMABandwidthStallNone
<> 128:9bcdf88f62b0 436 * @arg kEDMABandwidthStall4Cycle
<> 128:9bcdf88f62b0 437 * @arg kEDMABandwidthStall8Cycle
<> 128:9bcdf88f62b0 438 */
<> 128:9bcdf88f62b0 439 void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth);
<> 128:9bcdf88f62b0 440
<> 128:9bcdf88f62b0 441 /*!
<> 128:9bcdf88f62b0 442 * @brief Sets the source modulo and destination modulo for eDMA transfer.
<> 128:9bcdf88f62b0 443 *
<> 128:9bcdf88f62b0 444 * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
<> 128:9bcdf88f62b0 445 * calculation is performed or the original register value. It provides the ability to implement a circular data
<> 128:9bcdf88f62b0 446 * queue easily.
<> 128:9bcdf88f62b0 447 *
<> 128:9bcdf88f62b0 448 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 449 * @param channel eDMA channel number.
<> 128:9bcdf88f62b0 450 * @param srcModulo Source modulo value.
<> 128:9bcdf88f62b0 451 * @param destModulo Destination modulo value.
<> 128:9bcdf88f62b0 452 */
<> 128:9bcdf88f62b0 453 void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo);
<> 128:9bcdf88f62b0 454
<> 128:9bcdf88f62b0 455 #if defined(FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT) && FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT
<> 128:9bcdf88f62b0 456 /*!
<> 128:9bcdf88f62b0 457 * @brief Enables an async request for the eDMA transfer.
<> 128:9bcdf88f62b0 458 *
<> 128:9bcdf88f62b0 459 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 460 * @param channel eDMA channel number.
<> 128:9bcdf88f62b0 461 * @param enable The command for enable(ture) or disable(false).
<> 128:9bcdf88f62b0 462 */
<> 128:9bcdf88f62b0 463 static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable)
<> 128:9bcdf88f62b0 464 {
<> 128:9bcdf88f62b0 465 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
<> 128:9bcdf88f62b0 466
<> 128:9bcdf88f62b0 467 base->EARS = (base->EARS & (~(1U << channel))) | ((uint32_t)enable << channel);
<> 128:9bcdf88f62b0 468 }
<> 128:9bcdf88f62b0 469 #endif /* FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT */
<> 128:9bcdf88f62b0 470
<> 128:9bcdf88f62b0 471 /*!
<> 128:9bcdf88f62b0 472 * @brief Enables an auto stop request for the eDMA transfer.
<> 128:9bcdf88f62b0 473 *
<> 128:9bcdf88f62b0 474 * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.
<> 128:9bcdf88f62b0 475 *
<> 128:9bcdf88f62b0 476 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 477 * @param channel eDMA channel number.
<> 128:9bcdf88f62b0 478 * @param enable The command for enable (true) or disable (false).
<> 128:9bcdf88f62b0 479 */
<> 128:9bcdf88f62b0 480 static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable)
<> 128:9bcdf88f62b0 481 {
<> 128:9bcdf88f62b0 482 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
<> 128:9bcdf88f62b0 483
<> 128:9bcdf88f62b0 484 base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable);
<> 128:9bcdf88f62b0 485 }
<> 128:9bcdf88f62b0 486
<> 128:9bcdf88f62b0 487 /*!
<> 128:9bcdf88f62b0 488 * @brief Enables the interrupt source for the eDMA transfer.
<> 128:9bcdf88f62b0 489 *
<> 128:9bcdf88f62b0 490 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 491 * @param channel eDMA channel number.
<> 128:9bcdf88f62b0 492 * @param mask The mask of interrupt source to be set. Users need to use
<> 128:9bcdf88f62b0 493 * the defined edma_interrupt_enable_t type.
<> 128:9bcdf88f62b0 494 */
<> 128:9bcdf88f62b0 495 void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask);
<> 128:9bcdf88f62b0 496
<> 128:9bcdf88f62b0 497 /*!
<> 128:9bcdf88f62b0 498 * @brief Disables the interrupt source for the eDMA transfer.
<> 128:9bcdf88f62b0 499 *
<> 128:9bcdf88f62b0 500 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 501 * @param channel eDMA channel number.
<> 128:9bcdf88f62b0 502 * @param mask The mask of interrupt source to be set. Use
<> 128:9bcdf88f62b0 503 * the defined edma_interrupt_enable_t type.
<> 128:9bcdf88f62b0 504 */
<> 128:9bcdf88f62b0 505 void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask);
<> 128:9bcdf88f62b0 506
<> 128:9bcdf88f62b0 507 /* @} */
<> 128:9bcdf88f62b0 508 /*!
<> 128:9bcdf88f62b0 509 * @name eDMA TCD Operation
<> 128:9bcdf88f62b0 510 * @{
<> 128:9bcdf88f62b0 511 */
<> 128:9bcdf88f62b0 512
<> 128:9bcdf88f62b0 513 /*!
<> 128:9bcdf88f62b0 514 * @brief Sets all fields to default values for the TCD structure.
<> 128:9bcdf88f62b0 515 *
<> 128:9bcdf88f62b0 516 * This function sets all fields for this TCD structure to default value.
<> 128:9bcdf88f62b0 517 *
<> 128:9bcdf88f62b0 518 * @param tcd Pointer to the TCD structure.
<> 128:9bcdf88f62b0 519 * @note This function enables the auto stop request feature.
<> 128:9bcdf88f62b0 520 */
<> 128:9bcdf88f62b0 521 void EDMA_TcdReset(edma_tcd_t *tcd);
<> 128:9bcdf88f62b0 522
<> 128:9bcdf88f62b0 523 /*!
<> 128:9bcdf88f62b0 524 * @brief Configures the eDMA TCD transfer attribute.
<> 128:9bcdf88f62b0 525 *
<> 128:9bcdf88f62b0 526 * TCD is a transfer control descriptor. The content of the TCD is the same as hardware TCD registers.
<> 128:9bcdf88f62b0 527 * STCD is used in scatter-gather mode.
<> 128:9bcdf88f62b0 528 * This function configures the TCD transfer attribute, including source address, destination address,
<> 128:9bcdf88f62b0 529 * transfer size, address offset, and so on. It also configures the scatter gather feature if the
<> 128:9bcdf88f62b0 530 * user supplies the next TCD address.
<> 128:9bcdf88f62b0 531 * Example:
<> 128:9bcdf88f62b0 532 * @code
<> 128:9bcdf88f62b0 533 * edma_transfer_t config = {
<> 128:9bcdf88f62b0 534 * ...
<> 128:9bcdf88f62b0 535 * }
<> 128:9bcdf88f62b0 536 * edma_tcd_t tcd __aligned(32);
<> 128:9bcdf88f62b0 537 * edma_tcd_t nextTcd __aligned(32);
<> 128:9bcdf88f62b0 538 * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);
<> 128:9bcdf88f62b0 539 * @endcode
<> 128:9bcdf88f62b0 540 *
<> 128:9bcdf88f62b0 541 * @param tcd Pointer to the TCD structure.
<> 128:9bcdf88f62b0 542 * @param config Pointer to eDMA transfer configuration structure.
<> 128:9bcdf88f62b0 543 * @param nextTcd Pointer to the next TCD structure. It can be NULL if users
<> 128:9bcdf88f62b0 544 * do not want to enable scatter/gather feature.
<> 128:9bcdf88f62b0 545 * @note TCD address should be 32 bytes aligned, or it causes an eDMA error.
<> 128:9bcdf88f62b0 546 * @note If the nextTcd is not NULL, the scatter gather feature is enabled
<> 128:9bcdf88f62b0 547 * and DREQ bit is cleared in the previous transfer configuration, which
<> 128:9bcdf88f62b0 548 * is set in the EDMA_TcdReset.
<> 128:9bcdf88f62b0 549 */
<> 128:9bcdf88f62b0 550 void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd);
<> 128:9bcdf88f62b0 551
<> 128:9bcdf88f62b0 552 /*!
<> 128:9bcdf88f62b0 553 * @brief Configures the eDMA TCD minor offset feature.
<> 128:9bcdf88f62b0 554 *
<> 128:9bcdf88f62b0 555 * Minor offset is a signed-extended value added to the source address or destination
<> 128:9bcdf88f62b0 556 * address after each minor loop.
<> 128:9bcdf88f62b0 557 *
<> 128:9bcdf88f62b0 558 * @param tcd Point to the TCD structure.
<> 128:9bcdf88f62b0 559 * @param config Pointer to Minor offset configuration structure.
<> 128:9bcdf88f62b0 560 */
<> 128:9bcdf88f62b0 561 void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config);
<> 128:9bcdf88f62b0 562
<> 128:9bcdf88f62b0 563 /*!
<> 128:9bcdf88f62b0 564 * @brief Sets the channel link for eDMA TCD.
<> 128:9bcdf88f62b0 565 *
<> 128:9bcdf88f62b0 566 * This function configures either a minor link or a major link. The minor link means the channel link is
<> 128:9bcdf88f62b0 567 * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is
<> 128:9bcdf88f62b0 568 * exhausted.
<> 128:9bcdf88f62b0 569 *
<> 128:9bcdf88f62b0 570 * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
<> 128:9bcdf88f62b0 571 * @param tcd Point to the TCD structure.
<> 128:9bcdf88f62b0 572 * @param type Channel link type, it can be one of:
<> 128:9bcdf88f62b0 573 * @arg kEDMA_LinkNone
<> 128:9bcdf88f62b0 574 * @arg kEDMA_MinorLink
<> 128:9bcdf88f62b0 575 * @arg kEDMA_MajorLink
<> 128:9bcdf88f62b0 576 * @param linkedChannel The linked channel number.
<> 128:9bcdf88f62b0 577 */
<> 128:9bcdf88f62b0 578 void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel);
<> 128:9bcdf88f62b0 579
<> 128:9bcdf88f62b0 580 /*!
<> 128:9bcdf88f62b0 581 * @brief Sets the bandwidth for the eDMA TCD.
<> 128:9bcdf88f62b0 582 *
<> 128:9bcdf88f62b0 583 * In general, because the eDMA processes the minor loop, it continuously generates read/write sequences
<> 128:9bcdf88f62b0 584 * until the minor count is exhausted. Bandwidth forces the eDMA to stall after the completion of
<> 128:9bcdf88f62b0 585 * each read/write access to control the bus request bandwidth seen by the crossbar switch.
<> 128:9bcdf88f62b0 586 * @param tcd Point to the TCD structure.
<> 128:9bcdf88f62b0 587 * @param bandWidth Bandwidth setting, it can be one of:
<> 128:9bcdf88f62b0 588 * @arg kEDMABandwidthStallNone
<> 128:9bcdf88f62b0 589 * @arg kEDMABandwidthStall4Cycle
<> 128:9bcdf88f62b0 590 * @arg kEDMABandwidthStall8Cycle
<> 128:9bcdf88f62b0 591 */
<> 128:9bcdf88f62b0 592 static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth)
<> 128:9bcdf88f62b0 593 {
<> 128:9bcdf88f62b0 594 assert(tcd != NULL);
<> 128:9bcdf88f62b0 595 assert(((uint32_t)tcd & 0x1FU) == 0);
<> 128:9bcdf88f62b0 596
<> 128:9bcdf88f62b0 597 tcd->CSR = (tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth);
<> 128:9bcdf88f62b0 598 }
<> 128:9bcdf88f62b0 599
<> 128:9bcdf88f62b0 600 /*!
<> 128:9bcdf88f62b0 601 * @brief Sets the source modulo and destination modulo for eDMA TCD.
<> 128:9bcdf88f62b0 602 *
<> 128:9bcdf88f62b0 603 * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
<> 128:9bcdf88f62b0 604 * calculation is performed or the original register value. It provides the ability to implement a circular data
<> 128:9bcdf88f62b0 605 * queue easily.
<> 128:9bcdf88f62b0 606 *
<> 128:9bcdf88f62b0 607 * @param tcd Point to the TCD structure.
<> 128:9bcdf88f62b0 608 * @param srcModulo Source modulo value.
<> 128:9bcdf88f62b0 609 * @param destModulo Destination modulo value.
<> 128:9bcdf88f62b0 610 */
<> 128:9bcdf88f62b0 611 void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo);
<> 128:9bcdf88f62b0 612
<> 128:9bcdf88f62b0 613 /*!
<> 128:9bcdf88f62b0 614 * @brief Sets the auto stop request for the eDMA TCD.
<> 128:9bcdf88f62b0 615 *
<> 128:9bcdf88f62b0 616 * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.
<> 128:9bcdf88f62b0 617 *
<> 128:9bcdf88f62b0 618 * @param tcd Point to the TCD structure.
<> 128:9bcdf88f62b0 619 * @param enable The command for enable(ture) or disable(false).
<> 128:9bcdf88f62b0 620 */
<> 128:9bcdf88f62b0 621 static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable)
<> 128:9bcdf88f62b0 622 {
<> 128:9bcdf88f62b0 623 assert(tcd != NULL);
<> 128:9bcdf88f62b0 624 assert(((uint32_t)tcd & 0x1FU) == 0);
<> 128:9bcdf88f62b0 625
<> 128:9bcdf88f62b0 626 tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable);
<> 128:9bcdf88f62b0 627 }
<> 128:9bcdf88f62b0 628
<> 128:9bcdf88f62b0 629 /*!
<> 128:9bcdf88f62b0 630 * @brief Enables the interrupt source for the eDMA TCD.
<> 128:9bcdf88f62b0 631 *
<> 128:9bcdf88f62b0 632 * @param tcd Point to the TCD structure.
<> 128:9bcdf88f62b0 633 * @param mask The mask of interrupt source to be set. Users need to use
<> 128:9bcdf88f62b0 634 * the defined edma_interrupt_enable_t type.
<> 128:9bcdf88f62b0 635 */
<> 128:9bcdf88f62b0 636 void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask);
<> 128:9bcdf88f62b0 637
<> 128:9bcdf88f62b0 638 /*!
<> 128:9bcdf88f62b0 639 * @brief Disables the interrupt source for the eDMA TCD.
<> 128:9bcdf88f62b0 640 *
<> 128:9bcdf88f62b0 641 * @param tcd Point to the TCD structure.
<> 128:9bcdf88f62b0 642 * @param mask The mask of interrupt source to be set. Users need to use
<> 128:9bcdf88f62b0 643 * the defined edma_interrupt_enable_t type.
<> 128:9bcdf88f62b0 644 */
<> 128:9bcdf88f62b0 645 void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask);
<> 128:9bcdf88f62b0 646
<> 128:9bcdf88f62b0 647 /*! @} */
<> 128:9bcdf88f62b0 648 /*!
<> 128:9bcdf88f62b0 649 * @name eDMA Channel Transfer Operation
<> 128:9bcdf88f62b0 650 * @{
<> 128:9bcdf88f62b0 651 */
<> 128:9bcdf88f62b0 652
<> 128:9bcdf88f62b0 653 /*!
<> 128:9bcdf88f62b0 654 * @brief Enables the eDMA hardware channel request.
<> 128:9bcdf88f62b0 655 *
<> 128:9bcdf88f62b0 656 * This function enables the hardware channel request.
<> 128:9bcdf88f62b0 657 *
<> 128:9bcdf88f62b0 658 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 659 * @param channel eDMA channel number.
<> 128:9bcdf88f62b0 660 */
<> 128:9bcdf88f62b0 661 static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel)
<> 128:9bcdf88f62b0 662 {
<> 128:9bcdf88f62b0 663 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
<> 128:9bcdf88f62b0 664
<> 128:9bcdf88f62b0 665 base->SERQ = DMA_SERQ_SERQ(channel);
<> 128:9bcdf88f62b0 666 }
<> 128:9bcdf88f62b0 667
<> 128:9bcdf88f62b0 668 /*!
<> 128:9bcdf88f62b0 669 * @brief Disables the eDMA hardware channel request.
<> 128:9bcdf88f62b0 670 *
<> 128:9bcdf88f62b0 671 * This function disables the hardware channel request.
<> 128:9bcdf88f62b0 672 *
<> 128:9bcdf88f62b0 673 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 674 * @param channel eDMA channel number.
<> 128:9bcdf88f62b0 675 */
<> 128:9bcdf88f62b0 676 static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel)
<> 128:9bcdf88f62b0 677 {
<> 128:9bcdf88f62b0 678 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
<> 128:9bcdf88f62b0 679
<> 128:9bcdf88f62b0 680 base->CERQ = DMA_CERQ_CERQ(channel);
<> 128:9bcdf88f62b0 681 }
<> 128:9bcdf88f62b0 682
<> 128:9bcdf88f62b0 683 /*!
<> 128:9bcdf88f62b0 684 * @brief Starts the eDMA transfer by software trigger.
<> 128:9bcdf88f62b0 685 *
<> 128:9bcdf88f62b0 686 * This function starts a minor loop transfer.
<> 128:9bcdf88f62b0 687 *
<> 128:9bcdf88f62b0 688 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 689 * @param channel eDMA channel number.
<> 128:9bcdf88f62b0 690 */
<> 128:9bcdf88f62b0 691 static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel)
<> 128:9bcdf88f62b0 692 {
<> 128:9bcdf88f62b0 693 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
<> 128:9bcdf88f62b0 694
<> 128:9bcdf88f62b0 695 base->SSRT = DMA_SSRT_SSRT(channel);
<> 128:9bcdf88f62b0 696 }
<> 128:9bcdf88f62b0 697
<> 128:9bcdf88f62b0 698 /*! @} */
<> 128:9bcdf88f62b0 699 /*!
<> 128:9bcdf88f62b0 700 * @name eDMA Channel Status Operation
<> 128:9bcdf88f62b0 701 * @{
<> 128:9bcdf88f62b0 702 */
<> 128:9bcdf88f62b0 703
<> 128:9bcdf88f62b0 704 /*!
<> 128:9bcdf88f62b0 705 * @brief Gets the Remaining bytes from the eDMA current channel TCD.
<> 128:9bcdf88f62b0 706 *
<> 128:9bcdf88f62b0 707 * This function checks the TCD (Task Control Descriptor) status for a specified
<> 128:9bcdf88f62b0 708 * eDMA channel and returns the the number of bytes that have not finished.
<> 128:9bcdf88f62b0 709 *
<> 128:9bcdf88f62b0 710 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 711 * @param channel eDMA channel number.
<> 128:9bcdf88f62b0 712 * @return Bytes have not been transferred yet for the current TCD.
<> 128:9bcdf88f62b0 713 * @note This function can only be used to get unfinished bytes of transfer without
<> 128:9bcdf88f62b0 714 * the next TCD, or it might be inaccuracy.
<> 128:9bcdf88f62b0 715 */
<> 128:9bcdf88f62b0 716 uint32_t EDMA_GetRemainingBytes(DMA_Type *base, uint32_t channel);
<> 128:9bcdf88f62b0 717
<> 128:9bcdf88f62b0 718 /*!
<> 128:9bcdf88f62b0 719 * @brief Gets the eDMA channel error status flags.
<> 128:9bcdf88f62b0 720 *
<> 128:9bcdf88f62b0 721 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 722 * @return The mask of error status flags. Users need to use the
<> 128:9bcdf88f62b0 723 * _edma_error_status_flags type to decode the return variables.
<> 128:9bcdf88f62b0 724 */
<> 128:9bcdf88f62b0 725 static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base)
<> 128:9bcdf88f62b0 726 {
<> 128:9bcdf88f62b0 727 return base->ES;
<> 128:9bcdf88f62b0 728 }
<> 128:9bcdf88f62b0 729
<> 128:9bcdf88f62b0 730 /*!
<> 128:9bcdf88f62b0 731 * @brief Gets the eDMA channel status flags.
<> 128:9bcdf88f62b0 732 *
<> 128:9bcdf88f62b0 733 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 734 * @param channel eDMA channel number.
<> 128:9bcdf88f62b0 735 * @return The mask of channel status flags. Users need to use the
<> 128:9bcdf88f62b0 736 * _edma_channel_status_flags type to decode the return variables.
<> 128:9bcdf88f62b0 737 */
<> 128:9bcdf88f62b0 738 uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel);
<> 128:9bcdf88f62b0 739
<> 128:9bcdf88f62b0 740 /*!
<> 128:9bcdf88f62b0 741 * @brief Clears the eDMA channel status flags.
<> 128:9bcdf88f62b0 742 *
<> 128:9bcdf88f62b0 743 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 744 * @param channel eDMA channel number.
<> 128:9bcdf88f62b0 745 * @param mask The mask of channel status to be cleared. Users need to use
<> 128:9bcdf88f62b0 746 * the defined _edma_channel_status_flags type.
<> 128:9bcdf88f62b0 747 */
<> 128:9bcdf88f62b0 748 void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask);
<> 128:9bcdf88f62b0 749
<> 128:9bcdf88f62b0 750 /*! @} */
<> 128:9bcdf88f62b0 751 /*!
<> 128:9bcdf88f62b0 752 * @name eDMA Transactional Operation
<> 128:9bcdf88f62b0 753 */
<> 128:9bcdf88f62b0 754
<> 128:9bcdf88f62b0 755 /*!
<> 128:9bcdf88f62b0 756 * @brief Creates the eDMA handle.
<> 128:9bcdf88f62b0 757 *
<> 128:9bcdf88f62b0 758 * This function is called if using transaction API for eDMA. This function
<> 128:9bcdf88f62b0 759 * initializes the internal state of eDMA handle.
<> 128:9bcdf88f62b0 760 *
<> 128:9bcdf88f62b0 761 * @param handle eDMA handle pointer. The eDMA handle stores callback function and
<> 128:9bcdf88f62b0 762 * parameters.
<> 128:9bcdf88f62b0 763 * @param base eDMA peripheral base address.
<> 128:9bcdf88f62b0 764 * @param channel eDMA channel number.
<> 128:9bcdf88f62b0 765 */
<> 128:9bcdf88f62b0 766 void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel);
<> 128:9bcdf88f62b0 767
<> 128:9bcdf88f62b0 768 /*!
<> 128:9bcdf88f62b0 769 * @brief Installs the TCDs memory pool into eDMA handle.
<> 128:9bcdf88f62b0 770 *
<> 128:9bcdf88f62b0 771 * This function is called after the EDMA_CreateHandle to use scatter/gather feature.
<> 128:9bcdf88f62b0 772 *
<> 128:9bcdf88f62b0 773 * @param handle eDMA handle pointer.
<> 128:9bcdf88f62b0 774 * @param tcdPool Memory pool to store TCDs. It must be 32 bytes aligned.
<> 128:9bcdf88f62b0 775 * @param tcdSize The number of TCD slots.
<> 128:9bcdf88f62b0 776 */
<> 128:9bcdf88f62b0 777 void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize);
<> 128:9bcdf88f62b0 778
<> 128:9bcdf88f62b0 779 /*!
<> 128:9bcdf88f62b0 780 * @brief Installs a callback function for the eDMA transfer.
<> 128:9bcdf88f62b0 781 *
<> 128:9bcdf88f62b0 782 * This callback is called in eDMA IRQ handler. Use the callback to do something after
<> 128:9bcdf88f62b0 783 * the current major loop transfer completes.
<> 128:9bcdf88f62b0 784 *
<> 128:9bcdf88f62b0 785 * @param handle eDMA handle pointer.
<> 128:9bcdf88f62b0 786 * @param callback eDMA callback function pointer.
<> 128:9bcdf88f62b0 787 * @param userData Parameter for callback function.
<> 128:9bcdf88f62b0 788 */
<> 128:9bcdf88f62b0 789 void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData);
<> 128:9bcdf88f62b0 790
<> 128:9bcdf88f62b0 791 /*!
<> 128:9bcdf88f62b0 792 * @brief Prepares the eDMA transfer structure.
<> 128:9bcdf88f62b0 793 *
<> 128:9bcdf88f62b0 794 * This function prepares the transfer configuration structure according to the user input.
<> 128:9bcdf88f62b0 795 *
<> 128:9bcdf88f62b0 796 * @param config The user configuration structure of type edma_transfer_t.
<> 128:9bcdf88f62b0 797 * @param srcAddr eDMA transfer source address.
<> 128:9bcdf88f62b0 798 * @param srcWidth eDMA transfer source address width(bytes).
<> 128:9bcdf88f62b0 799 * @param destAddr eDMA transfer destination address.
<> 128:9bcdf88f62b0 800 * @param destWidth eDMA transfer destination address width(bytes).
<> 128:9bcdf88f62b0 801 * @param bytesEachRequest eDMA transfer bytes per channel request.
<> 128:9bcdf88f62b0 802 * @param transferBytes eDMA transfer bytes to be transferred.
<> 128:9bcdf88f62b0 803 * @param type eDMA transfer type.
<> 128:9bcdf88f62b0 804 * @note The data address and the data width must be consistent. For example, if the SRC
<> 128:9bcdf88f62b0 805 * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in
<> 128:9bcdf88f62b0 806 * source address error(SAE).
<> 128:9bcdf88f62b0 807 */
<> 128:9bcdf88f62b0 808 void EDMA_PrepareTransfer(edma_transfer_config_t *config,
<> 128:9bcdf88f62b0 809 void *srcAddr,
<> 128:9bcdf88f62b0 810 uint32_t srcWidth,
<> 128:9bcdf88f62b0 811 void *destAddr,
<> 128:9bcdf88f62b0 812 uint32_t destWidth,
<> 128:9bcdf88f62b0 813 uint32_t bytesEachRequest,
<> 128:9bcdf88f62b0 814 uint32_t transferBytes,
<> 128:9bcdf88f62b0 815 edma_transfer_type_t type);
<> 128:9bcdf88f62b0 816
<> 128:9bcdf88f62b0 817 /*!
<> 128:9bcdf88f62b0 818 * @brief Submits the eDMA transfer request.
<> 128:9bcdf88f62b0 819 *
<> 128:9bcdf88f62b0 820 * This function submits the eDMA transfer request according to the transfer configuration structure.
<> 128:9bcdf88f62b0 821 * If the user submits the transfer request repeatedly, this function packs an unprocessed request as
<> 128:9bcdf88f62b0 822 * a TCD and enables scatter/gather feature to process it in the next time.
<> 128:9bcdf88f62b0 823 *
<> 128:9bcdf88f62b0 824 * @param handle eDMA handle pointer.
<> 128:9bcdf88f62b0 825 * @param config Pointer to eDMA transfer configuration structure.
<> 128:9bcdf88f62b0 826 * @retval kStatus_EDMA_Success It means submit transfer request succeed.
<> 128:9bcdf88f62b0 827 * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
<> 128:9bcdf88f62b0 828 * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later.
<> 128:9bcdf88f62b0 829 */
<> 128:9bcdf88f62b0 830 status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config);
<> 128:9bcdf88f62b0 831
<> 128:9bcdf88f62b0 832 /*!
<> 128:9bcdf88f62b0 833 * @brief eDMA start transfer.
<> 128:9bcdf88f62b0 834 *
<> 128:9bcdf88f62b0 835 * This function enables the channel request. Users can call this function after submitting the transfer request
<> 128:9bcdf88f62b0 836 * or before submitting the transfer request.
<> 128:9bcdf88f62b0 837 *
<> 128:9bcdf88f62b0 838 * @param handle eDMA handle pointer.
<> 128:9bcdf88f62b0 839 */
<> 128:9bcdf88f62b0 840 void EDMA_StartTransfer(edma_handle_t *handle);
<> 128:9bcdf88f62b0 841
<> 128:9bcdf88f62b0 842 /*!
<> 128:9bcdf88f62b0 843 * @brief eDMA stop transfer.
<> 128:9bcdf88f62b0 844 *
<> 128:9bcdf88f62b0 845 * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer()
<> 128:9bcdf88f62b0 846 * again to resume the transfer.
<> 128:9bcdf88f62b0 847 *
<> 128:9bcdf88f62b0 848 * @param handle eDMA handle pointer.
<> 128:9bcdf88f62b0 849 */
<> 128:9bcdf88f62b0 850 void EDMA_StopTransfer(edma_handle_t *handle);
<> 128:9bcdf88f62b0 851
<> 128:9bcdf88f62b0 852 /*!
<> 128:9bcdf88f62b0 853 * @brief eDMA abort transfer.
<> 128:9bcdf88f62b0 854 *
<> 128:9bcdf88f62b0 855 * This function disables the channel request and clear transfer status bits.
<> 128:9bcdf88f62b0 856 * Users can submit another transfer after calling this API.
<> 128:9bcdf88f62b0 857 *
<> 128:9bcdf88f62b0 858 * @param handle DMA handle pointer.
<> 128:9bcdf88f62b0 859 */
<> 128:9bcdf88f62b0 860 void EDMA_AbortTransfer(edma_handle_t *handle);
<> 128:9bcdf88f62b0 861
<> 128:9bcdf88f62b0 862 /*!
<> 128:9bcdf88f62b0 863 * @brief eDMA IRQ handler for current major loop transfer complete.
<> 128:9bcdf88f62b0 864 *
<> 128:9bcdf88f62b0 865 * This function clears the channel major interrupt flag and call
<> 128:9bcdf88f62b0 866 * the callback function if it is not NULL.
<> 128:9bcdf88f62b0 867 *
<> 128:9bcdf88f62b0 868 * @param handle eDMA handle pointer.
<> 128:9bcdf88f62b0 869 */
<> 128:9bcdf88f62b0 870 void EDMA_HandleIRQ(edma_handle_t *handle);
<> 128:9bcdf88f62b0 871
<> 128:9bcdf88f62b0 872 /* @} */
<> 128:9bcdf88f62b0 873
<> 128:9bcdf88f62b0 874 #if defined(__cplusplus)
<> 128:9bcdf88f62b0 875 }
<> 128:9bcdf88f62b0 876 #endif /* __cplusplus */
<> 128:9bcdf88f62b0 877
<> 128:9bcdf88f62b0 878 /* @} */
<> 128:9bcdf88f62b0 879
<> 128:9bcdf88f62b0 880 #endif /*_FSL_EDMA_H_*/