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TARGET_EFM32LG_STK3600/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_aes.h@128:9bcdf88f62b0, 2016-10-27 (annotated)

Committer:
<>
Date:
Thu Oct 27 16:45:56 2016 +0100
Revision:
128:9bcdf88f62b0
Release 128 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



2966: Add kw24 support https://github.com/ARMmbed/mbed-os/pull/2966

3068: MultiTech mDot - clean up PeripheralPins.c and add new pin names https://github.com/ARMmbed/mbed-os/pull/3068

3089: Kinetis HAL: Remove clock initialization code from serial and ticker  https://github.com/ARMmbed/mbed-os/pull/3089

2943: [NRF5] NVIC_SetVector functionality https://github.com/ARMmbed/mbed-os/pull/2943

2938: InterruptIn changes in NCS36510 HAL. https://github.com/ARMmbed/mbed-os/pull/2938

3108: Fix sleep function for NRF52. https://github.com/ARMmbed/mbed-os/pull/3108

3076: STM32F1: Correct timer master value reading https://github.com/ARMmbed/mbed-os/pull/3076

3085: Add LOWPOWERTIMER capability for NUCLEO_F303ZE https://github.com/ARMmbed/mbed-os/pull/3085

3046: [BEETLE] Update BLE stack on Beetle board https://github.com/ARMmbed/mbed-os/pull/3046

3122: [Silicon Labs] Update of Silicon Labs HAL https://github.com/ARMmbed/mbed-os/pull/3122

3022: OnSemi RAM usage fix https://github.com/ARMmbed/mbed-os/pull/3022

3121: STM32F3: Correct UART4 and UART5 defines when using DEVICE_SERIAL_ASYNCH https://github.com/ARMmbed/mbed-os/pull/3121

3142: Targets- NUMAKER_PFM_NUC47216 remove mbed 2 https://github.com/ARMmbed/mbed-os/pull/3142

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**************************************************************************//**
<> 128:9bcdf88f62b0 2 * @file efm32lg_aes.h
<> 128:9bcdf88f62b0 3 * @brief EFM32LG_AES register and bit field definitions
<> 128:9bcdf88f62b0 4 * @version 5.0.0
<> 128:9bcdf88f62b0 5 ******************************************************************************
<> 128:9bcdf88f62b0 6 * @section License
<> 128:9bcdf88f62b0 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 *
<> 128:9bcdf88f62b0 10 * Permission is granted to anyone to use this software for any purpose,
<> 128:9bcdf88f62b0 11 * including commercial applications, and to alter it and redistribute it
<> 128:9bcdf88f62b0 12 * freely, subject to the following restrictions:
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 * 1. The origin of this software must not be misrepresented; you must not
<> 128:9bcdf88f62b0 15 * claim that you wrote the original software.@n
<> 128:9bcdf88f62b0 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 128:9bcdf88f62b0 17 * misrepresented as being the original software.@n
<> 128:9bcdf88f62b0 18 * 3. This notice may not be removed or altered from any source distribution.
<> 128:9bcdf88f62b0 19 *
<> 128:9bcdf88f62b0 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 128:9bcdf88f62b0 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 128:9bcdf88f62b0 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 128:9bcdf88f62b0 23 * kind, including, but not limited to, any implied warranties of
<> 128:9bcdf88f62b0 24 * merchantability or fitness for any particular purpose or warranties against
<> 128:9bcdf88f62b0 25 * infringement of any proprietary rights of a third party.
<> 128:9bcdf88f62b0 26 *
<> 128:9bcdf88f62b0 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 128:9bcdf88f62b0 28 * incidental, or special damages, or any other relief, or for any claim by
<> 128:9bcdf88f62b0 29 * any third party, arising from your use of this Software.
<> 128:9bcdf88f62b0 30 *
<> 128:9bcdf88f62b0 31 *****************************************************************************/
<> 128:9bcdf88f62b0 32 /**************************************************************************//**
<> 128:9bcdf88f62b0 33 * @addtogroup Parts
<> 128:9bcdf88f62b0 34 * @{
<> 128:9bcdf88f62b0 35 ******************************************************************************/
<> 128:9bcdf88f62b0 36 /**************************************************************************//**
<> 128:9bcdf88f62b0 37 * @defgroup EFM32LG_AES
<> 128:9bcdf88f62b0 38 * @{
<> 128:9bcdf88f62b0 39 * @brief EFM32LG_AES Register Declaration
<> 128:9bcdf88f62b0 40 *****************************************************************************/
<> 128:9bcdf88f62b0 41 typedef struct
<> 128:9bcdf88f62b0 42 {
<> 128:9bcdf88f62b0 43 __IOM uint32_t CTRL; /**< Control Register */
<> 128:9bcdf88f62b0 44 __IOM uint32_t CMD; /**< Command Register */
<> 128:9bcdf88f62b0 45 __IM uint32_t STATUS; /**< Status Register */
<> 128:9bcdf88f62b0 46 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 128:9bcdf88f62b0 47 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 128:9bcdf88f62b0 48 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 128:9bcdf88f62b0 49 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 128:9bcdf88f62b0 50 __IOM uint32_t DATA; /**< DATA Register */
<> 128:9bcdf88f62b0 51 __IOM uint32_t XORDATA; /**< XORDATA Register */
<> 128:9bcdf88f62b0 52 uint32_t RESERVED0[3]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 53 __IOM uint32_t KEYLA; /**< KEY Low Register */
<> 128:9bcdf88f62b0 54 __IOM uint32_t KEYLB; /**< KEY Low Register */
<> 128:9bcdf88f62b0 55 __IOM uint32_t KEYLC; /**< KEY Low Register */
<> 128:9bcdf88f62b0 56 __IOM uint32_t KEYLD; /**< KEY Low Register */
<> 128:9bcdf88f62b0 57 __IOM uint32_t KEYHA; /**< KEY High Register */
<> 128:9bcdf88f62b0 58 __IOM uint32_t KEYHB; /**< KEY High Register */
<> 128:9bcdf88f62b0 59 __IOM uint32_t KEYHC; /**< KEY High Register */
<> 128:9bcdf88f62b0 60 __IOM uint32_t KEYHD; /**< KEY High Register */
<> 128:9bcdf88f62b0 61 } AES_TypeDef; /** @} */
<> 128:9bcdf88f62b0 62
<> 128:9bcdf88f62b0 63 /**************************************************************************//**
<> 128:9bcdf88f62b0 64 * @defgroup EFM32LG_AES_BitFields
<> 128:9bcdf88f62b0 65 * @{
<> 128:9bcdf88f62b0 66 *****************************************************************************/
<> 128:9bcdf88f62b0 67
<> 128:9bcdf88f62b0 68 /* Bit fields for AES CTRL */
<> 128:9bcdf88f62b0 69 #define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */
<> 128:9bcdf88f62b0 70 #define _AES_CTRL_MASK 0x00000077UL /**< Mask for AES_CTRL */
<> 128:9bcdf88f62b0 71 #define AES_CTRL_DECRYPT (0x1UL << 0) /**< Decryption/Encryption Mode */
<> 128:9bcdf88f62b0 72 #define _AES_CTRL_DECRYPT_SHIFT 0 /**< Shift value for AES_DECRYPT */
<> 128:9bcdf88f62b0 73 #define _AES_CTRL_DECRYPT_MASK 0x1UL /**< Bit mask for AES_DECRYPT */
<> 128:9bcdf88f62b0 74 #define _AES_CTRL_DECRYPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
<> 128:9bcdf88f62b0 75 #define AES_CTRL_DECRYPT_DEFAULT (_AES_CTRL_DECRYPT_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */
<> 128:9bcdf88f62b0 76 #define AES_CTRL_AES256 (0x1UL << 1) /**< AES-256 Mode */
<> 128:9bcdf88f62b0 77 #define _AES_CTRL_AES256_SHIFT 1 /**< Shift value for AES_AES256 */
<> 128:9bcdf88f62b0 78 #define _AES_CTRL_AES256_MASK 0x2UL /**< Bit mask for AES_AES256 */
<> 128:9bcdf88f62b0 79 #define _AES_CTRL_AES256_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
<> 128:9bcdf88f62b0 80 #define AES_CTRL_AES256_DEFAULT (_AES_CTRL_AES256_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */
<> 128:9bcdf88f62b0 81 #define AES_CTRL_KEYBUFEN (0x1UL << 2) /**< Key Buffer Enable */
<> 128:9bcdf88f62b0 82 #define _AES_CTRL_KEYBUFEN_SHIFT 2 /**< Shift value for AES_KEYBUFEN */
<> 128:9bcdf88f62b0 83 #define _AES_CTRL_KEYBUFEN_MASK 0x4UL /**< Bit mask for AES_KEYBUFEN */
<> 128:9bcdf88f62b0 84 #define _AES_CTRL_KEYBUFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
<> 128:9bcdf88f62b0 85 #define AES_CTRL_KEYBUFEN_DEFAULT (_AES_CTRL_KEYBUFEN_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */
<> 128:9bcdf88f62b0 86 #define AES_CTRL_DATASTART (0x1UL << 4) /**< AES_DATA Write Start */
<> 128:9bcdf88f62b0 87 #define _AES_CTRL_DATASTART_SHIFT 4 /**< Shift value for AES_DATASTART */
<> 128:9bcdf88f62b0 88 #define _AES_CTRL_DATASTART_MASK 0x10UL /**< Bit mask for AES_DATASTART */
<> 128:9bcdf88f62b0 89 #define _AES_CTRL_DATASTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
<> 128:9bcdf88f62b0 90 #define AES_CTRL_DATASTART_DEFAULT (_AES_CTRL_DATASTART_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */
<> 128:9bcdf88f62b0 91 #define AES_CTRL_XORSTART (0x1UL << 5) /**< AES_XORDATA Write Start */
<> 128:9bcdf88f62b0 92 #define _AES_CTRL_XORSTART_SHIFT 5 /**< Shift value for AES_XORSTART */
<> 128:9bcdf88f62b0 93 #define _AES_CTRL_XORSTART_MASK 0x20UL /**< Bit mask for AES_XORSTART */
<> 128:9bcdf88f62b0 94 #define _AES_CTRL_XORSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
<> 128:9bcdf88f62b0 95 #define AES_CTRL_XORSTART_DEFAULT (_AES_CTRL_XORSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_CTRL */
<> 128:9bcdf88f62b0 96 #define AES_CTRL_BYTEORDER (0x1UL << 6) /**< Configure byte order in data and key registers */
<> 128:9bcdf88f62b0 97 #define _AES_CTRL_BYTEORDER_SHIFT 6 /**< Shift value for AES_BYTEORDER */
<> 128:9bcdf88f62b0 98 #define _AES_CTRL_BYTEORDER_MASK 0x40UL /**< Bit mask for AES_BYTEORDER */
<> 128:9bcdf88f62b0 99 #define _AES_CTRL_BYTEORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
<> 128:9bcdf88f62b0 100 #define AES_CTRL_BYTEORDER_DEFAULT (_AES_CTRL_BYTEORDER_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_CTRL */
<> 128:9bcdf88f62b0 101
<> 128:9bcdf88f62b0 102 /* Bit fields for AES CMD */
<> 128:9bcdf88f62b0 103 #define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */
<> 128:9bcdf88f62b0 104 #define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */
<> 128:9bcdf88f62b0 105 #define AES_CMD_START (0x1UL << 0) /**< Encryption/Decryption Start */
<> 128:9bcdf88f62b0 106 #define _AES_CMD_START_SHIFT 0 /**< Shift value for AES_START */
<> 128:9bcdf88f62b0 107 #define _AES_CMD_START_MASK 0x1UL /**< Bit mask for AES_START */
<> 128:9bcdf88f62b0 108 #define _AES_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */
<> 128:9bcdf88f62b0 109 #define AES_CMD_START_DEFAULT (_AES_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */
<> 128:9bcdf88f62b0 110 #define AES_CMD_STOP (0x1UL << 1) /**< Encryption/Decryption Stop */
<> 128:9bcdf88f62b0 111 #define _AES_CMD_STOP_SHIFT 1 /**< Shift value for AES_STOP */
<> 128:9bcdf88f62b0 112 #define _AES_CMD_STOP_MASK 0x2UL /**< Bit mask for AES_STOP */
<> 128:9bcdf88f62b0 113 #define _AES_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */
<> 128:9bcdf88f62b0 114 #define AES_CMD_STOP_DEFAULT (_AES_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */
<> 128:9bcdf88f62b0 115
<> 128:9bcdf88f62b0 116 /* Bit fields for AES STATUS */
<> 128:9bcdf88f62b0 117 #define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */
<> 128:9bcdf88f62b0 118 #define _AES_STATUS_MASK 0x00000001UL /**< Mask for AES_STATUS */
<> 128:9bcdf88f62b0 119 #define AES_STATUS_RUNNING (0x1UL << 0) /**< AES Running */
<> 128:9bcdf88f62b0 120 #define _AES_STATUS_RUNNING_SHIFT 0 /**< Shift value for AES_RUNNING */
<> 128:9bcdf88f62b0 121 #define _AES_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for AES_RUNNING */
<> 128:9bcdf88f62b0 122 #define _AES_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */
<> 128:9bcdf88f62b0 123 #define AES_STATUS_RUNNING_DEFAULT (_AES_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */
<> 128:9bcdf88f62b0 124
<> 128:9bcdf88f62b0 125 /* Bit fields for AES IEN */
<> 128:9bcdf88f62b0 126 #define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */
<> 128:9bcdf88f62b0 127 #define _AES_IEN_MASK 0x00000001UL /**< Mask for AES_IEN */
<> 128:9bcdf88f62b0 128 #define AES_IEN_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Enable */
<> 128:9bcdf88f62b0 129 #define _AES_IEN_DONE_SHIFT 0 /**< Shift value for AES_DONE */
<> 128:9bcdf88f62b0 130 #define _AES_IEN_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
<> 128:9bcdf88f62b0 131 #define _AES_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */
<> 128:9bcdf88f62b0 132 #define AES_IEN_DONE_DEFAULT (_AES_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */
<> 128:9bcdf88f62b0 133
<> 128:9bcdf88f62b0 134 /* Bit fields for AES IF */
<> 128:9bcdf88f62b0 135 #define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */
<> 128:9bcdf88f62b0 136 #define _AES_IF_MASK 0x00000001UL /**< Mask for AES_IF */
<> 128:9bcdf88f62b0 137 #define AES_IF_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag */
<> 128:9bcdf88f62b0 138 #define _AES_IF_DONE_SHIFT 0 /**< Shift value for AES_DONE */
<> 128:9bcdf88f62b0 139 #define _AES_IF_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
<> 128:9bcdf88f62b0 140 #define _AES_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */
<> 128:9bcdf88f62b0 141 #define AES_IF_DONE_DEFAULT (_AES_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */
<> 128:9bcdf88f62b0 142
<> 128:9bcdf88f62b0 143 /* Bit fields for AES IFS */
<> 128:9bcdf88f62b0 144 #define _AES_IFS_RESETVALUE 0x00000000UL /**< Default value for AES_IFS */
<> 128:9bcdf88f62b0 145 #define _AES_IFS_MASK 0x00000001UL /**< Mask for AES_IFS */
<> 128:9bcdf88f62b0 146 #define AES_IFS_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag Set */
<> 128:9bcdf88f62b0 147 #define _AES_IFS_DONE_SHIFT 0 /**< Shift value for AES_DONE */
<> 128:9bcdf88f62b0 148 #define _AES_IFS_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
<> 128:9bcdf88f62b0 149 #define _AES_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFS */
<> 128:9bcdf88f62b0 150 #define AES_IFS_DONE_DEFAULT (_AES_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFS */
<> 128:9bcdf88f62b0 151
<> 128:9bcdf88f62b0 152 /* Bit fields for AES IFC */
<> 128:9bcdf88f62b0 153 #define _AES_IFC_RESETVALUE 0x00000000UL /**< Default value for AES_IFC */
<> 128:9bcdf88f62b0 154 #define _AES_IFC_MASK 0x00000001UL /**< Mask for AES_IFC */
<> 128:9bcdf88f62b0 155 #define AES_IFC_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag Clear */
<> 128:9bcdf88f62b0 156 #define _AES_IFC_DONE_SHIFT 0 /**< Shift value for AES_DONE */
<> 128:9bcdf88f62b0 157 #define _AES_IFC_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
<> 128:9bcdf88f62b0 158 #define _AES_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFC */
<> 128:9bcdf88f62b0 159 #define AES_IFC_DONE_DEFAULT (_AES_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFC */
<> 128:9bcdf88f62b0 160
<> 128:9bcdf88f62b0 161 /* Bit fields for AES DATA */
<> 128:9bcdf88f62b0 162 #define _AES_DATA_RESETVALUE 0x00000000UL /**< Default value for AES_DATA */
<> 128:9bcdf88f62b0 163 #define _AES_DATA_MASK 0xFFFFFFFFUL /**< Mask for AES_DATA */
<> 128:9bcdf88f62b0 164 #define _AES_DATA_DATA_SHIFT 0 /**< Shift value for AES_DATA */
<> 128:9bcdf88f62b0 165 #define _AES_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_DATA */
<> 128:9bcdf88f62b0 166 #define _AES_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_DATA */
<> 128:9bcdf88f62b0 167 #define AES_DATA_DATA_DEFAULT (_AES_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_DATA */
<> 128:9bcdf88f62b0 168
<> 128:9bcdf88f62b0 169 /* Bit fields for AES XORDATA */
<> 128:9bcdf88f62b0 170 #define _AES_XORDATA_RESETVALUE 0x00000000UL /**< Default value for AES_XORDATA */
<> 128:9bcdf88f62b0 171 #define _AES_XORDATA_MASK 0xFFFFFFFFUL /**< Mask for AES_XORDATA */
<> 128:9bcdf88f62b0 172 #define _AES_XORDATA_XORDATA_SHIFT 0 /**< Shift value for AES_XORDATA */
<> 128:9bcdf88f62b0 173 #define _AES_XORDATA_XORDATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_XORDATA */
<> 128:9bcdf88f62b0 174 #define _AES_XORDATA_XORDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_XORDATA */
<> 128:9bcdf88f62b0 175 #define AES_XORDATA_XORDATA_DEFAULT (_AES_XORDATA_XORDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_XORDATA */
<> 128:9bcdf88f62b0 176
<> 128:9bcdf88f62b0 177 /* Bit fields for AES KEYLA */
<> 128:9bcdf88f62b0 178 #define _AES_KEYLA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLA */
<> 128:9bcdf88f62b0 179 #define _AES_KEYLA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLA */
<> 128:9bcdf88f62b0 180 #define _AES_KEYLA_KEYLA_SHIFT 0 /**< Shift value for AES_KEYLA */
<> 128:9bcdf88f62b0 181 #define _AES_KEYLA_KEYLA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLA */
<> 128:9bcdf88f62b0 182 #define _AES_KEYLA_KEYLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLA */
<> 128:9bcdf88f62b0 183 #define AES_KEYLA_KEYLA_DEFAULT (_AES_KEYLA_KEYLA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLA */
<> 128:9bcdf88f62b0 184
<> 128:9bcdf88f62b0 185 /* Bit fields for AES KEYLB */
<> 128:9bcdf88f62b0 186 #define _AES_KEYLB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLB */
<> 128:9bcdf88f62b0 187 #define _AES_KEYLB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLB */
<> 128:9bcdf88f62b0 188 #define _AES_KEYLB_KEYLB_SHIFT 0 /**< Shift value for AES_KEYLB */
<> 128:9bcdf88f62b0 189 #define _AES_KEYLB_KEYLB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLB */
<> 128:9bcdf88f62b0 190 #define _AES_KEYLB_KEYLB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLB */
<> 128:9bcdf88f62b0 191 #define AES_KEYLB_KEYLB_DEFAULT (_AES_KEYLB_KEYLB_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLB */
<> 128:9bcdf88f62b0 192
<> 128:9bcdf88f62b0 193 /* Bit fields for AES KEYLC */
<> 128:9bcdf88f62b0 194 #define _AES_KEYLC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLC */
<> 128:9bcdf88f62b0 195 #define _AES_KEYLC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLC */
<> 128:9bcdf88f62b0 196 #define _AES_KEYLC_KEYLC_SHIFT 0 /**< Shift value for AES_KEYLC */
<> 128:9bcdf88f62b0 197 #define _AES_KEYLC_KEYLC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLC */
<> 128:9bcdf88f62b0 198 #define _AES_KEYLC_KEYLC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLC */
<> 128:9bcdf88f62b0 199 #define AES_KEYLC_KEYLC_DEFAULT (_AES_KEYLC_KEYLC_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLC */
<> 128:9bcdf88f62b0 200
<> 128:9bcdf88f62b0 201 /* Bit fields for AES KEYLD */
<> 128:9bcdf88f62b0 202 #define _AES_KEYLD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLD */
<> 128:9bcdf88f62b0 203 #define _AES_KEYLD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLD */
<> 128:9bcdf88f62b0 204 #define _AES_KEYLD_KEYLD_SHIFT 0 /**< Shift value for AES_KEYLD */
<> 128:9bcdf88f62b0 205 #define _AES_KEYLD_KEYLD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLD */
<> 128:9bcdf88f62b0 206 #define _AES_KEYLD_KEYLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLD */
<> 128:9bcdf88f62b0 207 #define AES_KEYLD_KEYLD_DEFAULT (_AES_KEYLD_KEYLD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLD */
<> 128:9bcdf88f62b0 208
<> 128:9bcdf88f62b0 209 /* Bit fields for AES KEYHA */
<> 128:9bcdf88f62b0 210 #define _AES_KEYHA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHA */
<> 128:9bcdf88f62b0 211 #define _AES_KEYHA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHA */
<> 128:9bcdf88f62b0 212 #define _AES_KEYHA_KEYHA_SHIFT 0 /**< Shift value for AES_KEYHA */
<> 128:9bcdf88f62b0 213 #define _AES_KEYHA_KEYHA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHA */
<> 128:9bcdf88f62b0 214 #define _AES_KEYHA_KEYHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHA */
<> 128:9bcdf88f62b0 215 #define AES_KEYHA_KEYHA_DEFAULT (_AES_KEYHA_KEYHA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHA */
<> 128:9bcdf88f62b0 216
<> 128:9bcdf88f62b0 217 /* Bit fields for AES KEYHB */
<> 128:9bcdf88f62b0 218 #define _AES_KEYHB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHB */
<> 128:9bcdf88f62b0 219 #define _AES_KEYHB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHB */
<> 128:9bcdf88f62b0 220 #define _AES_KEYHB_KEYHB_SHIFT 0 /**< Shift value for AES_KEYHB */
<> 128:9bcdf88f62b0 221 #define _AES_KEYHB_KEYHB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHB */
<> 128:9bcdf88f62b0 222 #define _AES_KEYHB_KEYHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHB */
<> 128:9bcdf88f62b0 223 #define AES_KEYHB_KEYHB_DEFAULT (_AES_KEYHB_KEYHB_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHB */
<> 128:9bcdf88f62b0 224
<> 128:9bcdf88f62b0 225 /* Bit fields for AES KEYHC */
<> 128:9bcdf88f62b0 226 #define _AES_KEYHC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHC */
<> 128:9bcdf88f62b0 227 #define _AES_KEYHC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHC */
<> 128:9bcdf88f62b0 228 #define _AES_KEYHC_KEYHC_SHIFT 0 /**< Shift value for AES_KEYHC */
<> 128:9bcdf88f62b0 229 #define _AES_KEYHC_KEYHC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHC */
<> 128:9bcdf88f62b0 230 #define _AES_KEYHC_KEYHC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHC */
<> 128:9bcdf88f62b0 231 #define AES_KEYHC_KEYHC_DEFAULT (_AES_KEYHC_KEYHC_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHC */
<> 128:9bcdf88f62b0 232
<> 128:9bcdf88f62b0 233 /* Bit fields for AES KEYHD */
<> 128:9bcdf88f62b0 234 #define _AES_KEYHD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHD */
<> 128:9bcdf88f62b0 235 #define _AES_KEYHD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHD */
<> 128:9bcdf88f62b0 236 #define _AES_KEYHD_KEYHD_SHIFT 0 /**< Shift value for AES_KEYHD */
<> 128:9bcdf88f62b0 237 #define _AES_KEYHD_KEYHD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHD */
<> 128:9bcdf88f62b0 238 #define _AES_KEYHD_KEYHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHD */
<> 128:9bcdf88f62b0 239 #define AES_KEYHD_KEYHD_DEFAULT (_AES_KEYHD_KEYHD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHD */
<> 128:9bcdf88f62b0 240
<> 128:9bcdf88f62b0 241 /** @} End of group EFM32LG_AES */
<> 128:9bcdf88f62b0 242 /** @} End of group Parts */
<> 128:9bcdf88f62b0 243