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TARGET_MAX32625NEXPAQ/TARGET_Maxim/TARGET_MAX32625/device/spix_regs.h@135:fce8a9387ed1, 2017-01-17 (annotated)

Committer:
kaoshen
Date:
Tue Jan 17 23:27:32 2017 +0000
Revision:
135:fce8a9387ed1
Parent:
129:0ab6a29f35bf 
333 ADS1115 ADC1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 129:0ab6a29f35bf 1 /*******************************************************************************
<> 129:0ab6a29f35bf 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 129:0ab6a29f35bf 3 *
<> 129:0ab6a29f35bf 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 129:0ab6a29f35bf 5 * copy of this software and associated documentation files (the "Software"),
<> 129:0ab6a29f35bf 6 * to deal in the Software without restriction, including without limitation
<> 129:0ab6a29f35bf 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 129:0ab6a29f35bf 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 129:0ab6a29f35bf 9 * Software is furnished to do so, subject to the following conditions:
<> 129:0ab6a29f35bf 10 *
<> 129:0ab6a29f35bf 11 * The above copyright notice and this permission notice shall be included
<> 129:0ab6a29f35bf 12 * in all copies or substantial portions of the Software.
<> 129:0ab6a29f35bf 13 *
<> 129:0ab6a29f35bf 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 129:0ab6a29f35bf 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 129:0ab6a29f35bf 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 129:0ab6a29f35bf 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 129:0ab6a29f35bf 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 129:0ab6a29f35bf 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 129:0ab6a29f35bf 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 129:0ab6a29f35bf 21 *
<> 129:0ab6a29f35bf 22 * Except as contained in this notice, the name of Maxim Integrated
<> 129:0ab6a29f35bf 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 129:0ab6a29f35bf 24 * Products, Inc. Branding Policy.
<> 129:0ab6a29f35bf 25 *
<> 129:0ab6a29f35bf 26 * The mere transfer of this software does not imply any licenses
<> 129:0ab6a29f35bf 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 129:0ab6a29f35bf 28 * trademarks, maskwork rights, or any other form of intellectual
<> 129:0ab6a29f35bf 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 129:0ab6a29f35bf 30 * ownership rights.
<> 129:0ab6a29f35bf 31 ******************************************************************************/
<> 129:0ab6a29f35bf 32
<> 129:0ab6a29f35bf 33 #ifndef _MXC_SPIX_REGS_H_
<> 129:0ab6a29f35bf 34 #define _MXC_SPIX_REGS_H_
<> 129:0ab6a29f35bf 35
<> 129:0ab6a29f35bf 36 #ifdef __cplusplus
<> 129:0ab6a29f35bf 37 extern "C" {
<> 129:0ab6a29f35bf 38 #endif
<> 129:0ab6a29f35bf 39
<> 129:0ab6a29f35bf 40 #include <stdint.h>
<> 129:0ab6a29f35bf 41 #include "mxc_device.h"
<> 129:0ab6a29f35bf 42
<> 129:0ab6a29f35bf 43 /*
<> 129:0ab6a29f35bf 44 If types are not defined elsewhere (CMSIS) define them here
<> 129:0ab6a29f35bf 45 */
<> 129:0ab6a29f35bf 46 #ifndef __IO
<> 129:0ab6a29f35bf 47 #define __IO volatile
<> 129:0ab6a29f35bf 48 #endif
<> 129:0ab6a29f35bf 49 #ifndef __I
<> 129:0ab6a29f35bf 50 #define __I volatile const
<> 129:0ab6a29f35bf 51 #endif
<> 129:0ab6a29f35bf 52 #ifndef __O
<> 129:0ab6a29f35bf 53 #define __O volatile
<> 129:0ab6a29f35bf 54 #endif
<> 129:0ab6a29f35bf 55
<> 129:0ab6a29f35bf 56
<> 129:0ab6a29f35bf 57 /*
<> 129:0ab6a29f35bf 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 129:0ab6a29f35bf 59 access to each register in module.
<> 129:0ab6a29f35bf 60 */
<> 129:0ab6a29f35bf 61
<> 129:0ab6a29f35bf 62 /* Offset Register Description
<> 129:0ab6a29f35bf 63 ============= ============================================================================ */
<> 129:0ab6a29f35bf 64 typedef struct {
<> 129:0ab6a29f35bf 65 __IO uint32_t master_cfg; /* 0x0000 SPIX Master Configuration */
<> 129:0ab6a29f35bf 66 __IO uint32_t fetch_ctrl; /* 0x0004 SPIX Fetch Control */
<> 129:0ab6a29f35bf 67 __IO uint32_t mode_ctrl; /* 0x0008 SPIX Mode Control */
<> 129:0ab6a29f35bf 68 __IO uint32_t mode_data; /* 0x000C SPIX Mode Data */
<> 129:0ab6a29f35bf 69 __IO uint32_t sck_fb_ctrl; /* 0x0010 SPIX SCK_FB Control Register */
<> 129:0ab6a29f35bf 70 } mxc_spix_regs_t;
<> 129:0ab6a29f35bf 71
<> 129:0ab6a29f35bf 72
<> 129:0ab6a29f35bf 73 /*
<> 129:0ab6a29f35bf 74 Register offsets for module SPIX.
<> 129:0ab6a29f35bf 75 */
<> 129:0ab6a29f35bf 76
<> 129:0ab6a29f35bf 77 #define MXC_R_SPIX_OFFS_MASTER_CFG ((uint32_t)0x00000000UL)
<> 129:0ab6a29f35bf 78 #define MXC_R_SPIX_OFFS_FETCH_CTRL ((uint32_t)0x00000004UL)
<> 129:0ab6a29f35bf 79 #define MXC_R_SPIX_OFFS_MODE_CTRL ((uint32_t)0x00000008UL)
<> 129:0ab6a29f35bf 80 #define MXC_R_SPIX_OFFS_MODE_DATA ((uint32_t)0x0000000CUL)
<> 129:0ab6a29f35bf 81 #define MXC_R_SPIX_OFFS_SCK_FB_CTRL ((uint32_t)0x00000010UL)
<> 129:0ab6a29f35bf 82
<> 129:0ab6a29f35bf 83
<> 129:0ab6a29f35bf 84 /*
<> 129:0ab6a29f35bf 85 Field positions and masks for module SPIX.
<> 129:0ab6a29f35bf 86 */
<> 129:0ab6a29f35bf 87
<> 129:0ab6a29f35bf 88 #define MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS 0
<> 129:0ab6a29f35bf 89 #define MXC_F_SPIX_MASTER_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS))
<> 129:0ab6a29f35bf 90 #define MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS 2
<> 129:0ab6a29f35bf 91 #define MXC_F_SPIX_MASTER_CFG_SS_ACT_LO ((uint32_t)(0x00000001UL << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS))
<> 129:0ab6a29f35bf 92 #define MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS 3
<> 129:0ab6a29f35bf 93 #define MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN ((uint32_t)(0x00000001UL << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS))
<> 129:0ab6a29f35bf 94 #define MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS 4
<> 129:0ab6a29f35bf 95 #define MXC_F_SPIX_MASTER_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS))
<> 129:0ab6a29f35bf 96 #define MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS 8
<> 129:0ab6a29f35bf 97 #define MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS))
<> 129:0ab6a29f35bf 98 #define MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS 12
<> 129:0ab6a29f35bf 99 #define MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS))
<> 129:0ab6a29f35bf 100 #define MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS 16
<> 129:0ab6a29f35bf 101 #define MXC_F_SPIX_MASTER_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS))
<> 129:0ab6a29f35bf 102 #define MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS 18
<> 129:0ab6a29f35bf 103 #define MXC_F_SPIX_MASTER_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS))
<> 129:0ab6a29f35bf 104 #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK_POS 20
<> 129:0ab6a29f35bf 105 #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK_POS))
<> 129:0ab6a29f35bf 106 #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK_POS 24
<> 129:0ab6a29f35bf 107 #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK_POS))
<> 129:0ab6a29f35bf 108 #define MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT_POS 28
<> 129:0ab6a29f35bf 109 #define MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT_POS))
<> 129:0ab6a29f35bf 110
<> 129:0ab6a29f35bf 111 #define MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS 0
<> 129:0ab6a29f35bf 112 #define MXC_F_SPIX_FETCH_CTRL_CMD_VALUE ((uint32_t)(0x000000FFUL << MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS))
<> 129:0ab6a29f35bf 113 #define MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS 8
<> 129:0ab6a29f35bf 114 #define MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS))
<> 129:0ab6a29f35bf 115 #define MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS 10
<> 129:0ab6a29f35bf 116 #define MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS))
<> 129:0ab6a29f35bf 117 #define MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS 12
<> 129:0ab6a29f35bf 118 #define MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS))
<> 129:0ab6a29f35bf 119 #define MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR_POS 16
<> 129:0ab6a29f35bf 120 #define MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR ((uint32_t)(0x00000001UL << MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR_POS))
<> 129:0ab6a29f35bf 121
<> 129:0ab6a29f35bf 122 #define MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS 0
<> 129:0ab6a29f35bf 123 #define MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS))
<> 129:0ab6a29f35bf 124 #define MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS 8
<> 129:0ab6a29f35bf 125 #define MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS))
<> 129:0ab6a29f35bf 126
<> 129:0ab6a29f35bf 127 #define MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS 0
<> 129:0ab6a29f35bf 128 #define MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS ((uint32_t)(0x0000FFFFUL << MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS))
<> 129:0ab6a29f35bf 129 #define MXC_F_SPIX_MODE_DATA_MODE_DATA_OE_POS 16
<> 129:0ab6a29f35bf 130 #define MXC_F_SPIX_MODE_DATA_MODE_DATA_OE ((uint32_t)(0x0000FFFFUL << MXC_F_SPIX_MODE_DATA_MODE_DATA_OE_POS))
<> 129:0ab6a29f35bf 131
<> 129:0ab6a29f35bf 132 #define MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE_POS 0
<> 129:0ab6a29f35bf 133 #define MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE_POS))
<> 129:0ab6a29f35bf 134 #define MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK_POS 1
<> 129:0ab6a29f35bf 135 #define MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK ((uint32_t)(0x00000001UL << MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK_POS))
<> 129:0ab6a29f35bf 136
<> 129:0ab6a29f35bf 137 #if(MXC_SPIX_REV == 0)
<> 129:0ab6a29f35bf 138 #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_POS 4
<> 129:0ab6a29f35bf 139 #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS ((uint32_t)(0x0000003FUL << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_POS))
<> 129:0ab6a29f35bf 140 #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS 12
<> 129:0ab6a29f35bf 141 #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD ((uint32_t)(0x0000003FUL << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS))
<> 129:0ab6a29f35bf 142 #endif
<> 129:0ab6a29f35bf 143
<> 129:0ab6a29f35bf 144
<> 129:0ab6a29f35bf 145 /*
<> 129:0ab6a29f35bf 146 Field values and shifted values for module SPIX.
<> 129:0ab6a29f35bf 147 */
<> 129:0ab6a29f35bf 148
<> 129:0ab6a29f35bf 149 #define MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(0x00000000UL))
<> 129:0ab6a29f35bf 150 #define MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(0x00000003UL))
<> 129:0ab6a29f35bf 151
<> 129:0ab6a29f35bf 152 #define MXC_S_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS))
<> 129:0ab6a29f35bf 153 #define MXC_S_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS))
<> 129:0ab6a29f35bf 154
<> 129:0ab6a29f35bf 155 #define MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH ((uint32_t)(0x00000000UL))
<> 129:0ab6a29f35bf 156 #define MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW ((uint32_t)(0x00000001UL))
<> 129:0ab6a29f35bf 157
<> 129:0ab6a29f35bf 158 #define MXC_S_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS))
<> 129:0ab6a29f35bf 159 #define MXC_S_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS))
<> 129:0ab6a29f35bf 160
<> 129:0ab6a29f35bf 161 #define MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED ((uint32_t)(0x00000000UL))
<> 129:0ab6a29f35bf 162 #define MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED ((uint32_t)(0x00000001UL))
<> 129:0ab6a29f35bf 163
<> 129:0ab6a29f35bf 164 #define MXC_S_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS))
<> 129:0ab6a29f35bf 165 #define MXC_S_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS))
<> 129:0ab6a29f35bf 166
<> 129:0ab6a29f35bf 167 #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(0x00000000UL))
<> 129:0ab6a29f35bf 168 #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL))
<> 129:0ab6a29f35bf 169 #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL))
<> 129:0ab6a29f35bf 170 #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL))
<> 129:0ab6a29f35bf 171
<> 129:0ab6a29f35bf 172 #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_OFF << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS))
<> 129:0ab6a29f35bf 173 #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS))
<> 129:0ab6a29f35bf 174 #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS))
<> 129:0ab6a29f35bf 175 #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS))
<> 129:0ab6a29f35bf 176
<> 129:0ab6a29f35bf 177 #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(0x00000000UL))
<> 129:0ab6a29f35bf 178 #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL))
<> 129:0ab6a29f35bf 179 #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL))
<> 129:0ab6a29f35bf 180 #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL))
<> 129:0ab6a29f35bf 181
<> 129:0ab6a29f35bf 182 #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_OFF << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS))
<> 129:0ab6a29f35bf 183 #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS))
<> 129:0ab6a29f35bf 184 #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS))
<> 129:0ab6a29f35bf 185 #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS))
<> 129:0ab6a29f35bf 186
<> 129:0ab6a29f35bf 187 #define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)(0x00000000UL))
<> 129:0ab6a29f35bf 188 #define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL))
<> 129:0ab6a29f35bf 189 #define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL))
<> 129:0ab6a29f35bf 190
<> 129:0ab6a29f35bf 191 #define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS))
<> 129:0ab6a29f35bf 192 #define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS))
<> 129:0ab6a29f35bf 193 #define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS))
<> 129:0ab6a29f35bf 194
<> 129:0ab6a29f35bf 195 #define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)(0x00000000UL))
<> 129:0ab6a29f35bf 196 #define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL))
<> 129:0ab6a29f35bf 197 #define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL))
<> 129:0ab6a29f35bf 198
<> 129:0ab6a29f35bf 199 #define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS))
<> 129:0ab6a29f35bf 200 #define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS))
<> 129:0ab6a29f35bf 201 #define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS))
<> 129:0ab6a29f35bf 202
<> 129:0ab6a29f35bf 203 #define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)(0x00000000UL))
<> 129:0ab6a29f35bf 204 #define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL))
<> 129:0ab6a29f35bf 205 #define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL))
<> 129:0ab6a29f35bf 206
<> 129:0ab6a29f35bf 207 #define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS))
<> 129:0ab6a29f35bf 208 #define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS))
<> 129:0ab6a29f35bf 209 #define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS))
<> 129:0ab6a29f35bf 210
<> 129:0ab6a29f35bf 211
<> 129:0ab6a29f35bf 212
<> 129:0ab6a29f35bf 213 #ifdef __cplusplus
<> 129:0ab6a29f35bf 214 }
<> 129:0ab6a29f35bf 215 #endif
<> 129:0ab6a29f35bf 216
<> 129:0ab6a29f35bf 217 #endif /* _MXC_SPIX_REGS_H_ */
<> 129:0ab6a29f35bf 218