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TARGET_MAXWSNENV/TARGET_Maxim/TARGET_MAX32610/device/ioman_regs.h@128:9bcdf88f62b0, 2016-10-27 (annotated)

Committer:
<>
Date:
Thu Oct 27 16:45:56 2016 +0100
Revision:
128:9bcdf88f62b0
Release 128 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



2966: Add kw24 support https://github.com/ARMmbed/mbed-os/pull/2966

3068: MultiTech mDot - clean up PeripheralPins.c and add new pin names https://github.com/ARMmbed/mbed-os/pull/3068

3089: Kinetis HAL: Remove clock initialization code from serial and ticker  https://github.com/ARMmbed/mbed-os/pull/3089

2943: [NRF5] NVIC_SetVector functionality https://github.com/ARMmbed/mbed-os/pull/2943

2938: InterruptIn changes in NCS36510 HAL. https://github.com/ARMmbed/mbed-os/pull/2938

3108: Fix sleep function for NRF52. https://github.com/ARMmbed/mbed-os/pull/3108

3076: STM32F1: Correct timer master value reading https://github.com/ARMmbed/mbed-os/pull/3076

3085: Add LOWPOWERTIMER capability for NUCLEO_F303ZE https://github.com/ARMmbed/mbed-os/pull/3085

3046: [BEETLE] Update BLE stack on Beetle board https://github.com/ARMmbed/mbed-os/pull/3046

3122: [Silicon Labs] Update of Silicon Labs HAL https://github.com/ARMmbed/mbed-os/pull/3122

3022: OnSemi RAM usage fix https://github.com/ARMmbed/mbed-os/pull/3022

3121: STM32F3: Correct UART4 and UART5 defines when using DEVICE_SERIAL_ASYNCH https://github.com/ARMmbed/mbed-os/pull/3121

3142: Targets- NUMAKER_PFM_NUC47216 remove mbed 2 https://github.com/ARMmbed/mbed-os/pull/3142

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /*******************************************************************************
<> 128:9bcdf88f62b0 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 128:9bcdf88f62b0 3 *
<> 128:9bcdf88f62b0 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 128:9bcdf88f62b0 5 * copy of this software and associated documentation files (the "Software"),
<> 128:9bcdf88f62b0 6 * to deal in the Software without restriction, including without limitation
<> 128:9bcdf88f62b0 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 128:9bcdf88f62b0 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 128:9bcdf88f62b0 9 * Software is furnished to do so, subject to the following conditions:
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * The above copyright notice and this permission notice shall be included
<> 128:9bcdf88f62b0 12 * in all copies or substantial portions of the Software.
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 128:9bcdf88f62b0 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 128:9bcdf88f62b0 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 128:9bcdf88f62b0 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 128:9bcdf88f62b0 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 128:9bcdf88f62b0 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 128:9bcdf88f62b0 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 128:9bcdf88f62b0 21 *
<> 128:9bcdf88f62b0 22 * Except as contained in this notice, the name of Maxim Integrated
<> 128:9bcdf88f62b0 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 128:9bcdf88f62b0 24 * Products, Inc. Branding Policy.
<> 128:9bcdf88f62b0 25 *
<> 128:9bcdf88f62b0 26 * The mere transfer of this software does not imply any licenses
<> 128:9bcdf88f62b0 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 128:9bcdf88f62b0 28 * trademarks, maskwork rights, or any other form of intellectual
<> 128:9bcdf88f62b0 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 128:9bcdf88f62b0 30 * ownership rights.
<> 128:9bcdf88f62b0 31 *******************************************************************************
<> 128:9bcdf88f62b0 32 */
<> 128:9bcdf88f62b0 33
<> 128:9bcdf88f62b0 34 #ifndef _MXC_IOMAN_REGS_H_
<> 128:9bcdf88f62b0 35 #define _MXC_IOMAN_REGS_H_
<> 128:9bcdf88f62b0 36
<> 128:9bcdf88f62b0 37 #ifdef __cplusplus
<> 128:9bcdf88f62b0 38 extern "C" {
<> 128:9bcdf88f62b0 39 #endif
<> 128:9bcdf88f62b0 40
<> 128:9bcdf88f62b0 41 #include <stdint.h>
<> 128:9bcdf88f62b0 42
<> 128:9bcdf88f62b0 43 /**
<> 128:9bcdf88f62b0 44 * @file ioman_regs.h
<> 128:9bcdf88f62b0 45 * @addtogroup ioman IO MUX Manager
<> 128:9bcdf88f62b0 46 * @{
<> 128:9bcdf88f62b0 47 */
<> 128:9bcdf88f62b0 48
<> 128:9bcdf88f62b0 49 typedef enum {
<> 128:9bcdf88f62b0 50 /** Pin Mapping 'A' */
<> 128:9bcdf88f62b0 51 MXC_E_IOMAN_MAPPING_A = 0,
<> 128:9bcdf88f62b0 52 /** Pin Mapping 'B' */
<> 128:9bcdf88f62b0 53 MXC_E_IOMAN_MAPPING_B,
<> 128:9bcdf88f62b0 54 /** Pin Mapping 'C' */
<> 128:9bcdf88f62b0 55 MXC_E_IOMAN_MAPPING_C,
<> 128:9bcdf88f62b0 56 /** Pin Mapping 'D' */
<> 128:9bcdf88f62b0 57 MXC_E_IOMAN_MAPPING_D,
<> 128:9bcdf88f62b0 58 /** Pin Mapping 'E' */
<> 128:9bcdf88f62b0 59 MXC_E_IOMAN_MAPPING_E,
<> 128:9bcdf88f62b0 60 /** Pin Mapping 'F' */
<> 128:9bcdf88f62b0 61 MXC_E_IOMAN_MAPPING_F,
<> 128:9bcdf88f62b0 62 /** Pin Mapping 'G' */
<> 128:9bcdf88f62b0 63 MXC_E_IOMAN_MAPPING_G,
<> 128:9bcdf88f62b0 64 /** Pin Mapping 'H' */
<> 128:9bcdf88f62b0 65 MXC_E_IOMAN_MAPPING_H,
<> 128:9bcdf88f62b0 66 } ioman_mapping_t;
<> 128:9bcdf88f62b0 67
<> 128:9bcdf88f62b0 68 /* Offset Register Description
<> 128:9bcdf88f62b0 69 ====== ========================================== */
<> 128:9bcdf88f62b0 70 typedef struct {
<> 128:9bcdf88f62b0 71 __IO uint32_t wud_req0; /* 0x0000 Wakeup Detect Mode Request Register 0 */
<> 128:9bcdf88f62b0 72 __IO uint32_t wud_req1; /* 0x0004 Wakeup Detect Mode Request Register 1 */
<> 128:9bcdf88f62b0 73 __IO uint32_t wud_ack0; /* 0x0008 Wakeup Detect Mode Acknowledge Register 0 */
<> 128:9bcdf88f62b0 74 __IO uint32_t wud_ack1; /* 0x000C Wakeup Detect Mode Acknowledge Register 1 */
<> 128:9bcdf88f62b0 75 __IO uint32_t ali_req0; /* 0x0010 Analog Input Request Register 0 */
<> 128:9bcdf88f62b0 76 __IO uint32_t ali_req1; /* 0x0014 Analog Input Request Register 1 */
<> 128:9bcdf88f62b0 77 __IO uint32_t ali_ack0; /* 0x0018 Analog Input Acknowledge Register 0 */
<> 128:9bcdf88f62b0 78 __IO uint32_t ali_ack1; /* 0x001C Analog Input Acknowledge Register 1 */
<> 128:9bcdf88f62b0 79 __IO uint32_t spi0_req; /* 0x0020 SPI0 I/O Mode Request */
<> 128:9bcdf88f62b0 80 __IO uint32_t spi0_ack; /* 0x0024 SPI0 I/O Mode Acknowledge */
<> 128:9bcdf88f62b0 81 __IO uint32_t spi1_req; /* 0x0028 SPI1 I/O Mode Request */
<> 128:9bcdf88f62b0 82 __IO uint32_t spi1_ack; /* 0x002C SPI1 I/O Mode Acknowledge */
<> 128:9bcdf88f62b0 83 __IO uint32_t spi2_req; /* 0x0030 SPI2 I/O Mode Request */
<> 128:9bcdf88f62b0 84 __IO uint32_t spi2_ack; /* 0x0034 SPI2 I/O Mode Acknowledge */
<> 128:9bcdf88f62b0 85 __IO uint32_t uart0_req; /* 0x0038 UART0 I/O Mode Request */
<> 128:9bcdf88f62b0 86 __IO uint32_t uart0_ack; /* 0x003C UART0 I/O Mode Acknowledge */
<> 128:9bcdf88f62b0 87 __IO uint32_t uart1_req; /* 0x0040 UART1 I/O Mode Request */
<> 128:9bcdf88f62b0 88 __IO uint32_t uart1_ack; /* 0x0044 UART1 I/O Mode Acknowledge */
<> 128:9bcdf88f62b0 89 __IO uint32_t i2cm0_req; /* 0x0048 I2C Master 0 I/O Request */
<> 128:9bcdf88f62b0 90 __IO uint32_t i2cm0_ack; /* 0x004C I2C Master 0 I/O Acknowledge */
<> 128:9bcdf88f62b0 91 __IO uint32_t i2cs0_req; /* 0x0050 I2C Slave 0 I/O Request */
<> 128:9bcdf88f62b0 92 __IO uint32_t i2s0_ack; /* 0x0054 I2C Slave 0 I/O Acknowledge */
<> 128:9bcdf88f62b0 93 __IO uint32_t lcd_com_req; /* 0x0058 LCD COM Driver I/O Request */
<> 128:9bcdf88f62b0 94 __IO uint32_t lcd_com_ack; /* 0x005C LCD COM Driver I/O Acknowledge */
<> 128:9bcdf88f62b0 95 __IO uint32_t lcd_seg_req0; /* 0x0060 LCD SEG Driver I/O Request Register 0 */
<> 128:9bcdf88f62b0 96 __IO uint32_t lcd_seg_req1; /* 0x0064 LCD SEG Driver I/O Request Register 1 */
<> 128:9bcdf88f62b0 97 __IO uint32_t lcd_seg_ack0; /* 0x0068 LCD SEG Driver I/O Acknowledge Register 0 */
<> 128:9bcdf88f62b0 98 __IO uint32_t lcd_seg_ack1; /* 0x006C LCD SEG Driver I/O Acknowledge Register 1 */
<> 128:9bcdf88f62b0 99 __IO uint32_t crnt_req; /* 0x0070 Current Drive I/O Request Register */
<> 128:9bcdf88f62b0 100 __IO uint32_t io_crnt_ack; /* 0x0074 Current Drive I/O Acknowledge Register */
<> 128:9bcdf88f62b0 101 __IO uint32_t crnt_mode; /* 0x0078 Current Drive I/O Mode Control */
<> 128:9bcdf88f62b0 102 __IO uint32_t ali_connect0; /* 0x007C Analog I/O Connection Control Register 0 */
<> 128:9bcdf88f62b0 103 __IO uint32_t ali_connect1; /* 0x0080 Analog I/O Connection Control Register 1 */
<> 128:9bcdf88f62b0 104 __IO uint32_t i2cm1_req; /* 0x0084 I2C Master 1 I/O Request */
<> 128:9bcdf88f62b0 105 __IO uint32_t i2cm1_ack; /* 0x0088 I2C Master 1 I/O Acknowledge */
<> 128:9bcdf88f62b0 106 __IO uint32_t padx_control; /* 0x008C PADX Control */
<> 128:9bcdf88f62b0 107 } mxc_ioman_regs_t;
<> 128:9bcdf88f62b0 108
<> 128:9bcdf88f62b0 109
<> 128:9bcdf88f62b0 110 /*
<> 128:9bcdf88f62b0 111 Register offsets for module IOMAN.
<> 128:9bcdf88f62b0 112 */
<> 128:9bcdf88f62b0 113 #define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL)
<> 128:9bcdf88f62b0 114 #define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL)
<> 128:9bcdf88f62b0 115 #define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL)
<> 128:9bcdf88f62b0 116 #define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL)
<> 128:9bcdf88f62b0 117 #define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL)
<> 128:9bcdf88f62b0 118 #define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL)
<> 128:9bcdf88f62b0 119 #define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL)
<> 128:9bcdf88f62b0 120 #define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL)
<> 128:9bcdf88f62b0 121 #define MXC_R_IOMAN_OFFS_SPI0_REQ ((uint32_t)0x00000020UL)
<> 128:9bcdf88f62b0 122 #define MXC_R_IOMAN_OFFS_SPI0_ACK ((uint32_t)0x00000024UL)
<> 128:9bcdf88f62b0 123 #define MXC_R_IOMAN_OFFS_SPI1_REQ ((uint32_t)0x00000028UL)
<> 128:9bcdf88f62b0 124 #define MXC_R_IOMAN_OFFS_SPI1_ACK ((uint32_t)0x0000002CUL)
<> 128:9bcdf88f62b0 125 #define MXC_R_IOMAN_OFFS_SPI2_REQ ((uint32_t)0x00000030UL)
<> 128:9bcdf88f62b0 126 #define MXC_R_IOMAN_OFFS_SPI2_ACK ((uint32_t)0x00000034UL)
<> 128:9bcdf88f62b0 127 #define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000038UL)
<> 128:9bcdf88f62b0 128 #define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x0000003CUL)
<> 128:9bcdf88f62b0 129 #define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000040UL)
<> 128:9bcdf88f62b0 130 #define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x00000044UL)
<> 128:9bcdf88f62b0 131 #define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000048UL)
<> 128:9bcdf88f62b0 132 #define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x0000004CUL)
<> 128:9bcdf88f62b0 133 #define MXC_R_IOMAN_OFFS_I2CS0_REQ ((uint32_t)0x00000050UL)
<> 128:9bcdf88f62b0 134 #define MXC_R_IOMAN_OFFS_I2SC0_ACK ((uint32_t)0x00000054UL)
<> 128:9bcdf88f62b0 135 #define MXC_R_IOMAN_OFFS_LCD_COM_REQ ((uint32_t)0x00000058UL)
<> 128:9bcdf88f62b0 136 #define MXC_R_IOMAN_OFFS_LCD_COM_ACK ((uint32_t)0x0000005CUL)
<> 128:9bcdf88f62b0 137 #define MXC_R_IOMAN_OFFS_LCD_SEG_REQ0 ((uint32_t)0x00000060UL)
<> 128:9bcdf88f62b0 138 #define MXC_R_IOMAN_OFFS_LCD_SEG_REQ1 ((uint32_t)0x00000064UL)
<> 128:9bcdf88f62b0 139 #define MXC_R_IOMAN_OFFS_LCD_SEG_ACK0 ((uint32_t)0x00000068UL)
<> 128:9bcdf88f62b0 140 #define MXC_R_IOMAN_OFFS_LCD_SEG_ACK1 ((uint32_t)0x0000006CUL)
<> 128:9bcdf88f62b0 141 #define MXC_R_IOMAN_OFFS_IO_CRNT_REQ ((uint32_t)0x00000070UL)
<> 128:9bcdf88f62b0 142 #define MXC_R_IOMAN_OFFS_IO_CRNT_ACK ((uint32_t)0x00000074UL)
<> 128:9bcdf88f62b0 143 #define MXC_R_IOMAN_OFFS_IO_CRNT_MODE ((uint32_t)0x00000078UL)
<> 128:9bcdf88f62b0 144 #define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x0000007CUL)
<> 128:9bcdf88f62b0 145 #define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000080UL)
<> 128:9bcdf88f62b0 146 #define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000084UL)
<> 128:9bcdf88f62b0 147 #define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x00000088UL)
<> 128:9bcdf88f62b0 148 #define MXC_R_IOMAN_OFFS_PADX_CONTROL ((uint32_t)0x0000008CUL)
<> 128:9bcdf88f62b0 149
<> 128:9bcdf88f62b0 150
<> 128:9bcdf88f62b0 151 /*
<> 128:9bcdf88f62b0 152 Field positions and masks for module IOMAN.
<> 128:9bcdf88f62b0 153 */
<> 128:9bcdf88f62b0 154 #define MXC_F_IOMAN_WUD_REQ0_PORT0_POS 0
<> 128:9bcdf88f62b0 155 #define MXC_F_IOMAN_WUD_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT0_POS))
<> 128:9bcdf88f62b0 156 #define MXC_F_IOMAN_WUD_REQ0_PORT1_POS 8
<> 128:9bcdf88f62b0 157 #define MXC_F_IOMAN_WUD_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT1_POS))
<> 128:9bcdf88f62b0 158 #define MXC_F_IOMAN_WUD_REQ0_PORT2_POS 16
<> 128:9bcdf88f62b0 159 #define MXC_F_IOMAN_WUD_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT2_POS))
<> 128:9bcdf88f62b0 160 #define MXC_F_IOMAN_WUD_REQ0_PORT3_POS 24
<> 128:9bcdf88f62b0 161 #define MXC_F_IOMAN_WUD_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT3_POS))
<> 128:9bcdf88f62b0 162
<> 128:9bcdf88f62b0 163 #define MXC_F_IOMAN_WUD_REQ1_PORT4_POS 0
<> 128:9bcdf88f62b0 164 #define MXC_F_IOMAN_WUD_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT4_POS))
<> 128:9bcdf88f62b0 165 #define MXC_F_IOMAN_WUD_REQ1_PORT5_POS 8
<> 128:9bcdf88f62b0 166 #define MXC_F_IOMAN_WUD_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT5_POS))
<> 128:9bcdf88f62b0 167 #define MXC_F_IOMAN_WUD_REQ1_PORT6_POS 16
<> 128:9bcdf88f62b0 168 #define MXC_F_IOMAN_WUD_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT6_POS))
<> 128:9bcdf88f62b0 169 #define MXC_F_IOMAN_WUD_REQ1_PORT7_POS 24
<> 128:9bcdf88f62b0 170 #define MXC_F_IOMAN_WUD_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT7_POS))
<> 128:9bcdf88f62b0 171
<> 128:9bcdf88f62b0 172 #define MXC_F_IOMAN_WUD_ACK0_PORT0_POS 0
<> 128:9bcdf88f62b0 173 #define MXC_F_IOMAN_WUD_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT0_POS))
<> 128:9bcdf88f62b0 174 #define MXC_F_IOMAN_WUD_ACK0_PORT1_POS 8
<> 128:9bcdf88f62b0 175 #define MXC_F_IOMAN_WUD_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT1_POS))
<> 128:9bcdf88f62b0 176 #define MXC_F_IOMAN_WUD_ACK0_PORT2_POS 16
<> 128:9bcdf88f62b0 177 #define MXC_F_IOMAN_WUD_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT2_POS))
<> 128:9bcdf88f62b0 178 #define MXC_F_IOMAN_WUD_ACK0_PORT3_POS 24
<> 128:9bcdf88f62b0 179 #define MXC_F_IOMAN_WUD_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT3_POS))
<> 128:9bcdf88f62b0 180
<> 128:9bcdf88f62b0 181 #define MXC_F_IOMAN_WUD_ACK1_PORT4_POS 0
<> 128:9bcdf88f62b0 182 #define MXC_F_IOMAN_WUD_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT4_POS))
<> 128:9bcdf88f62b0 183 #define MXC_F_IOMAN_WUD_ACK1_PORT5_POS 8
<> 128:9bcdf88f62b0 184 #define MXC_F_IOMAN_WUD_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT5_POS))
<> 128:9bcdf88f62b0 185 #define MXC_F_IOMAN_WUD_ACK1_PORT6_POS 16
<> 128:9bcdf88f62b0 186 #define MXC_F_IOMAN_WUD_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT6_POS))
<> 128:9bcdf88f62b0 187 #define MXC_F_IOMAN_WUD_ACK1_PORT7_POS 24
<> 128:9bcdf88f62b0 188 #define MXC_F_IOMAN_WUD_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT7_POS))
<> 128:9bcdf88f62b0 189
<> 128:9bcdf88f62b0 190 #define MXC_F_IOMAN_ALI_REQ0_PORT0_POS 0
<> 128:9bcdf88f62b0 191 #define MXC_F_IOMAN_ALI_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT0_POS))
<> 128:9bcdf88f62b0 192 #define MXC_F_IOMAN_ALI_REQ0_PORT1_POS 8
<> 128:9bcdf88f62b0 193 #define MXC_F_IOMAN_ALI_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT1_POS))
<> 128:9bcdf88f62b0 194 #define MXC_F_IOMAN_ALI_REQ0_PORT2_POS 16
<> 128:9bcdf88f62b0 195 #define MXC_F_IOMAN_ALI_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT2_POS))
<> 128:9bcdf88f62b0 196 #define MXC_F_IOMAN_ALI_REQ0_PORT3_POS 24
<> 128:9bcdf88f62b0 197 #define MXC_F_IOMAN_ALI_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT3_POS))
<> 128:9bcdf88f62b0 198
<> 128:9bcdf88f62b0 199 #define MXC_F_IOMAN_ALI_REQ1_PORT4_POS 0
<> 128:9bcdf88f62b0 200 #define MXC_F_IOMAN_ALI_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT4_POS))
<> 128:9bcdf88f62b0 201 #define MXC_F_IOMAN_ALI_REQ1_PORT5_POS 8
<> 128:9bcdf88f62b0 202 #define MXC_F_IOMAN_ALI_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT5_POS))
<> 128:9bcdf88f62b0 203 #define MXC_F_IOMAN_ALI_REQ1_PORT6_POS 16
<> 128:9bcdf88f62b0 204 #define MXC_F_IOMAN_ALI_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT6_POS))
<> 128:9bcdf88f62b0 205 #define MXC_F_IOMAN_ALI_REQ1_PORT7_POS 24
<> 128:9bcdf88f62b0 206 #define MXC_F_IOMAN_ALI_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT7_POS))
<> 128:9bcdf88f62b0 207
<> 128:9bcdf88f62b0 208 #define MXC_F_IOMAN_ALI_ACK0_PORT0_POS 0
<> 128:9bcdf88f62b0 209 #define MXC_F_IOMAN_ALI_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT0_POS))
<> 128:9bcdf88f62b0 210 #define MXC_F_IOMAN_ALI_ACK0_PORT1_POS 8
<> 128:9bcdf88f62b0 211 #define MXC_F_IOMAN_ALI_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT1_POS))
<> 128:9bcdf88f62b0 212 #define MXC_F_IOMAN_ALI_ACK0_PORT2_POS 16
<> 128:9bcdf88f62b0 213 #define MXC_F_IOMAN_ALI_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT2_POS))
<> 128:9bcdf88f62b0 214 #define MXC_F_IOMAN_ALI_ACK0_PORT3_POS 24
<> 128:9bcdf88f62b0 215 #define MXC_F_IOMAN_ALI_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT3_POS))
<> 128:9bcdf88f62b0 216
<> 128:9bcdf88f62b0 217 #define MXC_F_IOMAN_ALI_ACK1_PORT4_POS 0
<> 128:9bcdf88f62b0 218 #define MXC_F_IOMAN_ALI_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT4_POS))
<> 128:9bcdf88f62b0 219 #define MXC_F_IOMAN_ALI_ACK1_PORT5_POS 8
<> 128:9bcdf88f62b0 220 #define MXC_F_IOMAN_ALI_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT5_POS))
<> 128:9bcdf88f62b0 221 #define MXC_F_IOMAN_ALI_ACK1_PORT6_POS 16
<> 128:9bcdf88f62b0 222 #define MXC_F_IOMAN_ALI_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT6_POS))
<> 128:9bcdf88f62b0 223 #define MXC_F_IOMAN_ALI_ACK1_PORT7_POS 24
<> 128:9bcdf88f62b0 224 #define MXC_F_IOMAN_ALI_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT7_POS))
<> 128:9bcdf88f62b0 225
<> 128:9bcdf88f62b0 226 #define MXC_F_IOMAN_SPI_MAPPING_POS 0
<> 128:9bcdf88f62b0 227 #define MXC_F_IOMAN_SPI_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPI_MAPPING_POS))
<> 128:9bcdf88f62b0 228 #define MXC_F_IOMAN_SPI_CORE_IO_POS 4
<> 128:9bcdf88f62b0 229 #define MXC_F_IOMAN_SPI_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_CORE_IO_POS))
<> 128:9bcdf88f62b0 230 #define MXC_F_IOMAN_SPI_SS0_IO_POS 8
<> 128:9bcdf88f62b0 231 #define MXC_F_IOMAN_SPI_SS0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS0_IO_POS))
<> 128:9bcdf88f62b0 232 #define MXC_F_IOMAN_SPI_SS1_IO_POS 9
<> 128:9bcdf88f62b0 233 #define MXC_F_IOMAN_SPI_SS1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS1_IO_POS))
<> 128:9bcdf88f62b0 234 #define MXC_F_IOMAN_SPI_SS2_IO_POS 10
<> 128:9bcdf88f62b0 235 #define MXC_F_IOMAN_SPI_SS2_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS2_IO_POS))
<> 128:9bcdf88f62b0 236 #define MXC_F_IOMAN_SPI_SS3_IO_POS 11
<> 128:9bcdf88f62b0 237 #define MXC_F_IOMAN_SPI_SS3_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS3_IO_POS))
<> 128:9bcdf88f62b0 238 #define MXC_F_IOMAN_SPI_SS4_IO_POS 12
<> 128:9bcdf88f62b0 239 #define MXC_F_IOMAN_SPI_SS4_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS4_IO_POS))
<> 128:9bcdf88f62b0 240 #define MXC_F_IOMAN_SPI_SR0_IO_POS 16
<> 128:9bcdf88f62b0 241 #define MXC_F_IOMAN_SPI_SR0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR0_IO_POS))
<> 128:9bcdf88f62b0 242 #define MXC_F_IOMAN_SPI_SR1_IO_POS 17
<> 128:9bcdf88f62b0 243 #define MXC_F_IOMAN_SPI_SR1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR1_IO_POS))
<> 128:9bcdf88f62b0 244 #define MXC_F_IOMAN_SPI_QUAD_IO_POS 20
<> 128:9bcdf88f62b0 245 #define MXC_F_IOMAN_SPI_QUAD_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_QUAD_IO_POS))
<> 128:9bcdf88f62b0 246 #define MXC_F_IOMAN_SPI_FAST_MODE_POS 24
<> 128:9bcdf88f62b0 247 #define MXC_F_IOMAN_SPI_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_FAST_MODE_POS))
<> 128:9bcdf88f62b0 248
<> 128:9bcdf88f62b0 249 #define MXC_F_IOMAN_UART_MAPPING_POS 0
<> 128:9bcdf88f62b0 250 #define MXC_F_IOMAN_UART_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_UART_MAPPING_POS))
<> 128:9bcdf88f62b0 251 #define MXC_F_IOMAN_UART_CORE_IO_POS 4
<> 128:9bcdf88f62b0 252 #define MXC_F_IOMAN_UART_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CORE_IO_POS))
<> 128:9bcdf88f62b0 253 #define MXC_F_IOMAN_UART_CTS_IO_POS 5
<> 128:9bcdf88f62b0 254 #define MXC_F_IOMAN_UART_CTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CTS_IO_POS))
<> 128:9bcdf88f62b0 255 #define MXC_F_IOMAN_UART_RTS_IO_POS 6
<> 128:9bcdf88f62b0 256 #define MXC_F_IOMAN_UART_RTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_RTS_IO_POS))
<> 128:9bcdf88f62b0 257
<> 128:9bcdf88f62b0 258 #define MXC_F_IOMAN_I2CM_MAPPING_POS 0
<> 128:9bcdf88f62b0 259 #define MXC_F_IOMAN_I2CM_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM_MAPPING_POS))
<> 128:9bcdf88f62b0 260 #define MXC_F_IOMAN_I2CM_CORE_IO_POS 4
<> 128:9bcdf88f62b0 261 #define MXC_F_IOMAN_I2CM_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM_CORE_IO_POS))
<> 128:9bcdf88f62b0 262
<> 128:9bcdf88f62b0 263 #define MXC_F_IOMAN_I2CS_MAPPING_POS 0
<> 128:9bcdf88f62b0 264 #define MXC_F_IOMAN_I2CS_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_MAPPING_POS))
<> 128:9bcdf88f62b0 265 #define MXC_F_IOMAN_I2CS_CORE_IO_POS 4
<> 128:9bcdf88f62b0 266 #define MXC_F_IOMAN_I2CS_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_CORE_IO_POS))
<> 128:9bcdf88f62b0 267
<> 128:9bcdf88f62b0 268 #define MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS 0
<> 128:9bcdf88f62b0 269 #define MXC_F_IOMAN_LCD_COM_REQ_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS))
<> 128:9bcdf88f62b0 270
<> 128:9bcdf88f62b0 271 #define MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS 0
<> 128:9bcdf88f62b0 272 #define MXC_F_IOMAN_LCD_COM_ACK_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS))
<> 128:9bcdf88f62b0 273
<> 128:9bcdf88f62b0 274 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS 0
<> 128:9bcdf88f62b0 275 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS))
<> 128:9bcdf88f62b0 276 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS 1
<> 128:9bcdf88f62b0 277 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS))
<> 128:9bcdf88f62b0 278 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS 2
<> 128:9bcdf88f62b0 279 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS))
<> 128:9bcdf88f62b0 280 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS 3
<> 128:9bcdf88f62b0 281 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS))
<> 128:9bcdf88f62b0 282 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS 4
<> 128:9bcdf88f62b0 283 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS))
<> 128:9bcdf88f62b0 284 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS 5
<> 128:9bcdf88f62b0 285 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS))
<> 128:9bcdf88f62b0 286 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS 6
<> 128:9bcdf88f62b0 287 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS))
<> 128:9bcdf88f62b0 288 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS 7
<> 128:9bcdf88f62b0 289 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS))
<> 128:9bcdf88f62b0 290 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS 8
<> 128:9bcdf88f62b0 291 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS))
<> 128:9bcdf88f62b0 292 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS 9
<> 128:9bcdf88f62b0 293 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS))
<> 128:9bcdf88f62b0 294 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS 10
<> 128:9bcdf88f62b0 295 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS))
<> 128:9bcdf88f62b0 296 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS 11
<> 128:9bcdf88f62b0 297 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS))
<> 128:9bcdf88f62b0 298 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS 12
<> 128:9bcdf88f62b0 299 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS))
<> 128:9bcdf88f62b0 300 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS 13
<> 128:9bcdf88f62b0 301 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS))
<> 128:9bcdf88f62b0 302 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS 14
<> 128:9bcdf88f62b0 303 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS))
<> 128:9bcdf88f62b0 304 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS 15
<> 128:9bcdf88f62b0 305 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS))
<> 128:9bcdf88f62b0 306 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS 16
<> 128:9bcdf88f62b0 307 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS))
<> 128:9bcdf88f62b0 308 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS 17
<> 128:9bcdf88f62b0 309 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS))
<> 128:9bcdf88f62b0 310 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS 18
<> 128:9bcdf88f62b0 311 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS))
<> 128:9bcdf88f62b0 312 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS 19
<> 128:9bcdf88f62b0 313 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS))
<> 128:9bcdf88f62b0 314 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS 20
<> 128:9bcdf88f62b0 315 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS))
<> 128:9bcdf88f62b0 316 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS 21
<> 128:9bcdf88f62b0 317 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS))
<> 128:9bcdf88f62b0 318 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS 22
<> 128:9bcdf88f62b0 319 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS))
<> 128:9bcdf88f62b0 320 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS 23
<> 128:9bcdf88f62b0 321 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS))
<> 128:9bcdf88f62b0 322 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS 24
<> 128:9bcdf88f62b0 323 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS))
<> 128:9bcdf88f62b0 324 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS 25
<> 128:9bcdf88f62b0 325 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS))
<> 128:9bcdf88f62b0 326 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS 26
<> 128:9bcdf88f62b0 327 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS))
<> 128:9bcdf88f62b0 328 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS 27
<> 128:9bcdf88f62b0 329 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS))
<> 128:9bcdf88f62b0 330 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS 28
<> 128:9bcdf88f62b0 331 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS))
<> 128:9bcdf88f62b0 332 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS 29
<> 128:9bcdf88f62b0 333 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS))
<> 128:9bcdf88f62b0 334 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS 30
<> 128:9bcdf88f62b0 335 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS))
<> 128:9bcdf88f62b0 336 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS 31
<> 128:9bcdf88f62b0 337 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS))
<> 128:9bcdf88f62b0 338
<> 128:9bcdf88f62b0 339 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS 0
<> 128:9bcdf88f62b0 340 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS))
<> 128:9bcdf88f62b0 341 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS 1
<> 128:9bcdf88f62b0 342 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS))
<> 128:9bcdf88f62b0 343 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS 2
<> 128:9bcdf88f62b0 344 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS))
<> 128:9bcdf88f62b0 345 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS 3
<> 128:9bcdf88f62b0 346 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS))
<> 128:9bcdf88f62b0 347 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS 4
<> 128:9bcdf88f62b0 348 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS))
<> 128:9bcdf88f62b0 349 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS 5
<> 128:9bcdf88f62b0 350 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS))
<> 128:9bcdf88f62b0 351 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS 6
<> 128:9bcdf88f62b0 352 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS))
<> 128:9bcdf88f62b0 353 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS 7
<> 128:9bcdf88f62b0 354 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS))
<> 128:9bcdf88f62b0 355
<> 128:9bcdf88f62b0 356 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS 0
<> 128:9bcdf88f62b0 357 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS))
<> 128:9bcdf88f62b0 358 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS 1
<> 128:9bcdf88f62b0 359 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS))
<> 128:9bcdf88f62b0 360 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS 2
<> 128:9bcdf88f62b0 361 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS))
<> 128:9bcdf88f62b0 362 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS 3
<> 128:9bcdf88f62b0 363 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS))
<> 128:9bcdf88f62b0 364 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS 4
<> 128:9bcdf88f62b0 365 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS))
<> 128:9bcdf88f62b0 366 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS 5
<> 128:9bcdf88f62b0 367 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS))
<> 128:9bcdf88f62b0 368 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS 6
<> 128:9bcdf88f62b0 369 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS))
<> 128:9bcdf88f62b0 370 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS 7
<> 128:9bcdf88f62b0 371 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS))
<> 128:9bcdf88f62b0 372 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS 8
<> 128:9bcdf88f62b0 373 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS))
<> 128:9bcdf88f62b0 374 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS 9
<> 128:9bcdf88f62b0 375 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS))
<> 128:9bcdf88f62b0 376 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS 10
<> 128:9bcdf88f62b0 377 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS))
<> 128:9bcdf88f62b0 378 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS 11
<> 128:9bcdf88f62b0 379 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS))
<> 128:9bcdf88f62b0 380 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS 12
<> 128:9bcdf88f62b0 381 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS))
<> 128:9bcdf88f62b0 382 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS 13
<> 128:9bcdf88f62b0 383 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS))
<> 128:9bcdf88f62b0 384 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS 14
<> 128:9bcdf88f62b0 385 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS))
<> 128:9bcdf88f62b0 386 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS 15
<> 128:9bcdf88f62b0 387 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS))
<> 128:9bcdf88f62b0 388 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS 16
<> 128:9bcdf88f62b0 389 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS))
<> 128:9bcdf88f62b0 390 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS 17
<> 128:9bcdf88f62b0 391 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS))
<> 128:9bcdf88f62b0 392 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS 18
<> 128:9bcdf88f62b0 393 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS))
<> 128:9bcdf88f62b0 394 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS 19
<> 128:9bcdf88f62b0 395 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS))
<> 128:9bcdf88f62b0 396 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS 20
<> 128:9bcdf88f62b0 397 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS))
<> 128:9bcdf88f62b0 398 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS 21
<> 128:9bcdf88f62b0 399 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS))
<> 128:9bcdf88f62b0 400 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS 22
<> 128:9bcdf88f62b0 401 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS))
<> 128:9bcdf88f62b0 402 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS 23
<> 128:9bcdf88f62b0 403 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS))
<> 128:9bcdf88f62b0 404 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS 24
<> 128:9bcdf88f62b0 405 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS))
<> 128:9bcdf88f62b0 406 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS 25
<> 128:9bcdf88f62b0 407 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS))
<> 128:9bcdf88f62b0 408 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS 26
<> 128:9bcdf88f62b0 409 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS))
<> 128:9bcdf88f62b0 410 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS 27
<> 128:9bcdf88f62b0 411 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS))
<> 128:9bcdf88f62b0 412 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS 28
<> 128:9bcdf88f62b0 413 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS))
<> 128:9bcdf88f62b0 414 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS 29
<> 128:9bcdf88f62b0 415 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS))
<> 128:9bcdf88f62b0 416 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS 30
<> 128:9bcdf88f62b0 417 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS))
<> 128:9bcdf88f62b0 418 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS 31
<> 128:9bcdf88f62b0 419 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS))
<> 128:9bcdf88f62b0 420
<> 128:9bcdf88f62b0 421 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS 0
<> 128:9bcdf88f62b0 422 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS))
<> 128:9bcdf88f62b0 423 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS 1
<> 128:9bcdf88f62b0 424 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS))
<> 128:9bcdf88f62b0 425 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS 2
<> 128:9bcdf88f62b0 426 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS))
<> 128:9bcdf88f62b0 427 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS 3
<> 128:9bcdf88f62b0 428 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS))
<> 128:9bcdf88f62b0 429 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS 4
<> 128:9bcdf88f62b0 430 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS))
<> 128:9bcdf88f62b0 431 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS 5
<> 128:9bcdf88f62b0 432 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS))
<> 128:9bcdf88f62b0 433 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS 6
<> 128:9bcdf88f62b0 434 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS))
<> 128:9bcdf88f62b0 435 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS 7
<> 128:9bcdf88f62b0 436 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS))
<> 128:9bcdf88f62b0 437
<> 128:9bcdf88f62b0 438 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS 0
<> 128:9bcdf88f62b0 439 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS))
<> 128:9bcdf88f62b0 440 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS 1
<> 128:9bcdf88f62b0 441 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS))
<> 128:9bcdf88f62b0 442 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS 2
<> 128:9bcdf88f62b0 443 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS))
<> 128:9bcdf88f62b0 444 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS 3
<> 128:9bcdf88f62b0 445 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS))
<> 128:9bcdf88f62b0 446 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS 4
<> 128:9bcdf88f62b0 447 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS))
<> 128:9bcdf88f62b0 448 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS 5
<> 128:9bcdf88f62b0 449 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS))
<> 128:9bcdf88f62b0 450 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS 6
<> 128:9bcdf88f62b0 451 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS))
<> 128:9bcdf88f62b0 452 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS 7
<> 128:9bcdf88f62b0 453 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS))
<> 128:9bcdf88f62b0 454
<> 128:9bcdf88f62b0 455 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS 0
<> 128:9bcdf88f62b0 456 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS))
<> 128:9bcdf88f62b0 457 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS 1
<> 128:9bcdf88f62b0 458 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS))
<> 128:9bcdf88f62b0 459 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS 2
<> 128:9bcdf88f62b0 460 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS))
<> 128:9bcdf88f62b0 461 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS 3
<> 128:9bcdf88f62b0 462 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS))
<> 128:9bcdf88f62b0 463 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS 4
<> 128:9bcdf88f62b0 464 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS))
<> 128:9bcdf88f62b0 465 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS 5
<> 128:9bcdf88f62b0 466 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS))
<> 128:9bcdf88f62b0 467 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS 6
<> 128:9bcdf88f62b0 468 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS))
<> 128:9bcdf88f62b0 469 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS 7
<> 128:9bcdf88f62b0 470 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS))
<> 128:9bcdf88f62b0 471
<> 128:9bcdf88f62b0 472 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS 0
<> 128:9bcdf88f62b0 473 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS))
<> 128:9bcdf88f62b0 474 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS 4
<> 128:9bcdf88f62b0 475 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS))
<> 128:9bcdf88f62b0 476 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS 8
<> 128:9bcdf88f62b0 477 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS))
<> 128:9bcdf88f62b0 478 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS 12
<> 128:9bcdf88f62b0 479 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS))
<> 128:9bcdf88f62b0 480 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS 16
<> 128:9bcdf88f62b0 481 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS))
<> 128:9bcdf88f62b0 482 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS 20
<> 128:9bcdf88f62b0 483 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS))
<> 128:9bcdf88f62b0 484 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS 24
<> 128:9bcdf88f62b0 485 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS))
<> 128:9bcdf88f62b0 486 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS 28
<> 128:9bcdf88f62b0 487 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS))
<> 128:9bcdf88f62b0 488
<> 128:9bcdf88f62b0 489 #define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS 0
<> 128:9bcdf88f62b0 490 #define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS))
<> 128:9bcdf88f62b0 491 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS 4
<> 128:9bcdf88f62b0 492 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS))
<> 128:9bcdf88f62b0 493 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS 6
<> 128:9bcdf88f62b0 494 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS))
<> 128:9bcdf88f62b0 495 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS 8
<> 128:9bcdf88f62b0 496 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS))
<> 128:9bcdf88f62b0 497 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS 10
<> 128:9bcdf88f62b0 498 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS))
<> 128:9bcdf88f62b0 499
<> 128:9bcdf88f62b0 500 #ifdef __cplusplus
<> 128:9bcdf88f62b0 501 }
<> 128:9bcdf88f62b0 502 #endif
<> 128:9bcdf88f62b0 503
<> 128:9bcdf88f62b0 504 /**
<> 128:9bcdf88f62b0 505 * @}
<> 128:9bcdf88f62b0 506 */
<> 128:9bcdf88f62b0 507
<> 128:9bcdf88f62b0 508 #endif /* _MXC_IOMAN_REGS_H_ */