cc y / mbed

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of mbed by mbed official

TARGET_EFM32WG_STK3800/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_vcmp.h@128:9bcdf88f62b0, 2016-10-27 (annotated)

Committer:
<>
Date:
Thu Oct 27 16:45:56 2016 +0100
Revision:
128:9bcdf88f62b0
Release 128 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



2966: Add kw24 support https://github.com/ARMmbed/mbed-os/pull/2966

3068: MultiTech mDot - clean up PeripheralPins.c and add new pin names https://github.com/ARMmbed/mbed-os/pull/3068

3089: Kinetis HAL: Remove clock initialization code from serial and ticker  https://github.com/ARMmbed/mbed-os/pull/3089

2943: [NRF5] NVIC_SetVector functionality https://github.com/ARMmbed/mbed-os/pull/2943

2938: InterruptIn changes in NCS36510 HAL. https://github.com/ARMmbed/mbed-os/pull/2938

3108: Fix sleep function for NRF52. https://github.com/ARMmbed/mbed-os/pull/3108

3076: STM32F1: Correct timer master value reading https://github.com/ARMmbed/mbed-os/pull/3076

3085: Add LOWPOWERTIMER capability for NUCLEO_F303ZE https://github.com/ARMmbed/mbed-os/pull/3085

3046: [BEETLE] Update BLE stack on Beetle board https://github.com/ARMmbed/mbed-os/pull/3046

3122: [Silicon Labs] Update of Silicon Labs HAL https://github.com/ARMmbed/mbed-os/pull/3122

3022: OnSemi RAM usage fix https://github.com/ARMmbed/mbed-os/pull/3022

3121: STM32F3: Correct UART4 and UART5 defines when using DEVICE_SERIAL_ASYNCH https://github.com/ARMmbed/mbed-os/pull/3121

3142: Targets- NUMAKER_PFM_NUC47216 remove mbed 2 https://github.com/ARMmbed/mbed-os/pull/3142

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**************************************************************************//**
<> 128:9bcdf88f62b0 2 * @file efm32wg_vcmp.h
<> 128:9bcdf88f62b0 3 * @brief EFM32WG_VCMP register and bit field definitions
<> 128:9bcdf88f62b0 4 * @version 5.0.0
<> 128:9bcdf88f62b0 5 ******************************************************************************
<> 128:9bcdf88f62b0 6 * @section License
<> 128:9bcdf88f62b0 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 *
<> 128:9bcdf88f62b0 10 * Permission is granted to anyone to use this software for any purpose,
<> 128:9bcdf88f62b0 11 * including commercial applications, and to alter it and redistribute it
<> 128:9bcdf88f62b0 12 * freely, subject to the following restrictions:
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 * 1. The origin of this software must not be misrepresented; you must not
<> 128:9bcdf88f62b0 15 * claim that you wrote the original software.@n
<> 128:9bcdf88f62b0 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 128:9bcdf88f62b0 17 * misrepresented as being the original software.@n
<> 128:9bcdf88f62b0 18 * 3. This notice may not be removed or altered from any source distribution.
<> 128:9bcdf88f62b0 19 *
<> 128:9bcdf88f62b0 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 128:9bcdf88f62b0 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 128:9bcdf88f62b0 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 128:9bcdf88f62b0 23 * kind, including, but not limited to, any implied warranties of
<> 128:9bcdf88f62b0 24 * merchantability or fitness for any particular purpose or warranties against
<> 128:9bcdf88f62b0 25 * infringement of any proprietary rights of a third party.
<> 128:9bcdf88f62b0 26 *
<> 128:9bcdf88f62b0 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 128:9bcdf88f62b0 28 * incidental, or special damages, or any other relief, or for any claim by
<> 128:9bcdf88f62b0 29 * any third party, arising from your use of this Software.
<> 128:9bcdf88f62b0 30 *
<> 128:9bcdf88f62b0 31 *****************************************************************************/
<> 128:9bcdf88f62b0 32 /**************************************************************************//**
<> 128:9bcdf88f62b0 33 * @addtogroup Parts
<> 128:9bcdf88f62b0 34 * @{
<> 128:9bcdf88f62b0 35 ******************************************************************************/
<> 128:9bcdf88f62b0 36 /**************************************************************************//**
<> 128:9bcdf88f62b0 37 * @defgroup EFM32WG_VCMP
<> 128:9bcdf88f62b0 38 * @{
<> 128:9bcdf88f62b0 39 * @brief EFM32WG_VCMP Register Declaration
<> 128:9bcdf88f62b0 40 *****************************************************************************/
<> 128:9bcdf88f62b0 41 typedef struct
<> 128:9bcdf88f62b0 42 {
<> 128:9bcdf88f62b0 43 __IOM uint32_t CTRL; /**< Control Register */
<> 128:9bcdf88f62b0 44 __IOM uint32_t INPUTSEL; /**< Input Selection Register */
<> 128:9bcdf88f62b0 45 __IM uint32_t STATUS; /**< Status Register */
<> 128:9bcdf88f62b0 46 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 128:9bcdf88f62b0 47 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 128:9bcdf88f62b0 48 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 128:9bcdf88f62b0 49 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 128:9bcdf88f62b0 50 } VCMP_TypeDef; /** @} */
<> 128:9bcdf88f62b0 51
<> 128:9bcdf88f62b0 52 /**************************************************************************//**
<> 128:9bcdf88f62b0 53 * @defgroup EFM32WG_VCMP_BitFields
<> 128:9bcdf88f62b0 54 * @{
<> 128:9bcdf88f62b0 55 *****************************************************************************/
<> 128:9bcdf88f62b0 56
<> 128:9bcdf88f62b0 57 /* Bit fields for VCMP CTRL */
<> 128:9bcdf88f62b0 58 #define _VCMP_CTRL_RESETVALUE 0x47000000UL /**< Default value for VCMP_CTRL */
<> 128:9bcdf88f62b0 59 #define _VCMP_CTRL_MASK 0x4F030715UL /**< Mask for VCMP_CTRL */
<> 128:9bcdf88f62b0 60 #define VCMP_CTRL_EN (0x1UL << 0) /**< Voltage Supply Comparator Enable */
<> 128:9bcdf88f62b0 61 #define _VCMP_CTRL_EN_SHIFT 0 /**< Shift value for VCMP_EN */
<> 128:9bcdf88f62b0 62 #define _VCMP_CTRL_EN_MASK 0x1UL /**< Bit mask for VCMP_EN */
<> 128:9bcdf88f62b0 63 #define _VCMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
<> 128:9bcdf88f62b0 64 #define VCMP_CTRL_EN_DEFAULT (_VCMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 128:9bcdf88f62b0 65 #define VCMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */
<> 128:9bcdf88f62b0 66 #define _VCMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for VCMP_INACTVAL */
<> 128:9bcdf88f62b0 67 #define _VCMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for VCMP_INACTVAL */
<> 128:9bcdf88f62b0 68 #define _VCMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
<> 128:9bcdf88f62b0 69 #define VCMP_CTRL_INACTVAL_DEFAULT (_VCMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 128:9bcdf88f62b0 70 #define VCMP_CTRL_HYSTEN (0x1UL << 4) /**< Hysteresis Enable */
<> 128:9bcdf88f62b0 71 #define _VCMP_CTRL_HYSTEN_SHIFT 4 /**< Shift value for VCMP_HYSTEN */
<> 128:9bcdf88f62b0 72 #define _VCMP_CTRL_HYSTEN_MASK 0x10UL /**< Bit mask for VCMP_HYSTEN */
<> 128:9bcdf88f62b0 73 #define _VCMP_CTRL_HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
<> 128:9bcdf88f62b0 74 #define VCMP_CTRL_HYSTEN_DEFAULT (_VCMP_CTRL_HYSTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 128:9bcdf88f62b0 75 #define _VCMP_CTRL_WARMTIME_SHIFT 8 /**< Shift value for VCMP_WARMTIME */
<> 128:9bcdf88f62b0 76 #define _VCMP_CTRL_WARMTIME_MASK 0x700UL /**< Bit mask for VCMP_WARMTIME */
<> 128:9bcdf88f62b0 77 #define _VCMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
<> 128:9bcdf88f62b0 78 #define _VCMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /**< Mode 4CYCLES for VCMP_CTRL */
<> 128:9bcdf88f62b0 79 #define _VCMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /**< Mode 8CYCLES for VCMP_CTRL */
<> 128:9bcdf88f62b0 80 #define _VCMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /**< Mode 16CYCLES for VCMP_CTRL */
<> 128:9bcdf88f62b0 81 #define _VCMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /**< Mode 32CYCLES for VCMP_CTRL */
<> 128:9bcdf88f62b0 82 #define _VCMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /**< Mode 64CYCLES for VCMP_CTRL */
<> 128:9bcdf88f62b0 83 #define _VCMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /**< Mode 128CYCLES for VCMP_CTRL */
<> 128:9bcdf88f62b0 84 #define _VCMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /**< Mode 256CYCLES for VCMP_CTRL */
<> 128:9bcdf88f62b0 85 #define _VCMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /**< Mode 512CYCLES for VCMP_CTRL */
<> 128:9bcdf88f62b0 86 #define VCMP_CTRL_WARMTIME_DEFAULT (_VCMP_CTRL_WARMTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 128:9bcdf88f62b0 87 #define VCMP_CTRL_WARMTIME_4CYCLES (_VCMP_CTRL_WARMTIME_4CYCLES << 8) /**< Shifted mode 4CYCLES for VCMP_CTRL */
<> 128:9bcdf88f62b0 88 #define VCMP_CTRL_WARMTIME_8CYCLES (_VCMP_CTRL_WARMTIME_8CYCLES << 8) /**< Shifted mode 8CYCLES for VCMP_CTRL */
<> 128:9bcdf88f62b0 89 #define VCMP_CTRL_WARMTIME_16CYCLES (_VCMP_CTRL_WARMTIME_16CYCLES << 8) /**< Shifted mode 16CYCLES for VCMP_CTRL */
<> 128:9bcdf88f62b0 90 #define VCMP_CTRL_WARMTIME_32CYCLES (_VCMP_CTRL_WARMTIME_32CYCLES << 8) /**< Shifted mode 32CYCLES for VCMP_CTRL */
<> 128:9bcdf88f62b0 91 #define VCMP_CTRL_WARMTIME_64CYCLES (_VCMP_CTRL_WARMTIME_64CYCLES << 8) /**< Shifted mode 64CYCLES for VCMP_CTRL */
<> 128:9bcdf88f62b0 92 #define VCMP_CTRL_WARMTIME_128CYCLES (_VCMP_CTRL_WARMTIME_128CYCLES << 8) /**< Shifted mode 128CYCLES for VCMP_CTRL */
<> 128:9bcdf88f62b0 93 #define VCMP_CTRL_WARMTIME_256CYCLES (_VCMP_CTRL_WARMTIME_256CYCLES << 8) /**< Shifted mode 256CYCLES for VCMP_CTRL */
<> 128:9bcdf88f62b0 94 #define VCMP_CTRL_WARMTIME_512CYCLES (_VCMP_CTRL_WARMTIME_512CYCLES << 8) /**< Shifted mode 512CYCLES for VCMP_CTRL */
<> 128:9bcdf88f62b0 95 #define VCMP_CTRL_IRISE (0x1UL << 16) /**< Rising Edge Interrupt Sense */
<> 128:9bcdf88f62b0 96 #define _VCMP_CTRL_IRISE_SHIFT 16 /**< Shift value for VCMP_IRISE */
<> 128:9bcdf88f62b0 97 #define _VCMP_CTRL_IRISE_MASK 0x10000UL /**< Bit mask for VCMP_IRISE */
<> 128:9bcdf88f62b0 98 #define _VCMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
<> 128:9bcdf88f62b0 99 #define VCMP_CTRL_IRISE_DEFAULT (_VCMP_CTRL_IRISE_DEFAULT << 16) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 128:9bcdf88f62b0 100 #define VCMP_CTRL_IFALL (0x1UL << 17) /**< Falling Edge Interrupt Sense */
<> 128:9bcdf88f62b0 101 #define _VCMP_CTRL_IFALL_SHIFT 17 /**< Shift value for VCMP_IFALL */
<> 128:9bcdf88f62b0 102 #define _VCMP_CTRL_IFALL_MASK 0x20000UL /**< Bit mask for VCMP_IFALL */
<> 128:9bcdf88f62b0 103 #define _VCMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
<> 128:9bcdf88f62b0 104 #define VCMP_CTRL_IFALL_DEFAULT (_VCMP_CTRL_IFALL_DEFAULT << 17) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 128:9bcdf88f62b0 105 #define _VCMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for VCMP_BIASPROG */
<> 128:9bcdf88f62b0 106 #define _VCMP_CTRL_BIASPROG_MASK 0xF000000UL /**< Bit mask for VCMP_BIASPROG */
<> 128:9bcdf88f62b0 107 #define _VCMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for VCMP_CTRL */
<> 128:9bcdf88f62b0 108 #define VCMP_CTRL_BIASPROG_DEFAULT (_VCMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 128:9bcdf88f62b0 109 #define VCMP_CTRL_HALFBIAS (0x1UL << 30) /**< Half Bias Current */
<> 128:9bcdf88f62b0 110 #define _VCMP_CTRL_HALFBIAS_SHIFT 30 /**< Shift value for VCMP_HALFBIAS */
<> 128:9bcdf88f62b0 111 #define _VCMP_CTRL_HALFBIAS_MASK 0x40000000UL /**< Bit mask for VCMP_HALFBIAS */
<> 128:9bcdf88f62b0 112 #define _VCMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for VCMP_CTRL */
<> 128:9bcdf88f62b0 113 #define VCMP_CTRL_HALFBIAS_DEFAULT (_VCMP_CTRL_HALFBIAS_DEFAULT << 30) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 128:9bcdf88f62b0 114
<> 128:9bcdf88f62b0 115 /* Bit fields for VCMP INPUTSEL */
<> 128:9bcdf88f62b0 116 #define _VCMP_INPUTSEL_RESETVALUE 0x00000000UL /**< Default value for VCMP_INPUTSEL */
<> 128:9bcdf88f62b0 117 #define _VCMP_INPUTSEL_MASK 0x0000013FUL /**< Mask for VCMP_INPUTSEL */
<> 128:9bcdf88f62b0 118 #define _VCMP_INPUTSEL_TRIGLEVEL_SHIFT 0 /**< Shift value for VCMP_TRIGLEVEL */
<> 128:9bcdf88f62b0 119 #define _VCMP_INPUTSEL_TRIGLEVEL_MASK 0x3FUL /**< Bit mask for VCMP_TRIGLEVEL */
<> 128:9bcdf88f62b0 120 #define _VCMP_INPUTSEL_TRIGLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_INPUTSEL */
<> 128:9bcdf88f62b0 121 #define VCMP_INPUTSEL_TRIGLEVEL_DEFAULT (_VCMP_INPUTSEL_TRIGLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_INPUTSEL */
<> 128:9bcdf88f62b0 122 #define VCMP_INPUTSEL_LPREF (0x1UL << 8) /**< Low Power Reference */
<> 128:9bcdf88f62b0 123 #define _VCMP_INPUTSEL_LPREF_SHIFT 8 /**< Shift value for VCMP_LPREF */
<> 128:9bcdf88f62b0 124 #define _VCMP_INPUTSEL_LPREF_MASK 0x100UL /**< Bit mask for VCMP_LPREF */
<> 128:9bcdf88f62b0 125 #define _VCMP_INPUTSEL_LPREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_INPUTSEL */
<> 128:9bcdf88f62b0 126 #define VCMP_INPUTSEL_LPREF_DEFAULT (_VCMP_INPUTSEL_LPREF_DEFAULT << 8) /**< Shifted mode DEFAULT for VCMP_INPUTSEL */
<> 128:9bcdf88f62b0 127
<> 128:9bcdf88f62b0 128 /* Bit fields for VCMP STATUS */
<> 128:9bcdf88f62b0 129 #define _VCMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for VCMP_STATUS */
<> 128:9bcdf88f62b0 130 #define _VCMP_STATUS_MASK 0x00000003UL /**< Mask for VCMP_STATUS */
<> 128:9bcdf88f62b0 131 #define VCMP_STATUS_VCMPACT (0x1UL << 0) /**< Voltage Supply Comparator Active */
<> 128:9bcdf88f62b0 132 #define _VCMP_STATUS_VCMPACT_SHIFT 0 /**< Shift value for VCMP_VCMPACT */
<> 128:9bcdf88f62b0 133 #define _VCMP_STATUS_VCMPACT_MASK 0x1UL /**< Bit mask for VCMP_VCMPACT */
<> 128:9bcdf88f62b0 134 #define _VCMP_STATUS_VCMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_STATUS */
<> 128:9bcdf88f62b0 135 #define VCMP_STATUS_VCMPACT_DEFAULT (_VCMP_STATUS_VCMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_STATUS */
<> 128:9bcdf88f62b0 136 #define VCMP_STATUS_VCMPOUT (0x1UL << 1) /**< Voltage Supply Comparator Output */
<> 128:9bcdf88f62b0 137 #define _VCMP_STATUS_VCMPOUT_SHIFT 1 /**< Shift value for VCMP_VCMPOUT */
<> 128:9bcdf88f62b0 138 #define _VCMP_STATUS_VCMPOUT_MASK 0x2UL /**< Bit mask for VCMP_VCMPOUT */
<> 128:9bcdf88f62b0 139 #define _VCMP_STATUS_VCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_STATUS */
<> 128:9bcdf88f62b0 140 #define VCMP_STATUS_VCMPOUT_DEFAULT (_VCMP_STATUS_VCMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_STATUS */
<> 128:9bcdf88f62b0 141
<> 128:9bcdf88f62b0 142 /* Bit fields for VCMP IEN */
<> 128:9bcdf88f62b0 143 #define _VCMP_IEN_RESETVALUE 0x00000000UL /**< Default value for VCMP_IEN */
<> 128:9bcdf88f62b0 144 #define _VCMP_IEN_MASK 0x00000003UL /**< Mask for VCMP_IEN */
<> 128:9bcdf88f62b0 145 #define VCMP_IEN_EDGE (0x1UL << 0) /**< Edge Trigger Interrupt Enable */
<> 128:9bcdf88f62b0 146 #define _VCMP_IEN_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
<> 128:9bcdf88f62b0 147 #define _VCMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
<> 128:9bcdf88f62b0 148 #define _VCMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IEN */
<> 128:9bcdf88f62b0 149 #define VCMP_IEN_EDGE_DEFAULT (_VCMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IEN */
<> 128:9bcdf88f62b0 150 #define VCMP_IEN_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Enable */
<> 128:9bcdf88f62b0 151 #define _VCMP_IEN_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
<> 128:9bcdf88f62b0 152 #define _VCMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
<> 128:9bcdf88f62b0 153 #define _VCMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IEN */
<> 128:9bcdf88f62b0 154 #define VCMP_IEN_WARMUP_DEFAULT (_VCMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IEN */
<> 128:9bcdf88f62b0 155
<> 128:9bcdf88f62b0 156 /* Bit fields for VCMP IF */
<> 128:9bcdf88f62b0 157 #define _VCMP_IF_RESETVALUE 0x00000000UL /**< Default value for VCMP_IF */
<> 128:9bcdf88f62b0 158 #define _VCMP_IF_MASK 0x00000003UL /**< Mask for VCMP_IF */
<> 128:9bcdf88f62b0 159 #define VCMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */
<> 128:9bcdf88f62b0 160 #define _VCMP_IF_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
<> 128:9bcdf88f62b0 161 #define _VCMP_IF_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
<> 128:9bcdf88f62b0 162 #define _VCMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IF */
<> 128:9bcdf88f62b0 163 #define VCMP_IF_EDGE_DEFAULT (_VCMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IF */
<> 128:9bcdf88f62b0 164 #define VCMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */
<> 128:9bcdf88f62b0 165 #define _VCMP_IF_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
<> 128:9bcdf88f62b0 166 #define _VCMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
<> 128:9bcdf88f62b0 167 #define _VCMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IF */
<> 128:9bcdf88f62b0 168 #define VCMP_IF_WARMUP_DEFAULT (_VCMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IF */
<> 128:9bcdf88f62b0 169
<> 128:9bcdf88f62b0 170 /* Bit fields for VCMP IFS */
<> 128:9bcdf88f62b0 171 #define _VCMP_IFS_RESETVALUE 0x00000000UL /**< Default value for VCMP_IFS */
<> 128:9bcdf88f62b0 172 #define _VCMP_IFS_MASK 0x00000003UL /**< Mask for VCMP_IFS */
<> 128:9bcdf88f62b0 173 #define VCMP_IFS_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Set */
<> 128:9bcdf88f62b0 174 #define _VCMP_IFS_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
<> 128:9bcdf88f62b0 175 #define _VCMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
<> 128:9bcdf88f62b0 176 #define _VCMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFS */
<> 128:9bcdf88f62b0 177 #define VCMP_IFS_EDGE_DEFAULT (_VCMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IFS */
<> 128:9bcdf88f62b0 178 #define VCMP_IFS_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Set */
<> 128:9bcdf88f62b0 179 #define _VCMP_IFS_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
<> 128:9bcdf88f62b0 180 #define _VCMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
<> 128:9bcdf88f62b0 181 #define _VCMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFS */
<> 128:9bcdf88f62b0 182 #define VCMP_IFS_WARMUP_DEFAULT (_VCMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFS */
<> 128:9bcdf88f62b0 183
<> 128:9bcdf88f62b0 184 /* Bit fields for VCMP IFC */
<> 128:9bcdf88f62b0 185 #define _VCMP_IFC_RESETVALUE 0x00000000UL /**< Default value for VCMP_IFC */
<> 128:9bcdf88f62b0 186 #define _VCMP_IFC_MASK 0x00000003UL /**< Mask for VCMP_IFC */
<> 128:9bcdf88f62b0 187 #define VCMP_IFC_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Clear */
<> 128:9bcdf88f62b0 188 #define _VCMP_IFC_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
<> 128:9bcdf88f62b0 189 #define _VCMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
<> 128:9bcdf88f62b0 190 #define _VCMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFC */
<> 128:9bcdf88f62b0 191 #define VCMP_IFC_EDGE_DEFAULT (_VCMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IFC */
<> 128:9bcdf88f62b0 192 #define VCMP_IFC_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Clear */
<> 128:9bcdf88f62b0 193 #define _VCMP_IFC_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
<> 128:9bcdf88f62b0 194 #define _VCMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
<> 128:9bcdf88f62b0 195 #define _VCMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFC */
<> 128:9bcdf88f62b0 196 #define VCMP_IFC_WARMUP_DEFAULT (_VCMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFC */
<> 128:9bcdf88f62b0 197
<> 128:9bcdf88f62b0 198 /** @} End of group EFM32WG_VCMP */
<> 128:9bcdf88f62b0 199 /** @} End of group Parts */
<> 128:9bcdf88f62b0 200